repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
mitchsm/nvc
|
test/lower/loop1.vhd
| 4 | 405 |
entity loop1 is
end entity;
architecture test of loop1 is
begin
process is
variable a, b : integer;
begin
loop
exit when a = 10;
a := a + 1;
end loop;
loop
a := a + 1;
next when (a mod 2) = 0;
b := b + 1;
exit when b = 10;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
6c725f0583a4a5a4394175659f9521e8
| 0.441975 | 3.970588 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_t_e-rtl-a.vhd
| 1 | 3,185 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:13 wig Exp $
-- $Date: 2004/04/06 10:50:13 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:13 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_b_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_c_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_d_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_e_e
cgs_ramclk : out std_ulogic;
p_mix_nreset_go : out std_ulogic;
si_vclkx2 : in std_ulogic;
tmu_dac_reset : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
;
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
;
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: inst_c_e
;
-- End of Generated Instance Port Map for inst_c
-- Generated Instance Port Map for inst_d
inst_d: inst_d_e
;
-- End of Generated Instance Port Map for inst_d
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
cgs_ramclk => cgs_ramclk, -- ClockSignalsESDRAMInterface
p_mix_nreset_go => nreset, -- GlobalRESET(Verilogmacro)
si_vclkx2 => si_vclkx2, -- DigitalVideoPort
tmu_dac_reset => tmu_dac_reset, -- CADCTestModeRGBADAC
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
03c039a363bc0a9b0410d2cb63a79c72
| 0.609419 | 3.266667 | false | false | false | false |
blutsvente/MIX
|
test/results/padio2/pad_tb-struct-a.vhd
| 1 | 4,904 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pad_tb
--
-- Generated
-- by: wig
-- on: Wed Jul 5 17:16:56 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_tb-struct-a.vhd,v 1.5 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: pad_tb-struct-a.vhd,v $
-- Revision 1.5 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of pad_tb
--
architecture struct of pad_tb is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component padframe
-- No Generated Generics
port (
-- Generated Port for Entity padframe
db2o_0 : inout std_ulogic; -- Flat Panel
db2o_1 : inout std_ulogic; -- Flat Panel
db2o_10 : inout std_ulogic; -- Flat Panel
db2o_11 : inout std_ulogic; -- Flat Panel
db2o_12 : inout std_ulogic; -- Flat Panel
db2o_13 : inout std_ulogic; -- Flat Panel
db2o_14 : inout std_ulogic; -- Flat Panel
db2o_15 : inout std_ulogic; -- Flat Panel
db2o_2 : inout std_ulogic; -- Flat Panel
db2o_3 : inout std_ulogic; -- Flat Panel
db2o_4 : inout std_ulogic; -- Flat Panel
db2o_5 : inout std_ulogic; -- Flat Panel
db2o_6 : inout std_ulogic; -- Flat Panel
db2o_7 : inout std_ulogic; -- Flat Panel
db2o_8 : inout std_ulogic; -- Flat Panel
db2o_9 : inout std_ulogic; -- Flat Panel
db2o_i : in std_ulogic_vector(15 downto 0); -- padin
db2o_o : out std_ulogic_vector(15 downto 0); -- padout
dbo_0 : inout std_ulogic; -- Flat Panel
dbo_1 : inout std_ulogic; -- Flat Panel
dbo_10 : inout std_ulogic; -- Flat Panel
dbo_11 : inout std_ulogic; -- Flat Panel
dbo_12 : inout std_ulogic; -- Flat Panel
dbo_13 : inout std_ulogic; -- Flat Panel
dbo_14 : inout std_ulogic; -- Flat Panel
dbo_15 : inout std_ulogic; -- Flat Panel
dbo_2 : inout std_ulogic; -- Flat Panel
dbo_3 : inout std_ulogic; -- Flat Panel
dbo_4 : inout std_ulogic; -- Flat Panel
dbo_5 : inout std_ulogic; -- Flat Panel
dbo_6 : inout std_ulogic; -- Flat Panel
dbo_7 : inout std_ulogic; -- Flat Panel
dbo_8 : inout std_ulogic; -- Flat Panel
dbo_9 : inout std_ulogic; -- Flat Panel
dbo_i : in std_ulogic_vector(15 downto 0); -- padin
dbo_o : out std_ulogic_vector(15 downto 0) -- padout
-- End of Generated Port for Entity padframe
);
end component;
-- ---------
--
-- Generated Signal List
--
signal db2o_i : std_ulogic_vector(15 downto 0);
-- __I_OUT_OPEN signal db2o_o : std_ulogic_vector(15 downto 0);
signal dbo_i : std_ulogic_vector(15 downto 0);
-- __I_OUT_OPEN signal dbo_o : std_ulogic_vector(15 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for i_padframe
i_padframe: padframe
port map (
db2o_0 => db2o_0, -- Flat Panel
db2o_1 => db2o_1, -- Flat Panel
db2o_10 => db2o_10, -- Flat Panel
db2o_11 => db2o_11, -- Flat Panel
db2o_12 => db2o_12, -- Flat Panel
db2o_13 => db2o_13, -- Flat Panel
db2o_14 => db2o_14, -- Flat Panel
db2o_15 => db2o_15, -- Flat Panel
db2o_2 => db2o_2, -- Flat Panel
db2o_3 => db2o_3, -- Flat Panel
db2o_4 => db2o_4, -- Flat Panel
db2o_5 => db2o_5, -- Flat Panel
db2o_6 => db2o_6, -- Flat Panel
db2o_7 => db2o_7, -- Flat Panel
db2o_8 => db2o_8, -- Flat Panel
db2o_9 => db2o_9, -- Flat Panel
db2o_i => db2o_i, -- padin (X2)
db2o_o => open, -- padout (X2) -- __I_OUT_OPEN
dbo_0 => dbo_0, -- Flat Panel
dbo_1 => dbo_1, -- Flat Panel
dbo_10 => dbo_10, -- Flat Panel
dbo_11 => dbo_11, -- Flat Panel
dbo_12 => dbo_12, -- Flat Panel
dbo_13 => dbo_13, -- Flat Panel
dbo_14 => dbo_14, -- Flat Panel
dbo_15 => dbo_15, -- Flat Panel
dbo_2 => dbo_2, -- Flat Panel
dbo_3 => dbo_3, -- Flat Panel
dbo_4 => dbo_4, -- Flat Panel
dbo_5 => dbo_5, -- Flat Panel
dbo_6 => dbo_6, -- Flat Panel
dbo_7 => dbo_7, -- Flat Panel
dbo_8 => dbo_8, -- Flat Panel
dbo_9 => dbo_9, -- Flat Panel
dbo_i => dbo_i, -- padin (X2)
dbo_o => open -- padout -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for i_padframe
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
2b960e1d79c875d9e82bae34c7b0730a
| 0.590946 | 2.629491 | false | false | false | false |
mitchsm/nvc
|
test/elab/open2.vhd
| 5 | 942 |
entity sub2 is
generic (
WIDTH : integer );
port (
x : in bit_vector(WIDTH - 1 downto 0);
y : out bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub2 is
begin
gen: for i in 0 to WIDTH - 1 generate
y(i) <= not x(i);
end generate;
end architecture;
-------------------------------------------------------------------------------
entity sub1 is
port (
x : in bit;
y : out bit );
end entity;
architecture test of sub1 is
begin
sub2_i: entity work.sub2
generic map (
WIDTH => 1 )
port map (
x(0) => x,
y(0) => y );
end architecture;
-------------------------------------------------------------------------------
entity elab22 is
end entity;
architecture test of elab22 is
signal a, b : bit;
begin
sub1_i: entity work.sub1
port map (
x => a );
end architecture;
|
gpl-3.0
|
9586c7673be82e08cadf4c5c2fe38a9e
| 0.446921 | 4.095652 | false | true | false | false |
mitchsm/nvc
|
test/regress/wait5.vhd
| 5 | 474 |
entity wait5 is
end entity;
architecture test of wait5 is
signal x, y : integer := 0;
begin
a: process (x) is
begin
y <= y + 1;
end process;
b: process is
begin
wait for 1 ns;
assert y = 1;
x <= 1;
wait for 1 ns;
x <= 0;
wait for 1 ns;
assert y = 3;
x <= 0;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
5cbee75aecb5ca6c7cb9a5df0f192ed5
| 0.445148 | 3.761905 | false | false | false | false |
blutsvente/MIX
|
test/results/autoopen/aaa/inst_aa_e-rtl-a.vhd
| 1 | 4,915 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_aa_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-rtl-a.vhd,v 1.1 2004/04/06 11:19:54 wig Exp $
-- $Date: 2004/04/06 11:19:54 $
-- $Log: inst_aa_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 11:19:54 wig
-- Adding result/autoopen
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Revision: 1.28 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_aa_e
--
architecture rtl of inst_aa_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aaa_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_aaa_e
s_ai14 : out std_ulogic_vector(7 downto 0);
s_ai16 : in std_ulogic_vector(7 downto 0);
s_ai6 : out std_ulogic;
s_ai8 : in std_ulogic;
s_aio17 : inout std_ulogic;
s_aio18 : inout std_ulogic;
s_aio19 : inout std_ulogic;
s_ao1 : out std_ulogic;
s_ao10 : out std_ulogic_vector(7 downto 0);
s_ao11 : out std_ulogic_vector(7 downto 0);
s_ao12 : in std_ulogic_vector(7 downto 0);
s_ao13 : in std_ulogic_vector(7 downto 0);
s_ao2 : out std_ulogic;
s_ao3 : out std_ulogic;
s_ao4 : in std_ulogic;
s_ao5 : out std_ulogic;
s_ao9 : out std_ulogic_vector(7 downto 0);
s_intname : out std_ulogic
-- End of Generated Port for Entity inst_aaa_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_ai14 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ai16 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ai6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ai8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_aio17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_aio18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_aio19 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao10 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao11 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao12 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao13 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao9 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_intname : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_s_ai14_go <= s_ai14; -- __I_O_BUS_PORT
s_ai16 <= p_mix_s_ai16_gi; -- __I_I_BUS_PORT
p_mix_s_ai6_go <= s_ai6; -- __I_O_SLICE_PORT -- __I_SINGLE_BIT (0)
s_ai8 <= p_mix_s_ai8_gi; -- __I_I_BIT_PORT
s_aio17 <= p_mix_s_aio17_gc; -- __I_I_BIT_PORT
s_aio18 <= p_mix_s_aio18_gc; -- __I_I_BIT_PORT
s_aio19 <= p_mix_s_aio19_gc; -- __I_I_BIT_PORT
p_mix_s_ao1_go <= s_ao1; -- __I_O_BIT_PORT
p_mix_s_ao10_go <= s_ao10; -- __I_O_BUS_PORT
p_mix_s_ao11_go <= s_ao11; -- __I_O_BUS_PORT
s_ao12 <= p_mix_s_ao12_gi; -- __I_I_BUS_PORT
s_ao13 <= p_mix_s_ao13_gi; -- __I_I_BUS_PORT
p_mix_s_ao2_go <= s_ao2; -- __I_O_BIT_PORT
p_mix_s_ao3_go <= s_ao3; -- __I_O_BIT_PORT
s_ao4 <= p_mix_s_ao4_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
p_mix_s_ao5_go <= s_ao5; -- __I_O_BIT_PORT
p_mix_s_ao9_go <= s_ao9; -- __I_O_BUS_PORT
port_aa <= s_intname; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aaa
inst_aaa: inst_aaa_e
port map (
s_ai14 => s_ai14,
s_ai16 => s_ai16,
s_ai6 => s_ai6,
s_ai8 => s_ai8,
s_aio17 => s_aio17,
s_aio18 => s_aio18,
s_aio19 => s_aio19,
s_ao1 => s_ao1,
s_ao10 => s_ao10,
s_ao11 => s_ao11,
s_ao12 => s_ao12,
s_ao13 => s_ao13,
s_ao2 => s_ao2,
s_ao3 => s_ao3,
s_ao4 => s_ao4,
s_ao5 => s_ao5,
s_ao9 => s_ao9,
s_intname => s_intname
);
-- End of Generated Instance Port Map for inst_aaa
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
a85f6179de15bb48931ce7375da34ea2
| 0.580061 | 2.390564 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue82.vhd
| 5 | 739 |
package nested_pkg is
procedure parent_proc(signal sig : out integer;
var : inout integer);
end package;
package body nested_pkg is
procedure parent_proc(signal sig : out integer; var : inout integer) is
procedure nested_proc is
begin
assert var /= 4;
sig <= var;
var := 4;
end procedure;
begin
nested_proc;
end procedure;
end package body;
entity issue82 is
end entity;
use work.nested_pkg.all;
architecture test of issue82 is
signal s : integer;
begin
process is
variable v : integer := 2;
begin
parent_proc(s, v);
wait for 1 ns;
assert v = 4;
assert s = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
0100aa80dfa17b7039b754bccf5aae53
| 0.600812 | 3.951872 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/parallel_add0.vhd
| 1 | 5,721 |
-- megafunction wizard: %PARALLEL_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: parallel_add
-- ============================================================
-- File Name: parallel_add0.vhd
-- Megafunction Name(s):
-- parallel_add
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY parallel_add0 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END parallel_add0;
ARCHITECTURE SYN OF parallel_add0 IS
-- type ALTERA_MF_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire2 : ALTERA_MF_LOGIC_2D (3 DOWNTO 0, 7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
sub_wire5 <= data0x(7 DOWNTO 0);
sub_wire4 <= data1x(7 DOWNTO 0);
sub_wire3 <= data2x(7 DOWNTO 0);
result <= sub_wire0(9 DOWNTO 0);
sub_wire1 <= data3x(7 DOWNTO 0);
sub_wire2(3, 0) <= sub_wire1(0);
sub_wire2(3, 1) <= sub_wire1(1);
sub_wire2(3, 2) <= sub_wire1(2);
sub_wire2(3, 3) <= sub_wire1(3);
sub_wire2(3, 4) <= sub_wire1(4);
sub_wire2(3, 5) <= sub_wire1(5);
sub_wire2(3, 6) <= sub_wire1(6);
sub_wire2(3, 7) <= sub_wire1(7);
sub_wire2(2, 0) <= sub_wire3(0);
sub_wire2(2, 1) <= sub_wire3(1);
sub_wire2(2, 2) <= sub_wire3(2);
sub_wire2(2, 3) <= sub_wire3(3);
sub_wire2(2, 4) <= sub_wire3(4);
sub_wire2(2, 5) <= sub_wire3(5);
sub_wire2(2, 6) <= sub_wire3(6);
sub_wire2(2, 7) <= sub_wire3(7);
sub_wire2(1, 0) <= sub_wire4(0);
sub_wire2(1, 1) <= sub_wire4(1);
sub_wire2(1, 2) <= sub_wire4(2);
sub_wire2(1, 3) <= sub_wire4(3);
sub_wire2(1, 4) <= sub_wire4(4);
sub_wire2(1, 5) <= sub_wire4(5);
sub_wire2(1, 6) <= sub_wire4(6);
sub_wire2(1, 7) <= sub_wire4(7);
sub_wire2(0, 0) <= sub_wire5(0);
sub_wire2(0, 1) <= sub_wire5(1);
sub_wire2(0, 2) <= sub_wire5(2);
sub_wire2(0, 3) <= sub_wire5(3);
sub_wire2(0, 4) <= sub_wire5(4);
sub_wire2(0, 5) <= sub_wire5(5);
sub_wire2(0, 6) <= sub_wire5(6);
sub_wire2(0, 7) <= sub_wire5(7);
parallel_add_component : parallel_add
GENERIC MAP (
msw_subtract => "NO",
pipeline => 0,
representation => "SIGNED",
result_alignment => "LSB",
shift => 0,
size => 4,
width => 8,
widthr => 10,
lpm_type => "parallel_add"
)
PORT MAP (
data => sub_wire2,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
-- Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
-- Retrieval info: CONSTANT: SHIFT NUMERIC "0"
-- Retrieval info: CONSTANT: SIZE NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHR NUMERIC "10"
-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
-- Retrieval info: USED_PORT: result 0 0 10 0 OUTPUT NODEFVAL "result[9..0]"
-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 10 0 @result 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL parallel_add0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL parallel_add0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL parallel_add0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL parallel_add0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL parallel_add0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
8b5de66fa7de2f973186d67280c03dd1
| 0.623318 | 2.95049 | false | false | false | false |
blutsvente/MIX
|
test/results/sigport/use/ent_a-rtl-a.vhd
| 1 | 7,055 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:11 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.3 2005/07/15 16:20:07 wig Exp $
-- $Date: 2005/07/15 16:20:07 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:07 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa --
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic;
port_ab_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_ac_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0);
port_ae_5 : in std_ulogic_vector(3 downto 0);
port_ae_6 : in std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2);
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
-- Generated Instance Port Map for inst_ae2
inst_ae2: ent_ae
;
-- End of Generated Instance Port Map for inst_ae2
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
a65a4457011fc747efbc05e31f2929ac
| 0.620411 | 2.826522 | false | false | false | false |
mitchsm/nvc
|
test/regress/record9.vhd
| 4 | 930 |
entity sub is
end entity;
architecture test of sub is
type rec is record
x : integer;
end record;
constant c : rec := (x => 2);
signal s : rec := c;
function add1(x : integer) return integer is
begin
return x + 1;
end function;
begin
process is
variable r : rec := c;
begin
r.x := add1(s.x);
assert r.x = 3;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record9 is
end entity;
architecture test of record9 is
type rec is record
x : bit_vector(1 to 3);
end record;
constant c : rec := (x => "101");
signal s : rec := c;
begin
uut: entity work.sub;
s.x <= "111";
process is
begin
assert s = c;
wait for 1 ns;
assert s = (x => "111");
wait;
end process;
end architecture;
|
gpl-3.0
|
a2e551f4b642d6ecd08b95930c9eec02
| 0.484946 | 3.891213 | false | false | false | false |
mitchsm/nvc
|
test/regress/signal9.vhd
| 5 | 589 |
entity signal9 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of signal9 is
signal vec : std_logic_vector(7 downto 0);
begin
assign_p: vec <= X"52";
count_p: process is
variable ctr : unsigned(7 downto 0) := X"00";
begin
wait for 1 ns;
loop
ctr := ctr + 1;
exit when vec = std_logic_vector(ctr);
end loop;
loop
ctr := ctr + 1;
exit when unsigned(vec) = ctr;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
732b39114f710bc0f3f55b8b0c18acbf
| 0.556876 | 3.635802 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/RMEM/example_design/RMEM_prod.vhd
| 1 | 10,057 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RMEM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RMEM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RMEM_prod;
ARCHITECTURE xilinx OF RMEM_prod IS
COMPONENT RMEM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RMEM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-2.0
|
d35372111cdb1b83177633d820cf5d09
| 0.492194 | 3.834159 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_m2s_memory_dc.vhd
| 1 | 35,061 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_m2s_memory_dc.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank;
use axis_accelerator_adapter_v2_1_6.oarg_columnized_mem_bank;
use axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt;
entity xd_m2s_memory_dc is
generic (
-- System generics:
C_FAMILY : string ; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
SIZE_WIDTH : integer;
CONV_DATA_WIDTH : integer;
CONV_ADDR_WIDTH : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer;
C_AP_ARG_WIDTH : integer;
C_AP_ARG_N_DIM : integer;
C_AP_ARG_DIMS : int_vector;
C_AP_ARG_DIM_1 : integer;
C_AP_ARG_DIM_2 : integer;
C_AP_ARG_FORMAT_TYPE : integer;
C_AP_ARG_FORMAT_FACTOR : integer;
C_AP_ARG_FORMAT_DIM : integer;
C_NONE : integer := 2);
port (
clk : in std_logic;
rst : in std_logic;
conv_addr : in std_logic_vector(CONV_ADDR_WIDTH-1 downto 0);
conv_ce : in std_logic;
conv_we : in std_logic;
conv_last : in std_logic;
conv_rdy : out std_logic;
conv_data : out std_logic_vector(CONV_DATA_WIDTH-1 downto 0);
conv_size : out std_logic_vector(SIZE_WIDTH-1 downto 0);
sw_length : in std_logic_vector(31 downto 0);
sw_length_we : in std_logic;
use_sw_length : in std_logic;
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_arg_addr : in std_logic_vector(C_AP_ARG_ADDR_WIDTH-1 downto 0);
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_rqt : out std_logic;
ap_arg_ack : in std_logic;
-- Status info
ap_arg_empty : out std_logic;
ap_arg_full : out std_logic;
ap_arg_used : out std_logic_vector(3 downto 0)); -- Number of used buffers
end entity;
architecture rtl of xd_m2s_memory_dc is
function calc_sw_length_fifo_width return integer is
variable N_elements : integer;
begin
if (C_AP_ARG_N_DIM = 2) then
N_elements := C_AP_ARG_DIM_1*C_AP_ARG_DIM_2;
else
N_elements := C_AP_ARG_DIM_1;
end if;
return log2(N_elements)+1;
end function calc_sw_length_fifo_width;
function calc_use_columnized_bank return boolean is
variable ret : boolean := false;
begin
if (C_AP_ARG_N_DIM = 2) then
if(C_AP_ARG_FORMAT_TYPE = FORMAT_TYPE_RESHAPE_BLOCK) then
if(C_AP_ARG_FORMAT_DIM = 1 and C_AP_ARG_FORMAT_FACTOR > 1) then
ret := true;
end if;
end if;
end if;
return ret;
end function calc_use_columnized_bank;
--------------------------------------------------------------------------
-- C_AP_ARG_DIMS generic is a vector with range between 1 and C_AP_ARG_N_DIM.
-- It follows VivadoHLS approach (i.e., dimension 1 is the closest to the
-- varibale declaration). For example, A[2][4][8]:
-- C_AP_ARG_DIMS[1] = 2
-- C_AP_ARG_DIMS[2] = 4
-- C_AP_ARG_DIMS[3] = 8
-- For the memory bank organization, it's easier to have this sorted
-- differently, so it reflects the linear organization in which is stored in
-- memory. That is, the dimension more far away from definition is 0 and
-- closest is C_AP_ARG_N_DIM-1. For previous example:
-- ARG_DIMS[2] = 2
-- ARG_DIMS[1] = 4
-- ARG_DIMS[0] = 8
constant ARG_DIMS : int_vector(0 to C_AP_ARG_N_DIM-1) := C_AP_ARG_DIMS;
function calc_addr_lsb return int_vector is
variable lsb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable msb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable lsb : integer := 0;
variable dim_width : integer;
begin
for i in 0 to C_AP_ARG_N_DIM-1 loop
dim_width := log2(ARG_DIMS(i));
lsb_vector(i) := lsb;
msb_vector(i) := lsb+dim_width-1;
lsb := lsb + dim_width;
end loop;
return lsb_vector;
end function calc_addr_lsb;
function calc_addr_msb return int_vector is
variable lsb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable msb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable lsb : integer := 0;
variable dim_width : integer;
begin
for i in 0 to C_AP_ARG_N_DIM-1 loop
dim_width := log2(ARG_DIMS(i));
lsb_vector(i) := lsb;
msb_vector(i) := lsb+dim_width-1;
lsb := lsb + dim_width;
end loop;
return msb_vector;
end function calc_addr_msb;
--constant PTR_WIDTH : integer := log2(C_MULTIBUFFER_DEPTH);
constant PTR_WIDTH : integer := if_then_else((C_MULTIBUFFER_DEPTH = 1),1,log2(C_MULTIBUFFER_DEPTH));
constant GRAY_WIDTH : integer := calc_gray_width(C_MULTIBUFFER_DEPTH);
constant INIT_RD_GRAY : integer := 0;
constant INIT_WR_GRAY : integer := INIT_RD_GRAY;
constant INIT_WR_GRAY_AHEAD : integer := INIT_RD_GRAY-C_MULTIBUFFER_DEPTH+1;
constant conv_din_zero : std_logic_vector(CONV_DATA_WIDTH-1 downto 0) := (others => '0');
constant SW_LENGTH_FIFO_WIDTH : integer := calc_sw_length_fifo_width;
constant USE_COLUMNIZED_BANK : boolean := calc_use_columnized_bank;
signal empty_n : std_logic;
signal full_n : std_logic;
-- Multibuffer push/pop
signal mb_push : std_logic;
signal mb_pop : std_logic;
signal mb_push_ok : std_logic;
signal mb_pop_ok : std_logic;
signal mb_pop_ok1 : std_logic;
signal mb_pop_ok_rd : std_logic;
signal mb_pop_ok_vect: std_logic_vector(0 downto 0);
--
signal iport_ce : std_logic; -- ap_arg_ce validated with full_n
signal oport_ce : std_logic; -- conv_ce validated with empty_n
-- Read buffer selection
signal rd_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal rd_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal rd_pntr_wr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal rd_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_gray_wr : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray_wr: std_logic_vector(GRAY_WIDTH-1 downto 0);
signal prev_rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
-- Gray counter for writes synchronized with read clock
signal wr_gray_sync : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal rd_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal wr_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal ptr_dist : unsigned(GRAY_WIDTH-1 downto 0);
signal pntr_dist : std_logic_vector(PTR_WIDTH-1 downto 0);
-- Write buffer selection
signal wr_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal wr_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal wr_pntr_rd : std_logic_vector(PTR_WIDTH-1 downto 0);
signal wr_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal wr_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
-- Only required for almost empty:
signal prev_wr_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
-- pragma translate_off
signal empty : std_logic;
signal full : std_logic;
-- pragma translate_on
signal ap_arg_hw_length : unsigned(C_AP_ARG_ADDR_WIDTH downto 0);
signal ap_arg_length : std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
signal sw_length_fifo_dout : std_logic_vector(SW_LENGTH_FIFO_WIDTH-1 downto 0);
signal sw_length_wr : std_logic_vector(SW_LENGTH_FIFO_WIDTH-1 downto 0);
signal sw_length_rd : std_logic_vector(SW_LENGTH_FIFO_WIDTH-1 downto 0);
signal sw_length_we_vector : std_logic_vector(0 downto 0);
signal sw_length_we_rd : std_logic;
signal sw_length_we_rd_vector : std_logic_vector(0 downto 0);
signal ap_arg_full_i : std_logic;
type length_mem_type is array (2**PTR_WIDTH-1 downto 0) of std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
signal hw_length_mem : length_mem_type;
signal hw_length_mem_dout : std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
signal hw_length_mem_dout_rd : std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
attribute ram_style : string;
attribute ram_style of hw_length_mem : signal is "distributed";
constant C_EXTRA_SYNCS : integer := 1;
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
-- pragma translate_on
-- New buffer has been produced when accelerator generates ack and the
-- multibuffer is not full.
mb_push <= full_n and ap_arg_ack;
-- New buffer consumed when the last data is read and the multibuffer is not
-- empty.
mb_pop <= empty_n and conv_ce and conv_last;
-- Selection pointer to write buffer (push)
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_ptr <= (others => '0');
wr_ptr_dec <= (others => '0');
wr_ptr_dec(0) <= '1';
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
if(wr_ptr = C_MULTIBUFFER_DEPTH-1) then
wr_ptr <= (others => '0');
else
wr_ptr <= wr_ptr + 1;
end if;
wr_ptr_dec <= wr_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & wr_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
prev_wr_gray <= bin2gray(INIT_WR_GRAY-1, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
prev_wr_gray <= wr_gray;
end if;
end if;
end process;
-- Full status signal generation
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
full_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Go to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
-- Read buffer selection pointer (pop)
process(clk, rst)
begin
if(rst = '1') then
rd_ptr <= (others => '0');
rd_ptr_dec <= (others => '0');
rd_ptr_dec(0) <= '1';
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
if(rd_ptr = C_MULTIBUFFER_DEPTH-1) then
rd_ptr <= (others => '0');
else
rd_ptr <= rd_ptr + 1;
end if;
rd_ptr_dec <= rd_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & rd_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (read) to manage status of multibuffer
process(clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
prev_rd_gray <= bin2gray(INIT_RD_GRAY-1, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
prev_rd_gray <= rd_gray;
end if;
end if;
end process;
-- Empty status signal generation:
process(clk, rst)
begin
if(rst = '1') then
empty_n <= '0';
elsif(clk'event and clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray) then
empty_n <= not(mb_pop_ok);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
-- Management of pseudo-static buffers
-- Para los argumentos de salida no hay buffers pseudo-estáticos.
mb_pop_ok <= mb_pop and empty_n;
---------------------------------------------
conv_rdy <= empty_n;
ap_arg_rqt <= full_n;
iport_ce <= ap_arg_ce and full_n;
oport_ce <= conv_ce and empty_n;
-- Number of used buffers it's calculated as the distance between read/write
-- pointers
-- synch wr_gray to reduce metastability. Added one cycle clock latency on rd_clk
process(clk, rst)
begin
if(rst = '1') then
wr_gray_sync <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
wr_gray_sync <= wr_gray;
end if;
end process;
wr_bin <= unsigned(gray2bin(wr_gray_sync));
process(clk, rst)
begin
if(rst = '1') then
rd_bin <= to_unsigned(INIT_RD_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
rd_bin <= rd_bin + 1;
end if;
end if;
end process;
-- If we only look at the pointers, there will be one cycle latency to reflect
-- the status of the fifo. To refresh inmediately during a read, we decrement
-- the counter
process(clk, rst)
begin
if(rst = '1') then
ptr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
ptr_dist <= ptr_dist - 1;
else
-- This ia also valid when we arrive at the end of sequence counter wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
process(ptr_dist)
begin
ap_arg_used <= (others => '0');
ap_arg_used(ptr_dist'range) <= std_logic_vector(ptr_dist);
end process;
-- Status signals empty/full should be synchronized with AXI clk
ap_arg_empty <= not(empty_n);
process(clk, rst)
begin
if(rst = '1') then
ap_arg_full_i <= '1';
elsif(clk'event and clk = '1') then
-- If read, we move out of full state
if(mb_pop_ok = '1') then
ap_arg_full_i <= '0';
else
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray) then
ap_arg_full_i <= '1';
else
ap_arg_full_i <= '0';
end if;
end if;
end if;
end process;
ap_arg_full <= ap_arg_full_i;
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate
CONSTANT LOG2DEPTH : integer := log2(C_MULTIBUFFER_DEPTH);
CONSTANT ONE : std_logic_vector(PTR_WIDTH-1 DOWNTO 0)
:= int2lv(1, PTR_WIDTH);
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
-- pragma translate_on
-- New buffer has been produced when accelerator generates ack and the
-- multibuffer is not full.
mb_push <= full_n and ap_arg_ack;
-- New buffer consumed when the last data is read and the multibuffer is not
-- empty.
mb_pop <= empty_n and conv_ce and conv_last;
-- Selection pointer to write buffer (push)
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_pntr <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
if(wr_pntr = int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
wr_pntr <= (others => '0');
else
wr_pntr <= wr_pntr + ONE;
end if;
end if;
end if;
end process;
process(clk, rst)
begin
if(rst = '1') then
rd_pntr <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
if(rd_pntr = int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
rd_pntr <= (others => '0');
else
rd_pntr <= rd_pntr + ONE;
end if;
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
prev_wr_gray <= bin2gray(INIT_WR_GRAY-1, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
prev_wr_gray <= wr_gray;
end if;
end if;
end process;
-- Gray pointers (read) to manage status of multibuffer
process(clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
prev_rd_gray <= bin2gray(INIT_RD_GRAY-1, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
prev_rd_gray <= rd_gray;
end if;
end if;
end process;
clkx_1: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => wr_gray,
RD_PNTR => rd_gray,
WR_PNTR_RD => wr_gray_rd,
RD_PNTR_WR => rd_gray_wr
);
clkx_2: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => wr_gray_ahead,
RD_PNTR => next_rd_gray,
WR_PNTR_RD => wr_gray_ahead_rd,
RD_PNTR_WR => next_rd_gray_wr
);
clkx_3: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => PTR_WIDTH,
C_WR_PNTR_WIDTH => PTR_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => wr_pntr,
RD_PNTR => rd_pntr,
WR_PNTR_RD => wr_pntr_rd,
RD_PNTR_WR => rd_pntr_wr
);
-- Full status signal generation
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
full_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray_wr) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Go to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray_wr) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
prd1: PROCESS (clk, rst)
BEGIN
-- Register Stage #1
IF (rst = '1') THEN
mb_pop_ok1 <= '0';
mb_pop_ok_rd <= '0';
ELSIF (clk'event and clk = '1') THEN
mb_pop_ok1 <= mb_pop_ok;
mb_pop_ok_rd <= mb_pop_ok1;
END IF;
END PROCESS prd1;
-- Empty status signal generation:
process(clk, rst)
begin
if(rst = '1') then
empty_n <= '0';
elsif(clk'event and clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray_rd) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray_rd) then
empty_n <= not(mb_pop_ok_rd);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
-- Management of pseudo-static buffers
-- Para los argumentos de salida no hay buffers pseudo-estáticos.
mb_pop_ok <= mb_pop and empty_n;
---------------------------------------------
conv_rdy <= empty_n;
ap_arg_rqt <= full_n;
iport_ce <= ap_arg_ce and full_n;
oport_ce <= conv_ce and empty_n;
-- If we only look at the pointers, there will be one cycle latency to reflect
-- the status of the fifo. To refresh inmediately during a read, we decrement
-- the counter
MBn : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
pntr_dist <= pntr_dist - 1;
else
-- This ia also valid when we arrive at the end of sequence counter wr_bin < rd_bin
--pntr_dist <= ('0' & wr_pntr_rd) - ('0' & rd_pntr);
pntr_dist <= (wr_pntr_rd) - (rd_pntr);
end if;
end if;
end process;
end generate MBn;
MB1 : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
process(clk, rst)
begin
if(rst = '1') then
rd_bins <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
rd_bins <= rd_bins + 1;
end if;
end if;
end process;
wr_bins <= wr_gray_rd;
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
pntr_dist <= pntr_dist - 1;
else
-- This ia also valid when we arrive at the end of sequence counter wr_bin < rd_bin
--pntr_dist <= ('0' & wr_pntr_rd) - ('0' & rd_pntr);
pntr_dist <= (wr_bins) - (rd_bins);
end if;
end if;
end process;
end generate MB1;
process(pntr_dist)
begin
ap_arg_used <= (others => '0');
ap_arg_used(pntr_dist'range) <= (pntr_dist);
end process;
-- Status signals empty/full should be synchronized with AXI clk
ap_arg_empty <= not(empty_n);
process(clk, rst)
begin
if(rst = '1') then
ap_arg_full_i <= '1';
elsif(clk'event and clk = '1') then
-- If read, we move out of full state
if(mb_pop_ok_rd = '1') then
ap_arg_full_i <= '0';
else
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead_rd = next_rd_gray) then
ap_arg_full_i <= '1';
else
ap_arg_full_i <= '0';
end if;
end if;
end if;
end process;
ap_arg_full <= ap_arg_full_i;
end generate NEW_INTRO;
LINEAR_BANK_GEN : if not(USE_COLUMNIZED_BANK) generate
-- address width for input port is the addition of required bits for the
-- argument plus the required bits to select buffer (PTR_WIDTH).
constant IPORT_ADDR_WIDTH : integer := C_AP_ARG_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
constant OPORT_ADDR_WIDTH : integer := CONV_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
signal iport_addr : std_logic_vector(IPORT_ADDR_WIDTH-1 downto 0);
signal oport_addr : std_logic_vector(OPORT_ADDR_WIDTH-1 downto 0);
begin
MB1_addr : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
iport_addr <= ap_arg_addr;
oport_addr <= conv_addr;
end generate MB1_addr;
MBn_addr : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
iport_addr <= std_logic_vector(wr_pntr) & ap_arg_addr;
oport_addr <= std_logic_vector(rd_pntr) & conv_addr;
end generate MBn_addr;
MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => 0,
C_IPORT_DWIDTH => C_AP_ARG_DATA_WIDTH,
C_IPORT_AWIDTH => IPORT_ADDR_WIDTH,
C_OPORT_DWIDTH => CONV_DATA_WIDTH,
C_OPORT_AWIDTH => OPORT_ADDR_WIDTH)
port map (
rst => ap_rst,
iport_clk => ap_clk,
iport_ce => iport_ce,
iport_we => ap_arg_we,
iport_addr => iport_addr,
iport_din => ap_arg_din,
iport_dout => ap_arg_dout,
oport_clk => clk,
oport_ce => oport_ce,
oport_we => conv_we,
oport_addr => oport_addr,
oport_din => conv_din_zero,
oport_dout => conv_data);
end generate LINEAR_BANK_GEN;
COLUMNIZED_BANK_GEN : if (USE_COLUMNIZED_BANK) generate
begin
MEM_I : entity axis_accelerator_adapter_v2_1_6.oarg_columnized_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_FACTOR => C_AP_ARG_FORMAT_FACTOR,
C_BUFFER_WIDTH => PTR_WIDTH,
C_CONV_AWIDTH => CONV_ADDR_WIDTH,
C_CONV_DWIDTH => CONV_DATA_WIDTH,
C_ARG_WIDTH => C_AP_ARG_WIDTH,
C_ARG_AWIDTH => C_AP_ARG_ADDR_WIDTH)
port map (
ap_rst => ap_rst,
ap_clk => ap_clk,
ap_arg_ce => ap_arg_ce,
ap_arg_we => ap_arg_we,
ap_arg_buffer => std_logic_vector(wr_ptr),
ap_arg_addr => ap_arg_addr,
ap_arg_din => ap_arg_din,
ap_arg_dout => ap_arg_dout,
clk => clk,
conv_ce => conv_ce,
conv_we => conv_we,
conv_buffer => std_logic_vector(rd_ptr),
conv_addr => conv_addr,
conv_data => conv_data);
end generate COLUMNIZED_BANK_GEN;
-- To know how many beats to produce on output stream, we track the highest
-- address written
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
ap_arg_hw_length <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if(ap_arg_ack = '1') then
ap_arg_hw_length <= (others => '0');
elsif(iport_ce = '1' and ap_arg_we = '1') then
if(unsigned(ap_arg_addr) >= ap_arg_hw_length) then
ap_arg_hw_length <= unsigned('0' & ap_arg_addr) + 1;
end if;
end if;
end if;
end process;
-- length memory modeling (XST infer)
process(ap_clk)
begin
if(ap_clk'event and ap_clk = '1') then
if(ap_arg_ack = '1') then
hw_length_mem(to_integer(wr_ptr)) <= std_logic_vector(ap_arg_hw_length);
end if;
end if;
end process;
hw_length_mem_dout <= hw_length_mem(to_integer(rd_ptr));
-- clkx_4: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
-- GENERIC MAP(
-- C_HAS_RST => 1,
-- C_RD_PNTR_WIDTH => SW_LENGTH_FIFO_WIDTH,
-- C_WR_PNTR_WIDTH => SW_LENGTH_FIFO_WIDTH,
-- C_MSGON_VAL => 1,
-- C_SYNCHRONIZER_STAGE => 2
-- )
-- PORT MAP(
-- WR_CLK => ap_clk,
-- RD_CLK => clk,
-- WR_RST => ap_rst,
-- RD_RST => rst,
-- WR_PNTR => sw_length_wr,
-- RD_PNTR => open,
-- WR_PNTR_RD => sw_length_rd,
-- RD_PNTR_WR => open
-- );
-- SW_LENGTH_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 0,
-- C_VECTOR_WIDTH => SW_LENGTH_FIFO_WIDTH,
-- C_MTBF_STAGES => 2
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => '0',
-- prmry_vect_in => sw_length_wr,
--
-- scndry_aclk => clk,
-- scndry_resetn => rst,
-- scndry_out => open,
-- scndry_vect_out => sw_length_rd
-- );
clkx_5: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => C_AP_ARG_ADDR_WIDTH+1,
C_WR_PNTR_WIDTH => C_AP_ARG_ADDR_WIDTH+1,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => 2
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => hw_length_mem_dout,
RD_PNTR => open,
WR_PNTR_RD => hw_length_mem_dout_rd,
RD_PNTR_WR => open
);
sw_length_rd <= sw_length(SW_LENGTH_FIFO_WIDTH-1 downto 0);
sw_length_we_vector(0) <= sw_length_we;
sw_length_we_rd <= sw_length_we_rd_vector(0);
wr_stg_inst: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 1,
C_WIDTH => 1
)
PORT MAP (
RST => rst,
CLK => clk,
D => sw_length_we_vector,
Q => sw_length_we_rd_vector
);
SW_LENGTH_FIFO : entity axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt
generic map (
C_FAMILY => C_FAMILY,
WIDTH => SW_LENGTH_FIFO_WIDTH)
port map (
rst => rst,
clk => clk,
din => sw_length_rd,
din_vld => sw_length_we_rd,
din_rdy => open,
dout => sw_length_fifo_dout,
dout_vld => open,
dout_rdy => mb_pop_ok_rd
);
process(use_sw_length, hw_length_mem_dout_rd, sw_length_fifo_dout)
constant HW_LSB : integer := log2(C_AP_ARG_DATA_WIDTH/8);
constant SW_LSB : integer := log2(C_AP_ARG_WIDTH/8);
constant SW_MSB : integer := SW_LSB+SW_LENGTH_FIFO_WIDTH-1;
begin
conv_size <= (others => '0');
if(use_sw_length = '0') then
conv_size(SIZE_WIDTH-1 downto HW_LSB) <= hw_length_mem_dout_rd;
else
conv_size(SW_MSB downto SW_LSB) <= sw_length_fifo_dout;
end if;
end process;
end rtl;
|
mit
|
b5f11bf98733154c5d15cd7e469315ff
| 0.544394 | 3.328049 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/synchronizer_ff.vhd
| 1 | 4,646 |
-------------------------------------------------------------------------------
-- $Id: synchronizer_ff.vhd,v 1.1 2011/06/02 09:44:03 robertb Exp $
-- Title : Binary Counter Module for Write Logic
-- Project : FIFO Generator
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : synchronizer_ff.vhd
-- Author : Xilinx
-------------------------------------------------------------------------------
-- Structure:
-- synchronizer_ff.vhd
--
-------------------------------------------------------------------------------
-- Description:
-- A basic Flip Flop with asynchronous reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
ENTITY synchronizer_ff IS
GENERIC (
C_HAS_RST : integer := 0;
C_WIDTH : integer := 0
);
PORT (
RST : IN std_logic := '0' ;
CLK : IN std_logic := '0' ;
D : IN std_logic_vector(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
Q : OUT std_logic_vector(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END synchronizer_ff;
ARCHITECTURE xilinx OF synchronizer_ff IS
ATTRIBUTE DowngradeIPIdentifiedWarnings: STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF xilinx : ARCHITECTURE IS "yes";
signal Q_reg : std_logic_vector(C_WIDTH-1 downto 0) := (OTHERS => '0');
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF Q_reg : SIGNAL IS "true";
ATTRIBUTE msgon : STRING;
ATTRIBUTE msgon OF Q_reg : SIGNAL IS "true";
-- attribute dont_touch : string;
-- attribute dont_touch of Q_reg : signal is "true";
-- ATTRIBUTE KEEP_HIERARCHY : STRING;
-- ATTRIBUTE KEEP_HIERARCHY of xilinx : ARCHITECTURE IS "yes";
BEGIN
PROCESS (CLK, RST)
BEGIN
IF (RST = '1' AND C_HAS_RST = 1) THEN
Q_reg <= (OTHERS => '0');
-- Q <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
Q_reg <= D AFTER TFF;
-- Q <= D AFTER TFF;
END IF;
END PROCESS;
Q <= Q_reg;
END xilinx;
|
mit
|
18b0b53043b1df952d8149b4ed44ca8e
| 0.600947 | 4.49758 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/comparator.vhd
| 2 | 2,343 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:53:34 11/20/2013
-- Design Name:
-- Module Name: Comparator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comparator is
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
write_t : in STD_LOGIC;
t : in STD_LOGIC_VECTOR(15 downto 0);
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(15 downto 0);
jump : out STD_LOGIC
);
end Comparator;
architecture Behavioral of Comparator is
begin
process(code, write_t, t, T_src_SF, T_src_ZF, T_cmd_src, a)
variable real_t : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
begin
real_t := ZERO;
case code is
-- if (a == 0) jump
when INST_CODE_BEQZ =>
if (a = ZERO) then
jump <= JUMP_TRUE;
else
jump <= JUMP_FALSE;
end if;
-- if (a != 0) jump
when INST_CODE_BNEZ =>
if (a = ZERO) then
jump <= JUMP_FALSE;
else
jump <= JUMP_TRUE;
end if;
--if (t == 0) jump
when INST_CODE_ADDSP_BTEQZ_MTSP =>
if (write_t = WRITE_T_YES) then
if (T_cmd_src = T_SRC_IS_SF) then
if (T_src_SF = '1') then
real_t := FFFF;
else
real_t := ZERO;
end if;
elsif (T_cmd_src = T_SRC_IS_NOT_ZF) then
if (T_src_ZF = '0') then
real_t := FFFF;
else
real_t := ZERO;
end if;
else
NULL;
end if;
else
real_t := t;
end if;
if (real_t = 0) then
jump <= JUMP_TRUE;
else
jump <= JUMP_FALSE;
end if;
when others =>
jump <= JUMP_FALSE;
end case;
end process;
end Behavioral;
|
apache-2.0
|
232fbbd1feb321d85af510ddd14801b9
| 0.559539 | 3.070773 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue143.vhd
| 3 | 1,663 |
package access_field_through_function_pkg is
type record_t is record
field : integer;
end record;
type protected_t is protected
function fun return record_t;
end protected;
function fun return record_t;
function fun(param : integer) return record_t;
function access_field_fun1 return integer;
function access_field_fun2 return integer;
function access_field_fun3 return integer;
end package;
package body access_field_through_function_pkg is
type protected_t is protected body
function fun return record_t is
begin
return (field => 0);
end function;
end protected body;
function fun return record_t is
begin
return (field => 0);
end function;
function fun(param : integer) return record_t is
begin
return (field => param);
end function;
function access_field_fun1 return integer is
begin
return fun.field; -- <-- does not work
end function;
function access_field_fun2 return integer is
begin
return fun(10).field; -- <-- works
end function;
function access_field_fun3 return integer is
variable prot : protected_t;
begin
return prot.fun.field; -- <-- does not work
end function;
end package body;
-------------------------------------------------------------------------------
entity issue143 is
end entity;
use work.access_field_through_function_pkg.all;
architecture test of issue143 is
begin
process is
begin
assert fun.field = 0;
assert fun(4).field = 4;
assert access_field_fun1 = 0;
assert access_field_fun2 = 10;
assert access_field_fun3 = 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
2ecfd5cab1648954cbb5a841240c5468
| 0.657246 | 4.085995 | false | false | false | false |
mitchsm/nvc
|
test/regress/proc3.vhd
| 3 | 1,531 |
package pack is
function func(x : in integer) return integer;
end package;
package body pack is
procedure p5(x : in integer; y : out integer) is
variable k : integer := x + 1;
begin
y := k;
end procedure;
function func(x : in integer) return integer is
variable y : integer;
begin
p5(x, y);
return y;
end function;
end package body;
-------------------------------------------------------------------------------
entity proc3 is
end entity;
use work.pack.all;
architecture test of proc3 is
procedure p1 is
begin
wait for 10 ns;
wait for 5 ns;
end procedure;
procedure p2 is
begin
p1;
p1;
end procedure;
procedure p3(t : in time) is
begin
loop
wait for t;
if now >= 100 ns then
return;
end if;
end loop;
end procedure;
procedure p4(x : in integer; y : out integer) is
variable k : integer;
begin
k := x;
for i in 1 to 5 loop
k := k + 1;
wait for 1 ns;
end loop;
y := k;
end procedure;
begin
process is
variable x : integer;
begin
p1;
assert now = 15 ns;
p2;
assert now = 45 ns;
p3(5 ns);
assert now = 100 ns;
p4(5, x);
assert x = 10;
assert now = 105 ns;
x := func(9);
assert x = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
9141313079e94ea231fb18cf4a3501cd
| 0.474853 | 4.050265 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/mix/inst_b_e-rtl-a.vhd
| 1 | 4,230 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_xa_e -- mulitple instantiated
-- No Generated Generics
port (
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end component;
-- ---------
component inst_bb_e -- bb instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end component;
-- ---------
component inst_vb_e -- verilog udc inst_bc2_i
-- No Generated Generics
-- Generated Generics for Entity inst_vb_e
-- End of Generated Generics for Entity inst_vb_e
-- No Generated Port
end component;
-- ---------
component inst_be_i -- no verilog udc here
-- No Generated Generics
-- Generated Generics for Entity inst_be_i
-- End of Generated Generics for Entity inst_be_i
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
udc: THIS GOES TO DECL of inst_b_i
begin
udc: THIS ARE TWO LINES in BODY of inst_b_i
SECOND LINE
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_aa_ba <= p_mix_signal_aa_ba_gi; -- __I_I_BIT_PORT
p_mix_signal_bb_ab_go <= signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba_i
inst_ba_i: inst_xa_e -- mulitple instantiated
port map (
port_xa_i => signal_aa_ba, -- signal test aa to ba
port_xa_o => open -- open signal to create port
);
-- End of Generated Instance Port Map for inst_ba_i
-- Generated Instance Port Map for inst_bb_i
inst_bb_i: inst_bb_e -- bb instance
port map (
port_bb_o => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_bb_i
-- Generated Instance Port Map for inst_bc1_i
inst_bc1_i: inst_vb_e -- verilog udc inst_bc2_i
;
-- End of Generated Instance Port Map for inst_bc1_i
udc: preinst_udc for inst_bc2_i
-- Generated Instance Port Map for inst_bc2_i
inst_bc2_i: inst_vb_e -- verilog udc inst_bc2_i
;
-- End of Generated Instance Port Map for inst_bc2_i
udc: post_inst_udc for inst_bc2_i
udc: preinst_udc for inst_bc2_i
-- Generated Instance Port Map for inst_be_i
inst_be_i: inst_be_i -- no verilog udc here
;
-- End of Generated Instance Port Map for inst_be_i
udc: post_inst_udc for inst_bc2_i
-- Generated Instance Port Map for inst_bf_i
inst_bf_i: inst_be_i -- no verilog udc here
;
-- End of Generated Instance Port Map for inst_bf_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
86a6dfad54725f0df23ef980604bc353
| 0.628605 | 3.040978 | false | false | false | false |
blutsvente/MIX
|
test/results/nreset2/mdec_core-rtl-a.vhd
| 1 | 7,662 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of mdec_core
--
-- Generated
-- by: wig
-- on: Mon Jun 26 16:38:04 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: mdec_core-rtl-a.vhd,v 1.3 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: mdec_core-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of mdec_core
--
architecture rtl of mdec_core is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component aou
-- No Generated Generics
-- Generated Generics for Entity aou
-- End of Generated Generics for Entity aou
port (
-- Generated Port for Entity aou
reset_i_n : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity aou
);
end component;
-- ---------
component cgu
-- No Generated Generics
-- Generated Generics for Entity cgu
-- End of Generated Generics for Entity cgu
port (
-- Generated Port for Entity cgu
nreset : in std_ulogic; -- Auxiliary Signals (PAD)
nreset_out : out std_ulogic -- Auxiliary Signals (PAD)
-- End of Generated Port for Entity cgu
);
end component;
-- ---------
component cpu
-- No Generated Generics
-- Generated Generics for Entity cpu
-- End of Generated Generics for Entity cpu
port (
-- Generated Port for Entity cpu
nreset : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity cpu
);
end component;
-- ---------
component ema
-- No Generated Generics
-- Generated Generics for Entity ema
-- End of Generated Generics for Entity ema
port (
-- Generated Port for Entity ema
nreset : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity ema
);
end component;
-- ---------
component ga
-- No Generated Generics
port (
-- Generated Port for Entity ga
reset_n : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity ga
);
end component;
-- ---------
component i58_io_logic
-- No Generated Generics
-- Generated Generics for Entity i58_io_logic
-- End of Generated Generics for Entity i58_io_logic
port (
-- Generated Port for Entity i58_io_logic
nreset : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity i58_io_logic
);
end component;
-- ---------
component ifu_top
-- No Generated Generics
-- Generated Generics for Entity ifu_top
-- End of Generated Generics for Entity ifu_top
port (
-- Generated Port for Entity ifu_top
nreset : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity ifu_top
);
end component;
-- ---------
component pdu
-- No Generated Generics
-- Generated Generics for Entity pdu
-- End of Generated Generics for Entity pdu
port (
-- Generated Port for Entity pdu
nreset : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity pdu
);
end component;
-- ---------
component tsd_top
-- No Generated Generics
-- Generated Generics for Entity tsd_top
-- End of Generated Generics for Entity tsd_top
port (
-- Generated Port for Entity tsd_top
nreset : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity tsd_top
);
end component;
-- ---------
component vip
-- No Generated Generics
port (
-- Generated Port for Entity vip
reset_n : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity vip
);
end component;
-- ---------
component vo
-- No Generated Generics
port (
-- Generated Port for Entity vo
reset_n : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity vo
);
end component;
-- ---------
component vor
-- No Generated Generics
port (
-- Generated Port for Entity vor
reset_n : in std_ulogic -- Async. Reset (CGU,PAD)
-- End of Generated Port for Entity vor
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_int_nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
nreset <= s_int_nreset; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for aou_i1
aou_i1: aou
port map (
reset_i_n => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for aou_i1
-- Generated Instance Port Map for cgu_i1
cgu_i1: cgu
port map (
nreset => s_int_nreset, -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
nreset_out => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for cgu_i1
-- Generated Instance Port Map for cpu_i1
cpu_i1: cpu
port map (
nreset => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for cpu_i1
-- Generated Instance Port Map for ema_i1
ema_i1: ema
port map (
nreset => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for ema_i1
-- Generated Instance Port Map for ga_i1
ga_i1: ga
port map (
reset_n => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for ga_i1
-- Generated Instance Port Map for i58_io_logic_i1
i58_io_logic_i1: i58_io_logic
port map (
nreset => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for i58_io_logic_i1
-- Generated Instance Port Map for ifu_top_i1
ifu_top_i1: ifu_top
port map (
nreset => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for ifu_top_i1
-- Generated Instance Port Map for pdu_i1
pdu_i1: pdu
port map (
nreset => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for pdu_i1
-- Generated Instance Port Map for tsd_top_i1
tsd_top_i1: tsd_top
port map (
nreset => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for tsd_top_i1
-- Generated Instance Port Map for vip_i1
vip_i1: vip
port map (
reset_n => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for vip_i1
-- Generated Instance Port Map for vo_i1
vo_i1: vo
port map (
reset_n => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for vo_i1
-- Generated Instance Port Map for vor_i1
vor_i1: vor
port map (
reset_n => s_int_nreset -- Async. Reset (CGU,PAD) (X11)Auxiliary Signals (PAD)
);
-- End of Generated Instance Port Map for vor_i1
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
d9e8fb172fd84439299b6e9057275760
| 0.63704 | 3.215275 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue79.vhd
| 5 | 976 |
package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
end function;
end package body;
entity issue79 is
end entity;
use work.access_bug.all;
architecture test of issue79 is
function make_ptrs(init : integer) return integer_access_array is
variable r : integer_access_array(1 to 5);
begin
for i in r'range loop
r(i) := new integer'(init);
end loop;
return r;
end function;
begin
process is
variable p : integer_access_array(1 to 5);
begin
assert p = (1 to 5 => null);
p := make_ptrs(2);
for i in p'range loop
assert p(i).all = 2;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
528e0f834637246d3227a2c4f0442c12
| 0.633197 | 3.76834 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue95.vhd
| 4 | 785 |
entity issue95 is
end entity;
architecture behav of issue95 is
type point is record
x : integer;
y : integer;
z : boolean;
end record point;
type point_array is array (natural range <>) of point;
signal points : point_array(1 to 4) := (others => (x => 1, y => 1, z => true));
procedure update(signal pa : out point_array) is
begin
pa(3).x <= 7;
end procedure;
begin
process
begin
assert points(3).x = 1;
points(2).y <= 4;
wait for 2 ns;
update(points);
wait;
end process;
process is
begin
wait for 1 ns;
assert points(2) = (1, 4, true);
wait for 2 ns;
assert points(3) = (7, 1, true);
wait;
end process;
end behav;
|
gpl-3.0
|
012f8885a59ecfba6b41e978d918dbe6
| 0.533758 | 3.685446 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue196.vhd
| 5 | 1,142 |
package pkg is
procedure proc(s : string);
end package;
package body pkg is
procedure proc(s : string) is
begin
end procedure;
end package body;
-------------------------------------------------------------------------------
use work.pkg.all;
entity issue196 is
end entity;
architecture tb of issue196 is
type rec_t is record
field : natural;
end record;
procedure proc is
begin
proc("" & LF);
wait for 0 ns;
proc("------------------------------------------------------------" & LF);
end;
procedure proc2 (
constant var : in rec_t := (others => 0)) is
begin
wait for 0 ns;
report integer'image(var.field);
assert var = (others => 0);
proc("--------------------------------abcd" & LF); -- abcd corrupts var
-- var.field was overwritten by "abcd"
report integer'image(var.field) & " = " & integer'image((((character'pos('d')*256 + character'pos('c'))*256 + character'pos('b'))*256 + character'pos('a')));
assert var = (others => 0); -- Should still be 0
end procedure;
begin
main : process
begin
proc;
proc2;
wait;
end process;
end architecture;
|
gpl-3.0
|
1049c25065d82d3a88b14d60cca9aaca
| 0.531524 | 3.979094 | false | false | false | false |
mitchsm/nvc
|
test/sem/std.vhd
| 5 | 570 |
entity a is
end entity;
architecture b of a is
signal i : integer := 5;
signal t : time := 5 fs;
signal c : character := 'x';
subtype my_time is time;
constant x : my_time := my_time'left + 5 ns;
begin
process is
begin
wait for 4 ns;
t <= now;
end process;
process is
-- Default values
variable a : time;
variable b : my_time;
begin
end process;
process is
variable t : time := -1 ns;
variable u : time := 1.2 ns;
begin
end process;
end architecture;
|
gpl-3.0
|
78aec57e1f85fd6462a2df396058c2a9
| 0.542105 | 3.8 | false | false | false | false |
mitchsm/nvc
|
test/regress/agg1.vhd
| 5 | 413 |
entity agg1 is
end entity;
architecture test of agg1 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : integer;
variable v : int_array(1 to 3);
begin
x := 5;
v := ( 1, x, 2 );
assert v = ( 1, 5, 2 );
v := ( v(3), v(2), v(1) );
assert v = ( 2, 5, 1 );
wait;
end process;
end architecture;
|
gpl-3.0
|
dd34e98647a80a7ad13f2fb8f2bc1d26
| 0.491525 | 3.385246 | false | false | false | false |
mitchsm/nvc
|
test/lower/record1.vhd
| 4 | 351 |
entity record1 is
end entity;
architecture test of record1 is
type r1 is record
x, y : integer;
end record;
begin
process is
variable a, b : r1 := (1, 2);
begin
assert a.x = 1;
a.x := 5;
a := b;
assert a.x = 1;
assert a = b;
wait;
end process;
end architecture;
|
gpl-3.0
|
133df8c41119cf2e5fd9094c76da4aca
| 0.501425 | 3.441176 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/connport/inst_t_e-rtl-a.vhd
| 1 | 5,364 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2006/04/10 15:42:07 wig Exp $
-- $Date: 2006/04/10 15:42:07 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:07 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
unsplice_a1 : out std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : out std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : out std_ulogic_vector(127 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_bad_a : out std_ulogic_vector(127 downto 0);
unsplice_bad_b : out std_ulogic_vector(127 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_c_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_d_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_e_e
p_mix_unsplice_a1_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0)
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal unsplice_a1 : std_ulogic_vector(127 downto 0);
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0);
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0);
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0);
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0);
signal unsplice_bad_a : std_ulogic_vector(127 downto 0);
signal unsplice_bad_b : std_ulogic_vector(127 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
unsplice_a1 => unsplice_a1, -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100, -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100, -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100, -- connect mid 100 bits
unsplice_bad_a => unsplice_bad_a,
unsplice_bad_b => unsplice_bad_b -- # conflict
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
;
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: inst_c_e
;
-- End of Generated Instance Port Map for inst_c
-- Generated Instance Port Map for inst_d
inst_d: inst_d_e
;
-- End of Generated Instance Port Map for inst_d
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
p_mix_unsplice_a1_125_0_gi => unsplice_a1(125 downto 0), -- leaves 3 unconnected
p_mix_unsplice_a1_127_127_gi => unsplice_a1(127), -- leaves 3 unconnected
p_mix_unsplice_a2_all128_127_0_gi => unsplice_a2_all128, -- full 128 bit port
p_mix_unsplice_a3_up100_100_0_gi => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
p_mix_unsplice_a4_mid100_99_2_gi => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_a5_midp100_99_2_gi => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_bad_a_1_1_gi => unsplice_bad_a(1),
p_mix_unsplice_bad_b_1_0_gi => unsplice_bad_b(1 downto 0) -- # conflict
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
5c381ac40460229c4079f070fd9ab14a
| 0.644109 | 2.921569 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_e_e-rtl-a.vhd
| 1 | 11,032 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:20 wig Exp $
-- $Date: 2004/04/06 10:50:20 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:20 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
egi_scani : in std_ulogic_vector(10 downto 0);
egi_scano : out std_ulogic_vector(10 downto 0);
p_mix_cp_laddr_31_1_gi : in std_ulogic_vector(30 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_gpio_int_4_0_go : out std_ulogic_vector(4 downto 0);
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
p_mix_tmu_dac_reset_go : out std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
component inst_eb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eb_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_tmi_sbist_fail_12_10_go : out std_ulogic_vector(2 downto 0);
p_mix_v_select_5_0_go : out std_ulogic_vector(5 downto 0);
vclkl27 : in std_ulogic;
vio_scani : in std_ulogic_vector(30 downto 0);
vio_scano : out std_ulogic_vector(30 downto 0)
-- End of Generated Port for Entity inst_eb_e
);
end component;
-- ---------
component inst_ec_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ec_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_v_select_5_0_gi : in std_ulogic_vector(5 downto 0);
tpm_scani : in std_ulogic_vector(12 downto 0);
tpm_scano : out std_ulogic_vector(12 downto 0)
-- End of Generated Port for Entity inst_ec_e
);
end component;
-- ---------
component inst_ed_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ed_e
p_mix_acg_systime_init_30_0_gi : in std_ulogic_vector(30 downto 0);
p_mix_cgs_ramclk_go : out std_ulogic;
p_mix_gpio_int_2_0_gi : in std_ulogic_vector(2 downto 0);
p_mix_itm_scani_0_0_gi : in std_ulogic;
p_mix_nreset_go : out std_ulogic;
p_mix_nreset_s_go : out std_ulogic;
p_mix_tmi_scano_0_0_go : out std_ulogic;
p_mix_vclkl27_go : out std_ulogic
-- End of Generated Port for Entity inst_ed_e
);
end component;
-- ---------
component inst_ee_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ee_e
-- End of Generated Generics for Entity inst_ee_e
port (
-- Generated Port for Entity inst_ee_e
cgs_ramclk : in std_ulogic;
itm_scani : out std_ulogic_vector(70 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic;
si_vclkx2 : in std_ulogic;
tmi_sbist_fail : in std_ulogic_vector(12 downto 0);
tmi_scano : in std_ulogic_vector(70 downto 0)
-- End of Generated Port for Entity inst_ee_e
);
end component;
-- ---------
component inst_ef_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ef_e
-- End of Generated Generics for Entity inst_ef_e
port (
-- Generated Port for Entity inst_ef_e
cp_laddro : out std_ulogic_vector(31 downto 0);
cp_lcmd : out std_ulogic_vector(6 downto 0);
cpu_scani : in std_ulogic_vector(7 downto 0);
cpu_scano : out std_ulogic_vector(7 downto 0);
int23 : in std_ulogic;
int24 : in std_ulogic;
int25 : in std_ulogic;
int26 : in std_ulogic;
int27 : in std_ulogic;
nreset : in std_ulogic;
nreset_s : in std_ulogic;
tap_reset_n : in std_ulogic;
tap_reset_n_o : out std_ulogic
-- End of Generated Port for Entity inst_ef_e
);
end component;
-- ---------
component inst_eg_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eg_e
-- End of Generated Generics for Entity inst_eg_e
port (
-- Generated Port for Entity inst_eg_e
acg_systime_init : out std_ulogic_vector(30 downto 0);
adp_scani : in std_ulogic_vector(6 downto 0);
adp_scano : out std_ulogic_vector(6 downto 0);
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_eg_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal acg_systime_init : std_ulogic_vector(30 downto 0);
signal s_int_cgs_ramclk : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal cp_laddr : std_ulogic_vector(31 downto 0);
signal cp_lcmd : std_ulogic_vector(6 downto 0);
signal gpio_int : std_ulogic_vector(4 downto 0);
signal itm_scani : std_ulogic_vector(70 downto 0);
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic;
signal tap_reset_n_o : std_ulogic;
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0);
signal tmi_scano : std_ulogic_vector(70 downto 0);
signal v_select : std_ulogic_vector(5 downto 0);
signal s_int_vclkl27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
cgs_ramclk <= s_int_cgs_ramclk; -- __I_O_BIT_PORT
p_mix_nreset_go <= nreset; -- __I_O_BIT_PORT
vclkl27 <= s_int_vclkl27; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
egi_scani => itm_scani(31 downto 21),
egi_scano => tmi_scano(31 downto 21),
p_mix_cp_laddr_31_1_gi => cp_laddr(31 downto 1), -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
p_mix_cp_lcmd_6_6_gi => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
p_mix_gpio_int_4_0_go => gpio_int, -- GPIOWakeUPSignalsInterruptinputs
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_11_10_gi => tmi_sbist_fail(11 downto 10),
p_mix_tmi_sbist_fail_9_0_go => tmi_sbist_fail(9 downto 0),
p_mix_tmu_dac_reset_go => tmu_dac_reset, -- CADCTestModeRGBADAC
p_mix_v_select_2_2_gi => v_select(2), -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
p_mix_v_select_5_5_gi => v_select(5) -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_sbist_fail_12_10_go => tmi_sbist_fail(12 downto 10),
p_mix_v_select_5_0_go => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
vclkl27 => s_int_vclkl27, -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
vio_scani => itm_scani(70 downto 40),
vio_scano => tmi_scano(70 downto 40)
);
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
port map (
p_mix_nreset_gi => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_gi => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_v_select_5_0_gi => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
tpm_scani => itm_scani(20 downto 8),
tpm_scano => tmi_scano(20 downto 8)
);
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
port map (
p_mix_acg_systime_init_30_0_gi => acg_systime_init, -- ADPinterfaceScan
p_mix_cgs_ramclk_go => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
p_mix_gpio_int_2_0_gi => gpio_int(2 downto 0), -- GPIOWakeUPSignalsInterruptinputs
p_mix_itm_scani_0_0_gi => itm_scani(0),
p_mix_nreset_go => nreset, -- GlobalRESET(Verilogmacro)
p_mix_nreset_s_go => nreset_s, -- GlobalRESET(Verilogmacro)
p_mix_tmi_scano_0_0_go => tmi_scano(0),
p_mix_vclkl27_go => s_int_vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
port map (
cgs_ramclk => s_int_cgs_ramclk, -- ClockSignalsESDRAMInterface
itm_scani => itm_scani,
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
si_vclkx2 => si_vclkx2, -- DigitalVideoPort
tmi_sbist_fail => tmi_sbist_fail,
tmi_scano => tmi_scano
);
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
port map (
cp_laddro => cp_laddr, -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
cp_lcmd => cp_lcmd, -- GuestBusLBC(memorymappedI/O)Interface
cpu_scani => itm_scani(39 downto 32),
cpu_scano => tmi_scano(39 downto 32),
int23 => gpio_int(0), -- GPIOWakeUPSignalsInterruptinputs
int24 => gpio_int(1), -- GPIOWakeUPSignalsInterruptinputs
int25 => gpio_int(2), -- GPIOWakeUPSignalsInterruptinputs
int26 => gpio_int(3), -- GPIOWakeUPSignalsInterruptinputs
int27 => gpio_int(4), -- GPIOWakeUPSignalsInterruptinputs
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
tap_reset_n => tap_reset_n_o, -- RESETports
tap_reset_n_o => tap_reset_n_o -- RESETports
);
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
port map (
acg_systime_init => acg_systime_init, -- ADPinterfaceScan
adp_scani => itm_scani(7 downto 1),
adp_scano => tmi_scano(7 downto 1),
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
1753e6863d3e378b5d39f9ae01b8228f
| 0.662527 | 2.936385 | false | false | false | false |
mitchsm/nvc
|
lib/synopsys/std_logic_arith.vhd
| 4 | 70,489 |
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
|
gpl-3.0
|
f224449d20fa023751185838a2fa59bb
| 0.63905 | 3.441846 | false | false | false | false |
mitchsm/nvc
|
test/regress/const7.vhd
| 5 | 549 |
entity const7 is
end entity;
architecture test of const7 is
function get_bits(x, len : natural) return bit_vector is
begin
if x = 1 then
return bit_vector'(1 to len => '1');
else
return bit_vector'(1 to len => '0');
end if;
end function;
signal x : bit_vector(7 downto 0) := get_bits(1, 8);
signal y : bit_vector(3 downto 0) := get_bits(5, 4);
begin
process is
begin
assert x = X"ff";
assert y = X"0";
wait;
end process;
end architecture;
|
gpl-3.0
|
678a1682ea14afd57af831bafc333901
| 0.550091 | 3.519231 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab2.vhd
| 5 | 764 |
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
|
gpl-3.0
|
9c32716b2e1fbb71eafb4ffbcf54a96d
| 0.46466 | 3.897959 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/RMEM/simulation/bmg_stim_gen.vhd
| 1 | 7,571 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(12 DOWNTO 0) <= WRITE_ADDR(12 DOWNTO 0);
READ_ADDR_INT(12 DOWNTO 0) <= READ_ADDR(12 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 8192
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
gpl-2.0
|
c3a58a42cd7d36ea584a15937fec2f05
| 0.558183 | 3.77606 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/vhls/get/solution/syn/vhdl/get_gmem_m_axi.vhd
| 4 | 110,726 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity get_gmem_m_axi;
architecture behave of get_gmem_m_axi is
component get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_write;
component get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_read;
component get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component get_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : get_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : get_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity get_gmem_m_axi_fifo;
architecture behave of get_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity get_gmem_m_axi_decoder;
architecture behav of get_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity get_gmem_m_axi_throttl;
architecture behav of get_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_read;
architecture behave of get_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_write;
architecture behave of get_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component get_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : get_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
mit
|
b9c8a40cf07d34c4374d2b5da9a1061a
| 0.448702 | 4.001807 | false | false | false | false |
mitchsm/nvc
|
test/regress/driver3.vhd
| 5 | 444 |
entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert x = "0";
x <= "Z";
wait for 1 ns;
assert x = "H";
wait;
end process;
end architecture;
|
gpl-3.0
|
4a40e854d0f52fd4a55cd981a3d1904e
| 0.497748 | 3.338346 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_3_2/sim/zc702_proc_sys_reset_3_2.vhd
| 1 | 5,843 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_3_2 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_3_2;
ARCHITECTURE zc702_proc_sys_reset_3_2_arch OF zc702_proc_sys_reset_3_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_3_2_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_3_2_arch;
|
mit
|
3db00a96a6f4afed684e0a87b9dcf004
| 0.706144 | 3.575887 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue72.vhd
| 4 | 731 |
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0));
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 0 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
assert s2 = ( "11", "11" );
wait;
end process;
end architecture;
entity issue72 is
end entity;
architecture topi of issue72 is
begin
subi: entity work.arraysub
generic map(par1=>"1111");
end architecture;
|
gpl-3.0
|
07f446bd4814e720b9a699fa6fab909b
| 0.603283 | 3.045833 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/arg_mem_bank.vhd
| 1 | 5,426 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : arg_mem_bank.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-04
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-04 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank_v6;
entity arg_mem_bank is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_IS_UNIDIR : integer range 0 to 1 := 0;
C_OPORT_AWIDTH : integer;
C_OPORT_DWIDTH : integer;
C_IPORT_AWIDTH : integer;
C_IPORT_DWIDTH : integer);
port (
rst : in std_logic;
oport_clk : in std_logic;
oport_ce : in std_logic;
oport_we : in std_logic;
oport_addr : in std_logic_vector(C_OPORT_AWIDTH-1 downto 0);
oport_din : in std_logic_vector(C_OPORT_DWIDTH-1 downto 0);
oport_dout : out std_logic_vector(C_OPORT_DWIDTH-1 downto 0);
iport_clk : in std_logic;
iport_ce : in std_logic;
iport_we : in std_logic;
iport_addr : in std_logic_vector(C_IPORT_AWIDTH-1 downto 0);
iport_din : in std_logic_vector(C_IPORT_DWIDTH-1 downto 0);
iport_dout : out std_logic_vector(C_IPORT_DWIDTH-1 downto 0));
end arg_mem_bank;
architecture rtl of arg_mem_bank is
begin
ARG_MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank_v6
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => C_IS_UNIDIR,
C_OPORT_AWIDTH => C_OPORT_AWIDTH,
C_OPORT_DWIDTH => C_OPORT_DWIDTH,
C_IPORT_AWIDTH => C_IPORT_AWIDTH,
C_IPORT_DWIDTH => C_IPORT_DWIDTH)
port map (
rst => rst,
oport_clk => oport_clk,
oport_ce => oport_ce,
oport_we => oport_we,
oport_addr => oport_addr,
oport_din => oport_din,
oport_dout => oport_dout,
iport_clk => iport_clk,
iport_ce => iport_ce,
iport_we => iport_we,
iport_addr => iport_addr,
iport_din => iport_din,
iport_dout => iport_dout);
end rtl;
|
mit
|
d42cc562bba840cc84580fc73c573c0b
| 0.581091 | 4.116844 | false | false | false | false |
mitchsm/nvc
|
lib/std/standard.vhd
| 3 | 2,567 |
-- -*- coding: latin-1; -*-
--
-- STANDARD package as defined by IEEE 1076-1993
--
package STANDARD is
type INTEGER;
type STRING;
type REAL;
type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
C128, C129, C130, C131, C132, C133, C134,
C135, C136, C137, C138, C139, C140, C141,
C142, C143, C144, C145, C146, C147, C148,
C149, C150, C151, C152, C153, C154, C155,
C156, C157, C158, C159,
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '¶', '¹'
-- TODO: 0xba onwards
);
type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
type INTEGER is range -2147483648 to 2147483647;
type REAL is range -1.7976931348623157e308 to 1.7976931348623157e308;
type TIME is range -9223372036854775808 to 9223372036854775807
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
impure function NOW return DELAY_LENGTH;
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
type STRING is array (POSITIVE range <>) of CHARACTER;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
type FILE_OPEN_KIND is (READ_MODE, WRITE_MODE, APPEND_MODE);
type FILE_OPEN_STATUS is (OPEN_OK, STATUS_ERROR, NAME_ERROR,
MODE_ERROR);
attribute FOREIGN : STRING;
attribute FOREIGN of NOW : function is "_std_standard_now";
end package;
|
gpl-3.0
|
712ef8837b78b9d7cdd1d93f94b52676
| 0.439034 | 3.070574 | false | false | false | false |
mitchsm/nvc
|
test/regress/loop1.vhd
| 5 | 970 |
entity loop1 is
end entity;
architecture test of loop1 is
begin
process is
variable a, b, c : integer;
begin
a := 0;
loop
exit when a = 10;
a := a + 1;
end loop;
assert a = 10;
a := 0;
b := 0;
loop
a := a + 1;
next when (a mod 2) = 0;
b := b + 1;
exit when b = 10;
end loop;
assert b = 10;
assert a = 19;
a := 0;
b := 0;
loop
a := a + 1;
if (a mod 2) = 0 then
next;
end if;
b := b + 1;
exit when b = 10;
end loop;
assert b = 10;
assert a = 19;
a := 0;
outer: loop
for i in 1 to 10 loop
a := a + 1;
exit outer when a = 50;
end loop;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
d9e5123f7daebf80dd83368bfcebd95a
| 0.353608 | 3.99177 | false | false | false | false |
mitchsm/nvc
|
test/sem/generate.vhd
| 5 | 1,106 |
entity g is
end entity;
architecture test of g is
constant c : integer := 5;
signal x : integer;
signal b : bit_vector(1 to 5);
begin
g1: if true generate -- OK
begin
x <= 5;
end generate;
g2: if x generate -- Error
begin
end generate;
g3: if false generate -- OK
signal y : integer;
begin
y <= x;
end generate;
g4: if false generate
y <= 5; -- Error
end generate;
g5: for i in 1 to 5 generate -- OK
b(i) <= '1';
end generate;
g6: for x in b'range generate -- OK
constant k : bit := '1';
begin
b(x) <= k;
end generate;
g7: for x in b'range generate
alias a is b(x); -- OK
begin
a <= '1';
end generate;
g8: if x > 4 generate -- Error
end generate;
g9: for i in 1 to x generate -- Error
end generate;
g10: for i in integer (-4) to integer (-1) generate -- OK
end generate;
end architecture;
|
gpl-3.0
|
0942f8afce5e9e8056aff09a4902d79f
| 0.473779 | 3.853659 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/symmetric_dp_bank_v6.vhd
| 1 | 33,836 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : symmetric_dp_bank_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
entity symmetric_dp_bank_v6 is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_BANK_AWIDTH : integer;
C_BANK_DWIDTH : integer);
port (
rst : in std_logic;
clk_a : in std_logic;
ce_a : in std_logic;
we_a : in std_logic;
addr_a : in std_logic_vector(C_BANK_AWIDTH-1 downto 0);
din_a : in std_logic_vector(C_BANK_DWIDTH-1 downto 0);
dout_a : out std_logic_vector(C_BANK_DWIDTH-1 downto 0);
clk_b : in std_logic;
ce_b : in std_logic;
we_b : in std_logic;
addr_b : in std_logic_vector(C_BANK_AWIDTH-1 downto 0);
din_b : in std_logic_vector(C_BANK_DWIDTH-1 downto 0);
dout_b : out std_logic_vector(C_BANK_DWIDTH-1 downto 0));
end symmetric_dp_bank_v6;
architecture rtl of symmetric_dp_bank_v6 is
constant MAX_BRAM_AWIDTH : integer := 15; -- 32Kx1
constant MIN_BRAM_AWIDTH : integer := 10; -- 1Kx32
constant MAX_BRAM_DWIDTH : integer := 32; -- 1Kx32
constant MIN_BRAM_DWIDTH : integer := 1; -- 32Kx1
function calc_cfg_bram_dwidth(awidth : natural) return integer is
variable dwidth : integer;
begin
if(awidth > MAX_BRAM_AWIDTH) then
-- If required address bitwidth is bigger than possible bitwidth, then we
-- have to increase depth. In this case, the BRAMs are configured x1.
dwidth := 1;
else
-- bitwidth for data bus is calculated using the following expression:
dwidth := 2**(MAX_BRAM_AWIDTH-awidth);
-- assuming that we do not go above max possible bitwidth:
if(dwidth > MAX_BRAM_DWIDTH) then
dwidth := MAX_BRAM_DWIDTH;
end if;
end if;
return dwidth;
end function calc_cfg_bram_dwidth;
function calc_cfg_bram_awidth(bank_awidth : natural) return integer is
variable awidth : integer;
begin
if(bank_awidth > MAX_BRAM_AWIDTH) then
-- If bitwidth of address for bank is bigger than max possible BRAM
-- configuration, we should increase depth. in this case, we use max
-- bitwidth for BRAMs
awidth := MAX_BRAM_AWIDTH;
else
-- otherwise, we use same bitwidth as the bank, given that it's not less
-- than the BRAM bitwidth
if(bank_awidth < MIN_BRAM_AWIDTH) then
awidth := MIN_BRAM_AWIDTH;
else
awidth := bank_awidth;
end if;
end if;
return awidth;
end function calc_cfg_bram_awidth;
function calc_col_size(bank_awidth : natural) return integer is
variable col_size : integer;
begin
if(bank_awidth > MAX_BRAM_AWIDTH) then
col_size := 2**(bank_awidth-MAX_BRAM_AWIDTH);
else
col_size := 1;
end if;
return col_size;
end function calc_col_size;
constant BRAM_CFG_AWIDTH : integer := calc_cfg_bram_awidth(C_BANK_AWIDTH);
constant BRAM_AWIDTH : integer := min_size(BRAM_CFG_AWIDTH, C_BANK_AWIDTH);
constant COL_SIZE : integer := calc_col_size(C_BANK_AWIDTH);
constant BRAM_CFG_DWIDTH : integer := calc_cfg_bram_dwidth(BRAM_CFG_AWIDTH);
constant BRAM_DWIDTH : integer := min_size(BRAM_CFG_DWIDTH, C_BANK_DWIDTH);
constant ROW_SIZE : integer := div_round_up(C_BANK_DWIDTH, BRAM_CFG_DWIDTH);
begin
ONE_COL_GEN : if (COL_SIZE = 1) generate
signal bram_addr_a : std_logic_vector(15 downto 0);
signal bram_addr_b : std_logic_vector(15 downto 0);
-- address bus for primitive has a width of MAX_BRAM_AWIDTH+1 bits (15),
-- but when we use configurations with widths bigger than x1, then LSB's
-- are not used. In this case, the efective LSB is given by BRAM_CFG_DWIDTH
-- and efective bitwidth is given by the bank C_BANK_AWIDTH
constant BRAM_ADDR_LSB : integer := log2(BRAM_CFG_DWIDTH);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+C_BANK_AWIDTH-1;
begin
process(addr_a)
begin
bram_addr_a <= (others => '0');
bram_addr_a(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_a;
end process;
process(addr_b)
begin
bram_addr_b <= (others => '0');
bram_addr_b(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_b;
end process;
MEM_BANK_GEN : for i in 0 to ROW_SIZE-1 generate
signal bram_din_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_a : std_logic_vector(3 downto 0);
signal bram_din_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_b : std_logic_vector(7 downto 0);
begin
-- In the BRAM input port, only BRAM_DWIDTH LS bits are used
process(din_a)
begin
bram_din_a <= (others => '0');
bram_din_a(BRAM_DWIDTH-1 downto 0) <= din_a(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i);
end process;
process(din_b)
begin
bram_din_b <= (others => '0');
bram_din_b(BRAM_DWIDTH-1 downto 0) <= din_b(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i);
end process;
-- same approach is used on output port
dout_a(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i) <= bram_dout_a(BRAM_DWIDTH-1 downto 0);
dout_b(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i) <= bram_dout_b(BRAM_DWIDTH-1 downto 0);
-- we signals are comon; dont support byte-level we signals
bram_we_a <= (others => we_a);
bram_we_b <= (others => we_b);
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP", -- "SDP" or "TDP"
READ_WIDTH_A => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din_a, -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout_a, -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_addr_a, -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a, -- 1-bit input A port clock/Read clock input
ENARDEN => ce_a, -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => bram_we_a, -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din_b, -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout_b, -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_addr_b, -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b, -- 1-bit input B port clock/Write clock input
ENBWREN => ce_b, -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
--WEBWE => x"FF"); -- 8-bit input B port write enable/Write enable input
WEBWE => bram_we_b); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72,
READ_WIDTH_B => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8) -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
)
PORT MAP (
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
DBITERR => open,
DOUTADOUT => bram_dout_a, -- 32-bit output A port data/LSB data output
DOUTBDOUT => bram_dout_b, -- 32-bit output B port data/MSB data output
DOUTPADOUTP => open,
DOUTPBDOUTP => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
ADDRARDADDR => bram_addr_a(14 downto 0), -- 16-bit input A port address/Read address input
ADDRBWRADDR => bram_addr_b(14 downto 0), -- 16-bit input B port address/Write address input
ADDRENA => '0',
ADDRENB => '0',
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
CLKARDCLK => clk_a,
CLKBWRCLK => clk_b,
DINADIN => bram_din_a, -- 32-bit input A port data/LSB data input
DINBDIN => bram_din_b, -- 32-bit input B port data/MSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
ECCPIPECE => '0',
ENARDEN => ce_a, -- 1-bit input A port enable/Read enable input
ENBWREN => ce_b, -- 1-bit input B port enable/Write enable input
INJECTDBITERR => '0',
INJECTSBITERR => '0',
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => rst,
RSTRAMB => rst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SLEEP => '0',
WEA => bram_we_a, -- 4-bit input A port write enable input
WEBWE => bram_we_b -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate MEM_BANK_GEN;
end generate ONE_COL_GEN;
DEPTH_EXPANSION_GEN : if (COL_SIZE > 1) generate
constant BRAM_ADDR_LSB : integer := log2(BRAM_CFG_DWIDTH);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+C_BANK_AWIDTH-1;
constant WORD_AWIDTH : integer := log2(COL_SIZE);
constant ADDR_LSB : integer := 0;
constant ADDR_MSB : integer := MAX_BRAM_AWIDTH-1;
constant BRAM_SEL_LSB : integer := ADDR_MSB+1;
constant BRAM_SEL_MSB : integer := C_BANK_AWIDTH-1;
signal bram_addr_a : std_logic_vector(15 downto 0);
signal bram_addr_b : std_logic_vector(15 downto 0);
signal bram_ce_a : std_logic_vector(COL_SIZE-1 downto 0);
signal bram_ce_b : std_logic_vector(COL_SIZE-1 downto 0);
signal bram_sel_addr_a : std_logic_vector(WORD_AWIDTH-1 downto 0);
signal bram_sel_addr_b : std_logic_vector(WORD_AWIDTH-1 downto 0);
begin
-- we use WORD_AWIDTH MS bits to select the BRAM inside a column
process(addr_a, ce_a)
begin
bram_ce_a <= (others => '0');
if (ce_a = '1') then
for i in 0 to COL_SIZE-1 loop
if (unsigned(addr_a(BRAM_SEL_MSB downto BRAM_SEL_LSB)) = i) then
bram_ce_a(i) <= '1';
end if;
end loop;
end if;
end process;
process(addr_b, ce_b)
begin
bram_ce_b <= (others => '0');
if (ce_b = '1') then
for i in 0 to COL_SIZE-1 loop
if (unsigned(addr_b(BRAM_SEL_MSB downto BRAM_SEL_LSB)) = i) then
bram_ce_b(i) <= '1';
end if;
end loop;
end if;
end process;
-- This set of bits have to be registered to generate the selection signal
-- on the mux's in the output datapath
process(clk_a)
begin
if (clk_a'event and clk_a = '1') then
if (ce_a = '1') then
bram_sel_addr_a <= addr_a(BRAM_SEL_MSB downto BRAM_SEL_LSB);
end if;
end if;
end process;
process(clk_b)
begin
if (clk_b'event and clk_b = '1') then
if (ce_b = '1') then
bram_sel_addr_b <= addr_b(BRAM_SEL_MSB downto BRAM_SEL_LSB);
end if;
end if;
end process;
-- In this case, given that it is a depth increase, we use all width for
-- address bus on BRAMs
process(addr_a)
begin
bram_addr_a <= (others => '0');
bram_addr_a(MAX_BRAM_AWIDTH-1 downto 0) <= addr_a(MAX_BRAM_AWIDTH-1 downto 0);
end process;
process(addr_b)
begin
bram_addr_b <= (others => '0');
bram_addr_b(MAX_BRAM_AWIDTH-1 downto 0) <= addr_b(MAX_BRAM_AWIDTH-1 downto 0);
end process;
MEM_BANK_GEN : for i in 0 to ROW_SIZE-1 generate
signal bram_din_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_a : std_logic_vector(3 downto 0);
signal bram_din_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_b : std_logic_vector(7 downto 0);
-- These "superbusses" represent all data busses at the output of all
-- BRAM's in the same column. In reality, BRAM_DWIDTH is always 1.
signal col_dout_a : std_logic_vector(COL_SIZE*BRAM_DWIDTH-1 downto 0);
signal col_dout_b : std_logic_vector(COL_SIZE*BRAM_DWIDTH-1 downto 0);
begin
-- In each BRAM column, the input data is applied in parallel to all
-- BRAMs. we only use BRAM_DWIDTH LS bits:
process(din_a)
begin
bram_din_a <= (others => '0');
bram_din_a(BRAM_DWIDTH-1 downto 0) <= din_a(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i);
end process;
process(din_b)
begin
bram_din_b <= (others => '0');
bram_din_b(BRAM_DWIDTH-1 downto 0) <= din_b(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i);
end process;
-- mux's on output busses on the same column
process(col_dout_a, bram_sel_addr_a)
variable mux_dout : std_logic_vector(BRAM_DWIDTH-1 downto 0);
begin
mux_dout := (others => '0');
for k in 0 to COL_SIZE-1 loop
if (unsigned(bram_sel_addr_a) = k) then
mux_dout := col_dout_a(BRAM_DWIDTH*(k+1)-1 downto BRAM_DWIDTH*k);
end if;
end loop;
dout_a(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i) <= mux_dout;
end process;
process(col_dout_b, bram_sel_addr_b)
variable mux_dout : std_logic_vector(BRAM_DWIDTH-1 downto 0);
begin
mux_dout := (others => '0');
for k in 0 to COL_SIZE-1 loop
if (unsigned(bram_sel_addr_b) = k) then
mux_dout := col_dout_b(BRAM_DWIDTH*(k+1)-1 downto BRAM_DWIDTH*k);
end if;
end loop;
dout_b(BRAM_DWIDTH*(i+1)-1 downto BRAM_DWIDTH*i) <= mux_dout;
end process;
-- not supported byte-level we signals. All bystes written at the same time.
bram_we_a <= (others => we_a);
bram_we_b <= (others => we_b);
BRAM_COL_GEN : for k in 0 to COL_SIZE-1 generate
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
begin
-- this superbus groups all datapath at memory outputs
col_dout_a(BRAM_DWIDTH*(k+1)-1 downto BRAM_DWIDTH*k) <= bram_dout_a(BRAM_DWIDTH-1 downto 0);
col_dout_b(BRAM_DWIDTH*(k+1)-1 downto BRAM_DWIDTH*k) <= bram_dout_b(BRAM_DWIDTH-1 downto 0);
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP", -- "SDP" or "TDP"
READ_WIDTH_A => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din_a, -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout_a, -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_addr_a, -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a, -- 1-bit input A port clock/Read clock input
ENARDEN => bram_ce_a(k), -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => bram_we_a, -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din_b, -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout_b, -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_addr_b, -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b, -- 1-bit input B port clock/Write clock input
ENBWREN => bram_ce_b(k), -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
WEBWE => bram_we_b); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72,
READ_WIDTH_B => BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A=> BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B=> BRAM_CFG_DWIDTH+(BRAM_CFG_DWIDTH/8) -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
)
PORT MAP (
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
DBITERR => open,
DOUTADOUT => bram_dout_a, -- 32-bit output A port data/LSB data output
DOUTBDOUT => bram_dout_b, -- 32-bit output B port data/MSB data output
DOUTPADOUTP => open,
DOUTPBDOUTP => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
ADDRARDADDR => bram_addr_a(14 downto 0), -- 16-bit input A port address/Read address input
ADDRBWRADDR => bram_addr_b(14 downto 0), -- 16-bit input B port address/Write address input
ADDRENA => '0',
ADDRENB => '0',
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
CLKARDCLK => clk_a,
CLKBWRCLK => clk_b,
DINADIN => bram_din_a, -- 32-bit input A port data/LSB data input
DINBDIN => bram_din_b, -- 32-bit input B port data/MSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
ECCPIPECE => '0',
ENARDEN => bram_ce_a(k), -- 1-bit input A port enable/Read enable input
ENBWREN => bram_ce_b(k), -- 1-bit input B port enable/Write enable input
INJECTDBITERR=> '0',
INJECTSBITERR=> '0',
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM=> rst,
RSTRAMB => rst,
RSTREGARSTREG=> '0',
RSTREGB => '0',
SLEEP => '0',
WEA => bram_we_a, -- 4-bit input A port write enable input
WEBWE => bram_we_b -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate BRAM_COL_GEN;
end generate MEM_BANK_GEN;
end generate DEPTH_EXPANSION_GEN;
end rtl;
|
mit
|
9c0554f7c5b3a4e77fc660bd0757d40e
| 0.535436 | 3.820687 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/blk_mem_gen_inputMem_ste/example_design/bmg_wrapper.vhd
| 1 | 10,225 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 131072
-- C_READ_DEPTH_A : 131072
-- C_ADDRA_WIDTH : 17
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 131072
-- C_READ_DEPTH_B : 131072
-- C_ADDRB_WIDTH : 17
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 1
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 1
-- C_DISABLE_WARN_BHV_RANGE : 1
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT blk_mem_gen_inputMem_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_inputMem_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
gpl-2.0
|
b23e98c74d822862bbce92894e6f1780
| 0.49291 | 3.838213 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/RMEM/simulation/RMEM_synth.vhd
| 1 | 7,855 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RMEM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY RMEM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE RMEM_synth_ARCH OF RMEM_synth IS
COMPONENT RMEM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: RMEM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-2.0
|
99a907f12d0377bf271d99f2e2cb25bf
| 0.564099 | 3.780077 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue38.vhd
| 4 | 720 |
package p is
function f (i : bit) return integer;
end package p;
package body p is
function f (i : bit) return integer is
begin
assert f'instance_name = ":work:p:f";
assert f'path_name = ":work:p:f";
return 0;
end function f;
end package body p;
-------------------------------------------------------------------------------
entity issue38 is
begin
end entity issue38;
use work.p.all;
architecture a of issue38 is
function g (i : bit) return integer is
begin
assert g'instance_name = ":issue38(a):g";
assert g'path_name = ":issue38:g";
return 0;
end function g;
begin
assert (f('1') = 0);
assert (g('1') = 0);
end architecture a;
|
gpl-3.0
|
f7a4ecd9e674034c5e5724b1ba0c4e3d
| 0.5375 | 3.654822 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd
| 6 | 22,231 |
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_8;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_8.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
mit
|
3ad250b09e1451fb994fb2102ec0a91c
| 0.436688 | 4.153774 | false | false | false | false |
mitchsm/nvc
|
test/sem/concat.vhd
| 4 | 1,294 |
entity concat is
end entity;
architecture t of concat is
type int_array is array (integer range <>) of integer;
begin
process
variable w : int_array(1 to 4);
variable x, y : int_array(1 to 3);
variable z : int_array(1 to 6);
variable s : string(1 to 5);
variable t : int_array(1 to 2);
variable b : bit_vector(1 to 3);
variable c : bit_vector(1 to 4);
begin
x := ( 1, 2, 3 );
y := ( 4, 5, 6 );
z := x & y; -- OK
w := 1 & x; -- OK
w := y & 5; -- OK
s := 'h' & string'("ello"); -- OK
s := 1 & string'("ello"); -- Error
t := 6 & 7; -- OK
t := 7 & character'( 'x' ); -- Error
c := bit_vector(b & '1'); -- OK
assert "10" = ("1" & b(1)); -- OK
assert ("1" & b(1)) = "10"; -- OK
assert "10" = (b(1) & "0"); -- OK
wait;
end process;
process
type mem_type is array (1 to 128) of bit_vector(7 downto 0);
variable mem : mem_type;
variable byte : bit_vector(7 downto 0);
begin
mem := mem(1 to 127) & byte; -- OK
wait;
end process;
end architecture;
|
gpl-3.0
|
ea8be8a99a712d11338f8dc77e3845cb
| 0.419629 | 3.535519 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/cu.vhd
| 1 | 2,943 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
use work.cu_package.all;
use work.dma_package.all;
entity cu is
port (
i : in cu_in;
o : out cu_out
);
end entity cu;
architecture logic of cu is
signal q, r : cu_int;
signal re : cu_ext;
begin
comb : process(all)
variable v : cu_int;
begin
----------------------------------------------------------------------------------------------------------------------- default assignments
v := r;
v.pull := '0';
v.o.read.valid := '0';
v.o.write.request.valid := '0';
v.o.write.data.valid := '0';
----------------------------------------------------------------------------------------------------------------------- state machine
case r.state is
when idle =>
if i.start then
v.state := copy;
v.wed := i.wed;
v.o.done := '0';
read_cachelines (v.o.read, i.wed.source, i.wed.size);
write_cachelines (v.o.write.request, i.wed.destination, i.wed.size);
end if;
when copy =>
if not(re.fifo.empty) and not(i.write.full(0)) then
v.pull := '1';
write_data (v.o.write.data, re.fifo.data);
end if;
v.wed.size := r.wed.size - u(i.write.valid);
if v.wed.size = 0 then
v.state := done;
end if;
when done =>
v.o.done := '1';
v.state := idle;
when others => null;
end case;
----------------------------------------------------------------------------------------------------------------------- outputs
-- drive input registers
q <= v;
-- outputs
o <= r.o;
end process;
----------------------------------------------------------------------------------------------------------------------- fifo
fifo0 : entity work.fifo generic map (DMA_DATA_WIDTH, 8, '1', 0)
port map (
cr.clk => i.cr.clk,
cr.rst => i.start,
put => i.read.valid,
data_in => i.read.data,
pull => q.pull,
data_out => re.fifo.data,
empty => re.fifo.empty,
full => re.fifo.full
);
----------------------------------------------------------------------------------------------------------------------- reset & registers
reg : process(i.cr)
begin
if rising_edge(i.cr.clk) then
if i.cr.rst then
cu_reset(r);
else
r <= q;
end if;
end if;
end process;
end architecture logic;
|
bsd-2-clause
|
e331fc22453824aaf20cc6a350697e5a
| 0.346925 | 4.405689 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_compare5.vhd
| 2 | 4,429 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare5.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare5 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare5;
ARCHITECTURE SYN OF lpm_compare5 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "100011100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "284"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 284 0 0 9 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
3911fac6f8cbf0a7dfa3f7f84a66510f
| 0.654775 | 3.68776 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_get_0_if_0/synth/zc702_get_0_if_0.vhd
| 1 | 55,359 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axis_accelerator_adapter:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axis_accelerator_adapter_v2_1_6;
USE axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter;
ENTITY zc702_get_0_if_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_vld : IN STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END zc702_get_0_if_0;
ARCHITECTURE zc702_get_0_if_0_arch OF zc702_get_0_if_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_get_0_if_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_accelerator_adapter IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_AP_ADAPTER_ID : INTEGER;
C_N_INPUT_ARGS : INTEGER;
C_N_OUTPUT_ARGS : INTEGER;
C_S_AXIS_TDATA_WIDTH : INTEGER;
C_S_AXIS_TUSER_WIDTH : INTEGER;
C_S_AXIS_TID_WIDTH : INTEGER;
C_S_AXIS_TDEST_WIDTH : INTEGER;
C_AP_IARG_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_IARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_IARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_0_DWIDTH : INTEGER;
C_AP_IARG_1_DWIDTH : INTEGER;
C_AP_IARG_2_DWIDTH : INTEGER;
C_AP_IARG_3_DWIDTH : INTEGER;
C_AP_IARG_4_DWIDTH : INTEGER;
C_AP_IARG_5_DWIDTH : INTEGER;
C_AP_IARG_6_DWIDTH : INTEGER;
C_AP_IARG_7_DWIDTH : INTEGER;
C_M_AXIS_TDATA_WIDTH : INTEGER;
C_M_AXIS_TUSER_WIDTH : INTEGER;
C_M_AXIS_TID_WIDTH : INTEGER;
C_M_AXIS_TDEST_WIDTH : INTEGER;
C_AP_OARG_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_OARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_OARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_0_DWIDTH : INTEGER;
C_AP_OARG_1_DWIDTH : INTEGER;
C_AP_OARG_2_DWIDTH : INTEGER;
C_AP_OARG_3_DWIDTH : INTEGER;
C_AP_OARG_4_DWIDTH : INTEGER;
C_AP_OARG_5_DWIDTH : INTEGER;
C_AP_OARG_6_DWIDTH : INTEGER;
C_AP_OARG_7_DWIDTH : INTEGER;
C_N_INOUT_SCALARS : INTEGER;
C_N_INPUT_SCALARS : INTEGER;
C_INPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_INPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_OUTPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_AP_ISCALAR_DOUT_WIDTH : INTEGER;
C_AP_ISCALAR_IO_DOUT_WIDTH : INTEGER;
C_INPUT_SCALAR_0_WIDTH : INTEGER;
C_INPUT_SCALAR_1_WIDTH : INTEGER;
C_INPUT_SCALAR_2_WIDTH : INTEGER;
C_INPUT_SCALAR_3_WIDTH : INTEGER;
C_INPUT_SCALAR_4_WIDTH : INTEGER;
C_INPUT_SCALAR_5_WIDTH : INTEGER;
C_INPUT_SCALAR_6_WIDTH : INTEGER;
C_INPUT_SCALAR_7_WIDTH : INTEGER;
C_INPUT_SCALAR_8_WIDTH : INTEGER;
C_INPUT_SCALAR_9_WIDTH : INTEGER;
C_INPUT_SCALAR_10_WIDTH : INTEGER;
C_INPUT_SCALAR_11_WIDTH : INTEGER;
C_INPUT_SCALAR_12_WIDTH : INTEGER;
C_INPUT_SCALAR_13_WIDTH : INTEGER;
C_INPUT_SCALAR_14_WIDTH : INTEGER;
C_INPUT_SCALAR_15_WIDTH : INTEGER;
C_OUTPUT_SCALAR_0_WIDTH : INTEGER;
C_OUTPUT_SCALAR_1_WIDTH : INTEGER;
C_OUTPUT_SCALAR_2_WIDTH : INTEGER;
C_OUTPUT_SCALAR_3_WIDTH : INTEGER;
C_OUTPUT_SCALAR_4_WIDTH : INTEGER;
C_OUTPUT_SCALAR_5_WIDTH : INTEGER;
C_OUTPUT_SCALAR_6_WIDTH : INTEGER;
C_OUTPUT_SCALAR_7_WIDTH : INTEGER;
C_OUTPUT_SCALAR_8_WIDTH : INTEGER;
C_OUTPUT_SCALAR_9_WIDTH : INTEGER;
C_OUTPUT_SCALAR_10_WIDTH : INTEGER;
C_OUTPUT_SCALAR_11_WIDTH : INTEGER;
C_OUTPUT_SCALAR_12_WIDTH : INTEGER;
C_OUTPUT_SCALAR_13_WIDTH : INTEGER;
C_OUTPUT_SCALAR_14_WIDTH : INTEGER;
C_OUTPUT_SCALAR_15_WIDTH : INTEGER;
C_N_OUTPUT_SCALARS : INTEGER;
C_OUTPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_AP_OSCALAR_DIN_WIDTH : INTEGER;
C_AP_OSCALAR_IO_DIN_WIDTH : INTEGER;
C_ENABLE_STREAM_CLK : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_S_AXIS_HAS_TSTRB : INTEGER;
C_S_AXIS_HAS_TKEEP : INTEGER;
C_NONE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_aresetn : IN STD_LOGIC;
s_axis_0_aclk : IN STD_LOGIC;
s_axis_0_aresetn : IN STD_LOGIC;
s_axis_0_tvalid : IN STD_LOGIC;
s_axis_0_tready : OUT STD_LOGIC;
s_axis_0_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_0_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tlast : IN STD_LOGIC;
s_axis_0_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_aclk : IN STD_LOGIC;
s_axis_1_aresetn : IN STD_LOGIC;
s_axis_1_tvalid : IN STD_LOGIC;
s_axis_1_tready : OUT STD_LOGIC;
s_axis_1_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_1_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tlast : IN STD_LOGIC;
s_axis_1_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_aclk : IN STD_LOGIC;
s_axis_2_aresetn : IN STD_LOGIC;
s_axis_2_tvalid : IN STD_LOGIC;
s_axis_2_tready : OUT STD_LOGIC;
s_axis_2_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_2_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tlast : IN STD_LOGIC;
s_axis_2_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_aclk : IN STD_LOGIC;
s_axis_3_aresetn : IN STD_LOGIC;
s_axis_3_tvalid : IN STD_LOGIC;
s_axis_3_tready : OUT STD_LOGIC;
s_axis_3_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_3_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tlast : IN STD_LOGIC;
s_axis_3_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_aclk : IN STD_LOGIC;
s_axis_4_aresetn : IN STD_LOGIC;
s_axis_4_tvalid : IN STD_LOGIC;
s_axis_4_tready : OUT STD_LOGIC;
s_axis_4_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_4_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tlast : IN STD_LOGIC;
s_axis_4_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_aclk : IN STD_LOGIC;
s_axis_5_aresetn : IN STD_LOGIC;
s_axis_5_tvalid : IN STD_LOGIC;
s_axis_5_tready : OUT STD_LOGIC;
s_axis_5_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_5_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tlast : IN STD_LOGIC;
s_axis_5_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_aclk : IN STD_LOGIC;
s_axis_6_aresetn : IN STD_LOGIC;
s_axis_6_tvalid : IN STD_LOGIC;
s_axis_6_tready : OUT STD_LOGIC;
s_axis_6_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_6_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tlast : IN STD_LOGIC;
s_axis_6_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_aclk : IN STD_LOGIC;
s_axis_7_aresetn : IN STD_LOGIC;
s_axis_7_tvalid : IN STD_LOGIC;
s_axis_7_tready : OUT STD_LOGIC;
s_axis_7_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_7_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tlast : IN STD_LOGIC;
s_axis_7_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_iarg_0_clk : IN STD_LOGIC;
ap_iarg_0_rst : IN STD_LOGIC;
ap_iarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_ce : IN STD_LOGIC;
ap_iarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_clk : IN STD_LOGIC;
ap_iarg_1_rst : IN STD_LOGIC;
ap_iarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_ce : IN STD_LOGIC;
ap_iarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_clk : IN STD_LOGIC;
ap_iarg_2_rst : IN STD_LOGIC;
ap_iarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_ce : IN STD_LOGIC;
ap_iarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_clk : IN STD_LOGIC;
ap_iarg_3_rst : IN STD_LOGIC;
ap_iarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_ce : IN STD_LOGIC;
ap_iarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_clk : IN STD_LOGIC;
ap_iarg_4_rst : IN STD_LOGIC;
ap_iarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_ce : IN STD_LOGIC;
ap_iarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_clk : IN STD_LOGIC;
ap_iarg_5_rst : IN STD_LOGIC;
ap_iarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_ce : IN STD_LOGIC;
ap_iarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_clk : IN STD_LOGIC;
ap_iarg_6_rst : IN STD_LOGIC;
ap_iarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_ce : IN STD_LOGIC;
ap_iarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_clk : IN STD_LOGIC;
ap_iarg_7_rst : IN STD_LOGIC;
ap_iarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_ce : IN STD_LOGIC;
ap_iarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_read : IN STD_LOGIC;
ap_fifo_iarg_0_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_1_read : IN STD_LOGIC;
ap_fifo_iarg_1_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_2_read : IN STD_LOGIC;
ap_fifo_iarg_2_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_3_read : IN STD_LOGIC;
ap_fifo_iarg_3_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_4_read : IN STD_LOGIC;
ap_fifo_iarg_4_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_5_read : IN STD_LOGIC;
ap_fifo_iarg_5_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_6_read : IN STD_LOGIC;
ap_fifo_iarg_6_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_7_read : IN STD_LOGIC;
ap_fifo_iarg_7_empty_n : OUT STD_LOGIC;
m_axis_aclk : IN STD_LOGIC;
m_axis_aresetn : IN STD_LOGIC;
m_axis_0_aclk : IN STD_LOGIC;
m_axis_0_aresetn : IN STD_LOGIC;
m_axis_0_tvalid : OUT STD_LOGIC;
m_axis_0_tready : IN STD_LOGIC;
m_axis_0_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_0_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tlast : OUT STD_LOGIC;
m_axis_0_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_aclk : IN STD_LOGIC;
m_axis_1_aresetn : IN STD_LOGIC;
m_axis_1_tvalid : OUT STD_LOGIC;
m_axis_1_tready : IN STD_LOGIC;
m_axis_1_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_1_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tlast : OUT STD_LOGIC;
m_axis_1_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_aclk : IN STD_LOGIC;
m_axis_2_aresetn : IN STD_LOGIC;
m_axis_2_tvalid : OUT STD_LOGIC;
m_axis_2_tready : IN STD_LOGIC;
m_axis_2_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_2_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tlast : OUT STD_LOGIC;
m_axis_2_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_aclk : IN STD_LOGIC;
m_axis_3_aresetn : IN STD_LOGIC;
m_axis_3_tvalid : OUT STD_LOGIC;
m_axis_3_tready : IN STD_LOGIC;
m_axis_3_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_3_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tlast : OUT STD_LOGIC;
m_axis_3_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_aclk : IN STD_LOGIC;
m_axis_4_aresetn : IN STD_LOGIC;
m_axis_4_tvalid : OUT STD_LOGIC;
m_axis_4_tready : IN STD_LOGIC;
m_axis_4_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_4_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tlast : OUT STD_LOGIC;
m_axis_4_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_aclk : IN STD_LOGIC;
m_axis_5_aresetn : IN STD_LOGIC;
m_axis_5_tvalid : OUT STD_LOGIC;
m_axis_5_tready : IN STD_LOGIC;
m_axis_5_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_5_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tlast : OUT STD_LOGIC;
m_axis_5_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_aclk : IN STD_LOGIC;
m_axis_6_aresetn : IN STD_LOGIC;
m_axis_6_tvalid : OUT STD_LOGIC;
m_axis_6_tready : IN STD_LOGIC;
m_axis_6_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_6_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tlast : OUT STD_LOGIC;
m_axis_6_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_aclk : IN STD_LOGIC;
m_axis_7_aresetn : IN STD_LOGIC;
m_axis_7_tvalid : OUT STD_LOGIC;
m_axis_7_tready : IN STD_LOGIC;
m_axis_7_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_7_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tlast : OUT STD_LOGIC;
m_axis_7_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_oarg_0_clk : IN STD_LOGIC;
ap_oarg_0_rst : IN STD_LOGIC;
ap_oarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_ce : IN STD_LOGIC;
ap_oarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_clk : IN STD_LOGIC;
ap_oarg_1_rst : IN STD_LOGIC;
ap_oarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_ce : IN STD_LOGIC;
ap_oarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_clk : IN STD_LOGIC;
ap_oarg_2_rst : IN STD_LOGIC;
ap_oarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_ce : IN STD_LOGIC;
ap_oarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_clk : IN STD_LOGIC;
ap_oarg_3_rst : IN STD_LOGIC;
ap_oarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_ce : IN STD_LOGIC;
ap_oarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_clk : IN STD_LOGIC;
ap_oarg_4_rst : IN STD_LOGIC;
ap_oarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_ce : IN STD_LOGIC;
ap_oarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_clk : IN STD_LOGIC;
ap_oarg_5_rst : IN STD_LOGIC;
ap_oarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_ce : IN STD_LOGIC;
ap_oarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_clk : IN STD_LOGIC;
ap_oarg_6_rst : IN STD_LOGIC;
ap_oarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_ce : IN STD_LOGIC;
ap_oarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_clk : IN STD_LOGIC;
ap_oarg_7_rst : IN STD_LOGIC;
ap_oarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_ce : IN STD_LOGIC;
ap_oarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_write : IN STD_LOGIC;
ap_fifo_oarg_0_full_n : OUT STD_LOGIC;
ap_fifo_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_1_write : IN STD_LOGIC;
ap_fifo_oarg_1_full_n : OUT STD_LOGIC;
ap_fifo_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_2_write : IN STD_LOGIC;
ap_fifo_oarg_2_full_n : OUT STD_LOGIC;
ap_fifo_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_3_write : IN STD_LOGIC;
ap_fifo_oarg_3_full_n : OUT STD_LOGIC;
ap_fifo_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_4_write : IN STD_LOGIC;
ap_fifo_oarg_4_full_n : OUT STD_LOGIC;
ap_fifo_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_5_write : IN STD_LOGIC;
ap_fifo_oarg_5_full_n : OUT STD_LOGIC;
ap_fifo_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_6_write : IN STD_LOGIC;
ap_fifo_oarg_6_full_n : OUT STD_LOGIC;
ap_fifo_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_7_write : IN STD_LOGIC;
ap_fifo_oarg_7_full_n : OUT STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_8_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_9_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_10_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_11_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_12_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_13_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_14_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_15_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_8_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_9_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_10_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_11_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_12_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_13_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_14_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_15_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_vld : IN STD_LOGIC;
ap_oscalar_1_vld : IN STD_LOGIC;
ap_oscalar_2_vld : IN STD_LOGIC;
ap_oscalar_3_vld : IN STD_LOGIC;
ap_oscalar_4_vld : IN STD_LOGIC;
ap_oscalar_5_vld : IN STD_LOGIC;
ap_oscalar_6_vld : IN STD_LOGIC;
ap_oscalar_7_vld : IN STD_LOGIC;
ap_oscalar_8_vld : IN STD_LOGIC;
ap_oscalar_9_vld : IN STD_LOGIC;
ap_oscalar_10_vld : IN STD_LOGIC;
ap_oscalar_11_vld : IN STD_LOGIC;
ap_oscalar_12_vld : IN STD_LOGIC;
ap_oscalar_13_vld : IN STD_LOGIC;
ap_oscalar_14_vld : IN STD_LOGIC;
ap_oscalar_15_vld : IN STD_LOGIC;
ap_oscalar_0_ack : OUT STD_LOGIC;
ap_oscalar_1_ack : OUT STD_LOGIC;
ap_oscalar_2_ack : OUT STD_LOGIC;
ap_oscalar_3_ack : OUT STD_LOGIC;
ap_oscalar_4_ack : OUT STD_LOGIC;
ap_oscalar_5_ack : OUT STD_LOGIC;
ap_oscalar_6_ack : OUT STD_LOGIC;
ap_oscalar_7_ack : OUT STD_LOGIC;
ap_oscalar_8_ack : OUT STD_LOGIC;
ap_oscalar_9_ack : OUT STD_LOGIC;
ap_oscalar_10_ack : OUT STD_LOGIC;
ap_oscalar_11_ack : OUT STD_LOGIC;
ap_oscalar_12_ack : OUT STD_LOGIC;
ap_oscalar_13_ack : OUT STD_LOGIC;
ap_oscalar_14_ack : OUT STD_LOGIC;
ap_oscalar_15_ack : OUT STD_LOGIC;
ap_iscalar_0_ack : IN STD_LOGIC;
ap_iscalar_1_ack : IN STD_LOGIC;
ap_iscalar_2_ack : IN STD_LOGIC;
ap_iscalar_3_ack : IN STD_LOGIC;
ap_iscalar_4_ack : IN STD_LOGIC;
ap_iscalar_5_ack : IN STD_LOGIC;
ap_iscalar_6_ack : IN STD_LOGIC;
ap_iscalar_7_ack : IN STD_LOGIC;
ap_iscalar_8_ack : IN STD_LOGIC;
ap_iscalar_9_ack : IN STD_LOGIC;
ap_iscalar_10_ack : IN STD_LOGIC;
ap_iscalar_11_ack : IN STD_LOGIC;
ap_iscalar_12_ack : IN STD_LOGIC;
ap_iscalar_13_ack : IN STD_LOGIC;
ap_iscalar_14_ack : IN STD_LOGIC;
ap_iscalar_15_ack : IN STD_LOGIC;
ap_iscalar_0_vld : OUT STD_LOGIC;
ap_iscalar_1_vld : OUT STD_LOGIC;
ap_iscalar_2_vld : OUT STD_LOGIC;
ap_iscalar_3_vld : OUT STD_LOGIC;
ap_iscalar_4_vld : OUT STD_LOGIC;
ap_iscalar_5_vld : OUT STD_LOGIC;
ap_iscalar_6_vld : OUT STD_LOGIC;
ap_iscalar_7_vld : OUT STD_LOGIC;
ap_iscalar_8_vld : OUT STD_LOGIC;
ap_iscalar_9_vld : OUT STD_LOGIC;
ap_iscalar_10_vld : OUT STD_LOGIC;
ap_iscalar_11_vld : OUT STD_LOGIC;
ap_iscalar_12_vld : OUT STD_LOGIC;
ap_iscalar_13_vld : OUT STD_LOGIC;
ap_iscalar_14_vld : OUT STD_LOGIC;
ap_iscalar_15_vld : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT axis_accelerator_adapter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zc702_get_0_if_0_arch: ARCHITECTURE IS "axis_accelerator_adapter,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zc702_get_0_if_0_arch : ARCHITECTURE IS "zc702_get_0_if_0,axis_accelerator_adapter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zc702_get_0_if_0_arch: ARCHITECTURE IS "zc702_get_0_if_0,axis_accelerator_adapter,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_accelerator_adapter,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_AP_ADAPTER_ID=1,C_N_INPUT_ARGS=0,C_N_OUTPUT_ARGS=0,C_S_AXIS_TDATA_WIDTH=64,C_S_AXIS_TUSER_WIDTH=8,C_S_AXIS_TID_WIDTH=4,C_S_AXIS_TDEST_WIDTH=4,C_AP_IARG_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_IARG_MB_DEPTH=0x0000000400000004000000040000000400000004000000040000000400000004,C_AP_IARG_WIDTH=0x0000002000000020000000200000002000000020000000200000002000000020,C_AP_IARG_N_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_DIM_1=0x0000040000000400000004000000040000000400000004000000040000000400,C_AP_IARG_DIM_2=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_FORMAT_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_IARG_FORMAT_FACTOR=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_FORMAT_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_0_DWIDTH=32,C_AP_IARG_1_DWIDTH=32,C_AP_IARG_2_DWIDTH=32,C_AP_IARG_3_DWIDTH=32,C_AP_IARG_4_DWIDTH=32,C_AP_IARG_5_DWIDTH=32,C_AP_IARG_6_DWIDTH=32,C_AP_IARG_7_DWIDTH=32,C_M_AXIS_TDATA_WIDTH=64,C_M_AXIS_TUSER_WIDTH=8,C_M_AXIS_TID_WIDTH=4,C_M_AXIS_TDEST_WIDTH=4,C_AP_OARG_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_OARG_MB_DEPTH=0x0000000400000004000000040000000400000004000000040000000400000004,C_AP_OARG_WIDTH=0x0000002000000020000000200000002000000020000000200000002000000020,C_AP_OARG_N_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_DIM=0x0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008,C_AP_OARG_DIM_1=0x0000040000000400000004000000040000000400000004000000040000000400,C_AP_OARG_DIM_2=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_FORMAT_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_OARG_FORMAT_FACTOR=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_FORMAT_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_0_DWIDTH=32,C_AP_OARG_1_DWIDTH=32,C_AP_OARG_2_DWIDTH=32,C_AP_OARG_3_DWIDTH=32,C_AP_OARG_4_DWIDTH=32,C_AP_OARG_5_DWIDTH=32,C_AP_OARG_6_DWIDTH=32,C_AP_OARG_7_DWIDTH=32,C_N_INOUT_SCALARS=0,C_N_INPUT_SCALARS=2,C_INPUT_SCALAR_DWIDTH=0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020,C_INPUT_SCALAR_MODE=0x0000000000000000,C_OUTPUT_SCALAR_MODE=0x0000000000000010,C_AP_ISCALAR_DOUT_WIDTH=64,C_AP_ISCALAR_IO_DOUT_WIDTH=32,C_INPUT_SCALAR_0_WIDTH=32,C_INPUT_SCALAR_1_WIDTH=32,C_INPUT_SCALAR_2_WIDTH=32,C_INPUT_SCALAR_3_WIDTH=32,C_INPUT_SCALAR_4_WIDTH=32,C_INPUT_SCALAR_5_WIDTH=32,C_INPUT_SCALAR_6_WIDTH=32,C_INPUT_SCALAR_7_WIDTH=32,C_INPUT_SCALAR_8_WIDTH=32,C_INPUT_SCALAR_9_WIDTH=32,C_INPUT_SCALAR_10_WIDTH=32,C_INPUT_SCALAR_11_WIDTH=32,C_INPUT_SCALAR_12_WIDTH=32,C_INPUT_SCALAR_13_WIDTH=32,C_INPUT_SCALAR_14_WIDTH=32,C_INPUT_SCALAR_15_WIDTH=32,C_OUTPUT_SCALAR_0_WIDTH=32,C_OUTPUT_SCALAR_1_WIDTH=32,C_OUTPUT_SCALAR_2_WIDTH=32,C_OUTPUT_SCALAR_3_WIDTH=32,C_OUTPUT_SCALAR_4_WIDTH=32,C_OUTPUT_SCALAR_5_WIDTH=32,C_OUTPUT_SCALAR_6_WIDTH=32,C_OUTPUT_SCALAR_7_WIDTH=32,C_OUTPUT_SCALAR_8_WIDTH=32,C_OUTPUT_SCALAR_9_WIDTH=32,C_OUTPUT_SCALAR_10_WIDTH=32,C_OUTPUT_SCALAR_11_WIDTH=32,C_OUTPUT_SCALAR_12_WIDTH=32,C_OUTPUT_SCALAR_13_WIDTH=32,C_OUTPUT_SCALAR_14_WIDTH=32,C_OUTPUT_SCALAR_15_WIDTH=32,C_N_OUTPUT_SCALARS=2,C_OUTPUT_SCALAR_DWIDTH=0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020,C_AP_OSCALAR_DIN_WIDTH=64,C_AP_OSCALAR_IO_DIN_WIDTH=32,C_ENABLE_STREAM_CLK=0,C_PRMRY_IS_ACLK_ASYNC=0,C_S_AXIS_HAS_TSTRB=0,C_S_AXIS_HAS_TKEEP=0,C_NONE=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL start";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done";
ATTRIBUTE X_INTERFACE_INFO OF ap_continue: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL continue";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL idle";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axis_accelerator_adapter
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_AP_ADAPTER_ID => 1,
C_N_INPUT_ARGS => 0,
C_N_OUTPUT_ARGS => 0,
C_S_AXIS_TDATA_WIDTH => 64,
C_S_AXIS_TUSER_WIDTH => 8,
C_S_AXIS_TID_WIDTH => 4,
C_S_AXIS_TDEST_WIDTH => 4,
C_AP_IARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_IARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_IARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_IARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_0_DWIDTH => 32,
C_AP_IARG_1_DWIDTH => 32,
C_AP_IARG_2_DWIDTH => 32,
C_AP_IARG_3_DWIDTH => 32,
C_AP_IARG_4_DWIDTH => 32,
C_AP_IARG_5_DWIDTH => 32,
C_AP_IARG_6_DWIDTH => 32,
C_AP_IARG_7_DWIDTH => 32,
C_M_AXIS_TDATA_WIDTH => 64,
C_M_AXIS_TUSER_WIDTH => 8,
C_M_AXIS_TID_WIDTH => 4,
C_M_AXIS_TDEST_WIDTH => 4,
C_AP_OARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_OARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_OARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_DIM => X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008",
C_AP_OARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_OARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_0_DWIDTH => 32,
C_AP_OARG_1_DWIDTH => 32,
C_AP_OARG_2_DWIDTH => 32,
C_AP_OARG_3_DWIDTH => 32,
C_AP_OARG_4_DWIDTH => 32,
C_AP_OARG_5_DWIDTH => 32,
C_AP_OARG_6_DWIDTH => 32,
C_AP_OARG_7_DWIDTH => 32,
C_N_INOUT_SCALARS => 0,
C_N_INPUT_SCALARS => 2,
C_INPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_INPUT_SCALAR_MODE => X"0000000000000000",
C_OUTPUT_SCALAR_MODE => X"0000000000000010",
C_AP_ISCALAR_DOUT_WIDTH => 64,
C_AP_ISCALAR_IO_DOUT_WIDTH => 32,
C_INPUT_SCALAR_0_WIDTH => 32,
C_INPUT_SCALAR_1_WIDTH => 32,
C_INPUT_SCALAR_2_WIDTH => 32,
C_INPUT_SCALAR_3_WIDTH => 32,
C_INPUT_SCALAR_4_WIDTH => 32,
C_INPUT_SCALAR_5_WIDTH => 32,
C_INPUT_SCALAR_6_WIDTH => 32,
C_INPUT_SCALAR_7_WIDTH => 32,
C_INPUT_SCALAR_8_WIDTH => 32,
C_INPUT_SCALAR_9_WIDTH => 32,
C_INPUT_SCALAR_10_WIDTH => 32,
C_INPUT_SCALAR_11_WIDTH => 32,
C_INPUT_SCALAR_12_WIDTH => 32,
C_INPUT_SCALAR_13_WIDTH => 32,
C_INPUT_SCALAR_14_WIDTH => 32,
C_INPUT_SCALAR_15_WIDTH => 32,
C_OUTPUT_SCALAR_0_WIDTH => 32,
C_OUTPUT_SCALAR_1_WIDTH => 32,
C_OUTPUT_SCALAR_2_WIDTH => 32,
C_OUTPUT_SCALAR_3_WIDTH => 32,
C_OUTPUT_SCALAR_4_WIDTH => 32,
C_OUTPUT_SCALAR_5_WIDTH => 32,
C_OUTPUT_SCALAR_6_WIDTH => 32,
C_OUTPUT_SCALAR_7_WIDTH => 32,
C_OUTPUT_SCALAR_8_WIDTH => 32,
C_OUTPUT_SCALAR_9_WIDTH => 32,
C_OUTPUT_SCALAR_10_WIDTH => 32,
C_OUTPUT_SCALAR_11_WIDTH => 32,
C_OUTPUT_SCALAR_12_WIDTH => 32,
C_OUTPUT_SCALAR_13_WIDTH => 32,
C_OUTPUT_SCALAR_14_WIDTH => 32,
C_OUTPUT_SCALAR_15_WIDTH => 32,
C_N_OUTPUT_SCALARS => 2,
C_OUTPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_AP_OSCALAR_DIN_WIDTH => 64,
C_AP_OSCALAR_IO_DIN_WIDTH => 32,
C_ENABLE_STREAM_CLK => 0,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_S_AXIS_HAS_TSTRB => 0,
C_S_AXIS_HAS_TKEEP => 0,
C_NONE => 2
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axis_aclk => '0',
s_axis_aresetn => '0',
s_axis_0_aclk => '0',
s_axis_0_aresetn => '0',
s_axis_0_tvalid => '0',
s_axis_0_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_0_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tlast => '0',
s_axis_0_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_aclk => '0',
s_axis_1_aresetn => '0',
s_axis_1_tvalid => '0',
s_axis_1_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_1_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tlast => '0',
s_axis_1_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_aclk => '0',
s_axis_2_aresetn => '0',
s_axis_2_tvalid => '0',
s_axis_2_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_2_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tlast => '0',
s_axis_2_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_aclk => '0',
s_axis_3_aresetn => '0',
s_axis_3_tvalid => '0',
s_axis_3_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_3_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tlast => '0',
s_axis_3_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_aclk => '0',
s_axis_4_aresetn => '0',
s_axis_4_tvalid => '0',
s_axis_4_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_4_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tlast => '0',
s_axis_4_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_aclk => '0',
s_axis_5_aresetn => '0',
s_axis_5_tvalid => '0',
s_axis_5_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_5_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tlast => '0',
s_axis_5_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_aclk => '0',
s_axis_6_aresetn => '0',
s_axis_6_tvalid => '0',
s_axis_6_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_6_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tlast => '0',
s_axis_6_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_aclk => '0',
s_axis_7_aresetn => '0',
s_axis_7_tvalid => '0',
s_axis_7_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_7_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tlast => '0',
s_axis_7_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ap_iarg_0_clk => '0',
ap_iarg_0_rst => '0',
ap_iarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_0_ce => '0',
ap_iarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_clk => '0',
ap_iarg_1_rst => '0',
ap_iarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_ce => '0',
ap_iarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_clk => '0',
ap_iarg_2_rst => '0',
ap_iarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_ce => '0',
ap_iarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_clk => '0',
ap_iarg_3_rst => '0',
ap_iarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_ce => '0',
ap_iarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_clk => '0',
ap_iarg_4_rst => '0',
ap_iarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_ce => '0',
ap_iarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_clk => '0',
ap_iarg_5_rst => '0',
ap_iarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_ce => '0',
ap_iarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_clk => '0',
ap_iarg_6_rst => '0',
ap_iarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_ce => '0',
ap_iarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_clk => '0',
ap_iarg_7_rst => '0',
ap_iarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_ce => '0',
ap_iarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_iarg_0_read => '0',
ap_fifo_iarg_1_read => '0',
ap_fifo_iarg_2_read => '0',
ap_fifo_iarg_3_read => '0',
ap_fifo_iarg_4_read => '0',
ap_fifo_iarg_5_read => '0',
ap_fifo_iarg_6_read => '0',
ap_fifo_iarg_7_read => '0',
m_axis_aclk => '0',
m_axis_aresetn => '0',
m_axis_0_aclk => '0',
m_axis_0_aresetn => '0',
m_axis_0_tready => '0',
m_axis_1_aclk => '0',
m_axis_1_aresetn => '0',
m_axis_1_tready => '0',
m_axis_2_aclk => '0',
m_axis_2_aresetn => '0',
m_axis_2_tready => '0',
m_axis_3_aclk => '0',
m_axis_3_aresetn => '0',
m_axis_3_tready => '0',
m_axis_4_aclk => '0',
m_axis_4_aresetn => '0',
m_axis_4_tready => '0',
m_axis_5_aclk => '0',
m_axis_5_aresetn => '0',
m_axis_5_tready => '0',
m_axis_6_aclk => '0',
m_axis_6_aresetn => '0',
m_axis_6_tready => '0',
m_axis_7_aclk => '0',
m_axis_7_aresetn => '0',
m_axis_7_tready => '0',
ap_oarg_0_clk => '0',
ap_oarg_0_rst => '0',
ap_oarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_0_ce => '0',
ap_oarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_clk => '0',
ap_oarg_1_rst => '0',
ap_oarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_ce => '0',
ap_oarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_clk => '0',
ap_oarg_2_rst => '0',
ap_oarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_ce => '0',
ap_oarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_clk => '0',
ap_oarg_3_rst => '0',
ap_oarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_ce => '0',
ap_oarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_clk => '0',
ap_oarg_4_rst => '0',
ap_oarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_ce => '0',
ap_oarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_clk => '0',
ap_oarg_5_rst => '0',
ap_oarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_ce => '0',
ap_oarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_clk => '0',
ap_oarg_6_rst => '0',
ap_oarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_ce => '0',
ap_oarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_clk => '0',
ap_oarg_7_rst => '0',
ap_oarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_ce => '0',
ap_oarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_write => '0',
ap_fifo_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_1_write => '0',
ap_fifo_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_2_write => '0',
ap_fifo_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_3_write => '0',
ap_fifo_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_4_write => '0',
ap_fifo_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_5_write => '0',
ap_fifo_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_6_write => '0',
ap_fifo_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_7_write => '0',
aclk => aclk,
aresetn => aresetn,
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_iscalar_0_dout => ap_iscalar_0_dout,
ap_iscalar_1_dout => ap_iscalar_1_dout,
ap_oscalar_0_din => ap_oscalar_0_din,
ap_oscalar_1_din => ap_oscalar_1_din,
ap_oscalar_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_8_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_9_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_10_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_11_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_12_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_13_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_14_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_15_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_0_vld => '0',
ap_oscalar_1_vld => ap_oscalar_1_vld,
ap_oscalar_2_vld => '0',
ap_oscalar_3_vld => '0',
ap_oscalar_4_vld => '0',
ap_oscalar_5_vld => '0',
ap_oscalar_6_vld => '0',
ap_oscalar_7_vld => '0',
ap_oscalar_8_vld => '0',
ap_oscalar_9_vld => '0',
ap_oscalar_10_vld => '0',
ap_oscalar_11_vld => '0',
ap_oscalar_12_vld => '0',
ap_oscalar_13_vld => '0',
ap_oscalar_14_vld => '0',
ap_oscalar_15_vld => '0',
ap_iscalar_0_ack => '0',
ap_iscalar_1_ack => '0',
ap_iscalar_2_ack => '0',
ap_iscalar_3_ack => '0',
ap_iscalar_4_ack => '0',
ap_iscalar_5_ack => '0',
ap_iscalar_6_ack => '0',
ap_iscalar_7_ack => '0',
ap_iscalar_8_ack => '0',
ap_iscalar_9_ack => '0',
ap_iscalar_10_ack => '0',
ap_iscalar_11_ack => '0',
ap_iscalar_12_ack => '0',
ap_iscalar_13_ack => '0',
ap_iscalar_14_ack => '0',
ap_iscalar_15_ack => '0',
interrupt => interrupt
);
END zc702_get_0_if_0_arch;
|
mit
|
03756e978e2088ff0d811b469e550f3b
| 0.636012 | 2.937129 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/pkg/mmio_package.vhd
| 1 | 2,383 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psl.all;
package mmio_package is
----------------------------------------------------------------------------------------------------------------------- parameters
constant MMIO_REG_ADDRESS : unsigned(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0) := x"fffffe";
----------------------------------------------------------------------------------------------------------------------- io
type mmio_ac_in is record
data : std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
end record;
type mmio_in is record
cr : cr_in;
ac : mmio_ac_in;
ha : psl_mmio_in;
end record;
type mmio_out is record
ah : psl_mmio_out;
end record;
----------------------------------------------------------------------------------------------------------------------- internals
type mmio_int is record
ack : std_logic;
cfg_read : std_logic;
cfg_write : std_logic;
cfg_data : std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
mmio_read : std_logic;
mmio_write : std_logic;
mmio_dw : std_logic;
mmio_wdata : std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
mmio_rdata : std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
reg : std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
end record;
----------------------------------------------------------------------------------------------------------------------- functions + procedures
procedure mmio_reset (signal r : inout mmio_int);
end package mmio_package;
package body mmio_package is
procedure mmio_reset (signal r : inout mmio_int) is
begin
r.ack <= '0';
r.cfg_read <= '0';
r.cfg_write <= '0';
r.cfg_data <= (others => '0');
r.mmio_read <= '0';
r.mmio_write <= '0';
r.mmio_dw <= '0';
r.mmio_wdata <= (others => '0');
r.mmio_rdata <= (others => '0');
r.reg <= (others => '0');
end procedure mmio_reset;
end package body mmio_package;
|
bsd-2-clause
|
909fe460e651d6a609645f97d65af39d
| 0.397818 | 4.496226 | false | false | false | false |
mitchsm/nvc
|
test/sem/ports.vhd
| 3 | 8,404 |
package foo_pkg is
type my_int is range 0 to 100;
subtype my_int_sub is my_int range 10 to 20;
end package;
-------------------------------------------------------------------------------
use work.foo_pkg.all;
entity foo is
port (
o : out my_int;
i : in my_int );
end entity;
-------------------------------------------------------------------------------
architecture bar of foo is
begin
process is
variable x : my_int;
begin
x := i; -- OK
end process;
process is
variable x : my_int;
begin
-- Cannot read output
x := o;
end process;
process is
begin
o <= 24; -- OK
end process;
process is
begin
-- Cannot assign input
i <= 23;
end process;
end architecture;
-------------------------------------------------------------------------------
entity top is generic (str : string := "boo");
end entity;
use work.foo_pkg.all;
architecture test of top is
component foo is
port (
o : out my_int;
i : in my_int );
end component;
type int_vec is array (integer range <>) of integer;
component bar is
port (
i : in int_vec(1 to 10);
o : out int_vec(1 to 2) );
end component;
signal x, y : my_int;
begin
foo1: entity work.foo -- OK
port map (
o => x,
i => y );
foo2: entity work.foo -- OK
port map ( x, y );
foo3: entity work.foo
; -- Missing i association
foo4: entity work.foo -- Two associations for i
port map ( i => x, i => y,
o => x );
foo5: entity work.foo -- Too many ports
port map ( x, y, x, y );
foo6: entity work.foo -- No port cake
port map ( cake => 4 );
bad1: entity work.bad; -- No such entity
open1: entity work.foo -- OK
port map (
i => x,
o => open );
open2: entity work.foo -- Cannot use OPEN with input
port map (
i => open,
o => open );
foo7: foo -- OK
port map (
o => x,
i => y );
foo8: component foo -- OK
port map (
o => x,
i => y );
bad2: component x -- Not component
port map (
a => 1,
b => 2 );
b1: block is
signal x : int_vec(1 to 10);
signal y : int_vec(1 to 2);
signal k : integer;
begin
bar1: bar -- OK
port map (
o(1 to 10) => x(1 to 10),
i(1 to 2) => y(1 to 2) );
bar2: bar -- OK
port map (
o(1 to 4) => x(1 to 4),
o(5 to 10) => x(5 to 10),
i(1 to 2) => y(1 to 2) );
bar3: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to 10) => x(3 to 10),
i => y );
bar4: bar
port map (
o(1) => x(1),
o(2) => x(k), -- Error
o(3 to 10) => x(3 to 10),
i => y );
bar5: bar
port map (
o(1) => x(1),
o(q) => x(2), -- Error
o(3 to 10) => x(3 to 10),
i => y );
bar6: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to u) => x(3 to 10), -- Error
i => y );
bar7: bar
port map (
o(k) => x(1), -- Error
o(2) => x(2),
o(3 to 10) => x(3 to 10),
i => y );
bar8: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to k) => x(3 to 10), -- Error
i => y );
end block;
foo9: foo -- Error
port map (
o => x,
i => hello(5) );
foo10: foo
port map (
i => y ); -- OK
end architecture;
-------------------------------------------------------------------------------
architecture other of top is
type int_vec is array (integer range <>) of integer;
component comp1 is
port (
a : in integer := 5;
o : out int_vec );
end component;
signal s : int_vec(1 to 3);
begin
c1: component comp1 -- OK
port map (
a => open,
o => s );
c2: component comp1
port map (
a => 5,
o => open ); -- Error
c3: component comp1
port map (
a => 1.0, -- Error
o => s );
end architecture;
-------------------------------------------------------------------------------
architecture conv of top is
type int_vec1 is array (integer range <>) of integer;
type int_vec2 is array (integer range <>) of integer;
type my_int1 is range 0 to 1;
component comp1 is
port (
i : in int_vec1(1 to 3);
n : in my_int1 := 5;
o : out int_vec2(1 to 3) );
end component;
component comp2 is
port (
i : in int_vec1 );
end component;
component comp3 is
port (
b : out bit );
end component;
component comp4 is
port (
b : inout bit );
end component;
function func1(x : in bit) return my_int1;
function func2(x : in bit; y : in integer := 5) return my_int1;
function func3(x : in bit) return integer;
function func4(x : in integer) return bit;
signal x : int_vec1(1 to 3);
signal y : int_vec2(1 to 3);
signal z : bit;
signal i : integer;
begin
c1: component comp1
port map ( i => int_vec1(y) ); -- OK
c2: component comp2
port map ( i => int_vec1(y) ); -- Error
c3: component comp1
port map ( i => x,
n => func1(z) ); -- OK
c4: component comp1
port map ( i => x,
n => func2(z) ); -- Error
c6: component comp1
port map ( i => int_vec1(y),
o => int_vec2(x) ); -- Error
c7: component comp3
port map ( func3(b) => i ); -- OK
c8: component comp1
port map ( i => (1, 1, 1),
int_vec1(o) => x ); -- OK
c9: component comp1
port map ( int_vec2(i) => y, -- Error
int_vec1(o) => x );
c10: component comp3
port map ( func3(b) => open ); -- Error
c11: component comp4
port map ( func3(b) => func4(i) ); -- OK
end architecture;
entity ent_with_vec is
port ( x : in bit_vector(3 downto 0);
y : out bit_vector(3 downto 0) );
end entity;
architecture test of ent_with_vec is
begin
x(1) <= '0'; -- Error
y(1) <= y(0); -- Error
end architecture;
-------------------------------------------------------------------------------
architecture other2 of top is
procedure assign(x : out integer) is
begin
x := 5;
end procedure;
procedure assign_and_check(x : inout integer) is
begin
assign(x); -- OK
assert x = 5;
end procedure;
procedure bad(x : in integer) is
begin
assign(x);
end procedure;
begin
end architecture;
-------------------------------------------------------------------------------
architecture actual_func of top is
component comp is
port (
i : in integer );
end component;
signal s : integer;
function "not"(x : integer) return integer;
begin
c1: component comp
port map (
i => "not"(s) ); -- OK
c2: component comp
port map (
i => not s ); -- Error, not treated as conversion func
end architecture;
|
gpl-3.0
|
f858c2e2623c0f6db0c26eb7ce31f771
| 0.382437 | 4.073679 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_mux0.vhd
| 2 | 5,660 |
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: lpm_mux0.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_mux0 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_mux0;
ARCHITECTURE SYN OF lpm_mux0 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 8 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (8 DOWNTO 0);
BEGIN
sub_wire5 <= data0x(8 DOWNTO 0);
sub_wire4 <= data1x(8 DOWNTO 0);
sub_wire3 <= data2x(8 DOWNTO 0);
result <= sub_wire0(8 DOWNTO 0);
sub_wire1 <= data3x(8 DOWNTO 0);
sub_wire2(3, 0) <= sub_wire1(0);
sub_wire2(3, 1) <= sub_wire1(1);
sub_wire2(3, 2) <= sub_wire1(2);
sub_wire2(3, 3) <= sub_wire1(3);
sub_wire2(3, 4) <= sub_wire1(4);
sub_wire2(3, 5) <= sub_wire1(5);
sub_wire2(3, 6) <= sub_wire1(6);
sub_wire2(3, 7) <= sub_wire1(7);
sub_wire2(3, 8) <= sub_wire1(8);
sub_wire2(2, 0) <= sub_wire3(0);
sub_wire2(2, 1) <= sub_wire3(1);
sub_wire2(2, 2) <= sub_wire3(2);
sub_wire2(2, 3) <= sub_wire3(3);
sub_wire2(2, 4) <= sub_wire3(4);
sub_wire2(2, 5) <= sub_wire3(5);
sub_wire2(2, 6) <= sub_wire3(6);
sub_wire2(2, 7) <= sub_wire3(7);
sub_wire2(2, 8) <= sub_wire3(8);
sub_wire2(1, 0) <= sub_wire4(0);
sub_wire2(1, 1) <= sub_wire4(1);
sub_wire2(1, 2) <= sub_wire4(2);
sub_wire2(1, 3) <= sub_wire4(3);
sub_wire2(1, 4) <= sub_wire4(4);
sub_wire2(1, 5) <= sub_wire4(5);
sub_wire2(1, 6) <= sub_wire4(6);
sub_wire2(1, 7) <= sub_wire4(7);
sub_wire2(1, 8) <= sub_wire4(8);
sub_wire2(0, 0) <= sub_wire5(0);
sub_wire2(0, 1) <= sub_wire5(1);
sub_wire2(0, 2) <= sub_wire5(2);
sub_wire2(0, 3) <= sub_wire5(3);
sub_wire2(0, 4) <= sub_wire5(4);
sub_wire2(0, 5) <= sub_wire5(5);
sub_wire2(0, 6) <= sub_wire5(6);
sub_wire2(0, 7) <= sub_wire5(7);
sub_wire2(0, 8) <= sub_wire5(8);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 4,
lpm_type => "LPM_MUX",
lpm_width => 9,
lpm_widths => 2
)
PORT MAP (
data => sub_wire2,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
-- Retrieval info: USED_PORT: data0x 0 0 9 0 INPUT NODEFVAL "data0x[8..0]"
-- Retrieval info: USED_PORT: data1x 0 0 9 0 INPUT NODEFVAL "data1x[8..0]"
-- Retrieval info: USED_PORT: data2x 0 0 9 0 INPUT NODEFVAL "data2x[8..0]"
-- Retrieval info: USED_PORT: data3x 0 0 9 0 INPUT NODEFVAL "data3x[8..0]"
-- Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
-- Retrieval info: CONNECT: @data 1 0 9 0 data0x 0 0 9 0
-- Retrieval info: CONNECT: @data 1 1 9 0 data1x 0 0 9 0
-- Retrieval info: CONNECT: @data 1 2 9 0 data2x 0 0 9 0
-- Retrieval info: CONNECT: @data 1 3 9 0 data3x 0 0 9 0
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
-- Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
f0139605168045eca0356e4bfc4931a7
| 0.610601 | 2.827173 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_add_sub0.vhd
| 1 | 4,698 |
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_ADD_SUB
-- ============================================================
-- File Name: lpm_add_sub0.vhd
-- Megafunction Name(s):
-- LPM_ADD_SUB
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_add_sub0;
ARCHITECTURE SYN OF lpm_add_sub0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
LPM_ADD_SUB_component : LPM_ADD_SUB
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_representation => "SIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "3"
-- Retrieval info: PRIVATE: Function NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "1"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
ace22a0608459430fbb642de7f9ccaee
| 0.656875 | 3.613846 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/Hazard_Detector.vhd
| 2 | 27,703 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:38:59 11/23/2013
-- Design Name:
-- Module Name: Hazard_Detector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Hazard_Detector is
Port ( STALL_OR_NOT_FU : in STD_LOGIC := STALL_NO;
CUR_INST_CODE : in STD_LOGIC_VECTOR (4 downto 0) := NOP_INST(15 downto 11);
CUR_INST_RS : in STD_LOGIC_VECTOR (2 downto 0) := NOP_INST(10 downto 8);
CUR_INST_RT : in STD_LOGIC_VECTOR (2 downto 0) := NOP_INST(7 downto 5);
CUR_INST_RD : in STD_LOGIC_VECTOR (2 downto 0) := NOP_INST(4 downto 2);
CUR_INST_FUNC : in STD_LOGIC_VECTOR (1 downto 0):= NOP_INST(1 downto 0);
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
LAST_LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
LAST_LAST_DM_VISIT_ADDR : in STD_LOGIC_VECTOR (15 downto 0) := HIGH_RESIST;
CUR_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
CUR_DM_WRITE_DATA_SRC : in STD_LOGIC_VECTOR(1 downto 0) := WRITE_DM_DATA_SRC_Z;
JUMP_OR_NOT : in STD_LOGIC := JUMP_FALSE;
WRITE_PC_OR_NOT : out STD_LOGIC := WRITE_PC_YES;
NEW_PC_SRC_SELEC : out STD_LOGIC_VECTOR (1 downto 0) := NEW_PC_SRC_SELEC_PC_ADD_ONE;
WRITE_IR_OR_NOT : out STD_LOGIC := WRITE_IR_YES;
WRITE_IR_SRC_SELEC : out STD_LOGIC := WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP : out STD_LOGIC := COMMAND_ORIGIN;
DM_DATA_RESULT_SELEC : out STD_LOGIC := DM_DATA_RESULT_DM ;
IM_ADDR_SELEC : out STD_LOGIC := IM_ADDR_PC;
IM_DATA_SELEC : out STD_LOGIC := IM_DATA_Z;
IM_READ_WRITE_SELEC : out STD_LOGIC_VECTOR(1 downto 0) := MEM_READ
);
end Hazard_Detector;
architecture Behavioral of Hazard_Detector is
signal never_used_pin : std_logic;
begin
never_used_pin <= STALL_OR_NOT_FU;
process (CUR_INST_CODE, CUR_INST_RS, CUR_INST_RT, CUR_INST_RD, CUR_INST_FUNC,
LAST_WRITE_REGS_OR_NOT, LAST_WRITE_REGS_TARGET, LAST_VISIT_DM_OR_NOT,
LAST_LAST_WRITE_REGS_OR_NOT, LAST_LAST_WRITE_REGS_TARGET,
LAST_LAST_VISIT_DM_OR_NOT, LAST_LAST_DM_VISIT_ADDR, CUR_DM_READ_WRITE, CUR_DM_WRITE_DATA_SRC, JUMP_OR_NOT)
variable inst_rd_func : std_logic_vector(4 downto 0);
variable stall_or_not : boolean := False;
variable write_dm_or_not : boolean := False;
variable write_data_a_flag : boolean := False;
variable write_data_b_flag : boolean := False;
variable write_a_flag : boolean := False;
variable write_b_flag : boolean := False;
variable a_conflict_flag : boolean := False;
variable b_conflict_flag : boolean := False;
begin
inst_rd_func(4 downto 2) := CUR_INST_RD;
inst_rd_func(1 downto 0) := CUR_INST_FUNC;
write_dm_or_not := (CUR_DM_READ_WRITE = MEM_WRITE) and (CUR_DM_READ_WRITE = MEM_WRITE);
write_data_a_flag := CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_A;
write_data_b_flag := CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_B;
write_a_flag := (LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS);
write_b_flag := (LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RT) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RT);
a_conflict_flag := write_data_a_flag and write_a_flag;
b_conflict_flag := write_data_b_flag and write_b_flag;
stall_or_not := write_dm_or_not and (a_conflict_flag or b_conflict_flag);
-- if forward unit call for stall, stop PC, IR, set CMD NOP
-- if (STALL_OR_NOT_FU = STALL_YES) then
-- WRITE_PC_OR_NOT <= WRITE_PC_NO ;
-- NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
-- WRITE_IR_OR_NOT <= WRITE_IR_NO ;
-- WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN ;
-- COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- 暂且无谓暂停也无所谓
if (LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and
(LAST_WRITE_REGS_TARGET = CUR_INST_RS or LAST_WRITE_REGS_TARGET = CUR_INST_RT) and
LAST_VISIT_DM_OR_NOT = MEM_READ) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN ;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- SW型指令要直接用到A或B的值，有可能存在数据冲突，若有，暂停
elsif (CUR_DM_READ_WRITE = MEM_WRITE and
((CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_A and
((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)))
or (CUR_DM_WRITE_DATA_SRC = WRITE_DM_DATA_SRC_B and
((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RT) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RT))))) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN ;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
case CUR_INST_CODE is
-- B inst, must jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
when INST_CODE_B =>
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
when INST_CODE_BEQZ =>
-- BEQZ inst, if has data conflict, stall, stop PC, stop IR, set CMD to NOP
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- no conflict, if jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
elsif (JUMP_OR_NOT = JUMP_TRUE) then
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
end if;
when INST_CODE_BNEZ =>
-- BNEZ inst, if has data conflict, stall, stop PC, stop IR, set CMD to NOP
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
-- no conflict, if jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
elsif (JUMP_OR_NOT = JUMP_TRUE) then
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when INST_CODE_ADDSP_BTEQZ_MTSP =>
if (CUR_INST_RS = INST_RS_BTEQZ ) then
-- BTEQZ inst, if jump, set PC to PC + IMM, set IR to NOP, set CMD to NOP
if (JUMP_OR_NOT = JUMP_TRUE) then
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_IMM ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when INST_CODE_AND_TO_SLT =>
if (inst_rd_func = INST_RD_FUNC_JALR_JR_MFPC ) then
case CUR_INST_RT is
-- JALR inst, jump, set PC to reg A, set IR to NOP, keep CMD as origin
when INST_RT_JALR =>
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
-- JR inst, jump, set PC to reg A, set IR to NOP, keep CMD as origin
when INST_RT_JR =>
if ((LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_WRITE_REGS_TARGET = CUR_INST_RS) or
(LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES and LAST_LAST_WRITE_REGS_TARGET = CUR_INST_RS)) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_NO ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_REG_A ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_NOP ;
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when others =>
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end case;
else
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end if;
when others =>
-- load user's program, just stop PC
if ((LAST_LAST_VISIT_DM_OR_NOT = MEM_READ or LAST_LAST_VISIT_DM_OR_NOT = MEM_WRITE) and
CONV_INTEGER(LAST_LAST_DM_VISIT_ADDR) < INST_DATA_MEM_ADDR_EDGE) then
WRITE_PC_OR_NOT <= WRITE_PC_NO ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_NOP;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_IM ;
IM_ADDR_SELEC <= IM_ADDR_ALU_RESULT;
IM_DATA_SELEC <= IM_DATA_ALU_RESULT;
IM_READ_WRITE_SELEC <= LAST_LAST_VISIT_DM_OR_NOT;
-- no conflict keep all as origin
else
WRITE_PC_OR_NOT <= WRITE_PC_YES ;
NEW_PC_SRC_SELEC <= NEW_PC_SRC_SELEC_PC_ADD_ONE ;
WRITE_IR_OR_NOT <= WRITE_IR_YES ;
WRITE_IR_SRC_SELEC <= WRITE_IR_SRC_SELEC_ORIGIN;
COMMAND_ORIGIN_OR_NOP <= COMMAND_ORIGIN ;
DM_DATA_RESULT_SELEC <= DM_DATA_RESULT_DM ;
IM_ADDR_SELEC <= IM_ADDR_PC;
IM_DATA_SELEC <= IM_DATA_Z;
IM_READ_WRITE_SELEC <= MEM_READ;
end if;
end case;
end if;
end process;
end Behavioral;
|
apache-2.0
|
1228b35643c7d1736a034e1868691c3d
| 0.599732 | 2.853057 | false | false | false | false |
mitchsm/nvc
|
test/regress/shared2.vhd
| 5 | 617 |
entity shared2 is
end entity;
architecture test of shared2 is
type ram_t is array (integer range <>) of bit_vector(7 downto 0);
shared variable ram : ram_t(1 to 8) := (
1 => X"11",
2 => X"22",
3 => X"33",
others => X"00" );
begin
update: process is
begin
wait for 1 ns;
ram(5) := X"aa";
wait;
end process;
check: process is
begin
assert ram(1) = X"11";
assert ram(2) = X"22";
assert ram(5) = X"00";
wait for 5 ns;
assert ram(5) = X"aa";
wait;
end process;
end architecture;
|
gpl-3.0
|
77f01da5f6ffac514a4b34963fb33d4f
| 0.50081 | 3.371585 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_get_0_if_0/sim/zc702_get_0_if_0.vhd
| 1 | 50,744 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axis_accelerator_adapter:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axis_accelerator_adapter_v2_1_6;
USE axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter;
ENTITY zc702_get_0_if_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_vld : IN STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END zc702_get_0_if_0;
ARCHITECTURE zc702_get_0_if_0_arch OF zc702_get_0_if_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_get_0_if_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_accelerator_adapter IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_AP_ADAPTER_ID : INTEGER;
C_N_INPUT_ARGS : INTEGER;
C_N_OUTPUT_ARGS : INTEGER;
C_S_AXIS_TDATA_WIDTH : INTEGER;
C_S_AXIS_TUSER_WIDTH : INTEGER;
C_S_AXIS_TID_WIDTH : INTEGER;
C_S_AXIS_TDEST_WIDTH : INTEGER;
C_AP_IARG_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_IARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_IARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_0_DWIDTH : INTEGER;
C_AP_IARG_1_DWIDTH : INTEGER;
C_AP_IARG_2_DWIDTH : INTEGER;
C_AP_IARG_3_DWIDTH : INTEGER;
C_AP_IARG_4_DWIDTH : INTEGER;
C_AP_IARG_5_DWIDTH : INTEGER;
C_AP_IARG_6_DWIDTH : INTEGER;
C_AP_IARG_7_DWIDTH : INTEGER;
C_M_AXIS_TDATA_WIDTH : INTEGER;
C_M_AXIS_TUSER_WIDTH : INTEGER;
C_M_AXIS_TID_WIDTH : INTEGER;
C_M_AXIS_TDEST_WIDTH : INTEGER;
C_AP_OARG_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_OARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_OARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_0_DWIDTH : INTEGER;
C_AP_OARG_1_DWIDTH : INTEGER;
C_AP_OARG_2_DWIDTH : INTEGER;
C_AP_OARG_3_DWIDTH : INTEGER;
C_AP_OARG_4_DWIDTH : INTEGER;
C_AP_OARG_5_DWIDTH : INTEGER;
C_AP_OARG_6_DWIDTH : INTEGER;
C_AP_OARG_7_DWIDTH : INTEGER;
C_N_INOUT_SCALARS : INTEGER;
C_N_INPUT_SCALARS : INTEGER;
C_INPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_INPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_OUTPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_AP_ISCALAR_DOUT_WIDTH : INTEGER;
C_AP_ISCALAR_IO_DOUT_WIDTH : INTEGER;
C_INPUT_SCALAR_0_WIDTH : INTEGER;
C_INPUT_SCALAR_1_WIDTH : INTEGER;
C_INPUT_SCALAR_2_WIDTH : INTEGER;
C_INPUT_SCALAR_3_WIDTH : INTEGER;
C_INPUT_SCALAR_4_WIDTH : INTEGER;
C_INPUT_SCALAR_5_WIDTH : INTEGER;
C_INPUT_SCALAR_6_WIDTH : INTEGER;
C_INPUT_SCALAR_7_WIDTH : INTEGER;
C_INPUT_SCALAR_8_WIDTH : INTEGER;
C_INPUT_SCALAR_9_WIDTH : INTEGER;
C_INPUT_SCALAR_10_WIDTH : INTEGER;
C_INPUT_SCALAR_11_WIDTH : INTEGER;
C_INPUT_SCALAR_12_WIDTH : INTEGER;
C_INPUT_SCALAR_13_WIDTH : INTEGER;
C_INPUT_SCALAR_14_WIDTH : INTEGER;
C_INPUT_SCALAR_15_WIDTH : INTEGER;
C_OUTPUT_SCALAR_0_WIDTH : INTEGER;
C_OUTPUT_SCALAR_1_WIDTH : INTEGER;
C_OUTPUT_SCALAR_2_WIDTH : INTEGER;
C_OUTPUT_SCALAR_3_WIDTH : INTEGER;
C_OUTPUT_SCALAR_4_WIDTH : INTEGER;
C_OUTPUT_SCALAR_5_WIDTH : INTEGER;
C_OUTPUT_SCALAR_6_WIDTH : INTEGER;
C_OUTPUT_SCALAR_7_WIDTH : INTEGER;
C_OUTPUT_SCALAR_8_WIDTH : INTEGER;
C_OUTPUT_SCALAR_9_WIDTH : INTEGER;
C_OUTPUT_SCALAR_10_WIDTH : INTEGER;
C_OUTPUT_SCALAR_11_WIDTH : INTEGER;
C_OUTPUT_SCALAR_12_WIDTH : INTEGER;
C_OUTPUT_SCALAR_13_WIDTH : INTEGER;
C_OUTPUT_SCALAR_14_WIDTH : INTEGER;
C_OUTPUT_SCALAR_15_WIDTH : INTEGER;
C_N_OUTPUT_SCALARS : INTEGER;
C_OUTPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_AP_OSCALAR_DIN_WIDTH : INTEGER;
C_AP_OSCALAR_IO_DIN_WIDTH : INTEGER;
C_ENABLE_STREAM_CLK : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_S_AXIS_HAS_TSTRB : INTEGER;
C_S_AXIS_HAS_TKEEP : INTEGER;
C_NONE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_aresetn : IN STD_LOGIC;
s_axis_0_aclk : IN STD_LOGIC;
s_axis_0_aresetn : IN STD_LOGIC;
s_axis_0_tvalid : IN STD_LOGIC;
s_axis_0_tready : OUT STD_LOGIC;
s_axis_0_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_0_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tlast : IN STD_LOGIC;
s_axis_0_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_aclk : IN STD_LOGIC;
s_axis_1_aresetn : IN STD_LOGIC;
s_axis_1_tvalid : IN STD_LOGIC;
s_axis_1_tready : OUT STD_LOGIC;
s_axis_1_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_1_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tlast : IN STD_LOGIC;
s_axis_1_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_aclk : IN STD_LOGIC;
s_axis_2_aresetn : IN STD_LOGIC;
s_axis_2_tvalid : IN STD_LOGIC;
s_axis_2_tready : OUT STD_LOGIC;
s_axis_2_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_2_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tlast : IN STD_LOGIC;
s_axis_2_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_aclk : IN STD_LOGIC;
s_axis_3_aresetn : IN STD_LOGIC;
s_axis_3_tvalid : IN STD_LOGIC;
s_axis_3_tready : OUT STD_LOGIC;
s_axis_3_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_3_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tlast : IN STD_LOGIC;
s_axis_3_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_aclk : IN STD_LOGIC;
s_axis_4_aresetn : IN STD_LOGIC;
s_axis_4_tvalid : IN STD_LOGIC;
s_axis_4_tready : OUT STD_LOGIC;
s_axis_4_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_4_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tlast : IN STD_LOGIC;
s_axis_4_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_aclk : IN STD_LOGIC;
s_axis_5_aresetn : IN STD_LOGIC;
s_axis_5_tvalid : IN STD_LOGIC;
s_axis_5_tready : OUT STD_LOGIC;
s_axis_5_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_5_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tlast : IN STD_LOGIC;
s_axis_5_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_aclk : IN STD_LOGIC;
s_axis_6_aresetn : IN STD_LOGIC;
s_axis_6_tvalid : IN STD_LOGIC;
s_axis_6_tready : OUT STD_LOGIC;
s_axis_6_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_6_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tlast : IN STD_LOGIC;
s_axis_6_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_aclk : IN STD_LOGIC;
s_axis_7_aresetn : IN STD_LOGIC;
s_axis_7_tvalid : IN STD_LOGIC;
s_axis_7_tready : OUT STD_LOGIC;
s_axis_7_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_7_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tlast : IN STD_LOGIC;
s_axis_7_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_iarg_0_clk : IN STD_LOGIC;
ap_iarg_0_rst : IN STD_LOGIC;
ap_iarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_ce : IN STD_LOGIC;
ap_iarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_clk : IN STD_LOGIC;
ap_iarg_1_rst : IN STD_LOGIC;
ap_iarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_ce : IN STD_LOGIC;
ap_iarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_clk : IN STD_LOGIC;
ap_iarg_2_rst : IN STD_LOGIC;
ap_iarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_ce : IN STD_LOGIC;
ap_iarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_clk : IN STD_LOGIC;
ap_iarg_3_rst : IN STD_LOGIC;
ap_iarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_ce : IN STD_LOGIC;
ap_iarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_clk : IN STD_LOGIC;
ap_iarg_4_rst : IN STD_LOGIC;
ap_iarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_ce : IN STD_LOGIC;
ap_iarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_clk : IN STD_LOGIC;
ap_iarg_5_rst : IN STD_LOGIC;
ap_iarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_ce : IN STD_LOGIC;
ap_iarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_clk : IN STD_LOGIC;
ap_iarg_6_rst : IN STD_LOGIC;
ap_iarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_ce : IN STD_LOGIC;
ap_iarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_clk : IN STD_LOGIC;
ap_iarg_7_rst : IN STD_LOGIC;
ap_iarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_ce : IN STD_LOGIC;
ap_iarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_read : IN STD_LOGIC;
ap_fifo_iarg_0_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_1_read : IN STD_LOGIC;
ap_fifo_iarg_1_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_2_read : IN STD_LOGIC;
ap_fifo_iarg_2_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_3_read : IN STD_LOGIC;
ap_fifo_iarg_3_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_4_read : IN STD_LOGIC;
ap_fifo_iarg_4_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_5_read : IN STD_LOGIC;
ap_fifo_iarg_5_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_6_read : IN STD_LOGIC;
ap_fifo_iarg_6_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_7_read : IN STD_LOGIC;
ap_fifo_iarg_7_empty_n : OUT STD_LOGIC;
m_axis_aclk : IN STD_LOGIC;
m_axis_aresetn : IN STD_LOGIC;
m_axis_0_aclk : IN STD_LOGIC;
m_axis_0_aresetn : IN STD_LOGIC;
m_axis_0_tvalid : OUT STD_LOGIC;
m_axis_0_tready : IN STD_LOGIC;
m_axis_0_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_0_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tlast : OUT STD_LOGIC;
m_axis_0_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_aclk : IN STD_LOGIC;
m_axis_1_aresetn : IN STD_LOGIC;
m_axis_1_tvalid : OUT STD_LOGIC;
m_axis_1_tready : IN STD_LOGIC;
m_axis_1_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_1_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tlast : OUT STD_LOGIC;
m_axis_1_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_aclk : IN STD_LOGIC;
m_axis_2_aresetn : IN STD_LOGIC;
m_axis_2_tvalid : OUT STD_LOGIC;
m_axis_2_tready : IN STD_LOGIC;
m_axis_2_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_2_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tlast : OUT STD_LOGIC;
m_axis_2_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_aclk : IN STD_LOGIC;
m_axis_3_aresetn : IN STD_LOGIC;
m_axis_3_tvalid : OUT STD_LOGIC;
m_axis_3_tready : IN STD_LOGIC;
m_axis_3_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_3_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tlast : OUT STD_LOGIC;
m_axis_3_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_aclk : IN STD_LOGIC;
m_axis_4_aresetn : IN STD_LOGIC;
m_axis_4_tvalid : OUT STD_LOGIC;
m_axis_4_tready : IN STD_LOGIC;
m_axis_4_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_4_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tlast : OUT STD_LOGIC;
m_axis_4_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_aclk : IN STD_LOGIC;
m_axis_5_aresetn : IN STD_LOGIC;
m_axis_5_tvalid : OUT STD_LOGIC;
m_axis_5_tready : IN STD_LOGIC;
m_axis_5_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_5_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tlast : OUT STD_LOGIC;
m_axis_5_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_aclk : IN STD_LOGIC;
m_axis_6_aresetn : IN STD_LOGIC;
m_axis_6_tvalid : OUT STD_LOGIC;
m_axis_6_tready : IN STD_LOGIC;
m_axis_6_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_6_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tlast : OUT STD_LOGIC;
m_axis_6_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_aclk : IN STD_LOGIC;
m_axis_7_aresetn : IN STD_LOGIC;
m_axis_7_tvalid : OUT STD_LOGIC;
m_axis_7_tready : IN STD_LOGIC;
m_axis_7_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_7_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tlast : OUT STD_LOGIC;
m_axis_7_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_oarg_0_clk : IN STD_LOGIC;
ap_oarg_0_rst : IN STD_LOGIC;
ap_oarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_ce : IN STD_LOGIC;
ap_oarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_clk : IN STD_LOGIC;
ap_oarg_1_rst : IN STD_LOGIC;
ap_oarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_ce : IN STD_LOGIC;
ap_oarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_clk : IN STD_LOGIC;
ap_oarg_2_rst : IN STD_LOGIC;
ap_oarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_ce : IN STD_LOGIC;
ap_oarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_clk : IN STD_LOGIC;
ap_oarg_3_rst : IN STD_LOGIC;
ap_oarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_ce : IN STD_LOGIC;
ap_oarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_clk : IN STD_LOGIC;
ap_oarg_4_rst : IN STD_LOGIC;
ap_oarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_ce : IN STD_LOGIC;
ap_oarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_clk : IN STD_LOGIC;
ap_oarg_5_rst : IN STD_LOGIC;
ap_oarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_ce : IN STD_LOGIC;
ap_oarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_clk : IN STD_LOGIC;
ap_oarg_6_rst : IN STD_LOGIC;
ap_oarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_ce : IN STD_LOGIC;
ap_oarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_clk : IN STD_LOGIC;
ap_oarg_7_rst : IN STD_LOGIC;
ap_oarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_ce : IN STD_LOGIC;
ap_oarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_write : IN STD_LOGIC;
ap_fifo_oarg_0_full_n : OUT STD_LOGIC;
ap_fifo_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_1_write : IN STD_LOGIC;
ap_fifo_oarg_1_full_n : OUT STD_LOGIC;
ap_fifo_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_2_write : IN STD_LOGIC;
ap_fifo_oarg_2_full_n : OUT STD_LOGIC;
ap_fifo_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_3_write : IN STD_LOGIC;
ap_fifo_oarg_3_full_n : OUT STD_LOGIC;
ap_fifo_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_4_write : IN STD_LOGIC;
ap_fifo_oarg_4_full_n : OUT STD_LOGIC;
ap_fifo_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_5_write : IN STD_LOGIC;
ap_fifo_oarg_5_full_n : OUT STD_LOGIC;
ap_fifo_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_6_write : IN STD_LOGIC;
ap_fifo_oarg_6_full_n : OUT STD_LOGIC;
ap_fifo_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_7_write : IN STD_LOGIC;
ap_fifo_oarg_7_full_n : OUT STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_8_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_9_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_10_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_11_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_12_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_13_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_14_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_15_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_8_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_9_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_10_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_11_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_12_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_13_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_14_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_15_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_vld : IN STD_LOGIC;
ap_oscalar_1_vld : IN STD_LOGIC;
ap_oscalar_2_vld : IN STD_LOGIC;
ap_oscalar_3_vld : IN STD_LOGIC;
ap_oscalar_4_vld : IN STD_LOGIC;
ap_oscalar_5_vld : IN STD_LOGIC;
ap_oscalar_6_vld : IN STD_LOGIC;
ap_oscalar_7_vld : IN STD_LOGIC;
ap_oscalar_8_vld : IN STD_LOGIC;
ap_oscalar_9_vld : IN STD_LOGIC;
ap_oscalar_10_vld : IN STD_LOGIC;
ap_oscalar_11_vld : IN STD_LOGIC;
ap_oscalar_12_vld : IN STD_LOGIC;
ap_oscalar_13_vld : IN STD_LOGIC;
ap_oscalar_14_vld : IN STD_LOGIC;
ap_oscalar_15_vld : IN STD_LOGIC;
ap_oscalar_0_ack : OUT STD_LOGIC;
ap_oscalar_1_ack : OUT STD_LOGIC;
ap_oscalar_2_ack : OUT STD_LOGIC;
ap_oscalar_3_ack : OUT STD_LOGIC;
ap_oscalar_4_ack : OUT STD_LOGIC;
ap_oscalar_5_ack : OUT STD_LOGIC;
ap_oscalar_6_ack : OUT STD_LOGIC;
ap_oscalar_7_ack : OUT STD_LOGIC;
ap_oscalar_8_ack : OUT STD_LOGIC;
ap_oscalar_9_ack : OUT STD_LOGIC;
ap_oscalar_10_ack : OUT STD_LOGIC;
ap_oscalar_11_ack : OUT STD_LOGIC;
ap_oscalar_12_ack : OUT STD_LOGIC;
ap_oscalar_13_ack : OUT STD_LOGIC;
ap_oscalar_14_ack : OUT STD_LOGIC;
ap_oscalar_15_ack : OUT STD_LOGIC;
ap_iscalar_0_ack : IN STD_LOGIC;
ap_iscalar_1_ack : IN STD_LOGIC;
ap_iscalar_2_ack : IN STD_LOGIC;
ap_iscalar_3_ack : IN STD_LOGIC;
ap_iscalar_4_ack : IN STD_LOGIC;
ap_iscalar_5_ack : IN STD_LOGIC;
ap_iscalar_6_ack : IN STD_LOGIC;
ap_iscalar_7_ack : IN STD_LOGIC;
ap_iscalar_8_ack : IN STD_LOGIC;
ap_iscalar_9_ack : IN STD_LOGIC;
ap_iscalar_10_ack : IN STD_LOGIC;
ap_iscalar_11_ack : IN STD_LOGIC;
ap_iscalar_12_ack : IN STD_LOGIC;
ap_iscalar_13_ack : IN STD_LOGIC;
ap_iscalar_14_ack : IN STD_LOGIC;
ap_iscalar_15_ack : IN STD_LOGIC;
ap_iscalar_0_vld : OUT STD_LOGIC;
ap_iscalar_1_vld : OUT STD_LOGIC;
ap_iscalar_2_vld : OUT STD_LOGIC;
ap_iscalar_3_vld : OUT STD_LOGIC;
ap_iscalar_4_vld : OUT STD_LOGIC;
ap_iscalar_5_vld : OUT STD_LOGIC;
ap_iscalar_6_vld : OUT STD_LOGIC;
ap_iscalar_7_vld : OUT STD_LOGIC;
ap_iscalar_8_vld : OUT STD_LOGIC;
ap_iscalar_9_vld : OUT STD_LOGIC;
ap_iscalar_10_vld : OUT STD_LOGIC;
ap_iscalar_11_vld : OUT STD_LOGIC;
ap_iscalar_12_vld : OUT STD_LOGIC;
ap_iscalar_13_vld : OUT STD_LOGIC;
ap_iscalar_14_vld : OUT STD_LOGIC;
ap_iscalar_15_vld : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT axis_accelerator_adapter;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL start";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done";
ATTRIBUTE X_INTERFACE_INFO OF ap_continue: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL continue";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL idle";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axis_accelerator_adapter
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_AP_ADAPTER_ID => 1,
C_N_INPUT_ARGS => 0,
C_N_OUTPUT_ARGS => 0,
C_S_AXIS_TDATA_WIDTH => 64,
C_S_AXIS_TUSER_WIDTH => 8,
C_S_AXIS_TID_WIDTH => 4,
C_S_AXIS_TDEST_WIDTH => 4,
C_AP_IARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_IARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_IARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_IARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_0_DWIDTH => 32,
C_AP_IARG_1_DWIDTH => 32,
C_AP_IARG_2_DWIDTH => 32,
C_AP_IARG_3_DWIDTH => 32,
C_AP_IARG_4_DWIDTH => 32,
C_AP_IARG_5_DWIDTH => 32,
C_AP_IARG_6_DWIDTH => 32,
C_AP_IARG_7_DWIDTH => 32,
C_M_AXIS_TDATA_WIDTH => 64,
C_M_AXIS_TUSER_WIDTH => 8,
C_M_AXIS_TID_WIDTH => 4,
C_M_AXIS_TDEST_WIDTH => 4,
C_AP_OARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_OARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_OARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_DIM => X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008",
C_AP_OARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_OARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_0_DWIDTH => 32,
C_AP_OARG_1_DWIDTH => 32,
C_AP_OARG_2_DWIDTH => 32,
C_AP_OARG_3_DWIDTH => 32,
C_AP_OARG_4_DWIDTH => 32,
C_AP_OARG_5_DWIDTH => 32,
C_AP_OARG_6_DWIDTH => 32,
C_AP_OARG_7_DWIDTH => 32,
C_N_INOUT_SCALARS => 0,
C_N_INPUT_SCALARS => 2,
C_INPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_INPUT_SCALAR_MODE => X"0000000000000000",
C_OUTPUT_SCALAR_MODE => X"0000000000000010",
C_AP_ISCALAR_DOUT_WIDTH => 64,
C_AP_ISCALAR_IO_DOUT_WIDTH => 32,
C_INPUT_SCALAR_0_WIDTH => 32,
C_INPUT_SCALAR_1_WIDTH => 32,
C_INPUT_SCALAR_2_WIDTH => 32,
C_INPUT_SCALAR_3_WIDTH => 32,
C_INPUT_SCALAR_4_WIDTH => 32,
C_INPUT_SCALAR_5_WIDTH => 32,
C_INPUT_SCALAR_6_WIDTH => 32,
C_INPUT_SCALAR_7_WIDTH => 32,
C_INPUT_SCALAR_8_WIDTH => 32,
C_INPUT_SCALAR_9_WIDTH => 32,
C_INPUT_SCALAR_10_WIDTH => 32,
C_INPUT_SCALAR_11_WIDTH => 32,
C_INPUT_SCALAR_12_WIDTH => 32,
C_INPUT_SCALAR_13_WIDTH => 32,
C_INPUT_SCALAR_14_WIDTH => 32,
C_INPUT_SCALAR_15_WIDTH => 32,
C_OUTPUT_SCALAR_0_WIDTH => 32,
C_OUTPUT_SCALAR_1_WIDTH => 32,
C_OUTPUT_SCALAR_2_WIDTH => 32,
C_OUTPUT_SCALAR_3_WIDTH => 32,
C_OUTPUT_SCALAR_4_WIDTH => 32,
C_OUTPUT_SCALAR_5_WIDTH => 32,
C_OUTPUT_SCALAR_6_WIDTH => 32,
C_OUTPUT_SCALAR_7_WIDTH => 32,
C_OUTPUT_SCALAR_8_WIDTH => 32,
C_OUTPUT_SCALAR_9_WIDTH => 32,
C_OUTPUT_SCALAR_10_WIDTH => 32,
C_OUTPUT_SCALAR_11_WIDTH => 32,
C_OUTPUT_SCALAR_12_WIDTH => 32,
C_OUTPUT_SCALAR_13_WIDTH => 32,
C_OUTPUT_SCALAR_14_WIDTH => 32,
C_OUTPUT_SCALAR_15_WIDTH => 32,
C_N_OUTPUT_SCALARS => 2,
C_OUTPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_AP_OSCALAR_DIN_WIDTH => 64,
C_AP_OSCALAR_IO_DIN_WIDTH => 32,
C_ENABLE_STREAM_CLK => 0,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_S_AXIS_HAS_TSTRB => 0,
C_S_AXIS_HAS_TKEEP => 0,
C_NONE => 2
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axis_aclk => '0',
s_axis_aresetn => '0',
s_axis_0_aclk => '0',
s_axis_0_aresetn => '0',
s_axis_0_tvalid => '0',
s_axis_0_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_0_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tlast => '0',
s_axis_0_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_aclk => '0',
s_axis_1_aresetn => '0',
s_axis_1_tvalid => '0',
s_axis_1_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_1_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tlast => '0',
s_axis_1_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_aclk => '0',
s_axis_2_aresetn => '0',
s_axis_2_tvalid => '0',
s_axis_2_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_2_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tlast => '0',
s_axis_2_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_aclk => '0',
s_axis_3_aresetn => '0',
s_axis_3_tvalid => '0',
s_axis_3_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_3_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tlast => '0',
s_axis_3_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_aclk => '0',
s_axis_4_aresetn => '0',
s_axis_4_tvalid => '0',
s_axis_4_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_4_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tlast => '0',
s_axis_4_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_aclk => '0',
s_axis_5_aresetn => '0',
s_axis_5_tvalid => '0',
s_axis_5_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_5_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tlast => '0',
s_axis_5_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_aclk => '0',
s_axis_6_aresetn => '0',
s_axis_6_tvalid => '0',
s_axis_6_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_6_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tlast => '0',
s_axis_6_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_aclk => '0',
s_axis_7_aresetn => '0',
s_axis_7_tvalid => '0',
s_axis_7_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_7_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tlast => '0',
s_axis_7_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ap_iarg_0_clk => '0',
ap_iarg_0_rst => '0',
ap_iarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_0_ce => '0',
ap_iarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_clk => '0',
ap_iarg_1_rst => '0',
ap_iarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_ce => '0',
ap_iarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_clk => '0',
ap_iarg_2_rst => '0',
ap_iarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_ce => '0',
ap_iarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_clk => '0',
ap_iarg_3_rst => '0',
ap_iarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_ce => '0',
ap_iarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_clk => '0',
ap_iarg_4_rst => '0',
ap_iarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_ce => '0',
ap_iarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_clk => '0',
ap_iarg_5_rst => '0',
ap_iarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_ce => '0',
ap_iarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_clk => '0',
ap_iarg_6_rst => '0',
ap_iarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_ce => '0',
ap_iarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_clk => '0',
ap_iarg_7_rst => '0',
ap_iarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_ce => '0',
ap_iarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_iarg_0_read => '0',
ap_fifo_iarg_1_read => '0',
ap_fifo_iarg_2_read => '0',
ap_fifo_iarg_3_read => '0',
ap_fifo_iarg_4_read => '0',
ap_fifo_iarg_5_read => '0',
ap_fifo_iarg_6_read => '0',
ap_fifo_iarg_7_read => '0',
m_axis_aclk => '0',
m_axis_aresetn => '0',
m_axis_0_aclk => '0',
m_axis_0_aresetn => '0',
m_axis_0_tready => '0',
m_axis_1_aclk => '0',
m_axis_1_aresetn => '0',
m_axis_1_tready => '0',
m_axis_2_aclk => '0',
m_axis_2_aresetn => '0',
m_axis_2_tready => '0',
m_axis_3_aclk => '0',
m_axis_3_aresetn => '0',
m_axis_3_tready => '0',
m_axis_4_aclk => '0',
m_axis_4_aresetn => '0',
m_axis_4_tready => '0',
m_axis_5_aclk => '0',
m_axis_5_aresetn => '0',
m_axis_5_tready => '0',
m_axis_6_aclk => '0',
m_axis_6_aresetn => '0',
m_axis_6_tready => '0',
m_axis_7_aclk => '0',
m_axis_7_aresetn => '0',
m_axis_7_tready => '0',
ap_oarg_0_clk => '0',
ap_oarg_0_rst => '0',
ap_oarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_0_ce => '0',
ap_oarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_clk => '0',
ap_oarg_1_rst => '0',
ap_oarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_ce => '0',
ap_oarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_clk => '0',
ap_oarg_2_rst => '0',
ap_oarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_ce => '0',
ap_oarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_clk => '0',
ap_oarg_3_rst => '0',
ap_oarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_ce => '0',
ap_oarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_clk => '0',
ap_oarg_4_rst => '0',
ap_oarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_ce => '0',
ap_oarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_clk => '0',
ap_oarg_5_rst => '0',
ap_oarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_ce => '0',
ap_oarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_clk => '0',
ap_oarg_6_rst => '0',
ap_oarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_ce => '0',
ap_oarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_clk => '0',
ap_oarg_7_rst => '0',
ap_oarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_ce => '0',
ap_oarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_write => '0',
ap_fifo_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_1_write => '0',
ap_fifo_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_2_write => '0',
ap_fifo_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_3_write => '0',
ap_fifo_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_4_write => '0',
ap_fifo_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_5_write => '0',
ap_fifo_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_6_write => '0',
ap_fifo_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_7_write => '0',
aclk => aclk,
aresetn => aresetn,
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_iscalar_0_dout => ap_iscalar_0_dout,
ap_iscalar_1_dout => ap_iscalar_1_dout,
ap_oscalar_0_din => ap_oscalar_0_din,
ap_oscalar_1_din => ap_oscalar_1_din,
ap_oscalar_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_8_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_9_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_10_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_11_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_12_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_13_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_14_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_15_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_0_vld => '0',
ap_oscalar_1_vld => ap_oscalar_1_vld,
ap_oscalar_2_vld => '0',
ap_oscalar_3_vld => '0',
ap_oscalar_4_vld => '0',
ap_oscalar_5_vld => '0',
ap_oscalar_6_vld => '0',
ap_oscalar_7_vld => '0',
ap_oscalar_8_vld => '0',
ap_oscalar_9_vld => '0',
ap_oscalar_10_vld => '0',
ap_oscalar_11_vld => '0',
ap_oscalar_12_vld => '0',
ap_oscalar_13_vld => '0',
ap_oscalar_14_vld => '0',
ap_oscalar_15_vld => '0',
ap_iscalar_0_ack => '0',
ap_iscalar_1_ack => '0',
ap_iscalar_2_ack => '0',
ap_iscalar_3_ack => '0',
ap_iscalar_4_ack => '0',
ap_iscalar_5_ack => '0',
ap_iscalar_6_ack => '0',
ap_iscalar_7_ack => '0',
ap_iscalar_8_ack => '0',
ap_iscalar_9_ack => '0',
ap_iscalar_10_ack => '0',
ap_iscalar_11_ack => '0',
ap_iscalar_12_ack => '0',
ap_iscalar_13_ack => '0',
ap_iscalar_14_ack => '0',
ap_iscalar_15_ack => '0',
interrupt => interrupt
);
END zc702_get_0_if_0_arch;
|
mit
|
360cefb788f188bc58191e653addbe07
| 0.616841 | 2.905468 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter6.vhd
| 1 | 4,449 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter6.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter6 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_counter6;
ARCHITECTURE SYN OF lpm_counter6 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 525,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 10
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "525"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "525"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter6.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter6.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter6.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter6.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
ce66c3f1ae7b3a5121f497a6460a87d6
| 0.652281 | 3.692116 | false | false | false | false |
mitchsm/nvc
|
test/group/issue73.vhd
| 5 | 540 |
entity issue73 is
end entity;
architecture test of issue73 is
type ma_t is array (1 downto 0) of bit_vector(3 downto 0);
signal x : ma_t; -- 0..7
signal y : ma_t; -- 8..15
begin
x(0)(1 downto 0) <= "00";
x(0)(3 downto 2) <= "11";
x(1)(0 downto 0) <= "0";
x(1)(3 downto 1) <= "101";
process (y) is
begin
for i in x'range loop
y(i)(1 downto 0) <= "00";
y(i)(3 downto 2) <= "11";
end loop;
end process;
end architecture;
|
gpl-3.0
|
b5dc60718faa49af671c605edd0dda3e
| 0.475926 | 3.121387 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/vhls/set/solution/syn/vhdl/set_gmem_m_axi.vhd
| 4 | 110,726 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity set_gmem_m_axi;
architecture behave of set_gmem_m_axi is
component set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_write;
component set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_read;
component set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component set_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : set_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : set_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity set_gmem_m_axi_fifo;
architecture behave of set_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity set_gmem_m_axi_decoder;
architecture behav of set_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity set_gmem_m_axi_throttl;
architecture behav of set_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_read;
architecture behave of set_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_write;
architecture behave of set_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component set_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : set_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
mit
|
c50281736202c4330b90bea41f4e1687
| 0.448702 | 4.001807 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/frame.vhd
| 1 | 2,138 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
use work.control_package.all;
use work.mmio_package.all;
use work.dma_package.all;
use work.frame_package.all;
entity frame is
port (
ha : in frame_in;
ah : out frame_out
);
end entity frame;
architecture logic of frame is
signal cr : cr_in;
signal ci : control_in;
signal co : control_out;
signal mi : mmio_in;
signal mo : mmio_out;
signal di : dma_in;
signal do : dma_out;
signal rc : unsigned(63 downto 0);
begin
----------------------------------------------------------------------------------------------------------------------- clock/reset
cr.clk <= ha.j.pclock;
cr.rst <= co.ca.reset;
----------------------------------------------------------------------------------------------------------------------- control
ci.clk <= cr.clk;
ci.ha <= ha.j;
ci.dc <= do.dc;
c0 : entity work.control port map (ci, co);
ah.j <= co.ah;
----------------------------------------------------------------------------------------------------------------------- mmio
mi.cr <= cr;
mi.ha <= ha.mm;
mi.ac.data <= slv(rc);
m0 : entity work.mmio port map (mi, mo);
ah.mm <= mo.ah;
----------------------------------------------------------------------------------------------------------------------- dma
di.cr <= cr;
--di.c <= ha.c;
di.b <= ha.b;
di.r <= ha.r;
di.cd <= co.cd;
d0 : entity work.dma port map (di, do);
ah.c <= do.c;
ah.b <= do.b;
----------------------------------------------------------------------------------------------------------------------- reset & registers
reg : process(cr)
begin
if rising_edge(cr.clk) then
if cr.rst then
rc <= (others => '0');
else
-- debug counter
if ha.r.valid then
rc <= rc + 1;
end if;
end if;
end if;
end process;
end architecture logic;
|
bsd-2-clause
|
32a2d3c82b64afb600560a6614010e59
| 0.371843 | 4.041588 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_2_1/synth/zc702_proc_sys_reset_2_1.vhd
| 1 | 6,659 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_2_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_2_1;
ARCHITECTURE zc702_proc_sys_reset_2_1_arch OF zc702_proc_sys_reset_2_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_2_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zc702_proc_sys_reset_2_1_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zc702_proc_sys_reset_2_1_arch : ARCHITECTURE IS "zc702_proc_sys_reset_2_1,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zc702_proc_sys_reset_2_1_arch: ARCHITECTURE IS "zc702_proc_sys_reset_2_1,proc_sys_reset,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_2_1_arch;
|
mit
|
9c3aac4a05663d62d5cbf7c9a7da4157
| 0.71317 | 3.439566 | false | false | false | false |
blutsvente/MIX
|
Resources/Examples/pin_master_vhdl_di_tnr/vhdl/di_tnr-struct-a.vhd
| 1 | 8,027 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of di_tnr
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 14:19:39 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
--
-- Generator: mix_1.pl Revision: 1.3 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of di_tnr
--
architecture struct of di_tnr is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component di_tnr_ctrl
-- No Generated Generics
port (
-- Generated Port for Entity di_tnr_ctrl
af_c0_o : out std_ulogic ;
af_c1_o : out std_ulogic;
af_p0_i : in std_ulogic;
al_c0_o : out std_ulogic;
al_c1_o : out std_ulogic;
al_c2_o : out std_ulogic;
al_p0_i : in std_ulogic;
ap_c0_o : out std_ulogic;
ap_c1_o : out std_ulogic;
ap_p0_i : in std_ulogic;
asresi_n : in std_ulogic;
clkin : in std_ulogic;
field_p0_i : in std_ulogic;
fieldc_c1_o : out std_ulogic;
fieldy0_c1_o : out std_ulogic;
fieldy1_c1_o : out std_ulogic;
frafiesel_iic_i : in std_ulogic;
hsync_c1_o : out std_ulogic;
hsync_p0_i : in std_ulogic;
hsync_p0_o : out std_ulogic;
req_p1_o : out std_ulogic;
tnrmdnr4c_iic_i : in std_ulogic;
tnrnr4y_iic_i : in std_ulogic;
uen_c1_o : out std_ulogic;
uen_p0_i : in std_ulogic;
vsync_c1_o : out std_ulogic;
vsync_p0_i : in std_ulogic
-- End of Generated Port for Entity di_tnr_ctrl
);
end component;
-- ---------
component di_tnrc
-- No Generated Generics
port (
-- Generated Port for Entity di_tnrc
af_c0_i : in std_ulogic ;
al_c0_i : in std_ulogic;
al_c1_i : in std_ulogic;
ap_c0_i : in std_ulogic;
ap_p0_i : in std_ulogic;
asresi_n : in std_ulogic;
c_p0_i : in std_ulogic_vector(7 downto 0);
c_p0_o : out std_ulogic_vector(7 downto 0);
c_p1_i : in std_ulogic_vector(7 downto 0);
c_p1_o : out std_ulogic_vector(7 downto 0);
cblack_p_i : in std_ulogic_vector(7 downto 0);
clkin : in std_ulogic;
hsync_c_i : in std_ulogic;
nr_dis_c_i : in std_ulogic;
nron_iic_i : in std_ulogic;
tnrabs_iic_i : in std_ulogic;
tnrclc_iic_i : in std_ulogic_vector(3 downto 0);
tnrkvaly_p_i : in std_ulogic_vector(3 downto 0);
tnrs0c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs1c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs2c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs3c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs4c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs5c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs6c_iic_i : in std_ulogic_vector(3 downto 0);
tnrs7c_iic_i : in std_ulogic_vector(3 downto 0);
tnrsel_iic_i : in std_ulogic;
tnrssc_iic_i : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity di_tnrc
);
end component;
-- ---------
component di_tnry
-- No Generated Generics
port (
-- Generated Port for Entity di_tnry
af_c0_i : in std_ulogic ;
al_c0_i : in std_ulogic;
al_c1_i : in std_ulogic;
ap_c0_i : in std_ulogic;
ap_p0_i : in std_ulogic;
asresi_n : in std_ulogic;
clkin : in std_ulogic;
hsync_c_i : in std_ulogic;
nr_dis_c_i : in std_ulogic;
nron_iic_i : in std_ulogic;
tnrabs_iic_i : in std_ulogic;
tnrcly_iic_i : in std_ulogic_vector(3 downto 0);
tnrkvaly_p_o : out std_ulogic_vector(3 downto 0);
tnrmd4y_iic_i : in std_ulogic;
tnrnr4y_iic_i : in std_ulogic;
tnrs0y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs1y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs2y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs3y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs4y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs5y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs6y_iic_i : in std_ulogic_vector(3 downto 0);
tnrs7y_iic_i : in std_ulogic_vector(3 downto 0);
tnrssy_iic_i : in std_ulogic_vector(3 downto 0);
y0_p1_i : in std_ulogic_vector(7 downto 0);
y0_p1_o : out std_ulogic_vector(7 downto 0);
y1_p1_i : in std_ulogic_vector(7 downto 0);
y1_p1_o : out std_ulogic_vector(7 downto 0);
y_p0_i : in std_ulogic_vector(7 downto 0);
y_p0_o : out std_ulogic_vector(7 downto 0);
yblack_p_i : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity di_tnry
);
end component;
-- ---------
--
-- Generated Signal List
--
signal af_c0 : std_ulogic ;
signal al_c0 : std_ulogic;
signal al_c2 : std_ulogic;
signal ap_c0 : std_ulogic;
signal hsync_c : std_ulogic;
signal tnrkvaly : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ctrl
ctrl: di_tnr_ctrl
port map (
af_c0_o => af_c0,
af_c1_o => af_c1_o,
af_p0_i => af_p0_i,
al_c0_o => al_c0,
al_c1_o => al_c1_o,
al_c2_o => al_c2,
al_p0_i => al_p0_i,
ap_c0_o => ap_c0,
ap_c1_o => ap_c1_o,
ap_p0_i => ap_p0_i,
asresi_n => asresi_n,
clkin => clkin,
field_p0_i => field_p0_i,
fieldc_c1_o => fieldc_c1_o,
fieldy0_c1_o => fieldy0_c1_o,
fieldy1_c1_o => fieldy1_c1_o,
frafiesel_iic_i => frafiesel_iic_i,
hsync_c1_o => hsync_c1_o,
hsync_p0_i => hsync_p0_i,
hsync_p0_o => hsync_c,
req_p1_o => req_p1_o,
tnrmdnr4c_iic_i => tnrmdnr4c_iic_i,
tnrnr4y_iic_i => tnrnr4y_iic_i,
uen_c1_o => uen_c1_o,
uen_p0_i => uen_p0_i,
vsync_c1_o => vsync_c1_o,
vsync_p0_i => vsync_p0_i
);
-- End of Generated Instance Port Map for ctrl
-- Generated Instance Port Map for tnrc
tnrc: di_tnrc
port map (
af_c0_i => af_c0,
al_c0_i => al_c0,
al_c1_i => al_c2,
ap_c0_i => ap_c0,
ap_p0_i => ap_p0_i,
asresi_n => asresi_n,
c_p0_i => c0_p0_i,
c_p0_o => c0_p0_o,
c_p1_i => c1_p1_i,
c_p1_o => c1_p1_o,
cblack_p_i => cblack_p_i,
clkin => clkin,
hsync_c_i => hsync_c,
nr_dis_c_i => nr_dis_c_i,
nron_iic_i => nron_iic_i,
tnrabs_iic_i => tnrabs_iic_i,
tnrclc_iic_i => tnrclc_iic_i,
tnrkvaly_p_i => tnrkvaly,
tnrs0c_iic_i => tnrs0c_iic_i,
tnrs1c_iic_i => tnrs1c_iic_i,
tnrs2c_iic_i => tnrs2c_iic_i,
tnrs3c_iic_i => tnrs3c_iic_i,
tnrs4c_iic_i => tnrs4c_iic_i,
tnrs5c_iic_i => tnrs5c_iic_i,
tnrs6c_iic_i => tnrs6c_iic_i,
tnrs7c_iic_i => tnrs7c_iic_i,
tnrsel_iic_i => tnrsel_iic_i,
tnrssc_iic_i => tnrssc_iic_i
);
-- End of Generated Instance Port Map for tnrc
-- Generated Instance Port Map for tnry
tnry: di_tnry
port map (
af_c0_i => af_c0,
al_c0_i => al_c0,
al_c1_i => al_c2,
ap_c0_i => ap_c0,
ap_p0_i => ap_p0_i,
asresi_n => asresi_n,
clkin => clkin,
hsync_c_i => hsync_c,
nr_dis_c_i => nr_dis_c_i,
nron_iic_i => nron_iic_i,
tnrabs_iic_i => tnrabs_iic_i,
tnrcly_iic_i => tnrcly_iic_i,
tnrkvaly_p_o => tnrkvaly,
tnrmd4y_iic_i => tnrmd4y_iic_i,
tnrnr4y_iic_i => tnrnr4y_iic_i,
tnrs0y_iic_i => tnrs0y_iic_i,
tnrs1y_iic_i => tnrs1y_iic_i,
tnrs2y_iic_i => tnrs2y_iic_i,
tnrs3y_iic_i => tnrs3y_iic_i,
tnrs4y_iic_i => tnrs4y_iic_i,
tnrs5y_iic_i => tnrs5y_iic_i,
tnrs6y_iic_i => tnrs6y_iic_i,
tnrs7y_iic_i => tnrs7y_iic_i,
tnrssy_iic_i => tnrssy_iic_i,
y0_p1_i => y2_p1_i,
y0_p1_o => y2_p1_o,
y1_p1_i => y1_p1_i,
y1_p1_o => y1_p1_o,
y_p0_i => y0_p0_i,
y_p0_o => y0_p0_o,
yblack_p_i => yblack_p_i
);
-- End of Generated Instance Port Map for tnry
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
2751ec5a97e0600fdaea043dc52ded49
| 0.595864 | 2.191373 | false | false | false | false |
agural/FPGA-Oscilloscope
|
FPGA/Test/NIOS/synthesis/NIOS.vhd
| 1 | 31,070 |
-- NIOS.vhd
-- Generated using ACDS version 13.1 162 at 2014.04.29.10:53:18
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity NIOS is
port (
clk_clk : in std_logic := '0' -- clk.clk
);
end entity NIOS;
architecture rtl of NIOS is
component NIOS_nios2_qsys_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(15 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(15 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
jtag_debug_module_resetrequest : out std_logic; -- reset
jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess
jtag_debug_module_read : in std_logic := 'X'; -- read
jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_debug_module_waitrequest : out std_logic; -- waitrequest
jtag_debug_module_write : in std_logic := 'X'; -- write
jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
no_ci_readra : out std_logic -- readra
);
end component NIOS_nios2_qsys_0;
component NIOS_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component NIOS_onchip_memory2_0;
component NIOS_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
nios2_qsys_0_reset_n_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_qsys_0_data_master_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
nios2_qsys_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_qsys_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_qsys_0_data_master_read : in std_logic := 'X'; -- read
nios2_qsys_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_qsys_0_data_master_write : in std_logic := 'X'; -- write
nios2_qsys_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_qsys_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_qsys_0_instruction_master_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
nios2_qsys_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_qsys_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_qsys_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_qsys_0_jtag_debug_module_address : out std_logic_vector(8 downto 0); -- address
nios2_qsys_0_jtag_debug_module_write : out std_logic; -- write
nios2_qsys_0_jtag_debug_module_read : out std_logic; -- read
nios2_qsys_0_jtag_debug_module_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_qsys_0_jtag_debug_module_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_qsys_0_jtag_debug_module_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_qsys_0_jtag_debug_module_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_qsys_0_jtag_debug_module_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(12 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic -- clken
);
end component NIOS_mm_interconnect_0;
component NIOS_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component NIOS_irq_mapper;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal nios2_qsys_0_jtag_debug_module_reset_reset : std_logic; -- nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in0, rst_controller:reset_in1]
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(12 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal nios2_qsys_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_qsys_0_data_master_waitrequest -> nios2_qsys_0:d_waitrequest
signal nios2_qsys_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0:d_writedata -> mm_interconnect_0:nios2_qsys_0_data_master_writedata
signal nios2_qsys_0_data_master_address : std_logic_vector(15 downto 0); -- nios2_qsys_0:d_address -> mm_interconnect_0:nios2_qsys_0_data_master_address
signal nios2_qsys_0_data_master_write : std_logic; -- nios2_qsys_0:d_write -> mm_interconnect_0:nios2_qsys_0_data_master_write
signal nios2_qsys_0_data_master_read : std_logic; -- nios2_qsys_0:d_read -> mm_interconnect_0:nios2_qsys_0_data_master_read
signal nios2_qsys_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_qsys_0_data_master_readdata -> nios2_qsys_0:d_readdata
signal nios2_qsys_0_data_master_debugaccess : std_logic; -- nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_0_data_master_debugaccess
signal nios2_qsys_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0:d_byteenable -> mm_interconnect_0:nios2_qsys_0_data_master_byteenable
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest : std_logic; -- nios2_qsys_0:jtag_debug_module_waitrequest -> mm_interconnect_0:nios2_qsys_0_jtag_debug_module_waitrequest
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_qsys_0_jtag_debug_module_writedata -> nios2_qsys_0:jtag_debug_module_writedata
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_qsys_0_jtag_debug_module_address -> nios2_qsys_0:jtag_debug_module_address
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write : std_logic; -- mm_interconnect_0:nios2_qsys_0_jtag_debug_module_write -> nios2_qsys_0:jtag_debug_module_write
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read : std_logic; -- mm_interconnect_0:nios2_qsys_0_jtag_debug_module_read -> nios2_qsys_0:jtag_debug_module_read
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0:jtag_debug_module_readdata -> mm_interconnect_0:nios2_qsys_0_jtag_debug_module_readdata
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess : std_logic; -- mm_interconnect_0:nios2_qsys_0_jtag_debug_module_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
signal mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_qsys_0_jtag_debug_module_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
signal nios2_qsys_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_qsys_0_instruction_master_waitrequest -> nios2_qsys_0:i_waitrequest
signal nios2_qsys_0_instruction_master_address : std_logic_vector(15 downto 0); -- nios2_qsys_0:i_address -> mm_interconnect_0:nios2_qsys_0_instruction_master_address
signal nios2_qsys_0_instruction_master_read : std_logic; -- nios2_qsys_0:i_read -> mm_interconnect_0:nios2_qsys_0_instruction_master_read
signal nios2_qsys_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_qsys_0_instruction_master_readdata -> nios2_qsys_0:i_readdata
signal nios2_qsys_0_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_qsys_0:d_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_qsys_0_reset_n_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_reset_out_reset:in]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2_qsys_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> nios2_qsys_0:reset_n
begin
nios2_qsys_0 : component NIOS_nios2_qsys_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
d_address => nios2_qsys_0_data_master_address, -- data_master.address
d_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
d_read => nios2_qsys_0_data_master_read, -- .read
d_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_qsys_0_data_master_write, -- .write
d_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
jtag_debug_module_debugaccess_to_roms => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_qsys_0_instruction_master_address, -- instruction_master.address
i_read => nios2_qsys_0_instruction_master_read, -- .read
i_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
d_irq => nios2_qsys_0_d_irq_irq, -- d_irq.irq
jtag_debug_module_resetrequest => nios2_qsys_0_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset
jtag_debug_module_address => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address, -- jtag_debug_module.address
jtag_debug_module_byteenable => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable, -- .byteenable
jtag_debug_module_debugaccess => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess, -- .debugaccess
jtag_debug_module_read => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read, -- .read
jtag_debug_module_readdata => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata, -- .readdata
jtag_debug_module_waitrequest => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest, -- .waitrequest
jtag_debug_module_write => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write, -- .write
jtag_debug_module_writedata => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata, -- .writedata
no_ci_readra => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component NIOS_onchip_memory2_0
port map (
clk => clk_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
mm_interconnect_0 : component NIOS_mm_interconnect_0
port map (
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
nios2_qsys_0_reset_n_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- nios2_qsys_0_reset_n_reset_bridge_in_reset.reset
nios2_qsys_0_data_master_address => nios2_qsys_0_data_master_address, -- nios2_qsys_0_data_master.address
nios2_qsys_0_data_master_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
nios2_qsys_0_data_master_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
nios2_qsys_0_data_master_read => nios2_qsys_0_data_master_read, -- .read
nios2_qsys_0_data_master_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
nios2_qsys_0_data_master_write => nios2_qsys_0_data_master_write, -- .write
nios2_qsys_0_data_master_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
nios2_qsys_0_data_master_debugaccess => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
nios2_qsys_0_instruction_master_address => nios2_qsys_0_instruction_master_address, -- nios2_qsys_0_instruction_master.address
nios2_qsys_0_instruction_master_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
nios2_qsys_0_instruction_master_read => nios2_qsys_0_instruction_master_read, -- .read
nios2_qsys_0_instruction_master_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
nios2_qsys_0_jtag_debug_module_address => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address, -- nios2_qsys_0_jtag_debug_module.address
nios2_qsys_0_jtag_debug_module_write => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write, -- .write
nios2_qsys_0_jtag_debug_module_read => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read, -- .read
nios2_qsys_0_jtag_debug_module_readdata => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata, -- .readdata
nios2_qsys_0_jtag_debug_module_writedata => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata, -- .writedata
nios2_qsys_0_jtag_debug_module_byteenable => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable, -- .byteenable
nios2_qsys_0_jtag_debug_module_waitrequest => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest, -- .waitrequest
nios2_qsys_0_jtag_debug_module_debugaccess => mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken -- .clken
);
irq_mapper : component NIOS_irq_mapper
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sender_irq => nios2_qsys_0_d_irq_irq -- sender.irq
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of NIOS
|
mit
|
0fe3b2a7b92c39bd33adbff0798cb6c7
| 0.489186 | 3.73752 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/pad_pads_e-rtl-a.vhd
| 1 | 14,240 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of pad_pads_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:22 wig Exp $
-- $Date: 2006/07/05 10:01:22 $
-- $Log: pad_pads_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:22 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of pad_pads_e
--
architecture rtl of pad_pads_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component w_pad_i
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_i
di : out std_ulogic -- data in from pad
-- End of Generated Port for Entity w_pad_i
);
end component;
-- ---------
component w_disp
-- No Generated Generics
port (
-- Generated Port for Entity w_disp
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_disp
);
end component;
-- ---------
component w_pad_o
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_o
do : in std_ulogic; -- data out to pad
en : in std_ulogic -- pad output enable
-- End of Generated Port for Entity w_pad_o
);
end component;
-- ---------
component w_data2
-- No Generated Generics
port (
-- Generated Port for Entity w_data2
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data2
);
end component;
-- ---------
component w_data3
-- No Generated Generics
port (
-- Generated Port for Entity w_data3
di : out std_ulogic; -- data in from pad
do : in std_ulogic; -- data out to pad
en : in std_ulogic; -- pad output enable
pu : in std_ulogic -- pull-up control
-- End of Generated Port for Entity w_data3
);
end component;
-- ---------
component w_pad_dir
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dir
di : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dir
);
end component;
-- ---------
component w_pad_dire
-- No Generated Generics
port (
-- Generated Port for Entity w_pad_dire
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_pad_dire
);
end component;
-- ---------
component w_osc
-- No Generated Generics
port (
-- Generated Port for Entity w_osc
pd : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
xo : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity w_osc
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_1 : std_ulogic;
signal mix_logic0_0 : std_ulogic;
-- __I_NODRV_I signal clki2c : std_ulogic;
signal clki3c : std_ulogic;
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal pad_dir_di : std_ulogic;
-- __I_OUT_OPEN signal pad_dir_di38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_do38 : std_ulogic;
-- __I_NODRV_I signal pad_dir_en38 : std_ulogic;
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_1 <= '1';
mix_logic0_0 <= '0';
p_mix_pad_di_1_go <= pad_di_1; -- __I_O_BIT_PORT
p_mix_pad_di_12_go <= pad_di_12; -- __I_O_BIT_PORT
p_mix_pad_di_13_go <= pad_di_13; -- __I_O_BIT_PORT
p_mix_pad_di_14_go <= pad_di_14; -- __I_O_BIT_PORT
p_mix_pad_di_15_go <= pad_di_15; -- __I_O_BIT_PORT
p_mix_pad_di_16_go <= pad_di_16; -- __I_O_BIT_PORT
p_mix_pad_di_17_go <= pad_di_17; -- __I_O_BIT_PORT
p_mix_pad_di_18_go <= pad_di_18; -- __I_O_BIT_PORT
p_mix_pad_di_31_go <= pad_di_31; -- __I_O_BIT_PORT
p_mix_pad_di_32_go <= pad_di_32; -- __I_O_BIT_PORT
p_mix_pad_di_33_go <= pad_di_33; -- __I_O_BIT_PORT
p_mix_pad_di_34_go <= pad_di_34; -- __I_O_BIT_PORT
p_mix_pad_di_39_go <= pad_di_39; -- __I_O_BIT_PORT
p_mix_pad_di_40_go <= pad_di_40; -- __I_O_BIT_PORT
pad_do_12 <= p_mix_pad_do_12_gi; -- __I_I_BIT_PORT
pad_do_13 <= p_mix_pad_do_13_gi; -- __I_I_BIT_PORT
pad_do_14 <= p_mix_pad_do_14_gi; -- __I_I_BIT_PORT
pad_do_15 <= p_mix_pad_do_15_gi; -- __I_I_BIT_PORT
pad_do_16 <= p_mix_pad_do_16_gi; -- __I_I_BIT_PORT
pad_do_17 <= p_mix_pad_do_17_gi; -- __I_I_BIT_PORT
pad_do_18 <= p_mix_pad_do_18_gi; -- __I_I_BIT_PORT
pad_do_2 <= p_mix_pad_do_2_gi; -- __I_I_BIT_PORT
pad_do_31 <= p_mix_pad_do_31_gi; -- __I_I_BIT_PORT
pad_do_32 <= p_mix_pad_do_32_gi; -- __I_I_BIT_PORT
pad_do_35 <= p_mix_pad_do_35_gi; -- __I_I_BIT_PORT
pad_do_36 <= p_mix_pad_do_36_gi; -- __I_I_BIT_PORT
pad_do_39 <= p_mix_pad_do_39_gi; -- __I_I_BIT_PORT
pad_do_40 <= p_mix_pad_do_40_gi; -- __I_I_BIT_PORT
pad_en_12 <= p_mix_pad_en_12_gi; -- __I_I_BIT_PORT
pad_en_13 <= p_mix_pad_en_13_gi; -- __I_I_BIT_PORT
pad_en_14 <= p_mix_pad_en_14_gi; -- __I_I_BIT_PORT
pad_en_15 <= p_mix_pad_en_15_gi; -- __I_I_BIT_PORT
pad_en_16 <= p_mix_pad_en_16_gi; -- __I_I_BIT_PORT
pad_en_17 <= p_mix_pad_en_17_gi; -- __I_I_BIT_PORT
pad_en_18 <= p_mix_pad_en_18_gi; -- __I_I_BIT_PORT
pad_en_2 <= p_mix_pad_en_2_gi; -- __I_I_BIT_PORT
pad_en_31 <= p_mix_pad_en_31_gi; -- __I_I_BIT_PORT
pad_en_32 <= p_mix_pad_en_32_gi; -- __I_I_BIT_PORT
pad_en_35 <= p_mix_pad_en_35_gi; -- __I_I_BIT_PORT
pad_en_36 <= p_mix_pad_en_36_gi; -- __I_I_BIT_PORT
pad_en_39 <= p_mix_pad_en_39_gi; -- __I_I_BIT_PORT
pad_en_40 <= p_mix_pad_en_40_gi; -- __I_I_BIT_PORT
pad_pu_31 <= p_mix_pad_pu_31_gi; -- __I_I_BIT_PORT
pad_pu_32 <= p_mix_pad_pu_32_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for pad_1
pad_1: w_pad_i
port map (
di => pad_di_1 -- data in from pad
);
-- End of Generated Instance Port Map for pad_1
-- Generated Instance Port Map for pad_12
pad_12: w_disp
port map (
di => pad_di_12, -- data in from pad
do => pad_do_12, -- data out to pad
en => pad_en_12 -- pad output enable
);
-- End of Generated Instance Port Map for pad_12
-- Generated Instance Port Map for pad_13
pad_13: w_disp
port map (
di => pad_di_13, -- data in from pad
do => pad_do_13, -- data out to pad
en => pad_en_13 -- pad output enable
);
-- End of Generated Instance Port Map for pad_13
-- Generated Instance Port Map for pad_14
pad_14: w_disp
port map (
di => pad_di_14, -- data in from pad
do => pad_do_14, -- data out to pad
en => pad_en_14 -- pad output enable
);
-- End of Generated Instance Port Map for pad_14
-- Generated Instance Port Map for pad_15
pad_15: w_disp
port map (
di => pad_di_15, -- data in from pad
do => pad_do_15, -- data out to pad
en => pad_en_15 -- pad output enable
);
-- End of Generated Instance Port Map for pad_15
-- Generated Instance Port Map for pad_16
pad_16: w_disp
port map (
di => pad_di_16, -- data in from pad
do => pad_do_16, -- data out to pad
en => pad_en_16 -- pad output enable
);
-- End of Generated Instance Port Map for pad_16
-- Generated Instance Port Map for pad_17
pad_17: w_disp
port map (
di => pad_di_17, -- data in from pad
do => pad_do_17, -- data out to pad
en => pad_en_17 -- pad output enable
);
-- End of Generated Instance Port Map for pad_17
-- Generated Instance Port Map for pad_18
pad_18: w_disp
port map (
di => pad_di_18, -- data in from pad
do => pad_do_18, -- data out to pad
en => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for pad_18
-- Generated Instance Port Map for pad_2
pad_2: w_pad_o
port map (
do => pad_do_2, -- data out to pad
en => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for pad_2
-- Generated Instance Port Map for pad_31
pad_31: w_data2
port map (
di => pad_di_31, -- data in from pad
do => pad_do_31, -- data out to pad
en => pad_en_31, -- pad output enable
pu => pad_pu_31 -- pull-up control
);
-- End of Generated Instance Port Map for pad_31
-- Generated Instance Port Map for pad_32
pad_32: w_data3
port map (
di => pad_di_32, -- data in from pad
do => pad_do_32, -- data out to pad
en => pad_en_32, -- pad output enable
pu => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_32
-- Generated Instance Port Map for pad_33
pad_33: w_pad_i
port map (
di => pad_di_33 -- data in from pad
);
-- End of Generated Instance Port Map for pad_33
-- Generated Instance Port Map for pad_34
pad_34: w_pad_i
port map (
di => pad_di_34 -- data in from pad
);
-- End of Generated Instance Port Map for pad_34
-- Generated Instance Port Map for pad_35
pad_35: w_pad_o
port map (
do => pad_do_35, -- data out to pad
en => pad_en_35 -- pad output enable
);
-- End of Generated Instance Port Map for pad_35
-- Generated Instance Port Map for pad_36
pad_36: w_pad_o
port map (
do => pad_do_36, -- data out to pad
en => pad_en_36 -- pad output enable
);
-- End of Generated Instance Port Map for pad_36
-- Generated Instance Port Map for pad_37
pad_37: w_pad_dir
port map (
di => open -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for pad_37
-- Generated Instance Port Map for pad_38
pad_38: w_pad_dire
port map (
di => open, -- __I_OUT_OPEN
-- __I_NODRV_I -- __I_NODRV_I do => __nodrv__/pad_dir_en38/pad_dir_do38,
-- __I_NODRV_I en => __nodrv__/pad_dir_en38
);
-- End of Generated Instance Port Map for pad_38
-- Generated Instance Port Map for pad_39
pad_39: w_disp
port map (
di => pad_di_39, -- data in from pad
do => pad_do_39, -- data out to pad
en => pad_en_39 -- pad output enable
);
-- End of Generated Instance Port Map for pad_39
-- Generated Instance Port Map for pad_40
pad_40: w_disp
port map (
di => pad_di_40, -- data in from pad
do => pad_do_40, -- data out to pad
en => pad_en_40 -- pad output enable
);
-- End of Generated Instance Port Map for pad_40
-- Generated Instance Port Map for pad_41
pad_41: w_osc
port map (
pd => mix_logic1_0,
-- __I_NODRV_I xo => __nodrv__/clki2c
);
-- End of Generated Instance Port Map for pad_41
-- Generated Instance Port Map for pad_42
pad_42: w_osc
port map (
pd => mix_logic1_1,
xo => clki3c
);
-- End of Generated Instance Port Map for pad_42
-- Generated Instance Port Map for pad_43
pad_43: w_osc
port map (
pd => mix_logic0_0,
xo => clki3c
);
-- End of Generated Instance Port Map for pad_43
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
f331459fffdf99a65884cb2cda71cd89
| 0.601966 | 2.484299 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/vhls/set/solution/syn/vhdl/set.vhd
| 4 | 37,773 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set is
generic (
C_M_AXI_GMEM_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_ID_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_DATA_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_BUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_CACHE_VALUE : INTEGER := 3;
C_M_AXI_GMEM_USER_VALUE : INTEGER := 0;
C_M_AXI_GMEM_PROT_VALUE : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_gmem_AWVALID : OUT STD_LOGIC;
m_axi_gmem_AWREADY : IN STD_LOGIC;
m_axi_gmem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_AWUSER_WIDTH-1 downto 0);
m_axi_gmem_WVALID : OUT STD_LOGIC;
m_axi_gmem_WREADY : IN STD_LOGIC;
m_axi_gmem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH/8-1 downto 0);
m_axi_gmem_WLAST : OUT STD_LOGIC;
m_axi_gmem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_WUSER_WIDTH-1 downto 0);
m_axi_gmem_ARVALID : OUT STD_LOGIC;
m_axi_gmem_ARREADY : IN STD_LOGIC;
m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ARUSER_WIDTH-1 downto 0);
m_axi_gmem_RVALID : IN STD_LOGIC;
m_axi_gmem_RREADY : OUT STD_LOGIC;
m_axi_gmem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_RLAST : IN STD_LOGIC;
m_axi_gmem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_RUSER_WIDTH-1 downto 0);
m_axi_gmem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BVALID : IN STD_LOGIC;
m_axi_gmem_BREADY : OUT STD_LOGIC;
m_axi_gmem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_BUSER_WIDTH-1 downto 0);
data : IN STD_LOGIC_VECTOR (31 downto 0);
key : IN STD_LOGIC_VECTOR (31 downto 0);
val_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"set,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.500000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.437500,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=623,HLS_SYN_LUT=743}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal gmem_AWVALID : STD_LOGIC;
signal gmem_AWREADY : STD_LOGIC;
signal gmem_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WVALID : STD_LOGIC;
signal gmem_WREADY : STD_LOGIC;
signal gmem_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_WLAST : STD_LOGIC;
signal gmem_WID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARVALID : STD_LOGIC;
signal gmem_ARREADY : STD_LOGIC;
signal gmem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RVALID : STD_LOGIC;
signal gmem_RREADY : STD_LOGIC;
signal gmem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_RLAST : STD_LOGIC;
signal gmem_RID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BVALID : STD_LOGIC;
signal gmem_BREADY : STD_LOGIC;
signal gmem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal set_gmem_m_axi_U_ap_dummy_ce : STD_LOGIC;
signal data1_reg_90 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_ap_start : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_done : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_idle : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_ready : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_data1 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_tmp : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_src : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component set_assign_val IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
component set_gmem_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
set_gmem_m_axi_U : component set_gmem_m_axi
generic map (
USER_DW => 32,
USER_AW => 32,
USER_MAXREQS => 5,
C_M_AXI_ID_WIDTH => C_M_AXI_GMEM_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_GMEM_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_GMEM_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_GMEM_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_GMEM_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_GMEM_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_GMEM_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_GMEM_BUSER_WIDTH,
C_USER_VALUE => C_M_AXI_GMEM_USER_VALUE,
C_PROT_VALUE => C_M_AXI_GMEM_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_GMEM_CACHE_VALUE)
port map (
AWVALID => m_axi_gmem_AWVALID,
AWREADY => m_axi_gmem_AWREADY,
AWADDR => m_axi_gmem_AWADDR,
AWID => m_axi_gmem_AWID,
AWLEN => m_axi_gmem_AWLEN,
AWSIZE => m_axi_gmem_AWSIZE,
AWBURST => m_axi_gmem_AWBURST,
AWLOCK => m_axi_gmem_AWLOCK,
AWCACHE => m_axi_gmem_AWCACHE,
AWPROT => m_axi_gmem_AWPROT,
AWQOS => m_axi_gmem_AWQOS,
AWREGION => m_axi_gmem_AWREGION,
AWUSER => m_axi_gmem_AWUSER,
WVALID => m_axi_gmem_WVALID,
WREADY => m_axi_gmem_WREADY,
WDATA => m_axi_gmem_WDATA,
WSTRB => m_axi_gmem_WSTRB,
WLAST => m_axi_gmem_WLAST,
WID => m_axi_gmem_WID,
WUSER => m_axi_gmem_WUSER,
ARVALID => m_axi_gmem_ARVALID,
ARREADY => m_axi_gmem_ARREADY,
ARADDR => m_axi_gmem_ARADDR,
ARID => m_axi_gmem_ARID,
ARLEN => m_axi_gmem_ARLEN,
ARSIZE => m_axi_gmem_ARSIZE,
ARBURST => m_axi_gmem_ARBURST,
ARLOCK => m_axi_gmem_ARLOCK,
ARCACHE => m_axi_gmem_ARCACHE,
ARPROT => m_axi_gmem_ARPROT,
ARQOS => m_axi_gmem_ARQOS,
ARREGION => m_axi_gmem_ARREGION,
ARUSER => m_axi_gmem_ARUSER,
RVALID => m_axi_gmem_RVALID,
RREADY => m_axi_gmem_RREADY,
RDATA => m_axi_gmem_RDATA,
RLAST => m_axi_gmem_RLAST,
RID => m_axi_gmem_RID,
RUSER => m_axi_gmem_RUSER,
RRESP => m_axi_gmem_RRESP,
BVALID => m_axi_gmem_BVALID,
BREADY => m_axi_gmem_BREADY,
BRESP => m_axi_gmem_BRESP,
BID => m_axi_gmem_BID,
BUSER => m_axi_gmem_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => set_gmem_m_axi_U_ap_dummy_ce,
I_ARVALID => gmem_ARVALID,
I_ARREADY => gmem_ARREADY,
I_ARADDR => gmem_ARADDR,
I_ARID => gmem_ARID,
I_ARLEN => gmem_ARLEN,
I_ARSIZE => gmem_ARSIZE,
I_ARLOCK => gmem_ARLOCK,
I_ARCACHE => gmem_ARCACHE,
I_ARQOS => gmem_ARQOS,
I_ARPROT => gmem_ARPROT,
I_ARUSER => gmem_ARUSER,
I_ARBURST => gmem_ARBURST,
I_ARREGION => gmem_ARREGION,
I_RVALID => gmem_RVALID,
I_RREADY => gmem_RREADY,
I_RDATA => gmem_RDATA,
I_RID => gmem_RID,
I_RUSER => gmem_RUSER,
I_RRESP => gmem_RRESP,
I_RLAST => gmem_RLAST,
I_AWVALID => gmem_AWVALID,
I_AWREADY => gmem_AWREADY,
I_AWADDR => gmem_AWADDR,
I_AWID => gmem_AWID,
I_AWLEN => gmem_AWLEN,
I_AWSIZE => gmem_AWSIZE,
I_AWLOCK => gmem_AWLOCK,
I_AWCACHE => gmem_AWCACHE,
I_AWQOS => gmem_AWQOS,
I_AWPROT => gmem_AWPROT,
I_AWUSER => gmem_AWUSER,
I_AWBURST => gmem_AWBURST,
I_AWREGION => gmem_AWREGION,
I_WVALID => gmem_WVALID,
I_WREADY => gmem_WREADY,
I_WDATA => gmem_WDATA,
I_WID => gmem_WID,
I_WUSER => gmem_WUSER,
I_WLAST => gmem_WLAST,
I_WSTRB => gmem_WSTRB,
I_BVALID => gmem_BVALID,
I_BREADY => gmem_BREADY,
I_BRESP => gmem_BRESP,
I_BID => gmem_BID,
I_BUSER => gmem_BUSER);
grp_set_assign_val_fu_58 : component set_assign_val
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_set_assign_val_fu_58_ap_start,
ap_done => grp_set_assign_val_fu_58_ap_done,
ap_idle => grp_set_assign_val_fu_58_ap_idle,
ap_ready => grp_set_assign_val_fu_58_ap_ready,
m_axi_dest_AWVALID => grp_set_assign_val_fu_58_m_axi_dest_AWVALID,
m_axi_dest_AWREADY => grp_set_assign_val_fu_58_m_axi_dest_AWREADY,
m_axi_dest_AWADDR => grp_set_assign_val_fu_58_m_axi_dest_AWADDR,
m_axi_dest_AWID => grp_set_assign_val_fu_58_m_axi_dest_AWID,
m_axi_dest_AWLEN => grp_set_assign_val_fu_58_m_axi_dest_AWLEN,
m_axi_dest_AWSIZE => grp_set_assign_val_fu_58_m_axi_dest_AWSIZE,
m_axi_dest_AWBURST => grp_set_assign_val_fu_58_m_axi_dest_AWBURST,
m_axi_dest_AWLOCK => grp_set_assign_val_fu_58_m_axi_dest_AWLOCK,
m_axi_dest_AWCACHE => grp_set_assign_val_fu_58_m_axi_dest_AWCACHE,
m_axi_dest_AWPROT => grp_set_assign_val_fu_58_m_axi_dest_AWPROT,
m_axi_dest_AWQOS => grp_set_assign_val_fu_58_m_axi_dest_AWQOS,
m_axi_dest_AWREGION => grp_set_assign_val_fu_58_m_axi_dest_AWREGION,
m_axi_dest_AWUSER => grp_set_assign_val_fu_58_m_axi_dest_AWUSER,
m_axi_dest_WVALID => grp_set_assign_val_fu_58_m_axi_dest_WVALID,
m_axi_dest_WREADY => grp_set_assign_val_fu_58_m_axi_dest_WREADY,
m_axi_dest_WDATA => grp_set_assign_val_fu_58_m_axi_dest_WDATA,
m_axi_dest_WSTRB => grp_set_assign_val_fu_58_m_axi_dest_WSTRB,
m_axi_dest_WLAST => grp_set_assign_val_fu_58_m_axi_dest_WLAST,
m_axi_dest_WID => grp_set_assign_val_fu_58_m_axi_dest_WID,
m_axi_dest_WUSER => grp_set_assign_val_fu_58_m_axi_dest_WUSER,
m_axi_dest_ARVALID => grp_set_assign_val_fu_58_m_axi_dest_ARVALID,
m_axi_dest_ARREADY => grp_set_assign_val_fu_58_m_axi_dest_ARREADY,
m_axi_dest_ARADDR => grp_set_assign_val_fu_58_m_axi_dest_ARADDR,
m_axi_dest_ARID => grp_set_assign_val_fu_58_m_axi_dest_ARID,
m_axi_dest_ARLEN => grp_set_assign_val_fu_58_m_axi_dest_ARLEN,
m_axi_dest_ARSIZE => grp_set_assign_val_fu_58_m_axi_dest_ARSIZE,
m_axi_dest_ARBURST => grp_set_assign_val_fu_58_m_axi_dest_ARBURST,
m_axi_dest_ARLOCK => grp_set_assign_val_fu_58_m_axi_dest_ARLOCK,
m_axi_dest_ARCACHE => grp_set_assign_val_fu_58_m_axi_dest_ARCACHE,
m_axi_dest_ARPROT => grp_set_assign_val_fu_58_m_axi_dest_ARPROT,
m_axi_dest_ARQOS => grp_set_assign_val_fu_58_m_axi_dest_ARQOS,
m_axi_dest_ARREGION => grp_set_assign_val_fu_58_m_axi_dest_ARREGION,
m_axi_dest_ARUSER => grp_set_assign_val_fu_58_m_axi_dest_ARUSER,
m_axi_dest_RVALID => grp_set_assign_val_fu_58_m_axi_dest_RVALID,
m_axi_dest_RREADY => grp_set_assign_val_fu_58_m_axi_dest_RREADY,
m_axi_dest_RDATA => grp_set_assign_val_fu_58_m_axi_dest_RDATA,
m_axi_dest_RLAST => grp_set_assign_val_fu_58_m_axi_dest_RLAST,
m_axi_dest_RID => grp_set_assign_val_fu_58_m_axi_dest_RID,
m_axi_dest_RUSER => grp_set_assign_val_fu_58_m_axi_dest_RUSER,
m_axi_dest_RRESP => grp_set_assign_val_fu_58_m_axi_dest_RRESP,
m_axi_dest_BVALID => grp_set_assign_val_fu_58_m_axi_dest_BVALID,
m_axi_dest_BREADY => grp_set_assign_val_fu_58_m_axi_dest_BREADY,
m_axi_dest_BRESP => grp_set_assign_val_fu_58_m_axi_dest_BRESP,
m_axi_dest_BID => grp_set_assign_val_fu_58_m_axi_dest_BID,
m_axi_dest_BUSER => grp_set_assign_val_fu_58_m_axi_dest_BUSER,
data1 => grp_set_assign_val_fu_58_data1,
tmp => grp_set_assign_val_fu_58_tmp,
src => grp_set_assign_val_fu_58_src);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_set_assign_val_fu_58_ap_start_ap_start_reg assign process. --
grp_set_assign_val_fu_58_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_set_assign_val_fu_58_ap_ready)) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
data1_reg_90 <= data(31 downto 2);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, grp_set_assign_val_fu_58_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
gmem_ARADDR <= ap_const_lv32_0;
gmem_ARBURST <= ap_const_lv2_0;
gmem_ARCACHE <= ap_const_lv4_0;
gmem_ARID <= ap_const_lv1_0;
gmem_ARLEN <= ap_const_lv32_0;
gmem_ARLOCK <= ap_const_lv2_0;
gmem_ARPROT <= ap_const_lv3_0;
gmem_ARQOS <= ap_const_lv4_0;
gmem_ARREGION <= ap_const_lv4_0;
gmem_ARSIZE <= ap_const_lv3_0;
gmem_ARUSER <= ap_const_lv1_0;
gmem_ARVALID <= ap_const_logic_0;
gmem_AWADDR <= grp_set_assign_val_fu_58_m_axi_dest_AWADDR;
gmem_AWBURST <= grp_set_assign_val_fu_58_m_axi_dest_AWBURST;
gmem_AWCACHE <= grp_set_assign_val_fu_58_m_axi_dest_AWCACHE;
gmem_AWID <= grp_set_assign_val_fu_58_m_axi_dest_AWID;
gmem_AWLEN <= grp_set_assign_val_fu_58_m_axi_dest_AWLEN;
gmem_AWLOCK <= grp_set_assign_val_fu_58_m_axi_dest_AWLOCK;
gmem_AWPROT <= grp_set_assign_val_fu_58_m_axi_dest_AWPROT;
gmem_AWQOS <= grp_set_assign_val_fu_58_m_axi_dest_AWQOS;
gmem_AWREGION <= grp_set_assign_val_fu_58_m_axi_dest_AWREGION;
gmem_AWSIZE <= grp_set_assign_val_fu_58_m_axi_dest_AWSIZE;
gmem_AWUSER <= grp_set_assign_val_fu_58_m_axi_dest_AWUSER;
-- gmem_AWVALID assign process. --
gmem_AWVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_AWVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_AWVALID <= grp_set_assign_val_fu_58_m_axi_dest_AWVALID;
else
gmem_AWVALID <= ap_const_logic_0;
end if;
end process;
-- gmem_BREADY assign process. --
gmem_BREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_BREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_BREADY <= grp_set_assign_val_fu_58_m_axi_dest_BREADY;
else
gmem_BREADY <= ap_const_logic_0;
end if;
end process;
gmem_RREADY <= ap_const_logic_0;
gmem_WDATA <= grp_set_assign_val_fu_58_m_axi_dest_WDATA;
gmem_WID <= grp_set_assign_val_fu_58_m_axi_dest_WID;
gmem_WLAST <= grp_set_assign_val_fu_58_m_axi_dest_WLAST;
gmem_WSTRB <= grp_set_assign_val_fu_58_m_axi_dest_WSTRB;
gmem_WUSER <= grp_set_assign_val_fu_58_m_axi_dest_WUSER;
-- gmem_WVALID assign process. --
gmem_WVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_WVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_WVALID <= grp_set_assign_val_fu_58_m_axi_dest_WVALID;
else
gmem_WVALID <= ap_const_logic_0;
end if;
end process;
grp_set_assign_val_fu_58_ap_start <= grp_set_assign_val_fu_58_ap_start_ap_start_reg;
grp_set_assign_val_fu_58_data1 <= data1_reg_90;
grp_set_assign_val_fu_58_m_axi_dest_ARREADY <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_AWREADY <= gmem_AWREADY;
grp_set_assign_val_fu_58_m_axi_dest_BID <= gmem_BID;
grp_set_assign_val_fu_58_m_axi_dest_BRESP <= gmem_BRESP;
grp_set_assign_val_fu_58_m_axi_dest_BUSER <= gmem_BUSER;
grp_set_assign_val_fu_58_m_axi_dest_BVALID <= gmem_BVALID;
grp_set_assign_val_fu_58_m_axi_dest_RDATA <= ap_const_lv32_0;
grp_set_assign_val_fu_58_m_axi_dest_RID <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RLAST <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_RRESP <= ap_const_lv2_0;
grp_set_assign_val_fu_58_m_axi_dest_RUSER <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RVALID <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_WREADY <= gmem_WREADY;
grp_set_assign_val_fu_58_src <= val_r;
grp_set_assign_val_fu_58_tmp <= key;
set_gmem_m_axi_U_ap_dummy_ce <= ap_const_logic_1;
end behav;
|
mit
|
cef5fe6ffcd95c02cca9d169f228f422
| 0.598311 | 2.970743 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_s2m_converter.vhd
| 1 | 5,175 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_s2m_converter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-08-01 2.0 pvk Removed conv_bank port.Not being used.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
entity xd_s2m_converter is
generic (
-- System generics:
C_FAMILY : string; -- Xilinx FPGA family
AXI_DATA_WIDTH : integer;
AXI_ADDR_WIDTH : integer;
C_EXTRA_SYNCS : integer);
port (
axi_clk : in std_logic;
axi_rst : in std_logic;
axis_vld : in std_logic;
axis_rdy : out std_logic;
axis_last : in std_logic;
axis_keep : in std_logic_vector((AXI_DATA_WIDTH/8)-1 downto 0);
axis_data : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
--conv_bank : out std_logic_vector(5 downto 0);
conv_addr : out std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
conv_ce : out std_logic;
conv_we : out std_logic;
conv_last : out std_logic;
conv_rdy : in std_logic;
conv_data : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0));
end entity;
architecture rtl of xd_s2m_converter is
signal axis_rdy_i : std_logic;
signal addr_cnt : unsigned(AXI_ADDR_WIDTH-1 downto 0);
begin
axis_rdy <= axis_rdy_i;
process(axi_clk)
begin
if(axi_clk'event and axi_clk = '1') then
if(axi_rst = '1' or (axis_vld and axis_rdy_i and axis_last) = '1') then
addr_cnt <= (others => '0');
elsif((axis_vld and axis_rdy_i) = '1') then
addr_cnt <= addr_cnt + 1;
end if;
end if;
end process;
-- Used a simple approach; would be good to elaborate more in the long term.
conv_we <= or_reduce(axis_keep);
conv_ce <= axis_vld;
conv_data <= axis_data;
conv_last <= axis_last;
axis_rdy_i <= conv_rdy;
conv_addr <= std_logic_vector(addr_cnt);
end rtl;
|
mit
|
e28ae40ef38380fa17122a5939f7dce4
| 0.594203 | 4.107143 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_counter0.vhd
| 2 | 4,338 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter0 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter0;
ARCHITECTURE SYN OF lpm_counter0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
7121707f2239b05f15a2e6fae643b6b3
| 0.650761 | 3.69821 | false | false | false | false |
mitchsm/nvc
|
test/regress/jcore6.vhd
| 3 | 630 |
entity jcore6 is
end entity;
architecture test of jcore6 is
procedure update(signal x : in bit_vector(1 downto 0);
sel : in integer;
signal y : out bit) is
begin
y <= x(sel);
end procedure;
signal s_sel : integer range 0 to 1;
signal s_x : bit_vector(1 downto 0);
signal s_y : bit;
begin
update(s_x, s_sel, s_y);
process is
begin
s_x <= "10";
s_sel <= 1;
wait for 1 ns;
assert s_y = '1';
s_sel <= 0;
wait for 1 ns;
assert s_y = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
35ea7275f17f0c7abb88ec27f09011c9
| 0.5 | 3.5 | false | false | false | false |
mitchsm/nvc
|
test/sem/conc.vhd
| 5 | 782 |
entity e is
end entity;
architecture a of e is
signal x, y : integer;
begin
x <= 4; -- OK
y <= x + 2; -- OK
x <= '4'; -- Wrong type
x <= 6 when y > 2 else 7; -- OK
x <= 7 when 7 else 3; -- Condition not boolean
x <= reject 5 inertial 7; -- Reject not time
with y select x <= -- OK
1 when 3,
2 when 8,
3 when others;
with y select x <=
1 when y; -- Not locally static
with y select x <=
true when 5; -- Wrong type
with y select x <=
6, 7 after 1 ns when false; -- Wrong type
end architecture;
|
gpl-3.0
|
09eac4870026dbc97efac04ba446fe6f
| 0.393862 | 4.494253 | false | false | false | false |
blutsvente/MIX
|
test/results/highlow/ent_a-rtl-a.vhd
| 1 | 4,284 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jun 9 05:15:53 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.3 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.3 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
high_bus_3_0 : in std_ulogic_vector(3 downto 0); -- Ground wire_low port
low_bit_aa : in std_ulogic;
mix_logic0_bus_2 : in std_ulogic_vector(3 downto 0); -- Ground port
mix_logic1_0 : in std_ulogic; -- Wire bit to high
part_zero : out std_ulogic_vector(3 downto 0) -- Wire two bits to port
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
low_bus_6_0 : in std_ulogic_vector(6 downto 0); -- Wide low port
port_part_zero_u : in std_ulogic_vector(3 downto 0) -- Wire two bits to portWire two bits to low
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_ad
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_ae
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_bus_1 : std_ulogic_vector(3 downto 0);
signal mix_logic0_1 : std_ulogic;
signal mix_logic0_bus_2 : std_ulogic_vector(3 downto 0);
signal mix_logic0_bus_3 : std_ulogic_vector(6 downto 0);
signal mix_logic0_bus_4 : std_ulogic_vector(1 downto 0);
signal part_zero : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_bus_1 <= ( others => '1' );
mix_logic0_1 <= '0';
mix_logic0_bus_2 <= ( others => '0' );
mix_logic0_bus_3 <= ( others => '0' );
mix_logic0_bus_4 <= ( others => '0' );
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
high_bus_3_0 => mix_logic1_bus_1, -- Ground wire_low port
low_bit_aa => mix_logic0_1,
mix_logic0_bus_2 => mix_logic0_bus_2, -- Ground port
mix_logic1_0 => mix_logic1_0, -- Wire bit to high
part_zero => part_zero -- Wire two bits to port
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
low_bus_6_0 => mix_logic0_bus_3, -- Wide low port
port_part_zero_u(1 downto 0) => part_zero(3 downto 2), -- Wire two bits to port
port_part_zero_u(3 downto 2) => mix_logic0_bus_4 -- __W_PORT -- Wire two bits to low
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
;
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
;
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
;
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
9218add14e47a385372b7423c4d831e1
| 0.613679 | 2.970874 | false | false | false | false |
mitchsm/nvc
|
test/lower/signal4.vhd
| 4 | 331 |
entity signal4 is
end entity;
architecture test of signal4 is
signal s : bit_vector(3 downto 0) := (1 => '1', others => '0');
begin
process is
variable v : bit_vector(3 downto 0) := (others => '1');
begin
v(2) := s(3);
s <= v;
v := s;
wait;
end process;
end architecture;
|
gpl-3.0
|
e9b1039d22d354eb3ee6f29b21bcf634
| 0.522659 | 3.343434 | false | true | false | false |
DacHt/CU_Droptest
|
component/work/CU_Main_tst/CU_Main_tst.vhd
| 1 | 2,881 |
----------------------------------------------------------------------
-- Created by SmartDesign Fri Apr 14 17:30:23 2017
-- Version: v11.8 11.8.0.26
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
use proasic3.all;
----------------------------------------------------------------------
-- CU_Main_tst entity declaration
----------------------------------------------------------------------
entity CU_Main_tst is
-- Port list
port(
-- Inputs
CLK : in std_logic;
-- Outputs
LED1 : out std_logic;
LED2 : out std_logic
);
end CU_Main_tst;
----------------------------------------------------------------------
-- CU_Main_tst architecture body
----------------------------------------------------------------------
architecture RTL of CU_Main_tst is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- CU_Main
component CU_Main
-- Port list
port(
-- Inputs
CLK : in std_logic;
-- Outputs
BEACON_PWR : out std_logic;
CUTTER_EN : out std_logic;
LDO_FRONTEND_PWR : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
PR_OP_PWR : out std_logic;
STX_PWR : out std_logic;
V3_LINEAR_PWR : out std_logic
);
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal LED1_net_0 : std_logic;
signal LED2_net_0 : std_logic;
signal LED1_net_1 : std_logic;
signal LED2_net_1 : std_logic;
begin
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
LED1_net_1 <= LED1_net_0;
LED1 <= LED1_net_1;
LED2_net_1 <= LED2_net_0;
LED2 <= LED2_net_1;
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- CU_Main_0
CU_Main_0 : CU_Main
port map(
-- Inputs
CLK => CLK,
-- Outputs
LED1 => LED1_net_0,
CUTTER_EN => OPEN,
PR_OP_PWR => OPEN,
STX_PWR => OPEN,
V3_LINEAR_PWR => OPEN,
BEACON_PWR => OPEN,
LDO_FRONTEND_PWR => OPEN,
LED2 => LED2_net_0
);
end RTL;
|
mit
|
40ab2ef376da2ffed95d17eed0afc39d
| 0.317251 | 5.153846 | false | false | false | false |
mitchsm/nvc
|
test/regress/signal1.vhd
| 5 | 468 |
entity signal1 is
end entity;
architecture test of signal1 is
signal x : integer := 5;
begin
process is
begin
assert x = 5 report "initial value not 5";
x <= 6;
assert x = 5 report "x changed after nb assign";
wait for 1 ns;
assert x = 6 report "x not updated";
x <= 7;
wait for 0 ns;
assert x = 7 report "x not updated after delta cycle";
wait;
end process;
end architecture;
|
gpl-3.0
|
c419e613fbe1052e59c298d9b51fefbb
| 0.57265 | 4.034483 | false | false | false | false |
xieguigang/GCModeller
|
src/GCModeller/engine/assembly/demo_hsa.vhd
| 2 | 2,276 |
-- Example of the GCModeller assembly script for
-- compile a virtual vell data model file
-- *.vhd GCModeller virtual assembly script
--
-- V virtual cell
-- H habiliment
-- D dialog
-- build a new virtual cell model from a base model
-- which the base model is named hsa and version label is
-- 20200929
--
-- if the version label is missing, then the latest model
-- of the specific name "hsa" in your repository will be
-- used
FROM hsa:20200929
-- add meta data for your new model
-- MAINTAINER is a kind of shortcut of the
-- LABEL maintainer="xxx"
MAINTAINER xieguigang "<[email protected]>"
-- keyword is a term list that used for registry indexing
-- of your generated virtual cell model
-- these keywords is used for local repository search and
-- online search.
--
-- the quot character can be omit if the keyword contains no
-- white space
-- and each keyword terms should be seperated by the comma
-- symbol
KEYWORDS hsa,"Human Diseases"
-- the label is apply for add meta data to your virtual
-- cell data model
-- label meta is written in key-string_value pair format
-- the meta data key is not limited on number, andalso
-- you can add any meta name as you wish
LABEL version="1.0",day="2020-10-01"
LABEL author="xieguigang <[email protected]>"
LABEL about="blabla"
LABEL url="https://gcmodeller.org"
-- set compiler environment variables
-- the environment variable could affect some compiler
-- behaviors
ENV name="value"
ENV name2="value2"
-- do virtual cell model modifications
-- example of add enzyme by a specific kegg ortholog id
-- this usually could reshape the metabolic network
-- structure
ADD K00087,K00106,K11177,K11178,K13479,K13480,K13482
-- example of add enzyme by specific a kegg orthology
-- category.
-- this command will add all enzymes in the specific
-- category
ADD KO:"Human Diseases\Neurodegenerative disease\*"
-- as the same as the ADD command, DELETE command also can
-- accept a list of KO id or category match for removes the
-- specific enzymes from the base model for create a new
-- model
-- example of delete enzyme by specific a kegg orthology
-- category.
-- this command will removes all enzymes under the
-- specific category.
DELETE KO:"Human Diseases\Substance dependence\*"
|
gpl-3.0
|
1aa153895302f190d69c8f8f12fffd53
| 0.749561 | 3.545171 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare1.vhd
| 1 | 4,446 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare1.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
aeb : OUT STD_LOGIC
);
END lpm_compare1;
ARCHITECTURE SYN OF lpm_compare1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aeb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(10 DOWNTO 0) <= "00001100100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
aeb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 11
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
aeb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "100"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "11"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
-- Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL "dataa[10..0]"
-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
-- Retrieval info: CONNECT: @datab 0 0 11 0 100 0 0 11 0
-- Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
6b944de26fc0123ca6b0ec22bc54cdff
| 0.656095 | 3.698835 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab21.vhd
| 4 | 997 |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
fa7630cf8de3eab7508612badb34a777
| 0.407222 | 3.70632 | false | false | false | false |
mitchsm/nvc
|
test/regress/wait4.vhd
| 5 | 649 |
entity wait4 is
end entity;
architecture test of wait4 is
signal x, y, z : bit;
begin
proc_a: process is
begin
wait for 1 ns;
y <= '1';
wait for 1 ns;
z <= '1';
wait for 1 ns;
assert x = '1';
wait;
end process;
proc_b: process is
begin
wait on x, y;
assert y = '1';
assert now = 1 ns;
assert y'event report "not y'event";
assert not x'event report "x'event";
wait on z;
assert not x'event;
assert z'event;
assert z = '1';
x <= '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
18051440dacf74c930c7a34931e6ab27
| 0.48228 | 3.625698 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_ea_e-rtl-a.vhd
| 1 | 7,439 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Tue Sep 27 05:31:52 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-rtl-a.vhd,v 1.2 2006/06/22 07:20:00 wig Exp $
-- $Date: 2006/06/22 07:20:00 $
-- $Log: inst_ea_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:20:00 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.58 2005/09/14 14:40:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ea_e
--
architecture rtl of inst_ea_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eaa_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eaa_e
mbist_clut_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_fifo_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
reset_n : in std_ulogic;
reset_n_s : in std_ulogic
-- End of Generated Port for Entity inst_eaa_e
);
end component;
-- ---------
component inst_eab_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eab_e
nreset : in std_ulogic;
nreset_s : in std_ulogic;
v_select : in std_ulogic_vector(5 downto 0)
-- End of Generated Port for Entity inst_eab_e
);
end component;
-- ---------
component inst_eac_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eac_e
adp_bist_fail : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
cp_laddr : in std_ulogic_vector(31 downto 0);
cp_lcmd : in std_ulogic_vector(6 downto 0);
cpu_bist_fail : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
cvi_sbist_fail0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
cvi_sbist_fail1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ema_bist_fail : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ga_sbist_fail0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ga_sbist_fail1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpio_int : out std_ulogic_vector(4 downto 0);
ifu_bist_fail : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mcu_bist_fail : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nreset : in std_ulogic;
nreset_s : in std_ulogic;
pdu_bist_fail0 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
pdu_bist_fail1 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
tmu_dac_reset : out std_ulogic;
tsd_bist_fail : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_eac_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_bus_1 : std_ulogic_vector(5 downto 0);
signal cp_laddr : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal gpio_int : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal tmu_dac_reset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
mix_logic0_0 <= '0';
mix_logic0_2 <= '0';
mix_logic0_bus_1 <= ( others => '0' );
cp_laddr(31 downto 1) <= p_mix_cp_laddr_31_1_gi(30 downto 0); -- __I_I_SLICE_PORT
cp_lcmd(6) <= p_mix_cp_lcmd_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_gpio_int_4_0_go <= gpio_int; -- __I_O_BUS_PORT
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
tmi_sbist_fail(11 downto 10) <= p_mix_tmi_sbist_fail_11_10_gi(1 downto 0); -- __I_I_SLICE_PORT
p_mix_tmi_sbist_fail_9_0_go(9 downto 0) <= tmi_sbist_fail(9 downto 0); -- __I_O_SLICE_PORT
p_mix_tmu_dac_reset_go <= tmu_dac_reset; -- __I_O_BIT_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eaa
inst_eaa: inst_eaa_e
port map (
mbist_clut_fail_o => tmi_sbist_fail(8),
mbist_fifo_fail_o => tmi_sbist_fail(9),
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_eaa
-- Generated Instance Port Map for inst_eab
inst_eab: inst_eab_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
v_select(0) => mix_logic0_0, -- __I_BIT_TO_BUSPORT -- GuestBusLBC(memorymappedI/O)Interface
v_select(1) => mix_logic0_0, -- __I_BIT_TO_BUSPORT -- GuestBusLBC(memorymappedI/O)Interface
v_select(2) => v_select(2), -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
v_select(3) => mix_logic0_0, -- __I_BIT_TO_BUSPORT -- GuestBusLBC(memorymappedI/O)Interface
v_select(4) => mix_logic0_0, -- __I_BIT_TO_BUSPORT -- GuestBusLBC(memorymappedI/O)Interface
v_select(5) => v_select(5) -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_eab
-- Generated Instance Port Map for inst_eac
inst_eac: inst_eac_e
port map (
adp_bist_fail => tmi_sbist_fail(0),
cp_laddr(0) => mix_logic0_2, -- __I_BIT_TO_BUSPORT -- GuestBusLBC(memorymappedI/O)Interface
cp_laddr(31 downto 1) => cp_laddr(31 downto 1), -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
cp_lcmd(5 downto 0) => mix_logic0_bus_1, -- __W_PORT
cp_lcmd(6) => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
cpu_bist_fail => tmi_sbist_fail(1),
cvi_sbist_fail0 => tmi_sbist_fail(10),
cvi_sbist_fail1 => tmi_sbist_fail(11),
ema_bist_fail => tmi_sbist_fail(7),
ga_sbist_fail0 => tmi_sbist_fail(8),
ga_sbist_fail1 => tmi_sbist_fail(9),
gpio_int => gpio_int, -- GPIOWakeUPSignalsInterruptinputs
ifu_bist_fail => tmi_sbist_fail(6),
mcu_bist_fail => tmi_sbist_fail(2),
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
pdu_bist_fail0 => tmi_sbist_fail(3),
pdu_bist_fail1 => tmi_sbist_fail(4),
tmu_dac_reset => tmu_dac_reset, -- CADCTestModeRGBADAC
tsd_bist_fail => tmi_sbist_fail(5)
);
-- End of Generated Instance Port Map for inst_eac
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
863f65cdedf0ca9c9e2d919413503eb8
| 0.640678 | 2.828517 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/MUX_2.vhd
| 2 | 1,322 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:42:26 11/25/2013
-- Design Name:
-- Module Name: MUX_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_2 is
Port ( SELEC : in STD_LOGIC;
SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
end MUX_2;
architecture Behavioral of MUX_2 is
begin
process(SRC_1, SRC_2, SELEC)
begin
case SELEC is
when '0' =>
OUTPUT <= SRC_1;
when '1' =>
OUTPUT <= SRC_2;
when others =>
OUTPUT <= HIGH_RESIST;
end case;
end process;
end Behavioral;
|
apache-2.0
|
09a64a6c5a31e18b1024d787d14ad5da
| 0.571104 | 3.66205 | false | false | false | false |
mitchsm/nvc
|
test/regress/attr8.vhd
| 5 | 648 |
entity attr8 is
end entity;
architecture test of attr8 is
begin
process is
type myint is range 1 to 3;
subtype myint_sub is myint range 1 to 2;
variable x : integer;
begin
assert myint'val(1) = 1;
assert myint'val(2) = 2;
x := 1;
assert myint'val(x) = 1;
x := 2;
assert myint'val(x) = 2;
assert myint_sub'val(2) = 2;
assert myint_sub'val(x) = 2;
assert myint'pos(myint(x)) = x;
assert myint_sub'pos(myint(x)) = x;
assert myint'pos(1) = 1;
assert myint_sub'pos(1) = 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
5254c5adf6d07db06b7f7ce7d9058dbb
| 0.537037 | 3.28934 | false | false | false | false |
blutsvente/MIX
|
Resources/Examples/a_clk_20030129/PADS_struct-a.vhd
| 1 | 3,674 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for PADS_struct
--
-- Generated by wig
-- on Wed Jan 29 16:39:40 2003
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template
--
-- Generator: mix_0.pl /mix/0.1, [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
--
--
-- Start of Generated Architecture PADS_struct
--
architecture PADS_struct of PADS is
--
-- Components
--
-- Generated Components
component padcell
port (
-- generated
-- NO OUT PORTs : ;
EI : in std_ulogic;
EO : out std_ulogic
-- end of generated port
);
end component;
-- ---------
component padcell_4_e
port (
-- generated
EI : in std_ulogic;
EO : out std_ulogic
-- end of generated port
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signals
--
signal __LOGIC0__ : __E_TYPE_MISMATCH(3 downto 0);
signal pad_conn_1_2 : std_ulogic;
signal pad_conn_2_3 : std_ulogic;
signal pad_conn_3_4 : std_ulogic;
signal pad_conn_4_5 : std_ulogic;
signal pad_conn_5_6 : std_ulogic;
signal pad_conn_6_7 : std_ulogic;
signal pad_conn_7_8 : std_ulogic;
signal pad_conn_8_9 : std_ulogic;
signal pad_conn_9_10 : std_ulogic;
--
-- End of Generated Signals
--
-- %CONSTANTS%
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
__LOGIC0__ <= '0';
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for Pad_1
Pad_1: padcell PORT MAP(
EI => __LOGIC0__,
EO => pad_conn_1_2
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_10
Pad_10: padcell PORT MAP(
EI => pad_conn_9_10
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_2
Pad_2: padcell PORT MAP(
EI => pad_conn_1_2,
EO => pad_conn_2_3
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_3
Pad_3: padcell PORT MAP(
EI => pad_conn_2_3,
EO => pad_conn_3_4
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_4
Pad_4: padcell_4_e PORT MAP(
EI => pad_conn_3_4,
EO => pad_conn_4_5
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_5
Pad_5: padcell PORT MAP(
EI => pad_conn_4_5,
EO => pad_conn_5_6
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_6
Pad_6: padcell PORT MAP(
EI => pad_conn_5_6,
EO => pad_conn_6_7
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_7
Pad_7: padcell PORT MAP(
EI => pad_conn_6_7,
EO => pad_conn_7_8
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_8
Pad_8: padcell PORT MAP(
EI => pad_conn_7_8,
EO => pad_conn_8_9
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for Pad_9
Pad_9: padcell PORT MAP(
EI => pad_conn_8_9,
EO => pad_conn_9_10
);
-- End of Generated Instance Port Map
end PADS_struct;
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
cf297d69a46b83a3d46931f5b134f2ca
| 0.544366 | 3.16179 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_constant0.vhd
| 3 | 3,472 |
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(8 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 9
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
-- Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
23c3ef7f22915267da50f402010e0e21
| 0.645161 | 3.823789 | false | false | false | false |
mitchsm/nvc
|
test/sem/access.vhd
| 3 | 2,388 |
package p is
type int_ptr is access integer; -- OK
type bad1 is access foo; -- Error
type rec;
type rec_ptr is access rec;
type rec is record
value : integer;
link : rec_ptr;
end record;
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
type string_ptr is access string;
end package;
package body p is
procedure test is
variable v : int_ptr;
variable i : integer;
variable r : rec_ptr;
variable a : int_vec_ptr;
variable s : string_ptr;
begin
v := null; -- OK
i := null; -- Error
deallocate(v); -- OK
v := new integer; -- OK
v := new integer'(5); -- OK
v := new 5; -- Error
v := new i; -- Error
v.all := 5; -- OK
v := 5; -- Error
i := v.all + 5; -- OK
r := new rec; -- OK
r.all.value := 1; -- OK
r.value := 1; -- OK
r.link := r; -- OK
r.link := r.all; -- Error
i := r.value; -- OK
r := r.all.link; -- OK
a := new int_vec(1 to 3); -- OK
a.all(5) := 2; -- OK
a(5) := 2; -- OK
a(1 to 2) := (1, 2); -- OK
s := new string'(""); -- OK
s := new integer'(1); -- Error
s := new s(1 to 3); -- Error
end procedure;
procedure test2(x : inout rec_ptr) is
begin
x.value := x.value + 1;
end procedure;
procedure test3 is
type a;
type a is access integer; -- OK
variable v : a; -- OK
begin
end procedure;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array; -- Error
x := new int_ptr_array(1 to 3); -- OK
x.all := (null, null, null); -- OK
end procedure;
end package body;
|
gpl-3.0
|
f58bcc727aee9a2f6597af07aa4ce00a
| 0.401173 | 4.047458 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/given/a_clk-rtl-a.vhd
| 1 | 32,150 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-a.vhd,v 1.2 2005/07/19 07:13:15 wig Exp $
-- $Date: 2005/07/19 07:13:15 $
-- $Log: a_clk-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:15 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of a_clk
--
architecture rtl of a_clk is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component a_fsm --
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
clk : in std_ulogic;
d9_core_di : in std_ulogic_vector(1 downto 0);
d9_core_en : in std_ulogic_vector(1 downto 0);
d9_core_pu : in std_ulogic_vector(1 downto 0);
data_core_do : out std_ulogic_vector(1 downto 0);
data_core_i33 : in std_ulogic_vector(7 downto 0);
data_core_i34 : in std_ulogic_vector(7 downto 0);
data_core_o35 : out std_ulogic_vector(7 downto 0);
data_core_o36 : out std_ulogic_vector(7 downto 0);
data_i1 : in std_ulogic_vector(7 downto 0);
data_o1 : out std_ulogic_vector(7 downto 0);
di : in std_ulogic_vector(7 downto 0);
di2 : in std_ulogic_vector(8 downto 0);
disp2_en : in std_ulogic_vector(7 downto 0);
disp_ls_port : out std_ulogic;
disp_ms_port : out std_ulogic;
iosel_bus : out std_ulogic_vector(7 downto 0);
iosel_bus_disp : out std_ulogic;
iosel_bus_ls_hr : out std_ulogic;
iosel_bus_ls_min : out std_ulogic;
iosel_bus_ms_hr : out std_ulogic;
iosel_bus_ms_min : out std_ulogic;
iosel_bus_nosel : out std_ulogic;
iosel_bus_port : out std_ulogic_vector(7 downto 0);
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component ios_e --
-- No Generated Generics
port (
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end component;
-- ---------
component pad_pads_e --
-- No Generated Generics
port (
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end component;
-- ---------
component testctrl_e --
-- No Generated Generics
port (
-- Generated Port for Entity testctrl_e
nand_dir : out std_ulogic;
nand_en : out std_ulogic
-- End of Generated Port for Entity testctrl_e
);
end component;
-- ---------
component alreg --
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4 --
-- No Generated Generics
port (
-- Generated Port for Entity count4
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4 --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad --
-- No Generated Generics
port (
-- Generated Port for Entity keypad
columns : in std_ulogic_vector(2 downto 0);
rows : out std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan --
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen --
-- No Generated Generics
port (
-- Generated Port for Entity timegen
one_minute : out std_ulogic;
one_second : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_di : std_ulogic_vector(1 downto 0);
signal d9_do : std_ulogic_vector(1 downto 0);
signal d9_en : std_ulogic_vector(1 downto 0);
signal d9_pu : std_ulogic_vector(1 downto 0);
signal data_i1 : std_ulogic_vector(7 downto 0);
signal data_i33 : std_ulogic_vector(7 downto 0);
signal data_i34 : std_ulogic_vector(7 downto 0);
signal data_o1 : std_ulogic_vector(7 downto 0);
signal data_o35 : std_ulogic_vector(7 downto 0);
signal data_o36 : std_ulogic_vector(7 downto 0);
signal di2 : std_ulogic_vector(8 downto 0);
signal disp2 : std_ulogic_vector(7 downto 0);
signal disp2_en : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic;
signal s_int_display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic;
signal s_int_display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic;
signal iosel_1 : std_ulogic;
signal iosel_2 : std_ulogic;
signal iosel_3 : std_ulogic;
signal iosel_4 : std_ulogic;
signal iosel_5 : std_ulogic;
-- __I_OUT_OPEN signal iosel_6 : std_ulogic;
-- __I_OUT_OPEN signal iosel_7 : std_ulogic;
signal iosel_bus : std_ulogic_vector(7 downto 0);
signal iosel_disp : std_ulogic;
signal iosel_ls_hr : std_ulogic;
signal iosel_ls_min : std_ulogic;
signal iosel_ms_hr : std_ulogic;
-- __I_OUT_OPEN signal iosel_ms_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_nosel : std_ulogic;
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal nand_dir : std_ulogic;
-- __I_OUT_OPEN signal nand_en : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal pad_di_1 : std_ulogic;
signal pad_di_12 : std_ulogic;
signal pad_di_13 : std_ulogic;
signal pad_di_14 : std_ulogic;
signal pad_di_15 : std_ulogic;
signal pad_di_16 : std_ulogic;
signal pad_di_17 : std_ulogic;
signal pad_di_18 : std_ulogic;
signal pad_di_31 : std_ulogic;
signal pad_di_32 : std_ulogic;
signal pad_di_33 : std_ulogic;
signal pad_di_34 : std_ulogic;
signal pad_di_39 : std_ulogic;
signal pad_di_40 : std_ulogic;
signal pad_do_12 : std_ulogic;
signal pad_do_13 : std_ulogic;
signal pad_do_14 : std_ulogic;
signal pad_do_15 : std_ulogic;
signal pad_do_16 : std_ulogic;
signal pad_do_17 : std_ulogic;
signal pad_do_18 : std_ulogic;
signal pad_do_2 : std_ulogic;
signal pad_do_31 : std_ulogic;
signal pad_do_32 : std_ulogic;
signal pad_do_35 : std_ulogic;
signal pad_do_36 : std_ulogic;
signal pad_do_39 : std_ulogic;
signal pad_do_40 : std_ulogic;
signal pad_en_12 : std_ulogic;
signal pad_en_13 : std_ulogic;
signal pad_en_14 : std_ulogic;
signal pad_en_15 : std_ulogic;
signal pad_en_16 : std_ulogic;
signal pad_en_17 : std_ulogic;
signal pad_en_18 : std_ulogic;
signal pad_en_2 : std_ulogic;
signal pad_en_31 : std_ulogic;
signal pad_en_32 : std_ulogic;
signal pad_en_35 : std_ulogic;
signal pad_en_36 : std_ulogic;
signal pad_en_39 : std_ulogic;
signal pad_en_40 : std_ulogic;
signal pad_pu_31 : std_ulogic;
signal pad_pu_32 : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
display_ls_hr <= s_int_display_ls_hr; -- __I_O_BUS_PORT
display_ls_min <= s_int_display_ls_min; -- __I_O_BUS_PORT
display_ms_hr <= s_int_display_ms_hr; -- __I_O_BUS_PORT
display_ms_min <= s_int_display_ms_min; -- __I_O_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
clk => clk,
d9_core_di => d9_di, -- d9io
d9_core_en => d9_en, -- d9io
d9_core_pu => d9_pu, -- d9io
data_core_do => d9_do, -- d9io
data_core_i33 => data_i33, -- io data
data_core_i34 => data_i34, -- io data
data_core_o35 => data_o35, -- io data
data_core_o36 => data_o36, -- io data
data_i1 => data_i1, -- io data
data_o1 => data_o1, -- io data
di => disp2, -- io data
di2 => di2, -- io data
disp2_en => disp2_en, -- io data
disp_ls_port => display_ls_en, -- io_enable
disp_ms_port => display_ms_en, -- io_enable
iosel_bus(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(6) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(7) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus_disp => iosel_disp, -- IO_Select
iosel_bus_ls_hr => iosel_ls_hr, -- IO_Select
iosel_bus_ls_min => iosel_ls_min, -- IO_Select
iosel_bus_ms_hr => iosel_ms_hr, -- IO_Select
iosel_bus_ms_min => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_nosel => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_port => iosel_bus, -- io data
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset,
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for ios
ios: ios_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18, -- pad output enable
p_mix_pad_en_2_go => pad_en_2, -- pad output enable
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ios
-- Generated Instance Port Map for pad_pads
pad_pads: pad_pads_e
port map (
p_mix_pad_di_12_go => pad_di_12, -- data in from pad
p_mix_pad_di_13_go => pad_di_13, -- data in from pad
p_mix_pad_di_14_go => pad_di_14, -- data in from pad
p_mix_pad_di_15_go => pad_di_15, -- data in from pad
p_mix_pad_di_16_go => pad_di_16, -- data in from pad
p_mix_pad_di_17_go => pad_di_17, -- data in from pad
p_mix_pad_di_18_go => pad_di_18, -- data in from pad
p_mix_pad_di_1_go => pad_di_1, -- data in from pad
p_mix_pad_di_31_go => pad_di_31, -- data in from pad
p_mix_pad_di_32_go => pad_di_32, -- data in from pad
p_mix_pad_di_33_go => pad_di_33, -- data in from pad
p_mix_pad_di_34_go => pad_di_34, -- data in from pad
p_mix_pad_di_39_go => pad_di_39, -- data in from pad
p_mix_pad_di_40_go => pad_di_40, -- data in from pad
p_mix_pad_do_12_gi => pad_do_12, -- data out to pad
p_mix_pad_do_13_gi => pad_do_13, -- data out to pad
p_mix_pad_do_14_gi => pad_do_14, -- data out to pad
p_mix_pad_do_15_gi => pad_do_15, -- data out to pad
p_mix_pad_do_16_gi => pad_do_16, -- data out to pad
p_mix_pad_do_17_gi => pad_do_17, -- data out to pad
p_mix_pad_do_18_gi => pad_do_18, -- data out to pad
p_mix_pad_do_2_gi => pad_do_2, -- data out to pad
p_mix_pad_do_31_gi => pad_do_31, -- data out to pad
p_mix_pad_do_32_gi => pad_do_32, -- data out to pad
p_mix_pad_do_35_gi => pad_do_35, -- data out to pad
p_mix_pad_do_36_gi => pad_do_36, -- data out to pad
p_mix_pad_do_39_gi => pad_do_39, -- data out to pad
p_mix_pad_do_40_gi => pad_do_40, -- data out to pad
p_mix_pad_en_12_gi => pad_en_12, -- pad output enable
p_mix_pad_en_13_gi => pad_en_13, -- pad output enable
p_mix_pad_en_14_gi => pad_en_14, -- pad output enable
p_mix_pad_en_15_gi => pad_en_15, -- pad output enable
p_mix_pad_en_16_gi => pad_en_16, -- pad output enable
p_mix_pad_en_17_gi => pad_en_17, -- pad output enable
p_mix_pad_en_18_gi => pad_en_18, -- pad output enable
p_mix_pad_en_2_gi => pad_en_2, -- pad output enable
p_mix_pad_en_31_gi => pad_en_31, -- pad output enable
p_mix_pad_en_32_gi => pad_en_32, -- pad output enable
p_mix_pad_en_35_gi => pad_en_35, -- pad output enable
p_mix_pad_en_36_gi => pad_en_36, -- pad output enable
p_mix_pad_en_39_gi => pad_en_39, -- pad output enable
p_mix_pad_en_40_gi => pad_en_40, -- pad output enable
p_mix_pad_pu_31_gi => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_gi => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_pads
-- Generated Instance Port Map for test_ctrl
test_ctrl: testctrl_e
port map (
nand_dir => nand_dir, -- Direction (X17)
nand_en => open -- Enable (X17) -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for test_ctrl
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0 -- Display storage buffer 0 ls_min
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1 -- Display storage buffer 1 ms_min
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2 -- Display storage buffer 2 ls_hr
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3 -- Display storage buffer 3 ms_hr
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_display_ls_hr_go => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_go => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_hr_go => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_go => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_sound_alarm_go => sound_alarm,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
columns => columns,
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
one_minute => one_minute,
one_second => one_sec_pulse,
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
f892148387c966de20f4446028aa0dc8
| 0.630078 | 2.441525 | false | false | false | false |
blutsvente/MIX
|
test/results/constant/inst_e_e-rtl-a.vhd
| 1 | 3,056 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.3 2004/08/18 10:47:05 wig Exp $
-- $Date: 2004/08/18 10:47:05 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.3 2004/08/18 10:47:05 wig
-- reworked some testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
bad_width_p : in bit_vector(7 downto 0);
const_06_p : in std_ulogic_vector(6 downto 0);
const_07_p : in std_ulogic_vector(5 downto 0);
zero_dup_e : in std_ulogic
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
constant const_06_c : std_ulogic_vector(6 downto 0) := "0001111"; -- __I_ConvConstant: 0xf
signal const_06 : std_ulogic_vector(6 downto 0);
constant mix_const_0_c : std_ulogic_vector(5 downto 0) := "001111"; -- __I_ConvConstant: 0xf
signal mix_const_0 : std_ulogic_vector(5 downto 0);
constant mix_const_17_c : bit_vector(7 downto 0) := "1010"; -- __I_VectorConv
signal mix_const_17 : bit_vector(7 downto 0);
constant mix_const_19_c : std_ulogic := '0';
signal mix_const_19 : std_ulogic;
constant mix_const_20_c : std_ulogic := '1';
signal mix_const_20 : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
const_06 <= const_06_c;
mix_const_0 <= mix_const_0_c;
mix_const_17 <= mix_const_17_c;
mix_const_19 <= mix_const_19_c;
mix_const_20 <= mix_const_20_c;
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
bad_width_p => mix_const_17, -- #!Illegal
const_06_p => const_06, -- Constant Wire, # take literally, but will not work!
const_07_p => mix_const_0, -- Constant Wire, # take literally, but will not valid VHDL
zero_dup_e => mix_const_19, -- #Illegal
zero_dup_e => mix_const_20 -- #Illegal
);
-- End of Generated Instance Port Map for inst_ea
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
fe83370b91702543be108d8f9e6fb759
| 0.59784 | 3.028741 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_ea_e-rtl-a.vhd
| 1 | 19,747 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_ea_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ea_e
--
architecture rtl of inst_ea_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eaa_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eaa_e
mbist_clut_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_fifo_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
c_addr_i : in std_ulogic_vector(12 downto 0);
c_bus_i : in std_ulogic_vector(31 downto 0); -- CBUSinterface
video_p_0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_0 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_10 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_11 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_12 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_13 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_14 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_15 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_16 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_17 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_18 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_19 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_20 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_21 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_22 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_23 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_24 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_25 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_26 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_27 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_28 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_29 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_3 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_30 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_31 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_4 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_5 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_6 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_7 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_8 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p_9 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
widesig_p : in std_ulogic_vector(30 downto 0);
unsplice_a1_no3 : in std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : in std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : in std_ulogic_vector(100 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : in std_ulogic_vector(97 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : in std_ulogic_vector(99 downto 2); -- connect mid 100 bits
unsplice_bad_a : in std_ulogic_vector(1 downto 0);
unsplice_bad_b : in std_ulogic_vector(3 downto 0); -- # conflict
widemerge_a1_p : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_eaa_e
);
end component;
-- ---------
component inst_eab_e
-- No Generated Generics
-- Generated Generics for Entity inst_eab_e
-- End of Generated Generics for Entity inst_eab_e
port (
-- Generated Port for Entity inst_eab_e
v_select : in std_ulogic_vector(5 downto 0); -- VPUinterface
c_add : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CBUSinterface
video_p_1 : in std_ulogic
-- End of Generated Port for Entity inst_eab_e
);
end component;
-- ---------
component inst_eac_e
-- No Generated Generics
-- Generated Generics for Entity inst_eac_e
-- End of Generated Generics for Entity inst_eac_e
port (
-- Generated Port for Entity inst_eac_e
adp_bist_fail : out std_ulogic;
cpu_bist_fail : out std_ulogic;
ema_bist_fail : out std_ulogic;
ifu_bist_fail : out std_ulogic;
mcu_bist_fail : out std_ulogic;
pdu_bist_fail0 : out std_ulogic;
pdu_bist_fail1 : out std_ulogic;
tsd_bist_fail : out std_ulogic;
cp_lcmd : in std_ulogic_vector(6 downto 0); -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p : in std_ulogic_vector(6 downto 0); -- Signal name != port name
cp_lcmd_2 : in std_ulogic_vector(6 downto 0); -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CBUSinterface
cvi_sbist_fail0 : in std_ulogic;
cvi_sbist_fail1 : in std_ulogic;
ga_sbist_fail0 : in std_ulogic;
ga_sbist_fail1 : in std_ulogic;
video_p_2 : in std_ulogic
-- End of Generated Port for Entity inst_eac_e
);
end component;
-- ---------
component inst_ead_e
-- No Generated Generics
-- Generated Generics for Entity inst_ead_e
-- End of Generated Generics for Entity inst_ead_e
port (
-- Generated Port for Entity inst_ead_e
video_p_3 : in std_ulogic
-- End of Generated Port for Entity inst_ead_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_bus_0 : std_ulogic_vector(5 downto 0);
signal mix_logic0_bus_1 : std_ulogic_vector(5 downto 0);
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd_2 : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
constant cp_lcmd_2_tolow_c : std_ulogic_vector(5 downto 0) := ( others => '0' );
signal cp_lcmd_2_tolow : std_ulogic_vector(5 downto 0);
signal cp_lcmd_3 : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_a : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_b : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widemerge_a1 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_11 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_19 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_20 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_21 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_22 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_23 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_24 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_25 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_26 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_28 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_29 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_30 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_2 <= '0';
mix_logic0_bus_0 <= ( others => '0' );
mix_logic0_bus_1 <= ( others => '0' );
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
cp_lcmd(6) <= p_mix_cp_lcmd_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
cp_lcmd_2(6) <= p_mix_cp_lcmd_2_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
cp_lcmd_2_tolow <= cp_lcmd_2_tolow_c;
cp_lcmd_3(6) <= p_mix_cp_lcmd_3_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
tmi_sbist_fail(11 downto 10) <= p_mix_tmi_sbist_fail_11_10_gi(1 downto 0); -- __I_I_SLICE_PORT
p_mix_tmi_sbist_fail_9_0_go(9 downto 0) <= tmi_sbist_fail(9 downto 0); -- __I_O_SLICE_PORT
unsplice_a1_no3(125 downto 0) <= p_mix_unsplice_a1_no3_125_0_gi(125 downto 0); -- __I_I_SLICE_PORT
unsplice_a1_no3(127) <= p_mix_unsplice_a1_no3_127_127_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_a2_all128 <= p_mix_unsplice_a2_all128_127_0_gi; -- __I_I_BUS_PORT
unsplice_a3_up100(100 downto 0) <= p_mix_unsplice_a3_up100_100_0_gi(100 downto 0); -- __I_I_SLICE_PORT
unsplice_a4_mid100(99 downto 2) <= p_mix_unsplice_a4_mid100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_a5_midp100(99 downto 2) <= p_mix_unsplice_a5_midp100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_bad_a(1) <= p_mix_unsplice_bad_a_1_1_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_bad_b(1 downto 0) <= p_mix_unsplice_bad_b_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
widemerge_a1 <= p_mix_widemerge_a1_31_0_gi; -- __I_I_BUS_PORT
widesig <= p_mix_widesig_31_0_gi; -- __I_I_BUS_PORT
widesig_r_0 <= p_mix_widesig_r_0_gi; -- __I_I_BIT_PORT
widesig_r_1 <= p_mix_widesig_r_1_gi; -- __I_I_BIT_PORT
widesig_r_10 <= p_mix_widesig_r_10_gi; -- __I_I_BIT_PORT
widesig_r_11 <= p_mix_widesig_r_11_gi; -- __I_I_BIT_PORT
widesig_r_12 <= p_mix_widesig_r_12_gi; -- __I_I_BIT_PORT
widesig_r_13 <= p_mix_widesig_r_13_gi; -- __I_I_BIT_PORT
widesig_r_14 <= p_mix_widesig_r_14_gi; -- __I_I_BIT_PORT
widesig_r_15 <= p_mix_widesig_r_15_gi; -- __I_I_BIT_PORT
widesig_r_16 <= p_mix_widesig_r_16_gi; -- __I_I_BIT_PORT
widesig_r_17 <= p_mix_widesig_r_17_gi; -- __I_I_BIT_PORT
widesig_r_18 <= p_mix_widesig_r_18_gi; -- __I_I_BIT_PORT
widesig_r_19 <= p_mix_widesig_r_19_gi; -- __I_I_BIT_PORT
widesig_r_2 <= p_mix_widesig_r_2_gi; -- __I_I_BIT_PORT
widesig_r_20 <= p_mix_widesig_r_20_gi; -- __I_I_BIT_PORT
widesig_r_21 <= p_mix_widesig_r_21_gi; -- __I_I_BIT_PORT
widesig_r_22 <= p_mix_widesig_r_22_gi; -- __I_I_BIT_PORT
widesig_r_23 <= p_mix_widesig_r_23_gi; -- __I_I_BIT_PORT
widesig_r_24 <= p_mix_widesig_r_24_gi; -- __I_I_BIT_PORT
widesig_r_25 <= p_mix_widesig_r_25_gi; -- __I_I_BIT_PORT
widesig_r_26 <= p_mix_widesig_r_26_gi; -- __I_I_BIT_PORT
widesig_r_27 <= p_mix_widesig_r_27_gi; -- __I_I_BIT_PORT
widesig_r_28 <= p_mix_widesig_r_28_gi; -- __I_I_BIT_PORT
widesig_r_29 <= p_mix_widesig_r_29_gi; -- __I_I_BIT_PORT
widesig_r_3 <= p_mix_widesig_r_3_gi; -- __I_I_BIT_PORT
widesig_r_30 <= p_mix_widesig_r_30_gi; -- __I_I_BIT_PORT
widesig_r_4 <= p_mix_widesig_r_4_gi; -- __I_I_BIT_PORT
widesig_r_5 <= p_mix_widesig_r_5_gi; -- __I_I_BIT_PORT
widesig_r_6 <= p_mix_widesig_r_6_gi; -- __I_I_BIT_PORT
widesig_r_7 <= p_mix_widesig_r_7_gi; -- __I_I_BIT_PORT
widesig_r_8 <= p_mix_widesig_r_8_gi; -- __I_I_BIT_PORT
widesig_r_9 <= p_mix_widesig_r_9_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eaa
inst_eaa: inst_eaa_e
port map (
-- __E_PRINTCONN unsplice_bad_a => unsplice_bad_a
c_addr_i => c_addr,
c_bus_i => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
mbist_clut_fail_o => tmi_sbist_fail(8),
mbist_fifo_fail_o => tmi_sbist_fail(9),
unsplice_a1_no3(1 downto 0) => unsplice_a1_no3(1 downto 0), -- leaves 3 unconnected
unsplice_a1_no3(127 downto 4) => unsplice_a1_no3(125 downto 2), -- leaves 3 unconnected
unsplice_a1_no3(2) => unsplice_a1_no3(127), -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
unsplice_bad_b(1 downto 0) => unsplice_bad_b(1 downto 0), -- # conflict
unsplice_bad_b(3 downto 2) => unsplice_bad_b(1 downto 0), -- # conflict
video_p_0 => video_i(0),
widemerge_a1_p => widemerge_a1,
widesig_p(0) => widesig_r_0, -- __I_BIT_TO_BUSPORT
widesig_p(1) => widesig_r_1, -- __I_BIT_TO_BUSPORT
widesig_p(10) => widesig_r_10, -- __I_BIT_TO_BUSPORT
widesig_p(11) => widesig_r_11, -- __I_BIT_TO_BUSPORT
widesig_p(12) => widesig_r_12, -- __I_BIT_TO_BUSPORT
widesig_p(13) => widesig_r_13, -- __I_BIT_TO_BUSPORT
widesig_p(14) => widesig_r_14, -- __I_BIT_TO_BUSPORT
widesig_p(15) => widesig_r_15, -- __I_BIT_TO_BUSPORT
widesig_p(16) => widesig_r_16, -- __I_BIT_TO_BUSPORT
widesig_p(17) => widesig_r_17, -- __I_BIT_TO_BUSPORT
widesig_p(18) => widesig_r_18, -- __I_BIT_TO_BUSPORT
widesig_p(19) => widesig_r_19, -- __I_BIT_TO_BUSPORT
widesig_p(2) => widesig_r_2, -- __I_BIT_TO_BUSPORT
widesig_p(20) => widesig_r_20, -- __I_BIT_TO_BUSPORT
widesig_p(21) => widesig_r_21, -- __I_BIT_TO_BUSPORT
widesig_p(22) => widesig_r_22, -- __I_BIT_TO_BUSPORT
widesig_p(23) => widesig_r_23, -- __I_BIT_TO_BUSPORT
widesig_p(24) => widesig_r_24, -- __I_BIT_TO_BUSPORT
widesig_p(25) => widesig_r_25, -- __I_BIT_TO_BUSPORT
widesig_p(26) => widesig_r_26, -- __I_BIT_TO_BUSPORT
widesig_p(27) => widesig_r_27, -- __I_BIT_TO_BUSPORT
widesig_p(28) => widesig_r_28, -- __I_BIT_TO_BUSPORT
widesig_p(29) => widesig_r_29, -- __I_BIT_TO_BUSPORT
widesig_p(3) => widesig_r_3, -- __I_BIT_TO_BUSPORT
widesig_p(30) => widesig_r_30, -- __I_BIT_TO_BUSPORT
widesig_p(4) => widesig_r_4, -- __I_BIT_TO_BUSPORT
widesig_p(5) => widesig_r_5, -- __I_BIT_TO_BUSPORT
widesig_p(6) => widesig_r_6, -- __I_BIT_TO_BUSPORT
widesig_p(7) => widesig_r_7, -- __I_BIT_TO_BUSPORT
widesig_p(8) => widesig_r_8, -- __I_BIT_TO_BUSPORT
widesig_p(9) => widesig_r_9, -- __I_BIT_TO_BUSPORT
widesig_p_0 => widesig(0),
widesig_p_1 => widesig(1),
widesig_p_10 => widesig(10),
widesig_p_11 => widesig(11),
widesig_p_12 => widesig(12),
widesig_p_13 => widesig(13),
widesig_p_14 => widesig(14),
widesig_p_15 => widesig(15),
widesig_p_16 => widesig(16),
widesig_p_17 => widesig(17),
widesig_p_18 => widesig(18),
widesig_p_19 => widesig(19),
widesig_p_2 => widesig(2),
widesig_p_20 => widesig(20),
widesig_p_21 => widesig(21),
widesig_p_22 => widesig(22),
widesig_p_23 => widesig(23),
widesig_p_24 => widesig(24),
widesig_p_25 => widesig(25),
widesig_p_26 => widesig(26),
widesig_p_27 => widesig(27),
widesig_p_28 => widesig(28),
widesig_p_29 => widesig(29),
widesig_p_3 => widesig(3),
widesig_p_30 => widesig(30),
widesig_p_31 => widesig(31),
widesig_p_4 => widesig(4),
widesig_p_5 => widesig(5),
widesig_p_6 => widesig(6),
widesig_p_7 => widesig(7),
widesig_p_8 => widesig(8),
widesig_p_9 => widesig(9)
);
-- End of Generated Instance Port Map for inst_eaa
-- Generated Instance Port Map for inst_eab
inst_eab: inst_eab_e
port map (
c_add => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
v_select(0) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(1) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(2) => v_select(2), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
v_select(3) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(4) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
v_select(5) => v_select(5), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
video_p_1 => video_i(1)
);
-- End of Generated Instance Port Map for inst_eab
-- Generated Instance Port Map for inst_eac
inst_eac: inst_eac_e
port map (
adp_bist_fail => tmi_sbist_fail(0),
c_addr => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
cp_lcmd(5 downto 0) => mix_logic0_bus_0, -- __W_PORT
cp_lcmd(6) => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_2(5 downto 0) => cp_lcmd_2_tolow, -- __W_PORT
cp_lcmd_2(6) => cp_lcmd_2(6), -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p(5 downto 0) => mix_logic0_bus_1, -- __W_PORT
cp_lcmd_p(6) => cp_lcmd_3(6), -- Signal name != port name
cpu_bist_fail => tmi_sbist_fail(1),
cvi_sbist_fail0 => tmi_sbist_fail(10),
cvi_sbist_fail1 => tmi_sbist_fail(11),
ema_bist_fail => tmi_sbist_fail(7),
ga_sbist_fail0 => tmi_sbist_fail(8),
ga_sbist_fail1 => tmi_sbist_fail(9),
ifu_bist_fail => tmi_sbist_fail(6),
mcu_bist_fail => tmi_sbist_fail(2),
pdu_bist_fail0 => tmi_sbist_fail(3),
pdu_bist_fail1 => tmi_sbist_fail(4),
tsd_bist_fail => tmi_sbist_fail(5),
video_p_2 => video_i(2)
);
-- End of Generated Instance Port Map for inst_eac
-- Generated Instance Port Map for inst_ead
inst_ead: inst_ead_e
port map (
video_p_3 => video_i(3)
);
-- End of Generated Instance Port Map for inst_ead
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
bdfe4e7eeab6e53d91597c346b28627c
| 0.635641 | 2.464678 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/inst_t_e-rtl-a.vhd
| 1 | 12,020 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.4 2006/06/22 07:20:00 wig Exp $
-- $Date: 2006/06/22 07:20:00 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/22 07:20:00 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_test1_go : out std_ulogic;
unsplice_a1_no3 : out std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : out std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : out std_ulogic_vector(127 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_bad_a : out std_ulogic_vector(127 downto 0);
unsplice_bad_b : out std_ulogic_vector(127 downto 0);
widemerge_a1 : out std_ulogic_vector(31 downto 0);
widesig_o : out std_ulogic_vector(31 downto 0);
widesig_r_0 : out std_ulogic;
widesig_r_1 : out std_ulogic;
widesig_r_10 : out std_ulogic;
widesig_r_11 : out std_ulogic;
widesig_r_12 : out std_ulogic;
widesig_r_13 : out std_ulogic;
widesig_r_14 : out std_ulogic;
widesig_r_15 : out std_ulogic;
widesig_r_16 : out std_ulogic;
widesig_r_17 : out std_ulogic;
widesig_r_18 : out std_ulogic;
widesig_r_19 : out std_ulogic;
widesig_r_2 : out std_ulogic;
widesig_r_20 : out std_ulogic;
widesig_r_21 : out std_ulogic;
widesig_r_22 : out std_ulogic;
widesig_r_23 : out std_ulogic;
widesig_r_24 : out std_ulogic;
widesig_r_25 : out std_ulogic;
widesig_r_26 : out std_ulogic;
widesig_r_27 : out std_ulogic;
widesig_r_28 : out std_ulogic;
widesig_r_29 : out std_ulogic;
widesig_r_3 : out std_ulogic;
widesig_r_30 : out std_ulogic;
widesig_r_4 : out std_ulogic;
widesig_r_5 : out std_ulogic;
widesig_r_6 : out std_ulogic;
widesig_r_7 : out std_ulogic;
widesig_r_8 : out std_ulogic;
widesig_r_9 : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
port_b_1 : in std_ulogic
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_c_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_d_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_e_e
p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_widesig_r_0_gi : in std_ulogic;
p_mix_widesig_r_10_gi : in std_ulogic;
p_mix_widesig_r_11_gi : in std_ulogic;
p_mix_widesig_r_12_gi : in std_ulogic;
p_mix_widesig_r_13_gi : in std_ulogic;
p_mix_widesig_r_14_gi : in std_ulogic;
p_mix_widesig_r_15_gi : in std_ulogic;
p_mix_widesig_r_16_gi : in std_ulogic;
p_mix_widesig_r_17_gi : in std_ulogic;
p_mix_widesig_r_18_gi : in std_ulogic;
p_mix_widesig_r_19_gi : in std_ulogic;
p_mix_widesig_r_1_gi : in std_ulogic;
p_mix_widesig_r_20_gi : in std_ulogic;
p_mix_widesig_r_21_gi : in std_ulogic;
p_mix_widesig_r_22_gi : in std_ulogic;
p_mix_widesig_r_23_gi : in std_ulogic;
p_mix_widesig_r_24_gi : in std_ulogic;
p_mix_widesig_r_25_gi : in std_ulogic;
p_mix_widesig_r_26_gi : in std_ulogic;
p_mix_widesig_r_27_gi : in std_ulogic;
p_mix_widesig_r_28_gi : in std_ulogic;
p_mix_widesig_r_29_gi : in std_ulogic;
p_mix_widesig_r_2_gi : in std_ulogic;
p_mix_widesig_r_30_gi : in std_ulogic;
p_mix_widesig_r_3_gi : in std_ulogic;
p_mix_widesig_r_4_gi : in std_ulogic;
p_mix_widesig_r_5_gi : in std_ulogic;
p_mix_widesig_r_6_gi : in std_ulogic;
p_mix_widesig_r_7_gi : in std_ulogic;
p_mix_widesig_r_8_gi : in std_ulogic;
p_mix_widesig_r_9_gi : in std_ulogic;
video_i : in std_ulogic_vector(3 downto 0);
widesig_i : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal test1 : std_ulogic;
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0);
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0);
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0);
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0);
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0);
signal unsplice_bad_a : std_ulogic_vector(127 downto 0);
signal unsplice_bad_b : std_ulogic_vector(127 downto 0);
-- __I_NODRV_I signal video_i : std_ulogic_vector(3 downto 0);
signal widemerge_a1 : std_ulogic_vector(31 downto 0);
signal widesig : std_ulogic_vector(31 downto 0);
signal widesig_r_0 : std_ulogic;
signal widesig_r_1 : std_ulogic;
signal widesig_r_10 : std_ulogic;
signal widesig_r_11 : std_ulogic;
signal widesig_r_12 : std_ulogic;
signal widesig_r_13 : std_ulogic;
signal widesig_r_14 : std_ulogic;
signal widesig_r_15 : std_ulogic;
signal widesig_r_16 : std_ulogic;
signal widesig_r_17 : std_ulogic;
signal widesig_r_18 : std_ulogic;
signal widesig_r_19 : std_ulogic;
signal widesig_r_2 : std_ulogic;
signal widesig_r_20 : std_ulogic;
signal widesig_r_21 : std_ulogic;
signal widesig_r_22 : std_ulogic;
signal widesig_r_23 : std_ulogic;
signal widesig_r_24 : std_ulogic;
signal widesig_r_25 : std_ulogic;
signal widesig_r_26 : std_ulogic;
signal widesig_r_27 : std_ulogic;
signal widesig_r_28 : std_ulogic;
signal widesig_r_29 : std_ulogic;
signal widesig_r_3 : std_ulogic;
signal widesig_r_30 : std_ulogic;
signal widesig_r_4 : std_ulogic;
signal widesig_r_5 : std_ulogic;
signal widesig_r_6 : std_ulogic;
signal widesig_r_7 : std_ulogic;
signal widesig_r_8 : std_ulogic;
signal widesig_r_9 : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_test1_go => test1, -- Use internally test1
unsplice_a1_no3 => unsplice_a1_no3, -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100, -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100, -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100, -- connect mid 100 bits
unsplice_bad_a => unsplice_bad_a,
unsplice_bad_b => unsplice_bad_b, -- # conflict
widemerge_a1 => widemerge_a1,
widesig_o => widesig,
widesig_r_0 => widesig_r_0,
widesig_r_1 => widesig_r_1,
widesig_r_10 => widesig_r_10,
widesig_r_11 => widesig_r_11,
widesig_r_12 => widesig_r_12,
widesig_r_13 => widesig_r_13,
widesig_r_14 => widesig_r_14,
widesig_r_15 => widesig_r_15,
widesig_r_16 => widesig_r_16,
widesig_r_17 => widesig_r_17,
widesig_r_18 => widesig_r_18,
widesig_r_19 => widesig_r_19,
widesig_r_2 => widesig_r_2,
widesig_r_20 => widesig_r_20,
widesig_r_21 => widesig_r_21,
widesig_r_22 => widesig_r_22,
widesig_r_23 => widesig_r_23,
widesig_r_24 => widesig_r_24,
widesig_r_25 => widesig_r_25,
widesig_r_26 => widesig_r_26,
widesig_r_27 => widesig_r_27,
widesig_r_28 => widesig_r_28,
widesig_r_29 => widesig_r_29,
widesig_r_3 => widesig_r_3,
widesig_r_30 => widesig_r_30,
widesig_r_4 => widesig_r_4,
widesig_r_5 => widesig_r_5,
widesig_r_6 => widesig_r_6,
widesig_r_7 => widesig_r_7,
widesig_r_8 => widesig_r_8,
widesig_r_9 => widesig_r_9
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
port_b_1 => test1 -- Use internally test1
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: inst_c_e
;
-- End of Generated Instance Port Map for inst_c
-- Generated Instance Port Map for inst_d
inst_d: inst_d_e
;
-- End of Generated Instance Port Map for inst_d
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
p_mix_unsplice_a1_no3_125_0_gi => unsplice_a1_no3(125 downto 0), -- leaves 3 unconnected
p_mix_unsplice_a1_no3_127_127_gi => unsplice_a1_no3(127), -- leaves 3 unconnected
p_mix_unsplice_a2_all128_127_0_gi => unsplice_a2_all128, -- full 128 bit port
p_mix_unsplice_a3_up100_100_0_gi => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
p_mix_unsplice_a4_mid100_99_2_gi => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_a5_midp100_99_2_gi => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_bad_a_1_1_gi => unsplice_bad_a(1),
p_mix_unsplice_bad_b_1_0_gi => unsplice_bad_b(1 downto 0), -- # conflict
p_mix_widemerge_a1_31_0_gi => widemerge_a1,
p_mix_widesig_r_0_gi => widesig_r_0,
p_mix_widesig_r_10_gi => widesig_r_10,
p_mix_widesig_r_11_gi => widesig_r_11,
p_mix_widesig_r_12_gi => widesig_r_12,
p_mix_widesig_r_13_gi => widesig_r_13,
p_mix_widesig_r_14_gi => widesig_r_14,
p_mix_widesig_r_15_gi => widesig_r_15,
p_mix_widesig_r_16_gi => widesig_r_16,
p_mix_widesig_r_17_gi => widesig_r_17,
p_mix_widesig_r_18_gi => widesig_r_18,
p_mix_widesig_r_19_gi => widesig_r_19,
p_mix_widesig_r_1_gi => widesig_r_1,
p_mix_widesig_r_20_gi => widesig_r_20,
p_mix_widesig_r_21_gi => widesig_r_21,
p_mix_widesig_r_22_gi => widesig_r_22,
p_mix_widesig_r_23_gi => widesig_r_23,
p_mix_widesig_r_24_gi => widesig_r_24,
p_mix_widesig_r_25_gi => widesig_r_25,
p_mix_widesig_r_26_gi => widesig_r_26,
p_mix_widesig_r_27_gi => widesig_r_27,
p_mix_widesig_r_28_gi => widesig_r_28,
p_mix_widesig_r_29_gi => widesig_r_29,
p_mix_widesig_r_2_gi => widesig_r_2,
p_mix_widesig_r_30_gi => widesig_r_30,
p_mix_widesig_r_3_gi => widesig_r_3,
p_mix_widesig_r_4_gi => widesig_r_4,
p_mix_widesig_r_5_gi => widesig_r_5,
p_mix_widesig_r_6_gi => widesig_r_6,
p_mix_widesig_r_7_gi => widesig_r_7,
p_mix_widesig_r_8_gi => widesig_r_8,
p_mix_widesig_r_9_gi => widesig_r_9,
-- __I_NODRV_I video_i => __nodrv__/video_i,
widesig_i => widesig
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
b96826574ebe0790c87883dc4c1d1298
| 0.64426 | 2.475288 | false | false | false | false |
blutsvente/MIX
|
test/results/autoopen/inst_a_e-rtl-a.vhd
| 1 | 3,704 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Jul 6 05:51:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_aa_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
port_aa : out std_ulogic;
s_ai14 : out std_ulogic_vector(7 downto 0);
s_ai16 : in std_ulogic_vector(7 downto 0);
s_ai6 : out std_ulogic;
s_ai8 : in std_ulogic;
s_aio17 : inout std_ulogic;
s_aio18 : inout std_ulogic;
s_aio19 : inout std_ulogic;
s_ao1 : out std_ulogic;
s_ao10 : out std_ulogic_vector(7 downto 0);
s_ao11 : out std_ulogic_vector(7 downto 0);
s_ao12 : in std_ulogic_vector(7 downto 0);
s_ao13 : in std_ulogic_vector(7 downto 0);
s_ao2 : out std_ulogic;
s_ao3 : out std_ulogic;
s_ao4 : in std_ulogic;
s_ao5 : out std_ulogic;
s_ao9 : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
s_ao10 : in std_ulogic_vector(7 downto 0);
s_ao2 : in std_ulogic
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_aio17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao10 : std_ulogic_vector(7 downto 0);
signal s_ao11 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao2 : std_ulogic;
signal s_ao3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal s_intname : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
s_aio17 <= p_mix_s_aio17_gc; -- __I_I_BIT_PORT
p_mix_s_ao11_go <= s_ao11; -- __I_O_BUS_PORT
p_mix_s_ao3_go <= s_ao3; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
port map (
-- __I_RECONN port_aa => open, -- __I_OUT_OPEN
port_aa => s_outname,
s_ai14 => s_ai14,
s_ai16 => s_ai16,
s_ai6 => s_ai6,
s_ai8 => s_ai8,
s_aio17 => s_aio17,
s_aio18 => s_aio18,
s_aio19 => s_aio19,
s_ao1 => s_ao1,
s_ao10 => s_ao10,
s_ao11 => s_ao11,
s_ao12 => s_ao12,
s_ao13 => s_ao13,
s_ao2 => s_ao2,
s_ao3 => s_ao3,
s_ao4 => s_ao4,
s_ao5 => s_ao5,
s_ao9 => s_ao9
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
port map (
s_ao10 => s_ao10,
s_ao2 => s_ao2
);
-- End of Generated Instance Port Map for inst_ab
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
c56c5c2668aa418f3656a90bf32159c9
| 0.581803 | 2.566875 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_m2s_adapter.vhd
| 1 | 12,589 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_m2s_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_m2s_converter;
use axis_accelerator_adapter_v2_1_6.xd_m2s_memory_dc;
entity xd_m2s_adapter is
generic (
C_FAMILY : string; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_M_AXIS_TDATA_WIDTH : integer;
C_M_AXIS_TUSER_WIDTH : integer;
C_M_AXIS_TID_WIDTH : integer;
C_M_AXIS_TDEST_WIDTH : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer;
C_AP_ARG_WIDTH : integer;
C_AP_ARG_N_DIM : integer;
C_AP_ARG_DIMS : int_vector;
C_AP_ARG_DIM_1 : integer;
C_AP_ARG_DIM_2 : integer;
C_AP_ARG_FORMAT_TYPE : integer;
C_AP_ARG_FORMAT_FACTOR : integer;
C_AP_ARG_FORMAT_DIM : integer);
port (
-- Output streams
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TKEEP : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TID : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
sw_length : in std_logic_vector(31 downto 0);
sw_length_we : in std_logic;
use_sw_length : in std_logic;
host_oarg_tdest : in std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
ap_clk : in std_logic;
ap_rst_sync : in std_logic;
ap_rst : in std_logic;
ap_arg_addr : in std_logic_vector(C_AP_ARG_ADDR_WIDTH-1 downto 0);
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_rqt : out std_logic;
ap_arg_ack : in std_logic;
ap_arg_empty : out std_logic;
ap_arg_full : out std_logic;
ap_arg_used : out std_logic_vector(3 downto 0)); -- Number of used buffers
end entity;
architecture rtl of xd_m2s_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
function calc_axi_addr_width return integer is
variable addr_width : integer := 0;
begin
if (C_M_AXIS_TDATA_WIDTH > C_AP_ARG_DATA_WIDTH) then
addr_width := C_AP_ARG_ADDR_WIDTH-log2(C_M_AXIS_TDATA_WIDTH/C_AP_ARG_DATA_WIDTH);
else
addr_width := C_AP_ARG_ADDR_WIDTH+log2(C_AP_ARG_DATA_WIDTH/C_M_AXIS_TDATA_WIDTH);
end if;
return addr_width;
end function calc_axi_addr_width;
constant AXI_DATA_WIDTH : integer := C_M_AXIS_TDATA_WIDTH;
constant AXI_ADDR_WIDTH : integer := calc_axi_addr_width;
constant SIZE_WIDTH : integer := C_AP_ARG_ADDR_WIDTH+1+log2(C_AP_ARG_DATA_WIDTH/8);
-- signal ap_rst_sync1 : std_logic;
-- signal ap_rst_sync : std_logic;
signal axis_rst2 : std_logic;
signal axis_rst1 : std_logic;
signal conv_addr : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
signal conv_ce : std_logic;
signal conv_we : std_logic;
signal conv_last : std_logic;
signal conv_rdy : std_logic;
signal conv_data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
-- Number of bytes written by accelerator
signal conv_size : std_logic_vector(SIZE_WIDTH-1 downto 0);
signal axis_rst : std_logic;
signal ap_arg_rqt_i : std_logic;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF axis_rst : SIGNAL IS "true";
ATTRIBUTE async_reg OF axis_rst1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync1 : SIGNAL IS "true";
begin
-- prd1: PROCESS (M_AXIS_ACLK, ap_rst)
-- BEGIN
-- -- Register Stage #1
-- IF (ap_rst = '1') THEN
-- ap_rst_sync1 <= '1';
-- ap_rst_sync <= '1';
-- ELSIF (M_AXIS_ACLK'event and M_AXIS_ACLK = '1') THEN
-- ap_rst_sync1 <= '0';
-- ap_rst_sync <= ap_rst_sync1;
-- END IF;
-- END PROCESS prd1;
-- prd1: PROCESS (M_AXIS_ACLK)
-- BEGIN
-- -- Register Stage #1
-- IF (M_AXIS_ACLK'event and M_AXIS_ACLK = '1') THEN
-- ap_rst_sync1 <= ap_rst;
-- ap_rst_sync <= ap_rst_sync1;
-- END IF;
-- END PROCESS prd1;
axis_rst2 <= not(M_AXIS_ARESETN) or ap_rst_sync;
prd2: PROCESS (M_AXIS_ACLK, axis_rst2)
BEGIN
-- Register Stage #1
IF (axis_rst2 = '1') THEN
axis_rst1 <= '1';
axis_rst <= '1';
ELSIF (M_AXIS_ACLK'event and M_AXIS_ACLK = '1') THEN
axis_rst1 <= '0';
axis_rst <= axis_rst1;
END IF;
END PROCESS prd2;
-- rst_sync : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 0,
-- C_RESET_STATE => 1,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 2
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => ap_rst,
-- prmry_vect_in => (others=>'0'),
-- scndry_aclk => M_AXIS_ACLK,
-- scndry_resetn => axisn_rst,
-- scndry_out => axis_rst,
-- scndry_vect_out => open
-- );
CONVERTER_I : entity axis_accelerator_adapter_v2_1_6.xd_m2s_converter
generic map (
C_FAMILY => C_FAMILY,
SIZE_WIDTH => SIZE_WIDTH,
AXI_DATA_WIDTH => AXI_DATA_WIDTH,
AXI_ADDR_WIDTH => AXI_ADDR_WIDTH,
AXI_USER_WIDTH => C_M_AXIS_TUSER_WIDTH,
AXI_ID_WIDTH => C_M_AXIS_TID_WIDTH,
AXI_DEST_WIDTH => C_M_AXIS_TDEST_WIDTH)
port map (
axi_clk => M_AXIS_ACLK,
axi_rst => axis_rst,
axis_vld => M_AXIS_TVALID,
axis_rdy => M_AXIS_TREADY,
axis_data => M_AXIS_TDATA,
axis_keep => M_AXIS_TKEEP,
axis_strb => M_AXIS_TSTRB,
axis_last => M_AXIS_TLAST,
axis_id => M_AXIS_TID,
axis_dest => M_AXIS_TDEST,
axis_user => M_AXIS_TUSER,
conv_size => conv_size,
conv_addr => conv_addr,
conv_ce => conv_ce,
conv_we => conv_we,
conv_last => conv_last,
conv_rdy => conv_rdy,
conv_data => conv_data,
host_oarg_tdest => host_oarg_tdest);
MEM_CTRL_I : entity axis_accelerator_adapter_v2_1_6.xd_m2s_memory_dc
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_BRAM_TYPE => C_BRAM_TYPE,
SIZE_WIDTH => SIZE_WIDTH,
CONV_DATA_WIDTH => AXI_DATA_WIDTH,
CONV_ADDR_WIDTH => AXI_ADDR_WIDTH,
C_AP_ARG_DATA_WIDTH => C_AP_ARG_DATA_WIDTH,
C_AP_ARG_ADDR_WIDTH => C_AP_ARG_ADDR_WIDTH,
C_MULTIBUFFER_DEPTH => C_MULTIBUFFER_DEPTH,
C_AP_ARG_WIDTH => C_AP_ARG_WIDTH,
C_AP_ARG_N_DIM => C_AP_ARG_N_DIM,
C_AP_ARG_DIMS => C_AP_ARG_DIMS,
C_AP_ARG_DIM_1 => C_AP_ARG_DIM_1,
C_AP_ARG_DIM_2 => C_AP_ARG_DIM_2,
C_AP_ARG_FORMAT_TYPE => C_AP_ARG_FORMAT_TYPE,
C_AP_ARG_FORMAT_FACTOR => C_AP_ARG_FORMAT_FACTOR,
C_AP_ARG_FORMAT_DIM => C_AP_ARG_FORMAT_DIM,
C_NONE => 2)
port map (
clk => M_AXIS_ACLK,
rst => axis_rst,
conv_size => conv_size,
conv_addr => conv_addr,
conv_ce => conv_ce,
conv_we => conv_we,
conv_last => conv_last,
conv_rdy => conv_rdy,
conv_data => conv_data,
sw_length => sw_length,
sw_length_we => sw_length_we,
use_sw_length => use_sw_length,
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_arg_addr => ap_arg_addr,
ap_arg_ce => ap_arg_ce,
ap_arg_we => ap_arg_we,
ap_arg_din => ap_arg_din,
ap_arg_dout => ap_arg_dout,
ap_arg_rqt => ap_arg_rqt_i,
ap_arg_ack => ap_arg_ack,
ap_arg_empty => ap_arg_empty,
ap_arg_full => ap_arg_full,
ap_arg_used => ap_arg_used);
ap_arg_rqt <= ap_arg_rqt_i;
end rtl;
|
mit
|
2b601c10fb7e34024951ca0a9e90f52f
| 0.547939 | 3.379597 | false | false | false | false |
mitchsm/nvc
|
test/bounds/bounds2.vhd
| 2 | 3,316 |
entity bounds2 is
end entity;
architecture test of bounds2 is
begin
asssignment_delays: block
signal b1,b2,b3,b4,b5,b6,b7 : boolean;
begin
b1 <= true; -- OK
b2 <= true after 10 ns; -- OK
b3 <= true after 0 ns; -- OK
b4 <= true after -1 ns; -- Error
process
begin
b5 <= true; -- OK
b5 <= true after 0 ns; -- OK
b5 <= true after 1 fs; -- OK
b5 <= true after -1 fs; -- Error
wait;
end process;
b6 <= true after -10 ns when true else false;
b7 <= true when true else false after -10 ns;
end block;
rejection_limits: block
signal b1,b2,b3 : boolean;
begin
b1 <= reject 10 ns inertial true after 10 ns; -- OK
b2 <= reject -10 ns inertial true; -- Error
b3 <= reject 10 ns inertial true after 5 ns; -- Error
end block;
process
begin
wait for -10 ns; -- Error
wait;
end process;
default_values: block
type r is range 0 to 1;
constant ok1 : integer range 0 to 1 := 1; -- OK
constant ok2 : character range 'a' to 'z' := 'b'; -- OK
constant ok3 : real range 0.0 to 1.0 := 0.0; -- OK
constant ok4 : time range 10 ns to 20 ns := 10 ns; -- OK
constant ok5 : r := 0; -- OK
signal s : integer range 0 to 9 := 20; -- Error
constant c1 : character range 'a' to 'z' := 'Z'; -- Error
shared variable v : real range 0.0 to 5.0 := 10.0; -- Error
constant t : time range 10 ns to 10 us := 0 fs; -- Error
constant c2 : r := 10; -- Error
subtype subint is integer range 1 to 10;
procedure test(a : subint := 30) is
begin
end procedure;
function test(a : character range 'a' to 'b' := 'c') return integer is
begin
return 1;
end function;
component comp is
generic (
g2 : integer range 10 downto 0 := 20
);
port (
p2 : in integer range 0 to 1 := 2
);
end component;
begin
process is
variable v2 : real range 0.0 to 5.0 := 5.1; -- Error
begin
end process;
end block;
ascending_time: block
signal s : integer;
signal del : time;
begin
process
begin
s <= 0 after 10 ns, 1 after 11 ns; -- OK
s <= 0, 1 after 1 ns; -- OK
s <= 10 after del; -- OK
s <= 10 after del, 20 after del + 1 ns; -- OK
s <= 0, 1; -- Error
s <= 0 after 1 ns, 1; -- Error
s <= 0 after 2 ns, 1 after 1 ns; -- Error
s <= 0 after 1 ns, 1 after del, 2; -- Error
s <= 1 after del, 2; -- Error
wait;
end process;
end block;
end architecture;
|
gpl-3.0
|
26fdb6de3c440cef120e4dea0872699e
| 0.426417 | 4.063725 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter2.vhd
| 1 | 4,146 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter2.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter2 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_counter2;
ARCHITECTURE SYN OF lpm_counter2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(0 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 1
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
7345482f85a9f2eeade27b7af3239c67
| 0.65123 | 3.738503 | false | false | false | false |
blutsvente/MIX
|
test/results/intra/ent_t-rtl-a.vhd
| 1 | 5,948 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:51:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
generic (
generic_15 : integer := 4660; -- Parameter for genericGeneric
);
port (
-- Generated Port for Entity ent_a
const_p_19 : in std_ulogic_vector(15 downto 0); -- Constant on inst_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Generated Signal List
--
constant const_19_c : std_ulogic_vector(15 downto 0) := "0000110000011001"; -- __I_ConvConstant: 0xc19
signal const_19 : std_ulogic_vector(15 downto 0);
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
const_19 <= const_19_c;
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
generic map (
generic_15 => 17185
)
port map (
const_p_19 => const_19, -- Constant on inst_a
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
989785723ff149e490668a736fc4f745
| 0.629455 | 2.77296 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_t_e-rtl-a.vhd
| 1 | 12,076 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
widesig_o : out std_ulogic_vector(31 downto 0);
widesig_r_0 : out std_ulogic;
widesig_r_1 : out std_ulogic;
widesig_r_2 : out std_ulogic;
widesig_r_3 : out std_ulogic;
widesig_r_4 : out std_ulogic;
widesig_r_5 : out std_ulogic;
widesig_r_6 : out std_ulogic;
widesig_r_7 : out std_ulogic;
widesig_r_8 : out std_ulogic;
widesig_r_9 : out std_ulogic;
widesig_r_10 : out std_ulogic;
widesig_r_11 : out std_ulogic;
widesig_r_12 : out std_ulogic;
widesig_r_13 : out std_ulogic;
widesig_r_14 : out std_ulogic;
widesig_r_15 : out std_ulogic;
widesig_r_16 : out std_ulogic;
widesig_r_17 : out std_ulogic;
widesig_r_18 : out std_ulogic;
widesig_r_19 : out std_ulogic;
widesig_r_20 : out std_ulogic;
widesig_r_21 : out std_ulogic;
widesig_r_22 : out std_ulogic;
widesig_r_23 : out std_ulogic;
widesig_r_24 : out std_ulogic;
widesig_r_25 : out std_ulogic;
widesig_r_26 : out std_ulogic;
widesig_r_27 : out std_ulogic;
widesig_r_28 : out std_ulogic;
widesig_r_29 : out std_ulogic;
widesig_r_30 : out std_ulogic;
unsplice_a1_no3 : out std_ulogic_vector(127 downto 0); -- leaves 3 unconnected
unsplice_a2_all128 : out std_ulogic_vector(127 downto 0); -- full 128 bit port
unsplice_a3_up100 : out std_ulogic_vector(127 downto 0); -- connect 100 bits from 0
unsplice_a4_mid100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_a5_midp100 : out std_ulogic_vector(127 downto 0); -- connect mid 100 bits
unsplice_bad_a : out std_ulogic_vector(127 downto 0);
unsplice_bad_b : out std_ulogic_vector(127 downto 0);
widemerge_a1 : out std_ulogic_vector(31 downto 0);
p_mix_test1_go : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
port_b_1 : in std_ulogic
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_c_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_d_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_e_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_e_e
video_i : in std_ulogic_vector(3 downto 0);
widesig_i : in std_ulogic_vector(31 downto 0);
p_mix_widesig_r_0_gi : in std_ulogic;
p_mix_widesig_r_1_gi : in std_ulogic;
p_mix_widesig_r_2_gi : in std_ulogic;
p_mix_widesig_r_3_gi : in std_ulogic;
p_mix_widesig_r_4_gi : in std_ulogic;
p_mix_widesig_r_5_gi : in std_ulogic;
p_mix_widesig_r_6_gi : in std_ulogic;
p_mix_widesig_r_7_gi : in std_ulogic;
p_mix_widesig_r_8_gi : in std_ulogic;
p_mix_widesig_r_9_gi : in std_ulogic;
p_mix_widesig_r_10_gi : in std_ulogic;
p_mix_widesig_r_11_gi : in std_ulogic;
p_mix_widesig_r_12_gi : in std_ulogic;
p_mix_widesig_r_13_gi : in std_ulogic;
p_mix_widesig_r_14_gi : in std_ulogic;
p_mix_widesig_r_15_gi : in std_ulogic;
p_mix_widesig_r_16_gi : in std_ulogic;
p_mix_widesig_r_17_gi : in std_ulogic;
p_mix_widesig_r_18_gi : in std_ulogic;
p_mix_widesig_r_19_gi : in std_ulogic;
p_mix_widesig_r_20_gi : in std_ulogic;
p_mix_widesig_r_21_gi : in std_ulogic;
p_mix_widesig_r_22_gi : in std_ulogic;
p_mix_widesig_r_23_gi : in std_ulogic;
p_mix_widesig_r_24_gi : in std_ulogic;
p_mix_widesig_r_25_gi : in std_ulogic;
p_mix_widesig_r_26_gi : in std_ulogic;
p_mix_widesig_r_27_gi : in std_ulogic;
p_mix_widesig_r_28_gi : in std_ulogic;
p_mix_widesig_r_29_gi : in std_ulogic;
p_mix_widesig_r_30_gi : in std_ulogic;
p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal test1 : std_ulogic;
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0);
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0);
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0);
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0);
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0);
signal unsplice_bad_a : std_ulogic_vector(127 downto 0);
signal unsplice_bad_b : std_ulogic_vector(127 downto 0);
-- __I_NODRV_I signal video_i : std_ulogic_vector(3 downto 0);
signal widemerge_a1 : std_ulogic_vector(31 downto 0);
signal widesig : std_ulogic_vector(31 downto 0);
signal widesig_r_0 : std_ulogic;
signal widesig_r_1 : std_ulogic;
signal widesig_r_10 : std_ulogic;
signal widesig_r_11 : std_ulogic;
signal widesig_r_12 : std_ulogic;
signal widesig_r_13 : std_ulogic;
signal widesig_r_14 : std_ulogic;
signal widesig_r_15 : std_ulogic;
signal widesig_r_16 : std_ulogic;
signal widesig_r_17 : std_ulogic;
signal widesig_r_18 : std_ulogic;
signal widesig_r_19 : std_ulogic;
signal widesig_r_2 : std_ulogic;
signal widesig_r_20 : std_ulogic;
signal widesig_r_21 : std_ulogic;
signal widesig_r_22 : std_ulogic;
signal widesig_r_23 : std_ulogic;
signal widesig_r_24 : std_ulogic;
signal widesig_r_25 : std_ulogic;
signal widesig_r_26 : std_ulogic;
signal widesig_r_27 : std_ulogic;
signal widesig_r_28 : std_ulogic;
signal widesig_r_29 : std_ulogic;
signal widesig_r_3 : std_ulogic;
signal widesig_r_30 : std_ulogic;
signal widesig_r_4 : std_ulogic;
signal widesig_r_5 : std_ulogic;
signal widesig_r_6 : std_ulogic;
signal widesig_r_7 : std_ulogic;
signal widesig_r_8 : std_ulogic;
signal widesig_r_9 : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_test1_go => test1, -- Use internally test1
unsplice_a1_no3 => unsplice_a1_no3, -- leaves 3 unconnected
unsplice_a2_all128 => unsplice_a2_all128, -- full 128 bit port
unsplice_a3_up100 => unsplice_a3_up100, -- connect 100 bits from 0
unsplice_a4_mid100 => unsplice_a4_mid100, -- connect mid 100 bits
unsplice_a5_midp100 => unsplice_a5_midp100, -- connect mid 100 bits
unsplice_bad_a => unsplice_bad_a,
unsplice_bad_b => unsplice_bad_b, -- # conflict
widemerge_a1 => widemerge_a1,
widesig_o => widesig,
widesig_r_0 => widesig_r_0,
widesig_r_1 => widesig_r_1,
widesig_r_10 => widesig_r_10,
widesig_r_11 => widesig_r_11,
widesig_r_12 => widesig_r_12,
widesig_r_13 => widesig_r_13,
widesig_r_14 => widesig_r_14,
widesig_r_15 => widesig_r_15,
widesig_r_16 => widesig_r_16,
widesig_r_17 => widesig_r_17,
widesig_r_18 => widesig_r_18,
widesig_r_19 => widesig_r_19,
widesig_r_2 => widesig_r_2,
widesig_r_20 => widesig_r_20,
widesig_r_21 => widesig_r_21,
widesig_r_22 => widesig_r_22,
widesig_r_23 => widesig_r_23,
widesig_r_24 => widesig_r_24,
widesig_r_25 => widesig_r_25,
widesig_r_26 => widesig_r_26,
widesig_r_27 => widesig_r_27,
widesig_r_28 => widesig_r_28,
widesig_r_29 => widesig_r_29,
widesig_r_3 => widesig_r_3,
widesig_r_30 => widesig_r_30,
widesig_r_4 => widesig_r_4,
widesig_r_5 => widesig_r_5,
widesig_r_6 => widesig_r_6,
widesig_r_7 => widesig_r_7,
widesig_r_8 => widesig_r_8,
widesig_r_9 => widesig_r_9
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
port_b_1 => test1 -- Use internally test1
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: inst_c_e
;
-- End of Generated Instance Port Map for inst_c
-- Generated Instance Port Map for inst_d
inst_d: inst_d_e
;
-- End of Generated Instance Port Map for inst_d
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
p_mix_unsplice_a1_no3_125_0_gi => unsplice_a1_no3(125 downto 0), -- leaves 3 unconnected
p_mix_unsplice_a1_no3_127_127_gi => unsplice_a1_no3(127), -- leaves 3 unconnected
p_mix_unsplice_a2_all128_127_0_gi => unsplice_a2_all128, -- full 128 bit port
p_mix_unsplice_a3_up100_100_0_gi => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
p_mix_unsplice_a4_mid100_99_2_gi => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_a5_midp100_99_2_gi => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_bad_a_1_1_gi => unsplice_bad_a(1),
p_mix_unsplice_bad_b_1_0_gi => unsplice_bad_b(1 downto 0), -- # conflict
p_mix_widemerge_a1_31_0_gi => widemerge_a1,
p_mix_widesig_r_0_gi => widesig_r_0,
p_mix_widesig_r_10_gi => widesig_r_10,
p_mix_widesig_r_11_gi => widesig_r_11,
p_mix_widesig_r_12_gi => widesig_r_12,
p_mix_widesig_r_13_gi => widesig_r_13,
p_mix_widesig_r_14_gi => widesig_r_14,
p_mix_widesig_r_15_gi => widesig_r_15,
p_mix_widesig_r_16_gi => widesig_r_16,
p_mix_widesig_r_17_gi => widesig_r_17,
p_mix_widesig_r_18_gi => widesig_r_18,
p_mix_widesig_r_19_gi => widesig_r_19,
p_mix_widesig_r_1_gi => widesig_r_1,
p_mix_widesig_r_20_gi => widesig_r_20,
p_mix_widesig_r_21_gi => widesig_r_21,
p_mix_widesig_r_22_gi => widesig_r_22,
p_mix_widesig_r_23_gi => widesig_r_23,
p_mix_widesig_r_24_gi => widesig_r_24,
p_mix_widesig_r_25_gi => widesig_r_25,
p_mix_widesig_r_26_gi => widesig_r_26,
p_mix_widesig_r_27_gi => widesig_r_27,
p_mix_widesig_r_28_gi => widesig_r_28,
p_mix_widesig_r_29_gi => widesig_r_29,
p_mix_widesig_r_2_gi => widesig_r_2,
p_mix_widesig_r_30_gi => widesig_r_30,
p_mix_widesig_r_3_gi => widesig_r_3,
p_mix_widesig_r_4_gi => widesig_r_4,
p_mix_widesig_r_5_gi => widesig_r_5,
p_mix_widesig_r_6_gi => widesig_r_6,
p_mix_widesig_r_7_gi => widesig_r_7,
p_mix_widesig_r_8_gi => widesig_r_8,
p_mix_widesig_r_9_gi => widesig_r_9,
-- __I_NODRV_I video_i => __nodrv__/video_i,
widesig_i => widesig
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
aab4d4dc81070f5d28a461d886b0ab90
| 0.641438 | 2.484774 | false | false | false | false |
mitchsm/nvc
|
test/sem/universal.vhd
| 5 | 472 |
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; -- Error
r := 62.3 / 6; -- OK
r := 1.51 / i; -- Error
wait;
end process;
end architecture;
|
gpl-3.0
|
148774090bbbcb440af862d9bd70f010
| 0.341102 | 4.068966 | false | false | false | false |
blutsvente/MIX
|
Resources/Examples/a_clk_20030129/A_CLK_struct-a.vhd
| 1 | 11,525 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for A_CLK_struct
--
-- Generated by wig
-- on Wed Jan 29 16:39:40 2003
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Architecture Template
--
-- Generator: mix_0.pl /mix/0.1, [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
--
--
-- Start of Generated Architecture A_CLK_struct
--
architecture A_CLK_struct of A_CLK is
--
-- Components
--
-- Generated Components
component PADS
port (
-- generated
-- NO IN PORTs : ;
-- NO OUT PORTs :
-- end of generated port
);
end component;
-- ---------
component a_fsm
port (
-- generated
alarm_button : in std_ulogic;
alarm_in_u : in std_ulogic;
clk : in std_ulogic;
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic;
wire_high_bit : in __E_TYPE_MISMATCH(3 downto 0);
wire_high_bus : in __E_TYPE_MISMATCH(3 downto 0);
wire_low_bus : in __E_TYPE_MISMATCH(3 downto 0)
-- end of generated port
);
end component;
-- ---------
component alreg
port (
-- generated
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic
-- end of generated port
);
end component;
-- ---------
component count4
port (
-- generated
clk : in std_ulogic;
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic;
reset : in std_ulogic
-- end of generated port
);
end component;
-- ---------
component ddrv4
port (
-- generated
P_MIX_sound_alarm_test1_GI : in std_ulogic;
P_MIX_sound_alarm_test1_GO : out std_ulogic;
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
clk : in std_ulogic;
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
display_ls_hr : out std_ulogic_vector(6 downto 0);
display_ls_min : out std_ulogic_vector(6 downto 0);
display_ms_hr : out std_ulogic_vector(6 downto 0);
display_ms_min : out std_ulogic_vector(6 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
reset : in std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic
-- end of generated port
);
end component;
-- ---------
component keypad
port (
-- generated
clk : in std_ulogic;
columns : in std_ulogic_vector(2 downto 0);
reset : in std_ulogic;
rows : out std_ulogic_vector(3 downto 0)
-- end of generated port
);
end component;
-- ---------
component keyscan
port (
-- generated
alarm_button : out std_ulogic;
clk : in std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
reset : in std_ulogic;
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- end of generated port
);
end component;
-- ---------
component timegen
port (
-- generated
clk : in std_ulogic;
one_minute : out std_ulogic;
one_second : out std_ulogic;
reset : in std_ulogic;
stopwatch : in std_ulogic
-- end of generated port
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signals
--
signal __LOGIC1__ : __E_TYPE_MISMATCH(3 downto 0);
signal __LOGIC0__ : __E_TYPE_MISMATCH(3 downto 0);
signal alarm_button : std_ulogic;
signal alarm_time_ls_hr : std_ulogic_vector(3 downto 0);
signal alarm_time_ls_min : std_ulogic_vector(3 downto 0);
signal alarm_time_ms_hr : std_ulogic_vector(3 downto 0);
signal alarm_time_ms_min : std_ulogic_vector(3 downto 0);
signal clk : std_ulogic;
signal columns : std_ulogic_vector(2 downto 0);
signal current_time_ls_hr : std_ulogic_vector(3 downto 0);
signal current_time_ls_min : std_ulogic_vector(3 downto 0);
signal current_time_ms_hr : std_ulogic_vector(3 downto 0);
signal current_time_ms_min : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0);
signal display_ls_min : std_ulogic_vector(6 downto 0);
signal display_ms_hr : std_ulogic_vector(6 downto 0);
signal display_ms_min : std_ulogic_vector(6 downto 0);
signal key : std_ulogic_vector(3 downto 0);
signal key_buffer_0 : std_ulogic_vector(3 downto 0);
signal key_buffer_1 : std_ulogic_vector(3 downto 0);
signal key_buffer_2 : std_ulogic_vector(3 downto 0);
signal key_buffer_3 : std_ulogic_vector(3 downto 0);
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal reset : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal show_a : std_ulogic;
signal show_new_time : std_ulogic;
signal sound_alarm : std_ulogic;
signal sound_alarm_test1 : std_ulogic;
signal stopwatch : std_ulogic;
signal time_button : std_ulogic;
--
-- End of Generated Signals
--
-- %CONSTANTS%
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
__LOGIC1__ <= '0';
__LOGIC0__ <= '0';
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for PADS
PADS: PADS PORT MAP(
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for control
control: a_fsm PORT MAP(
wire_high_bit => __LOGIC1__,
wire_high_bus => __LOGIC1__,
wire_low_bus => __LOGIC0__,
alarm_button => alarm_button,
clk => clk,
key => key,
one_second => one_sec_pulse,
reset => reset,
alarm_in_u => sound_alarm_test1,
time_button => time_button,
load_new_a => load_new_a,
load_new_c => load_new_c,
shift => shift,
show_a => show_a,
show_new_time => show_new_time
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_0,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ls_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_1,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ms_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_2,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ls_hr
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg PORT MAP(
new_alarm_time => key_buffer_3,
load_new_a => load_new_a,
reset => reset,
alarm_time => alarm_time_ms_hr
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_counter
u_counter: count4 PORT MAP(
clk => clk,
new_current_time_ls_min => key_buffer_0,
new_current_time_ms_min => key_buffer_1,
new_current_time_ls_hr => key_buffer_2,
new_current_time_ms_hr => key_buffer_3,
load_new_c => load_new_c,
one_minute => one_minute,
reset => reset,
current_time_ls_hr => current_time_ls_hr,
current_time_ls_min => current_time_ls_min,
current_time_ms_hr => current_time_ms_hr,
current_time_ms_min => current_time_ms_min
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4 PORT MAP(
alarm_time_ls_hr => alarm_time_ls_hr,
alarm_time_ls_min => alarm_time_ls_min,
alarm_time_ms_hr => alarm_time_ms_hr,
alarm_time_ms_min => alarm_time_ms_min,
clk => clk,
current_time_ls_hr => current_time_ls_hr,
current_time_ls_min => current_time_ls_min,
current_time_ms_hr => current_time_ms_hr,
current_time_ms_min => current_time_ms_min,
key_buffer_0 => key_buffer_0,
key_buffer_1 => key_buffer_1,
key_buffer_2 => key_buffer_2,
key_buffer_3 => key_buffer_3,
reset => reset,
show_a => show_a,
show_new_time => show_new_time,
P_MIX_sound_alarm_test1_GI => sound_alarm_test1,
display_ls_hr => display_ls_hr,
display_ls_min => display_ls_min,
display_ms_hr => display_ms_hr,
display_ms_min => display_ms_min,
sound_alarm => sound_alarm,
P_MIX_sound_alarm_test1_GO => sound_alarm_test1
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_keypad
u_keypad: keypad PORT MAP(
clk => clk,
columns => columns,
reset => reset,
rows => rows
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan PORT MAP(
clk => clk,
reset => reset,
rows => rows,
shift => shift,
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => key_buffer_0,
key_buffer_1 => key_buffer_1,
key_buffer_2 => key_buffer_2,
key_buffer_3 => key_buffer_3,
time_button => time_button
);
-- End of Generated Instance Port Map
-- Generated Instance Port Map for u_timegen
u_timegen: timegen PORT MAP(
clk => clk,
reset => reset,
stopwatch => stopwatch,
one_minute => one_minute,
one_second => one_sec_pulse
);
-- End of Generated Instance Port Map
end A_CLK_struct;
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
gpl-3.0
|
59dd77b0a9bc7c3241a5bcf329416ef5
| 0.597223 | 2.91477 | false | false | false | false |
blutsvente/MIX
|
test/results/typecast/intbus/inst_a-rtl-a.vhd
| 1 | 5,484 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a
--
-- Generated
-- by: wig
-- on: Mon Aug 9 17:44:47 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a-rtl-a.vhd,v 1.2 2006/01/19 08:50:41 wig Exp $
-- $Date: 2006/01/19 08:50:41 $
-- $Log: inst_a-rtl-a.vhd,v $
-- Revision 1.2 2006/01/19 08:50:41 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.43 2004/08/04 12:49:37 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a
--
architecture rtl of inst_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aa -- typecast module
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa
port_a_1 : out std_ulogic;
port_a_11 : out std_ulogic_vector(7 downto 0);
port_a_3 : out std_ulogic_vector(7 downto 0);
port_a_5 : out std_ulogic;
port_a_7 : out std_logic_vector(7 downto 0);
port_a_9 : out std_ulogic;
signal_10 : out std_logic;
signal_12 : out std_logic_vector(15 downto 0);
signal_2 : out std_logic;
signal_4 : out std_logic_vector(15 downto 0);
signal_6 : out std_logic;
signal_8 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa
);
end component;
-- ---------
component inst_ab -- receiver module
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab
port_b_1 : in std_logic;
port_b_10 : in std_ulogic;
port_b_11 : in std_ulogic_vector(7 downto 0);
port_b_12 : in std_logic_vector(15 downto 0);
port_b_2 : in std_ulogic;
port_b_3 : in std_logic_vector(7 downto 0);
port_b_4 : in std_ulogic_vector(15 downto 0);
port_b_5 : in std_logic;
port_b_6 : in std_ulogic;
port_b_7 : in std_ulogic_vector(7 downto 0);
port_b_8 : in std_logic_vector(15 downto 0);
port_b_9 : in std_logic
-- End of Generated Port for Entity inst_ab
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_mix_tc_1_signal_3 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_2_signal_4 : std_logic_vector(15 downto 0);
signal s_mix_tc_3_signal_7 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_4_signal_8 : std_logic_vector(15 downto 0);
signal s_mix_tc_5_signal_11 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_6_signal_11 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_7_signal_12 : std_logic_vector(15 downto 0);
signal s_mix_tc_8_signal_12 : std_logic_vector(15 downto 0);
signal signal_1 : std_logic;
signal signal_10 : std_ulogic;
signal signal_11 : std_logic_vector(7 downto 0);
signal signal_12 : std_ulogic_vector(15 downto 0);
signal signal_2 : std_ulogic;
signal signal_3 : std_logic_vector(7 downto 0);
signal signal_4 : std_ulogic_vector(15 downto 0);
signal signal_5 : std_logic;
signal signal_6 : std_ulogic;
signal signal_7 : std_logic_vector(7 downto 0);
signal signal_8 : std_ulogic_vector(15 downto 0);
signal signal_9 : std_logic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
signal_3 <= std_logic_vector( s_mix_tc_1_signal_3 ); -- __I_TYPECAST
signal_4 <= std_ulogic_vector( s_mix_tc_2_signal_4 ); -- __I_TYPECAST
s_mix_tc_3_signal_7 <= std_ulogic_vector( signal_7 ); -- __I_TYPECAST
s_mix_tc_4_signal_8 <= std_logic_vector( signal_8 ); -- __I_TYPECAST
s_mix_tc_5_signal_11 <= std_ulogic_vector( signal_11 ); -- __I_TYPECAST
signal_11 <= std_logic_vector( s_mix_tc_6_signal_11 ); -- __I_TYPECAST
s_mix_tc_7_signal_12 <= std_logic_vector( signal_12 ); -- __I_TYPECAST
signal_12 <= std_ulogic_vector( s_mix_tc_8_signal_12 ); -- __I_TYPECAST
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_aa -- typecast module
port map (
port_a_1 => signal_1,
port_a_11 => s_mix_tc_6_signal_11,
port_a_3 => s_mix_tc_1_signal_3,
port_a_5 => signal_5,
port_a_7 => signal_7,
port_a_9 => signal_9,
signal_10 => signal_10,
signal_12 => s_mix_tc_8_signal_12,
signal_2 => signal_2,
signal_4 => s_mix_tc_2_signal_4,
signal_6 => signal_6,
signal_8 => signal_8
);
-- End of Generated Instance Port Map for inst_aa_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab -- receiver module
port map (
port_b_1 => signal_1,
port_b_10 => signal_10,
port_b_11 => s_mix_tc_5_signal_11,
port_b_12 => s_mix_tc_7_signal_12,
port_b_2 => signal_2,
port_b_3 => signal_3,
port_b_4 => signal_4,
port_b_5 => signal_5,
port_b_6 => signal_6,
port_b_7 => s_mix_tc_3_signal_7,
port_b_8 => s_mix_tc_4_signal_8,
port_b_9 => signal_9
);
-- End of Generated Instance Port Map for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
5caa16ad81463ebbcbaaf5f056016a8a
| 0.611962 | 2.672515 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare8.vhd
| 1 | 4,441 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare8.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare8 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare8;
ARCHITECTURE SYN OF lpm_compare8 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "000001100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "12"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 12 0 0 9 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare8.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare8_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
66d2f7a9cbd723d9334410b836182506
| 0.655483 | 3.694676 | false | false | false | false |
blutsvente/MIX
|
test/results/typecast/inst_a-rtl-a.vhd
| 1 | 4,407 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a
--
-- Generated
-- by: wig
-- on: Thu Jul 6 05:14:02 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a-rtl-a.vhd,v 1.4 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: inst_a-rtl-a.vhd,v $
-- Revision 1.4 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a
--
architecture rtl of inst_a is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_aa -- typecast module
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa
port_a_1 : out std_ulogic;
port_a_11 : out std_ulogic_vector(7 downto 0);
port_a_3 : out std_ulogic_vector(7 downto 0);
port_a_5 : out std_ulogic;
port_a_7 : out std_logic_vector(7 downto 0);
port_a_9 : out std_ulogic;
signal_10 : out std_logic;
signal_12 : out std_logic_vector(15 downto 0);
signal_2 : out std_logic;
signal_4 : out std_logic_vector(15 downto 0);
signal_6 : out std_logic;
signal_8 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa
);
end component;
-- ---------
component inst_ab -- receiver module
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab
port_b_1 : in std_logic;
port_b_10 : in std_ulogic;
port_b_11 : in std_ulogic_vector(7 downto 0);
port_b_12 : in std_logic_vector(15 downto 0);
port_b_2 : in std_ulogic;
port_b_3 : in std_logic_vector(7 downto 0);
port_b_4 : in std_ulogic_vector(15 downto 0);
port_b_5 : in std_logic;
port_b_6 : in std_ulogic;
port_b_7 : in std_ulogic_vector(7 downto 0);
port_b_8 : in std_logic_vector(15 downto 0);
port_b_9 : in std_logic
-- End of Generated Port for Entity inst_ab
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_1 : std_logic;
signal signal_10 : std_ulogic;
signal signal_11 : std_logic_vector(7 downto 0);
signal signal_12 : std_ulogic_vector(15 downto 0);
signal signal_2 : std_ulogic;
signal signal_3 : std_logic_vector(7 downto 0);
signal signal_4 : std_ulogic_vector(15 downto 0);
signal signal_5 : std_logic;
signal signal_6 : std_ulogic;
signal signal_7 : std_logic_vector(7 downto 0);
signal signal_8 : std_ulogic_vector(15 downto 0);
signal signal_9 : std_logic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_aa -- typecast module
port map (
port_a_7 => signal_7,
signal_8 => signal_8,
std_logic(port_a_1) => signal_1,
std_logic(port_a_5) => signal_5,
std_logic(port_a_9) => signal_9,
std_logic_vector(port_a_11) => signal_11,
std_logic_vector(port_a_3) => signal_3,
std_ulogic(signal_10) => signal_10,
std_ulogic(signal_2) => signal_2,
std_ulogic(signal_6) => signal_6,
std_ulogic_vector(signal_12) => signal_12,
std_ulogic_vector(signal_4) => signal_4
);
-- End of Generated Instance Port Map for inst_aa_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab -- receiver module
port map (
port_b_1 => signal_1,
port_b_10 => signal_10,
port_b_2 => signal_2,
port_b_3 => signal_3,
port_b_4 => signal_4,
port_b_5 => signal_5,
port_b_6 => signal_6,
port_b_9 => signal_9,
std_logic_vector(port_b_11) => signal_11,
std_logic_vector(port_b_7) => signal_7,
std_ulogic_vector(port_b_12) => signal_12,
std_ulogic_vector(port_b_8) => signal_8
);
-- End of Generated Instance Port Map for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
70c2c1d47747bdc129f6f3ab9ce405db
| 0.611754 | 2.742377 | false | false | false | false |
mitchsm/nvc
|
test/sem/array.vhd
| 2 | 10,573 |
package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
end package;
entity e is
end entity;
use work.p.all;
architecture a of e is
-- All these declarations are OK
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
alias a : int_array(2 to 3) is x(2 to 3);
begin
process is
-- Positional elements cannot follow named
variable e : int_array(1 to 2) := (
0 => 1, 2 );
begin
end process;
process is
-- Others element must be last
variable e : ten_ints := ( others => 5, 1 => 2 );
begin
end process;
process is
-- Only one others element
variable e : ten_ints := ( others => 5, others => 2 );
begin
end process;
process is
-- Single element aggregates must be named
variable a : int_array(0 to 0) := ( 0 => 1 );
variable b : int_array(0 to 0) := ( 1 ); -- Error
begin
end process;
process is
variable a : integer;
begin
x(0) <= 1; -- OK
x <= ( others => 2 ); -- OK
x <= 1; -- RHS not array
a := x(0); -- OK
a := x; -- LHS not array
end process;
process is
variable b : boolean;
begin
b := z = m; -- OK
b := z /= m; -- OK
b := z = y; -- Different types
end process;
process is
begin
x(1 to 3) <= z;
x(1 to 2) <= z(1 to 2);
x(x'range) <= (others => 0);
end process;
process is
begin
a(2) <= 4; -- OK
y(2) <= 1; -- OK
end process;
process is
type int2d is array (1 to 10, 1 to 4) of integer;
variable w : int2d := ( 1 => ( 1, 2, 3, 4 ),
2 => ( others => 5 ),
others => ( others => 0 ) );
begin
w(2, 4) := 6;
w(6) := 6; -- Too few indices
w(6, 7, 2) := 2; -- Too many indices
end process;
process is
type letter is (A, B, C);
type larray is array (letter) of integer;
variable w : larray;
begin
w(A) := 2; -- OK
w(5) := 66; -- Wrong index type
end process;
process is
variable n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 ); -- Error
begin
end process;
process is
variable x : integer;
constant c : integer := 3;
variable y : int_array(1 to 3);
begin
y := ( 1 => 2, 2 => 3, x => 5 ); -- Error
y := ( 1 => 2, 2 => 3, c => 5 ); -- OK
end process;
process is
variable x : integer;
variable y : int_array(3 downto 0);
begin
x(1 to 3) := (others => 4); -- Error
y(1 to 3) := (others => 4); -- Error
assert y = (others => 4); -- Error
end process;
process is
subtype four_ints is int_array(1 to 4);
variable x : four_ints;
begin
x(1 to 3) := (1, 2, 3); -- OK
x(2) := 1; -- OK
x(3 downto 1) := (others => '0'); -- Error
assert x(2) = 5; -- OK
end process;
process is
function foo(size: integer) return int_array is
subtype rtype is int_array(size-1 downto 0);
variable result: rtype;
begin
assert result(0) = 1;
return result;
end;
begin
end process;
process is
function plus(A, B: int_array) return int_array is
variable BV, sum: int_array(A'left downto 0);
begin
return sum;
end;
begin
end process;
process is
subtype int4_t is int_array(1 to 4);
type foo_t is array (integer'left to 10) of integer;
variable v : int_array(foo_t'range);
variable u : foo_t;
begin
assert int4_t'length = 4;
assert foo_t'length = 50;
end process;
process is
subtype a_to_c is character range 'a' to 'c';
type abc_ints is array (a_to_c) of integer;
variable v : abc_ints;
begin
assert abc_ints'length = 3;
v('b') := 2;
end process;
process is
type bit_map is array (bit) of integer;
variable b : bit_map := ( '0' => 5, '1' => 6 );
type bit_map2 is array (bit, 0 to 1) of integer;
variable c : bit_map2 := (
'0' => (0 => 0, 1 => 1),
'1' => (0 => 2, 1 => 3) );
begin
b('0') := 6;
c('1', 1) := 5;
end process;
process is
constant c : ten_ints := (ten_ints'range => 5);
variable v : ten_ints;
begin
v := (v'range => 6); -- OK
end process;
process is
type mybit is ('0', '1');
type bit_map is array (bit range '0' to '1') of integer;
variable v : bit_map;
variable b : bit;
begin
v(b) := 1; -- OK
end process;
process is
begin
assert x'length(1) = 5; -- OK
end process;
process is
type bad is array (integer range <>) of int_array; -- Error
begin
end process;
process is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := ( (0, 1, 2), (0, 1, 2) ); -- OK
constant d : int2d := ( (0, 1), (5, 6, 7) ); -- OK (at sem)
constant e : int2d := ( (0, 1), (others => 2) ); -- Error
begin
end process;
process is
variable b1 : bit_vector(7 downto 0);
begin
b1 := b1 sll 1;
b1 := b1 srl 2;
b1 := b1 sla 0;
b1 := b1 sra 1;
b1 := b1 rol 6;
b1 := b1 ror 1;
end process;
process is
variable i : integer;
alias xi is x(1 to i); -- Error
alias zi : integer is z(i); -- Error
alias xx : integer is x(1 to 2); -- Error
begin
end process;
process is
variable i : integer;
begin
i(6) := 2; -- Error
end process;
process is
constant c : integer := -1;
type bad_range is array (-1 to -5) of integer; -- Error
type ok_range is array(c to -5) of integer; -- OK
begin
end process;
process is
subtype bad_sub1 is int_array(1 to 3, 2 to 5); -- Error
begin
end process;
process is
type element is array (integer range 0 to 1) of bit_vector( 0 to 1);
begin
end process;
process is
type ten_ten_ints is array (1 to 10) of ten_ints;
type int2d is array (natural range <>, natural range <>) of integer;
variable t1, t2 : ten_ten_ints;
variable m1, m2 : int2d(1 to 3, 1 to 3);
begin
assert t1 = t2; -- OK
assert t1 /= t2; -- OK
assert t1 < t2; -- OK
assert t1 > t2; -- OK
assert m1 = m2; -- OK
assert m1 < m2; -- Error
end process;
process is
subtype num_array is int_array; -- OK
subtype bad_array is not_here; -- Error
variable a1 : num_array(1 to 3); -- OK
variable a2 : num_array; -- Error
begin
end process;
process is
constant k : integer := 5;
type a is array (k) of integer; -- Error
variable v : a; -- Error
begin
end process;
process is
type ibv is array (boolean range <>) of integer;
variable a : ibv(false to true);
begin
a(false) := 1; -- OK
a(4) := 2; -- Error
a(false to false) := (others => 1); -- OK
end process;
process is
subtype r is integer range 1 to 3;
begin
x(r'range) <= (others => 1);
x(r) <= (others => 1);
end process;
process is
subtype str is string;
constant x : str := "hello"; -- OK
begin
end process;
process is
type barry2d is array (boolean range <>, boolean range <>)
of integer;
variable b : barry2d(false to true, false to true);
type ibarray2d is array (integer range <>, boolean range <>)
of integer;
variable ib : ibarray2d(1 to 5, false to true);
begin
b(barry2d'left(1), barry2d'left(2)) := 5; -- OK
ib(integer'(5), boolean'(true)) := 1; -- OK
ib(ibarray2d'left(1), ibarray2d'left(2)) := 5; -- OK
end process;
process is
type enum1 is (m1, m2, m3, m4, m5);
type abase is array (enum1 range <>) of boolean;
subtype a1 is abase(enum1 range m1 to m5);
variable V1 : A1;
begin
assert v1 = (false, false, false); -- OK
end process;
process is
variable x : int_array(1 to 3);
begin
x := (1 | 2 to 3 => 5); -- OK
end process;
process is
variable b : bit_vector(1 to 3); -- OK
begin
b := "1fe"; -- Error
end process;
issue86: block is
type integer_vector is array (natural range <>) of integer;
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector;
function inside0 (constant E : ElementType;
constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop -- OK (issue #86)
if E = A(i) then
return TRUE;
end if ;
end loop ;
return FALSE ;
end function inside0;
begin
end block;
process is
subtype bad is ten_ints (1 to 4); -- Error
constant c : ten_ints(2 to 4) := (others => 0); -- Error
begin
end process;
process is
type e is (one, two, three);
type arr is array (e range <>) of integer;
constant c : arr := (1, 2, 3, 4);
begin
end process;
no_file_types: block is
type t_int_file is file of integer;
type t_file_array is array (0 to 1) of t_int_file; -- Error
begin
end block;
end architecture;
|
gpl-3.0
|
23019986b357cbdf3418c19d60b5ee59
| 0.468457 | 3.761295 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_iarg_s2s_adapter.vhd
| 1 | 15,870 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_iarg_s2s_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt;
entity xd_iarg_s2s_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_S_AXIS_TDATA_WIDTH : integer;
C_S_AXIS_TUSER_WIDTH : integer;
C_S_AXIS_TID_WIDTH : integer;
C_S_AXIS_TDEST_WIDTH : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer);
port (
-- Input streams
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TVALID : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TKEEP : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TID : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
---
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_iarg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_iarg_re : in std_logic;
ap_iarg_empty_n : out std_logic;
mb_arg_rdy : out std_logic;
mb_arg_done : in std_logic);
end entity;
architecture rtl of xd_iarg_s2s_adapter is
signal axis_rst : std_logic;
signal axis_rst1 : std_logic;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF axis_rst1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF axis_rst : SIGNAL IS "true";
begin
mb_arg_rdy <= '1';
--axis_rst <= not(S_AXIS_ARESETN);
prd1: PROCESS (S_AXIS_ACLK, S_AXIS_ARESETN)
BEGIN
-- Register Stage #1
IF (S_AXIS_ARESETN = '0') THEN
axis_rst1 <= '1';
axis_rst <= '1';
ELSIF (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') THEN
axis_rst1 <= '0';
axis_rst <= axis_rst1;
END IF;
END PROCESS prd1;
SAME_WIDTH_GEN : if (C_S_AXIS_TDATA_WIDTH = C_AP_ARG_DATA_WIDTH) generate
constant FIFO_DATA_LSB : integer := 0;
constant FIFO_DATA_MSB : integer := C_S_AXIS_TDATA_WIDTH-1;
constant FIFO_LAST_BIT : integer := FIFO_DATA_MSB+1;
constant FIFO_WIDTH : integer := FIFO_LAST_BIT+1;
signal fifo_din : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout_vld : std_logic;
signal fifo_dout_rdy : std_logic;
-- FIFO depth calculation
constant FIFO_DEPTH : integer := (2**C_AP_ARG_ADDR_WIDTH)-1;
begin
fifo_din(FIFO_DATA_MSB downto FIFO_DATA_LSB) <= S_AXIS_TDATA;
fifo_din(FIFO_LAST_BIT) <= S_AXIS_TLAST;
FIFO_I : entity axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
DEPTH => FIFO_DEPTH,
WIDTH => FIFO_WIDTH)
port map (
din => fifo_din,
din_vld => S_AXIS_TVALID,
din_rdy => S_AXIS_TREADY,
wr_clk => S_AXIS_ACLK,
wr_rst => axis_rst,
dout => fifo_dout,
dout_vld => fifo_dout_vld,
dout_rdy => fifo_dout_rdy,
rd_clk => ap_clk,
rd_rst => ap_rst);
ap_iarg_dout <= fifo_dout(FIFO_DATA_MSB downto FIFO_DATA_LSB);
ap_iarg_empty_n <= fifo_dout_vld;
fifo_dout_rdy <= ap_iarg_re;
end generate SAME_WIDTH_GEN;
AXI_WIDER_GEN : if (C_S_AXIS_TDATA_WIDTH > C_AP_ARG_DATA_WIDTH) generate
constant WORDS_PER_BEAT : integer := C_S_AXIS_TDATA_WIDTH/C_AP_ARG_DATA_WIDTH;
constant WORD_CNT_WIDTH : integer := log2(WORDS_PER_BEAT);
constant REM_WIDTH : integer := WORD_CNT_WIDTH;
constant FIFO_DATA_LSB : integer := 0;
constant FIFO_DATA_MSB : integer := C_S_AXIS_TDATA_WIDTH-1;
constant FIFO_REM_LSB : integer := FIFO_DATA_MSB+1;
constant FIFO_REM_MSB : integer := FIFO_REM_LSB+REM_WIDTH-1;
constant FIFO_LAST_BIT : integer := FIFO_REM_MSB+1;
constant FIFO_WIDTH : integer := FIFO_LAST_BIT+1;
-- Output register is an additional position to the FIFO. Substract one.
constant DATA_RATIO : integer := C_S_AXIS_TDATA_WIDTH/C_AP_ARG_DATA_WIDTH;
constant FIFO_DEPTH : integer := (2**(C_AP_ARG_ADDR_WIDTH-log2(DATA_RATIO)))-1;
signal word_cnt : unsigned(WORD_CNT_WIDTH-1 downto 0);
signal word_inc : std_logic;
signal axi_rem : std_logic_vector(REM_WIDTH-1 downto 0);
signal fifo_din : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout_vld : std_logic;
signal fifo_dout_rdy : std_logic;
-- Ouput for decoupling fifo
signal ap_data : std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
signal ap_rem : std_logic_vector(REM_WIDTH-1 downto 0);
signal ap_last : std_logic;
signal dout : std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
signal dout_ce : std_logic;
signal dout_vld : std_logic;
signal dout_rdy : std_logic;
begin
-- This logic should generate a set of LUTs (w.c. 8 inputs, 3 outputs)
process(S_AXIS_TKEEP)
constant BYTES_PER_WORD : integer := C_AP_ARG_DATA_WIDTH/8;
constant ones : std_logic_vector(BYTES_PER_WORD-1 downto 0) := (others => '1');
variable aux : integer range 0 to WORDS_PER_BEAT-1;
begin
aux := 0;
for i in 0 to WORDS_PER_BEAT-1 loop
if(S_AXIS_TKEEP(BYTES_PER_WORD*(i+1)-1 downto BYTES_PER_WORD*i) = ones) then
aux := i;
else
exit;
end if;
end loop;
axi_rem <= std_logic_vector(to_unsigned(aux, WORD_CNT_WIDTH));
end process;
fifo_din(FIFO_DATA_MSB downto FIFO_DATA_LSB) <= S_AXIS_TDATA;
fifo_din(FIFO_REM_MSB downto FIFO_REM_LSB) <= axi_rem;
fifo_din(FIFO_LAST_BIT) <= S_AXIS_TLAST;
FIFO_I : entity axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
DEPTH => FIFO_DEPTH,
WIDTH => FIFO_WIDTH)
port map (
din => fifo_din,
din_vld => S_AXIS_TVALID,
din_rdy => S_AXIS_TREADY,
wr_clk => S_AXIS_ACLK,
wr_rst => axis_rst,
dout => fifo_dout,
dout_vld => fifo_dout_vld,
dout_rdy => fifo_dout_rdy,
rd_clk => ap_clk,
rd_rst => ap_rst);
ap_data <= fifo_dout(FIFO_DATA_MSB downto FIFO_DATA_LSB);
ap_rem <= fifo_dout(FIFO_REM_MSB downto FIFO_REM_LSB);
ap_last <= fifo_dout(FIFO_LAST_BIT);
-- Set the output register when output is not valid or if it's valid it's
-- being taken (same cycle)
dout_ce <= not(dout_vld) or (dout_vld and dout_rdy);
-- Take output of the fifo when we move to the output the last word of the
-- beat
fifo_dout_rdy <= dout_ce when (word_cnt = unsigned(ap_rem)) else '0';
-- Increment word counter when we transfer one word at the output
word_inc <= fifo_dout_vld and dout_ce;
-- Counter of words transferd to output port:
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
word_cnt <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if(word_inc = '1') then
if(word_cnt = unsigned(ap_rem)) then
word_cnt <= (others => '0');
else
word_cnt <= word_cnt + 1;
end if;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
dout_vld <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(dout_ce = '1') then
dout_vld <= fifo_dout_vld;
end if;
end if;
end process;
-- Register + mux for output port
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
dout <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if(dout_ce = '1') then
for i in 0 to WORDS_PER_BEAT-1 loop
if(i = word_cnt) then
dout <= fifo_dout(C_AP_ARG_DATA_WIDTH*(i+1)-1 downto C_AP_ARG_DATA_WIDTH*i);
end if;
end loop;
end if;
end if;
end process;
ap_iarg_dout <= dout;
ap_iarg_empty_n <= dout_vld;
dout_rdy <= ap_iarg_re;
end generate AXI_WIDER_GEN;
AXI_NARROWER_GEN : if (C_S_AXIS_TDATA_WIDTH < C_AP_ARG_DATA_WIDTH) generate
constant BEATS_PER_WORD : integer := C_AP_ARG_DATA_WIDTH/C_S_AXIS_TDATA_WIDTH;
constant FIFO_DATA_LSB : integer := 0;
constant FIFO_DATA_MSB : integer := C_AP_ARG_DATA_WIDTH-1;
constant FIFO_WIDTH : integer := FIFO_DATA_MSB+1;
signal beat_sel : std_logic_vector(BEATS_PER_WORD-1 downto 0);
signal tap_0 : std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
signal tap_0_we : std_logic;
signal tap_0_vld : std_logic;
signal tap_0_rdy : std_logic;
signal axis_vld : std_logic;
signal axis_rdy : std_logic;
signal fifo_din : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_din_vld : std_logic;
signal fifo_din_rdy : std_logic;
signal fifo_dout : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout_vld : std_logic;
signal fifo_dout_rdy : std_logic;
-- register tap_0 is an extra position to the fifo. substract 1.
constant FIFO_DEPTH : integer := (2**C_AP_ARG_ADDR_WIDTH)-1;
begin
axis_vld <= S_AXIS_TVALID;
S_AXIS_TREADY <= axis_rdy;
process(S_AXIS_ACLK)
begin
if(S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
if(axis_rst = '1' or (S_AXIS_TLAST and tap_0_we) = '1') then
beat_sel <= (others => '0');
beat_sel(0) <= '1';
elsif(tap_0_we = '1') then
beat_sel <= beat_sel(BEATS_PER_WORD-2 downto 0) & beat_sel(BEATS_PER_WORD-1);
end if;
end if;
end process;
process(S_AXIS_ACLK)
begin
if(S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
if(tap_0_we = '1') then
for i in 0 to BEATS_PER_WORD-1 loop
if(beat_sel(i) = '1') then
tap_0(C_S_AXIS_TDATA_WIDTH*(i+1)-1 downto C_S_AXIS_TDATA_WIDTH*i) <= S_AXIS_TDATA;
end if;
end loop;
end if;
end if;
end process;
process(S_AXIS_ACLK, axis_rst)
begin
if(axis_rst = '1') then
tap_0_vld <= '0';
elsif(S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
if(tap_0_vld = '0' or (tap_0_vld and tap_0_rdy) = '1') then
tap_0_vld <= tap_0_we and (beat_sel(BEATS_PER_WORD-1) or S_AXIS_TLAST);
end if;
end if;
end process;
-- We accept new input data when:
-- 1. tap_0 is empty
-- 2. tap_0 is full but it's content is being moved to fifo
axis_rdy <= not(tap_0_vld) or (tap_0_vld and fifo_din_rdy);
-- under this conditions, a new write will occur on tap_0, if additionally
-- there is a new data at the input
tap_0_we <= axis_vld and (not(tap_0_vld) or (tap_0_vld and fifo_din_rdy));
-- fifo shows a data valid at the input when tap_0 is valid
fifo_din_vld <= tap_0_vld;
-- take tap_0 when it's moved the data to the fifo:
tap_0_rdy <= fifo_din_vld and fifo_din_rdy;
fifo_din(FIFO_DATA_MSB downto FIFO_DATA_LSB) <= tap_0;
FIFO_I : entity axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
DEPTH => FIFO_DEPTH,
WIDTH => FIFO_WIDTH)
port map (
din => fifo_din,
din_vld => fifo_din_vld,
din_rdy => fifo_din_rdy,
wr_clk => S_AXIS_ACLK,
wr_rst => axis_rst,
dout => fifo_dout,
dout_vld => fifo_dout_vld,
dout_rdy => fifo_dout_rdy,
rd_clk => ap_clk,
rd_rst => ap_rst);
ap_iarg_dout <= fifo_dout(FIFO_DATA_MSB downto FIFO_DATA_LSB);
ap_iarg_empty_n <= fifo_dout_vld;
fifo_dout_rdy <= ap_iarg_re;
end generate AXI_NARROWER_GEN;
end rtl;
|
mit
|
038ad219999441012946078b6ddde00b
| 0.577379 | 3.367997 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare15.vhd
| 1 | 4,452 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare15.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare15 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare15;
ARCHITECTURE SYN OF lpm_compare15 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "111100000";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "480"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 480 0 0 9 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
4896bcd5913d3fc7548a7c3c07fc8806
| 0.656334 | 3.703827 | false | false | false | false |
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