repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
LemurPwned/classic-fpga
|
multiplexers_registers/multiplex_1.vhdl
| 1 | 859 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplex_1 is
port (
smi : in std_logic_vector(6 downto 0);
smo : out std_logic;
se : in std_logic_vector(2 downto 0)
);
end entity;
architecture behav of multiplex_1 is
signal cp : std_logic_vector(2 downto 0);
signal smo_1 : std_logic_vector(6 downto 0);
begin
cp <= not se;
smo_1(0) <= (smi(0) and cp(0) and cp(1) and cp(2));
smo_1(1) <= (smi(1) and cp(2) and cp(1) and se(0));
smo_1(2) <= (smi(2) and cp(0) and se(1) and cp(2));
smo_1(3) <= (smi(3) and cp(2) and se(1) and se(0));
smo_1(4) <= (smi(4) and se(2) and cp(1) and cp(0));
smo_1(5) <= (smi(5) and se(0) and cp(1) and se(2));
smo_1(6) <= (smi(6) and se(2) and se(1) and cp(0));
smo <= smo_1(0) or smo_1(1) or smo_1(2) or smo_1(3) or smo_1(4) or smo_1(5) or smo_1(6);
end architecture;
|
gpl-3.0
|
a565dd37439e2af9e83e34679dc7a3c9
| 0.593714 | 2.284574 | false | false | false | false |
LemurPwned/classic-fpga
|
counters/counter_tb.vhdl
| 1 | 845 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_tb is
end entity;
architecture behavv of counter_tb is
component counter is
port(
clk, res_as, up : in std_logic;
count : out std_logic_vector (3 downto 0)
);
end component;
for counter_0 : counter use entity work.counter;
signal clk,up : std_logic :='1';
signal res_as : std_logic:='0';
signal count : std_logic_vector(3 downto 0);
constant period : time := 10 ns;
begin
counter_0 : counter port map (clk=>clk, res_as=>res_as, up=>up, count=>count);
clk_process: process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc : process
begin
res_as<='0';
up<='1';
wait for 80 ns;
up<='0';
wait for 30 ns;
res_as<='1';
wait for 10 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
b59aa9af298e971765ac388d0dc93810
| 0.64497 | 3.152985 | false | false | false | false |
jandecaluwe/ca
|
myhdl/calc_next_age/pck_myhdl_08.vhd
| 1 | 3,359 |
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Dec 16 22:45:16 2012
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
|
mit
|
780d4ad719d622e01e406b9972f942ff
| 0.601072 | 4.022754 | false | false | false | false |
LemurPwned/classic-fpga
|
compar_tb.vhdl
| 1 | 833 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity compar_tb is
end entity;
architecture behav of compar_tb is
component compar is
port (
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
so_a : out std_logic;
so_b : out std_logic
);
end component;
signal a,b : std_logic_vector(3 downto 0);
signal so_a, so_b : std_logic;
for compar_0: compar use entity work.compar;
begin
compar_0: compar port map (a=>a, b=>b, so_a=>so_a, so_b=>so_b);
process
begin
a<="1110";
b<="0111";
wait for 5 ns;
b<="1110";
a<="0000";
wait for 5 ns;
b<="0010";
a<="0111";
wait for 5 ns;
b<="1010";
a<="0111";
wait for 5 ns;
b<="0110";
a<="0110";
wait for 5 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
44bfd74c68dab011b5d0ffe659b25f94
| 0.582233 | 2.985663 | false | false | false | false |
LemurPwned/classic-fpga
|
machines/compar_fsm_tb.vhdl
| 1 | 1,189 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity compar_fsm_tb is
end entity;
architecture behav of compar_fsm_tb is
component compar_fsm is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector(1 downto 0);
--this is pair of bits of two numbers, a0b0, a1b1, etc.., easier to process
o: out std_logic_vector(1 downto 0)
-- 00 is equal, 10 a is bigger, 01 b is bigger
);
end component;
signal clk : std_logic :='1';
signal reset : std_logic :='0';
signal ab, o : std_logic_vector(1 downto 0) :="00";
constant period : time := 20 ns;
begin
mapping: compar_fsm port map (clk=>clk, reset=>reset, ab=>ab, o=>o);
clk_proc: process
begin
clk<=not clk;
wait for period/4;
end process;
stim_proc: process
begin
ab<="00";
wait for period;
ab<="00";
wait for period;
ab<="10";
wait for period;
ab<="01";
wait for period;
ab<="10";
wait for period;
ab<="10";
wait for period;
ab<="10";
wait for period;
ab<="01";
wait for period;
ab<="00";
wait for period;
ab<="00";
wait for period;
wait;
end process;
end architecture;
|
gpl-3.0
|
a725a25784b2e673031da1e0106b0919
| 0.617325 | 3.179144 | false | false | false | false |
jandecaluwe/ca
|
myhdl/calc_next_age/calc_next_age.vhd
| 1 | 1,133 |
-- File: calc_next_age.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Dec 16 22:44:22 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity calc_next_age is
port (
age_out: out std_logic;
live_count: in unsigned(3 downto 0);
step: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity calc_next_age;
architecture MyHDL of calc_next_age is
signal age: std_logic;
begin
CALC_NEXT_AGE_SEQ: process (clock, reset) is
variable survival: std_logic;
variable birth: std_logic;
begin
if (reset = '1') then
age <= '0';
elsif rising_edge(clock) then
birth := stdl(live_count = 3);
survival := stdl((live_count = 2) or (live_count = 3));
if bool(step) then
if ((age = '0') and bool(birth)) then
age <= '1';
elsif ((age = '1') and (not bool(survival))) then
age <= '0';
end if;
end if;
end if;
end process CALC_NEXT_AGE_SEQ;
age_out <= age;
end architecture MyHDL;
|
mit
|
030e842a8f5ff56d6759ce04dc771c9a
| 0.576346 | 3.182584 | false | false | false | false |
freecores/yavga
|
vhdl/charmaps_ROM.vhd
| 2 | 37,331 |
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity charmaps_ROM is
port (
i_EN : in std_logic; -- RAM Enable Input
i_clock : in std_logic; -- Clock
i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 11-bit Address Input
o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8-bit Data Output
);
end charmaps_ROM;
architecture Behavioral of charmaps_ROM is
signal s_EN : std_logic;
constant c_rom_size : natural := 2**c_INTCHMAP_ADDR_BUS_W;
type t_rom is array (c_rom_size-1 downto 0) of
std_logic_vector (c_INTCHMAP_DATA_BUS_W - 1 downto 0);
constant c_rom : t_rom := (
-- AUTOMATICALLY GENERATED... START
0 => X"00", 1 => X"00", 2 => X"00", 3 => X"00",
4 => X"00", 5 => X"00", 6 => X"00", 7 => X"00",
8 => X"00", 9 => X"00", 10 => X"00", 11 => X"00",
12 => X"00", 13 => X"00", 14 => X"00", 15 => X"00",
16 => X"00", 17 => X"00", 18 => X"00", 19 => X"FF",
20 => X"00", 21 => X"00", 22 => X"FF", 23 => X"00",
24 => X"00", 25 => X"FF", 26 => X"00", 27 => X"00",
28 => X"FF", 29 => X"00", 30 => X"00", 31 => X"00",
32 => X"00", 33 => X"00", 34 => X"FF", 35 => X"00",
36 => X"00", 37 => X"FF", 38 => X"00", 39 => X"00",
40 => X"FF", 41 => X"00", 42 => X"00", 43 => X"FF",
44 => X"00", 45 => X"00", 46 => X"00", 47 => X"00",
48 => X"00", 49 => X"00", 50 => X"24", 51 => X"24",
52 => X"24", 53 => X"24", 54 => X"24", 55 => X"24",
56 => X"24", 57 => X"24", 58 => X"24", 59 => X"24",
60 => X"24", 61 => X"24", 62 => X"00", 63 => X"00",
64 => X"00", 65 => X"00", 66 => X"49", 67 => X"49",
68 => X"49", 69 => X"49", 70 => X"49", 71 => X"49",
72 => X"49", 73 => X"49", 74 => X"49", 75 => X"49",
76 => X"49", 77 => X"49", 78 => X"00", 79 => X"00",
80 => X"00", 81 => X"00", 82 => X"92", 83 => X"92",
84 => X"92", 85 => X"92", 86 => X"92", 87 => X"92",
88 => X"92", 89 => X"92", 90 => X"92", 91 => X"92",
92 => X"92", 93 => X"92", 94 => X"00", 95 => X"00",
96 => X"00", 97 => X"00", 98 => X"55", 99 => X"55",
100 => X"55", 101 => X"55", 102 => X"55", 103 => X"55",
104 => X"55", 105 => X"55", 106 => X"55", 107 => X"55",
108 => X"55", 109 => X"55", 110 => X"00", 111 => X"00",
112 => X"00", 113 => X"00", 114 => X"AA", 115 => X"AA",
116 => X"AA", 117 => X"AA", 118 => X"AA", 119 => X"AA",
120 => X"AA", 121 => X"AA", 122 => X"AA", 123 => X"AA",
124 => X"AA", 125 => X"AA", 126 => X"00", 127 => X"00",
128 => X"00", 129 => X"00", 130 => X"00", 131 => X"FF",
132 => X"00", 133 => X"FF", 134 => X"00", 135 => X"FF",
136 => X"00", 137 => X"FF", 138 => X"00", 139 => X"FF",
140 => X"00", 141 => X"FF", 142 => X"00", 143 => X"00",
144 => X"00", 145 => X"00", 146 => X"FC", 147 => X"F3",
148 => X"FC", 149 => X"F3", 150 => X"FC", 151 => X"F3",
152 => X"FC", 153 => X"F3", 154 => X"FC", 155 => X"F3",
156 => X"FC", 157 => X"F3", 158 => X"00", 159 => X"00",
160 => X"00", 161 => X"00", 162 => X"3F", 163 => X"CF",
164 => X"3F", 165 => X"CF", 166 => X"3F", 167 => X"CF",
168 => X"3F", 169 => X"CF", 170 => X"3F", 171 => X"CF",
172 => X"3F", 173 => X"CF", 174 => X"00", 175 => X"00",
176 => X"00", 177 => X"00", 178 => X"03", 179 => X"0C",
180 => X"03", 181 => X"0C", 182 => X"03", 183 => X"0C",
184 => X"03", 185 => X"0C", 186 => X"03", 187 => X"0C",
188 => X"03", 189 => X"0C", 190 => X"00", 191 => X"00",
192 => X"00", 193 => X"00", 194 => X"C0", 195 => X"30",
196 => X"C0", 197 => X"30", 198 => X"C0", 199 => X"30",
200 => X"C0", 201 => X"30", 202 => X"C0", 203 => X"30",
204 => X"C0", 205 => X"30", 206 => X"00", 207 => X"00",
208 => X"00", 209 => X"00", 210 => X"00", 211 => X"66",
212 => X"66", 213 => X"66", 214 => X"66", 215 => X"00",
216 => X"00", 217 => X"66", 218 => X"66", 219 => X"66",
220 => X"66", 221 => X"00", 222 => X"00", 223 => X"00",
224 => X"00", 225 => X"00", 226 => X"FF", 227 => X"99",
228 => X"99", 229 => X"99", 230 => X"99", 231 => X"FF",
232 => X"FF", 233 => X"99", 234 => X"99", 235 => X"99",
236 => X"99", 237 => X"FF", 238 => X"00", 239 => X"00",
240 => X"00", 241 => X"00", 242 => X"0F", 243 => X"0F",
244 => X"0F", 245 => X"0F", 246 => X"0F", 247 => X"0F",
248 => X"0F", 249 => X"0F", 250 => X"0F", 251 => X"0F",
252 => X"0F", 253 => X"0F", 254 => X"00", 255 => X"00",
256 => X"00", 257 => X"00", 258 => X"F0", 259 => X"F0",
260 => X"F0", 261 => X"F0", 262 => X"F0", 263 => X"F0",
264 => X"F0", 265 => X"F0", 266 => X"F0", 267 => X"F0",
268 => X"F0", 269 => X"F0", 270 => X"00", 271 => X"00",
272 => X"00", 273 => X"00", 274 => X"FF", 275 => X"FF",
276 => X"FF", 277 => X"FF", 278 => X"FF", 279 => X"FF",
280 => X"00", 281 => X"00", 282 => X"00", 283 => X"00",
284 => X"00", 285 => X"00", 286 => X"00", 287 => X"00",
288 => X"00", 289 => X"00", 290 => X"00", 291 => X"00",
292 => X"00", 293 => X"00", 294 => X"00", 295 => X"00",
296 => X"FF", 297 => X"FF", 298 => X"FF", 299 => X"FF",
300 => X"FF", 301 => X"FF", 302 => X"00", 303 => X"00",
304 => X"00", 305 => X"00", 306 => X"0F", 307 => X"0F",
308 => X"0F", 309 => X"0F", 310 => X"0F", 311 => X"0F",
312 => X"0F", 313 => X"0F", 314 => X"0F", 315 => X"0F",
316 => X"0F", 317 => X"0F", 318 => X"00", 319 => X"00",
320 => X"00", 321 => X"00", 322 => X"F0", 323 => X"F0",
324 => X"F0", 325 => X"F0", 326 => X"F0", 327 => X"F0",
328 => X"F0", 329 => X"F0", 330 => X"F0", 331 => X"F0",
332 => X"F0", 333 => X"F0", 334 => X"00", 335 => X"00",
336 => X"00", 337 => X"00", 338 => X"00", 339 => X"7E",
340 => X"42", 341 => X"42", 342 => X"42", 343 => X"42",
344 => X"42", 345 => X"42", 346 => X"42", 347 => X"42",
348 => X"7E", 349 => X"00", 350 => X"00", 351 => X"00",
352 => X"00", 353 => X"00", 354 => X"FF", 355 => X"81",
356 => X"81", 357 => X"81", 358 => X"81", 359 => X"81",
360 => X"81", 361 => X"81", 362 => X"81", 363 => X"81",
364 => X"81", 365 => X"FF", 366 => X"00", 367 => X"00",
368 => X"00", 369 => X"00", 370 => X"49", 371 => X"24",
372 => X"49", 373 => X"24", 374 => X"49", 375 => X"24",
376 => X"49", 377 => X"24", 378 => X"49", 379 => X"24",
380 => X"49", 381 => X"24", 382 => X"00", 383 => X"00",
384 => X"00", 385 => X"00", 386 => X"92", 387 => X"24",
388 => X"92", 389 => X"24", 390 => X"92", 391 => X"24",
392 => X"92", 393 => X"24", 394 => X"92", 395 => X"24",
396 => X"92", 397 => X"24", 398 => X"00", 399 => X"00",
400 => X"00", 401 => X"00", 402 => X"92", 403 => X"49",
404 => X"92", 405 => X"49", 406 => X"92", 407 => X"49",
408 => X"92", 409 => X"49", 410 => X"92", 411 => X"49",
412 => X"92", 413 => X"49", 414 => X"00", 415 => X"00",
416 => X"00", 417 => X"00", 418 => X"AA", 419 => X"55",
420 => X"AA", 421 => X"55", 422 => X"AA", 423 => X"55",
424 => X"AA", 425 => X"55", 426 => X"AA", 427 => X"55",
428 => X"AA", 429 => X"55", 430 => X"00", 431 => X"00",
432 => X"00", 433 => X"00", 434 => X"55", 435 => X"AA",
436 => X"55", 437 => X"AA", 438 => X"55", 439 => X"AA",
440 => X"55", 441 => X"AA", 442 => X"55", 443 => X"AA",
444 => X"55", 445 => X"AA", 446 => X"00", 447 => X"00",
448 => X"00", 449 => X"00", 450 => X"B6", 451 => X"DB",
452 => X"B6", 453 => X"DB", 454 => X"B6", 455 => X"DB",
456 => X"B6", 457 => X"DB", 458 => X"B6", 459 => X"DB",
460 => X"B6", 461 => X"DB", 462 => X"00", 463 => X"00",
464 => X"00", 465 => X"00", 466 => X"6D", 467 => X"DB",
468 => X"6D", 469 => X"DB", 470 => X"6D", 471 => X"DB",
472 => X"6D", 473 => X"DB", 474 => X"6D", 475 => X"DB",
476 => X"6D", 477 => X"DB", 478 => X"00", 479 => X"00",
480 => X"00", 481 => X"00", 482 => X"6D", 483 => X"B6",
484 => X"6D", 485 => X"B6", 486 => X"6D", 487 => X"B6",
488 => X"6D", 489 => X"B6", 490 => X"6D", 491 => X"B6",
492 => X"6D", 493 => X"B6", 494 => X"00", 495 => X"00",
496 => X"00", 497 => X"00", 498 => X"FF", 499 => X"FF",
500 => X"FF", 501 => X"FF", 502 => X"FF", 503 => X"FF",
504 => X"FF", 505 => X"FF", 506 => X"FF", 507 => X"FF",
508 => X"FF", 509 => X"FF", 510 => X"00", 511 => X"00",
512 => X"00", 513 => X"00", 514 => X"00", 515 => X"00",
516 => X"00", 517 => X"00", 518 => X"00", 519 => X"00",
520 => X"00", 521 => X"00", 522 => X"00", 523 => X"00",
524 => X"00", 525 => X"00", 526 => X"00", 527 => X"00",
528 => X"00", 529 => X"00", 530 => X"10", 531 => X"10",
532 => X"10", 533 => X"10", 534 => X"10", 535 => X"10",
536 => X"10", 537 => X"10", 538 => X"00", 539 => X"00",
540 => X"10", 541 => X"00", 542 => X"00", 543 => X"00",
544 => X"00", 545 => X"00", 546 => X"44", 547 => X"44",
548 => X"44", 549 => X"44", 550 => X"44", 551 => X"00",
552 => X"00", 553 => X"00", 554 => X"00", 555 => X"00",
556 => X"00", 557 => X"00", 558 => X"00", 559 => X"00",
560 => X"00", 561 => X"00", 562 => X"44", 563 => X"44",
564 => X"FE", 565 => X"44", 566 => X"44", 567 => X"44",
568 => X"44", 569 => X"44", 570 => X"FE", 571 => X"44",
572 => X"44", 573 => X"00", 574 => X"00", 575 => X"00",
576 => X"00", 577 => X"00", 578 => X"7C", 579 => X"92",
580 => X"90", 581 => X"90", 582 => X"90", 583 => X"7C",
584 => X"12", 585 => X"12", 586 => X"12", 587 => X"92",
588 => X"7C", 589 => X"00", 590 => X"00", 591 => X"00",
592 => X"00", 593 => X"00", 594 => X"60", 595 => X"90",
596 => X"92", 597 => X"64", 598 => X"08", 599 => X"10",
600 => X"20", 601 => X"4C", 602 => X"92", 603 => X"12",
604 => X"0C", 605 => X"00", 606 => X"00", 607 => X"00",
608 => X"00", 609 => X"00", 610 => X"30", 611 => X"48",
612 => X"88", 613 => X"88", 614 => X"90", 615 => X"70",
616 => X"50", 617 => X"8A", 618 => X"84", 619 => X"84",
620 => X"7A", 621 => X"00", 622 => X"00", 623 => X"00",
624 => X"00", 625 => X"00", 626 => X"10", 627 => X"10",
628 => X"10", 629 => X"10", 630 => X"10", 631 => X"00",
632 => X"00", 633 => X"00", 634 => X"00", 635 => X"00",
636 => X"00", 637 => X"00", 638 => X"00", 639 => X"00",
640 => X"00", 641 => X"00", 642 => X"10", 643 => X"20",
644 => X"20", 645 => X"40", 646 => X"40", 647 => X"40",
648 => X"40", 649 => X"40", 650 => X"20", 651 => X"20",
652 => X"10", 653 => X"00", 654 => X"00", 655 => X"00",
656 => X"00", 657 => X"00", 658 => X"10", 659 => X"08",
660 => X"08", 661 => X"04", 662 => X"04", 663 => X"04",
664 => X"04", 665 => X"04", 666 => X"08", 667 => X"08",
668 => X"10", 669 => X"00", 670 => X"00", 671 => X"00",
672 => X"00", 673 => X"00", 674 => X"92", 675 => X"92",
676 => X"54", 677 => X"54", 678 => X"38", 679 => X"FE",
680 => X"38", 681 => X"54", 682 => X"54", 683 => X"92",
684 => X"92", 685 => X"00", 686 => X"00", 687 => X"00",
688 => X"00", 689 => X"00", 690 => X"00", 691 => X"10",
692 => X"10", 693 => X"10", 694 => X"10", 695 => X"FE",
696 => X"10", 697 => X"10", 698 => X"10", 699 => X"10",
700 => X"00", 701 => X"00", 702 => X"00", 703 => X"00",
704 => X"00", 705 => X"00", 706 => X"00", 707 => X"00",
708 => X"00", 709 => X"00", 710 => X"00", 711 => X"00",
712 => X"00", 713 => X"08", 714 => X"08", 715 => X"10",
716 => X"20", 717 => X"00", 718 => X"00", 719 => X"00",
720 => X"00", 721 => X"00", 722 => X"00", 723 => X"00",
724 => X"00", 725 => X"00", 726 => X"00", 727 => X"FE",
728 => X"00", 729 => X"00", 730 => X"00", 731 => X"00",
732 => X"00", 733 => X"00", 734 => X"00", 735 => X"00",
736 => X"00", 737 => X"00", 738 => X"00", 739 => X"00",
740 => X"00", 741 => X"00", 742 => X"00", 743 => X"00",
744 => X"00", 745 => X"18", 746 => X"18", 747 => X"00",
748 => X"00", 749 => X"00", 750 => X"00", 751 => X"00",
752 => X"00", 753 => X"00", 754 => X"00", 755 => X"00",
756 => X"02", 757 => X"04", 758 => X"08", 759 => X"10",
760 => X"20", 761 => X"40", 762 => X"80", 763 => X"00",
764 => X"00", 765 => X"00", 766 => X"00", 767 => X"00",
768 => X"00", 769 => X"00", 770 => X"38", 771 => X"44",
772 => X"82", 773 => X"82", 774 => X"8A", 775 => X"92",
776 => X"A2", 777 => X"82", 778 => X"82", 779 => X"44",
780 => X"38", 781 => X"00", 782 => X"00", 783 => X"00",
784 => X"00", 785 => X"00", 786 => X"10", 787 => X"30",
788 => X"50", 789 => X"10", 790 => X"10", 791 => X"10",
792 => X"10", 793 => X"10", 794 => X"10", 795 => X"10",
796 => X"38", 797 => X"00", 798 => X"00", 799 => X"00",
800 => X"00", 801 => X"00", 802 => X"7C", 803 => X"82",
804 => X"02", 805 => X"02", 806 => X"02", 807 => X"7C",
808 => X"80", 809 => X"80", 810 => X"80", 811 => X"80",
812 => X"FE", 813 => X"00", 814 => X"00", 815 => X"00",
816 => X"00", 817 => X"00", 818 => X"7C", 819 => X"82",
820 => X"02", 821 => X"02", 822 => X"02", 823 => X"7C",
824 => X"02", 825 => X"02", 826 => X"02", 827 => X"82",
828 => X"7C", 829 => X"00", 830 => X"00", 831 => X"00",
832 => X"00", 833 => X"00", 834 => X"08", 835 => X"18",
836 => X"28", 837 => X"48", 838 => X"88", 839 => X"88",
840 => X"FE", 841 => X"08", 842 => X"08", 843 => X"08",
844 => X"1C", 845 => X"00", 846 => X"00", 847 => X"00",
848 => X"00", 849 => X"00", 850 => X"FE", 851 => X"80",
852 => X"80", 853 => X"80", 854 => X"80", 855 => X"7C",
856 => X"02", 857 => X"02", 858 => X"02", 859 => X"82",
860 => X"7C", 861 => X"00", 862 => X"00", 863 => X"00",
864 => X"00", 865 => X"00", 866 => X"7E", 867 => X"80",
868 => X"80", 869 => X"80", 870 => X"80", 871 => X"7C",
872 => X"82", 873 => X"82", 874 => X"82", 875 => X"82",
876 => X"7C", 877 => X"00", 878 => X"00", 879 => X"00",
880 => X"00", 881 => X"00", 882 => X"FE", 883 => X"02",
884 => X"02", 885 => X"04", 886 => X"08", 887 => X"10",
888 => X"10", 889 => X"10", 890 => X"10", 891 => X"10",
892 => X"38", 893 => X"00", 894 => X"00", 895 => X"00",
896 => X"00", 897 => X"00", 898 => X"7C", 899 => X"82",
900 => X"82", 901 => X"82", 902 => X"82", 903 => X"7C",
904 => X"82", 905 => X"82", 906 => X"82", 907 => X"82",
908 => X"7C", 909 => X"00", 910 => X"00", 911 => X"00",
912 => X"00", 913 => X"00", 914 => X"7C", 915 => X"82",
916 => X"82", 917 => X"82", 918 => X"82", 919 => X"7C",
920 => X"02", 921 => X"02", 922 => X"02", 923 => X"02",
924 => X"FC", 925 => X"00", 926 => X"00", 927 => X"00",
928 => X"00", 929 => X"00", 930 => X"00", 931 => X"00",
932 => X"18", 933 => X"18", 934 => X"00", 935 => X"00",
936 => X"00", 937 => X"18", 938 => X"18", 939 => X"00",
940 => X"00", 941 => X"00", 942 => X"00", 943 => X"00",
944 => X"00", 945 => X"00", 946 => X"00", 947 => X"00",
948 => X"18", 949 => X"18", 950 => X"00", 951 => X"00",
952 => X"00", 953 => X"08", 954 => X"08", 955 => X"10",
956 => X"20", 957 => X"00", 958 => X"00", 959 => X"00",
960 => X"00", 961 => X"00", 962 => X"00", 963 => X"00",
964 => X"02", 965 => X"0C", 966 => X"30", 967 => X"C0",
968 => X"30", 969 => X"0C", 970 => X"02", 971 => X"00",
972 => X"00", 973 => X"00", 974 => X"00", 975 => X"00",
976 => X"00", 977 => X"00", 978 => X"00", 979 => X"00",
980 => X"FE", 981 => X"00", 982 => X"00", 983 => X"00",
984 => X"00", 985 => X"00", 986 => X"FE", 987 => X"00",
988 => X"00", 989 => X"00", 990 => X"00", 991 => X"00",
992 => X"00", 993 => X"00", 994 => X"00", 995 => X"00",
996 => X"80", 997 => X"60", 998 => X"18", 999 => X"06",
1000 => X"18", 1001 => X"60", 1002 => X"80", 1003 => X"00",
1004 => X"00", 1005 => X"00", 1006 => X"00", 1007 => X"00",
1008 => X"00", 1009 => X"00", 1010 => X"38", 1011 => X"44",
1012 => X"82", 1013 => X"82", 1014 => X"02", 1015 => X"04",
1016 => X"08", 1017 => X"10", 1018 => X"10", 1019 => X"00",
1020 => X"10", 1021 => X"00", 1022 => X"00", 1023 => X"00",
1024 => X"00", 1025 => X"00", 1026 => X"38", 1027 => X"44",
1028 => X"82", 1029 => X"82", 1030 => X"9E", 1031 => X"A2",
1032 => X"A2", 1033 => X"9E", 1034 => X"80", 1035 => X"42",
1036 => X"3C", 1037 => X"00", 1038 => X"00", 1039 => X"00",
1040 => X"00", 1041 => X"00", 1042 => X"10", 1043 => X"28",
1044 => X"28", 1045 => X"28", 1046 => X"44", 1047 => X"7C",
1048 => X"44", 1049 => X"44", 1050 => X"82", 1051 => X"82",
1052 => X"82", 1053 => X"00", 1054 => X"00", 1055 => X"00",
1056 => X"00", 1057 => X"00", 1058 => X"FC", 1059 => X"82",
1060 => X"82", 1061 => X"82", 1062 => X"84", 1063 => X"F8",
1064 => X"84", 1065 => X"82", 1066 => X"82", 1067 => X"82",
1068 => X"FC", 1069 => X"00", 1070 => X"00", 1071 => X"00",
1072 => X"00", 1073 => X"00", 1074 => X"7C", 1075 => X"82",
1076 => X"80", 1077 => X"80", 1078 => X"80", 1079 => X"80",
1080 => X"80", 1081 => X"80", 1082 => X"80", 1083 => X"82",
1084 => X"7C", 1085 => X"00", 1086 => X"00", 1087 => X"00",
1088 => X"00", 1089 => X"00", 1090 => X"F0", 1091 => X"88",
1092 => X"84", 1093 => X"84", 1094 => X"82", 1095 => X"82",
1096 => X"82", 1097 => X"82", 1098 => X"84", 1099 => X"84",
1100 => X"F8", 1101 => X"00", 1102 => X"00", 1103 => X"00",
1104 => X"00", 1105 => X"00", 1106 => X"FE", 1107 => X"80",
1108 => X"80", 1109 => X"80", 1110 => X"80", 1111 => X"FC",
1112 => X"80", 1113 => X"80", 1114 => X"80", 1115 => X"80",
1116 => X"FE", 1117 => X"00", 1118 => X"00", 1119 => X"00",
1120 => X"00", 1121 => X"00", 1122 => X"FE", 1123 => X"80",
1124 => X"80", 1125 => X"80", 1126 => X"80", 1127 => X"FC",
1128 => X"80", 1129 => X"80", 1130 => X"80", 1131 => X"80",
1132 => X"80", 1133 => X"00", 1134 => X"00", 1135 => X"00",
1136 => X"00", 1137 => X"00", 1138 => X"7C", 1139 => X"82",
1140 => X"80", 1141 => X"80", 1142 => X"80", 1143 => X"9E",
1144 => X"82", 1145 => X"82", 1146 => X"82", 1147 => X"82",
1148 => X"7C", 1149 => X"00", 1150 => X"00", 1151 => X"00",
1152 => X"00", 1153 => X"00", 1154 => X"82", 1155 => X"82",
1156 => X"82", 1157 => X"82", 1158 => X"82", 1159 => X"7C",
1160 => X"82", 1161 => X"82", 1162 => X"82", 1163 => X"82",
1164 => X"82", 1165 => X"00", 1166 => X"00", 1167 => X"00",
1168 => X"00", 1169 => X"00", 1170 => X"38", 1171 => X"10",
1172 => X"10", 1173 => X"10", 1174 => X"10", 1175 => X"10",
1176 => X"10", 1177 => X"10", 1178 => X"10", 1179 => X"10",
1180 => X"38", 1181 => X"00", 1182 => X"00", 1183 => X"00",
1184 => X"00", 1185 => X"00", 1186 => X"1C", 1187 => X"08",
1188 => X"08", 1189 => X"08", 1190 => X"08", 1191 => X"08",
1192 => X"08", 1193 => X"08", 1194 => X"88", 1195 => X"88",
1196 => X"70", 1197 => X"00", 1198 => X"00", 1199 => X"00",
1200 => X"00", 1201 => X"00", 1202 => X"82", 1203 => X"82",
1204 => X"84", 1205 => X"84", 1206 => X"88", 1207 => X"F0",
1208 => X"88", 1209 => X"84", 1210 => X"84", 1211 => X"82",
1212 => X"82", 1213 => X"00", 1214 => X"00", 1215 => X"00",
1216 => X"00", 1217 => X"00", 1218 => X"80", 1219 => X"80",
1220 => X"80", 1221 => X"80", 1222 => X"80", 1223 => X"80",
1224 => X"80", 1225 => X"80", 1226 => X"80", 1227 => X"80",
1228 => X"FE", 1229 => X"00", 1230 => X"00", 1231 => X"00",
1232 => X"00", 1233 => X"00", 1234 => X"82", 1235 => X"C6",
1236 => X"AA", 1237 => X"AA", 1238 => X"AA", 1239 => X"92",
1240 => X"92", 1241 => X"82", 1242 => X"82", 1243 => X"82",
1244 => X"82", 1245 => X"00", 1246 => X"00", 1247 => X"00",
1248 => X"00", 1249 => X"00", 1250 => X"82", 1251 => X"C2",
1252 => X"A2", 1253 => X"A2", 1254 => X"A2", 1255 => X"92",
1256 => X"8A", 1257 => X"8A", 1258 => X"8A", 1259 => X"86",
1260 => X"82", 1261 => X"00", 1262 => X"00", 1263 => X"00",
1264 => X"00", 1265 => X"00", 1266 => X"7C", 1267 => X"82",
1268 => X"82", 1269 => X"82", 1270 => X"82", 1271 => X"82",
1272 => X"82", 1273 => X"82", 1274 => X"82", 1275 => X"82",
1276 => X"7C", 1277 => X"00", 1278 => X"00", 1279 => X"00",
1280 => X"00", 1281 => X"00", 1282 => X"7C", 1283 => X"82",
1284 => X"82", 1285 => X"82", 1286 => X"82", 1287 => X"FC",
1288 => X"80", 1289 => X"80", 1290 => X"80", 1291 => X"80",
1292 => X"80", 1293 => X"00", 1294 => X"00", 1295 => X"00",
1296 => X"00", 1297 => X"00", 1298 => X"7C", 1299 => X"82",
1300 => X"82", 1301 => X"82", 1302 => X"82", 1303 => X"82",
1304 => X"82", 1305 => X"B2", 1306 => X"8A", 1307 => X"84",
1308 => X"7A", 1309 => X"00", 1310 => X"00", 1311 => X"00",
1312 => X"00", 1313 => X"00", 1314 => X"7C", 1315 => X"82",
1316 => X"82", 1317 => X"82", 1318 => X"82", 1319 => X"FC",
1320 => X"A0", 1321 => X"90", 1322 => X"88", 1323 => X"84",
1324 => X"82", 1325 => X"00", 1326 => X"00", 1327 => X"00",
1328 => X"00", 1329 => X"00", 1330 => X"7C", 1331 => X"82",
1332 => X"80", 1333 => X"80", 1334 => X"80", 1335 => X"7C",
1336 => X"02", 1337 => X"02", 1338 => X"02", 1339 => X"82",
1340 => X"7C", 1341 => X"00", 1342 => X"00", 1343 => X"00",
1344 => X"00", 1345 => X"00", 1346 => X"FE", 1347 => X"92",
1348 => X"10", 1349 => X"10", 1350 => X"10", 1351 => X"10",
1352 => X"10", 1353 => X"10", 1354 => X"10", 1355 => X"10",
1356 => X"10", 1357 => X"00", 1358 => X"00", 1359 => X"00",
1360 => X"00", 1361 => X"00", 1362 => X"82", 1363 => X"82",
1364 => X"82", 1365 => X"82", 1366 => X"82", 1367 => X"82",
1368 => X"82", 1369 => X"82", 1370 => X"82", 1371 => X"82",
1372 => X"7C", 1373 => X"00", 1374 => X"00", 1375 => X"00",
1376 => X"00", 1377 => X"00", 1378 => X"82", 1379 => X"82",
1380 => X"82", 1381 => X"44", 1382 => X"44", 1383 => X"44",
1384 => X"28", 1385 => X"28", 1386 => X"28", 1387 => X"10",
1388 => X"10", 1389 => X"00", 1390 => X"00", 1391 => X"00",
1392 => X"00", 1393 => X"00", 1394 => X"82", 1395 => X"82",
1396 => X"82", 1397 => X"82", 1398 => X"92", 1399 => X"92",
1400 => X"AA", 1401 => X"AA", 1402 => X"AA", 1403 => X"C6",
1404 => X"82", 1405 => X"00", 1406 => X"00", 1407 => X"00",
1408 => X"00", 1409 => X"00", 1410 => X"82", 1411 => X"82",
1412 => X"44", 1413 => X"44", 1414 => X"28", 1415 => X"38",
1416 => X"28", 1417 => X"44", 1418 => X"44", 1419 => X"82",
1420 => X"82", 1421 => X"00", 1422 => X"00", 1423 => X"00",
1424 => X"00", 1425 => X"00", 1426 => X"82", 1427 => X"82",
1428 => X"44", 1429 => X"44", 1430 => X"28", 1431 => X"28",
1432 => X"10", 1433 => X"10", 1434 => X"10", 1435 => X"10",
1436 => X"10", 1437 => X"00", 1438 => X"00", 1439 => X"00",
1440 => X"00", 1441 => X"00", 1442 => X"FE", 1443 => X"82",
1444 => X"04", 1445 => X"04", 1446 => X"08", 1447 => X"38",
1448 => X"20", 1449 => X"40", 1450 => X"40", 1451 => X"82",
1452 => X"FE", 1453 => X"00", 1454 => X"00", 1455 => X"00",
1456 => X"00", 1457 => X"00", 1458 => X"38", 1459 => X"20",
1460 => X"20", 1461 => X"20", 1462 => X"20", 1463 => X"20",
1464 => X"20", 1465 => X"20", 1466 => X"20", 1467 => X"20",
1468 => X"38", 1469 => X"00", 1470 => X"00", 1471 => X"00",
1472 => X"00", 1473 => X"00", 1474 => X"00", 1475 => X"00",
1476 => X"80", 1477 => X"40", 1478 => X"20", 1479 => X"10",
1480 => X"08", 1481 => X"04", 1482 => X"02", 1483 => X"00",
1484 => X"00", 1485 => X"00", 1486 => X"00", 1487 => X"00",
1488 => X"00", 1489 => X"00", 1490 => X"38", 1491 => X"08",
1492 => X"08", 1493 => X"08", 1494 => X"08", 1495 => X"08",
1496 => X"08", 1497 => X"08", 1498 => X"08", 1499 => X"08",
1500 => X"38", 1501 => X"00", 1502 => X"00", 1503 => X"00",
1504 => X"00", 1505 => X"00", 1506 => X"00", 1507 => X"10",
1508 => X"28", 1509 => X"44", 1510 => X"82", 1511 => X"00",
1512 => X"00", 1513 => X"00", 1514 => X"00", 1515 => X"00",
1516 => X"00", 1517 => X"00", 1518 => X"00", 1519 => X"00",
1520 => X"00", 1521 => X"00", 1522 => X"00", 1523 => X"00",
1524 => X"00", 1525 => X"00", 1526 => X"00", 1527 => X"00",
1528 => X"00", 1529 => X"00", 1530 => X"00", 1531 => X"00",
1532 => X"FE", 1533 => X"00", 1534 => X"00", 1535 => X"00",
1536 => X"00", 1537 => X"00", 1538 => X"20", 1539 => X"20",
1540 => X"10", 1541 => X"10", 1542 => X"08", 1543 => X"00",
1544 => X"00", 1545 => X"00", 1546 => X"00", 1547 => X"00",
1548 => X"00", 1549 => X"00", 1550 => X"00", 1551 => X"00",
1552 => X"00", 1553 => X"00", 1554 => X"00", 1555 => X"00",
1556 => X"00", 1557 => X"00", 1558 => X"3A", 1559 => X"C6",
1560 => X"82", 1561 => X"82", 1562 => X"82", 1563 => X"C6",
1564 => X"3A", 1565 => X"00", 1566 => X"00", 1567 => X"00",
1568 => X"00", 1569 => X"00", 1570 => X"80", 1571 => X"80",
1572 => X"80", 1573 => X"80", 1574 => X"B8", 1575 => X"C6",
1576 => X"82", 1577 => X"82", 1578 => X"82", 1579 => X"C6",
1580 => X"B8", 1581 => X"00", 1582 => X"00", 1583 => X"00",
1584 => X"00", 1585 => X"00", 1586 => X"00", 1587 => X"00",
1588 => X"00", 1589 => X"00", 1590 => X"3C", 1591 => X"C2",
1592 => X"80", 1593 => X"80", 1594 => X"80", 1595 => X"C2",
1596 => X"3C", 1597 => X"00", 1598 => X"00", 1599 => X"00",
1600 => X"00", 1601 => X"00", 1602 => X"02", 1603 => X"02",
1604 => X"02", 1605 => X"02", 1606 => X"3A", 1607 => X"C6",
1608 => X"82", 1609 => X"82", 1610 => X"82", 1611 => X"C6",
1612 => X"3A", 1613 => X"00", 1614 => X"00", 1615 => X"00",
1616 => X"00", 1617 => X"00", 1618 => X"00", 1619 => X"00",
1620 => X"00", 1621 => X"00", 1622 => X"38", 1623 => X"C6",
1624 => X"82", 1625 => X"FC", 1626 => X"80", 1627 => X"C6",
1628 => X"38", 1629 => X"00", 1630 => X"00", 1631 => X"00",
1632 => X"00", 1633 => X"00", 1634 => X"3C", 1635 => X"42",
1636 => X"80", 1637 => X"80", 1638 => X"F8", 1639 => X"80",
1640 => X"80", 1641 => X"80", 1642 => X"80", 1643 => X"80",
1644 => X"80", 1645 => X"00", 1646 => X"00", 1647 => X"00",
1648 => X"00", 1649 => X"00", 1650 => X"00", 1651 => X"00",
1652 => X"00", 1653 => X"00", 1654 => X"38", 1655 => X"C6",
1656 => X"82", 1657 => X"7E", 1658 => X"02", 1659 => X"C6",
1660 => X"38", 1661 => X"00", 1662 => X"00", 1663 => X"00",
1664 => X"00", 1665 => X"00", 1666 => X"80", 1667 => X"80",
1668 => X"80", 1669 => X"80", 1670 => X"B8", 1671 => X"C6",
1672 => X"82", 1673 => X"82", 1674 => X"82", 1675 => X"82",
1676 => X"82", 1677 => X"00", 1678 => X"00", 1679 => X"00",
1680 => X"00", 1681 => X"00", 1682 => X"00", 1683 => X"10",
1684 => X"00", 1685 => X"00", 1686 => X"10", 1687 => X"10",
1688 => X"10", 1689 => X"10", 1690 => X"10", 1691 => X"12",
1692 => X"0C", 1693 => X"00", 1694 => X"00", 1695 => X"00",
1696 => X"00", 1697 => X"00", 1698 => X"00", 1699 => X"04",
1700 => X"00", 1701 => X"00", 1702 => X"04", 1703 => X"04",
1704 => X"04", 1705 => X"04", 1706 => X"04", 1707 => X"88",
1708 => X"70", 1709 => X"00", 1710 => X"00", 1711 => X"00",
1712 => X"00", 1713 => X"00", 1714 => X"00", 1715 => X"80",
1716 => X"80", 1717 => X"80", 1718 => X"86", 1719 => X"B8",
1720 => X"C0", 1721 => X"B0", 1722 => X"88", 1723 => X"84",
1724 => X"82", 1725 => X"00", 1726 => X"00", 1727 => X"00",
1728 => X"00", 1729 => X"00", 1730 => X"20", 1731 => X"20",
1732 => X"20", 1733 => X"20", 1734 => X"20", 1735 => X"20",
1736 => X"20", 1737 => X"20", 1738 => X"20", 1739 => X"10",
1740 => X"0E", 1741 => X"00", 1742 => X"00", 1743 => X"00",
1744 => X"00", 1745 => X"00", 1746 => X"00", 1747 => X"00",
1748 => X"00", 1749 => X"00", 1750 => X"AC", 1751 => X"D2",
1752 => X"92", 1753 => X"92", 1754 => X"92", 1755 => X"92",
1756 => X"92", 1757 => X"00", 1758 => X"00", 1759 => X"00",
1760 => X"00", 1761 => X"00", 1762 => X"00", 1763 => X"00",
1764 => X"00", 1765 => X"00", 1766 => X"B8", 1767 => X"C6",
1768 => X"82", 1769 => X"82", 1770 => X"82", 1771 => X"82",
1772 => X"82", 1773 => X"00", 1774 => X"00", 1775 => X"00",
1776 => X"00", 1777 => X"00", 1778 => X"00", 1779 => X"00",
1780 => X"00", 1781 => X"00", 1782 => X"38", 1783 => X"C6",
1784 => X"82", 1785 => X"82", 1786 => X"82", 1787 => X"C6",
1788 => X"38", 1789 => X"00", 1790 => X"00", 1791 => X"00",
1792 => X"00", 1793 => X"00", 1794 => X"00", 1795 => X"00",
1796 => X"00", 1797 => X"00", 1798 => X"B8", 1799 => X"C6",
1800 => X"82", 1801 => X"FC", 1802 => X"80", 1803 => X"80",
1804 => X"80", 1805 => X"00", 1806 => X"00", 1807 => X"00",
1808 => X"00", 1809 => X"00", 1810 => X"00", 1811 => X"00",
1812 => X"00", 1813 => X"00", 1814 => X"3A", 1815 => X"C6",
1816 => X"82", 1817 => X"7E", 1818 => X"02", 1819 => X"02",
1820 => X"02", 1821 => X"00", 1822 => X"00", 1823 => X"00",
1824 => X"00", 1825 => X"00", 1826 => X"00", 1827 => X"00",
1828 => X"00", 1829 => X"00", 1830 => X"B8", 1831 => X"C6",
1832 => X"80", 1833 => X"80", 1834 => X"80", 1835 => X"80",
1836 => X"80", 1837 => X"00", 1838 => X"00", 1839 => X"00",
1840 => X"00", 1841 => X"00", 1842 => X"00", 1843 => X"00",
1844 => X"00", 1845 => X"00", 1846 => X"7C", 1847 => X"82",
1848 => X"80", 1849 => X"7E", 1850 => X"02", 1851 => X"82",
1852 => X"7C", 1853 => X"00", 1854 => X"00", 1855 => X"00",
1856 => X"00", 1857 => X"00", 1858 => X"80", 1859 => X"80",
1860 => X"80", 1861 => X"80", 1862 => X"F8", 1863 => X"80",
1864 => X"80", 1865 => X"80", 1866 => X"80", 1867 => X"42",
1868 => X"3C", 1869 => X"00", 1870 => X"00", 1871 => X"00",
1872 => X"00", 1873 => X"00", 1874 => X"00", 1875 => X"00",
1876 => X"00", 1877 => X"00", 1878 => X"82", 1879 => X"82",
1880 => X"82", 1881 => X"82", 1882 => X"82", 1883 => X"C6",
1884 => X"3A", 1885 => X"00", 1886 => X"00", 1887 => X"00",
1888 => X"00", 1889 => X"00", 1890 => X"00", 1891 => X"00",
1892 => X"00", 1893 => X"00", 1894 => X"82", 1895 => X"82",
1896 => X"82", 1897 => X"82", 1898 => X"44", 1899 => X"28",
1900 => X"10", 1901 => X"00", 1902 => X"00", 1903 => X"00",
1904 => X"00", 1905 => X"00", 1906 => X"00", 1907 => X"00",
1908 => X"00", 1909 => X"00", 1910 => X"82", 1911 => X"92",
1912 => X"92", 1913 => X"92", 1914 => X"92", 1915 => X"92",
1916 => X"6C", 1917 => X"00", 1918 => X"00", 1919 => X"00",
1920 => X"00", 1921 => X"00", 1922 => X"00", 1923 => X"00",
1924 => X"00", 1925 => X"00", 1926 => X"00", 1927 => X"82",
1928 => X"44", 1929 => X"28", 1930 => X"38", 1931 => X"44",
1932 => X"82", 1933 => X"00", 1934 => X"00", 1935 => X"00",
1936 => X"00", 1937 => X"00", 1938 => X"00", 1939 => X"00",
1940 => X"00", 1941 => X"00", 1942 => X"00", 1943 => X"82",
1944 => X"42", 1945 => X"3C", 1946 => X"08", 1947 => X"08",
1948 => X"30", 1949 => X"00", 1950 => X"00", 1951 => X"00",
1952 => X"00", 1953 => X"00", 1954 => X"00", 1955 => X"00",
1956 => X"00", 1957 => X"00", 1958 => X"00", 1959 => X"FE",
1960 => X"04", 1961 => X"08", 1962 => X"30", 1963 => X"40",
1964 => X"FE", 1965 => X"00", 1966 => X"00", 1967 => X"00",
1968 => X"00", 1969 => X"00", 1970 => X"10", 1971 => X"20",
1972 => X"20", 1973 => X"20", 1974 => X"40", 1975 => X"80",
1976 => X"40", 1977 => X"20", 1978 => X"20", 1979 => X"20",
1980 => X"10", 1981 => X"00", 1982 => X"00", 1983 => X"00",
1984 => X"00", 1985 => X"00", 1986 => X"10", 1987 => X"10",
1988 => X"10", 1989 => X"10", 1990 => X"10", 1991 => X"10",
1992 => X"10", 1993 => X"10", 1994 => X"10", 1995 => X"10",
1996 => X"10", 1997 => X"00", 1998 => X"00", 1999 => X"00",
2000 => X"00", 2001 => X"00", 2002 => X"10", 2003 => X"08",
2004 => X"08", 2005 => X"08", 2006 => X"04", 2007 => X"02",
2008 => X"04", 2009 => X"08", 2010 => X"08", 2011 => X"08",
2012 => X"10", 2013 => X"00", 2014 => X"00", 2015 => X"00",
2016 => X"00", 2017 => X"00", 2018 => X"00", 2019 => X"00",
2020 => X"00", 2021 => X"00", 2022 => X"60", 2023 => X"92",
2024 => X"0C", 2025 => X"00", 2026 => X"00", 2027 => X"00",
2028 => X"00", 2029 => X"00", 2030 => X"00", 2031 => X"00",
2032 => X"00", 2033 => X"00", 2034 => X"00", 2035 => X"00",
2036 => X"00", 2037 => X"00", 2038 => X"00", 2039 => X"00",
2040 => X"00", 2041 => X"00", 2042 => X"00", 2043 => X"00",
2044 => X"00", 2045 => X"00", 2046 => X"00", 2047 => X"00",
others => X"00"
-- AUTOMATICALLY GENERATED... STOP
);
begin
s_EN <= i_EN;
p_rom : process (i_clock)
begin
if rising_edge(i_clock) then
if s_EN = '1' then
o_DO <= c_rom(conv_integer(i_ADDR));
end if;
end if;
end process p_rom;
end Behavioral;
|
bsd-3-clause
|
9029cdb3e0a90a81b48304eac812f065
| 0.412178 | 2.522365 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/register_file.vhd
| 1 | 2,072 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 01:28:25 03/22/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: register_file - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity register_file is
generic(
addr_width : integer := 5; -- log2(number of regs)
reg_width : integer := 32 -- width of a reg
);
port(
clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
wr_addr : in std_logic_vector(addr_width - 1 downto 0);
wr_data : in std_logic_vector(reg_width - 1 downto 0);
rd_addr : in std_logic_vector(addr_width - 1 downto 0);
rd_data : out std_logic_vector(reg_width - 1 downto 0);
rd_addr_2 : in std_logic_vector(addr_width - 1 downto 0);
rd_data_2 : out std_logic_vector(reg_width - 1 downto 0);
rd_addr_3 : in std_logic_vector(addr_width - 1 downto 0);
rd_data_3 : out std_logic_vector(reg_width - 1 downto 0)
);
end register_file;
architecture Behavioral of register_file is
type reg_file_type is array (2**addr_width - 1 downto 0) of std_logic_vector (reg_width - 1 downto 0);
signal reg_file, reg_file_2, reg_file_3 : reg_file_type;
begin
process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
reg_file <= (others => (others => '0'));
reg_file_2 <= (others => (others => '0'));
reg_file_3 <= (others => (others => '0'));
else
if wr_en = '1' then
reg_file(to_integer(unsigned(wr_addr))) <= wr_data;
reg_file_2(to_integer(unsigned(wr_addr))) <= wr_data;
reg_file_3(to_integer(unsigned(wr_addr))) <= wr_data;
end if;
end if;
end if;
end process;
rd_data <= reg_file(to_integer(unsigned(rd_addr)));
rd_data_2 <= reg_file_2(to_integer(unsigned(rd_addr_2)));
rd_data_3 <= reg_file_3(to_integer(unsigned(rd_addr_3)));
end Behavioral;
|
mit
|
35b9152aeced730372591ad0bccd1974
| 0.598938 | 2.97274 | false | false | false | false |
LemurPwned/classic-fpga
|
machines/code_det.vhdl
| 1 | 1,005 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity code_det is
port (
clk : in std_logic;
I : in std_logic_vector (3 downto 0);
O : out std_logic
);
end entity;
-- seq 9721
architecture code_det of code_det is
type state_type is (A, B, C, D);
signal state : state_type := A;
begin
process(clk)
begin
if rising_edge(clk) then
case state is
when A=>
O<='0';
if I=9 then
state<=B;
else
state<=A;
end if;
when B=>
O<='0';
if I=7 then
state<=C;
else
state<=A;
end if;
when C=>
O<='0';
if I=2 then
state<=D;
else
state<=C;
end if;
when D=>
if I=1 then
O<='1';
state<=A;
else
O<='1';
state<=A;
end if;
end case;
end if;
end process;
end architecture;
|
gpl-3.0
|
d1a2bf4207bd2551f07e7b13239d87dd
| 0.464677 | 3.465517 | false | false | false | false |
14bmkelley/Environmental-Mouse
|
environmental_mouse.vhdl
| 1 | 3,301 |
----------------------------------------------------------------------------------
-- Team: The Team Formally Known as Queen
-- Engineers: Brandon Kelley, Ignacio DeAnquin, Alan Nonaka and Anthony Velasquez
--
-- Create Date: December 3, 2015
-- Design Name: Environmental Mouse
-- Module Name: environmental_mouse.vhdl
-- Project Name: Environmental Mouse
-- Target Devices: Basys 3
-- Tool versions: Vivado 14.4
-- Description: This module controls the power of a PS/2 mouse, shutting it off
-- if it is found to be inactive.
-- Dependencies:
-- Hardware:
-- * Computer with Vivado software
-- * Basys 3 circuit board
-- * PS/2 mouse
-- * Jumper wires
-- * LEDs and resistors
-- * NPN Transistor
-- Software:
-- * Clock frequency divider
-- Version: 1.0.0
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Environmental mouse port description
entity environmental_mouse is
port (
ps2_data : in std_logic; -- Data from the mouse to read signal
board_clk : in std_logic; -- Clock from board to keep processes in time
board_btn : in std_logic; -- Button from board to turn mouse back on
red_led : out std_logic; -- LED lit up when mouse is turned off
yellow_led : out std_logic; -- LED lit up when mouse is waiting to turn off
green_led : out std_logic; -- LED lit up when mouse is active
mouse_power : out std_logic -- Signal controlling power to the mouse
);
end environmental_mouse;
-- Environmental mouse architecture description
architecture arch of environmental_mouse is
-- Clock divider port description
component clk_div2 is
port (
clk : in std_logic; -- Input clock
sclk : out std_logic -- Output (divided) clock
);
end component;
-- Power checker port description
component nas_counter is
port (
nas_data : in std_logic; -- Data used to reset counter
nas_clk : in std_logic; -- Clock used to keep processes in time
nas_btn : in std_logic; -- Button used to reset counter
nas_red : out std_logic; -- Signal used to show mouse is in off state
nas_yellow : out std_logic; -- Signal used to show mouse is in waiting state
nas_green : out std_logic -- Signal used to show mouse is in on state
);
end component;
-- Signals used to store intermediate values
signal slow_clk : std_logic; -- The divided clock
signal red : std_logic; -- The red led output
signal yellow : std_logic; -- The yellow led output
signal green : std_logic; -- The green led output
begin
-- Divide the clock to a usable speed
clk_divider : clk_div2
port map (
clk => board_clk,
sclk => slow_clk
);
-- Check which state the system is in
power_checker : nas_counter
port map (
nas_data => ps2_data,
nas_clk => slow_clk,
nas_btn => board_btn,
nas_red => red,
nas_yellow => yellow,
nas_green => green
);
-- Assign appropriate output values
red_led <= red;
yellow_led <= yellow;
green_led <= green;
mouse_power <= yellow or green;
end arch;
|
gpl-2.0
|
31f7901bb9152f5aede0a960483406fd
| 0.598909 | 4.030525 | false | false | false | false |
jimmystelzer/8086compipelineemvhdl
|
processor/src/processor.vhd
| 1 | 13,653 |
------------------------------------------------------------------
-- Processador Intel 8086 arquiteturado em pipeline e simplificado
------------------------------------------------------------------
-- Desenvolvedores: Jimmy Pinto Stelzer, Bruno Goulart e Bruno Paes
-- Baseado no exemplo de implementação do MIPS dos professores Fernando Moraes e Ney Calazans.
------------------------------------------------------------------
------------------------
-- Definições Gerais
------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package p_intel_8086 is
type instructions is
(JMP,CMP,JZ,LOOPNZ,HLT,ADD,MOVRR,MOVRI,MOVRM,NOP);
type microinstruction is record
op: instructions; -- meneumonicos
rsCode: STD_LOGIC_VECTOR (2 downto 0);
rdCode: STD_LOGIC_VECTOR (2 downto 0);
param: STD_LOGIC_VECTOR (31 downto 0);
modc: STD_LOGIC_VECTOR (1 downto 0);
w: std_logic;
ex: std_logic;
mem: std_logic;
wb: std_logic;
end record;
end p_intel_8086;
-------------------------------------
-- Registrador do pipeline
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_intel_8086.all;
entity regpl is
generic( INIT_VALUE : STD_LOGIC_VECTOR(83 downto 0) := (others=>'0') );
port( clock, reset, enable : in std_logic;
D : in STD_LOGIC_VECTOR (83 downto 0);
I : in instructions;
O : out instructions;
Q : out STD_LOGIC_VECTOR (83 downto 0)
);
end regpl;
architecture regpl of regpl is
begin
process(clock, reset)
begin
if reset = '1' then
Q <= INIT_VALUE(83 downto 0);
O <= NOP;
elsif clock'event and clock = '0' then
if enable = '1' then
Q <= D;
O <= I;
end if;
end if;
end process;
end regpl;
-------------------------------------
-- Registrador de 16bits para AX, BX, CX, DX, SP, BP, SI, DI, ES, DS, SS e ES.
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity reg16 is
generic( INIT_VALUE : STD_LOGIC_VECTOR(15 downto 0) := (others=>'0') );
port( clock, reset, enable : in std_logic;
D : in STD_LOGIC_VECTOR (15 downto 0);
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end reg16;
architecture reg16 of reg16 is
begin
process(clock, reset)
begin
if reset = '1' then
Q <= INIT_VALUE(15 downto 0);
elsif clock'event and clock = '0' then
if enable = '1' then
Q <= D;
end if;
end if;
end process;
end reg16;
-------------------------------------
-- Banco de Registradores
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.p_intel_8086.all;
entity reg_bank is
port( clock, reset, enable : in std_logic;
w : in std_logic;
RsCode, RdCode : in std_logic_vector( 2 downto 0);
RD : in std_logic_vector(15 downto 0);
R1, R2: out std_logic_vector(15 downto 0));
end reg_bank;
architecture reg_bank of reg_bank is
type bank is array(0 to 7) of std_logic_vector(15 downto 0);
signal reg : bank;
begin
g1: for i in 0 to 7 generate
rx: entity work.reg16 port map(clock=>clock, reset=>reset, enable=>'1', D=>RD, Q=>reg(i));
end generate g1;
R1 <= reg(CONV_INTEGER(RsCode)) when w='1' else --AX CX DX BX SP BP SI DI
"00000000" & reg(0)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --AL
"00000000" & reg(1)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --CL
"00000000" & reg(2)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --DL
"00000000" & reg(3)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --BL
"00000000" & reg(4)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --AH
"00000000" & reg(5)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --CH
"00000000" & reg(6)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --DH
"00000000" & reg(7)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0'; --BH
R2 <= reg(CONV_INTEGER(RdCode)) when w='1' else --AX CX DX BX SP BP SI DI
"00000000" & reg(0)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --AL
"00000000" & reg(1)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --CL
"00000000" & reg(2)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --DL
"00000000" & reg(3)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --BL
"00000000" & reg(4)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --AH
"00000000" & reg(5)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --CH
"00000000" & reg(6)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --DH
"00000000" & reg(7)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0'; --BH
end reg_bank;
-------------------------------------
-- ULA
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.p_intel_8086.all;
entity alu is
port( op1, op2 : in std_logic_vector(15 downto 0);
param : in std_logic_vector(31 downto 0);
dest : out std_logic_vector(15 downto 0);
opalu : in instructions;
w : in std_logic
);
end alu;
architecture alu of alu is
signal flags : std_logic_vector(15 downto 0) := (others=>'0');
signal soma : std_logic_vector(15 downto 0) := (others=>'0');
begin
-- FLAGS
soma <= (op1+op2);
-- ZF
flags(6) <= '1' when (op2-op1)=0 and (opalu=ADD or opalu=CMP or opalu=LOOPNZ) else
'0' when (op2-op1)/=0 and (opalu=ADD or opalu=CMP or opalu=LOOPNZ);
-- SF
flags(7) <= '1' when soma<0 and opalu=ADD else
'0' when soma>0 and opalu=ADD;
-- CF
flags(0) <= '1' when soma>255 and w='0' and opalu=ADD else
'0' when soma<255 and w='0' and opalu=ADD;
-- OF
flags(11) <= '1' when (soma<-128 or (op1+op2)>127) and w='0' and opalu=ADD else
'0' when (soma>-128 and (op1+op2)<127) and w='0' and opalu=ADD;
-- AF
flags(4) <= '1' when soma>65535 and w='1' and opalu=ADD else
'0' when soma<65535 and w='1' and opalu=ADD;
-- PF
flags(2) <= '1' when CONV_INTEGER(soma) mod 2=0 and w='0' and opalu=ADD else
'0' when CONV_INTEGER(soma) mod 2/=0 and w='0' and opalu=ADD;
--(JMP,CMP,JZ,LOOPNZ,HLT,ADD,MOVRR,MOVRI,MOVRM,NOP)
dest <=
op1 + op2 when opalu=ADD else
op2 when opalu=MOVRR else
param(31 downto 16) when opalu=MOVRI else
op1 - 2 when opalu=LOOPNZ else -- CX--
(others=>'1') when opalu=JZ and flags(6)='1' else -- seta dest
(others=>'0'); --nop, hlt, cmp, movrm, jmp,
end alu;
-----------------------------------------
-- Control
-----------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_intel_8086.all;
entity control_unit is
port(clock, reset : in std_logic;
uins : out microinstruction;
ir : in std_logic_vector(39 downto 0)
);
end control_unit;
architecture control_unit of control_unit is
signal i : instructions;
signal di : std_logic;
begin
i <= MOVRI when ir(39 downto 36)="1011" else
MOVRR when ir(39 downto 34)="100010" else
ADD when ir(39 downto 34)="000000" else
CMP when ir(39 downto 34)="100000" else
MOVRM when ir(39 downto 33)="0110011" else
HLT when ir(39 downto 32)="11110100" else
LOOPNZ when ir(39 downto 32)="11100000" else
JZ when ir(39 downto 32)="01110100" else
JMP when ir(39 downto 32)="11101001" else
NOP;
uins.op <= i;
-- execution
uins.ex <= '1' when i/=NOP and i/=JMP else
'0';
-- write back
uins.wb <= '0' when i=NOP or i=HLT or i=JZ or i=CMP or i=JMP else
'1';
-- memory
uins.mem <= '1' when i=MOVRM else
'0';
-- w
uins.w <= ir(35) when i=MOVRI else
ir(32) when i=MOVRM or i=CMP or i=ADD or i=MOVRR else
--'1' when i=LOOPNZ else --?
'X'; --Unknown
-- mod
uins.modc <= ir(31 downto 30) when i=MOVRM or i=CMP or i=ADD or i=MOVRR else
"XX"; -- Unknown
-- di
di <= ir(33) when i=CMP or i=ADD or i=MOVRR else
'X';
-- rdCode
uins.rdCode <= ir(34 downto 32) when i=MOVRI else
ir(26 downto 24) when i=MOVRM or (di='1' and (i=CMP or i=ADD or i=MOVRR)) else
ir(29 downto 27) when di='0' and (i=CMP or i=ADD or i=MOVRR) else
"001" when i=LOOPNZ else
(others=>'X');
-- rsCode
uins.rsCode <= ir(26 downto 24) when i=MOVRM or (di='0' and (i=CMP or i=ADD or i=MOVRR)) else
ir(29 downto 27) when di='1' and (i=CMP or i=ADD or i=MOVRR) else
(others=>'X');
-- param -- usado para carregar as informações como offset(-low|-high), seg(-low|-high), data(-low|-high), addr(-low|-high), disp
uins.param <= "00000000" & "00000000" & "00000000" & ir(31 downto 24) when (i=JZ or i=LOOPNZ) and ir(31)='0' else
"11111111" & "11111111" & "11111111" & ir(31 downto 24) when (i=JZ or i=LOOPNZ) and ir(31)='1' else
"00000000" & "00000000" & "00000000" & ir(23 downto 16) when i=CMP and ir(23)='0' else
"11111111" & "11111111" & "11111111" & ir(23 downto 16) when i=CMP and ir(23)='1' else
"00000000" & ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) when i=MOVRM and ir(23)='0' else
"11111111" & ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) when i=MOVRM and ir(23)='1' else
ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) & ir(31 downto 24) when i=MOVRI else
(others=>'X');
--39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
--1 0 1 1 w d d d MOVRI Param(7-0 & 15-8 & 23-16 & 31-24) se w = 1 else Param(31-24)
--0 1 1 0 0 1 1 w m m s s s d d d MOVRM Param(7-0 & 15-8 & 23-16)
--1 0 0 0 0 0 di w m m s s s d d d CMP Param(23-16) se di = 0 inverte sss e ddd
--0 0 0 0 0 0 di w m m s s s d d d ADD Param() se di = 0 inverte sss e ddd
--1 0 0 0 1 0 di w m m s s s d d d MOVRR Param() se di = 0 inverte sss e ddd
--1 1 1 1 0 1 0 0 HLT
--1 1 1 0 0 0 0 0 LOOPNZ Param(31-24) | w = 1 | rd = 001
--0 1 1 1 0 1 0 0 JZ Param(31-24) | w=0
--1 1 1 0 1 0 0 1 JMP Param(7-0 & 15-8 & 23-16 & 31-24)
-- NOP
end control_unit;
---------------------------
-- BIU - Bus Interface Unit (simplificada)
---------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity biu is
port( addr : in std_logic_vector(19 downto 0); -- endereço
clock : in std_logic;
reset : in std_logic;
mode : in std_logic; -- modo -> 0 = leitura; 1 = escrita
mtype : in std_logic; -- tipo -> 0 = instruções; 1 = dados;
memc : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de instruções
memd : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de dados
datain : in std_logic_vector(39 downto 0); -- dados a serem gravados
dataout : out std_logic_vector(39 downto 0) -- dados lidos
);
end biu;
architecture biu of biu is
signal datai : std_logic_vector(39 downto 0);
signal posi : integer;
signal posf : integer;
begin
gen : process(clock,reset)
begin
if (reset = '1') then
datai <= (others=>'X');
posi <= 0;
posf <= 0;
elsif(clock'event and clock='1') then
case mtype is
when '0' => -- memoria de instruções
if mode='0' then -- leitura
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
datai <= memc(posi to posf);
elsif mode='1' then -- escrita
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
memc(posi to posf) <= datain;
end if;
when '1' => -- memoria de dados
if mode='0' then -- leitura
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
datai <= memd(posi to posf);
elsif mode='1' then -- escrita
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
memd(posi to posf) <= datain;
end if;
when others =>
datai <= (others=>'X');
end case;
end if;
end process;
dataout<= datai;
end biu;
--------------------------------
-- Chip
--------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_intel_8086.all;
entity chip is
port( clock, reset : in std_logic;
memc : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de instruções
memd : inout std_logic_vector(0 to 1023) -- 1024bits -> 128bytes -- entrada e saida da memoria de dados
);
end chip;
architecture chip of chip is
signal IP,addr: std_logic_vector(19 downto 0) := (others=>'0');
signal mode,mtype,wrb,walu,enablerb: std_logic := 'X';
signal datain,dataout,ir: std_logic_vector(39 downto 0) := (others=>'X');
signal uins: microinstruction;
signal opalu: instructions;
signal RD,R1,R2,op1,op2,dest : std_logic_vector(15 downto 0);
signal param : std_logic_vector(31 downto 0);
signal RsCode, RdCode : std_logic_vector(2 downto 0);
begin
biu: entity work.biu port map(addr=>addr, clock=>clock, reset=>reset, mode=>mode, mtype=>mtype, memc=>memc, memd=>memd,datain=>datain,dataout=>dataout);
ctrl: entity work.control_unit port map(clock=>clock, reset=>reset, uins=>uins, ir=>ir);
alu: entity work.alu port map(op1=>op1, op2=>op2, param=>param, dest=>dest, opalu=>opalu, w=>walu);
rb: entity work.reg_bank port map(clock=>clock, reset=>reset, enable=>enablerb, w=>wrb, RsCode=>RsCode, RdCode=>RdCode, RD=>RD, R1=>R1,R2=>R2);
--entity regpl is
-- port( clock, reset, enable : in std_logic;
-- D : in STD_LOGIC_VECTOR (83 downto 0);
-- I : in instructions;
-- O : out instructions;
-- Q : out STD_LOGIC_VECTOR (83 downto 0)
-- );
end chip;
|
gpl-3.0
|
49dba389e047b7ee5cb560e425ced2df
| 0.585293 | 2.874316 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/trans_tb.vhdl
| 1 | 892 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity trans_tb is
end entity;
architecture behav of trans_tb is
component trans is
port (
A : in std_logic_vector (3 downto 0);
clk : in std_logic;
se : in std_logic;
C: out std_logic_vector(3 downto 0);
sum : out std_logic_vector(2 downto 0)
);
end component;
signal A, C : std_logic_vector(3 downto 0):="0000";
signal sum : std_logic_vector(2 downto 0) :="000";
signal clk, se: std_logic :='0';
constant period : time := 10 ns;
begin
uut: trans port map (clk=>clk, A=>A, C=>C, se=>se, sum=>sum);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc:
process
begin
se<='1';
A<="1101";
wait for 20 ns;
se<='0';
wait for 100 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
dc1e9b021a4f9ab2a64f97351a41e6a3
| 0.596413 | 3.197133 | false | false | false | false |
freecores/yavga
|
vhdl/vga_ctrl.vhd
| 1 | 20,247 |
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_ctrl is
-- generic (
-- g_H_SIZE : integer := 800; -- horizontal size of input image, MAX 800
-- g_V_SIZE : integer := 600 -- vertical size of input image, MAX 600
-- );
port (
i_clk : in std_logic; -- must be 50MHz
i_reset : in std_logic;
-- vga horizontal and vertical sync
o_h_sync : out std_logic;
o_v_sync : out std_logic;
-- horizontal and vertical sync enable (allow power saving on ?VESA? Monitors)
i_h_sync_en : in std_logic;
i_v_sync_en : in std_logic;
-- vga R G B signals (1 bit for each component (8 colors))
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic;
-- chars RAM memory
i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
i_chr_clk : in std_logic;
i_chr_en : in std_logic;
i_chr_we : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
i_chr_rst : in std_logic;
-- waveform RAM memory
i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_wav_we : in std_logic;
i_wav_clk : in std_logic;
i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0) --;
--o_DOA : OUT std_logic_vector(15 downto 0)
);
end vga_ctrl;
-- vga timings used
-- 0 TOT
-- ...-----------------|=============== PERIOD ==============|--...
-- | |
-- ...__ ___________________________ _______...
-- \_________/ \_________/
--
-- | | | | | | |
-- | | | | | | |
-- ...--|----S----|-F--|=======D=======|==B===|====S====|=F==|--...
-- Y R I A Y R
-- N O S C N O
-- C N P K C N
-- T T L P T T
-- I P T O I P
-- M O I R M O
-- E R M C E R
-- C E H C
-- H H
-- | | | | | | |
-- ...|---------|----|===============|======|=========|====|--...
-- HPx: 120 56 800 63 120 56 px (h PERIOD = 1039 px)
-- VLn: 6 37 600 23 6 37 ln (v PERIOD = 666 ln)
--
-- and with 50Mhz dot clock (20ns dot time):
-- | | | | | | |
-- ...|---------|----|===============|======|=========|====|--...
--Htime: 2.4 1.12 16 1.26 2.4 1.12 usec (h PERIOD = 20.78 usec) Hfreq 48123.195 Hz
--Vtime: 124.68 768.86 12468 477.94 124.68 768.68 usec (v PERIOD = 13839.48 usec) Vfreq 72.257 Hz
architecture rtl of vga_ctrl is
--
signal s_h_count : std_logic_vector(c_H_COUNT_W - 1 downto 0); -- horizontal pixel counter
signal s_v_count : std_logic_vector(c_V_COUNT_W - 1 downto 0); -- verticalal line counter
signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter mod 16 (char height)
signal s_h_sync : std_logic; -- horizontal sync trigger
signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger
--
-- signals for the charmaps Block RAM component...
signal s_charmaps_en : std_logic;
signal s_charmaps_ADDR : std_logic_vector (c_INTCHMAP_ADDR_BUS_W - 1 downto 0);
signal s_charmaps_DO : std_logic_vector (c_INTCHMAP_DATA_BUS_W - 1 downto 0);
--
-- to manage the outside display region's blanking
signal s_display : std_logic;
--
--
-- to manage the chars ram address and the ram ascii
signal s_chars_ram_addr : std_logic_vector(c_INTCHR_ADDR_BUS_W - 1 downto 0);
signal s_chars_ascii : std_logic_vector(c_INTCHR_DATA_BUS_W - 1 downto 0);
signal s_chars_EN_r : std_logic;
-- to manage the waveform ram address and data
signal s_waveform_ADDRB : std_logic_vector (c_WAVFRM_ADDR_BUS_W - 1 downto 0);
signal s_waveform_DOB : std_logic_vector (c_WAVFRM_DATA_BUS_W - 1 downto 0);
-- charmaps
-- |------| |-----------------|
-- | P | | D D D D D D D D |
-- |======| |=================|
-- | 8 | | 7 6 5 4 3 2 1 0 |
-- |======| |=================|
-- | Free | | Row char pixels |
-- |------| |-----------------|
--
component charmaps_rom
port(
i_EN : in std_logic;
i_clock : in std_logic;
i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 16 x ascii code (W=8 x H=16 pixel)
o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8 bit char pixel
);
end component;
-- wave form or video-line memory
-- |------| |-------------------------------------------|
-- | P P | | D D D | D D D | D D D D D D D D D D |
-- |======| |===========================================|
-- |17 16 | | 15 14 13 | 12 11 10 | 9 8 7 6 5 4 3 2 1 0 |
-- |======| |===========================================|
-- | Free | | Reserv. | R G B | vert. pos. |
-- |------| |-------------------------------------------|
--
component waveform_ram
port(
i_DIA : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_WEA : in std_logic;
i_clockA : in std_logic;
i_ADDRA : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
--o_DOA : OUT std_logic_vector(15 downto 0);
--
i_DIB : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_WEB : in std_logic;
i_clockB : in std_logic;
i_ADDRB : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
o_DOB : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0)
);
end component;
component chars_RAM
port(
i_clock_rw : in std_logic;
i_EN_rw : in std_logic;
i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
i_ADDR_rw : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
i_DI_rw : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
o_DI_rw : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
i_SSR : in std_logic;
i_clock_r : in std_logic;
i_EN_r : in std_logic;
i_ADDR_r : in std_logic_vector(c_INTCHR_ADDR_BUS_W - 1 downto 0);
o_DO_r : out std_logic_vector(c_INTCHR_DATA_BUS_W - 1 downto 0)
);
end component;
attribute U_SET : string;
attribute U_SET of "u0_chars_RAM" : label is "u0_chars_RAM_uset";
attribute U_SET of "u1_charmaps_rom" : label is "u1_charmaps_rom_uset";
attribute U_SET of "u2_waveform_ram" : label is "u2_waveform_ram_uset";
-- to read some configuration params from the char ram
signal s_config_time : std_logic;
--
-- to manage the background and cursor colors
signal s_cursor_color : std_logic_vector(2 downto 0) := "000";
signal s_bg_color : std_logic_vector(2 downto 0) := "000";
--
-- to manage the cursor position
signal s_cursor_x : std_logic_vector(c_H_COUNT_W - 1 downto 0);
signal s_cursor_y : std_logic_vector(c_V_COUNT_W - 1 downto 0);
function f_is_cursor_pixel(
s_h, s_v, s_cur_x, s_cur_y : std_logic_vector)
return boolean is
begin
return ((s_h = s_cur_x) or (s_v = s_cur_y));
end f_is_cursor_pixel;
function f_is_grid_pixel(
s_h, s_v : std_logic_vector)
return boolean is
begin
return (
(s_h(c_GRID_BIT downto 0) = c_GRID_SIZE(c_GRID_BIT downto 0)) or
(s_v(c_GRID_BIT downto 0) = c_GRID_SIZE(c_GRID_BIT downto 0))
);
end f_is_grid_pixel;
function f_is_waveform_pixel(
s_v, s_wav, s_wav_prev : std_logic_vector)
return boolean is
begin
return (
((s_v >= s_wav) and (s_v <= s_wav_prev)) or
((s_v <= s_wav) and (s_v >= s_wav_prev))
);
end f_is_waveform_pixel;
begin
-- read config params from ram...
p_config : process(i_clk)
begin
if rising_edge(i_clk) then
case s_chars_ram_addr is
when c_CFG_BG_CUR_COLOR_ADDR => -- bg and curs color are on the same byte byte
s_config_time <= '1';
s_cursor_color <= s_chars_ascii(2 downto 0);
s_bg_color <= s_chars_ascii(5 downto 3);
when c_CFG_CURS_XY1 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
when c_CFG_CURS_XY2 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
when c_CFG_CURS_XY3 => -- xy coords spans on three bytes
s_config_time <= '1';
s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
when others =>
s_config_time <= '0';
end case;
end if;
end process;
-- enable the ram both
-- - during the display time
-- - to read configuration params
s_chars_EN_r <= s_display or s_config_time;
-- modify the chars_ram address
s_chars_ram_addr <= s_v_count(9 downto 4) & s_h_count(9 downto 3);
u0_chars_RAM : chars_RAM port map(
i_clock_rw => i_chr_clk,
i_EN_rw => i_chr_en,
i_WE_rw => i_chr_we,
i_ADDR_rw => i_chr_addr,
i_DI_rw => i_chr_data,
o_DI_rw => o_chr_data,
i_SSR => i_chr_rst,
i_clock_r => not i_clk,
i_EN_r => s_chars_EN_r,
i_ADDR_r => s_chars_ram_addr,
o_DO_r => s_chars_ascii
);
-- modify the charmaps address (each 16 s_v_count - chars are 16 pixel tall)
-- v----- ascii code ------v v-- vert px mod 16 --v (chars are 16 pixel tall)
--s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count(3 downto 0));
s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count_d_4);
s_charmaps_en <=
'1' when s_h_count(2 downto 0) = "111" -- each 8 h_count (chars are 8 pixel wide)
else '0';
u1_charmaps_rom : charmaps_rom port map(
i_en => s_charmaps_en,
i_clock => not i_clk,
i_ADDR => s_charmaps_ADDR,
o_DO => s_charmaps_DO
);
-- modify the waveform address
s_waveform_ADDRB <= s_h_count(9 downto 0);
u2_waveform_ram : waveform_ram port map(
i_DIA => i_wav_d,
i_WEA => i_wav_we,
i_clockA => i_wav_clk,
i_ADDRA => i_wav_addr,
--o_DOA => o_DOA,
--
i_DIB => "1111111111111111",
i_WEB => '0',
i_clockB => not i_clk,
i_ADDRB => s_waveform_ADDRB,
o_DOB => s_waveform_DOB
);
-- generate a single clock pulse on hsync falling
p_pulse_on_hsync_falling : process(i_clk)
variable v_h_sync1 : std_logic;
begin
if rising_edge(i_clk) then
s_h_sync_pulse <= not s_h_sync and v_h_sync1;
v_h_sync1 := s_h_sync;
end if;
end process;
-- control the reset, increment and overflow of the horizontal pixel count
p_H_PX_COUNT : process(i_clk) --, i_reset)
begin
if rising_edge(i_clk) then
if i_reset = '1' or s_h_count = c_H_PERIODpx then -- sync reset
s_h_count <= (others => '0');
else
s_h_count <= s_h_count + 1;
end if;
end if;
end process;
-- control the reset, increment and overflow of the vertical pixel count
p_V_LN_COUNT : process(i_clk)
begin
if rising_edge(i_clk) then
if i_reset = '1' or s_v_count = c_V_PERIODln then -- sync reset
s_v_count <= (others => '0');
s_v_count_d_4 <= s_v_count(3 downto 0);
elsif s_h_sync_pulse = '1' then
s_v_count <= s_v_count + 1;
s_v_count_d_4 <= s_v_count(3 downto 0);
end if;
end if;
end process;
-- set the horizontal sync high time and low time according to the constants
p_MGM_H_SYNC : process(i_clk) --, i_reset)
begin
if rising_edge(i_clk) then
if (s_h_count = c_H_DISPLAYpx + c_H_BACKPORCHpx) then
s_h_sync <= '0';
elsif (s_h_count = c_H_PERIODpx - c_H_FRONTPORCHpx) then
s_h_sync <= '1';
end if;
end if;
end process;
o_h_sync <= s_h_sync and i_h_sync_en;
-- set the vertical sync high time and low time according to the constants
p_MGM_V_SYNC : process(i_clk) --, i_reset)
begin
--if falling_edge(i_clk) then
if rising_edge(i_clk) then
if i_v_sync_en = '0' or
(s_v_count = (c_V_DISPLAYln + c_V_BACKPORCHln)) then
o_v_sync <= '0';
elsif (s_v_count = (c_V_PERIODln - c_V_FRONTPORCHln)) then --and (s_h_sync_pulse = '1') then
o_v_sync <= '1';
end if;
end if;
end process;
-- asserts the blaking signal (active low)
p_MGM_BLANK : process (i_clk) --, i_reset)
begin
if rising_edge(i_clk) then
-- if we are outside the visible range on the screen then tell the RAMDAC to blank
-- in this section by putting s_display low
if not (s_h_count < c_H_DISPLAYpx and s_v_count < c_V_DISPLAYln) then
s_display <= '0';
else
s_display <= '1';
end if;
end if;
end process;
-- generates the r g b signals showing chars, grid and "cross cursor"
p_MGM_RGB : process (i_clk)
variable v_previous_pixel : std_logic_vector(9 downto 0) := "0100101100";
begin
if rising_edge(i_clk) then -- not async reset
if i_reset = '1' then -- sync reset
o_r <= '0';
o_g <= '0';
o_b <= '0';
else
if s_display = '1' then -- display zone
if (
f_is_cursor_pixel(s_h_count, s_v_count, s_cursor_x, s_cursor_y) or
f_is_grid_pixel(s_h_count, s_v_count)
) and (s_v_count(9) = '0') -- < 512
then -- draw the cursor and/or WaveForm Grid references
o_r <= s_cursor_color(2);
o_g <= s_cursor_color(1);
o_b <= s_cursor_color(0);
elsif
f_is_waveform_pixel(s_v_count, s_waveform_DOB(c_V_COUNT_W - 1 downto 0), v_previous_pixel)
then -- draw the waveform pixel...
o_r <= s_waveform_DOB(12) or s_waveform_DOB(15); -- the "or" is only
o_g <= s_waveform_DOB(11) or s_waveform_DOB(14); -- to not warning
o_b <= s_waveform_DOB(10) or s_waveform_DOB(13); -- unused signals
else -- draw the background and charmaps
case (s_h_count(2 downto 0)) is
when "000" => o_g <= s_charmaps_DO(7) xor s_bg_color(1);
when "001" => o_g <= s_charmaps_DO(6) xor s_bg_color(1);
when "010" => o_g <= s_charmaps_DO(5) xor s_bg_color(1);
when "011" => o_g <= s_charmaps_DO(4) xor s_bg_color(1);
when "100" => o_g <= s_charmaps_DO(3) xor s_bg_color(1);
when "101" => o_g <= s_charmaps_DO(2) xor s_bg_color(1);
when "110" => o_g <= s_charmaps_DO(1) xor s_bg_color(1);
when "111" => o_g <= s_charmaps_DO(0) xor s_bg_color(1);
when others => o_g <= 'X';
end case;
o_r <= s_bg_color(2);
--o_g <= s_bg_color(1);
o_b <= s_bg_color(0);
end if;
else -- blank zone
-- the blanking zone
o_r <= '0';
o_g <= '0';
o_b <= '0';
end if; -- if s_display
v_previous_pixel := s_waveform_DOB(9 downto 0);
end if; -- if i_reset
end if; -- if rising_edge(i_clk)
end process;
end rtl;
|
bsd-3-clause
|
3ea377a5e7d07ecc32cb751f7899141a
| 0.468464 | 3.420101 | false | false | false | false |
freecores/yavga
|
vhdl/s3e_starter_1600k.vhd
| 1 | 11,175 |
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity s3e_starter_1600k is
port (i_clk : in std_logic;
o_hsync : out std_logic;
o_vsync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic);
end s3e_starter_1600k;
architecture Behavioral of s3e_starter_1600k is
component vga_ctrl
port(
i_clk : in std_logic;
i_reset : in std_logic;
i_h_sync_en : in std_logic;
i_v_sync_en : in std_logic;
i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
i_chr_clk : in std_logic;
i_chr_en : in std_logic;
i_chr_we : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
i_chr_rst : in std_logic;
i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
i_wav_clk : in std_logic;
i_wav_we : in std_logic;
i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
o_h_sync : out std_logic;
o_v_sync : out std_logic;
o_r : out std_logic;
o_g : out std_logic;
o_b : out std_logic;
o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0)
);
end component;
signal s_hsync : std_logic;
signal s_vsync : std_logic;
signal s_r : std_logic;
signal s_g : std_logic;
signal s_b : std_logic;
signal s_vsync_count : std_logic_vector(7 downto 0) := (others => '0');
signal s_vsync1 : std_logic;
signal s_chr_addr : std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0); -- := (others => '0');
signal s_chr_data : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0); -- := (others => '0');
signal s_rnd : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0); -- := (others => '0');
signal s_chr_we : std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
signal s_wav_addr : std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
signal s_wav_d : std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
signal s_mul : std_logic_vector(7 downto 0);
signal s_initialized : std_logic := '0';
attribute U_SET : string;
attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset";
begin
o_hsync <= s_hsync;
o_vsync <= s_vsync;
o_r <= s_r;
o_g <= s_g;
o_b <= s_b;
u1_vga_ctrl : vga_ctrl port map(
i_clk => i_clk,
i_reset => '0',
o_h_sync => s_hsync,
o_v_sync => s_vsync,
i_h_sync_en => '1',
i_v_sync_en => '1',
o_r => s_r,
o_g => s_g,
o_b => s_b,
i_chr_addr => s_chr_addr, --B"000_0000_0000",
i_chr_data => s_chr_data, --X"00000000",
o_chr_data => open,
i_chr_clk => i_clk,
i_chr_en => '1',
i_chr_we => s_chr_we,
i_chr_rst => '0',
i_wav_d => s_wav_d, --X"0000", --s_rnd(15 downto 0), --
i_wav_clk => i_clk,
i_wav_we => '0', --'0', -- '1',
i_wav_addr => s_wav_addr --B"00_0000_0000" --s_chr_addr(9 downto 0) --
);
s_wav_addr <= s_rnd(1 downto 0) & s_vsync_count;
s_mul <= s_vsync_count(3 downto 0) * s_vsync_count(3 downto 0);
s_wav_d <= B"000" & s_rnd(2 downto 0) & B"00" & s_mul;
--s_wav_d <= B"000" & "100" & B"00" & s_mul;
-- s_chr_data <= s_rnd;
-- p_write_chars : process(i_clk)
-- begin
-- if rising_edge(i_clk) then
-- -- during the sync time in order to avoid flickering
-- -- and each 128 vsync in order to stop for a while
-- -- will write random chars...
-- if s_vsync_count(7) = '1' and (s_hsync = '0' or s_vsync = '0') then
-- -- generate a pseudo random 32 bit number
-- s_rnd <= s_rnd(30 downto 0) & (s_rnd(31) xnor s_rnd(21) xnor s_rnd(1) xnor s_rnd(0));
-- -- increment the address and write enable...
-- s_chr_addr <= s_chr_addr + 1;
-- s_chr_we <= "1111";
-- else
-- s_chr_addr <= s_chr_addr;
-- s_chr_we <= "0000";
-- s_rnd <= s_rnd;
-- end if;
-- end if;
-- end process;
-- cols cols
-- 00_01_02_03 ... 96_97_98_99
-- row_00 "00000000000" ... "00000011000"
-- row_01 "00000100000" ... "00000111000"
-- ... ... ...
-- row_37 "10010100000" ... "10010111000"
p_write_chars : process(i_clk)
begin
if rising_edge(i_clk) then
if s_initialized = '0' then
case s_vsync_count(2 downto 0) is
when "000" => -- write ABCD
s_chr_we <= "1111";
s_chr_addr <= "00000000000";
s_chr_data <= "01000001" & "01000010" & "01000011" & "01000100";
when "001" => -- write EFGH
s_chr_we <= "1111";
s_chr_addr <= "00000011000";
s_chr_data <= "01000101" & "01000110" & "01000111" & "01001000";
when "010" => -- write IJKL
s_chr_we <= "1111";
s_chr_addr <= "00000100000";
s_chr_data <= "01001001" & "01001010" & "01001011" & "01001100";
when "011" => -- write MNOP
s_chr_we <= "1111";
s_chr_addr <= "10010100000";
s_chr_data <= "01001101" & "01001110" & "01001111" & "01010000";
when "100" => -- write QRST
s_chr_we <= "1111";
s_chr_addr <= "10010111000";
s_chr_data <= "01010001" & "01010010" & "01010011" & "01010100";
when "101" => -- write config grid and cursor color (overwrite RAM defaults)
s_chr_we <= "1111";
s_chr_addr <= c_CFG_BG_CUR_COLOR_ADDR(c_CFG_BG_CUR_COLOR_ADDR'left downto 2); -- c_CFG_BG_CUR_COLOR_ADDR >> 2
-- ND bgColor grid,cur ND curs_x curs_y
s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
-- |--------108-------|-------109-------|----110-----|--111--|
s_initialized <= '1';
when others =>
s_chr_we <= (others => '0');
s_chr_addr <= (others => '1');
s_chr_data <= "10111110" & "10111101" & "10111100" & "10111011";
end case;
else
s_chr_we <= (others => '0');
end if;
end if;
end process;
-- p_rnd_bit : process(i_clk)
-- variable v_rnd_fb : std_logic;
-- variable v_rnd : std_logic_vector(31 downto 0);
-- begin
-- if rising_edge(i_clk) then
-- s_rnd_bit <= v_rnd_fb;
-- v_rnd_fb := v_rnd(31) xnor v_rnd(21) xnor v_rnd(1) xnor v_rnd(0);
-- v_rnd := v_rnd(30 downto 0) & v_rnd_fb;
-- end if;
-- end process;
p_vsync_count : process(i_clk)
begin
if rising_edge(i_clk) then
s_vsync1 <= s_vsync;
if (not s_vsync and s_vsync1) = '1' then -- pulse on vsync falling
s_vsync_count <= s_vsync_count + 1;
end if;
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
8ee6f747bf81acbd822d033ee695ff71
| 0.448143 | 3.556652 | false | false | false | false |
mitchsm/nvc
|
test/parse/process.vhd
| 2 | 363 |
architecture a of b is
signal x : integer := 0;
begin
p: process is
begin
end process;
process
variable y : integer := 5;
begin
x <= y;
end process;
process (x) is
begin
x <= x + 1;
end process;
postponed process is
begin
end process;
postponed assert x = 1;
end architecture;
|
gpl-3.0
|
8761789b79971d9bc1e0c0ac295c338a
| 0.5427 | 4.078652 | false | false | false | false |
mitchsm/nvc
|
test/regress/real1.vhd
| 3 | 739 |
entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0;
r := 2.0;
r := r * 3.0;
assert r > 5.99999;
assert r < 6.00001;
assert integer(r) = 6;
r := real(5);
report real'image(r);
report real'image(-5.262e2);
report real'image(1.23456);
report real'image(2.0 ** (-1));
report real'image(real'low);
report real'image(real'high);
wait;
end process;
end architecture;
|
gpl-3.0
|
88da84c7af188250097311c06941875c
| 0.488498 | 3.40553 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/names/a_clk-rtl-a.vhd
| 1 | 31,903 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-a.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: a_clk-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of a_clk
--
architecture rtl of a_clk is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component a_fsm --
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
clk : in std_ulogic;
d9_core_di : in std_ulogic_vector(1 downto 0);
d9_core_en : in std_ulogic_vector(1 downto 0);
d9_core_pu : in std_ulogic_vector(1 downto 0);
data_core_do : out std_ulogic_vector(1 downto 0);
data_core_i33 : in std_ulogic_vector(7 downto 0);
data_core_i34 : in std_ulogic_vector(7 downto 0);
data_core_o35 : out std_ulogic_vector(7 downto 0);
data_core_o36 : out std_ulogic_vector(7 downto 0);
data_i1 : in std_ulogic_vector(7 downto 0);
data_o1 : out std_ulogic_vector(7 downto 0);
di : in std_ulogic_vector(7 downto 0);
di2 : in std_ulogic_vector(8 downto 0);
disp2_en : in std_ulogic_vector(7 downto 0);
disp_ls_port : out std_ulogic;
disp_ms_port : out std_ulogic;
iosel_bus : out std_ulogic_vector(7 downto 0);
iosel_bus_disp : out std_ulogic;
iosel_bus_ls_hr : out std_ulogic;
iosel_bus_ls_min : out std_ulogic;
iosel_bus_ms_hr : out std_ulogic;
iosel_bus_ms_min : out std_ulogic;
iosel_bus_nosel : out std_ulogic;
iosel_bus_port : out std_ulogic_vector(7 downto 0);
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component ios_e --
-- No Generated Generics
port (
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end component;
-- ---------
component pad_pads_e --
-- No Generated Generics
port (
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end component;
-- ---------
component testctrl_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component alreg --
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4 --
-- No Generated Generics
port (
-- Generated Port for Entity count4
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4 --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad --
-- No Generated Generics
port (
-- Generated Port for Entity keypad
columns : in std_ulogic_vector(2 downto 0);
rows : out std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan --
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen --
-- No Generated Generics
port (
-- Generated Port for Entity timegen
one_minute : out std_ulogic;
one_second : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_di : std_ulogic_vector(1 downto 0);
signal d9_do : std_ulogic_vector(1 downto 0);
signal d9_en : std_ulogic_vector(1 downto 0);
signal d9_pu : std_ulogic_vector(1 downto 0);
signal data_i1 : std_ulogic_vector(7 downto 0);
signal data_i33 : std_ulogic_vector(7 downto 0);
signal data_i34 : std_ulogic_vector(7 downto 0);
signal data_o1 : std_ulogic_vector(7 downto 0);
signal data_o35 : std_ulogic_vector(7 downto 0);
signal data_o36 : std_ulogic_vector(7 downto 0);
signal di2 : std_ulogic_vector(8 downto 0);
signal disp2 : std_ulogic_vector(7 downto 0);
signal disp2_en : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic;
signal s_int_display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic;
signal s_int_display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic;
signal iosel_1 : std_ulogic;
signal iosel_2 : std_ulogic;
signal iosel_3 : std_ulogic;
signal iosel_4 : std_ulogic;
signal iosel_5 : std_ulogic;
signal iosel_6 : std_ulogic;
signal iosel_7 : std_ulogic;
signal iosel_bus : std_ulogic_vector(7 downto 0);
signal iosel_disp : std_ulogic;
signal iosel_ls_hr : std_ulogic;
signal iosel_ls_min : std_ulogic;
signal iosel_ms_hr : std_ulogic;
signal iosel_ms_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_nosel : std_ulogic;
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal pad_di_1 : std_ulogic;
signal pad_di_12 : std_ulogic;
signal pad_di_13 : std_ulogic;
signal pad_di_14 : std_ulogic;
signal pad_di_15 : std_ulogic;
signal pad_di_16 : std_ulogic;
signal pad_di_17 : std_ulogic;
signal pad_di_18 : std_ulogic;
signal pad_di_31 : std_ulogic;
signal pad_di_32 : std_ulogic;
signal pad_di_33 : std_ulogic;
signal pad_di_34 : std_ulogic;
signal pad_di_39 : std_ulogic;
signal pad_di_40 : std_ulogic;
signal pad_do_12 : std_ulogic;
signal pad_do_13 : std_ulogic;
signal pad_do_14 : std_ulogic;
signal pad_do_15 : std_ulogic;
signal pad_do_16 : std_ulogic;
signal pad_do_17 : std_ulogic;
signal pad_do_18 : std_ulogic;
signal pad_do_2 : std_ulogic;
signal pad_do_31 : std_ulogic;
signal pad_do_32 : std_ulogic;
signal pad_do_35 : std_ulogic;
signal pad_do_36 : std_ulogic;
signal pad_do_39 : std_ulogic;
signal pad_do_40 : std_ulogic;
signal pad_en_12 : std_ulogic;
signal pad_en_13 : std_ulogic;
signal pad_en_14 : std_ulogic;
signal pad_en_15 : std_ulogic;
signal pad_en_16 : std_ulogic;
signal pad_en_17 : std_ulogic;
signal pad_en_18 : std_ulogic;
signal pad_en_2 : std_ulogic;
signal pad_en_31 : std_ulogic;
signal pad_en_32 : std_ulogic;
signal pad_en_35 : std_ulogic;
signal pad_en_36 : std_ulogic;
signal pad_en_39 : std_ulogic;
signal pad_en_40 : std_ulogic;
signal pad_pu_31 : std_ulogic;
signal pad_pu_32 : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
display_ls_hr <= s_int_display_ls_hr; -- __I_O_BUS_PORT
display_ls_min <= s_int_display_ls_min; -- __I_O_BUS_PORT
display_ms_hr <= s_int_display_ms_hr; -- __I_O_BUS_PORT
display_ms_min <= s_int_display_ms_min; -- __I_O_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
clk => clk,
d9_core_di => d9_di, -- d9io
d9_core_en => d9_en, -- d9io
d9_core_pu => d9_pu, -- d9io
data_core_do => d9_do, -- d9io
data_core_i33 => data_i33, -- io data
data_core_i34 => data_i34, -- io data
data_core_o35 => data_o35, -- io data
data_core_o36 => data_o36, -- io data
data_i1 => data_i1, -- io data
data_o1 => data_o1, -- io data
di => disp2, -- io data
di2 => di2, -- io data
disp2_en => disp2_en, -- io data
disp_ls_port => display_ls_en, -- io_enable
disp_ms_port => display_ms_en, -- io_enable
iosel_bus(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(6) => iosel_6, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(7) => iosel_7, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus_disp => iosel_disp, -- IO_Select
iosel_bus_ls_hr => iosel_ls_hr, -- IO_Select
iosel_bus_ls_min => iosel_ls_min, -- IO_Select
iosel_bus_ms_hr => iosel_ms_hr, -- IO_Select
iosel_bus_ms_min => iosel_ms_min, -- IO_Select
iosel_bus_nosel => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_port => iosel_bus, -- io data
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset,
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for ios
ios: ios_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_6_gi => iosel_6, -- IO_Select
p_mix_iosel_7_gi => iosel_7, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_iosel_ms_min_gi => iosel_ms_min, -- IO_Select
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18, -- pad output enable
p_mix_pad_en_2_go => pad_en_2, -- pad output enable
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ios
-- Generated Instance Port Map for pad_pads
pad_pads: pad_pads_e
port map (
p_mix_pad_di_12_go => pad_di_12, -- data in from pad
p_mix_pad_di_13_go => pad_di_13, -- data in from pad
p_mix_pad_di_14_go => pad_di_14, -- data in from pad
p_mix_pad_di_15_go => pad_di_15, -- data in from pad
p_mix_pad_di_16_go => pad_di_16, -- data in from pad
p_mix_pad_di_17_go => pad_di_17, -- data in from pad
p_mix_pad_di_18_go => pad_di_18, -- data in from pad
p_mix_pad_di_1_go => pad_di_1, -- data in from pad
p_mix_pad_di_31_go => pad_di_31, -- data in from pad
p_mix_pad_di_32_go => pad_di_32, -- data in from pad
p_mix_pad_di_33_go => pad_di_33, -- data in from pad
p_mix_pad_di_34_go => pad_di_34, -- data in from pad
p_mix_pad_di_39_go => pad_di_39, -- data in from pad
p_mix_pad_di_40_go => pad_di_40, -- data in from pad
p_mix_pad_do_12_gi => pad_do_12, -- data out to pad
p_mix_pad_do_13_gi => pad_do_13, -- data out to pad
p_mix_pad_do_14_gi => pad_do_14, -- data out to pad
p_mix_pad_do_15_gi => pad_do_15, -- data out to pad
p_mix_pad_do_16_gi => pad_do_16, -- data out to pad
p_mix_pad_do_17_gi => pad_do_17, -- data out to pad
p_mix_pad_do_18_gi => pad_do_18, -- data out to pad
p_mix_pad_do_2_gi => pad_do_2, -- data out to pad
p_mix_pad_do_31_gi => pad_do_31, -- data out to pad
p_mix_pad_do_32_gi => pad_do_32, -- data out to pad
p_mix_pad_do_35_gi => pad_do_35, -- data out to pad
p_mix_pad_do_36_gi => pad_do_36, -- data out to pad
p_mix_pad_do_39_gi => pad_do_39, -- data out to pad
p_mix_pad_do_40_gi => pad_do_40, -- data out to pad
p_mix_pad_en_12_gi => pad_en_12, -- pad output enable
p_mix_pad_en_13_gi => pad_en_13, -- pad output enable
p_mix_pad_en_14_gi => pad_en_14, -- pad output enable
p_mix_pad_en_15_gi => pad_en_15, -- pad output enable
p_mix_pad_en_16_gi => pad_en_16, -- pad output enable
p_mix_pad_en_17_gi => pad_en_17, -- pad output enable
p_mix_pad_en_18_gi => pad_en_18, -- pad output enable
p_mix_pad_en_2_gi => pad_en_2, -- pad output enable
p_mix_pad_en_31_gi => pad_en_31, -- pad output enable
p_mix_pad_en_32_gi => pad_en_32, -- pad output enable
p_mix_pad_en_35_gi => pad_en_35, -- pad output enable
p_mix_pad_en_36_gi => pad_en_36, -- pad output enable
p_mix_pad_en_39_gi => pad_en_39, -- pad output enable
p_mix_pad_en_40_gi => pad_en_40, -- pad output enable
p_mix_pad_pu_31_gi => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_gi => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_pads
-- Generated Instance Port Map for test_ctrl
test_ctrl: testctrl_e
;
-- End of Generated Instance Port Map for test_ctrl
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0 -- Display storage buffer 0 ls_min
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1 -- Display storage buffer 1 ms_min
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2 -- Display storage buffer 2 ls_hr
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3 -- Display storage buffer 3 ms_hr
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_display_ls_hr_go => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_go => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_hr_go => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_go => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_sound_alarm_go => sound_alarm,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
columns => columns,
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
one_minute => one_minute,
one_second => one_sec_pulse,
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
392b63e10156bdf1a2969aa56090b3d4
| 0.630599 | 2.437204 | false | false | false | false |
mitchsm/nvc
|
test/regress/implicit1.vhd
| 5 | 548 |
entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
wait for 0 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 0;
wait for 1 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
824ad6c43d281f45d91d32aab85ed428
| 0.523723 | 3.702703 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/coreparameters.vhd
| 1 | 740 |
----------------------------------------------------------------------
-- Created by Microsemi SmartDesign Thu Jun 22 17:22:48 2017
-- Parameters for COREUART
----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
package coreparameters is
constant BAUD_VAL_FRCTN_EN : integer := 1;
constant FAMILY : integer := 15;
constant HDL_license : string( 1 to 1 ) := "U";
constant RX_FIFO : integer := 0;
constant RX_LEGACY_MODE : integer := 0;
constant testbench : string( 1 to 4 ) := "User";
constant TX_FIFO : integer := 0;
constant USE_SOFT_FIFO : integer := 0;
end coreparameters;
|
mit
|
d56cb0d6547198680527821af0d2499a
| 0.539189 | 4.302326 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare4.vhd
| 1 | 4,450 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare4.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare4 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare4;
ARCHITECTURE SYN OF lpm_compare4 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "0000101001";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "41"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 41 0 0 10 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
5398622f53a9dd2a9717771c05b76da8
| 0.65618 | 3.702163 | false | false | false | false |
blutsvente/MIX
|
test/results/generic/inst_a_e-rtl-a.vhd
| 1 | 8,785 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_1_e
generic (
-- Generated Generics for Entity inst_1_e
FOO : integer -- Generic generator, value __W_NODEFAULT
-- End of Generated Generics for Entity inst_1_e
);
-- No Generated Port
end component;
-- ---------
component inst_10_e
generic (
-- Generated Generics for Entity inst_10_e
FOO : integer -- Generic generator __W_NODEFAULT
-- End of Generated Generics for Entity inst_10_e
);
-- No Generated Port
end component;
-- ---------
component inst_2_e
generic (
-- Generated Generics for Entity inst_2_e
FOO : integer := 10 -- Generic generator, value
-- End of Generated Generics for Entity inst_2_e
);
-- No Generated Port
end component;
-- ---------
component inst_3_e
generic (
-- Generated Generics for Entity inst_3_e
FOO : integer := 10 -- Generic generator, value
-- End of Generated Generics for Entity inst_3_e
);
-- No Generated Port
end component;
-- ---------
component inst_4_e
generic (
-- Generated Generics for Entity inst_4_e
FOO : integer := 10 -- Generic generator, value
-- End of Generated Generics for Entity inst_4_e
);
-- No Generated Port
end component;
-- ---------
component inst_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_6_e
generic (
-- Generated Generics for Entity inst_6_e
FOO : integer := 34 -- Generic generator
-- End of Generated Generics for Entity inst_6_e
);
-- No Generated Port
end component;
-- ---------
component inst_7_e
generic (
-- Generated Generics for Entity inst_7_e
FOO : integer := 34 -- Generic generatorGeneric generator
-- End of Generated Generics for Entity inst_7_e
);
-- No Generated Port
end component;
-- ---------
component inst_8_e
generic (
-- Generated Generics for Entity inst_8_e
FOO : integer -- Generic generator __W_NODEFAULT
-- End of Generated Generics for Entity inst_8_e
);
-- No Generated Port
end component;
-- ---------
component inst_9_e
generic (
-- Generated Generics for Entity inst_9_e
FOO : integer -- Generic generator __W_NODEFAULT
-- End of Generated Generics for Entity inst_9_e
);
-- No Generated Port
end component;
-- ---------
component inst_aa_e
generic (
-- Generated Generics for Entity inst_aa_e
NO_DEFAULT : string; -- Generic without default __W_NODEFAULT
NO_NAME : string; -- Parameter without Name __W_NODEFAULT
PRE_GENERIC : something := 7; -- Apply predefined generic
WIDTH : integer := 7 -- Generic width of control
-- End of Generated Generics for Entity inst_aa_e
);
-- No Generated Port
end component;
-- ---------
component inst_ab_e
generic (
-- Generated Generics for Entity inst_ab_e
FOO : integer := 64; -- Generic width for entity
WIDTH : integer -- apply generic value 31 to inst_ab __W_NODEFAULT
-- End of Generated Generics for Entity inst_ab_e
);
-- No Generated Port
end component;
-- ---------
component inst_ac_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ad_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ae_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_m_e
generic (
-- Generated Generics for Entity inst_m_e
FOO : integer := 19 -- Generic generator
-- End of Generated Generics for Entity inst_m_e
);
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_1
inst_1: inst_1_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_1
-- Generated Instance Port Map for inst_10
inst_10: inst_10_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_10
-- Generated Instance Port Map for inst_2
inst_2: inst_2_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_2
-- Generated Instance Port Map for inst_3
inst_3: inst_3_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_3
-- Generated Instance Port Map for inst_4
inst_4: inst_4_e
generic map (
FOO => 16
)
;
-- End of Generated Instance Port Map for inst_4
-- Generated Instance Port Map for inst_5
inst_5: inst_5_e
;
-- End of Generated Instance Port Map for inst_5
-- Generated Instance Port Map for inst_6
inst_6: inst_6_e
;
-- End of Generated Instance Port Map for inst_6
-- Generated Instance Port Map for inst_7
inst_7: inst_7_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_7
-- Generated Instance Port Map for inst_8
inst_8: inst_8_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_8
-- Generated Instance Port Map for inst_9
inst_9: inst_9_e
generic map (
FOO => 32
)
;
-- End of Generated Instance Port Map for inst_9
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
generic map (
NO_DEFAULT => "nodefault",
NO_NAME => "noname",
WIDTH => 15
)
;
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
generic map (
WIDTH => 31
)
;
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: inst_ac_e
;
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: inst_ad_e
;
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: inst_ae_e
;
-- End of Generated Instance Port Map for inst_ae
-- Generated Instance Port Map for inst_m1
inst_m1: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m1
-- Generated Instance Port Map for inst_m10
inst_m10: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m10
-- Generated Instance Port Map for inst_m2
inst_m2: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m2
-- Generated Instance Port Map for inst_m3
inst_m3: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m3
-- Generated Instance Port Map for inst_m4
inst_m4: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m4
-- Generated Instance Port Map for inst_m5
inst_m5: inst_m_e
generic map (
FOO => 15
)
;
-- End of Generated Instance Port Map for inst_m5
-- Generated Instance Port Map for inst_m6
inst_m6: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m6
-- Generated Instance Port Map for inst_m7
inst_m7: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m7
-- Generated Instance Port Map for inst_m8
inst_m8: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m8
-- Generated Instance Port Map for inst_m9
inst_m9: inst_m_e
generic map (
FOO => 30
)
;
-- End of Generated Instance Port Map for inst_m9
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
79f8f2928a90ae3cab4684aecefe0912
| 0.622652 | 3.202698 | false | false | false | false |
mitchsm/nvc
|
test/regress/attr1.vhd
| 4 | 831 |
entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
process is
variable x : integer;
variable y : my_int;
begin
assert integer'left = -2147483648;
x := integer'right;
wait for 1 ns;
assert x = 2147483647;
assert positive'left = 1;
assert natural'high = integer'high;
assert integer'ascending;
assert not my_int'ascending;
x := 0;
wait for 1 ns;
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
x := 1;
y := 1;
wait for 1 ns;
assert integer'leftof(x) = 0;
assert integer'rightof(x) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
4575dc33a55adad7cc47560e12f4e2bd
| 0.547533 | 3.777273 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare16.vhd
| 1 | 4,225 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare16.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare16 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare16;
ARCHITECTURE SYN OF lpm_compare16 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_representation => "SIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "1"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare16_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
7f4d58a3de66f41d284b0e6976e8f12c
| 0.653254 | 3.785842 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/names/ddrv4-rtl-a.vhd
| 1 | 5,642 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ddrv4
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-rtl-a.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ddrv4-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ddrv4
--
architecture rtl of ddrv4 is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ddrv --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv
alarm_time : in std_ulogic_vector(3 downto 0);
current_time : in std_ulogic_vector(3 downto 0);
display : out std_ulogic_vector(6 downto 0);
key_buffer : in std_ulogic_vector(3 downto 0);
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ddrv
);
end component;
-- ---------
component and_f --
-- No Generated Generics
port (
-- Generated Port for Entity and_f
out_p : out std_ulogic;
y : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity and_f
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sound_alarm : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_display_ls_hr_go <= display_ls_hr; -- __I_O_BUS_PORT
p_mix_display_ls_min_go <= display_ls_min; -- __I_O_BUS_PORT
p_mix_display_ms_hr_go <= display_ms_hr; -- __I_O_BUS_PORT
p_mix_display_ms_min_go <= display_ms_min; -- __I_O_BUS_PORT
p_mix_sound_alarm_go <= sound_alarm; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv
port map (
alarm_time => alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time => current_time_ls_hr, -- Display storage buffer 2 ls_hr
display => display_ls_hr, -- Display storage buffer 2 ls_hr
key_buffer => key_buffer_2, -- Display storage buffer 2 ls_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(2) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ls_hr
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv
port map (
alarm_time => alarm_time_ls_min, -- Display storage buffer 0 ls_min
current_time => current_time_ls_min, -- Display storage buffer 0 ls_min
display => display_ls_min, -- Display storage buffer 0 ls_min
key_buffer => key_buffer_0, -- Display storage buffer 0 ls_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ls_min
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv
port map (
alarm_time => alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time => current_time_ms_hr, -- Display storage buffer 3 ms_hr
display => display_ms_hr, -- Display storage buffer 3 ms_hr
key_buffer => key_buffer_3, -- Display storage buffer 3 ms_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(3) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ms_hr
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv
port map (
alarm_time => alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time => current_time_ms_min, -- Display storage buffer 1 ms_min
display => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer => key_buffer_1, -- Display storage buffer 1 ms_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(1) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for d_ms_min
-- Generated Instance Port Map for u_and_f
u_and_f: and_f
port map (
out_p => sound_alarm,
y => alarm -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp...
);
-- End of Generated Instance Port Map for u_and_f
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
838528eba090d4c495ee3c2f293ce43e
| 0.638603 | 3.120575 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/CU_TOP.vhd
| 1 | 15,095 |
----------------------------------------------------------------------
-- Created by SmartDesign Thu Jun 22 17:22:48 2017
-- Version: v11.8 11.8.0.26
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
use proasic3.all;
library COREUART_LIB;
use COREUART_LIB.all;
use COREUART_LIB.CU_TOP_FPGA_UART_components.all;
----------------------------------------------------------------------
-- CU_TOP entity declaration
----------------------------------------------------------------------
entity CU_TOP is
-- Port list
port(
-- Inputs
CLK : in std_logic;
FPGA_UART_RX : in std_logic;
PWRONRESET : in std_logic;
-- Outputs
CUTTER : out std_logic;
FPGA_UART_TX : out std_logic;
L1_GPS_PWR : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
MICRO_CLK : out std_logic;
PRESSURE_PWR : out std_logic;
SAT_PWR : out std_logic;
SENS_MEM_L5_PWR : out std_logic;
VHF_PWR : out std_logic
);
end CU_TOP;
----------------------------------------------------------------------
-- CU_TOP architecture body
----------------------------------------------------------------------
architecture RTL of CU_TOP is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- CLKINT
component CLKINT
-- Port list
port(
-- Inputs
A : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- CUTTER_PWM
component CUTTER_PWM
-- Port list
port(
-- Inputs
duty : in std_logic_vector(7 downto 0);
duty_wrt : in std_logic;
ena : in std_logic;
mclk : in std_logic;
reset : in std_logic;
-- Outputs
pwm_out : out std_logic_vector(0 to 0)
);
end component;
-- CU_TOP_FPGA_UART_COREUART - Actel:DirectCore:COREUART:5.6.102
component CU_TOP_FPGA_UART_COREUART
generic(
BAUD_VAL_FRCTN_EN : integer := 1 ;
FAMILY : integer := 15 ;
RX_FIFO : integer := 0 ;
RX_LEGACY_MODE : integer := 0 ;
TX_FIFO : integer := 0
);
-- Port list
port(
-- Inputs
BAUD_VAL : in std_logic_vector(12 downto 0);
BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0);
BIT8 : in std_logic;
CLK : in std_logic;
CSN : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ODD_N_EVEN : in std_logic;
OEN : in std_logic;
PARITY_EN : in std_logic;
RESET_N : in std_logic;
RX : in std_logic;
WEN : in std_logic;
-- Outputs
DATA_OUT : out std_logic_vector(7 downto 0);
FRAMING_ERR : out std_logic;
OVERFLOW : out std_logic;
PARITY_ERR : out std_logic;
RXRDY : out std_logic;
TX : out std_logic;
TXRDY : out std_logic
);
end component;
-- OR2
component OR2
-- Port list
port(
-- Inputs
A : in std_logic;
B : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- system_clock
component system_clock
-- Port list
port(
-- Inputs
mclk : in std_logic;
reset : in std_logic;
-- Outputs
m_time : out std_logic_vector(25 downto 0)
);
end component;
-- UART_reset_monitor
component UART_reset_monitor
-- Port list
port(
-- Inputs
data_in : in std_logic_vector(7 downto 0);
mclk : in std_logic;
reset_in : in std_logic;
txrdy : in std_logic;
-- Outputs
reset_out : out std_logic
);
end component;
-- WOLF_CONTROLLER
component WOLF_CONTROLLER
-- Port list
port(
-- Inputs
clk_1hz : in std_logic;
mclk : in std_logic;
reset : in std_logic;
uart_data_in : in std_logic_vector(7 downto 0);
uart_rxrdy : in std_logic;
uart_txrdy : in std_logic;
-- Outputs
cutter_en : out std_logic;
cutter_pwm_duty : out std_logic_vector(7 downto 0);
led1 : out std_logic;
led2 : out std_logic;
uart_baud_val : out std_logic_vector(12 downto 0);
uart_baud_val_frac : out std_logic_vector(2 downto 0);
uart_data_out : out std_logic_vector(7 downto 0);
uart_oen : out std_logic;
uart_wen : out std_logic
);
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal CLKINT_0_Y : std_logic;
signal CLKINT_1_Y : std_logic;
signal CUTTER_net_0 : std_logic_vector(0 to 0);
signal FPGA_UART_DATA_OUT : std_logic_vector(7 downto 0);
signal FPGA_UART_TX_net_0 : std_logic;
signal FPGA_UART_TXRDY : std_logic;
signal LED1_net_0 : std_logic;
signal LED1_0 : std_logic;
signal LED1_2 : std_logic;
signal LED1_3 : std_logic;
signal LED2_net_0 : std_logic;
signal LED2_1 : std_logic_vector(25 to 25);
signal MICRO_CLK_net_0 : std_logic_vector(1 to 1);
signal OR2_0_Y : std_logic;
signal WOLF_CONTROLLER_cutter_pwm_duty : std_logic_vector(7 downto 0);
signal WOLF_CONTROLLER_uart_baud_val : std_logic_vector(12 downto 0);
signal WOLF_CONTROLLER_uart_baud_val_frac : std_logic_vector(2 downto 0);
signal WOLF_CONTROLLER_uart_data_out : std_logic_vector(7 downto 0);
signal CUTTER_net_1 : std_logic;
signal LED2_1_net_0 : std_logic;
signal FPGA_UART_TX_net_1 : std_logic;
signal LED1_3_net_0 : std_logic;
signal MICRO_CLK_net_1 : std_logic;
signal m_time_slice_0 : std_logic_vector(0 to 0);
signal m_time_slice_1 : std_logic_vector(10 to 10);
signal m_time_slice_2 : std_logic_vector(11 to 11);
signal m_time_slice_3 : std_logic_vector(12 to 12);
signal m_time_slice_4 : std_logic_vector(13 to 13);
signal m_time_slice_5 : std_logic_vector(14 to 14);
signal m_time_slice_6 : std_logic_vector(15 to 15);
signal m_time_slice_7 : std_logic_vector(16 to 16);
signal m_time_slice_8 : std_logic_vector(17 to 17);
signal m_time_slice_9 : std_logic_vector(18 to 18);
signal m_time_slice_10 : std_logic_vector(19 to 19);
signal m_time_slice_11 : std_logic_vector(20 to 20);
signal m_time_slice_12 : std_logic_vector(21 to 21);
signal m_time_slice_13 : std_logic_vector(22 to 22);
signal m_time_slice_14 : std_logic_vector(23 to 23);
signal m_time_slice_15 : std_logic_vector(24 to 24);
signal m_time_slice_16 : std_logic_vector(2 to 2);
signal m_time_slice_17 : std_logic_vector(3 to 3);
signal m_time_slice_18 : std_logic_vector(4 to 4);
signal m_time_slice_19 : std_logic_vector(5 to 5);
signal m_time_slice_20 : std_logic_vector(6 to 6);
signal m_time_slice_21 : std_logic_vector(7 to 7);
signal m_time_slice_22 : std_logic_vector(8 to 8);
signal m_time_slice_23 : std_logic_vector(9 to 9);
signal m_time_net_0 : std_logic_vector(25 downto 0);
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal GND_net : std_logic;
signal VCC_net : std_logic;
----------------------------------------------------------------------
-- Inverted Signals
----------------------------------------------------------------------
signal RESET_N_IN_POST_INV0_0 : std_logic;
begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
GND_net <= '0';
VCC_net <= '1';
----------------------------------------------------------------------
-- Inversions
----------------------------------------------------------------------
RESET_N_IN_POST_INV0_0 <= NOT OR2_0_Y;
----------------------------------------------------------------------
-- TieOff assignments
----------------------------------------------------------------------
L1_GPS_PWR <= '0';
VHF_PWR <= '0';
SENS_MEM_L5_PWR <= '0';
SAT_PWR <= '0';
PRESSURE_PWR <= '0';
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
CUTTER_net_1 <= CUTTER_net_0(0);
CUTTER <= CUTTER_net_1;
LED2_1_net_0 <= LED2_1(25);
LED2 <= LED2_1_net_0;
FPGA_UART_TX_net_1 <= FPGA_UART_TX_net_0;
FPGA_UART_TX <= FPGA_UART_TX_net_1;
LED1_3_net_0 <= LED1_3;
LED1 <= LED1_3_net_0;
MICRO_CLK_net_1 <= MICRO_CLK_net_0(1);
MICRO_CLK <= MICRO_CLK_net_1;
----------------------------------------------------------------------
-- Slices assignments
----------------------------------------------------------------------
LED2_1(25) <= m_time_net_0(25);
MICRO_CLK_net_0(1) <= m_time_net_0(1);
m_time_slice_0(0) <= m_time_net_0(0);
m_time_slice_1(10) <= m_time_net_0(10);
m_time_slice_2(11) <= m_time_net_0(11);
m_time_slice_3(12) <= m_time_net_0(12);
m_time_slice_4(13) <= m_time_net_0(13);
m_time_slice_5(14) <= m_time_net_0(14);
m_time_slice_6(15) <= m_time_net_0(15);
m_time_slice_7(16) <= m_time_net_0(16);
m_time_slice_8(17) <= m_time_net_0(17);
m_time_slice_9(18) <= m_time_net_0(18);
m_time_slice_10(19) <= m_time_net_0(19);
m_time_slice_11(20) <= m_time_net_0(20);
m_time_slice_12(21) <= m_time_net_0(21);
m_time_slice_13(22) <= m_time_net_0(22);
m_time_slice_14(23) <= m_time_net_0(23);
m_time_slice_15(24) <= m_time_net_0(24);
m_time_slice_16(2) <= m_time_net_0(2);
m_time_slice_17(3) <= m_time_net_0(3);
m_time_slice_18(4) <= m_time_net_0(4);
m_time_slice_19(5) <= m_time_net_0(5);
m_time_slice_20(6) <= m_time_net_0(6);
m_time_slice_21(7) <= m_time_net_0(7);
m_time_slice_22(8) <= m_time_net_0(8);
m_time_slice_23(9) <= m_time_net_0(9);
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- CLKINT_0
CLKINT_0 : CLKINT
port map(
-- Inputs
A => CLK,
-- Outputs
Y => CLKINT_0_Y
);
-- CLKINT_1
CLKINT_1 : CLKINT
port map(
-- Inputs
A => PWRONRESET,
-- Outputs
Y => CLKINT_1_Y
);
-- CUTTER_PWM_inst_0
CUTTER_PWM_inst_0 : CUTTER_PWM
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset => OR2_0_Y,
ena => LED2_net_0,
duty_wrt => VCC_net,
duty => WOLF_CONTROLLER_cutter_pwm_duty,
-- Outputs
pwm_out => CUTTER_net_0
);
-- FPGA_UART - Actel:DirectCore:COREUART:5.6.102
FPGA_UART : CU_TOP_FPGA_UART_COREUART
generic map(
BAUD_VAL_FRCTN_EN => ( 1 ),
FAMILY => ( 15 ),
RX_FIFO => ( 0 ),
RX_LEGACY_MODE => ( 0 ),
TX_FIFO => ( 0 )
)
port map(
-- Inputs
BIT8 => VCC_net,
CLK => CLKINT_0_Y,
CSN => GND_net,
ODD_N_EVEN => VCC_net,
OEN => LED1_3,
PARITY_EN => GND_net,
RESET_N => RESET_N_IN_POST_INV0_0,
RX => FPGA_UART_RX,
WEN => LED1_2,
BAUD_VAL => WOLF_CONTROLLER_uart_baud_val,
DATA_IN => WOLF_CONTROLLER_uart_data_out,
BAUD_VAL_FRACTION => WOLF_CONTROLLER_uart_baud_val_frac,
-- Outputs
OVERFLOW => OPEN,
PARITY_ERR => OPEN,
RXRDY => LED1_0,
TX => FPGA_UART_TX_net_0,
TXRDY => FPGA_UART_TXRDY,
FRAMING_ERR => OPEN,
DATA_OUT => FPGA_UART_DATA_OUT
);
-- OR2_0
OR2_0 : OR2
port map(
-- Inputs
A => CLKINT_1_Y,
B => LED1_net_0,
-- Outputs
Y => OR2_0_Y
);
-- system_clock_inst_0
system_clock_inst_0 : system_clock
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset => OR2_0_Y,
-- Outputs
m_time => m_time_net_0
);
-- UART_reset_monitor_inst_0
UART_reset_monitor_inst_0 : UART_reset_monitor
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset_in => CLKINT_1_Y,
txrdy => FPGA_UART_TXRDY,
data_in => FPGA_UART_DATA_OUT,
-- Outputs
reset_out => LED1_net_0
);
-- WOLF_CONTROLLER_inst_0
WOLF_CONTROLLER_inst_0 : WOLF_CONTROLLER
port map(
-- Inputs
mclk => CLKINT_0_Y,
clk_1hz => LED2_1(25),
reset => OR2_0_Y,
uart_txrdy => FPGA_UART_TXRDY,
uart_rxrdy => LED1_0,
uart_data_in => FPGA_UART_DATA_OUT,
-- Outputs
cutter_en => LED2_net_0,
uart_wen => LED1_2,
uart_oen => LED1_3,
led1 => OPEN,
led2 => OPEN,
cutter_pwm_duty => WOLF_CONTROLLER_cutter_pwm_duty,
uart_data_out => WOLF_CONTROLLER_uart_data_out,
uart_baud_val => WOLF_CONTROLLER_uart_baud_val,
uart_baud_val_frac => WOLF_CONTROLLER_uart_baud_val_frac
);
end RTL;
|
mit
|
059912afeb516ae7a5f439501abb0dd2
| 0.424114 | 3.708845 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue146.vhd
| 5 | 986 |
package A_NG is
type A_NG_TYPE is record
debug : integer;
end record;
procedure PROC_B(B_ARG:inout A_NG_TYPE; B_VAL:out integer);
end A_NG;
package body A_NG is
procedure PROC_A(A_ARG:inout A_NG_TYPE) is
begin
A_ARG.debug := A_ARG.debug + 1;
end procedure;
procedure PROC_B(B_ARG:inout A_NG_TYPE; B_VAL:out integer) is
procedure PROC_C(C_VAL:out integer) is
begin
PROC_A(B_ARG);
C_VAL := B_ARG.debug;
end procedure;
begin
PROC_C(B_VAL);
end procedure;
end A_NG;
-------------------------------------------------------------------------------
entity issue146 is
end entity;
use work.a_ng.all;
architecture test of issue146 is
begin
process is
variable a_arg : a_ng_type := ( debug => 4 );
variable c_val : integer;
begin
proc_b(a_arg, c_val);
assert c_val = 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
8bccabb7c47eaf0525e0ea4dd6b4a7fe
| 0.522312 | 3.459649 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/blk_mem_gen_outputMem_ste/example_design/blk_mem_gen_outputMem_top.vhd
| 1 | 5,018 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_outputMem_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END blk_mem_gen_outputMem_top;
ARCHITECTURE xilinx OF blk_mem_gen_outputMem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_outputMem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : blk_mem_gen_outputMem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
gpl-2.0
|
a9a240eb452415dc4878608d97229ef6
| 0.561578 | 4.60367 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/a_clk-rtl-a.vhd
| 1 | 32,493 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of a_clk
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-a.vhd,v 1.5 2006/07/05 10:01:22 wig Exp $
-- $Date: 2006/07/05 10:01:22 $
-- $Log: a_clk-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:22 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of a_clk
--
architecture rtl of a_clk is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component a_fsm
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
clk : in std_ulogic;
d9_core_di : in std_ulogic_vector(1 downto 0); -- d9io
d9_core_en : in std_ulogic_vector(1 downto 0); -- d9io
d9_core_pu : in std_ulogic_vector(1 downto 0); -- d9io
data_core_do : out std_ulogic_vector(1 downto 0); -- d9io
data_core_i33 : in std_ulogic_vector(7 downto 0); -- io data
data_core_i34 : in std_ulogic_vector(7 downto 0); -- io data
data_core_o35 : out std_ulogic_vector(7 downto 0); -- io data
data_core_o36 : out std_ulogic_vector(7 downto 0); -- io data
data_i1 : in std_ulogic_vector(7 downto 0); -- io data
data_o1 : out std_ulogic_vector(7 downto 0); -- io data
di : in std_ulogic_vector(7 downto 0); -- io data
di2 : in std_ulogic_vector(8 downto 0); -- io data
disp2_en : in std_ulogic_vector(7 downto 0); -- io data
disp_ls_port : out std_ulogic; -- io_enable
disp_ms_port : out std_ulogic; -- io_enable
iosel_bus : out std_ulogic_vector(7 downto 0); -- IO_SelectIO_SelectIO_SelectIO_SelectIO_SelectIO_SelectIO_SelectIO_Select
iosel_bus_disp : out std_ulogic; -- IO_Select
iosel_bus_ls_hr : out std_ulogic; -- IO_Select
iosel_bus_ls_min : out std_ulogic; -- IO_Select
iosel_bus_ms_hr : out std_ulogic; -- IO_Select
iosel_bus_ms_min : out std_ulogic; -- IO_Select
iosel_bus_nosel : out std_ulogic; -- IO_Select
iosel_bus_port : out std_ulogic_vector(7 downto 0); -- io data
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component ios_e
-- No Generated Generics
port (
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end component;
-- ---------
component pad_pads_e
-- No Generated Generics
port (
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end component;
-- ---------
component testctrl_e
-- No Generated Generics
port (
-- Generated Port for Entity testctrl_e
nand_dir : out std_ulogic; -- Direction
nand_en : out std_ulogic -- Enable
-- End of Generated Port for Entity testctrl_e
);
end component;
-- ---------
component alreg
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4
-- No Generated Generics
port (
-- Generated Port for Entity count4
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad
-- No Generated Generics
port (
-- Generated Port for Entity keypad
columns : in std_ulogic_vector(2 downto 0);
rows : out std_ulogic_vector(3 downto 0) -- Keypad Output
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
rows : in std_ulogic_vector(3 downto 0); -- Keypad Output
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen
-- No Generated Generics
port (
-- Generated Port for Entity timegen
one_minute : out std_ulogic;
one_second : out std_ulogic;
stopwatch : in std_ulogic -- Driven by reset
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Generated Signal List
--
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_di : std_ulogic_vector(1 downto 0);
signal d9_do : std_ulogic_vector(1 downto 0);
signal d9_en : std_ulogic_vector(1 downto 0);
signal d9_pu : std_ulogic_vector(1 downto 0);
signal data_i1 : std_ulogic_vector(7 downto 0);
signal data_i33 : std_ulogic_vector(7 downto 0);
signal data_i34 : std_ulogic_vector(7 downto 0);
signal data_o1 : std_ulogic_vector(7 downto 0);
signal data_o35 : std_ulogic_vector(7 downto 0);
signal data_o36 : std_ulogic_vector(7 downto 0);
signal di2 : std_ulogic_vector(8 downto 0);
signal disp2 : std_ulogic_vector(7 downto 0);
signal disp2_en : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic;
signal s_int_display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic;
signal s_int_display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic;
signal iosel_1 : std_ulogic;
signal iosel_2 : std_ulogic;
signal iosel_3 : std_ulogic;
signal iosel_4 : std_ulogic;
signal iosel_5 : std_ulogic;
signal iosel_6 : std_ulogic;
signal iosel_7 : std_ulogic;
signal iosel_bus : std_ulogic_vector(7 downto 0);
signal iosel_disp : std_ulogic;
signal iosel_ls_hr : std_ulogic;
signal iosel_ls_min : std_ulogic;
signal iosel_ms_hr : std_ulogic;
signal iosel_ms_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_nosel : std_ulogic;
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal nand_dir : std_ulogic;
-- __I_OUT_OPEN signal nand_en : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal pad_di_1 : std_ulogic;
signal pad_di_12 : std_ulogic;
signal pad_di_13 : std_ulogic;
signal pad_di_14 : std_ulogic;
signal pad_di_15 : std_ulogic;
signal pad_di_16 : std_ulogic;
signal pad_di_17 : std_ulogic;
signal pad_di_18 : std_ulogic;
signal pad_di_31 : std_ulogic;
signal pad_di_32 : std_ulogic;
signal pad_di_33 : std_ulogic;
signal pad_di_34 : std_ulogic;
signal pad_di_39 : std_ulogic;
signal pad_di_40 : std_ulogic;
signal pad_do_12 : std_ulogic;
signal pad_do_13 : std_ulogic;
signal pad_do_14 : std_ulogic;
signal pad_do_15 : std_ulogic;
signal pad_do_16 : std_ulogic;
signal pad_do_17 : std_ulogic;
signal pad_do_18 : std_ulogic;
signal pad_do_2 : std_ulogic;
signal pad_do_31 : std_ulogic;
signal pad_do_32 : std_ulogic;
signal pad_do_35 : std_ulogic;
signal pad_do_36 : std_ulogic;
signal pad_do_39 : std_ulogic;
signal pad_do_40 : std_ulogic;
signal pad_en_12 : std_ulogic;
signal pad_en_13 : std_ulogic;
signal pad_en_14 : std_ulogic;
signal pad_en_15 : std_ulogic;
signal pad_en_16 : std_ulogic;
signal pad_en_17 : std_ulogic;
signal pad_en_18 : std_ulogic;
signal pad_en_2 : std_ulogic;
signal pad_en_31 : std_ulogic;
signal pad_en_32 : std_ulogic;
signal pad_en_35 : std_ulogic;
signal pad_en_36 : std_ulogic;
signal pad_en_39 : std_ulogic;
signal pad_en_40 : std_ulogic;
signal pad_pu_31 : std_ulogic;
signal pad_pu_32 : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
display_ls_hr <= s_int_display_ls_hr; -- __I_O_BUS_PORT
display_ls_min <= s_int_display_ls_min; -- __I_O_BUS_PORT
display_ms_hr <= s_int_display_ms_hr; -- __I_O_BUS_PORT
display_ms_min <= s_int_display_ms_min; -- __I_O_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
clk => clk,
d9_core_di => d9_di, -- d9io
d9_core_en => d9_en, -- d9io
d9_core_pu => d9_pu, -- d9io
data_core_do => d9_do, -- d9io
data_core_i33 => data_i33, -- io data
data_core_i34 => data_i34, -- io data
data_core_o35 => data_o35, -- io data
data_core_o36 => data_o36, -- io data
data_i1 => data_i1, -- io data
data_o1 => data_o1, -- io data
di => disp2, -- io data
di2 => di2, -- io data
disp2_en => disp2_en, -- io data
disp_ls_port => display_ls_en, -- io_enable
disp_ms_port => display_ms_en, -- io_enable
iosel_bus(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(6) => iosel_6, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(7) => iosel_7, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus_disp => iosel_disp, -- IO_Select
iosel_bus_ls_hr => iosel_ls_hr, -- IO_Select
iosel_bus_ls_min => iosel_ls_min, -- IO_Select
iosel_bus_ms_hr => iosel_ms_hr, -- IO_Select
iosel_bus_ms_min => iosel_ms_min, -- IO_Select
iosel_bus_nosel => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_port => iosel_bus, -- io data
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset,
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for ios
ios: ios_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_6_gi => iosel_6, -- IO_Select
p_mix_iosel_7_gi => iosel_7, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_iosel_ms_min_gi => iosel_ms_min, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18, -- pad output enable
p_mix_pad_en_2_go => pad_en_2, -- pad output enable
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ios
-- Generated Instance Port Map for pad_pads
pad_pads: pad_pads_e
port map (
p_mix_pad_di_12_go => pad_di_12, -- data in from pad
p_mix_pad_di_13_go => pad_di_13, -- data in from pad
p_mix_pad_di_14_go => pad_di_14, -- data in from pad
p_mix_pad_di_15_go => pad_di_15, -- data in from pad
p_mix_pad_di_16_go => pad_di_16, -- data in from pad
p_mix_pad_di_17_go => pad_di_17, -- data in from pad
p_mix_pad_di_18_go => pad_di_18, -- data in from pad
p_mix_pad_di_1_go => pad_di_1, -- data in from pad
p_mix_pad_di_31_go => pad_di_31, -- data in from pad
p_mix_pad_di_32_go => pad_di_32, -- data in from pad
p_mix_pad_di_33_go => pad_di_33, -- data in from pad
p_mix_pad_di_34_go => pad_di_34, -- data in from pad
p_mix_pad_di_39_go => pad_di_39, -- data in from pad
p_mix_pad_di_40_go => pad_di_40, -- data in from pad
p_mix_pad_do_12_gi => pad_do_12, -- data out to pad
p_mix_pad_do_13_gi => pad_do_13, -- data out to pad
p_mix_pad_do_14_gi => pad_do_14, -- data out to pad
p_mix_pad_do_15_gi => pad_do_15, -- data out to pad
p_mix_pad_do_16_gi => pad_do_16, -- data out to pad
p_mix_pad_do_17_gi => pad_do_17, -- data out to pad
p_mix_pad_do_18_gi => pad_do_18, -- data out to pad
p_mix_pad_do_2_gi => pad_do_2, -- data out to pad
p_mix_pad_do_31_gi => pad_do_31, -- data out to pad
p_mix_pad_do_32_gi => pad_do_32, -- data out to pad
p_mix_pad_do_35_gi => pad_do_35, -- data out to pad
p_mix_pad_do_36_gi => pad_do_36, -- data out to pad
p_mix_pad_do_39_gi => pad_do_39, -- data out to pad
p_mix_pad_do_40_gi => pad_do_40, -- data out to pad
p_mix_pad_en_12_gi => pad_en_12, -- pad output enable
p_mix_pad_en_13_gi => pad_en_13, -- pad output enable
p_mix_pad_en_14_gi => pad_en_14, -- pad output enable
p_mix_pad_en_15_gi => pad_en_15, -- pad output enable
p_mix_pad_en_16_gi => pad_en_16, -- pad output enable
p_mix_pad_en_17_gi => pad_en_17, -- pad output enable
p_mix_pad_en_18_gi => pad_en_18, -- pad output enable
p_mix_pad_en_2_gi => pad_en_2, -- pad output enable
p_mix_pad_en_31_gi => pad_en_31, -- pad output enable
p_mix_pad_en_32_gi => pad_en_32, -- pad output enable
p_mix_pad_en_35_gi => pad_en_35, -- pad output enable
p_mix_pad_en_36_gi => pad_en_36, -- pad output enable
p_mix_pad_en_39_gi => pad_en_39, -- pad output enable
p_mix_pad_en_40_gi => pad_en_40, -- pad output enable
p_mix_pad_pu_31_gi => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_gi => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_pads
-- Generated Instance Port Map for test_ctrl
test_ctrl: testctrl_e
port map (
nand_dir => nand_dir, -- Direction (X17)
nand_en => open -- Enable (X17) -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for test_ctrl
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0 -- Display storage buffer 0 ls_min
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1 -- Display storage buffer 1 ms_min
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2 -- Display storage buffer 2 ls_hr
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3 -- Display storage buffer 3 ms_hr
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_display_ls_hr_go => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_go => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_hr_go => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_go => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_sound_alarm_go => sound_alarm,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
columns => columns,
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
one_minute => one_minute,
one_second => one_sec_pulse,
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3256f1f1a5c613bcf2aec39f54fcb3b2
| 0.633552 | 2.388664 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_adapter_pkg.vhd
| 1 | 16,510 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_adapter_pkg.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-05
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
package xd_adapter_pkg is
type int_vector is array (natural range <>) of integer;
CONSTANT TFF : time := 100 ps;
constant SW_LENGTH_WIDTH : integer := 16;
constant AP_ARG_MEM_MAP_TYPE : integer := 0;
constant AP_ARG_STREAM_TYPE : integer := 1;
constant FORMAT_TYPE_NONE : integer := 0;
constant FORMAT_TYPE_RESHAPE_BLOCK : integer := 1;
constant FORMAT_TYPE_RESHAPE_CYCLIC : integer := 2;
constant FORMAT_TYPE_RESHAPE_COMPLETE : integer := 3;
constant FORMAT_TYPE_PARTITION_BLOCK : integer := 4;
constant FORMAT_TYPE_PARTITION_CYCLIC : integer := 5;
constant FORMAT_TYPE_PARTITION_COMPLETE : integer := 6;
function and_reduce(A : std_logic_vector) return std_logic;
function or_reduce(A : std_logic_vector) return std_logic;
function log2(x : natural) return integer;
function max(A : integer; B : integer) return integer;
function min_size(A : integer; B : integer) return integer;
function div_round_up(t : integer; Tclk : integer) return integer;
function int2lv (A : integer; width : integer := 32) return std_logic_vector;
function lv2int(A : std_logic_vector) return integer;
function int2l (A : integer) return std_logic;
function ext_lv (value : std_logic_vector; width : natural := 32) return std_logic_vector;
function get_int_element(A : std_logic_vector; index : natural) return integer;
function get_int_vector(A : std_logic_vector; x : natural; y : natural) return int_vector;
-- These next two functions are used to calculate the LSB and MSB for
-- "compacted" buses, e.g., output scalar data bus
function get_compact_LSB(A : std_logic_vector; index : natural) return integer;
function get_compact_MSB(A : std_logic_vector; index : natural) return integer;
function get_compact_LSB_IO(A : std_logic_vector; index : natural) return integer;
function get_compact_MSB_IO(A : std_logic_vector; index : natural) return integer;
function calc_fifo_depth(x : integer) return integer;
function bin2gray(bin : std_logic_vector) return std_logic_vector;
function bin2gray(bin : integer; N : natural) return std_logic_vector;
function gray2bin(gray : std_logic_vector) return std_logic_vector;
function gray_inc(gray : std_logic_vector; k : integer := 1) return std_logic_vector;
function calc_gray_width(N : integer) return integer;
FUNCTION bin2gray_fifo (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector;
FUNCTION gray2bin_fifo (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector;
FUNCTION if_then_else (
condition : integer;
true_case : integer;
false_case : integer)
RETURN integer;
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer;
end xd_adapter_pkg;
package body xd_adapter_pkg is
function and_reduce (A : std_logic_vector) return std_logic is
variable aux : std_logic := '1';
begin
for i in A'range loop
aux := aux and A(i);
end loop;
return aux;
end function and_reduce;
function or_reduce (A : std_logic_vector) return std_logic is
variable aux : std_logic := '0';
begin
for i in A'range loop
aux := aux or A(i);
end loop;
return aux;
end function or_reduce;
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if (x = 0) then
return 0;
else
while (x > (2**i)) loop
i := i+1;
end loop;
return i;
end if;
end function log2;
function max(A : integer; B : integer) return integer is
begin
if(A > B) then
return A;
else
return B;
end if;
end function max;
function min_size(A : integer; B : integer) return integer is
begin
if(A < B) then
return A;
else
return B;
end if;
end function min_size;
function div_round_up(t : integer; Tclk : integer) return integer is
begin
-- integer division give the integer part of the results (no rounding). To
-- obtain round up (excess), add to dividend, the divisor minus one.
return (t + Tclk-1) / Tclk;
end function div_round_up;
function int2lv (A : integer; width : integer := 32) return std_logic_vector is
variable value : std_logic_vector(width-1 downto 0);
begin
value := std_logic_vector(to_signed(A, width));
return value;
end function int2lv;
function lv2int(A : std_logic_vector) return integer is
variable value : integer;
begin
value := to_integer(signed(A));
return value;
end function lv2int;
function int2l (A : integer) return std_logic is
variable value : std_logic;
begin
if(A = 0) then
value := '0';
else
value := '1';
end if;
return value;
end function int2l;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : integer;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF condition=0 THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function ext_lv (value : std_logic_vector; width : natural := 32)
return std_logic_vector is
constant N : integer := value'length;
variable ret : std_logic_vector(width-1 downto 0);
begin
ret := (others => '0');
ret(N-1 downto 0) := value;
return ret;
end function ext_lv;
function get_int_element(A : std_logic_vector; index : natural)
return integer is
constant N : integer := A'length;
alias A_dw : std_logic_vector(N-1 downto 0) is A;
variable element : std_logic_vector(31 downto 0);
begin
element := A_dw(32*(index+1)-1 downto 32*index);
return to_integer(signed(element));
end function get_int_element;
function get_int_vector(A : std_logic_vector; x : natural; y : natural)
return int_vector is
constant N : integer := A'length;
alias A_dw : std_logic_vector(N-1 downto 0) is A;
variable element : std_logic_vector(31 downto 0);
constant first : integer := min_size(x, y);
constant last : integer := max(x, y);
constant N_elements : integer := last - first + 1;
variable ret_value : int_vector(N_elements-1 downto 0) := (others => 0);
begin
for i in first to last loop
ret_value(i-first) := get_int_element(A_dw, i);
end loop;
return ret_value;
end function get_int_vector;
function get_compact_LSB_IO(A : std_logic_vector; index : natural)
return integer is
constant N : integer := A'length;
alias A_dw : std_logic_vector(N-1 downto 0) is A;
variable element : std_logic_vector(31 downto 0);
variable acc_1 : integer := 256;
begin
for k in 8 to index-1 loop
element := A_dw(32*(k+1)-1 downto 32*k);
acc_1 := acc_1 + to_integer(signed(element));
end loop;
return acc_1;
end function get_compact_LSB_IO;
function get_compact_LSB(A : std_logic_vector; index : natural)
return integer is
constant N : integer := A'length;
alias A_dw : std_logic_vector(N-1 downto 0) is A;
variable element : std_logic_vector(31 downto 0);
variable acc : integer := 0;
begin
for k in 0 to index-1 loop
element := A_dw(32*(k+1)-1 downto 32*k);
acc := acc + to_integer(signed(element));
end loop;
return acc;
end function get_compact_LSB;
function get_compact_MSB_IO(A : std_logic_vector; index : natural)
return integer is
constant N : integer := A'length;
alias A_dw : std_logic_vector(N-1 downto 0) is A;
variable element : std_logic_vector(31 downto 0);
variable acc_1 : integer := 256;
begin
for k in 8 to index loop
element := A_dw(32*(k+1)-1 downto 32*k);
acc_1 := acc_1 + to_integer(signed(element));
end loop;
return acc_1-1;
end function get_compact_MSB_IO;
function get_compact_MSB(A : std_logic_vector; index : natural)
return integer is
constant N : integer := A'length;
alias A_dw : std_logic_vector(N-1 downto 0) is A;
variable element : std_logic_vector(31 downto 0);
variable acc : integer := 0;
begin
for k in 0 to index loop
element := A_dw(32*(k+1)-1 downto 32*k);
acc := acc + to_integer(signed(element));
end loop;
return acc-1;
end function get_compact_MSB;
---------------------------------------------------------------------
-- calculate the power inmediately above or equal to the provided depth and
-- substract one
function calc_fifo_depth(x : integer) return integer is
variable i : integer := 0;
begin
if (x = 0) then
return 0;
else
while (x > (2**i)) loop
i := i+1;
end loop;
return (2**i)-1;
end if;
end function calc_fifo_depth;
-- Functions to convert from gray code to bin codes and viceversa
function bin2gray(bin : std_logic_vector) return std_logic_vector is
constant N : integer := (bin'length);
alias bin_dw : std_logic_vector(N-1 downto 0) is bin;
variable gray : std_logic_vector(N-1 downto 0);
begin
gray(N-1) := bin_dw(N-1);
for i in 0 to N-2 loop
gray(i) := bin_dw(i) xor bin_dw(i+1);
end loop;
return gray;
end function bin2gray;
function bin2gray(bin : integer; N : natural) return std_logic_vector is
variable gray : std_logic_vector(N-1 downto 0);
begin
gray := bin2gray(std_logic_vector(to_signed(bin, N)));
return gray;
end function bin2gray;
function gray2bin(gray : std_logic_vector) return std_logic_vector is
constant N : integer := gray'length;
alias gray_dw : std_logic_vector(N-1 downto 0) is gray;
variable bin : std_logic_vector(N-1 downto 0);
begin
bin(N-1) := gray_dw(N-1);
for i in N-2 downto 0 loop
bin(i) := bin(i+1) xor gray(i);
end loop;
return bin;
end function gray2bin;
-----------------------------------------------------------------------------
-- FUNCTION : bin2gray
-----------------------------------------------------------------------------
-- This function receives a binary value, and returns the associated
-- graycoded value.
FUNCTION bin2gray_fifo (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := indata(I) XOR indata(I+1);
END LOOP;
RETURN tmp_value;
END bin2gray_fifo;
-----------------------------------------------------------------------------
-- FUNCTION : gray2bin
-----------------------------------------------------------------------------
-- This function receives a gray-coded value, and returns the associated
-- binary value.
FUNCTION gray2bin_fifo (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := XOR_REDUCE(indata(length-1 DOWNTO I));
END LOOP;
RETURN tmp_value;
END gray2bin_fifo;
function gray_inc(gray : std_logic_vector; k : integer := 1) return std_logic_vector is
constant N : integer := gray'length;
variable bin : unsigned(N-1 downto 0);
begin
bin := unsigned(gray2bin(gray));
bin := bin + k;
return bin2gray(std_logic_vector(bin));
end function gray_inc;
function calc_gray_width(N : integer) return integer is
variable bin_width : integer;
begin
bin_width := log2(N);
-- If number of elements is a power of 2, we need an additinal bit,
-- otherwise when full condition is asserted both gray pointer would be
-- equal. this is the same condition that shows-up for the empty condition.
if(N = 2**bin_width) then
bin_width := bin_width + 1;
end if;
return bin_width;
end function calc_gray_width;
end xd_adapter_pkg;
|
mit
|
a52a50c04f68192a90df138b4206b979
| 0.596426 | 3.9347 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare12.vhd
| 1 | 4,252 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare12.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare12 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
aleb : OUT STD_LOGIC
);
END lpm_compare12;
ARCHITECTURE SYN OF lpm_compare12 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aleb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
aleb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 16
)
PORT MAP (
dataa => dataa,
datab => datab,
aleb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "1"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "16"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
-- Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
-- Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
-- Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
-- Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
-- Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare12.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare12.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare12.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare12.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare12_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
18f5bc7f386fb5db0cf4d368c2f60111
| 0.655456 | 3.810036 | false | false | false | false |
blutsvente/MIX
|
test/results/bugver/constbug/vgca-struct-a.vhd
| 1 | 9,335 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of vgca
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca-struct-a.vhd,v 1.3 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: vgca-struct-a.vhd,v $
-- Revision 1.3 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of vgca
--
architecture struct of vgca is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component mic32_top --
-- No Generated Generics
port (
-- Generated Port for Entity mic32_top
eic_int_src_alt_i : in std_ulogic_vector(60 downto 1);
eic_int_src_i : in std_ulogic_vector(60 downto 1)
-- End of Generated Port for Entity mic32_top
);
end component;
-- ---------
component vgca_di --
-- No Generated Generics
port (
-- Generated Port for Entity vgca_di
fmdstatusm_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
fmdstatuss_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
lbdstatusm_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
lbdstatuss_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
line_stable_m_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
line_stable_s_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
pixel_stable_m_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
pixel_stable_s_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
vaqm_vsync_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
vaqs_vsync_irq_o : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity vgca_di
);
end component;
-- ---------
component vgca_dp --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_fe --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_ga --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_peri --
-- No Generated Generics
port (
-- Generated Port for Entity vgca_peri
cadc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
crt_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ddc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpio_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt1_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt2_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt3_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt4_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
i2c_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
i2s_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
irri_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nvmc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
rtc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi1_rx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi1_tx_irq_alt_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi1_tx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi2_rx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi2_tx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
uart1_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
uart2_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
wdt_irq_o : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity vgca_peri
);
end component;
-- ---------
component vgca_rc --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal eic_int_src : std_ulogic_vector(60 downto 1);
signal eic_int_src_alt : std_ulogic_vector(60 downto 1);
constant eic_int_src_c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant eic_int_src_c_1c : std_ulogic_vector(2 downto 0) := ( others => '0' );
constant eic_int_src_c_2c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant eic_int_src_c_3c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant eic_int_src_c_4c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_0 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_1 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_2 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_3 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_4 : std_ulogic_vector(2 downto 0) := ( others => '0' );
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
eic_int_src(1) <= eic_int_src_c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(10) <= eic_int_src_c_2c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(19) <= eic_int_src_c_3c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(44) <= eic_int_src_c_4c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(59 downto 57) <= eic_int_src_c_1c;
eic_int_src_alt(1) <= mix_const_0; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(10) <= mix_const_1; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(19) <= mix_const_2; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(44) <= mix_const_3; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(59 downto 57) <= mix_const_4;
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for i_mic32_top
i_mic32_top: mic32_top
port map (
eic_int_src_alt_i => eic_int_src_alt,
eic_int_src_i => eic_int_src -- Interrupt Controller (X10)
);
-- End of Generated Instance Port Map for i_mic32_top
-- Generated Instance Port Map for i_vgca_di
i_vgca_di: vgca_di
port map (
fmdstatusm_irq_o => eic_int_src(40), -- Interrupt Controller (X10)
fmdstatuss_irq_o => eic_int_src(43), -- Interrupt Controller (X10)
lbdstatusm_irq_o => eic_int_src(34), -- Interrupt Controller (X10)
lbdstatuss_irq_o => eic_int_src(37), -- Interrupt Controller (X10)
line_stable_m_irq_o => eic_int_src(2), -- Interrupt Controller (X10)
line_stable_s_irq_o => eic_int_src(3), -- Interrupt Controller (X10)
pixel_stable_m_irq_o => eic_int_src(46), -- Interrupt Controller (X10)
pixel_stable_s_irq_o => eic_int_src(47), -- Interrupt Controller (X10)
vaqm_vsync_irq_o => eic_int_src(17), -- Interrupt Controller (X10)
vaqs_vsync_irq_o => eic_int_src(18) -- Interrupt Controller (X10)
);
-- End of Generated Instance Port Map for i_vgca_di
-- Generated Instance Port Map for i_vgca_dp
i_vgca_dp: vgca_dp
;
-- End of Generated Instance Port Map for i_vgca_dp
-- Generated Instance Port Map for i_vgca_fe
i_vgca_fe: vgca_fe
;
-- End of Generated Instance Port Map for i_vgca_fe
-- Generated Instance Port Map for i_vgca_ga
i_vgca_ga: vgca_ga
;
-- End of Generated Instance Port Map for i_vgca_ga
-- Generated Instance Port Map for i_vgca_peri
i_vgca_peri: vgca_peri
port map (
cadc_irq_o => eic_int_src(30), -- Interrupt Controller (X10)
crt_irq_o => eic_int_src(54), -- Interrupt Controller (X10)
ddc_irq_o => eic_int_src(15), -- Interrupt Controller (X10)
gpio_irq_o => eic_int_src(26), -- Interrupt Controller (X10)
gpt1_irq_o => eic_int_src(48), -- Interrupt Controller (X10)
gpt2_irq_o => eic_int_src(27), -- Interrupt Controller (X10)
gpt3_irq_o => eic_int_src(28), -- Interrupt Controller (X10)
gpt4_irq_o => eic_int_src(29), -- Interrupt Controller (X10)
i2c_irq_o => eic_int_src(31), -- Interrupt Controller (X10)
i2s_irq_o => eic_int_src(16), -- Interrupt Controller (X10)
irri_irq_o => eic_int_src(51), -- Interrupt Controller (X10)
nvmc_irq_o => eic_int_src(14), -- Interrupt Controller (X10)
rtc_irq_o => eic_int_src(21), -- Interrupt Controller (X10)
ssi1_rx_irq_o => eic_int_src(22), -- Interrupt Controller (X10)
ssi1_tx_irq_alt_o => eic_int_src_alt(12),
ssi1_tx_irq_o => eic_int_src(12), -- Interrupt Controller (X10)
ssi2_rx_irq_o => eic_int_src(23), -- Interrupt Controller (X10)
ssi2_tx_irq_o => eic_int_src(13), -- Interrupt Controller (X10)
uart1_irq_o => eic_int_src(24), -- Interrupt Controller (X10)
uart2_irq_o => eic_int_src(25), -- Interrupt Controller (X10)
wdt_irq_o => eic_int_src(60) -- Interrupt Controller (X10)
);
-- End of Generated Instance Port Map for i_vgca_peri
-- Generated Instance Port Map for i_vgca_rc
i_vgca_rc: vgca_rc
;
-- End of Generated Instance Port Map for i_vgca_rc
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
7778ee534e86ebea9262ed72696e825e
| 0.630959 | 2.733529 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/RAM2_Visitor.vhd
| 2 | 1,763 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM2_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0);
---output
RAM2_Enable: out std_logic := '1';
RAM2_ReadEnable: out std_logic := '1';
RAM2_WriteEnable: out std_logic := '1;
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
end RAM2_Visitor;
architecture behavior of RAM2_Visitor is
signal tempRAM2_Enable :std_logic;
signal tempRAM2_ReadEnable:std_logic;
signal tempRAM2_WriteEnable:std_logic;
begin
process(EXandMEM_AluRes, DMemReadWrite, writeData)
begin
if DMemReadWrite = MEM_READ then
DMemData <= "ZZZZZZZZZZZZZZZZ";
DMemAddr <= EXandMEM_AluRes;
elsif DMemReadWrite = MEM_WRITE then
DMemData <= writeData;
DMemAddr <= EXandMEM_AluRes;
else
DMemData <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
RAM2_Enable <=tempRAM2_Enable;
RAM2_ReadEnable <= tempRAM2_ReadEnable;
RAM2_WriteEnable <= tempRAM2_WriteEnable;
process(clk, EXandMEM_AluRes, DMemReadWrite)
begin
if clk = '0' then
tempRAM2_Enable <= '0';
if DMemReadWrite = MEM_READ then
tempRAM2_ReadEnable <= '0';
tempRAM2_WriteEnable <= '1';
elsif DMemReadWrite = MEM_WRITE then
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '0';
else
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '1';
end if;
elsif clk = '1' then
tempRAM2_Enable <= '1';
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '1';
end if;
end process;
end behavior;
|
apache-2.0
|
2ba299cc40a8f6a29699ead8845e0aa2
| 0.676687 | 3.228938 | false | false | false | false |
mitchsm/nvc
|
test/regress/signal5.vhd
| 5 | 325 |
entity signal5 is
end entity;
architecture test of signal5 is
signal x, y : integer;
begin
update_y: y <= x + 4;
stim: process is
begin
x <= 1;
wait for 1 ns;
assert y = 5;
x <= 10;
wait on y;
assert y = 14;
wait;
end process;
end architecture;
|
gpl-3.0
|
3952e877f68f95ada42c7dfe0f982912
| 0.513846 | 3.611111 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare7.vhd
| 1 | 4,441 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare7.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare7 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare7;
ARCHITECTURE SYN OF lpm_compare7 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "000001010";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "10"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 10 0 0 9 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare7.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare7.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare7.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare7.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare7_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
63f0f5ed0d19ea10a9230b13ac7a73b6
| 0.655483 | 3.694676 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_e_e-rtl-a.vhd
| 1 | 17,412 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_ea_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
p_mix_tmi_sbist_fail_9_0_go : out std_ulogic_vector(9 downto 0);
video_i : in std_ulogic_vector(3 downto 0);
p_mix_cp_lcmd_6_6_gi : in std_ulogic;
p_mix_cp_lcmd_3_6_6_gi : in std_ulogic;
p_mix_cp_lcmd_2_6_6_gi : in std_ulogic;
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic;
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_tmi_sbist_fail_11_10_gi : in std_ulogic_vector(1 downto 0);
p_mix_widesig_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_widesig_r_0_gi : in std_ulogic;
p_mix_widesig_r_1_gi : in std_ulogic;
p_mix_widesig_r_2_gi : in std_ulogic;
p_mix_widesig_r_3_gi : in std_ulogic;
p_mix_widesig_r_4_gi : in std_ulogic;
p_mix_widesig_r_5_gi : in std_ulogic;
p_mix_widesig_r_6_gi : in std_ulogic;
p_mix_widesig_r_7_gi : in std_ulogic;
p_mix_widesig_r_8_gi : in std_ulogic;
p_mix_widesig_r_9_gi : in std_ulogic;
p_mix_widesig_r_10_gi : in std_ulogic;
p_mix_widesig_r_11_gi : in std_ulogic;
p_mix_widesig_r_12_gi : in std_ulogic;
p_mix_widesig_r_13_gi : in std_ulogic;
p_mix_widesig_r_14_gi : in std_ulogic;
p_mix_widesig_r_15_gi : in std_ulogic;
p_mix_widesig_r_16_gi : in std_ulogic;
p_mix_widesig_r_17_gi : in std_ulogic;
p_mix_widesig_r_18_gi : in std_ulogic;
p_mix_widesig_r_19_gi : in std_ulogic;
p_mix_widesig_r_20_gi : in std_ulogic;
p_mix_widesig_r_21_gi : in std_ulogic;
p_mix_widesig_r_22_gi : in std_ulogic;
p_mix_widesig_r_23_gi : in std_ulogic;
p_mix_widesig_r_24_gi : in std_ulogic;
p_mix_widesig_r_25_gi : in std_ulogic;
p_mix_widesig_r_26_gi : in std_ulogic;
p_mix_widesig_r_27_gi : in std_ulogic;
p_mix_widesig_r_28_gi : in std_ulogic;
p_mix_widesig_r_29_gi : in std_ulogic;
p_mix_widesig_r_30_gi : in std_ulogic;
p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
component inst_eb_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eb_e
p_mix_tmi_sbist_fail_12_10_go : out std_ulogic_vector(2 downto 0);
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_eb_e
);
end component;
-- ---------
component inst_ec_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ec_e
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic;
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ec_e
);
end component;
-- ---------
component inst_ed_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ed_e
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ed_e
);
end component;
-- ---------
component inst_ee_e
-- No Generated Generics
-- Generated Generics for Entity inst_ee_e
-- End of Generated Generics for Entity inst_ee_e
port (
-- Generated Port for Entity inst_ee_e
tmi_sbist_fail : in std_ulogic_vector(12 downto 0)
-- End of Generated Port for Entity inst_ee_e
);
end component;
-- ---------
component inst_ef_e
-- No Generated Generics
-- Generated Generics for Entity inst_ef_e
-- End of Generated Generics for Entity inst_ef_e
port (
-- Generated Port for Entity inst_ef_e
cp_lcmd : out std_ulogic_vector(6 downto 0); -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p : out std_ulogic_vector(6 downto 0); -- Signal name != port name
cp_lcmd_2 : out std_ulogic_vector(6 downto 0); -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
c_addr : out std_ulogic_vector(12 downto 0);
c_bus_in : out std_ulogic_vector(31 downto 0) -- CBUSinterface
-- End of Generated Port for Entity inst_ef_e
);
end component;
-- ---------
component inst_eg_e
-- No Generated Generics
-- Generated Generics for Entity inst_eg_e
-- End of Generated Generics for Entity inst_eg_e
port (
-- Generated Port for Entity inst_eg_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- cpui/finputs
-- End of Generated Port for Entity inst_eg_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0);
signal c_bus_in : std_ulogic_vector(31 downto 0);
signal cp_lcmd : std_ulogic_vector(6 downto 0);
signal cp_lcmd_2 : std_ulogic_vector(6 downto 0);
signal cp_lcmd_3 : std_ulogic_vector(6 downto 0);
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0);
signal unsplice_a1_no3 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_a : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_b : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0);
signal widemerge_a1 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_11 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_19 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_20 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_21 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_22 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_23 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_24 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_25 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_26 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_28 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_29 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_30 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal widesig_r_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
unsplice_a1_no3(125 downto 0) <= p_mix_unsplice_a1_no3_125_0_gi(125 downto 0); -- __I_I_SLICE_PORT
unsplice_a1_no3(127) <= p_mix_unsplice_a1_no3_127_127_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_a2_all128 <= p_mix_unsplice_a2_all128_127_0_gi; -- __I_I_BUS_PORT
unsplice_a3_up100(100 downto 0) <= p_mix_unsplice_a3_up100_100_0_gi(100 downto 0); -- __I_I_SLICE_PORT
unsplice_a4_mid100(99 downto 2) <= p_mix_unsplice_a4_mid100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_a5_midp100(99 downto 2) <= p_mix_unsplice_a5_midp100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_bad_a(1) <= p_mix_unsplice_bad_a_1_1_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_bad_b(1 downto 0) <= p_mix_unsplice_bad_b_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
widemerge_a1 <= p_mix_widemerge_a1_31_0_gi; -- __I_I_BUS_PORT
widesig <= widesig_i; -- __I_I_BUS_PORT
widesig_r_0 <= p_mix_widesig_r_0_gi; -- __I_I_BIT_PORT
widesig_r_1 <= p_mix_widesig_r_1_gi; -- __I_I_BIT_PORT
widesig_r_10 <= p_mix_widesig_r_10_gi; -- __I_I_BIT_PORT
widesig_r_11 <= p_mix_widesig_r_11_gi; -- __I_I_BIT_PORT
widesig_r_12 <= p_mix_widesig_r_12_gi; -- __I_I_BIT_PORT
widesig_r_13 <= p_mix_widesig_r_13_gi; -- __I_I_BIT_PORT
widesig_r_14 <= p_mix_widesig_r_14_gi; -- __I_I_BIT_PORT
widesig_r_15 <= p_mix_widesig_r_15_gi; -- __I_I_BIT_PORT
widesig_r_16 <= p_mix_widesig_r_16_gi; -- __I_I_BIT_PORT
widesig_r_17 <= p_mix_widesig_r_17_gi; -- __I_I_BIT_PORT
widesig_r_18 <= p_mix_widesig_r_18_gi; -- __I_I_BIT_PORT
widesig_r_19 <= p_mix_widesig_r_19_gi; -- __I_I_BIT_PORT
widesig_r_2 <= p_mix_widesig_r_2_gi; -- __I_I_BIT_PORT
widesig_r_20 <= p_mix_widesig_r_20_gi; -- __I_I_BIT_PORT
widesig_r_21 <= p_mix_widesig_r_21_gi; -- __I_I_BIT_PORT
widesig_r_22 <= p_mix_widesig_r_22_gi; -- __I_I_BIT_PORT
widesig_r_23 <= p_mix_widesig_r_23_gi; -- __I_I_BIT_PORT
widesig_r_24 <= p_mix_widesig_r_24_gi; -- __I_I_BIT_PORT
widesig_r_25 <= p_mix_widesig_r_25_gi; -- __I_I_BIT_PORT
widesig_r_26 <= p_mix_widesig_r_26_gi; -- __I_I_BIT_PORT
widesig_r_27 <= p_mix_widesig_r_27_gi; -- __I_I_BIT_PORT
widesig_r_28 <= p_mix_widesig_r_28_gi; -- __I_I_BIT_PORT
widesig_r_29 <= p_mix_widesig_r_29_gi; -- __I_I_BIT_PORT
widesig_r_3 <= p_mix_widesig_r_3_gi; -- __I_I_BIT_PORT
widesig_r_30 <= p_mix_widesig_r_30_gi; -- __I_I_BIT_PORT
widesig_r_4 <= p_mix_widesig_r_4_gi; -- __I_I_BIT_PORT
widesig_r_5 <= p_mix_widesig_r_5_gi; -- __I_I_BIT_PORT
widesig_r_6 <= p_mix_widesig_r_6_gi; -- __I_I_BIT_PORT
widesig_r_7 <= p_mix_widesig_r_7_gi; -- __I_I_BIT_PORT
widesig_r_8 <= p_mix_widesig_r_8_gi; -- __I_I_BIT_PORT
widesig_r_9 <= p_mix_widesig_r_9_gi; -- __I_I_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
p_mix_cp_lcmd_2_6_6_gi => cp_lcmd_2(6), -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
p_mix_cp_lcmd_3_6_6_gi => cp_lcmd_3(6), -- Signal name != port name
p_mix_cp_lcmd_6_6_gi => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
p_mix_tmi_sbist_fail_11_10_gi => tmi_sbist_fail(11 downto 10),
p_mix_tmi_sbist_fail_9_0_go => tmi_sbist_fail(9 downto 0),
p_mix_unsplice_a1_no3_125_0_gi => unsplice_a1_no3(125 downto 0), -- leaves 3 unconnected
p_mix_unsplice_a1_no3_127_127_gi => unsplice_a1_no3(127), -- leaves 3 unconnected
p_mix_unsplice_a2_all128_127_0_gi => unsplice_a2_all128, -- full 128 bit port
p_mix_unsplice_a3_up100_100_0_gi => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
p_mix_unsplice_a4_mid100_99_2_gi => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_a5_midp100_99_2_gi => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_bad_a_1_1_gi => unsplice_bad_a(1),
p_mix_unsplice_bad_b_1_0_gi => unsplice_bad_b(1 downto 0), -- # conflict
p_mix_v_select_2_2_gi => v_select(2), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
p_mix_v_select_5_5_gi => v_select(5), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
p_mix_widemerge_a1_31_0_gi => widemerge_a1,
p_mix_widesig_31_0_gi => widesig,
p_mix_widesig_r_0_gi => widesig_r_0,
p_mix_widesig_r_10_gi => widesig_r_10,
p_mix_widesig_r_11_gi => widesig_r_11,
p_mix_widesig_r_12_gi => widesig_r_12,
p_mix_widesig_r_13_gi => widesig_r_13,
p_mix_widesig_r_14_gi => widesig_r_14,
p_mix_widesig_r_15_gi => widesig_r_15,
p_mix_widesig_r_16_gi => widesig_r_16,
p_mix_widesig_r_17_gi => widesig_r_17,
p_mix_widesig_r_18_gi => widesig_r_18,
p_mix_widesig_r_19_gi => widesig_r_19,
p_mix_widesig_r_1_gi => widesig_r_1,
p_mix_widesig_r_20_gi => widesig_r_20,
p_mix_widesig_r_21_gi => widesig_r_21,
p_mix_widesig_r_22_gi => widesig_r_22,
p_mix_widesig_r_23_gi => widesig_r_23,
p_mix_widesig_r_24_gi => widesig_r_24,
p_mix_widesig_r_25_gi => widesig_r_25,
p_mix_widesig_r_26_gi => widesig_r_26,
p_mix_widesig_r_27_gi => widesig_r_27,
p_mix_widesig_r_28_gi => widesig_r_28,
p_mix_widesig_r_29_gi => widesig_r_29,
p_mix_widesig_r_2_gi => widesig_r_2,
p_mix_widesig_r_30_gi => widesig_r_30,
p_mix_widesig_r_3_gi => widesig_r_3,
p_mix_widesig_r_4_gi => widesig_r_4,
p_mix_widesig_r_5_gi => widesig_r_5,
p_mix_widesig_r_6_gi => widesig_r_6,
p_mix_widesig_r_7_gi => widesig_r_7,
p_mix_widesig_r_8_gi => widesig_r_8,
p_mix_widesig_r_9_gi => widesig_r_9,
video_i => video_i
);
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
p_mix_tmi_sbist_fail_12_10_go => tmi_sbist_fail(12 downto 10)
);
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
p_mix_v_select_2_2_gi => v_select(2), -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
p_mix_v_select_5_5_gi => v_select(5) -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
);
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
port map (
p_mix_c_addr_12_0_gi => c_addr,
p_mix_c_bus_in_31_0_gi => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
port map (
tmi_sbist_fail => tmi_sbist_fail
);
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
cp_lcmd => cp_lcmd, -- GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_2 => cp_lcmd_2, -- Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface
cp_lcmd_p => cp_lcmd_3 -- Signal name != port name
);
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
d332128eed20c253199380bcdd193e72
| 0.645934 | 2.414979 | false | false | false | false |
mitchsm/nvc
|
test/regress/agg2.vhd
| 5 | 509 |
entity agg2 is
end entity;
architecture test of agg2 is
type int_array is array (integer range <>) of integer;
function all_ones(x : int_array) return int_array is
variable y : int_array(1 to x'length) := (others => 0);
begin
y := (others => 1);
return y;
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
begin
assert all_ones(x) = (1, 1, 1);
wait;
end process;
end architecture;
|
gpl-3.0
|
e0e559faa19f20eb6c7c1d988083f2fa
| 0.555992 | 3.635714 | false | false | false | false |
blutsvente/MIX
|
test/results/verilog/vhdl/ent_a-rtl-a.vhd
| 1 | 7,284 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.4 2005/10/13 09:09:43 wig Exp $
-- $Date: 2005/10/13 09:09:43 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.4 2005/10/13 09:09:43 wig
-- Added intermediate CONN sheet split
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa --
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_14 : out std_ulogic_vector(6 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic;
port_ab_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0);
sig_14 : in std_ulogic_vector(6 downto 0)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_ac_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0);
port_ae_5 : in std_ulogic_vector(3 downto 0);
port_ae_6 : in std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2);
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_14 : std_ulogic_vector(6 downto 0);
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13, -- Create internal signal name
sig_14 => sig_14 -- Multiline comment 1
-- Multiline comment 2
-- Multiline comment 3
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13, -- Create internal signal name
sig_14 => sig_14 -- Mulitline comment 1
-- Multiline comment 2
-- Multiline comment 3
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
9b55767527eea6a834e3ffea89afc551
| 0.620538 | 2.830937 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/CoreUART.vhd
| 1 | 21,685 |
-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CU_TOP_FPGA_UART_COREUART/ CoreUARTapb UART core
--
--
-- Revision Information:
-- Date Description
-- Jun09 Revision 4.1
-- Aug10 Revision 4.2
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR Date Who Description
-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
-- sys clk (not baud clock). See note below.
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
use work.CU_TOP_FPGA_UART_coreuart_pkg.all;
ENTITY CU_TOP_FPGA_UART_COREUART IS
GENERIC (
FAMILY : INTEGER := 15; -- DEVICE FAMILY
-- TX PARAMETERS
TX_FIFO : INTEGER := 0; -- 0=WITHOUT TX FIFO, 1=WITH TX FIFO
-- RX PARAMETERS
RX_FIFO : INTEGER := 0; -- 0=WITHOUT RX FIFO, 1=WITH RX FIFO
RX_LEGACY_MODE : INTEGER := 0;
--BAUD FRACTION PARAMETER
BAUD_VAL_FRCTN_EN : INTEGER := 0 -- 0=DISABLE BAUD FRACTION, 1=ENABLE BAUD FRACTION
);
PORT (
RESET_N : IN STD_LOGIC;
CLK : IN STD_LOGIC;
WEN : IN STD_LOGIC;
OEN : IN STD_LOGIC;
CSN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RX : IN STD_LOGIC;
BAUD_VAL : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
BIT8 : IN STD_LOGIC; -- IF SET TO ONE 8 DATA BITS OTHERWISE 7 DATA BITS
PARITY_EN : IN STD_LOGIC; -- IF SET TO ONE PARITY IS ENABLED OTHERWISE DISABLED
ODD_N_EVEN : IN STD_LOGIC; -- IF SET TO ONE ODD PARITY OTHERWISE EVEN PARITY
BAUD_VAL_FRACTION : IN STD_LOGIC_VECTOR(2 DOWNTO 0); --USED TO ADD EXTRA PRECISION TO BAUD VALUE WHEN BAUD_VAL_FRCTN_EN = 1
PARITY_ERR : OUT STD_LOGIC; -- PARITY ERROR INDICATOR ON RECIEVED DATA
OVERFLOW : OUT STD_LOGIC; -- RECEIVER OVERFLOW
TXRDY : OUT STD_LOGIC; -- TRANSMIT READY FOR ANOTHER BYTE
RXRDY : OUT STD_LOGIC; -- RECEIVER HAS A BYTE READY
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
TX : OUT STD_LOGIC;
FRAMING_ERR : OUT STD_LOGIC);
END ENTITY CU_TOP_FPGA_UART_COREUART;
ARCHITECTURE translated OF CU_TOP_FPGA_UART_COREUART IS
-- State name constant definitions
CONSTANT S0 : std_logic_vector(1 DOWNTO 0) := "00";
CONSTANT S1 : std_logic_vector(1 DOWNTO 0) := "01";
CONSTANT S2 : std_logic_vector(1 DOWNTO 0) := "10";
CONSTANT S3 : std_logic_vector(1 DOWNTO 0) := "11";
-- Sync/Async Mode Select
CONSTANT SYNC_RESET : INTEGER := SYNC_MODE_SEL(FAMILY);
-- Configuration bits
-- Status bits
SIGNAL overflow_legacy : std_logic;
SIGNAL receive_full : std_logic;
SIGNAL fifo_write_rx : std_logic;
SIGNAL fifo_write : std_logic;
SIGNAL xmit_pulse : std_logic; -- transmit pulse
SIGNAL baud_clock : std_logic; -- 8x baud clock pulse
SIGNAL rst_tx_empty : std_logic; -- reset transmit empty
SIGNAL tx_hold_reg : std_logic_vector(7 DOWNTO 0); -- transmit byte hold register
SIGNAL tx_dout_reg : std_logic_vector(7 DOWNTO 0); -- transmit byte hold register
SIGNAL rx_dout : std_logic_vector(7 DOWNTO 0); -- receive data out
SIGNAL read_rx_byte : std_logic; -- read rx byte register
SIGNAL rx_dout_reg : std_logic_vector(7 DOWNTO 0); -- receive data out
SIGNAL rx_byte : std_logic_vector(7 DOWNTO 0); -- receive byte register
SIGNAL rx_byte_in : std_logic_vector(7 DOWNTO 0); -- receive byte register
SIGNAL fifo_empty_tx : std_logic;
SIGNAL fifo_empty_rx : std_logic;
SIGNAL fifo_read_rx : std_logic;
SIGNAL fifo_write_tx : std_logic;
SIGNAL fifo_read_tx : std_logic;
SIGNAL fifo_full_tx : std_logic;
SIGNAL fifo_full_rx : std_logic;
SIGNAL clear_parity : std_logic;
SIGNAL clear_parity_en : std_logic;
SIGNAL clear_parity_reg0 : std_logic;
SIGNAL clear_parity_reg : std_logic;
SIGNAL data_en : std_logic;
SIGNAL stop_strobe : std_logic;
SIGNAL clear_framing_error : std_logic;
-- AS: added framing error self-clear mechanism (RX FIFO mode)
SIGNAL clear_framing_error_en : std_logic;
SIGNAL clear_framing_error_reg0 : std_logic;
SIGNAL clear_framing_error_reg : std_logic;
signal rx_idle : std_logic; -- AS: Added this signal for proper framing_error sync
SIGNAL framing_err_i : std_logic; -- AS: Internal framing error, for reading
-- AS: Added changed overflow operation (new signals required - see below)
SIGNAL overflow_reg : std_logic;
SIGNAL clear_overflow : std_logic;
-- ----------------------------------------------------------------------------
-- cpu reads from UART registers
-- ----------------------------------------------------------------------------
SIGNAL temp_xhdl7 : std_logic;
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl11 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl13 : std_logic;
SIGNAL temp_xhdl14 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl17 : std_logic;
SIGNAL parity_err_xhdl1 : std_logic;
SIGNAL overflow_xhdl2 : std_logic;
SIGNAL txrdy_xhdl3 : std_logic;
SIGNAL rxrdy_xhdl4 : std_logic;
SIGNAL data_out_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_xhdl6 : std_logic;
SIGNAL rx_dout_reg_empty : std_logic;
SIGNAL rx_state : std_logic_vector(1 DOWNTO 0);
SIGNAL next_rx_state : std_logic_vector(1 DOWNTO 0);
SIGNAL aresetn : std_logic;
SIGNAL sresetn : std_logic;
COMPONENT CU_TOP_FPGA_UART_Rx_async
GENERIC (
-- RX Parameters
RX_FIFO : integer := 0; -- 0=without rx fifo
SYNC_RESET : integer := 0);
PORT (
clk : IN std_logic;
baud_clock : IN std_logic;
reset_n : IN std_logic;
bit8 : IN std_logic;
parity_en : IN std_logic;
odd_n_even : IN std_logic;
read_rx_byte : IN std_logic;
clear_parity : IN std_logic;
clear_framing_error : IN std_logic;
rx : IN std_logic;
overflow : OUT std_logic;
parity_err : OUT std_logic;
framing_error : OUT std_logic;
rx_idle_out : OUT std_logic; -- AS: added this signal to sync framing error properly
stop_strobe : OUT std_logic;
clear_parity_en : OUT std_logic;
clear_framing_error_en : OUT std_logic;
receive_full : OUT std_logic;
rx_byte : OUT std_logic_vector(7 DOWNTO 0);
fifo_write : OUT std_logic
);
END COMPONENT;
COMPONENT CU_TOP_FPGA_UART_Tx_async
GENERIC (
-- TX Parameters
TX_FIFO : integer := 0; -- 0=without tx fifo
SYNC_RESET : integer := 0);
PORT (
clk : IN std_logic;
xmit_pulse : IN std_logic;
reset_n : IN std_logic;
rst_tx_empty : IN std_logic;
tx_hold_reg : IN std_logic_vector(7 DOWNTO 0);
tx_dout_reg : IN std_logic_vector(7 DOWNTO 0);
fifo_empty : IN std_logic;
fifo_full : IN std_logic;
bit8 : IN std_logic;
parity_en : IN std_logic;
odd_n_even : IN std_logic;
txrdy : OUT std_logic;
tx : OUT std_logic;
fifo_read_tx : OUT std_logic);
END COMPONENT;
COMPONENT CU_TOP_FPGA_UART_Clock_gen
GENERIC(
--BAUD FRACTION Parameter
BAUD_VAL_FRCTN_EN : integer := 0; -- 0=disable baud fraction
SYNC_RESET : integer := 0);
port (
clk : in std_logic; -- system clock
reset_n : in std_logic; -- active low async reset
baud_val : in std_logic_vector(12 downto 0); -- value loaded into cntr
BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0); -- handles fractional part of baud value
baud_clock : out std_logic; -- 8x baud clock pulse
xmit_pulse : out std_logic -- transmit pulse
);
END COMPONENT;
COMPONENT CU_TOP_FPGA_UART_fifo_256x8 IS
GENERIC ( SYNC_RESET : integer := 0);
PORT (
DO : OUT std_logic_vector(7 DOWNTO 0);
RCLOCK : IN std_logic;
WCLOCK : IN std_logic;
DI : IN std_logic_vector(7 DOWNTO 0);
WRB : IN std_logic;
RDB : IN std_logic;
RESET : IN std_logic;
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
BEGIN
aresetn <= '1' WHEN (SYNC_RESET=1) ELSE RESET_N;
sresetn <= RESET_N WHEN (SYNC_RESET=1) ELSE '1';
FRAMING_ERR <= framing_err_i;
PARITY_ERR <= parity_err_xhdl1;
OVERFLOW <= overflow_xhdl2;
TXRDY <= txrdy_xhdl3;
RXRDY <= rxrdy_xhdl4;
DATA_OUT <= data_out_xhdl5;
TX <= tx_xhdl6;
-- ---------------------------------------------------------
-- COMPONENT DECLARATIONS
-- ---------------------------------------------------------
-- ----------------------------------------------------------------------------
-- cpu writes to UART registers
-- ----------------------------------------------------------------------------
reg_write : PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
tx_hold_reg <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
fifo_write_tx <= '1';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (sresetn = '0') THEN
tx_hold_reg <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
fifo_write_tx <= '1';
ELSE
fifo_write_tx <= '1';
IF (csn = '0' AND WEn = '0') THEN
tx_hold_reg <= DATA_IN;
fifo_write_tx <= '0';
END IF;
END IF;
END IF;
END PROCESS reg_write;
temp_xhdl7 <= '1' WHEN (WEn = '0' AND csn = '0') ELSE '0';
rst_tx_empty <= temp_xhdl7 ;
PROCESS (rx_byte, rx_dout_reg, parity_err_xhdl1)
VARIABLE data_out_xhdl5_xhdl8 : std_logic_vector(7 DOWNTO 0);
BEGIN
IF (RX_FIFO = 2#0#) THEN
data_out_xhdl5_xhdl8 := rx_byte;
ELSE
IF (parity_err_xhdl1 = '1') THEN
data_out_xhdl5_xhdl8 := rx_byte;
ELSE
data_out_xhdl5_xhdl8 := rx_dout_reg;
END IF;
END IF;
data_out_xhdl5 <= data_out_xhdl5_xhdl8;
END PROCESS;
temp_xhdl10 <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';
temp_xhdl11 <= (temp_xhdl10) WHEN (RX_FIFO = 2#0#) ELSE NOT fifo_full_rx;
read_rx_byte <= temp_xhdl11 ;
temp_xhdl12 <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';
temp_xhdl13 <= clear_parity_reg WHEN RX_FIFO /= 0 ELSE (temp_xhdl12);
clear_parity <= temp_xhdl13 ;
temp_xhdl14 <= rx_byte WHEN (parity_err_xhdl1 = '0') ELSE "00000000";
rx_byte_in <= temp_xhdl14 ;
--clear_framing_error <= clear_framing_error_reg WHEN RX_FIFO /= 0 ELSE (temp_xhdl12);
clear_framing_error <= temp_xhdl12 WHEN (RX_FIFO = 0) ELSE '1' WHEN (temp_xhdl12 = '1') ELSE clear_framing_error_reg;
clear_overflow <= '1' WHEN (csn = '0' AND OEn = '0') ELSE '0';
RXRDY_LEGACY: IF (RX_LEGACY_MODE = 1) GENERATE
PROCESS (receive_full, rx_dout_reg_empty)
VARIABLE rxrdy_xhdl4_xhdl15 : std_logic;
BEGIN
IF (RX_FIFO = 2#0#) THEN
rxrdy_xhdl4_xhdl15 := receive_full;
ELSE
rxrdy_xhdl4_xhdl15 := NOT rx_dout_reg_empty;
END IF;
rxrdy_xhdl4 <= rxrdy_xhdl4_xhdl15;
END PROCESS;
END GENERATE;
-- AS, added 11/17/08
RXRDY_NEW: IF (RX_LEGACY_MODE = 0) GENERATE
PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
rxrdy_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (sresetn = '0') THEN
rxrdy_xhdl4 <= '0';
ELSE
IF (RX_FIFO = 0) THEN
IF (stop_strobe = '1' OR receive_full = '0') THEN
rxrdy_xhdl4 <= receive_full;
END IF;
ELSE
IF (stop_strobe = '1' OR rx_dout_reg_empty = '1' or (rx_dout_reg_empty = '0' and (rx_idle = '1' or RX_FIFO = 1))) THEN
rxrdy_xhdl4 <= NOT rx_dout_reg_empty;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
clear_parity_reg <= '0';
clear_parity_reg0 <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (sresetn = '0') THEN
clear_parity_reg <= '0';
clear_parity_reg0 <= '0';
ELSE
clear_parity_reg0 <= clear_parity_en;
clear_parity_reg <= clear_parity_reg0;
END IF;
END IF;
END PROCESS;
-- AS: added self-clearing framing error
PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
clear_framing_error_reg <= '0';
clear_framing_error_reg0 <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (sresetn = '0') THEN
clear_framing_error_reg <= '0';
clear_framing_error_reg0 <= '0';
ELSE
clear_framing_error_reg0 <= clear_framing_error_en;
clear_framing_error_reg <= clear_framing_error_reg0;
END IF;
END IF;
END PROCESS;
-- state machine to control reading from the rx fifo
PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
rx_state <= S0;
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (sresetn = '0') THEN
rx_state <= S0;
ELSE
rx_state <= next_rx_state;
END IF;
END IF;
END PROCESS;
PROCESS (rx_state, rx_dout_reg_empty, fifo_empty_rx)
BEGIN
next_rx_state <= rx_state;
fifo_read_rx <= '1';
data_en <= '0';
CASE rx_state IS
WHEN S0 => IF (rx_dout_reg_empty = '1' AND fifo_empty_rx = '0') THEN
next_rx_state <= S1;
fifo_read_rx <= '0';
END IF;
WHEN S1 => next_rx_state <= S2;
WHEN S2 => next_rx_state <= S3;
WHEN S3 => next_rx_state <= S0;
data_en <= '1';
WHEN others => next_rx_state <= rx_state;
END CASE;
END PROCESS;
PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
rx_dout_reg <= "00000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (sresetn = '0') THEN
rx_dout_reg <= "00000000";
ELSE
IF (data_en = '1') THEN
rx_dout_reg <= rx_dout;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
rx_dout_reg_empty <= '1';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (sresetn = '0') THEN
rx_dout_reg_empty <= '1';
ELSE
IF (data_en = '1') THEN
rx_dout_reg_empty <= '0';
ELSE
IF (csn = '0' AND OEn = '0') THEN
IF (RX_FIFO = 1) THEN
IF(parity_err_xhdl1 = '0') THEN
rx_dout_reg_empty <= '1';
END IF;
ELSE
rx_dout_reg_empty <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (CLK, aresetn)
BEGIN
IF (aresetn = '0') THEN
overflow_reg <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (sresetn = '0') THEN
overflow_reg <= '0';
ELSE
IF (fifo_write = '0' AND fifo_full_rx = '1') THEN
overflow_reg <= '1';
ELSIF (clear_overflow = '1') THEN
overflow_reg <= '0';
ELSE
overflow_reg <= overflow_reg;
END IF;
END IF;
END IF;
END PROCESS;
-- AS: Changed OVERFLOW condition
-- - We should not be assigning OVERFLOW to FIFO_FULL;
-- instead, we should be asserting OVERFLOW if a write is
-- requested while fifo_full_rx is high
temp_xhdl16 <= overflow_reg WHEN RX_FIFO /= 0 ELSE overflow_legacy;
overflow_xhdl2 <= temp_xhdl16 ;
temp_xhdl17 <= '1' WHEN (parity_err_xhdl1 = '1' or fifo_full_rx = '1') ELSE fifo_write;
fifo_write_rx <= temp_xhdl17 ;
make_CU_TOP_FPGA_UART_Clock_gen : CU_TOP_FPGA_UART_Clock_gen
GENERIC MAP (
BAUD_VAL_FRCTN_EN => BAUD_VAL_FRCTN_EN,
SYNC_RESET => SYNC_RESET)
PORT MAP (
clk => CLK,
reset_n => RESET_N,
baud_val => BAUD_VAL,
BAUD_VAL_FRACTION => BAUD_VAL_FRACTION,
baud_clock => baud_clock,
xmit_pulse => xmit_pulse);
make_TX : CU_TOP_FPGA_UART_Tx_async
GENERIC MAP (
TX_FIFO => TX_FIFO,
SYNC_RESET => SYNC_RESET)
PORT MAP (
clk => CLK,
xmit_pulse => xmit_pulse,
reset_n => RESET_N,
rst_tx_empty => rst_tx_empty,
tx_hold_reg => tx_hold_reg,
tx_dout_reg => tx_dout_reg,
fifo_empty => fifo_empty_tx,
fifo_full => fifo_full_tx,
bit8 => bit8,
parity_en => parity_en,
odd_n_even => odd_n_even,
txrdy => txrdy_xhdl3,
tx => tx_xhdl6,
fifo_read_tx => fifo_read_tx);
make_RX : CU_TOP_FPGA_UART_Rx_async
GENERIC MAP (
RX_FIFO => RX_FIFO,
SYNC_RESET => SYNC_RESET)
PORT MAP (
clk => CLK,
baud_clock => baud_clock,
reset_n => RESET_N,
bit8 => bit8,
parity_en => parity_en,
odd_n_even => odd_n_even,
read_rx_byte => read_rx_byte,
clear_parity => clear_parity,
rx => RX,
overflow => overflow_legacy,
parity_err => parity_err_xhdl1,
clear_parity_en => clear_parity_en,
receive_full => receive_full,
rx_byte => rx_byte,
fifo_write => fifo_write,
clear_framing_error => clear_framing_error,
clear_framing_error_en => clear_framing_error_en,
framing_error => framing_err_i,
rx_idle_out => rx_idle,
stop_strobe => stop_strobe);
UG06a:IF (TX_FIFO = 2#1#) GENERATE
tx_fifo_xhdl79 : CU_TOP_FPGA_UART_fifo_256x8
GENERIC MAP ( SYNC_RESET => SYNC_RESET)
PORT MAP (
DO => tx_dout_reg,
RCLOCK => clk,
WCLOCK => clk,
-- AS: FIXED SARno 12821
-- DI => data_in,
DI => tx_hold_reg,
WRB => fifo_write_tx,
RDB => fifo_read_tx,
RESET => reset_n,
FULL => fifo_full_tx,
EMPTY => fifo_empty_tx);
END GENERATE;
UG06b:IF (TX_FIFO = 2#0#) GENERATE
tx_dout_reg <= "00000000";
fifo_full_tx <='0';
fifo_empty_tx <='0';
END GENERATE;
UG07:IF (RX_FIFO = 2#1#) GENERATE
rx_fifo_xhdl80 : CU_TOP_FPGA_UART_fifo_256x8
GENERIC MAP ( SYNC_RESET => SYNC_RESET)
PORT MAP (
DO => rx_dout,
RCLOCK => clk,
WCLOCK => clk,
DI => rx_byte_in,
WRB => fifo_write_rx,
RDB => fifo_read_rx,
RESET => reset_n,
FULL => fifo_full_rx,
EMPTY => fifo_empty_rx);
END GENERATE;
UG07b:IF (RX_FIFO = 2#0#) GENERATE
rx_dout <= "00000000";
fifo_full_rx <='0';
fifo_empty_rx <='0';
END GENERATE;
END ARCHITECTURE translated;
|
mit
|
eedec16fc820336a6e52032026a1dc58
| 0.488125 | 3.743957 | false | false | false | false |
mitchsm/nvc
|
test/regress/record7.vhd
| 5 | 483 |
entity record7 is
end entity;
architecture test of record7 is
type rec is record
x, y : integer;
end record;
signal s : rec;
begin
process is
begin
assert s = (integer'left, integer'left);
s <= (1, 2);
wait for 1 ns;
assert s = (1, 2);
assert s.x = 1;
assert s.y = 2;
s.x <= 3;
s.y <= 4;
wait for 1 ns;
assert s = (3, 4);
wait;
end process;
end architecture;
|
gpl-3.0
|
1ffd57659bce24fc3bc39fdb08699754
| 0.488613 | 3.47482 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/async_fifo_dist_inst.vhd
| 1 | 32,559 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : async_fifo_dist_inst.vhd
-- Author : ghanash
-- Company : Xilinx, Inc.
-- Created : 2014-11-21
-- Last update:
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-11-21 1.0 ghanash Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
entity async_fifo_dist_inst is
generic (
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
DEPTH : integer := 31;
WIDTH : integer := 32);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_clk : in std_logic;
wr_rst : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic);
end async_fifo_dist_inst;
architecture rtl of async_fifo_dist_inst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
--constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH);
--constant ADDR_BITS : integer := log2(FIFO_DEPTH);
signal din_rdy_n : std_logic;
signal dout_vld_i : std_logic;
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal empty : std_logic;
signal full : std_logic;
signal almost_full :std_logic;
signal wr_ack :std_logic;
signal overflow :std_logic;
signal almost_empty :std_logic;
signal valid :std_logic;
signal underflow :std_logic;
signal data_count :std_logic_vector(4 downto 0);
signal rd_data_count :std_logic_vector(4 downto 0);
signal wr_data_count :std_logic_vector(4 downto 0);
signal prog_full :std_logic;
signal prog_empty :std_logic;
signal sbiterr :std_logic;
signal dbiterr :std_logic;
signal wr_rst_busy :std_logic;
signal rd_rst_busy :std_logic;
signal m_axi_awid :std_logic_vector(0 downto 0);
signal m_axi_awaddr :std_logic_vector(31 downto 0);
signal m_axi_awlen :std_logic_vector(7 downto 0);
signal m_axi_awsize :std_logic_vector(2 downto 0);
signal m_axi_awburst :std_logic_vector(1 downto 0);
signal m_axi_awlock :std_logic_vector(0 downto 0);
signal m_axi_awcache :std_logic_vector(3 downto 0);
signal m_axi_awprot :std_logic_vector(2 downto 0);
signal m_axi_awqos :std_logic_vector(3 downto 0);
signal m_axi_awregion :std_logic_vector(3 downto 0);
signal m_axi_awuser :std_logic_vector(0 downto 0);
signal m_axi_awvalid :std_logic;
signal m_axi_wid :std_logic_vector(0 downto 0);
signal m_axi_wdata :std_logic_vector(63 downto 0);
signal m_axi_wstrb :std_logic_vector(7 downto 0);
signal m_axi_wlast :std_logic;
signal m_axi_wuser :std_logic_vector(0 downto 0);
signal m_axi_wvalid :std_logic;
signal m_axi_bready :std_logic;
signal s_axi_awready :std_logic;
signal s_axi_wready :std_logic;
signal s_axi_bid :std_logic_vector(0 downto 0);
signal s_axi_bresp :std_logic_vector(1 downto 0);
signal s_axi_buser :std_logic_vector(0 downto 0);
signal m_axi_arid :std_logic_vector(0 downto 0);
signal m_axi_araddr :std_logic_vector(31 downto 0);
signal m_axi_arlen :std_logic_vector(7 downto 0);
signal m_axi_arsize :std_logic_vector(2 downto 0);
signal m_axi_arburst :std_logic_vector(1 downto 0);
signal m_axi_arlock :std_logic_vector(0 downto 0);
signal m_axi_arcache :std_logic_vector(3 downto 0);
signal m_axi_arprot :std_logic_vector(2 downto 0);
signal m_axi_arqos :std_logic_vector(3 downto 0);
signal m_axi_arregion :std_logic_vector(3 downto 0);
signal m_axi_aruser :std_logic_vector(0 downto 0);
signal m_axi_arvalid :std_logic;
signal m_axi_rready :std_logic;
signal s_axi_arready :std_logic;
signal s_axi_rid :std_logic_vector(0 downto 0);
signal s_axi_rdata :std_logic_vector(63 downto 0);
signal s_axi_rresp :std_logic_vector(1 downto 0);
signal s_axi_rlast :std_logic;
signal s_axi_ruser :std_logic_vector(0 downto 0);
signal m_axis_tvalid :std_logic;
signal m_axis_tdata :std_logic_vector(7 downto 0);
signal m_axis_tstrb :std_logic_vector(0 downto 0);
signal m_axis_tlast :std_logic;
signal m_axis_tkeep :std_logic_vector(0 downto 0);
signal m_axis_tid :std_logic_vector(0 downto 0);
signal m_axis_tdest :std_logic_vector(0 downto 0);
signal m_axis_tuser :std_logic_vector(3 downto 0);
signal s_axis_tready :std_logic;
signal axi_aw_data_count :std_logic_vector(4 downto 0);
signal axi_aw_wr_data_count :std_logic_vector(4 downto 0);
signal axi_aw_rd_data_count :std_logic_vector(4 downto 0);
signal axi_aw_sbiterr :std_logic;
signal axi_aw_dbiterr :std_logic;
signal axi_aw_overflow :std_logic;
signal axi_aw_underflow :std_logic;
signal axi_aw_prog_full :std_logic;
signal axi_aw_prog_empty :std_logic;
signal axi_w_data_count :std_logic_vector(10 downto 0);
signal axi_w_wr_data_count :std_logic_vector(10 downto 0);
signal axi_w_rd_data_count :std_logic_vector(10 downto 0);
signal axi_w_sbiterr :std_logic;
signal axi_w_dbiterr :std_logic;
signal axi_w_overflow :std_logic;
signal axi_w_underflow :std_logic;
signal axi_w_prog_full :std_logic;
signal axi_w_prog_empty :std_logic;
signal axi_b_data_count :std_logic_vector(4 downto 0);
signal axi_b_wr_data_count :std_logic_vector(4 downto 0);
signal axi_b_rd_data_count :std_logic_vector(4 downto 0);
signal axi_b_sbiterr :std_logic;
signal axi_b_dbiterr :std_logic;
signal axi_b_overflow :std_logic;
signal axi_b_underflow :std_logic;
signal axi_b_prog_full :std_logic;
signal axi_b_prog_empty :std_logic;
signal axi_ar_data_count :std_logic_vector(4 downto 0);
signal axi_ar_wr_data_count :std_logic_vector(4 downto 0);
signal axi_ar_rd_data_count :std_logic_vector(4 downto 0);
signal axi_ar_sbiterr :std_logic;
signal axi_ar_dbiterr :std_logic;
signal axi_ar_overflow :std_logic;
signal axi_ar_underflow :std_logic;
signal axi_ar_prog_full :std_logic;
signal axi_ar_prog_empty :std_logic;
signal axi_r_data_count :std_logic_vector(10 downto 0);
signal axi_r_wr_data_count :std_logic_vector(10 downto 0);
signal axi_r_rd_data_count :std_logic_vector(10 downto 0);
signal axi_r_sbiterr :std_logic;
signal axi_r_dbiterr :std_logic;
signal axi_r_overflow :std_logic;
signal axi_r_underflow :std_logic;
signal axi_r_prog_full :std_logic;
signal axi_r_prog_empty :std_logic;
signal axis_data_count :std_logic_vector(10 downto 0);
signal axis_wr_data_count :std_logic_vector(10 downto 0);
signal axis_rd_data_count :std_logic_vector(10 downto 0);
signal axis_sbiterr :std_logic;
signal axis_dbiterr :std_logic;
signal axis_overflow :std_logic;
signal axis_underflow :std_logic;
signal axis_prog_full :std_logic;
signal axis_prog_empty :std_logic;
begin
-- fifo_we <= din_vld and (not(full));
-- fifo_re <= (not(dout_vld_i) or (dout_vld_i and dout_rdy)) and (not(empty));
din_rdy <= not(full);
dout_vld <= dout_vld_i;
-- fifo_we <= din_vld and (not(full));
-- fifo_re <= dout_rdy and (not(empty));
--
--
--
-- process(wr_clk, wr_rst)
-- begin
-- if(wr_rst = '1') then
-- din_rdy <= '0';
-- elsif(wr_clk'event and wr_clk = '1') then
-- if(fifo_we = '1') then
-- dout_vld <= not(empty);
-- end if;
-- end if;
-- end process;
-- process(rd_clk, rd_rst)
-- begin
-- if(rd_rst = '1') then
-- dout_vld_i <= '0';
-- elsif(rd_clk'event and rd_clk = '1') then
-- if((not(dout_vld_i) or (dout_vld_i and dout_rdy)) = '1') then
dout_vld_i <= not(empty);
-- end if;
-- end if;
-- end process;
FIF_DMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 5,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 5,
C_RD_DEPTH => 32,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 5,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 5,
C_WR_DEPTH => 32,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 5,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => wr_clk,
wr_rst => wr_rst,
rd_clk => rd_clk,
rd_rst => rd_rst,
din => din,
wr_en => din_vld,
rd_en => dout_rdy,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
end rtl;
|
mit
|
260361c3a3ceff59303ea6310ef54911
| 0.492951 | 3.547118 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare3.vhd
| 1 | 4,424 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare3.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare3 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
aeb : OUT STD_LOGIC
);
END lpm_compare3;
ARCHITECTURE SYN OF lpm_compare3 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aeb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(5 DOWNTO 0) <= "110010";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
aeb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 6
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
aeb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "50"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
-- Retrieval info: USED_PORT: dataa 0 0 6 0 INPUT NODEFVAL "dataa[5..0]"
-- Retrieval info: CONNECT: @dataa 0 0 6 0 dataa 0 0 6 0
-- Retrieval info: CONNECT: @datab 0 0 6 0 50 0 0 6 0
-- Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
f4bfcfbc0df9806e27b847c62c4f7d29
| 0.654385 | 3.683597 | false | false | false | false |
blutsvente/MIX
|
test/results/macro/variant/inst_t_e-rtl-a.vhd
| 1 | 24,079 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 13:21:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Calculate -nodelta ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2007/03/05 13:22:43 wig Exp $
-- $Date: 2007/03/05 13:22:43 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/05 13:22:43 wig
-- Added testcase for selection of macros with ::variant switch
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
#
# Generated Constant Declarations
#
#
# Generated Components
#
component inst_3_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_3_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_3_e
);
end component;
# ---------
component inst_4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_4_e
);
end component;
# ---------
component inst_5_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_5_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_5_e
);
end component;
# ---------
component inst_a_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_a_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_a_e
);
end component;
# ---------
component inst_b_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_b_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_b_e
);
end component;
# ---------
component inst_k1_k2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_k1_k2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_k1_k2_e
);
end component;
# ---------
component inst_k1_k4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_k1_k4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_k1_k4_e
);
end component;
# ---------
component inst_k3_k2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_k3_k2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_k3_k2_e
);
end component;
# ---------
component inst_k3_k4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_k3_k4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_k3_k4_e
);
end component;
# ---------
component inst_ok_1_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_1_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_1_e
);
end component;
# ---------
component inst_ok_10_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_10_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_10_e
);
end component;
# ---------
component inst_ok_2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_2_e
);
end component;
# ---------
component inst_ok_3_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_3_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_3_e
);
end component;
# ---------
component inst_ok_4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_4_e
);
end component;
# ---------
component inst_ok_5_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_5_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_5_e
);
end component;
# ---------
component inst_ok_6_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_6_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_6_e
);
end component;
# ---------
component inst_ok_7_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_7_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_7_e
);
end component;
# ---------
component inst_ok_8_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_8_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_8_e
);
end component;
# ---------
component inst_ok_9_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_ok_9_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_ok_9_e
);
end component;
# ---------
component inst_shadow_1_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_1_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_1_e
);
end component;
# ---------
component inst_shadow_10_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_10_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_10_e
);
end component;
# ---------
component inst_shadow_2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_2_e
);
end component;
# ---------
component inst_shadow_3_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_3_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_3_e
);
end component;
# ---------
component inst_shadow_4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_4_e
);
end component;
# ---------
component inst_shadow_5_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_5_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_5_e
);
end component;
# ---------
component inst_shadow_6_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_6_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_6_e
);
end component;
# ---------
component inst_shadow_7_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_7_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_7_e
);
end component;
# ---------
component inst_shadow_8_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_8_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_8_e
);
end component;
# ---------
component inst_shadow_9_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_9_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_9_e
);
end component;
# ---------
component inst_shadow_a_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_a_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_a_e
);
end component;
# ---------
component inst_shadow_b_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_b_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_b_e
);
end component;
# ---------
component inst_shadow_k1_k2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_k1_k2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_k1_k2_e
);
end component;
# ---------
component inst_shadow_k1_k4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_k1_k4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_k1_k4_e
);
end component;
# ---------
component inst_shadow_k3_k2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_k3_k2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_k3_k2_e
);
end component;
# ---------
component inst_shadow_k3_k4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_k3_k4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_k3_k4_e
);
end component;
# ---------
component inst_shadow_ok_1_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_1_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_1_e
);
end component;
# ---------
component inst_shadow_ok_10_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_10_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_10_e
);
end component;
# ---------
component inst_shadow_ok_2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_2_e
);
end component;
# ---------
component inst_shadow_ok_3_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_3_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_3_e
);
end component;
# ---------
component inst_shadow_ok_4_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_4_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_4_e
);
end component;
# ---------
component inst_shadow_ok_5_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_5_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_5_e
);
end component;
# ---------
component inst_shadow_ok_6_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_6_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_6_e
);
end component;
# ---------
component inst_shadow_ok_7_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_7_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_7_e
);
end component;
# ---------
component inst_shadow_ok_8_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_8_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_8_e
);
end component;
# ---------
component inst_shadow_ok_9_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_ok_9_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_ok_9_e
);
end component;
# ---------
component inst_shadow_t_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_shadow_t_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_shadow_t_e
);
end component;
# ---------
#
# Generated Signal List
#
signal gensig_1 : std_ulogic_vector(7 downto 0);
signal gensig_10 : std_ulogic_vector(7 downto 0);
signal gensig_2 : std_ulogic_vector(7 downto 0);
signal gensig_3 : std_ulogic_vector(7 downto 0);
signal gensig_4 : std_ulogic_vector(7 downto 0);
signal gensig_5 : std_ulogic_vector(7 downto 0);
signal gensig_6 : std_ulogic_vector(7 downto 0);
signal gensig_7 : std_ulogic_vector(7 downto 0);
signal gensig_8 : std_ulogic_vector(7 downto 0);
signal gensig_9 : std_ulogic_vector(7 downto 0);
signal macro_sigc : std_ulogic_vector(3 downto 0);
#
# End of Generated Signal List
#
begin
--
-- Generated Concurrent Statements
--
#
# Generated Signal Assignments
#
#
# Generated Instances and Port Mappings
#
# Generated Instance Port Map for inst_3
inst_3: inst_3_e
;
# End of Generated Instance Port Map for inst_3
# Generated Instance Port Map for inst_4
inst_4: inst_4_e
;
# End of Generated Instance Port Map for inst_4
# Generated Instance Port Map for inst_5
inst_5: inst_5_e
;
# End of Generated Instance Port Map for inst_5
# Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9, -- Generated signals, connecting b to a
port_mac_b => macro_sigc, -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
);
# End of Generated Instance Port Map for inst_a
# Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9, -- Generated signals, connecting b to a
);
# End of Generated Instance Port Map for inst_b
# Generated Instance Port Map for inst_k1_k2
inst_k1_k2: inst_k1_k2_e
port map (
port1 => macro_sig1_k1_k2, -- Macro test 0 k1_k2
port2 => macro_sig2_k1_k2, -- Macro test 0 k1_k2
port3 => macro_sign_0, -- Macro test 0 k1_k2
port_mac => macro_sigc(0), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k2, -- Macro test 0 k1_k2
);
# End of Generated Instance Port Map for inst_k1_k2
# Generated Instance Port Map for inst_k1_k4
inst_k1_k4: inst_k1_k4_e
port map (
port1 => macro_sig1_k1_k4, -- Macro test 1 k1_k4
port2 => macro_sig2_k1_k4, -- Macro test 1 k1_k4
port3 => macro_sign_1, -- Macro test 1 k1_k4
port_mac => macro_sigc(1), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k4, -- Macro test 1 k1_k4
);
# End of Generated Instance Port Map for inst_k1_k4
# Generated Instance Port Map for inst_k3_k2
inst_k3_k2: inst_k3_k2_e
port map (
port1 => macro_sig1_k3_k2, -- Macro test 2 k3_k2
port2 => macro_sig2_k3_k2, -- Macro test 2 k3_k2
port3 => macro_sign_2, -- Macro test 2 k3_k2
port_mac => macro_sigc(2), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k2, -- Macro test 2 k3_k2
);
# End of Generated Instance Port Map for inst_k3_k2
# Generated Instance Port Map for inst_k3_k4
inst_k3_k4: inst_k3_k4_e
port map (
port1 => macro_sig1_k3_k4, -- Macro test 3 k3_k4
port2 => macro_sig2_k3_k4, -- Macro test 3 k3_k4
port3 => macro_sign_3, -- Macro test 3 k3_k4
port_mac => macro_sigc(3), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k4, -- Macro test 3 k3_k4
);
# End of Generated Instance Port Map for inst_k3_k4
# Generated Instance Port Map for inst_ok_1
inst_ok_1: inst_ok_1_e
;
# End of Generated Instance Port Map for inst_ok_1
# Generated Instance Port Map for inst_ok_10
inst_ok_10: inst_ok_10_e
;
# End of Generated Instance Port Map for inst_ok_10
# Generated Instance Port Map for inst_ok_2
inst_ok_2: inst_ok_2_e
;
# End of Generated Instance Port Map for inst_ok_2
# Generated Instance Port Map for inst_ok_3
inst_ok_3: inst_ok_3_e
;
# End of Generated Instance Port Map for inst_ok_3
# Generated Instance Port Map for inst_ok_4
inst_ok_4: inst_ok_4_e
;
# End of Generated Instance Port Map for inst_ok_4
# Generated Instance Port Map for inst_ok_5
inst_ok_5: inst_ok_5_e
;
# End of Generated Instance Port Map for inst_ok_5
# Generated Instance Port Map for inst_ok_6
inst_ok_6: inst_ok_6_e
;
# End of Generated Instance Port Map for inst_ok_6
# Generated Instance Port Map for inst_ok_7
inst_ok_7: inst_ok_7_e
;
# End of Generated Instance Port Map for inst_ok_7
# Generated Instance Port Map for inst_ok_8
inst_ok_8: inst_ok_8_e
;
# End of Generated Instance Port Map for inst_ok_8
# Generated Instance Port Map for inst_ok_9
inst_ok_9: inst_ok_9_e
;
# End of Generated Instance Port Map for inst_ok_9
# Generated Instance Port Map for inst_shadow_1
inst_shadow_1: inst_shadow_1_e
;
# End of Generated Instance Port Map for inst_shadow_1
# Generated Instance Port Map for inst_shadow_10
inst_shadow_10: inst_shadow_10_e
;
# End of Generated Instance Port Map for inst_shadow_10
# Generated Instance Port Map for inst_shadow_2
inst_shadow_2: inst_shadow_2_e
;
# End of Generated Instance Port Map for inst_shadow_2
# Generated Instance Port Map for inst_shadow_3
inst_shadow_3: inst_shadow_3_e
;
# End of Generated Instance Port Map for inst_shadow_3
# Generated Instance Port Map for inst_shadow_4
inst_shadow_4: inst_shadow_4_e
;
# End of Generated Instance Port Map for inst_shadow_4
# Generated Instance Port Map for inst_shadow_5
inst_shadow_5: inst_shadow_5_e
;
# End of Generated Instance Port Map for inst_shadow_5
# Generated Instance Port Map for inst_shadow_6
inst_shadow_6: inst_shadow_6_e
;
# End of Generated Instance Port Map for inst_shadow_6
# Generated Instance Port Map for inst_shadow_7
inst_shadow_7: inst_shadow_7_e
;
# End of Generated Instance Port Map for inst_shadow_7
# Generated Instance Port Map for inst_shadow_8
inst_shadow_8: inst_shadow_8_e
;
# End of Generated Instance Port Map for inst_shadow_8
# Generated Instance Port Map for inst_shadow_9
inst_shadow_9: inst_shadow_9_e
;
# End of Generated Instance Port Map for inst_shadow_9
# Generated Instance Port Map for inst_shadow_a
inst_shadow_a: inst_shadow_a_e
;
# End of Generated Instance Port Map for inst_shadow_a
# Generated Instance Port Map for inst_shadow_b
inst_shadow_b: inst_shadow_b_e
;
# End of Generated Instance Port Map for inst_shadow_b
# Generated Instance Port Map for inst_shadow_k1_k2
inst_shadow_k1_k2: inst_shadow_k1_k2_e
;
# End of Generated Instance Port Map for inst_shadow_k1_k2
# Generated Instance Port Map for inst_shadow_k1_k4
inst_shadow_k1_k4: inst_shadow_k1_k4_e
;
# End of Generated Instance Port Map for inst_shadow_k1_k4
# Generated Instance Port Map for inst_shadow_k3_k2
inst_shadow_k3_k2: inst_shadow_k3_k2_e
;
# End of Generated Instance Port Map for inst_shadow_k3_k2
# Generated Instance Port Map for inst_shadow_k3_k4
inst_shadow_k3_k4: inst_shadow_k3_k4_e
;
# End of Generated Instance Port Map for inst_shadow_k3_k4
# Generated Instance Port Map for inst_shadow_ok_1
inst_shadow_ok_1: inst_shadow_ok_1_e
;
# End of Generated Instance Port Map for inst_shadow_ok_1
# Generated Instance Port Map for inst_shadow_ok_10
inst_shadow_ok_10: inst_shadow_ok_10_e
;
# End of Generated Instance Port Map for inst_shadow_ok_10
# Generated Instance Port Map for inst_shadow_ok_2
inst_shadow_ok_2: inst_shadow_ok_2_e
;
# End of Generated Instance Port Map for inst_shadow_ok_2
# Generated Instance Port Map for inst_shadow_ok_3
inst_shadow_ok_3: inst_shadow_ok_3_e
;
# End of Generated Instance Port Map for inst_shadow_ok_3
# Generated Instance Port Map for inst_shadow_ok_4
inst_shadow_ok_4: inst_shadow_ok_4_e
;
# End of Generated Instance Port Map for inst_shadow_ok_4
# Generated Instance Port Map for inst_shadow_ok_5
inst_shadow_ok_5: inst_shadow_ok_5_e
;
# End of Generated Instance Port Map for inst_shadow_ok_5
# Generated Instance Port Map for inst_shadow_ok_6
inst_shadow_ok_6: inst_shadow_ok_6_e
;
# End of Generated Instance Port Map for inst_shadow_ok_6
# Generated Instance Port Map for inst_shadow_ok_7
inst_shadow_ok_7: inst_shadow_ok_7_e
;
# End of Generated Instance Port Map for inst_shadow_ok_7
# Generated Instance Port Map for inst_shadow_ok_8
inst_shadow_ok_8: inst_shadow_ok_8_e
;
# End of Generated Instance Port Map for inst_shadow_ok_8
# Generated Instance Port Map for inst_shadow_ok_9
inst_shadow_ok_9: inst_shadow_ok_9_e
;
# End of Generated Instance Port Map for inst_shadow_ok_9
# Generated Instance Port Map for inst_shadow_t
inst_shadow_t: inst_shadow_t_e
;
# End of Generated Instance Port Map for inst_shadow_t
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
2e6f1cae2bea7ecfe8a781f6ec25ec66
| 0.662403 | 2.886132 | false | false | false | false |
mitchsm/nvc
|
test/sem/conv.vhd
| 5 | 1,161 |
entity conv is
end entity;
architecture test of conv is
type e is (F, G, H);
type a is array (integer range <>) of integer;
type b is array (integer range <>) of integer;
type c is array (integer range <>) of e;
subtype d is a(1 to 3);
function eq(x : a; y : b) return boolean is
begin
return x = a(y);
end function;
begin
process is
variable x : integer;
variable y : a(1 to 3);
variable z : b(1 to 3);
variable w : c(1 to 3);
variable u : d;
variable t : time;
variable r : real;
begin
x := integer(2); -- OK
x := integer(y); -- Error
y := z; -- Error
y := a(z); -- OK
w := c(y); -- Error
assert eq(y, z); -- OK
assert eq(y, b(y)); -- OK
assert eq(u, z); -- OK
assert eq(a(u), z); -- OK
r := real(sec / t); -- OK
x := integer(y(1)); -- OK
wait;
end process;
end architecture;
|
gpl-3.0
|
9517239c1e17b837bcb3e1fa24029511
| 0.410853 | 3.935593 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/RMEM/example_design/RMEM_exdes.vhd
| 1 | 4,585 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RMEM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RMEM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END RMEM_exdes;
ARCHITECTURE xilinx OF RMEM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT RMEM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : RMEM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-2.0
|
200569a6f6dd7a98f59f664c35695fe2
| 0.565758 | 4.761163 | false | false | false | false |
blutsvente/MIX
|
test/results/autoopen/aaa/inst_a_e-rtl-a.vhd
| 1 | 4,072 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.1 2004/04/06 11:19:52 wig Exp $
-- $Date: 2004/04/06 11:19:52 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 11:19:52 wig
-- Adding result/autoopen
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Revision: 1.28 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aa_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
p_mix_s_ai14_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ai16_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ai6_go : out std_ulogic;
p_mix_s_ai8_gi : in std_ulogic;
p_mix_s_aio17_gc : inout std_ulogic;
p_mix_s_aio18_gc : inout std_ulogic;
p_mix_s_aio19_gc : inout std_ulogic;
p_mix_s_ao10_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao11_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao12_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ao13_gi : in std_ulogic_vector(7 downto 0);
p_mix_s_ao1_go : out std_ulogic;
p_mix_s_ao2_go : out std_ulogic;
p_mix_s_ao3_go : out std_ulogic;
p_mix_s_ao4_gi : in std_ulogic;
p_mix_s_ao5_go : out std_ulogic;
p_mix_s_ao9_go : out std_ulogic_vector(7 downto 0);
port_aa : out std_ulogic
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
s_ao10 : in std_ulogic_vector(7 downto 0);
s_ao2 : in std_ulogic
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_aio17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao10 : std_ulogic_vector(7 downto 0);
signal s_ao11 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_ao2 : std_ulogic;
signal s_ao3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
-- __I_OUT_OPEN signal s_intname : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_aio17 <= p_mix_s_aio17_gc; -- __I_I_BIT_PORT
p_mix_s_ao11_go <= s_ao11; -- __I_O_BUS_PORT
p_mix_s_ao3_go <= s_ao3; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
port map (
p_mix_s_ai14_go => s_ai14,
p_mix_s_ai16_gi => s_ai16,
p_mix_s_ai6_go => s_ai6,
p_mix_s_ai8_gi => s_ai8,
p_mix_s_aio17_gc => s_aio17,
p_mix_s_aio18_gc => s_aio18,
p_mix_s_aio19_gc => s_aio19,
p_mix_s_ao10_go => s_ao10,
p_mix_s_ao11_go => s_ao11,
p_mix_s_ao12_gi => s_ao12,
p_mix_s_ao13_gi => s_ao13,
p_mix_s_ao1_go => s_ao1,
p_mix_s_ao2_go => s_ao2,
p_mix_s_ao3_go => s_ao3,
p_mix_s_ao4_gi => s_ao4,
p_mix_s_ao5_go => s_ao5,
p_mix_s_ao9_go => s_ao9,
-- __I_RECONN port_aa => open, -- __I_OUT_OPEN
port_aa => s_outname
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
port map (
s_ao10 => s_ao10,
s_ao2 => s_ao2
);
-- End of Generated Instance Port Map for inst_ab
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
c40c077ea4b7bd2177d98340ef8325ef
| 0.586935 | 2.466384 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/scoptrig.vhd
| 1 | 5,024 |
----------------------------------------------------------------------------
--
-- Oscilloscope Digital Trigger
--
-- This is an implementation of a trigger for a digital oscilloscope in
-- VHDL. There are three inputs to the system, one selects the trigger
-- slope and the other two determine the relationship between the trigger
-- level and the signal level. The only output is a trigger signal which
-- indicates a trigger event has occurred.
--
-- The file contains multiple architectures for a Moore state machine
-- implementation to demonstrate the different ways of building a state
-- machine.
--
--
-- Revision History:
-- 13 Apr 04 Glen George Initial revision.
-- 4 Nov 05 Glen George Updated comments.
-- 17 Nov 07 Glen George Updated comments.
-- 13 Feb 10 Glen George Added more example architectures.
-- 07 Jun 14 Albert Gural Added basic hysterises to reject LSB noise issues.
--
----------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
--
-- Oscilloscope Digital Trigger entity declaration
--
entity ScopeTrigger is
port (
TS : in std_logic; -- trigger slope (1 -> negative, 0 -> positive)
TGT : in std_logic; -- signal level > trigger level + epsilon
TLT : in std_logic; -- signal level < trigger level - epsilon
clk : in std_logic; -- clock
Reset : in std_logic; -- reset the system
TrigEvent : out std_logic -- a trigger event has occurred
);
end ScopeTrigger;
--
-- Oscilloscope Digital Trigger Moore State Machine
-- State Assignment Architecture
--
-- This architecture just shows the basic state machine syntax when the state
-- assignments are made manually. This is useful for minimizing output
-- decoding logic and avoiding glitches in the output (due to the decoding
-- logic).
--
architecture assign_statebits of ScopeTrigger is
subtype states is std_logic_vector(2 downto 0); -- state type
-- define the actual states as constants
constant IDLE : states := "000"; -- waiting for start of trigger event
constant WAIT_POS : states := "001"; -- waiting for positive slope trigger
constant WAIT_NEG : states := "010"; -- waiting for negative slope trigger
constant TRIGGER : states := "100"; -- got a trigger event
signal CurrentState : states; -- current state
signal NextState : states; -- next state
begin
-- the output is always the high bit of the state encoding
TrigEvent <= CurrentState(2);
-- compute the next state (function of current state and inputs)
transition: process (Reset, TS, TGT, TLT, CurrentState)
begin
case CurrentState is -- do the state transition/output
when IDLE => -- in idle state, do transition
if (TS = '0' and TLT = '1') then
NextState <= WAIT_POS; -- below trigger and + slope
elsif (TS = '1' and TGT = '1') then
NextState <= WAIT_NEG; -- above trigger and - slope
else
NextState <= IDLE; -- trigger not possible yet
end if;
when WAIT_POS => -- waiting for positive slope trigger
if (TS = '0' and TGT = '0') then
NextState <= WAIT_POS; -- no trigger yet
elsif (TS = '0' and TGT = '1') then
NextState <= TRIGGER; -- got a trigger
else
NextState <= IDLE; -- trigger slope changed
end if;
when WAIT_NEG => -- waiting for negative slope trigger
if (TS = '1' and TLT = '0') then
NextState <= WAIT_NEG; -- no trigger yet
elsif (TS = '1' and TLT = '1') then
NextState <= TRIGGER; -- got a trigger
else
NextState <= IDLE; -- trigger slope changed
end if;
when TRIGGER => -- in the trigger state
NextState <= IDLE; -- always go back to idle
when others => -- default
NextState <= IDLE; -- go back to idle
end case;
if Reset = '1' then -- reset overrides everything
NextState <= IDLE; -- go to idle on reset
end if;
end process transition;
-- storage of current state (loads the next state on the clock)
process (clk)
begin
if clk = '1' then -- only change on rising edge of clock
CurrentState <= NextState; -- save the new state information
end if;
end process;
end assign_statebits;
|
mit
|
166a33760b2fc1c2a3193109e1020645
| 0.54578 | 4.596523 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab18.vhd
| 4 | 973 |
entity sub is
port (
a : in bit_vector(1 downto 0);
b, c : out bit_vector(1 downto 0);
d : out bit_vector(1 downto 0) := "00" );
end entity;
architecture test of sub is
begin
(b(0), c(0)) <= a;
(b(1), c(1)) <= a;
d(1) <= '1';
end architecture;
-------------------------------------------------------------------------------
entity elab18 is
end entity;
architecture test of elab18 is
signal a1, b1, a2, b2 : bit_vector(1 downto 0);
begin
sub1_i: entity work.sub
port map (
a => a1,
b => b1,
c => open );
process is
begin
a1 <= "01";
wait for 1 ns;
assert b1 = "00";
wait;
end process;
sub2_i: entity work.sub
port map (
a => a2,
b => b2 );
process is
begin
a2 <= "10";
wait for 1 ns;
assert b2 = "11";
wait;
end process;
end architecture;
|
gpl-3.0
|
81f7908e8daa54fb9a5e6897fc13ee05
| 0.427544 | 3.5 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/verilog/inst_a_e-rtl-a.vhd
| 1 | 2,936 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.2 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_xa_e -- mulitple instantiated
-- No Generated Generics
port (
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end component;
-- ---------
component inst_ab_e -- ab instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
port_ab_i : in std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
udc: THIS GOES TO BODY of inst_a_i;
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
p_mix_signal_aa_ba_go <= signal_aa_ba; -- __I_O_BIT_PORT
signal_bb_ab <= p_mix_signal_bb_ab_gi; -- __I_I_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_xa_e -- mulitple instantiated
port map (
port_xa_i => mix_logic0_0, -- tie to low to create port
port_xa_o => signal_aa_ba -- signal test aa to ba
);
-- End of Generated Instance Port Map for inst_aa_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab_e -- ab instance
port map (
port_ab_i => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
ccf831a16ad322e0ece39114809e78e3
| 0.60252 | 3.002045 | false | false | false | false |
mitchsm/nvc
|
test/group/arrayref1.vhd
| 4 | 584 |
entity arrayref is
end entity;
architecture test of arrayref is
type bv2d is array (integer range <>) of bit_vector(1 downto 0);
signal x : bit_vector(2 downto 0); -- 0..2
signal y : bit_vector(1 downto 0); -- 3..4
signal i : integer; -- 5..5
signal p : bv2d(0 to 1); -- 6..9
signal q : bv2d(0 to 2); -- 10..15
signal r : bv2d(0 to 2); -- 16..21
begin
x(0) <= '1';
x(1) <= '0';
y(i) <= '1';
p(0)(i) <= '1';
p(1) <= "00";
q(i) <= "10";
r(2)(i) <= '1';
end architecture;
|
gpl-3.0
|
26d6f12428b1b793c4beede47359368a
| 0.457192 | 2.84878 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/lib/wed.vhd
| 1 | 2,731 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
package wed is
type wed_type is record
status : std_logic_vector(7 downto 0); -- 7 downto 0
wed00_a : std_logic_vector(7 downto 0); -- 15 downto 8
wed00_b : std_logic_vector(15 downto 0); -- 31 downto 16
size : unsigned(31 downto 0); -- 63 downto 32
source : unsigned(63 downto 0); -- 127 downto 64
destination : unsigned(63 downto 0); -- 191 downto 128
wed03 : std_logic_vector(63 downto 0); -- 255 downto 192
wed04 : std_logic_vector(63 downto 0); -- 319 downto 256
wed05 : std_logic_vector(63 downto 0); -- 383 downto 320
wed06 : std_logic_vector(63 downto 0); -- 447 downto 384
wed07 : std_logic_vector(63 downto 0); -- 511 downto 448
wed08 : std_logic_vector(63 downto 0); -- 575 downto 512
wed09 : std_logic_vector(63 downto 0); -- 639 downto 576
wed10 : std_logic_vector(63 downto 0); -- 703 downto 640
wed11 : std_logic_vector(63 downto 0); -- 767 downto 704
wed12 : std_logic_vector(63 downto 0); -- 831 downto 768
wed13 : std_logic_vector(63 downto 0); -- 895 downto 832
wed14 : std_logic_vector(63 downto 0); -- 959 downto 896
wed15 : std_logic_vector(63 downto 0); -- 1023 downto 960
end record;
procedure wed_parse (signal data : in std_logic_vector(1023 downto 0); variable wed : out wed_type);
end package wed;
package body wed is
procedure wed_parse (signal data : in std_logic_vector(1023 downto 0); variable wed : out wed_type) is
begin
wed.status := data(7 downto 0);
wed.wed00_a := data(15 downto 8);
wed.wed00_b := data(31 downto 16);
wed.size := u(data(63 downto 32));
wed.source := u(data(127 downto 64));
wed.destination := u(data(191 downto 128));
wed.wed03 := data(255 downto 192);
wed.wed04 := data(319 downto 256);
wed.wed05 := data(383 downto 320);
wed.wed06 := data(447 downto 384);
wed.wed07 := data(511 downto 448);
wed.wed08 := data(575 downto 512);
wed.wed09 := data(639 downto 576);
wed.wed10 := data(703 downto 640);
wed.wed11 := data(767 downto 704);
wed.wed12 := data(831 downto 768);
wed.wed13 := data(895 downto 832);
wed.wed14 := data(959 downto 896);
wed.wed15 := data(1023 downto 960);
end procedure wed_parse;
end package body wed;
|
bsd-2-clause
|
7d0cb88475f023cb266a9c9a3efba62f
| 0.569022 | 3.474555 | false | false | false | false |
mitchsm/nvc
|
test/regress/lfsr.vhd
| 5 | 1,468 |
entity lfsr16 is
generic (
WIDTH : positive := 16;
TAP : natural := 3 );
port (
clk : in bit;
reset : in bit; -- Asynchronous
en : in bit;
value : out bit_vector(15 downto 0) );
end entity;
architecture rtl of lfsr16 is
signal state_r : bit_vector(WIDTH - 1 downto 0);
begin
value <= state_r;
process (clk, reset) is
begin
if reset = '1' then
state_r <= (others => '0');
elsif clk'event and clk = '1' then
if en = '1' then
state_r(WIDTH - 1 downto 1) <= state_r(WIDTH - 2 downto 0);
state_r(0) <= state_r(WIDTH - 1) xnor state_r(TAP);
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity lfsr is
end entity;
architecture test of lfsr is
constant PERIOD : delay_length := 10 ns;
signal clk, en : bit := '0';
signal reset : bit := '1';
signal value : bit_vector(15 downto 0);
begin
clk <= not clk after PERIOD / 2;
reset <= '0' after 10 ns;
en <= '1' after 30 ns;
uut: entity work.lfsr16
port map ( clk, reset, en, value );
check: process is
begin
wait for 500 ns;
assert value = ('0','1','1','1','1','1','1','1',
'1','1','1','1','1','0','0','0');
wait;
end process;
end architecture;
|
gpl-3.0
|
430dfb6f91be35415991d24d2748c45f
| 0.474796 | 3.744898 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_ec_e-rtl-a.vhd
| 1 | 3,777 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:27 wig Exp $
-- $Date: 2004/04/06 10:50:27 $
-- $Log: inst_ec_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:27 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ec_e
--
architecture rtl of inst_ec_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eca_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eca_e
-- End of Generated Generics for Entity inst_eca_e
port (
-- Generated Port for Entity inst_eca_e
nreset : in std_ulogic;
nreset_s : in std_ulogic;
v_select : in std_ulogic_vector(5 downto 0)
-- End of Generated Port for Entity inst_eca_e
);
end component;
-- ---------
component inst_ecb_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ecb_e
-- End of Generated Generics for Entity inst_ecb_e
port (
-- Generated Port for Entity inst_ecb_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ecb_e
);
end component;
-- ---------
component inst_ecc_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ecc_e
-- End of Generated Generics for Entity inst_ecc_e
port (
-- Generated Port for Entity inst_ecc_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ecc_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
v_select <= p_mix_v_select_5_0_gi; -- __I_I_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eca
inst_eca: inst_eca_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
v_select => v_select -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_eca
-- Generated Instance Port Map for inst_ecb
inst_ecb: inst_ecb_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ecb
-- Generated Instance Port Map for inst_ecc
inst_ecc: inst_ecc_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ecc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
4141a458ab9f272fe50c5499ec19a1d1
| 0.625629 | 3.23928 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/Tx_async.vhd
| 1 | 10,870 |
-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreUART/ CoreUARTapb UART core
--
--
-- Revision Information:
-- Date Description
-- Jun09 Revision 4.1
-- Aug10 Revision 4.2
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR Date Who Description
-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
-- sys clk (not baud clock). See note below.
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY CU_TOP_FPGA_UART_Tx_async IS
GENERIC ( SYNC_RESET : integer := 0;
-- TX Parameters
TX_FIFO : integer := 0); -- 0=without tx fifo
PORT (
-- 1=with tx fifo
clk : IN std_logic;
xmit_pulse : IN std_logic;
reset_n : IN std_logic;
rst_tx_empty : IN std_logic;
tx_hold_reg : IN std_logic_vector(7 DOWNTO 0);
tx_dout_reg : IN std_logic_vector(7 DOWNTO 0);
fifo_empty : IN std_logic;
fifo_full : IN std_logic;
bit8 : IN std_logic;
parity_en : IN std_logic;
odd_n_even : IN std_logic;
txrdy : OUT std_logic;
tx : OUT std_logic;
fifo_read_tx : OUT std_logic);
END ENTITY CU_TOP_FPGA_UART_Tx_async;
ARCHITECTURE translated OF CU_TOP_FPGA_UART_Tx_async IS
CONSTANT tx_idle : integer := 0;
CONSTANT tx_load : integer := 1;
CONSTANT start_bit : integer := 2;
CONSTANT tx_data_bits : integer := 3;
CONSTANT parity_bit : integer := 4;
CONSTANT tx_stop_bit : integer := 5;
CONSTANT delay_state : integer := 6;
SIGNAL xmit_state : integer; -- transmit state machine
SIGNAL txrdy_int : std_logic; -- transmit ready for another byte
SIGNAL tx_byte : std_logic_vector(7 DOWNTO 0); -- transmit byte
SIGNAL xmit_bit_sel : std_logic_vector(3 DOWNTO 0); -- selects transmit bit
SIGNAL tx_parity : std_logic; -- transmit parity
-- AS: Removed deprecated signals due to SARfix for v4.2
SIGNAL fifo_read_en0 : std_logic;
--SIGNAL fifo_read_en1 : std_logic;
--SIGNAL fifo_read_en : std_logic;
SIGNAL txrdy_xhdl1 : std_logic;
SIGNAL tx_xhdl2 : std_logic;
--SIGNAL fifo_read_tx_xhdl3 : std_logic;
SIGNAL aresetn : std_logic;
SIGNAL sresetn : std_logic;
FUNCTION to_integer (
val : std_logic_vector) RETURN integer IS
CONSTANT vec : std_logic_vector(val'high-val'low DOWNTO 0) := val;
VARIABLE rtn : integer := 0;
BEGIN
FOR index IN vec'RANGE LOOP
IF (vec(index) = '1') THEN
rtn := rtn + (2**index);
END IF;
END LOOP;
RETURN(rtn);
END to_integer;
BEGIN
aresetn <= '1' WHEN (SYNC_RESET=1) ELSE reset_n;
sresetn <= reset_n WHEN (SYNC_RESET=1) ELSE '1';
txrdy <= txrdy_xhdl1;
tx <= tx_xhdl2;
-- Modified Sep 2006, ROK
-- ----------------------------------------------------------
-- AS, Sep10: synchronized to start bit, rather than load bit
-- since txload now happens on start bit state
make_txrdy : PROCESS (clk, aresetn)
BEGIN
IF (NOT aresetn = '1') THEN
txrdy_int <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (NOT sresetn = '1') THEN
txrdy_int <= '1';
ELSE
IF (TX_FIFO = 2#0#) THEN
IF (xmit_pulse = '1') THEN
IF (xmit_state = start_bit) THEN
txrdy_int <= '1';
END IF;
END IF;
IF (rst_tx_empty = '1') THEN
txrdy_int <= '0';
END IF;
ELSE
txrdy_int <= NOT fifo_full;
END IF;
END IF;
END IF;
END PROCESS make_txrdy;
-- Modified Sep10, AS
-- FIFO load state transitions and outputs register on system clock
-- (clk) instead of baud clock
xmit_sm : PROCESS (clk, aresetn)
BEGIN
IF (NOT aresetn = '1') THEN
xmit_state <= tx_idle;
tx_byte <= "00000000";
fifo_read_en0 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (NOT sresetn = '1') THEN
xmit_state <= tx_idle;
tx_byte <= "00000000";
fifo_read_en0 <= '1';
ELSE
-- AS:
-- (1) state on sysclk for tx_idle, tx_load, delay_state since these operations run
-- off the system clock, not the baud clock
-- (2) perform tx byte load on start bit state to ensure that data is
-- valid at that point
IF (xmit_pulse = '1' OR xmit_state = tx_idle OR xmit_state = delay_state OR xmit_state = tx_load) THEN
fifo_read_en0 <= '1';
CASE xmit_state IS
WHEN tx_idle =>
IF (TX_FIFO = 2#0#) THEN
IF (NOT txrdy_int = '1') THEN
xmit_state <= tx_load;
ELSE
xmit_state <= tx_idle;
END IF;
ELSE
IF (fifo_empty = '0') THEN
fifo_read_en0 <= '0';
xmit_state <= delay_state;
ELSE
xmit_state <= tx_idle;
fifo_read_en0 <= '1';
END IF;
END IF;
WHEN tx_load =>
xmit_state <= start_bit;
WHEN start_bit =>
IF (TX_FIFO = 2#0#) THEN
tx_byte <= tx_hold_reg;
ELSE
tx_byte <= tx_dout_reg;
END IF;
xmit_state <= tx_data_bits;
WHEN tx_data_bits =>
IF (bit8 = '1') THEN
IF (xmit_bit_sel = "0111") THEN
IF (parity_en = '1') THEN
xmit_state <= parity_bit;
ELSE
xmit_state <= tx_stop_bit;
END IF;
ELSE
xmit_state <= tx_data_bits;
END IF;
ELSE
IF (xmit_bit_sel = "0110") THEN
IF (parity_en = '1') THEN
xmit_state <= parity_bit;
ELSE
xmit_state <= tx_stop_bit;
END IF;
ELSE
xmit_state <= tx_data_bits;
END IF;
END IF;
WHEN parity_bit =>
xmit_state <= tx_stop_bit;
WHEN tx_stop_bit =>
xmit_state <= tx_idle;
WHEN delay_state =>
xmit_state <= tx_load;
WHEN OTHERS =>
xmit_state <= tx_idle;
END CASE;
END IF;
END IF;
END IF;
END PROCESS xmit_sm;
-- AS: Need to remove clock delay of fifo read, since tx_load state is
-- registered on sys clk now and fifo_read_en needs to be made available
-- immediately
-- Added by Hari
-- read_fifo : PROCESS (clk, reset_n)
-- BEGIN
-- IF (NOT reset_n = '1') THEN
-- fifo_read_tx_xhdl3 <= '1';
-- fifo_read_en1 <= '1';
-- ELSIF (clk'EVENT AND clk = '1') THEN
-- fifo_read_tx_xhdl3 <= '1';
-- fifo_read_en1 <= fifo_read_en0;
-- IF (fifo_read_en = '0') THEN
-- fifo_read_tx_xhdl3 <= '0';
-- END IF;
-- END IF;
-- END PROCESS read_fifo;
-- fifo_read_en <= NOT fifo_read_en1 OR fifo_read_en0 ;
fifo_read_tx <= fifo_read_en0;
xmit_cnt : PROCESS (clk, aresetn)
BEGIN
IF (NOT aresetn = '1') THEN
xmit_bit_sel <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (NOT sresetn = '1') THEN
xmit_bit_sel <= "0000";
ELSE
IF (xmit_pulse = '1') THEN
IF (xmit_state /= tx_data_bits) THEN
xmit_bit_sel <= "0000";
ELSE
xmit_bit_sel <= xmit_bit_sel + "0001";
END IF;
END IF;
END IF;
END IF;
END PROCESS xmit_cnt;
xmit_sel : PROCESS (clk, aresetn)
BEGIN
IF (NOT aresetn = '1') THEN
tx_xhdl2 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (NOT sresetn = '1') THEN
tx_xhdl2 <= '1';
ELSE
-- AS:
-- state on sysclk for tx_idle, tx_load, delay_state since these operations run
-- off the system clock, not the baud clock
IF (xmit_pulse = '1' OR xmit_state = tx_idle OR xmit_state = delay_state OR xmit_state = tx_load) THEN
CASE xmit_state IS
WHEN tx_idle =>
tx_xhdl2 <= '1';
WHEN tx_load =>
tx_xhdl2 <= '1';
WHEN start_bit =>
tx_xhdl2 <= '0';
WHEN tx_data_bits =>
--tx <= tx_byte[conv_integer(xmit_bit_sel)] ;
tx_xhdl2 <= tx_byte(to_integer(xmit_bit_sel));
WHEN parity_bit =>
tx_xhdl2 <= odd_n_even XOR tx_parity;
--when parity_bit => if(ODD_N_EVEN = '1') then
-- tx <= not tx_parity;
-- else
-- tx <= tx_parity;
-- end if;
WHEN tx_stop_bit =>
tx_xhdl2 <= '1';
WHEN OTHERS =>
tx_xhdl2 <= '1';
END CASE;
END IF;
END IF;
END IF;
END PROCESS xmit_sel;
xmit_par_calc : PROCESS (clk, aresetn)
BEGIN
IF (NOT aresetn = '1') THEN
tx_parity <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (NOT sresetn = '1') THEN
tx_parity <= '0';
ELSE
IF ((xmit_pulse AND parity_en) = '1') THEN
IF (xmit_state = tx_data_bits) THEN
--tx_parity <= tx_parity ^ tx_byte[conv_integer(xmit_bit_sel)] ;
tx_parity <= tx_parity XOR tx_byte(to_integer(xmit_bit_sel));
ELSE
tx_parity <= tx_parity;
END IF;
END IF;
IF (xmit_state = tx_stop_bit) THEN
tx_parity <= '0';
END IF;
END IF;
END IF;
END PROCESS xmit_par_calc;
txrdy_xhdl1 <= txrdy_int ;
END ARCHITECTURE translated;
|
mit
|
2600a3ecd94797d256a672270b90cfac
| 0.478013 | 3.802029 | false | false | false | false |
mitchsm/nvc
|
test/regress/assign1.vhd
| 5 | 585 |
entity assign1 is
end entity;
architecture test of assign1 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 7;
assert x = 5;
assert y = 7;
wait for 1 ns;
assert x + y = 12;
wait;
end process;
process is
variable x : integer := 64;
variable y : integer := -4;
begin
wait for 4 ns;
assert x = 64 report "x not 64";
assert y = -4 report "y not -4";
x := y * 2;
assert x = -8;
wait;
end process;
end architecture;
|
gpl-3.0
|
2710a19e5ebe9a51e058cd34545a141d
| 0.478632 | 3.823529 | false | false | false | false |
mitchsm/nvc
|
test/lower/assign2.vhd
| 4 | 470 |
entity assign2 is
end entity;
architecture test of assign2 is
begin
process is
variable x : bit_vector(7 downto 0) := (1 => '1', others => '0');
subtype myint is integer range 1 to 10;
type myint_array is array (integer range <>) of myint;
variable y : myint_array(1 to 3);
begin
assert x(0) = '0';
assert x(4) = x(7);
x(2) := '1';
y(1) := y(3);
wait;
end process;
end architecture;
|
gpl-3.0
|
3e503d8a3e86784798adc9aec3823a83
| 0.540426 | 3.455882 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/inst_eb_e-rtl-a.vhd
| 1 | 3,984 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.3 2006/09/25 09:49:31 wig Exp $
-- $Date: 2006/09/25 09:49:31 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.3 2006/09/25 09:49:31 wig
-- Update testcase repository.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eba_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eba_e
c_addr_i : in std_ulogic_vector(12 downto 0);
c_bus_i : in std_ulogic_vector(31 downto 0); -- C-Businterface
mbist_aci_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_vcd_fail_o : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_eba_e
);
end component;
-- ---------
component inst_ebb_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ebb_e
c_addr_i : in std_ulogic_vector(12 downto 0);
c_bus_i : in std_ulogic_vector(31 downto 0); -- CPUInterface
mbist_sum_fail_o : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_ebb_e
);
end component;
-- ---------
component inst_ebc_e
-- No Generated Generics
-- Generated Generics for Entity inst_ebc_e
-- End of Generated Generics for Entity inst_ebc_e
port (
-- Generated Port for Entity inst_ebc_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ebc_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
p_mix_tmi_sbist_fail_12_10_go(2 downto 0) <= tmi_sbist_fail(12 downto 10); -- __I_O_SLICE_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
port map (
c_addr_i => c_addr,
c_bus_i => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
mbist_aci_fail_o => tmi_sbist_fail(10),
mbist_vcd_fail_o => tmi_sbist_fail(11)
);
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
port map (
c_addr_i => c_addr,
c_bus_i => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
mbist_sum_fail_o => tmi_sbist_fail(12)
);
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
b239fbf35a66a9fd986913e195748c18
| 0.62751 | 2.957684 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter10.vhd
| 1 | 4,560 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter10.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter10 IS
PORT
(
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_counter10;
ARCHITECTURE SYN OF lpm_counter10 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 16
)
PORT MAP (
clock => clock,
cnt_en => cnt_en,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "16"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter10.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter10.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter10.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter10.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter10_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
d3915b577463e28892c5623f34111efe
| 0.651096 | 3.639266 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_output_scalars_module.vhd
| 1 | 15,423 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_scalars_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_output_scalars_fifo;
entity xd_output_scalars_module is
generic (
-- System generics:
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MAX_N_OSCALARS : integer;
C_MAX_SCALAR_DWIDTH : integer;
C_N_OUTPUT_SCALARS : integer;
C_N_INOUT_SCALARS : integer;
C_OUTPUT_SCALAR_DWIDTH : std_logic_vector;
C_AP_OSCALAR_DIN_WIDTH : integer;
C_NONE : integer := 2);
port (
--- AP output arguments
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_rst_s_axi_aclk : in std_logic;
ap_oscalar_vld : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ap_oscalar_rdy : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ap_oscalar_din : in std_logic_vector(C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
clk : in std_logic;
rst : in std_logic;
oscalar_rst : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
oscalar_data : out std_logic_vector(C_MAX_N_OSCALARS*C_MAX_SCALAR_DWIDTH-1 downto 0);
oscalar_re : in std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_empty : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_full : out std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_used : out std_logic_vector(C_MAX_N_OSCALARS*4-1 downto 0));
end entity;
architecture rtl of xd_output_scalars_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
signal status_oscalar_full_i : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal status_oscalar_full_i1 : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal ap_oscalar_rdy_i : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
signal ap_oscalar_rdy_i1 : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
begin
OUTPUT_SCALARS_GEN : for i in 0 to C_MAX_N_OSCALARS-1 generate
begin
ACTIVE_GEN : if (i < C_N_OUTPUT_SCALARS) generate
constant OSCALAR_DWIDTH : integer := get_int_element(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_LSB : integer := get_compact_LSB(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_MSB : integer := get_compact_MSB(C_OUTPUT_SCALAR_DWIDTH, i);
signal dout_i : std_logic_vector(OSCALAR_DWIDTH-1 downto 0);
signal fifo_rst_reg : std_logic;
begin
-- fifo_rst <= ap_rst_s_axi_aclk or oscalar_rst(i);
process(clk, ap_rst_s_axi_aclk)
begin
if(ap_rst_s_axi_aclk = '1') then
fifo_rst_reg <= '1';
elsif(clk'event and clk = '1') then
fifo_rst_reg <= oscalar_rst(i);
end if;
end process;
-- We might need to generate one hot for ap_oscalar_vld if there is no full handshake for output scalar vld
-- accelerator might hold valid high for more than one clock
-- TBD
-- oscalar_re signals are generated at the begining of the data phase;
-- not required a write-through fifo.
FIFO_I : entity axis_accelerator_adapter_v2_1_6.xd_output_scalars_fifo
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
WIDTH => OSCALAR_DWIDTH)
port map (
din => ap_oscalar_din(OSCALAR_MSB downto OSCALAR_LSB),
din_vld => ap_oscalar_vld(i),
din_rdy => ap_oscalar_rdy_i(i),
wr_clk => ap_clk,
dout => dout_i,
dout_vld => open,
dout_rdy => oscalar_re(i),
rd_used => status_oscalar_used(4*(i+1)-1 downto 4*i),
rd_empty => status_oscalar_empty(i),
rd_full => status_oscalar_full_i(i),
rd_clk => clk,
rst => fifo_rst_reg);
process(dout_i)
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
oscalar_data(i*C_MAX_SCALAR_DWIDTH+OSCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= dout_i;
end process;
EN_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_OSCALAR_FULL_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => status_oscalar_full_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => status_oscalar_full(i),
scndry_vect_out => open
);
XD_OSCALAR_RDY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => ap_oscalar_rdy_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => ap_oscalar_rdy(i),
scndry_vect_out => open
);
end generate EN_SYNC_GEN_OSCALAR;
NO_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_oscalar_full(i) <= status_oscalar_full_i(i);
ap_oscalar_rdy(i) <= ap_oscalar_rdy_i(i);
end generate NO_SYNC_GEN_OSCALAR;
end generate ACTIVE_GEN;
INACTIVE_GEN : if (i > C_N_OUTPUT_SCALARS-1 and i < 8) generate
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
-- A non used scalar is always ready:
ap_oscalar_rdy(i) <= '1';
status_oscalar_empty(i) <= '0';
status_oscalar_full(i) <= '0';
status_oscalar_used(4*(i+1)-1 downto 4*i) <= (others => '0');
end generate INACTIVE_GEN;
-- Pankaj
INOUT_ACTIVE_GEN : if (i > 7 and i < C_N_INOUT_SCALARS) generate
constant OSCALAR_DWIDTH : integer := get_int_element(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_LSB : integer := get_compact_LSB_IO(C_OUTPUT_SCALAR_DWIDTH, i);
constant OSCALAR_MSB : integer := get_compact_MSB_IO(C_OUTPUT_SCALAR_DWIDTH, i);
signal dout_i : std_logic_vector(OSCALAR_DWIDTH-1 downto 0);
signal fifo_rst_reg : std_logic;
begin
-- fifo_rst <= ap_rst_s_axi_aclk or oscalar_rst(i);
process(clk, ap_rst_s_axi_aclk)
begin
if(ap_rst_s_axi_aclk = '1') then
fifo_rst_reg <= '1';
elsif(clk'event and clk = '1') then
fifo_rst_reg <= oscalar_rst(i);
end if;
end process;
-- We might need to generate one hot for ap_oscalar_vld if there is no full handshake for output scalar vld
-- accelerator might hold valid high for more than one clock
-- TBD
-- oscalar_re signals are generated at the begining of the data phase;
-- not required a write-through fifo.
FIFO_I : entity axis_accelerator_adapter_v2_1_6.xd_output_scalars_fifo
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
WIDTH => OSCALAR_DWIDTH)
port map (
din => ap_oscalar_din(OSCALAR_MSB downto OSCALAR_LSB),
din_vld => ap_oscalar_vld(i),
din_rdy => ap_oscalar_rdy_i(i),
wr_clk => ap_clk,
dout => dout_i,
dout_vld => open,
dout_rdy => oscalar_re(i),
rd_used => status_oscalar_used(4*(i+1)-1 downto 4*i),
rd_empty => status_oscalar_empty(i),
rd_full => status_oscalar_full_i(i),
rd_clk => clk,
rst => fifo_rst_reg);
process(dout_i)
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
oscalar_data(i*C_MAX_SCALAR_DWIDTH+OSCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= dout_i;
end process;
EN_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_OSCALAR_FULL_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => status_oscalar_full_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => status_oscalar_full(i),
scndry_vect_out => open
);
XD_OSCALAR_RDY_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 1,
C_VECTOR_WIDTH => C_MAX_N_OSCALARS,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => ap_clk,
prmry_resetn => '1',
prmry_in => ap_oscalar_rdy_i(i),
prmry_vect_in => (others=>'0'),
scndry_aclk => clk,
scndry_resetn => '1',
scndry_out => ap_oscalar_rdy(i),
scndry_vect_out => open
);
-- process(clk, rst)
-- begin
-- if(clk'event and clk = '1') then
-- if(rst = '1') then
-- status_oscalar_full_i1(i) <= '0';
-- status_oscalar_full(i) <= '0';
-- else
-- status_oscalar_full_i1(i) <=status_oscalar_full_i(i) ;
-- status_oscalar_full(i) <= status_oscalar_full_i1(i);
-- end if;
-- end if;
-- end process;
--
--
-- process(clk, rst)
-- begin
-- if(clk'event and clk = '1') then
-- if(rst = '1') then
-- ap_oscalar_rdy_i1(i) <= '1';
-- ap_oscalar_rdy(i) <= '1';
-- else
-- ap_oscalar_rdy_i1(i) <=ap_oscalar_rdy_i(i) ;
-- ap_oscalar_rdy(i) <= ap_oscalar_rdy_i1(i);
-- end if;
-- end if;
-- end process;
end generate EN_SYNC_GEN_OSCALAR;
NO_SYNC_GEN_OSCALAR : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_oscalar_full(i) <= status_oscalar_full_i(i);
ap_oscalar_rdy(i) <= ap_oscalar_rdy_i(i);
end generate NO_SYNC_GEN_OSCALAR;
end generate INOUT_ACTIVE_GEN;
INOUT_INACTIVE_GEN : if(i > C_N_INOUT_SCALARS-1) generate
begin
oscalar_data((i+1)*C_MAX_SCALAR_DWIDTH-1 downto i*C_MAX_SCALAR_DWIDTH) <= (others => '0');
-- A non used scalar is always ready:
ap_oscalar_rdy(i) <= '1';
status_oscalar_empty(i) <= '0';
status_oscalar_full(i) <= '0';
status_oscalar_used(4*(i+1)-1 downto 4*i) <= (others => '0');
end generate INOUT_INACTIVE_GEN;
---
end generate OUTPUT_SCALARS_GEN;
end rtl;
|
mit
|
9274d0d4db4d6a5b5ffc6cc64c3ef9b1
| 0.537898 | 3.673017 | false | false | false | false |
mitchsm/nvc
|
test/sem/issue239.vhd
| 4 | 857 |
entity issue239 is
end entity;
architecture test of issue239 is
shared variable sv : boolean := false;
constant cb : boolean := sv;
signal sb : boolean := sv; -- ok
begin
process
variable var : boolean := false;
variable var2 : boolean := var; -- ok
procedure proc(
constant b : in boolean := var -- error
) is
begin
report boolean'image(b) severity note;
end procedure;
procedure proc2 (
variable b : in boolean := var -- error
) is
begin
report boolean'image(b) severity note;
end procedure;
begin
proc;
var := true;
proc;
wait;
end process;
end architecture;
package package_issue239 is
constant deferred : integer;
procedure proc(a : integer := deferred); -- OK
end package;
|
gpl-3.0
|
cc8f9e09c6d453029df0599648be7273
| 0.576429 | 4.242574 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/TestOfCpuCore.vhd
| 2 | 49,386 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:24:17 11/24/2013
-- Design Name:
-- Module Name: D:/Src/Computer/computer_work/CPU/TestOfCpuCore.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CPU_CORE
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestOfCpuCore IS
END TestOfCpuCore;
ARCHITECTURE behavior OF TestOfCpuCore IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CPU_CORE
PORT(
CLK : IN std_logic;
RAM1_Addr : OUT std_logic_vector(17 downto 0);
RAM1_EN : OUT std_logic;
RAM1_WE : OUT std_logic;
RAM1_OE : OUT std_logic;
RAM1_Data : INOUT std_logic_vector(15 downto 0);
RAM2_Addr : OUT std_logic_vector(17 downto 0);
RAM2_EN : OUT std_logic;
RAM2_WE : OUT std_logic;
RAM2_OE : OUT std_logic;
RAM2_Data : INOUT std_logic_vector(15 downto 0);
com_data_ready : IN std_logic;
com_rdn : OUT std_logic;
com_tbre : IN std_logic;
com_tsre : IN std_logic;
com_wrn : OUT std_logic;
LED : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal com_data_ready : std_logic := '0';
signal com_tbre : std_logic := '0';
signal com_tsre : std_logic := '0';
--BiDirs
signal RAM1_Data : std_logic_vector(15 downto 0);
signal RAM2_Data : std_logic_vector(15 downto 0);
--Outputs
signal RAM1_Addr : std_logic_vector(17 downto 0);
signal RAM1_EN : std_logic;
signal RAM1_WE : std_logic;
signal RAM1_OE : std_logic;
signal RAM2_Addr : std_logic_vector(17 downto 0);
signal RAM2_EN : std_logic;
signal RAM2_WE : std_logic;
signal RAM2_OE : std_logic;
signal com_rdn : std_logic;
signal com_wrn : std_logic;
signal LED : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CPU_CORE PORT MAP (
CLK => CLK,
RAM1_Addr => RAM1_Addr,
RAM1_EN => RAM1_EN,
RAM1_WE => RAM1_WE,
RAM1_OE => RAM1_OE,
RAM1_Data => RAM1_Data,
RAM2_Addr => RAM2_Addr,
RAM2_EN => RAM2_EN,
RAM2_WE => RAM2_WE,
RAM2_OE => RAM2_OE,
RAM2_Data => RAM2_Data,
com_data_ready => com_data_ready,
com_rdn => com_rdn,
com_tbre => com_tbre,
com_tsre => com_tsre,
com_wrn => com_wrn,
LED => LED
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
-- insert stimulus here
wait for CLK_period/3;
-- SW到IM
RAM1_Data <= ZERO;
RAM2_Data <= "0110100101000000"; --LI R1 40 6940
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011000100100000"; --SLL R1 R1 0000 3120
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101010000000"; --LI R2 80
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101100101000000"; --SW R1 R2 0000
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000001"; --LI R3 01
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000010"; --LI R3 02
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000011"; --LI R3 03
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000100"; --LI R3 04
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
--kernel
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0001000001000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1111000000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100100000010000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110010000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111000010000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000101";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111100000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0001000001001010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1001111000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110111000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1110100011001100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0010000011111000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1110111100000000"; --JR R7
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- test of JR
-------------------------------------------TESTW
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111"; -- LI R6 BF
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000"; -- SLL R6 R6 0x0000
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0100111000000001"; --ADDIU R6 0x0001
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1001111000000000"; --LW R6 R0 0x0000
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110111000000001"; --LI R6 0x0001
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1110100011001100"; --AND R0 R6
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0010000011111000"; --BEQZ R0 TESTW
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------访存到IM内
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000001"; -- LI R0
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
--RAM2_Data <= "1001100101000001"; -- LW from IM OK
RAM2_Data <= "1101100100000001"; -- SW to
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000101";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------条件跳转 OK
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000001"; -- LI R0
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0010000000001111"; --BEQZ R0 1111
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
wait for CLK_period;
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000101";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------写后读 OK
RAM1_Data <= ZERO;
RAM2_Data <= "1001100100000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000000101001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000000101001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000000101001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------写后读
RAM1_Data <= ZERO;
RAM2_Data <= "1110100000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1001100000100010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1001100001000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110100000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
--kernel
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0001000001000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1111000000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111000010000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
wait;
end process;
END;
|
apache-2.0
|
9f33510cedf0c337910bf07e76fafd51
| 0.532863 | 2.512779 | false | false | false | false |
mitchsm/nvc
|
test/misc/ramb_test.vhd
| 5 | 11,365 |
entity ramb_test is
end entity;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
architecture test of ramb_test is
signal doa : std_logic_vector(31 downto 0);
signal dopa : std_logic_vector(3 downto 0);
signal dob : std_logic_vector(31 downto 0);
signal dopb : std_logic_vector(3 downto 0);
signal addra : std_logic_vector(13 downto 0);
signal addrb : std_logic_vector(13 downto 0);
signal ena : std_logic := '1';
signal enb : std_logic := '1';
signal wea : std_logic_vector(3 downto 0) := X"0";
signal web : std_logic_vector(3 downto 0) := X"0";
signal clka : std_logic := '0';
signal dia : std_logic_vector(31 downto 0);
signal dipa : std_logic_vector(3 downto 0);
signal clkb : std_logic := '0';
signal rsta : std_logic := '0';
signal rstb : std_logic := '0';
signal regcea : std_logic := '1';
signal regceb : std_logic := '1';
signal dib : std_logic_vector(31 downto 0);
signal dipb : std_logic_vector(3 downto 0);
begin
RAMB16BWER_inst : entity work.RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INITP_00 to INITP_07: Initial memory contents.
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_00 to INIT_3F: Initial memory contents.
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) output Port A data
DOA => DOA,
-- 32-bit output A port data output
DOPA => DOPA,
-- 4-bit output A port parity output
-- Port B Data: 32-bit (each) output Port B data
DOB => DOB,
-- 32-bit output B port data output
DOPB => DOPB,
-- 4-bit output B port parity output
-- Port A Address/Control Signals: 14-bit (each) input Port A address and control signals
ADDRA => ADDRA,
-- 14-bit input A port address input
CLKA => CLKA,
-- 1-bit input A port clock input
ENA => ENA,
-- 1-bit input A port enable input
REGCEA => REGCEA, -- 1-bit input A port register clock enable input
RSTA => RSTA,
-- 1-bit input A port register set/reset input
WEA => WEA,
-- 4-bit input Port A byte-wide write enable input
-- Port A Data: 32-bit (each) input Port A data
DIA => DIA,
-- 32-bit input A port data input
DIPA => DIPA,
-- 4-bit input A port parity input
-- Port B Address/Control Signals: 14-bit (each) input Port B address and control signals
ADDRB => ADDRB,
-- 14-bit input B port address input
CLKB => CLKB,
-- 1-bit input B port clock input
ENB => ENB,
-- 1-bit input B port enable input
REGCEB => REGCEB, -- 1-bit input B port register clock enable input
RSTB => RSTB,
-- 1-bit input B port register set/reset input
WEB => WEB,
-- 4-bit input Port B byte-wide write enable input
-- Port B Data: 32-bit (each) input Port B data
DIB => DIB,
-- 32-bit input B port data input
DIPB => DIPB
-- 4-bit input B port parity input
);
end architecture;
|
gpl-3.0
|
076cdb5b4c6e71aaa46838f979178d92
| 0.671447 | 6.061333 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/Imm_Extend.vhd
| 2 | 2,960 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:58:51 11/22/2013
-- Design Name:
-- Module Name: Imm_Extend - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Imm_Extend is
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
rd : in STD_LOGIC_VECTOR(2 downto 0);
func : in STD_LOGIC_VECTOR(1 downto 0);
imm : out STD_LOGIC_VECTOR(15 downto 0)
);
end Imm_Extend;
architecture Behavioral of Imm_Extend is
begin
process(code, rs, rt, rd, func)
variable c : integer := 0;
variable res : STD_LOGIC_VECTOR(15 downto 0) := ZERO;
begin
c := 0;
res := ZERO;
case code is
when CODE_IMM_0_0 =>
c := 0;
when CODE_IMM_0_1 =>
c := 0;
when CODE_IMM_0_2 =>
c := 0;
when CODE_IMM_0_3 =>
c := 0;
when CODE_IMM_0_4 =>
c := 0;
when CODE_IMM_0_5 =>
c := 0;
when CODE_IMM_0_6 =>
c := 0;
when CODE_IMM_0_7 =>
c := 0;
when CODE_IMM_1 =>
c := 1;
when CODE_IMM_2_0 =>
c := 2;
when CODE_IMM_2_1 =>
c := 2;
when CODE_IMM_3 =>
c := 3;
when CODE_IMM_4 =>
c := 4;
when CODE_IMM_5 =>
c := 5;
when others =>
c := 6;
end case;
case c is
when 0 =>
if (rt(2) = '1') then
res(15 downto 8) := FFFF(15 downto 8);
end if;
res(7 downto 5) := rt;
res(4 downto 2) := rd;
res(1 downto 0) := func;
when 1 =>
res(7 downto 5) := rt;
res(4 downto 2) := rd;
res(1 downto 0) := func;
when 2 =>
if (rd(2) = '1') then
res(15 downto 5) := FFFF(15 downto 5);
end if;
res(4 downto 2) := rd;
res(1 downto 0) := func;
when 3 =>
if (rs(2) = '1') then
res(15 downto 11) := FFFF(15 downto 11);
end if;
res(10 downto 8) := rs;
res(7 downto 5) := rt;
res(4 downto 2) := rd;
res(1 downto 0) := func;
when 4 =>
if (rd(1) = '1') then
res(15 downto 4) := FFFF(15 downto 4);
end if;
res(3 downto 2) := rd(1 downto 0);
res(1 downto 0) := func;
when 5 =>
res(2 downto 0) := rd;
if (res = ZERO) then
res := EIGHT;
end if;
when others =>
NULL;
end case;
imm <= res;
end process;
end Behavioral;
|
apache-2.0
|
5d04f9221ac19a8e8845e16f84a5b0b3
| 0.531757 | 2.857143 | false | false | false | false |
mitchsm/nvc
|
test/regress/alias6.vhd
| 5 | 985 |
entity alias6 is
end entity;
architecture test of alias6 is
signal x : bit_vector(7 downto 0);
alias x_top is x(7);
alias x_low is x(3 downto 0);
alias x_high is x(7 downto 4);
begin
process is
begin
x <= X"80";
wait for 1 ns;
assert x_top = '1';
assert x_low = X"0";
assert x_high = X"8";
x <= X"04";
wait for 1 ns;
assert x_top = '0';
assert x_low = X"4";
assert x_high = X"0";
x_top <= '1';
wait for 1 ns;
assert x_top = '1';
assert x_low = X"4";
assert x_high = X"8";
x_high <= X"f";
wait for 1 ns;
assert x_top = '1';
assert x_low = X"4";
assert x_high = X"f";
x_low <= X"b";
x_high <= X"1";
wait for 1 ns;
assert x_top = '0';
assert x_low = X"b";
assert x_high = X"1";
assert x = X"1b";
wait;
end process;
end architecture;
|
gpl-3.0
|
4efca6f180124b8e8ee7d64cabc98bec
| 0.454822 | 3.126984 | false | false | false | false |
mitchsm/nvc
|
test/sem/static.vhd
| 1 | 2,046 |
entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
case i is
when bv'length => -- OK
null;
when bv'left => -- OK
null;
when byte'right => -- OK
null;
when bv'hello => -- OK
null;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(3 downto 0);
constant c : bit_vector := "1010";
constant d : bit_vector(G downto 0) := (others => '0');
begin
case v is
when c => -- Error
null;
when others =>
null;
end case;
case v is
when d => -- Error
null;
when others =>
null;
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity sub is
generic ( N : integer );
port ( x : bit_vector );
end entity;
architecture test of sub is
signal y : bit_vector(N - 1 downto 0) := (others => '0') ;
begin
sub_i: entity work.sub
generic map ( N => N )
port map (
x => x(x'left downto x'right) ); -- Error
gen1: for i in y'range generate -- OK
end generate;
b1: block is
type r is record
x, y : integer;
end record;
signal x : r := (1, 2);
begin
gen2: if (N, 2) = r'(1, 2) generate -- OK
end generate;
end block;
sub2_i: entity work.sub
generic map ( N => N )
port map (
x(N downto 0) => x ); -- Error
end architecture;
|
gpl-3.0
|
52ca796cb0e5461529c4f44105cfac08
| 0.427175 | 4.409483 | false | false | false | false |
DacHt/CU_Droptest
|
hdl/CUTTER_PWM.vhd
| 1 | 4,413 |
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: CUTTER_PWM.vhd
-- File history:
-- <V1.0>: <2017-06-08>: <Initial version>
--
-- Description:
-- PWM Controller for thermo cutter, code copied from internet from this link:
-- https://eewiki.net/pages/viewpage.action?pageId=20939345
-- Original author: Scott Larson
--
-- Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::100 VQFP>
-- Author: David Rozenbeek
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY CUTTER_PWM IS
GENERIC(
sys_clk : INTEGER := 32_768_000; --system clock frequency in Hz
pwm_freq : INTEGER := 1_024_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 8; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
PORT(
mclk : IN STD_LOGIC; --system clock
reset : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --Enable signal
duty_wrt : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0)); --pwm outputs
END CUTTER_PWM;
ARCHITECTURE logic OF CUTTER_PWM IS
CONSTANT period : INTEGER := sys_clk/pwm_freq; --number of clocks in one pwm period
TYPE counters IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period - 1; --data type for array of period counters
SIGNAL count : counters := (OTHERS => 0); --array of period counters
SIGNAL half_duty_new : INTEGER RANGE 0 TO period/2 := 0; --number of clocks in 1/2 duty cycle
TYPE half_duties IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period/2; --data type for array of half duty values
SIGNAL half_duty : half_duties := (OTHERS => 0); --array of half duty values (for each phase)
BEGIN
PROCESS(mclk, reset)
BEGIN
IF(reset = '1') THEN --asynchronous reset
count <= (OTHERS => 0); --clear counter
pwm_out <= (OTHERS => '0'); --clear pwm outputs
ELSIF(mclk'EVENT AND mclk = '1') THEN --rising system clock edge
IF(ENA = '1') THEN
IF(duty_wrt = '1') THEN --latch in new duty cycle
half_duty_new <= conv_integer(duty)*period/(2**bits_resolution)/2; --determine clocks in 1/2 duty cycle
END IF;
FOR i IN 0 to phases-1 LOOP --create a counter for each phase
IF(count(0) = period - 1 - i*period/phases) THEN --end of period reached
count(i) <= 0; --reset counter
half_duty(i) <= half_duty_new; --set most recent duty cycle value
ELSE --end of period not reached
count(i) <= count(i) + 1; --increment counter
END IF;
END LOOP;
FOR i IN 0 to phases-1 LOOP --control outputs for each phase
IF(count(i) = half_duty(i)) THEN --phase's falling edge reached
pwm_out(i) <= '0'; --deassert the pwm output
ELSIF(count(i) = period - half_duty(i)) THEN --phase's rising edge reached
pwm_out(i) <= '1'; --assert the pwm output
END IF;
END LOOP;
ELSE
pwm_out(0) <= '0';
END IF;
END IF;
END PROCESS;
END logic;
|
mit
|
4d20a0bb0798359efca1688bfe42a3c1
| 0.449128 | 4.740064 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_output_args_module.vhd
| 1 | 25,740 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_args_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_m2s_adapter;
use axis_accelerator_adapter_v2_1_6.xd_oarg_s2s_adapter;
use axis_accelerator_adapter_v2_1_6.cdc_sync;
entity xd_output_args_module is
generic (
-- System generics:
C_FAMILY : string ; -- Xilinx FPGA family
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_MAX_ARG_DWIDTH : integer;
C_MAX_ARG_AWIDTH : integer;
C_MAX_ARG_N_DIM : integer;
C_MAX_MB_DEPTH : integer;
C_MAX_N_OARGS : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MTBF_STAGES : integer;
C_N_OUTPUT_ARGS : integer;
C_M_AXIS_TDATA_WIDTH : integer;
C_M_AXIS_TUSER_WIDTH : integer;
C_M_AXIS_TID_WIDTH : integer;
C_M_AXIS_TDEST_WIDTH : integer;
C_AP_OARG_TYPE : std_logic_vector;
C_AP_OARG_DWIDTH : std_logic_vector; -- Interface width
C_AP_OARG_MB_DEPTH : std_logic_vector;
C_AP_OARG_WIDTH : std_logic_vector; -- Native width of data
C_AP_OARG_N_DIM : std_logic_vector;
C_AP_OARG_DIM : std_logic_vector;
C_AP_OARG_DIM_1 : std_logic_vector;
C_AP_OARG_DIM_2 : std_logic_vector;
C_AP_OARG_FORMAT_TYPE : std_logic_vector;
C_AP_OARG_FORMAT_FACTOR : std_logic_vector;
C_AP_OARG_FORMAT_DIM : std_logic_vector;
C_NONE : integer := 2);
port (
--- Slave AXI streams (output arguments)
M_AXIS_ACLK : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_ARESETN : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TVALID : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TREADY : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TDATA : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector(C_MAX_N_OARGS*(C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TKEEP : out std_logic_vector(C_MAX_N_OARGS*(C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
M_AXIS_TLAST : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TUSER_WIDTH-1 downto 0);
---
oarg_sw_length : in std_logic_vector(31 downto 0);
oarg_sw_length_m2s : in std_logic_vector(31 downto 0);
oarg_sw_length_we : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_use_sw_length : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
host_oarg_tdest : in std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
---
dbg_stream_nwords : out std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
dbg_buffer_nwords : out std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
dbg_ap_done : in std_logic;
--- AP output arguments
ap_clk : in std_logic;
ap_rst_maclk : in std_logic;
ap_rst : in std_logic;
ap_oarg_rst : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_addr : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_AWIDTH-1 downto 0);
ap_oarg_ce : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_we : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_din : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_oarg_dout : out std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_oarg_rdy : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_oarg_done : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_empty : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_full : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_used : out std_logic_vector(C_MAX_N_OARGS*4-1 downto 0);
ap_fifo_oarg_din : in std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_fifo_oarg_write : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_fifo_oarg_full_n : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
ap_start : in std_logic;
ap_done : in std_logic);
end entity;
architecture rtl of xd_output_args_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
constant C_M_AXIS_TSTRB_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TKEEP_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
alias C_AP_OARG_DIM_dw : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_N_DIM*32-1 downto 0) is C_AP_OARG_DIM;
-- Syncrhonizer Signals
signal oarg_use_sw_length_sync : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_sw_length_we_sync : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_aresetn : std_logic;
signal m_aclk : std_logic;
signal axis_rst : std_logic;
signal axis_rst1 : std_logic;
signal oarg_sw_length_sync_s2s : std_logic_vector(31 downto 0);
signal oarg_sw_length_sync_m2s : std_logic_vector(31 downto 0);
signal ap_rst_sync1_maclk : std_logic;
signal ap_rst_sync_maclk : std_logic;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF ap_rst_sync_maclk : SIGNAL IS "true";
ATTRIBUTE async_reg OF ap_rst_sync1_maclk : SIGNAL IS "true";
begin
-- undriven ports
dbg_stream_nwords <= (others => '0');
dbg_buffer_nwords <= (others => '0');
m_aresetn <= M_AXIS_ARESETN(0);
m_aclk <= M_AXIS_ACLK(0);
------------------------------------
--- aclk to m_axis_aclk Synchronizer
------------------------------------
-- EN_LITE_TO_STRM_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
-- begin
PROCESS (m_aclk, m_aresetn)
BEGIN
-- Register Stage #1
IF (m_aresetn = '0') THEN
axis_rst1 <= '1';
axis_rst <= '1';
ELSIF (m_aclk'event and m_aclk = '1') THEN
axis_rst1 <= '0';
axis_rst <= axis_rst1;
END IF;
END PROCESS;
-- prd1: PROCESS (m_aclk)
-- BEGIN
-- -- Register Stage #1
-- IF (m_aclk'event and m_aclk = '1') THEN
-- ap_rst_sync1_maclk <= ap_rst;
-- ap_rst_sync_maclk <= ap_rst_sync1_maclk;
-- END IF;
-- END PROCESS prd1;
SW_LENGTH_SYNC_M2S : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_sw_length_m2s,
scndry_aclk => m_aclk,
scndry_resetn => axis_rst,
scndry_out => open,
scndry_vect_out => oarg_sw_length_sync_m2s
);
SW_LENGTH_SYNC_S2S : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_sw_length,
scndry_aclk => m_aclk,
scndry_resetn => axis_rst,
scndry_out => open,
scndry_vect_out => oarg_sw_length_sync_s2s
);
XD_SW_LENGTH_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_MAX_N_OARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_use_sw_length,
scndry_aclk => m_aclk,
scndry_resetn => m_aresetn,
scndry_out => open,
scndry_vect_out => oarg_use_sw_length_sync
);
XD_SW_LENGTH_WE_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_MAX_N_OARGS,
C_MTBF_STAGES => C_MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => oarg_sw_length_we,
scndry_aclk => m_aclk,
scndry_resetn => m_aresetn,
scndry_out => open,
scndry_vect_out => oarg_sw_length_we_sync
);
-- end generate EN_LITE_TO_STRM_SYNC_GEN;
------------------------------------
--- Clocks are synchronous
------------------------------------
-- NO_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
-- begin
--
--
-- oarg_use_sw_length_sync <= oarg_use_sw_length;
-- -- oarg_sw_length_we_sync <= oarg_sw_length_we;
--
-- process(m_aclk)
-- begin
-- if(m_aclk'event and m_aclk = '1') then
-- if(m_aresetn = '0') then
-- oarg_sw_length_we_sync <= (others=>'0');
-- else
-- oarg_sw_length_we_sync <= oarg_sw_length_we;
-- end if;
-- end if;
-- end process;
--
-- end generate NO_SYNC_GEN;
------------------------------------
--- Output Argument generation
------------------------------------
OARGS_GEN : if (C_N_OUTPUT_ARGS > 0) generate
begin
OUTPUT_ARGS_GEN : for i in 0 to C_N_OUTPUT_ARGS-1 generate
constant OARG_TYPE : integer := get_int_element(C_AP_OARG_TYPE, i);
constant OARG_DWIDTH : integer := get_int_element(C_AP_OARG_DWIDTH, i);
constant OARG_MB_DEPTH : integer := get_int_element(C_AP_OARG_MB_DEPTH, i);
constant OARG_WIDTH : integer := get_int_element(C_AP_OARG_WIDTH, i);
constant OARG_N_DIM : integer := get_int_element(C_AP_OARG_N_DIM, i);
constant OARG_DIM_1 : integer := get_int_element(C_AP_OARG_DIM_1, i);
constant OARG_DIM_2 : integer := get_int_element(C_AP_OARG_DIM_2, i);
constant OARG_FORMAT_TYPE : integer := get_int_element(C_AP_OARG_FORMAT_TYPE, i);
constant OARG_FORMAT_FACTOR : integer := get_int_element(C_AP_OARG_FORMAT_FACTOR, i);
constant OARG_FORMAT_DIM : integer := get_int_element(C_AP_OARG_FORMAT_DIM, i);
constant OARG_DIM : std_logic_vector := C_AP_OARG_DIM_dw(C_MAX_ARG_N_DIM*32*(i+1)-1 downto C_MAX_ARG_N_DIM*32*i);
constant OARG_DIMS : int_vector(C_MAX_ARG_N_DIM downto 1) := get_int_vector(C_AP_OARG_DIM, C_MAX_ARG_N_DIM*(i+1)-1, C_MAX_ARG_N_DIM*i);
function calc_arg_addr_width2 return integer is
variable addr_width : integer := 10;
variable N_elements : integer := 1;
begin
if (OARG_TYPE = AP_ARG_MEM_MAP_TYPE) then -- Memory map interface
for i in 1 to OARG_N_DIM loop
N_elements := N_elements * OARG_DIMS(i);
end loop;
case OARG_FORMAT_TYPE is
when FORMAT_TYPE_NONE =>
when FORMAT_TYPE_RESHAPE_BLOCK => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_RESHAPE_CYCLIC => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_RESHAPE_COMPLETE =>
when FORMAT_TYPE_PARTITION_BLOCK => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_PARTITION_CYCLIC => N_elements := N_elements / OARG_FORMAT_FACTOR;
when FORMAT_TYPE_PARTITION_COMPLETE =>
when others =>
end case;
addr_width := log2(N_elements);
elsif (OARG_TYPE = AP_ARG_STREAM_TYPE) then -- FIFO interface
-- FIFO interface is considered a unidimentional array; taking the
-- number of elements from dimension 1
N_elements := OARG_DIMS(1);
addr_width := log2(N_elements);
end if;
return addr_width;
end function calc_arg_addr_width2;
signal dbg_arg_addr_width : integer := calc_arg_addr_width2;
function calc_arg_addr_width return integer is
variable addr_width : integer;
variable N_elements : integer;
begin
if (OARG_TYPE = AP_ARG_MEM_MAP_TYPE) then -- Memory map interface
if (OARG_N_DIM = 1) then
N_elements := OARG_DIM_1;
addr_width := log2(N_elements);
elsif (OARG_N_DIM = 2) then
if (OARG_FORMAT_TYPE = FORMAT_TYPE_RESHAPE_BLOCK) then
N_elements := (OARG_DIM_1*OARG_DIM_2)/OARG_FORMAT_FACTOR;
else
N_elements := (OARG_DIM_1*OARG_DIM_2);
end if;
addr_width := log2(N_elements);
end if;
elsif (OARG_TYPE = AP_ARG_STREAM_TYPE) then -- FIFO interface
N_elements := OARG_DIM_1;
addr_width := log2(N_elements);
end if;
return addr_width;
end function calc_arg_addr_width;
constant OARG_AWIDTH : integer := calc_arg_addr_width;
signal test_dim : int_vector(0 to OARG_N_DIM-1) :=
get_int_vector(C_AP_OARG_DIM, OARG_N_DIM-1+C_MAX_ARG_N_DIM*i, C_MAX_ARG_N_DIM*i);
begin
-- BRAM Interface towards accelerator
M2S_GEN : if (OARG_TYPE = AP_ARG_MEM_MAP_TYPE) generate
begin
OARG_M2S_I : entity axis_accelerator_adapter_v2_1_6.xd_m2s_adapter
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_BRAM_TYPE => C_BRAM_TYPE,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
C_AP_ARG_DATA_WIDTH => OARG_DWIDTH,
C_AP_ARG_ADDR_WIDTH => OARG_AWIDTH,
C_MULTIBUFFER_DEPTH => OARG_MB_DEPTH,
C_AP_ARG_WIDTH => OARG_WIDTH,
C_AP_ARG_N_DIM => OARG_N_DIM,
C_AP_ARG_DIMS => OARG_DIMS(OARG_N_DIM downto 1),
C_AP_ARG_DIM_1 => OARG_DIM_1,
C_AP_ARG_DIM_2 => OARG_DIM_2,
C_AP_ARG_FORMAT_TYPE => OARG_FORMAT_TYPE,
C_AP_ARG_FORMAT_FACTOR => OARG_FORMAT_FACTOR,
C_AP_ARG_FORMAT_DIM => OARG_FORMAT_DIM)
port map (
M_AXIS_ACLK => M_AXIS_ACLK(i),
M_AXIS_ARESETN => M_AXIS_ARESETN(i),
M_AXIS_TVALID => M_AXIS_TVALID(i),
M_AXIS_TREADY => M_AXIS_TREADY(i),
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_TDATA_WIDTH*(i+1)-1 downto C_M_AXIS_TDATA_WIDTH*i),
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_M_AXIS_TSTRB_WIDTH*i),
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_M_AXIS_TKEEP_WIDTH*i),
M_AXIS_TLAST => M_AXIS_TLAST(i),
M_AXIS_TID => M_AXIS_TID(C_M_AXIS_TID_WIDTH*(i+1)-1 downto C_M_AXIS_TID_WIDTH*i),
M_AXIS_TDEST => M_AXIS_TDEST(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_TUSER_WIDTH*(i+1)-1 downto C_M_AXIS_TUSER_WIDTH*i),
---
sw_length => oarg_sw_length_sync_m2s,
sw_length_we => oarg_sw_length_we_sync(i),
use_sw_length => oarg_use_sw_length_sync(i),
host_oarg_tdest => host_oarg_tdest(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
---
ap_clk => ap_clk,
ap_rst_sync => ap_rst_maclk,
ap_rst => ap_rst,
ap_arg_addr => ap_oarg_addr(OARG_AWIDTH-1+C_MAX_ARG_AWIDTH*i downto C_MAX_ARG_AWIDTH*i),
ap_arg_ce => ap_oarg_ce(i),
ap_arg_we => ap_oarg_we(i),
ap_arg_din => ap_oarg_din(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_arg_dout => ap_oarg_dout(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_arg_rqt => ap_oarg_rdy(i),
ap_arg_ack => ap_oarg_done(i),
-- Status info
ap_arg_empty => status_oarg_empty(i),
ap_arg_full => status_oarg_full(i),
ap_arg_used => status_oarg_used(4*(i+1)-1 downto 4*i));
-- Unused signals
ap_fifo_oarg_full_n(i) <= '0';
end generate M2S_GEN;
-- FIFO Interface towards accelerator
S2S_GEN : if (OARG_TYPE = AP_ARG_STREAM_TYPE) generate
begin
OARG_S2S_I : entity axis_accelerator_adapter_v2_1_6.xd_oarg_s2s_adapter
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
C_AP_ARG_DATA_WIDTH => OARG_DWIDTH,
C_AP_ARG_ADDR_WIDTH => OARG_AWIDTH,
C_MULTIBUFFER_DEPTH => OARG_MB_DEPTH)
port map (
M_AXIS_ACLK => M_AXIS_ACLK(i),
M_AXIS_ARESETN => M_AXIS_ARESETN(i),
M_AXIS_TVALID => M_AXIS_TVALID(i),
M_AXIS_TREADY => M_AXIS_TREADY(i),
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_TDATA_WIDTH*(i+1)-1 downto C_M_AXIS_TDATA_WIDTH*i),
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_M_AXIS_TSTRB_WIDTH*i),
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_M_AXIS_TKEEP_WIDTH*i),
M_AXIS_TLAST => M_AXIS_TLAST(i),
M_AXIS_TID => M_AXIS_TID(C_M_AXIS_TID_WIDTH*(i+1)-1 downto C_M_AXIS_TID_WIDTH*i),
M_AXIS_TDEST => M_AXIS_TDEST(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_TUSER_WIDTH*(i+1)-1 downto C_M_AXIS_TUSER_WIDTH*i),
---
sw_length => oarg_sw_length_sync_s2s,
sw_length_we => oarg_sw_length_we_sync(i),
use_sw_length => oarg_use_sw_length_sync(i),
host_oarg_tdest => host_oarg_tdest(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i),
---
ap_clk => ap_clk,
ap_rst_sync => ap_rst_maclk,
ap_rst => ap_rst,
ap_oarg_din => ap_fifo_oarg_din(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_oarg_we => ap_fifo_oarg_write(i),
ap_oarg_full_n => ap_fifo_oarg_full_n(i),
ap_arg_rqt => ap_oarg_rdy(i),
ap_arg_ack => ap_oarg_done(i),
ap_start => ap_start,
ap_done => ap_done);
-- Unused signals
ap_oarg_dout(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
status_oarg_empty(i) <= '1';
status_oarg_full(i) <= '0';
status_oarg_used(4*(i+1)-1 downto 4*i) <= (others => '0');
end generate S2S_GEN;
ap_oarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto OARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
end generate OUTPUT_ARGS_GEN;
OARGS_DEFAULT_GEN : if (C_N_OUTPUT_ARGS < C_MAX_N_OARGS) generate
begin
OUTPUT_ARGS_HIGHER_GEN : for i in C_N_OUTPUT_ARGS to C_MAX_N_OARGS-1 generate
constant OARG_DWIDTH : integer := get_int_element(C_AP_OARG_DWIDTH, C_N_OUTPUT_ARGS-1);
begin
M_AXIS_TVALID(i) <= '0';
M_AXIS_TLAST(i) <= '0';
ap_oarg_rdy(i) <= '0';
ap_fifo_oarg_full_n(i) <= '0';
status_oarg_empty(i) <= '0';
status_oarg_full(i) <= '0';
status_oarg_used(4*(i+1)-1 downto 4*i) <= (others => '0');
M_AXIS_TDATA(C_M_AXIS_TDATA_WIDTH*(i+1)-1 downto C_M_AXIS_TDATA_WIDTH*i) <= (others => '0');
M_AXIS_TSTRB(C_M_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_M_AXIS_TSTRB_WIDTH*i) <= (others => '0');
M_AXIS_TKEEP(C_M_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_M_AXIS_TKEEP_WIDTH*i) <= (others => '0');
M_AXIS_TID(C_M_AXIS_TID_WIDTH*(i+1)-1 downto C_M_AXIS_TID_WIDTH*i) <= (others => '0');
M_AXIS_TDEST(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i) <= (others => '0');
M_AXIS_TUSER(C_M_AXIS_TUSER_WIDTH*(i+1)-1 downto C_M_AXIS_TUSER_WIDTH*i) <= (others => '0');
ap_oarg_dout(OARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
ap_oarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto OARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
end generate OUTPUT_ARGS_HIGHER_GEN;
--ap_iarg_dout(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto C_MAX_ARG_DWIDTH*C_N_INPUT_ARGS) <= (others=>'0');
end generate OARGS_DEFAULT_GEN;
end generate OARGS_GEN;
end rtl;
|
mit
|
ffe65195f3a6ae1ed1697d270c7e1994
| 0.533916 | 3.288616 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter9.vhd
| 1 | 4,349 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter9.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter9 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END lpm_counter9;
ARCHITECTURE SYN OF lpm_counter9 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(23 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 24
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "24"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
ab7344269c2a09963cb2168d39e72afa
| 0.651644 | 3.707587 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/Clock_gen.vhd
| 1 | 12,618 |
-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreUART/ CoreUARTapb UART core
--
--
-- Revision Information:
-- Date Description
-- Jun09 Revision 4.1
-- Aug10 Revision 4.2
--
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR Date Who Description
-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
-- sys clk (not baud clock). See note below.
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
entity CU_TOP_FPGA_UART_Clock_gen is
GENERIC (BAUD_VAL_FRCTN_EN : integer := 0;
SYNC_RESET : integer := 0);
port ( clk : in std_logic; -- system clock
reset_n : in std_logic; -- active low async reset
baud_val : in std_logic_vector(12 downto 0); -- value loaded into cntr
BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0); -- fractional part of baud value
baud_clock : out std_logic; -- 16x baud clock pulse
xmit_pulse : out std_logic -- transmit pulse
);
end entity CU_TOP_FPGA_UART_Clock_gen;
architecture rtl of CU_TOP_FPGA_UART_Clock_gen is
signal baud_cntr : std_logic_vector(12 downto 0); -- 16x clock division counter reg.
signal baud_clock_int : std_logic; -- internal 16x baud clock pulse
signal xmit_clock : std_logic;
signal xmit_cntr : std_logic_vector(3 downto 0); -- baud tx counter reg.
signal baud_cntr_one : std_logic;
signal aresetn : std_logic;
signal sresetn : std_logic;
begin
aresetn <= '1' WHEN (SYNC_RESET=1) ELSE reset_n;
sresetn <= reset_n WHEN (SYNC_RESET=1) ELSE '1';
--------------------------------------------------
-- generate a x16 baud clock pulse
--------------------------------------------------
UG09:IF(BAUD_VAL_FRCTN_EN = 1) GENERATE
-- Add one cycle 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 of the time by freezing
-- baud_cntr for one cycle when count reaches 0 for certain xmit_cntr values.
-- xmit_cntr values are identifed by looking for bits of this counter
-- being certain combinations.
make_baud_cntr_one: process(clk,aresetn)
begin
if (aresetn = '0') then
baud_cntr_one <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr_one <= '0';
else
if (baud_cntr = "0000000000001") then
baud_cntr_one <= '1';
else
baud_cntr_one <= '0';
end if;
end if;
end if;
end process make_baud_cntr_one;
make_baud_cntr1: process(clk, aresetn)
begin
if (aresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
else
case BAUD_VAL_FRACTION is
when "000" => if (baud_cntr = "0000000000000") then --0
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "001" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(2 downto 0) = "111" and baud_cntr_one = '1') then --0.125
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "010" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(1 downto 0) = "11" and baud_cntr_one = '1') then --0.25
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "011" => if (baud_cntr = "0000000000000") then
if ((((xmit_cntr(2) = '1') or (xmit_cntr(1) = '1')) and xmit_cntr(0) ='1') and (baud_cntr_one = '1')) then --0.375
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "100" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(0) = '1' and baud_cntr_one = '1') then --0.5
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "101" => if (baud_cntr = "0000000000000") then
if (((xmit_cntr(2) = '1' and xmit_cntr(1) = '1') or xmit_cntr(0) = '1') and baud_cntr_one = '1') then --0.625
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "110" => if (baud_cntr = "0000000000000") then
if ((xmit_cntr(1) = '1' or xmit_cntr(0) = '1') and baud_cntr_one = '1') then -- 0.75
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "111" => if (baud_cntr = "0000000000000") then
if (((xmit_cntr(1) = '1' or xmit_cntr(0) = '1') or xmit_cntr(2 downto 0) = "100") and baud_cntr_one = '1') then -- 0.875
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when others => if (baud_cntr = "0000000000000") then --0
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
end case;
end if;
end if;
end process make_baud_cntr1;
END GENERATE;
UG10:IF(BAUD_VAL_FRCTN_EN= 0) GENERATE
make_baud_cntr2:process(clk,aresetn)
begin
if (aresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
else
if (baud_cntr = "0000000000000") then
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
end if;
end if;
end process make_baud_cntr2;
END GENERATE;
--baud_clock_int <= '1' when baud_cntr = "00000000" else
-- '0';
----------------------------------------------------
-- generate a transmit clock pulse
----------------------------------------------------
make_xmit_clock: process(clk,aresetn)
begin
if(aresetn = '0') then
xmit_cntr <= "0000";
xmit_clock <= '0';
elsif(clk'event and clk='1') then
if(sresetn = '0') then
xmit_cntr <= "0000";
xmit_clock <= '0';
else
if(baud_clock_int = '1') then
xmit_cntr <= xmit_cntr + '1';
if(xmit_cntr = "1111") then
xmit_clock <= '1';
else
xmit_clock <= '0';
end if;
end if;
end if;
end if;
end process;
xmit_pulse <= xmit_clock and baud_clock_int;
baud_clock <= baud_clock_int;
end rtl;
|
mit
|
03568c4397baaf584dfe6b3bca025265
| 0.336662 | 5.25531 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_s2m_memory_dc.vhd
| 1 | 28,283 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_s2m_memory_dc.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
-- Design note: Normally, a gray counter is implemented using a binary counter
-- and transfor the output to gray. However, in this design, the number of bit
-- for the gray counters is 4 worst case (C_MULTIBUFFER_DEPTH = 8). In this
-- situation we can use a look-up based approach (LUT4 for each bit). For a
-- gray counter of N bits, gray_inc function should infer a table of 2**N elements.
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank;
use axis_accelerator_adapter_v2_1_6.iarg_columnized_mem_bank;
entity xd_s2m_memory_dc is
generic (
-- System generics:
C_FAMILY : string; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
CONV_DATA_WIDTH : integer;
CONV_ADDR_WIDTH : integer;
C_AP_ARG_WIDTH : integer;
C_AP_ARG_N_DIM : integer;
C_AP_ARG_DIM_1 : integer;
C_AP_ARG_DIM_2 : integer;
C_AP_ARG_FORMAT_TYPE : integer;
C_AP_ARG_FORMAT_FACTOR : integer;
C_AP_ARG_FORMAT_DIM : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer;
C_NONE : integer := 2;
C_EXTRA_SYNCS : integer := 1);
port (
clk : in std_logic;
rst : in std_logic;
conv_addr : in std_logic_vector(CONV_ADDR_WIDTH-1 downto 0);
conv_ce : in std_logic;
conv_we : in std_logic;
conv_last : in std_logic;
conv_rdy : out std_logic;
conv_data : in std_logic_vector(CONV_DATA_WIDTH-1 downto 0);
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_arg_addr : in std_logic_vector(C_AP_ARG_ADDR_WIDTH-1 downto 0);
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
mb_arg_rdy : out std_logic;
mb_arg_done : in std_logic;
status_empty : out std_logic := '0';
status_full : out std_logic := '1';
status_used : out std_logic_vector(3 downto 0)); -- Number of used buffers
end entity;
architecture rtl of xd_s2m_memory_dc is
------------------------------------
function calc_use_columnized_bank return boolean is
variable ret : boolean := false;
begin
if (C_AP_ARG_N_DIM = 2) then
if(C_AP_ARG_FORMAT_TYPE = FORMAT_TYPE_RESHAPE_BLOCK) then
if(C_AP_ARG_FORMAT_DIM = 1 and C_AP_ARG_FORMAT_FACTOR > 1) then
ret := true;
end if;
end if;
end if;
return ret;
end function calc_use_columnized_bank;
constant PTR_WIDTH : integer := if_then_else((C_MULTIBUFFER_DEPTH = 1),1,log2(C_MULTIBUFFER_DEPTH));
constant GRAY_WIDTH : integer := calc_gray_width(C_MULTIBUFFER_DEPTH);
constant INIT_RD_GRAY : integer := 0;
constant INIT_WR_GRAY : integer := INIT_RD_GRAY;
constant INIT_WR_GRAY_AHEAD : integer := INIT_RD_GRAY-C_MULTIBUFFER_DEPTH+1;
constant USE_COLUMNIZED_BANK : boolean := calc_use_columnized_bank;
signal empty_n : std_logic;
signal ap_rstn : std_logic;
signal rstn : std_logic;
signal mb_arg_rdy_i : std_logic;
signal full_n : std_logic;
-- pragma translate_off
signal empty : std_logic;
signal full : std_logic;
-- pragma translate_on
signal status_empty_i : std_logic;
-- Multibuffer push/pop
signal mb_push : std_logic;
signal m_axis_tlast : std_logic;
signal m_axis_tvalid : std_logic;
signal mb_pop : std_logic;
signal mb_push_ok : std_logic;
signal mb_pop_ok : std_logic;
-- Selection for read buffer
signal rd_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal rd_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal rd_pntr_wr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal axis_rd_data_count : std_logic_vector(PTR_WIDTH downto 0);
signal rd_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_gray_wr : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray_wr: std_logic_vector(GRAY_WIDTH-1 downto 0);
-- Gray read counter synchronized with read clk
signal rd_gray_sync : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal rd_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal wr_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal ptr_dist : unsigned(GRAY_WIDTH-1 downto 0);
signal pntr_dist : std_logic_vector(PTR_WIDTH-1 downto 0);
-- Selection for write buffer
signal wr_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal wr_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal wr_pntr_rd : std_logic_vector(PTR_WIDTH-1 downto 0);
signal axis_wr_data_count : std_logic_vector(PTR_WIDTH downto 0);
signal wr_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal wr_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
-- pragma translate_on
-- New buffer is filled is last data beat is written and the multibuffer is
-- not full
mb_push <= full_n and conv_ce and conv_last;
-- Active buffer has been consumed when signal "mb_arg_done" is activated and
-- the multibuffer is not empty.
mb_pop <= empty_n and mb_arg_done;
-- Pointer to write buffer
process(clk, ap_rst)
begin
if(ap_rst = '1') then
wr_ptr <= (others => '0');
wr_ptr_dec <= (others => '0');
wr_ptr_dec(0) <= '1';
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
if(wr_ptr = C_MULTIBUFFER_DEPTH-1) then
wr_ptr <= (others => '0');
else
wr_ptr <= wr_ptr + 1;
end if;
wr_ptr_dec <= wr_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & wr_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(clk, ap_rst)
begin
if(ap_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD,GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
end if;
end if;
end process;
-- Generation of status full signal
process(clk, ap_rst)
begin
if(ap_rst = '1') then
full_n <= '0';
elsif(clk'event and clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Move to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
-- Selection pointer for read buffer (pop)
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
rd_ptr <= (others => '0');
rd_ptr_dec <= (others => '0');
rd_ptr_dec(0) <= '1';
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
if(rd_ptr = C_MULTIBUFFER_DEPTH-1) then
rd_ptr <= (others => '0');
else
rd_ptr <= rd_ptr + 1;
end if;
rd_ptr_dec <= rd_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & rd_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (read) to manage the status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
end if;
end if;
end process;
-- Generation of empty status signal
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
empty_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray) then
empty_n <= not(mb_pop_ok);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
mb_pop_ok <= mb_pop and empty_n;
conv_rdy <= full_n;
mb_arg_rdy <= empty_n;
-----------------
-- STATUS INFO --
-----------------
-- Following logic is used to provide status information to software. Among
-- others this information includes:
-- * empty signal
-- * full signal
-- * Number of buffers used
-- All this status information should be provided on the AXI clock domain
-- NUMBER OF USED BUFFERS:
-- this value is calculated based on the distance between the read and write
-- pointers.
-- Synchronization of rd_gray to reduce metastability issues. This will
-- introduce a latency of one clock on rd_clk
process(clk, ap_rst)
begin
if(ap_rst = '1') then
rd_gray_sync <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
rd_gray_sync <= rd_gray;
end if;
end process;
rd_bin <= unsigned(gray2bin(rd_gray_sync));
process(clk, ap_rst)
begin
if(ap_rst = '1') then
wr_bin <= to_unsigned(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_bin <= wr_bin + 1;
end if;
end if;
end process;
-- If comparing pointers happens during write, then there will be a one cycle
-- latency to reflect the status of the fifo. To refresh inmediately, during
-- a write we increment the counter.
process(clk, ap_rst)
begin
if(ap_rst = '1') then
ptr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
ptr_dist <= ptr_dist + 1;
else
-- This is also valid when we arrive at the end of counting sequence
-- for wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
process(ptr_dist)
begin
status_used <= (others => '0');
status_used(ptr_dist'range) <= std_logic_vector(ptr_dist);
end process;
-- STATUS FULL:
-- this signal is generated in the AXI clock domain; Hence, status_full
-- is just a simple copy of the internal signal
status_full <= not(full_n);
-- STATUS EMPTY:
-- This signal represents the empty status of the multibiffer from the point
-- of view of the write port (AXI clock domain)
process(clk, ap_rst)
begin
if(ap_rst = '1') then
status_empty_i <= '1';
elsif(clk'event and clk = '1') then
-- If write, we exit the empty condition inmediately
if(mb_push_ok = '1') then
status_empty_i <= '0';
else
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray) then
status_empty_i <= '1';
else
status_empty_i <= '0';
end if;
end if;
end if;
end process;
status_empty <= status_empty_i;
end generate EXISTING;
------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------
NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate
CONSTANT LOG2DEPTH : integer := log2(C_MULTIBUFFER_DEPTH);
CONSTANT ONE : std_logic_vector(PTR_WIDTH-1 DOWNTO 0)
:= int2lv(1, PTR_WIDTH);
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
ap_rstn <= not(ap_rst);
rstn <= not(rst);
-- pragma translate_on
-- New buffer is filled is last data beat is written and the multibuffer is
-- not full
mb_push <= full_n and conv_ce and conv_last;
-- Active buffer has been consumed when signal "mb_arg_done" is activated and
-- the multibuffer is not empty.
mb_pop <= empty_n and mb_arg_done;
-- Pointer to write buffer
process(clk, rst)
begin
if(rst = '1') then
wr_pntr <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
if(wr_pntr = int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
wr_pntr <= (others => '0');
else
wr_pntr <= wr_pntr + ONE;
end if;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
rd_pntr <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
if(rd_pntr =int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
rd_pntr <= (others => '0');
else
rd_pntr <= rd_pntr + ONE;
end if;
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(clk, rst)
begin
if(rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD,GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
end if;
end if;
end process;
-- Gray pointers (read) to manage the status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_pop_ok = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
end if;
end if;
end process;
clkx_1: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => clk,
RD_CLK => ap_clk,
WR_RST => rst,
RD_RST => ap_rst,
WR_PNTR => wr_gray,
RD_PNTR => rd_gray,
WR_PNTR_RD => wr_gray_rd,
RD_PNTR_WR => rd_gray_wr
);
clkx_2: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => clk,
RD_CLK => ap_clk,
WR_RST => rst,
RD_RST => ap_rst,
WR_PNTR => wr_gray_ahead,
RD_PNTR => next_rd_gray,
WR_PNTR_RD => wr_gray_ahead_rd,
RD_PNTR_WR => next_rd_gray_wr
);
clkx_3: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => PTR_WIDTH,
C_WR_PNTR_WIDTH => PTR_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => clk,
RD_CLK => ap_clk,
WR_RST => rst,
RD_RST => ap_rst,
WR_PNTR => wr_pntr,
RD_PNTR => rd_pntr,
WR_PNTR_RD => wr_pntr_rd,
RD_PNTR_WR => rd_pntr_wr
);
-- Generation of status full signal
process(clk, rst)
begin
if(rst = '1') then
full_n <= '0';
elsif(clk'event and clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray_wr) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Move to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray_wr) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
-- Generation of empty status signal
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
empty_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray_rd) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray_rd) then
empty_n <= not(mb_pop_ok);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
mb_pop_ok <= mb_pop and empty_n;
conv_rdy <= full_n;
mb_arg_rdy <= empty_n;
-- AP_IRGRDY_SYNC_I : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 1,
-- C_VECTOR_WIDTH => 2,
-- C_MTBF_STAGES => C_MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => ap_clk,
-- prmry_resetn => ap_rstn,
-- prmry_in => mb_arg_rdy_i,
-- prmry_vect_in => (others=>'0'),
--
-- scndry_aclk => clk,
-- scndry_resetn => rstn,
-- scndry_out => mb_arg_rdy,
-- scndry_vect_out => open
-- );
MBn : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
pntr_dist <= pntr_dist + 1;
else
-- pntr_dist <= ('0' & wr_pntr) - ( '0' & rd_pntr_wr);
pntr_dist <= ( wr_pntr) - ( rd_pntr_wr);
--pntr_dist <= ( wr_bins) - ( rd_bins);
end if;
end if;
end process;
end generate MBn;
MB1 : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
rd_bins <= rd_gray_wr;
process(clk, rst)
begin
if(rst = '1') then
wr_bins <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
wr_bins <= wr_bins + 1;
end if;
end if;
end process;
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_push_ok = '1') then
pntr_dist <= pntr_dist + 1;
else
pntr_dist <= ( wr_bins) - ( rd_bins);
end if;
end if;
end process;
end generate MB1;
process(pntr_dist)
begin
status_used <= (others => '0');
status_used(pntr_dist'range) <= (pntr_dist);
end process;
-- STATUS FULL:
-- this signal is generated in the AXI clock domain; Hence, status_full
-- is just a simple copy of the internal signal
status_full <= not(full_n);
-- STATUS EMPTY:
-- This signal represents the empty status of the multibiffer from the point
-- of view of the write port (AXI clock domain)
process(clk, rst)
begin
if(rst = '1') then
status_empty_i <= '1';
elsif(clk'event and clk = '1') then
-- If write, we exit the empty condition inmediately
if(mb_push_ok = '1') then
status_empty_i <= '0';
else
-- Stay in empty if rd_gray = wr_gray
if(rd_gray_wr = wr_gray) then
status_empty_i <= '1';
else
status_empty_i <= '0';
end if;
end if;
end if;
end process;
status_empty <= status_empty_i;
end generate NEW_INTRO;
LINEAR_BANK_GEN : if not(USE_COLUMNIZED_BANK) generate
-- Efective width for input address bus (conv_addr)
function calc_eff_addr_width return integer is
variable addr_width : integer;
begin
if(CONV_DATA_WIDTH > C_AP_ARG_DATA_WIDTH) then
addr_width := C_AP_ARG_ADDR_WIDTH-log2(CONV_DATA_WIDTH/C_AP_ARG_DATA_WIDTH);
else
addr_width := C_AP_ARG_ADDR_WIDTH+log2(C_AP_ARG_DATA_WIDTH/CONV_DATA_WIDTH);
end if;
return addr_width;
end function calc_eff_addr_width;
constant EFF_ADDR_WIDTH : integer := calc_eff_addr_width;
constant IPORT_ADDR_WIDTH : integer := EFF_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
constant OPORT_ADDR_WIDTH : integer := C_AP_ARG_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
signal iport_addr : std_logic_vector(IPORT_ADDR_WIDTH-1 downto 0);
-- Width of address bus of output port is the addition of number of bits
-- required by input argument plus the required bits to select the
-- appropiate bank (PTR_WIDTH).
signal oport_addr : std_logic_vector(OPORT_ADDR_WIDTH-1 downto 0);
begin
MB1_addr : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
iport_addr <= conv_addr(EFF_ADDR_WIDTH-1 downto 0);
oport_addr <= ap_arg_addr;
end generate MB1_addr;
MBn_addr : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
iport_addr <= std_logic_vector(wr_pntr) & conv_addr(EFF_ADDR_WIDTH-1 downto 0);
oport_addr <= std_logic_vector(rd_pntr) & ap_arg_addr;
end generate MBn_addr;
MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => 1,
C_IPORT_DWIDTH => CONV_DATA_WIDTH,
C_IPORT_AWIDTH => IPORT_ADDR_WIDTH,
C_OPORT_DWIDTH => C_AP_ARG_DATA_WIDTH,
C_OPORT_AWIDTH => OPORT_ADDR_WIDTH)
port map (
rst => ap_rst,
iport_clk => clk,
iport_ce => conv_ce,
iport_we => '1',
iport_addr => iport_addr,
iport_din => conv_data,
iport_dout => open,
oport_clk => ap_clk,
oport_ce => ap_arg_ce,
oport_we => ap_arg_we,
oport_addr => oport_addr,
oport_din => ap_arg_din,
oport_dout => ap_arg_dout);
end generate LINEAR_BANK_GEN;
COLUMNIZED_BANK_GEN : if (USE_COLUMNIZED_BANK) generate
begin
MEM_I : entity axis_accelerator_adapter_v2_1_6.iarg_columnized_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_FACTOR => C_AP_ARG_FORMAT_FACTOR,
C_BUFFER_WIDTH => PTR_WIDTH,
C_CONV_AWIDTH => CONV_ADDR_WIDTH,
C_CONV_DWIDTH => CONV_DATA_WIDTH,
C_ARG_WIDTH => C_AP_ARG_WIDTH,
C_ARG_AWIDTH => C_AP_ARG_ADDR_WIDTH)
port map (
ap_rst => ap_rst,
clk => clk,
conv_ce => conv_ce,
conv_we => conv_we,
conv_buffer => std_logic_vector(wr_ptr),
conv_addr => conv_addr,
conv_data => conv_data,
ap_clk => ap_clk,
ap_arg_ce => ap_arg_ce,
ap_arg_we => ap_arg_we,
ap_arg_buffer => std_logic_vector(rd_ptr),
ap_arg_addr => ap_arg_addr,
ap_arg_din => ap_arg_din,
ap_arg_dout => ap_arg_dout);
end generate COLUMNIZED_BANK_GEN;
end rtl;
|
mit
|
a58b2401b89787f63341253463519142
| 0.54478 | 3.467329 | false | false | false | false |
blutsvente/MIX
|
test/results/typecast/intsig/inst_a-rtl-a.vhd
| 1 | 6,221 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:56:39 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -nodelta ../../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a-rtl-a.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: inst_a-rtl-a.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a
--
architecture rtl of inst_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aa -- typecast module
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa
port_a_1 : out std_ulogic;
port_a_11 : out std_ulogic_vector(7 downto 0);
port_a_3 : out std_ulogic_vector(7 downto 0);
port_a_5 : out std_ulogic;
port_a_7 : out std_logic_vector(7 downto 0);
port_a_9 : out std_ulogic;
signal_10 : out std_logic;
signal_12 : out std_logic_vector(15 downto 0);
signal_2 : out std_logic;
signal_4 : out std_logic_vector(15 downto 0);
signal_6 : out std_logic;
signal_8 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa
);
end component;
-- ---------
component inst_ab -- receiver module
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab
port_b_1 : in std_logic;
port_b_10 : in std_ulogic;
port_b_11 : in std_ulogic_vector(7 downto 0);
port_b_12 : in std_logic_vector(15 downto 0);
port_b_2 : in std_ulogic;
port_b_3 : in std_logic_vector(7 downto 0);
port_b_4 : in std_ulogic_vector(15 downto 0);
port_b_5 : in std_logic;
port_b_6 : in std_ulogic;
port_b_7 : in std_ulogic_vector(7 downto 0);
port_b_8 : in std_logic_vector(15 downto 0);
port_b_9 : in std_logic
-- End of Generated Port for Entity inst_ab
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_mix_tc_10_signal_10 : std_logic;
signal s_mix_tc_11_signal_11 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_12_signal_11 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_13_signal_12 : std_logic_vector(15 downto 0);
signal s_mix_tc_14_signal_12 : std_logic_vector(15 downto 0);
signal s_mix_tc_1_signal_1 : std_ulogic;
signal s_mix_tc_2_signal_2 : std_logic;
signal s_mix_tc_3_signal_3 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_4_signal_4 : std_logic_vector(15 downto 0);
signal s_mix_tc_5_signal_5 : std_ulogic;
signal s_mix_tc_6_signal_6 : std_logic;
signal s_mix_tc_7_signal_7 : std_ulogic_vector(7 downto 0);
signal s_mix_tc_8_signal_8 : std_logic_vector(15 downto 0);
signal s_mix_tc_9_signal_9 : std_ulogic;
signal signal_1 : std_logic;
signal signal_10 : std_ulogic;
signal signal_11 : std_logic_vector(7 downto 0);
signal signal_12 : std_ulogic_vector(15 downto 0);
signal signal_2 : std_ulogic;
signal signal_3 : std_logic_vector(7 downto 0);
signal signal_4 : std_ulogic_vector(15 downto 0);
signal signal_5 : std_logic;
signal signal_6 : std_ulogic;
signal signal_7 : std_logic_vector(7 downto 0);
signal signal_8 : std_ulogic_vector(15 downto 0);
signal signal_9 : std_logic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
signal_1 <= std_logic( s_mix_tc_1_signal_1 ) ; -- __I_TYPECAST
signal_2 <= std_ulogic( s_mix_tc_2_signal_2 ) ; -- __I_TYPECAST
s_mix_tc_11_signal_11 <= std_ulogic_vector( signal_11 ) ; -- __I_TYPECAST
signal_11 <= std_logic_vector( s_mix_tc_12_signal_11 ) ; -- __I_TYPECAST
s_mix_tc_13_signal_12 <= std_logic_vector( signal_12 ) ; -- __I_TYPECAST
signal_12 <= std_ulogic_vector( s_mix_tc_14_signal_12 ) ; -- __I_TYPECAST
signal_3 <= std_logic_vector( s_mix_tc_3_signal_3 ) ; -- __I_TYPECAST
signal_4 <= std_ulogic_vector( s_mix_tc_4_signal_4 ) ; -- __I_TYPECAST
signal_5 <= std_logic( s_mix_tc_5_signal_5 ) ; -- __I_TYPECAST
signal_6 <= std_ulogic( s_mix_tc_6_signal_6 ) ; -- __I_TYPECAST
s_mix_tc_7_signal_7 <= std_ulogic_vector( signal_7 ) ; -- __I_TYPECAST
s_mix_tc_8_signal_8 <= std_logic_vector( signal_8 ) ; -- __I_TYPECAST
signal_9 <= std_logic( s_mix_tc_9_signal_9 ) ; -- __I_TYPECAST
signal_10 <= std_ulogic( s_mix_tc_10_signal_10 ) ; -- __I_TYPECAST
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_aa -- typecast module
port map (
port_a_1 => s_mix_tc_1_signal_1,
port_a_11 => s_mix_tc_12_signal_11,
port_a_3 => s_mix_tc_3_signal_3,
port_a_5 => s_mix_tc_5_signal_5,
port_a_7 => signal_7,
port_a_9 => s_mix_tc_9_signal_9,
signal_10 => s_mix_tc_10_signal_10,
signal_12 => s_mix_tc_14_signal_12,
signal_2 => s_mix_tc_2_signal_2,
signal_4 => s_mix_tc_4_signal_4,
signal_6 => s_mix_tc_6_signal_6,
signal_8 => signal_8
);
-- End of Generated Instance Port Map for inst_aa_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab -- receiver module
port map (
port_b_1 => signal_1,
port_b_10 => signal_10,
port_b_11 => s_mix_tc_11_signal_11,
port_b_12 => s_mix_tc_13_signal_12,
port_b_2 => signal_2,
port_b_3 => signal_3,
port_b_4 => signal_4,
port_b_5 => signal_5,
port_b_6 => signal_6,
port_b_7 => s_mix_tc_7_signal_7,
port_b_8 => s_mix_tc_8_signal_8,
port_b_9 => signal_9
);
-- End of Generated Instance Port Map for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
4c4a434352ba72080d70e547f0030b68
| 0.612442 | 2.599666 | false | false | false | false |
blutsvente/MIX
|
test/results/macro/inst_t_e-rtl-a.vhd
| 1 | 19,503 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 13:29:42 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.5 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.5 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
gensig_1 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
port_mac_b : in std_ulogic_vector(3 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
gensig_1 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : out std_ulogic_vector(7 downto 0) -- Generated signals, connecting b to a
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
component inst_k1_k2_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k1_k2_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port_mac : out std_ulogic; -- Macro test 0 k1_k2 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_k1_k2_e
);
end component;
-- ---------
component inst_k1_k4_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k1_k4_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 1 k1_k4
port_mac : out std_ulogic; -- Macro test 1 k1_k4 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 1 k1_k4
-- End of Generated Port for Entity inst_k1_k4_e
);
end component;
-- ---------
component inst_k3_k2_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k3_k2_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 2 k3_k2
port_mac : out std_ulogic; -- Macro test 2 k3_k2 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 2 k3_k2
-- End of Generated Port for Entity inst_k3_k2_e
);
end component;
-- ---------
component inst_k3_k4_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_k3_k4_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 3 k3_k4
port_mac : out std_ulogic; -- Macro test 3 k3_k4 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 3 k3_k4
-- End of Generated Port for Entity inst_k3_k4_e
);
end component;
-- ---------
component inst_ok_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ok_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_a_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_b_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k1_k2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k1_k4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k3_k2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_k3_k4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_1_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_10_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_3_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_4_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_5_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_6_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_7_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_8_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_ok_9_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_shadow_t_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal gensig_1 : std_ulogic_vector(7 downto 0);
signal gensig_10 : std_ulogic_vector(7 downto 0);
signal gensig_2 : std_ulogic_vector(7 downto 0);
signal gensig_3 : std_ulogic_vector(7 downto 0);
signal gensig_4 : std_ulogic_vector(7 downto 0);
signal gensig_5 : std_ulogic_vector(7 downto 0);
signal gensig_6 : std_ulogic_vector(7 downto 0);
signal gensig_7 : std_ulogic_vector(7 downto 0);
signal gensig_8 : std_ulogic_vector(7 downto 0);
signal gensig_9 : std_ulogic_vector(7 downto 0);
signal macro_sigc : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9, -- Generated signals, connecting b to a
port_mac_b => macro_sigc -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: inst_b_e
port map (
gensig_1 => gensig_1, -- Generated signals, connecting a to b
gensig_10 => gensig_10, -- Generated signals, connecting b to a
gensig_2 => gensig_2, -- Generated signals, connecting a to b
gensig_3 => gensig_3, -- Generated signals, connecting a to b
gensig_4 => gensig_4, -- Generated signals, connecting a to b
gensig_5 => gensig_5, -- Generated signals, connecting a to b
gensig_6 => gensig_6, -- Generated signals, connecting b to a
gensig_7 => gensig_7, -- Generated signals, connecting b to a
gensig_8 => gensig_8, -- Generated signals, connecting b to a
gensig_9 => gensig_9 -- Generated signals, connecting b to a
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_k1_k2
inst_k1_k2: inst_k1_k2_e
port map (
port1 => macro_sig1_k1_k2, -- Macro test 0 k1_k2
port2 => macro_sig2_k1_k2, -- Macro test 0 k1_k2
port3 => macro_sign_0, -- Macro test 0 k1_k2
port_mac => macro_sigc(0), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k2 -- Macro test 0 k1_k2
);
-- End of Generated Instance Port Map for inst_k1_k2
-- Generated Instance Port Map for inst_k1_k4
inst_k1_k4: inst_k1_k4_e
port map (
port1 => macro_sig1_k1_k4, -- Macro test 1 k1_k4
port2 => macro_sig2_k1_k4, -- Macro test 1 k1_k4
port3 => macro_sign_1, -- Macro test 1 k1_k4
port_mac => macro_sigc(1), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k1_k4 -- Macro test 1 k1_k4
);
-- End of Generated Instance Port Map for inst_k1_k4
-- Generated Instance Port Map for inst_k3_k2
inst_k3_k2: inst_k3_k2_e
port map (
port1 => macro_sig1_k3_k2, -- Macro test 2 k3_k2
port2 => macro_sig2_k3_k2, -- Macro test 2 k3_k2
port3 => macro_sign_2, -- Macro test 2 k3_k2
port_mac => macro_sigc(2), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k2 -- Macro test 2 k3_k2
);
-- End of Generated Instance Port Map for inst_k3_k2
-- Generated Instance Port Map for inst_k3_k4
inst_k3_k4: inst_k3_k4_e
port map (
port1 => macro_sig1_k3_k4, -- Macro test 3 k3_k4
port2 => macro_sig2_k3_k4, -- Macro test 3 k3_k4
port3 => macro_sign_3, -- Macro test 3 k3_k4
port_mac => macro_sigc(3), -- Macro test 0 k1_k2Macro test 1 k1_k4Macro test 2 k3_k2Macro test 3 k3_k4
port_mac_c => macro_sig4_k3_k4 -- Macro test 3 k3_k4
);
-- End of Generated Instance Port Map for inst_k3_k4
-- Generated Instance Port Map for inst_ok_1
inst_ok_1: inst_ok_1_e
;
-- End of Generated Instance Port Map for inst_ok_1
-- Generated Instance Port Map for inst_ok_10
inst_ok_10: inst_ok_10_e
;
-- End of Generated Instance Port Map for inst_ok_10
-- Generated Instance Port Map for inst_ok_2
inst_ok_2: inst_ok_2_e
;
-- End of Generated Instance Port Map for inst_ok_2
-- Generated Instance Port Map for inst_ok_3
inst_ok_3: inst_ok_3_e
;
-- End of Generated Instance Port Map for inst_ok_3
-- Generated Instance Port Map for inst_ok_4
inst_ok_4: inst_ok_4_e
;
-- End of Generated Instance Port Map for inst_ok_4
-- Generated Instance Port Map for inst_ok_5
inst_ok_5: inst_ok_5_e
;
-- End of Generated Instance Port Map for inst_ok_5
-- Generated Instance Port Map for inst_ok_6
inst_ok_6: inst_ok_6_e
;
-- End of Generated Instance Port Map for inst_ok_6
-- Generated Instance Port Map for inst_ok_7
inst_ok_7: inst_ok_7_e
;
-- End of Generated Instance Port Map for inst_ok_7
-- Generated Instance Port Map for inst_ok_8
inst_ok_8: inst_ok_8_e
;
-- End of Generated Instance Port Map for inst_ok_8
-- Generated Instance Port Map for inst_ok_9
inst_ok_9: inst_ok_9_e
;
-- End of Generated Instance Port Map for inst_ok_9
-- Generated Instance Port Map for inst_shadow_1
inst_shadow_1: inst_shadow_1_e
;
-- End of Generated Instance Port Map for inst_shadow_1
-- Generated Instance Port Map for inst_shadow_10
inst_shadow_10: inst_shadow_10_e
;
-- End of Generated Instance Port Map for inst_shadow_10
-- Generated Instance Port Map for inst_shadow_2
inst_shadow_2: inst_shadow_2_e
;
-- End of Generated Instance Port Map for inst_shadow_2
-- Generated Instance Port Map for inst_shadow_3
inst_shadow_3: inst_shadow_3_e
;
-- End of Generated Instance Port Map for inst_shadow_3
-- Generated Instance Port Map for inst_shadow_4
inst_shadow_4: inst_shadow_4_e
;
-- End of Generated Instance Port Map for inst_shadow_4
-- Generated Instance Port Map for inst_shadow_5
inst_shadow_5: inst_shadow_5_e
;
-- End of Generated Instance Port Map for inst_shadow_5
-- Generated Instance Port Map for inst_shadow_6
inst_shadow_6: inst_shadow_6_e
;
-- End of Generated Instance Port Map for inst_shadow_6
-- Generated Instance Port Map for inst_shadow_7
inst_shadow_7: inst_shadow_7_e
;
-- End of Generated Instance Port Map for inst_shadow_7
-- Generated Instance Port Map for inst_shadow_8
inst_shadow_8: inst_shadow_8_e
;
-- End of Generated Instance Port Map for inst_shadow_8
-- Generated Instance Port Map for inst_shadow_9
inst_shadow_9: inst_shadow_9_e
;
-- End of Generated Instance Port Map for inst_shadow_9
-- Generated Instance Port Map for inst_shadow_a
inst_shadow_a: inst_shadow_a_e
;
-- End of Generated Instance Port Map for inst_shadow_a
-- Generated Instance Port Map for inst_shadow_b
inst_shadow_b: inst_shadow_b_e
;
-- End of Generated Instance Port Map for inst_shadow_b
-- Generated Instance Port Map for inst_shadow_k1_k2
inst_shadow_k1_k2: inst_shadow_k1_k2_e
;
-- End of Generated Instance Port Map for inst_shadow_k1_k2
-- Generated Instance Port Map for inst_shadow_k1_k4
inst_shadow_k1_k4: inst_shadow_k1_k4_e
;
-- End of Generated Instance Port Map for inst_shadow_k1_k4
-- Generated Instance Port Map for inst_shadow_k3_k2
inst_shadow_k3_k2: inst_shadow_k3_k2_e
;
-- End of Generated Instance Port Map for inst_shadow_k3_k2
-- Generated Instance Port Map for inst_shadow_k3_k4
inst_shadow_k3_k4: inst_shadow_k3_k4_e
;
-- End of Generated Instance Port Map for inst_shadow_k3_k4
-- Generated Instance Port Map for inst_shadow_ok_1
inst_shadow_ok_1: inst_shadow_ok_1_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_1
-- Generated Instance Port Map for inst_shadow_ok_10
inst_shadow_ok_10: inst_shadow_ok_10_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_10
-- Generated Instance Port Map for inst_shadow_ok_2
inst_shadow_ok_2: inst_shadow_ok_2_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_2
-- Generated Instance Port Map for inst_shadow_ok_3
inst_shadow_ok_3: inst_shadow_ok_3_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_3
-- Generated Instance Port Map for inst_shadow_ok_4
inst_shadow_ok_4: inst_shadow_ok_4_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_4
-- Generated Instance Port Map for inst_shadow_ok_5
inst_shadow_ok_5: inst_shadow_ok_5_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_5
-- Generated Instance Port Map for inst_shadow_ok_6
inst_shadow_ok_6: inst_shadow_ok_6_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_6
-- Generated Instance Port Map for inst_shadow_ok_7
inst_shadow_ok_7: inst_shadow_ok_7_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_7
-- Generated Instance Port Map for inst_shadow_ok_8
inst_shadow_ok_8: inst_shadow_ok_8_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_8
-- Generated Instance Port Map for inst_shadow_ok_9
inst_shadow_ok_9: inst_shadow_ok_9_e
;
-- End of Generated Instance Port Map for inst_shadow_ok_9
-- Generated Instance Port Map for inst_shadow_t
inst_shadow_t: inst_shadow_t_e
;
-- End of Generated Instance Port Map for inst_shadow_t
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
586297cb8c666a60795681e24113f8ff
| 0.655797 | 2.962631 | false | true | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_output_scalars_fifo.vhd
| 1 | 73,049 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_scalars_fifo.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
entity xd_output_scalars_fifo is
generic (
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
C_MTBF_STAGES : integer := 4;
WIDTH : integer := 16);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_clk : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_used : out std_logic_vector(3 downto 0); -- Additional bit needed
rd_empty : out std_logic;
rd_full : out std_logic;
rd_clk : in std_logic;
rst : in std_logic);
end xd_output_scalars_fifo;
architecture rtl of xd_output_scalars_fifo is
-- FIFO constants
constant DEPTH : integer := 15;
constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH)+1;
constant ADDR_BITS : integer := log2(FIFO_DEPTH);
constant INIT_NEXT_RD_GRAY : integer := 2**ADDR_BITS-1;
constant INIT_RD_GRAY : integer := 2**ADDR_BITS-2;
constant INIT_PREV_RD_GRAY : integer := 2**ADDR_BITS-3;
constant INIT_NEXT_WR_GRAY : integer := INIT_NEXT_RD_GRAY;
constant INIT_WR_GRAY : integer := INIT_RD_GRAY;
constant INIT_WR_GRAY_AHEAD : integer := 2**ADDR_BITS-0;
signal rst_vec : std_logic_vector(0 downto 0);
signal wr_rst_vec : std_logic_vector(0 downto 0);
signal rd_rst_vec : std_logic_vector(0 downto 0);
signal wr_rst : std_logic;
signal rd_rst : std_logic;
signal rd_addr : unsigned(ADDR_BITS-1 downto 0);
signal wr_addr : unsigned(ADDR_BITS-1 downto 0);
-- Next signals are gray values:
signal wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_gray_ahead : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal prev_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
--
signal fifo_we : std_logic;
signal fifo_re : std_logic;
--
signal din_rdy_i : std_logic;
signal empty_i : std_logic;
signal rd_en : std_logic;
signal dout_vld_i : std_logic;
signal dout_trf_ok : std_logic;
type mem_type is array (2**ADDR_BITS-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal mem : mem_type;
attribute ram_style : string;
attribute ram_style of mem : signal is "distributed";
signal mem_dout : std_logic_vector(WIDTH-1 downto 0);
--
signal wr_gray_sync : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_bin : unsigned(ADDR_BITS-1 downto 0);
signal wr_bin : unsigned(ADDR_BITS-1 downto 0);
signal ptr_dist : unsigned(ADDR_BITS-1 downto 0);
signal rd_used_i : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_full_i : std_logic;
signal empty : std_logic;
signal full : std_logic;
signal rstn : std_logic;
signal almost_full :std_logic;
signal wr_ack :std_logic;
signal overflow :std_logic;
signal almost_empty :std_logic;
signal valid :std_logic;
signal underflow :std_logic;
signal data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal prog_full :std_logic;
signal prog_empty :std_logic;
signal sbiterr :std_logic;
signal dbiterr :std_logic;
signal wr_rst_busy :std_logic;
signal rd_rst_busy :std_logic;
signal m_axi_awid :std_logic_vector(0 downto 0);
signal m_axi_awaddr :std_logic_vector(31 downto 0);
signal m_axi_awlen :std_logic_vector(7 downto 0);
signal m_axi_awsize :std_logic_vector(2 downto 0);
signal m_axi_awburst :std_logic_vector(1 downto 0);
signal m_axi_awlock :std_logic_vector(0 downto 0);
signal m_axi_awcache :std_logic_vector(3 downto 0);
signal m_axi_awprot :std_logic_vector(2 downto 0);
signal m_axi_awqos :std_logic_vector(3 downto 0);
signal m_axi_awregion :std_logic_vector(3 downto 0);
signal m_axi_awuser :std_logic_vector(0 downto 0);
signal m_axi_awvalid :std_logic;
signal m_axi_wid :std_logic_vector(0 downto 0);
signal m_axi_wdata :std_logic_vector(63 downto 0);
signal m_axi_wstrb :std_logic_vector(7 downto 0);
signal m_axi_wlast :std_logic;
signal m_axi_wuser :std_logic_vector(0 downto 0);
signal m_axi_wvalid :std_logic;
signal m_axi_bready :std_logic;
signal s_axi_awready :std_logic;
signal s_axi_wready :std_logic;
signal s_axi_bid :std_logic_vector(0 downto 0);
signal s_axi_bresp :std_logic_vector(1 downto 0);
signal s_axi_buser :std_logic_vector(0 downto 0);
signal m_axi_arid :std_logic_vector(0 downto 0);
signal m_axi_araddr :std_logic_vector(31 downto 0);
signal m_axi_arlen :std_logic_vector(7 downto 0);
signal m_axi_arsize :std_logic_vector(2 downto 0);
signal m_axi_arburst :std_logic_vector(1 downto 0);
signal m_axi_arlock :std_logic_vector(0 downto 0);
signal m_axi_arcache :std_logic_vector(3 downto 0);
signal m_axi_arprot :std_logic_vector(2 downto 0);
signal m_axi_arqos :std_logic_vector(3 downto 0);
signal m_axi_arregion :std_logic_vector(3 downto 0);
signal m_axi_aruser :std_logic_vector(0 downto 0);
signal m_axi_arvalid :std_logic;
signal m_axi_rready :std_logic;
signal s_axi_arready :std_logic;
signal s_axi_rid :std_logic_vector(0 downto 0);
signal s_axi_rdata :std_logic_vector(63 downto 0);
signal s_axi_rresp :std_logic_vector(1 downto 0);
signal s_axi_rlast :std_logic;
signal s_axi_ruser :std_logic_vector(0 downto 0);
signal m_axis_tvalid :std_logic;
signal m_axis_tdata :std_logic_vector(7 downto 0);
signal m_axis_tstrb :std_logic_vector(0 downto 0);
signal m_axis_tlast :std_logic;
signal m_axis_tkeep :std_logic_vector(0 downto 0);
signal m_axis_tid :std_logic_vector(0 downto 0);
signal m_axis_tdest :std_logic_vector(0 downto 0);
signal m_axis_tuser :std_logic_vector(3 downto 0);
signal s_axis_tready :std_logic;
signal axi_aw_data_count :std_logic_vector(4 downto 0);
signal axi_aw_wr_data_count :std_logic_vector(4 downto 0);
signal axi_aw_rd_data_count :std_logic_vector(4 downto 0);
signal axi_aw_sbiterr :std_logic;
signal axi_aw_dbiterr :std_logic;
signal axi_aw_overflow :std_logic;
signal axi_aw_underflow :std_logic;
signal axi_aw_prog_full :std_logic;
signal axi_aw_prog_empty :std_logic;
signal axi_w_data_count :std_logic_vector(10 downto 0);
signal axi_w_wr_data_count :std_logic_vector(10 downto 0);
signal axi_w_rd_data_count :std_logic_vector(10 downto 0);
signal axi_w_sbiterr :std_logic;
signal axi_w_dbiterr :std_logic;
signal axi_w_overflow :std_logic;
signal axi_w_underflow :std_logic;
signal axi_w_prog_full :std_logic;
signal axi_w_prog_empty :std_logic;
signal axi_b_data_count :std_logic_vector(4 downto 0);
signal axi_b_wr_data_count :std_logic_vector(4 downto 0);
signal axi_b_rd_data_count :std_logic_vector(4 downto 0);
signal axi_b_sbiterr :std_logic;
signal axi_b_dbiterr :std_logic;
signal axi_b_overflow :std_logic;
signal axi_b_underflow :std_logic;
signal axi_b_prog_full :std_logic;
signal axi_b_prog_empty :std_logic;
signal axi_ar_data_count :std_logic_vector(4 downto 0);
signal axi_ar_wr_data_count :std_logic_vector(4 downto 0);
signal axi_ar_rd_data_count :std_logic_vector(4 downto 0);
signal axi_ar_sbiterr :std_logic;
signal axi_ar_dbiterr :std_logic;
signal axi_ar_overflow :std_logic;
signal axi_ar_underflow :std_logic;
signal axi_ar_prog_full :std_logic;
signal axi_ar_prog_empty :std_logic;
signal axi_r_data_count :std_logic_vector(10 downto 0);
signal axi_r_wr_data_count :std_logic_vector(10 downto 0);
signal axi_r_rd_data_count :std_logic_vector(10 downto 0);
signal axi_r_sbiterr :std_logic;
signal axi_r_dbiterr :std_logic;
signal axi_r_overflow :std_logic;
signal axi_r_underflow :std_logic;
signal axi_r_prog_full :std_logic;
signal axi_r_prog_empty :std_logic;
signal axis_data_count :std_logic_vector(10 downto 0);
signal axis_wr_data_count :std_logic_vector(10 downto 0);
signal axis_rd_data_count :std_logic_vector(10 downto 0);
signal axis_sbiterr :std_logic;
signal axis_dbiterr :std_logic;
signal axis_overflow :std_logic;
signal axis_underflow :std_logic;
signal axis_prog_full :std_logic;
signal axis_prog_empty :std_logic;
constant C_EXTRA_SYNCS : integer := 5;
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rst)
begin
if(rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(INIT_NEXT_RD_GRAY, ADDR_BITS);
rd_gray <= bin2gray(INIT_RD_GRAY, ADDR_BITS);
prev_rd_gray <= bin2gray(INIT_PREV_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
next_wr_gray <= bin2gray(INIT_NEXT_WR_GRAY, ADDR_BITS);
wr_gray <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
-- process(wr_clk, rst)
-- begin
-- if(rst = '1') then
-- din_rdy_i <= '0';
-- elsif(wr_clk'event and wr_clk = '1') then
-- if(din_rdy_i = '1') then
-- if (wr_gray_ahead = prev_rd_gray) then
-- din_rdy_i <= not(fifo_we);
-- else
-- din_rdy_i <= '1';
-- end if;
-- else
-- if (wr_gray_ahead = rd_gray) then
-- din_rdy_i <= '0';
-- else
-- din_rdy_i <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
-- CR 741423 fix
-- If the oscalar_fifo_depth needs to be 16, din_rdy_i signal has to be validated on
-- next_wr_gray instead of wr_gray_ahead. wr_gray_ahead should be used
-- to keep the oscalar_fifo_depth equal to 15.
process(wr_clk, rst)
begin
if(rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (next_wr_gray = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (next_wr_gray = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rst)
begin
if(rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rst)
begin
if(rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
dout_trf_ok <= dout_vld_i and dout_rdy;
-----------------------------------------------------------------------
-- Memory bank modeling. Let's allow XST do it for us:
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rst)
begin
if(rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- wr_gray is synchronized with rd_clk to reduce metastability.
-- This inserts an extra rd_clk cycle latency
process(rd_clk, rst)
begin
if(rst = '1') then
wr_gray_sync <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
wr_gray_sync <= wr_gray;
end if;
end process;
wr_bin <= unsigned(gray2bin(wr_gray_sync));
process(rd_clk, rst)
begin
if(rst = '1') then
rd_bin <= to_unsigned(INIT_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
rd_bin <= rd_bin + 1;
end if;
end if;
end process;
process(rd_clk, rst)
begin
if(rst = '1') then
ptr_dist <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
ptr_dist <= ptr_dist - 1;
else
-- this is also valid at the end of count sequence:
-- wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
rd_used <= std_logic_vector(ptr_dist);
----
process(rd_clk, rst)
begin
if(rst = '1') then
rd_full_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
-- If there is a read, we exit inmediately the full state
if(dout_trf_ok = '1') then
rd_full_i <= '0';
else
-- Stay in full if next_wr_gray = rd_gray
if(next_wr_gray = rd_gray) then
rd_full_i <= '1';
else
rd_full_i <= '0';
end if;
end if;
end if;
end process;
rd_full <= rd_full_i;
rd_empty <= not(dout_vld_i);
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 2) generate
begin
rst_vec(0) <= rst;
wr_rst <= wr_rst_vec(0);
rd_rst <= rd_rst_vec(0);
wr_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => wr_clk,
D => rst_vec,
Q => wr_rst_vec
);
rd_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => rd_clk,
D => rst_vec,
Q => rd_rst_vec
);
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
next_rd_gray <= bin2gray(INIT_NEXT_RD_GRAY, ADDR_BITS);
rd_gray <= bin2gray(INIT_RD_GRAY, ADDR_BITS);
prev_rd_gray <= bin2gray(INIT_PREV_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
next_wr_gray <= bin2gray(INIT_NEXT_WR_GRAY, ADDR_BITS);
wr_gray <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
-- process(wr_clk, rst)
-- begin
-- if(rst = '1') then
-- din_rdy_i <= '0';
-- elsif(wr_clk'event and wr_clk = '1') then
-- if(din_rdy_i = '1') then
-- if (wr_gray_ahead = prev_rd_gray) then
-- din_rdy_i <= not(fifo_we);
-- else
-- din_rdy_i <= '1';
-- end if;
-- else
-- if (wr_gray_ahead = rd_gray) then
-- din_rdy_i <= '0';
-- else
-- din_rdy_i <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
-- CR 741423 fix
-- If the oscalar_fifo_depth needs to be 16, din_rdy_i signal has to be validated on
-- next_wr_gray instead of wr_gray_ahead. wr_gray_ahead should be used
-- to keep the oscalar_fifo_depth equal to 15.
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (next_wr_gray = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (next_wr_gray = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
dout_trf_ok <= dout_vld_i and dout_rdy;
-----------------------------------------------------------------------
-- Memory bank modeling. Let's allow XST do it for us:
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- wr_gray is synchronized with rd_clk to reduce metastability.
-- This inserts an extra rd_clk cycle latency
-- clkx_1: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
-- GENERIC MAP(
-- C_HAS_RST => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_MSGON_VAL => 1,
-- C_SYNCHRONIZER_STAGE => 2
-- )
-- PORT MAP(
-- WR_CLK => wr_clk,
-- RD_CLK => rd_clk,
-- WR_RST => wr_rst,
-- RD_RST => rd_rst,
-- WR_PNTR => wr_gray,
-- RD_PNTR => open,
-- WR_PNTR_RD => wr_gray_sync,
-- RD_PNTR_WR => open
-- );
-- process(rd_clk, rd_rst)
-- begin
-- if(rd_rst = '1') then
-- wr_gray_sync <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
-- elsif(rd_clk'event and rd_clk = '1') then
-- wr_gray_sync <= wr_gray;
-- end if;
-- end process;
wr_bin <= unsigned(gray2bin(wr_gray_sync));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_bin <= to_unsigned(INIT_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
rd_bin <= rd_bin + 1;
end if;
end if;
end process;
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
ptr_dist <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
ptr_dist <= ptr_dist - 1;
else
-- this is also valid at the end of count sequence:
-- wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
rd_used <= std_logic_vector(ptr_dist(3 downto 0));
----
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_full_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
-- If there is a read, we exit inmediately the full state
if(dout_trf_ok = '1') then
rd_full_i <= '0';
else
-- Stay in full if next_wr_gray = rd_gray
if(next_wr_gray = rd_gray) then
rd_full_i <= '1';
else
rd_full_i <= '0';
end if;
end if;
end if;
end process;
rd_full <= rd_full_i;
rd_empty <= not(dout_vld_i);
end generate NEW_INTRO;
NEW_INTRO2 : if (C_EXTRA_SYNCS = 1) generate
begin
din_rdy <= not(full);
dout_vld <= not(empty);
rd_empty <= (empty);
rd_full <= (full);
-- FIF_DMG_INST : entity fifo_generator_v12_0_5.fifo_generator_v12_0_5
-- GENERIC MAP (
-- C_COMMON_CLOCK => 0,
-- C_COUNT_TYPE => 0,
-- C_DATA_COUNT_WIDTH => ADDR_BITS,
-- C_DEFAULT_VALUE => "BlankString",
-- C_DIN_WIDTH => WIDTH,
-- C_DOUT_RST_VAL => "0",
-- C_DOUT_WIDTH => WIDTH,
-- C_ENABLE_RLOCS => 0,
-- C_FAMILY => C_FAMILY,
-- C_FULL_FLAGS_RST_VAL => 0,
-- C_HAS_ALMOST_EMPTY => 0,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_BACKUP => 0,
-- C_HAS_DATA_COUNT => 0,
-- C_HAS_INT_CLK => 0,
-- C_HAS_MEMINIT_FILE => 0,
-- C_HAS_OVERFLOW => 0,
-- C_HAS_RD_DATA_COUNT => 1,
-- C_HAS_RD_RST => 0,
-- C_HAS_RST => 1,
-- C_HAS_SRST => 0,
-- C_HAS_UNDERFLOW => 0,
-- C_HAS_VALID => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_DATA_COUNT => 0,
-- C_HAS_WR_RST => 0,
-- C_IMPLEMENTATION_TYPE => 2,
-- C_INIT_WR_PNTR_VAL => 0,
-- C_MEMORY_TYPE => 2,
-- C_MIF_FILE_NAME => "BlankString",
-- C_OPTIMIZATION_MODE => 0,
-- C_OVERFLOW_LOW => 0,
-- C_PRELOAD_LATENCY => 0,
-- C_PRELOAD_REGS => 1,
-- C_PRIM_FIFO_TYPE => "512x36",
-- C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
-- C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
-- C_PROG_EMPTY_TYPE => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL => 29,
-- C_PROG_FULL_THRESH_NEGATE_VAL => 28,
-- C_PROG_FULL_TYPE => 0,
-- C_RD_DATA_COUNT_WIDTH => 4,
-- C_RD_DEPTH => FIFO_DEPTH,
-- C_RD_FREQ => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_UNDERFLOW_LOW => 0,
-- C_USE_DOUT_RST => 1,
-- C_USE_ECC => 0,
-- C_USE_EMBEDDED_REG => 0,
-- C_USE_PIPELINE_REG => 0,
-- C_POWER_SAVING_MODE => 0,
-- C_USE_FIFO16_FLAGS => 0,
-- C_USE_FWFT_DATA_COUNT => 0,
-- C_VALID_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
-- C_WR_DEPTH => FIFO_DEPTH,
-- C_WR_FREQ => 1,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_WR_RESPONSE_LATENCY => 1,
-- C_MSGON_VAL => 1,
-- C_ENABLE_RST_SYNC => 1,
-- C_ERROR_INJECTION_TYPE => 0,
-- C_SYNCHRONIZER_STAGE => 2,
-- C_INTERFACE_TYPE => 0,
-- C_AXI_TYPE => 1,
-- C_HAS_AXI_WR_CHANNEL => 1,
-- C_HAS_AXI_RD_CHANNEL => 1,
-- C_HAS_SLAVE_CE => 0,
-- C_HAS_MASTER_CE => 0,
-- C_ADD_NGC_CONSTRAINT => 0,
-- C_USE_COMMON_OVERFLOW => 0,
-- C_USE_COMMON_UNDERFLOW => 0,
-- C_USE_DEFAULT_SETTINGS => 0,
-- C_AXI_ID_WIDTH => 1,
-- C_AXI_ADDR_WIDTH => 32,
-- C_AXI_DATA_WIDTH => 64,
-- C_AXI_LEN_WIDTH => 8,
-- C_AXI_LOCK_WIDTH => 1,
-- C_HAS_AXI_ID => 0,
-- C_HAS_AXI_AWUSER => 0,
-- C_HAS_AXI_WUSER => 0,
-- C_HAS_AXI_BUSER => 0,
-- C_HAS_AXI_ARUSER => 0,
-- C_HAS_AXI_RUSER => 0,
-- C_AXI_ARUSER_WIDTH => 1,
-- C_AXI_AWUSER_WIDTH => 1,
-- C_AXI_WUSER_WIDTH => 1,
-- C_AXI_BUSER_WIDTH => 1,
-- C_AXI_RUSER_WIDTH => 1,
-- C_HAS_AXIS_TDATA => 1,
-- C_HAS_AXIS_TID => 0,
-- C_HAS_AXIS_TDEST => 0,
-- C_HAS_AXIS_TUSER => 1,
-- C_HAS_AXIS_TREADY => 1,
-- C_HAS_AXIS_TLAST => 0,
-- C_HAS_AXIS_TSTRB => 0,
-- C_HAS_AXIS_TKEEP => 0,
-- C_AXIS_TDATA_WIDTH => WIDTH,
-- C_AXIS_TID_WIDTH => 1,
-- C_AXIS_TDEST_WIDTH => 1,
-- C_AXIS_TUSER_WIDTH => 4,
-- C_AXIS_TSTRB_WIDTH => 1,
-- C_AXIS_TKEEP_WIDTH => 1,
-- C_WACH_TYPE => 0,
-- C_WDCH_TYPE => 0,
-- C_WRCH_TYPE => 0,
-- C_RACH_TYPE => 0,
-- C_RDCH_TYPE => 0,
-- C_AXIS_TYPE => 0,
-- C_IMPLEMENTATION_TYPE_WACH => 1,
-- C_IMPLEMENTATION_TYPE_WDCH => 1,
-- C_IMPLEMENTATION_TYPE_WRCH => 1,
-- C_IMPLEMENTATION_TYPE_RACH => 1,
-- C_IMPLEMENTATION_TYPE_RDCH => 1,
-- C_IMPLEMENTATION_TYPE_AXIS => 1,
-- C_APPLICATION_TYPE_WACH => 0,
-- C_APPLICATION_TYPE_WDCH => 0,
-- C_APPLICATION_TYPE_WRCH => 0,
-- C_APPLICATION_TYPE_RACH => 0,
-- C_APPLICATION_TYPE_RDCH => 0,
-- C_APPLICATION_TYPE_AXIS => 0,
-- C_PRIM_FIFO_TYPE_WACH => "512x36",
-- C_PRIM_FIFO_TYPE_WDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_WRCH => "512x36",
-- C_PRIM_FIFO_TYPE_RACH => "512x36",
-- C_PRIM_FIFO_TYPE_RDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_AXIS => "1kx18",
-- C_USE_ECC_WACH => 0,
-- C_USE_ECC_WDCH => 0,
-- C_USE_ECC_WRCH => 0,
-- C_USE_ECC_RACH => 0,
-- C_USE_ECC_RDCH => 0,
-- C_USE_ECC_AXIS => 0,
-- C_ERROR_INJECTION_TYPE_WACH => 0,
-- C_ERROR_INJECTION_TYPE_WDCH => 0,
-- C_ERROR_INJECTION_TYPE_WRCH => 0,
-- C_ERROR_INJECTION_TYPE_RACH => 0,
-- C_ERROR_INJECTION_TYPE_RDCH => 0,
-- C_ERROR_INJECTION_TYPE_AXIS => 0,
-- C_DIN_WIDTH_WACH => 32,
-- C_DIN_WIDTH_WDCH => 64,
-- C_DIN_WIDTH_WRCH => 2,
-- C_DIN_WIDTH_RACH => 32,
-- C_DIN_WIDTH_RDCH => 64,
-- C_DIN_WIDTH_AXIS => 1,
-- C_WR_DEPTH_WACH => 16,
-- C_WR_DEPTH_WDCH => 1024,
-- C_WR_DEPTH_WRCH => 16,
-- C_WR_DEPTH_RACH => 16,
-- C_WR_DEPTH_RDCH => 1024,
-- C_WR_DEPTH_AXIS => 1024,
-- C_WR_PNTR_WIDTH_WACH => 4,
-- C_WR_PNTR_WIDTH_WDCH => 10,
-- C_WR_PNTR_WIDTH_WRCH => 4,
-- C_WR_PNTR_WIDTH_RACH => 4,
-- C_WR_PNTR_WIDTH_RDCH => 10,
-- C_WR_PNTR_WIDTH_AXIS => 10,
-- C_HAS_DATA_COUNTS_WACH => 0,
-- C_HAS_DATA_COUNTS_WDCH => 0,
-- C_HAS_DATA_COUNTS_WRCH => 0,
-- C_HAS_DATA_COUNTS_RACH => 0,
-- C_HAS_DATA_COUNTS_RDCH => 0,
-- C_HAS_DATA_COUNTS_AXIS => 0,
-- C_HAS_PROG_FLAGS_WACH => 0,
-- C_HAS_PROG_FLAGS_WDCH => 0,
-- C_HAS_PROG_FLAGS_WRCH => 0,
-- C_HAS_PROG_FLAGS_RACH => 0,
-- C_HAS_PROG_FLAGS_RDCH => 0,
-- C_HAS_PROG_FLAGS_AXIS => 0,
-- C_PROG_FULL_TYPE_WACH => 0,
-- C_PROG_FULL_TYPE_WDCH => 0,
-- C_PROG_FULL_TYPE_WRCH => 0,
-- C_PROG_FULL_TYPE_RACH => 0,
-- C_PROG_FULL_TYPE_RDCH => 0,
-- C_PROG_FULL_TYPE_AXIS => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
-- C_PROG_EMPTY_TYPE_WACH => 0,
-- C_PROG_EMPTY_TYPE_WDCH => 0,
-- C_PROG_EMPTY_TYPE_WRCH => 0,
-- C_PROG_EMPTY_TYPE_RACH => 0,
-- C_PROG_EMPTY_TYPE_RDCH => 0,
-- C_PROG_EMPTY_TYPE_AXIS => 0,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
-- C_REG_SLICE_MODE_WACH => 0,
-- C_REG_SLICE_MODE_WDCH => 0,
-- C_REG_SLICE_MODE_WRCH => 0,
-- C_REG_SLICE_MODE_RACH => 0,
-- C_REG_SLICE_MODE_RDCH => 0,
-- C_REG_SLICE_MODE_AXIS => 0
-- )
-- PORT MAP (
-- backup => '0',
-- backup_marker => '0',
-- clk => '0',
-- rst => rst,
-- srst => '0',
-- wr_clk => wr_clk,
-- rd_clk => rd_clk,
-- din => din,
-- wr_en => din_vld,
-- rd_en => dout_rdy,
-- prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- int_clk => '0',
-- injectdbiterr => '0',
-- injectsbiterr => '0',
-- sleep => '0',
-- dout => dout,
-- full => full,
-- empty => empty,
-- rd_data_count => rd_used,
-- m_aclk => '0',
-- s_aclk => '0',
-- s_aresetn => '0',
-- m_aclk_en => '0',
-- s_aclk_en => '0',
-- s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awvalid => '0',
-- s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_wlast => '0',
-- s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wvalid => '0',
-- s_axi_bready => '0',
-- m_axi_awready => '0',
-- m_axi_wready => '0',
-- m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bvalid => '0',
-- s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arvalid => '0',
-- s_axi_rready => '0',
-- m_axi_arready => '0',
-- m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_rlast => '0',
-- m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rvalid => '0',
-- s_axis_tvalid => '0',
-- s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tlast => '0',
-- s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- m_axis_tready => '0',
-- axi_aw_injectsbiterr => '0',
-- axi_aw_injectdbiterr => '0',
-- axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_w_injectsbiterr => '0',
-- axi_w_injectdbiterr => '0',
-- axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_b_injectsbiterr => '0',
-- axi_b_injectdbiterr => '0',
-- axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_ar_injectsbiterr => '0',
-- axi_ar_injectdbiterr => '0',
-- axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_r_injectsbiterr => '0',
-- axi_r_injectdbiterr => '0',
-- axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_injectsbiterr => '0',
-- axis_injectdbiterr => '0',
-- axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
-- );
end generate NEW_INTRO2;
NEW_INTRO3 : if (C_EXTRA_SYNCS = 5) generate
begin
rstn <= not(rst);
din_rdy <= not(full);
din_rdy_i <= not(full);
dout_vld <= not(empty);
rd_empty <= (empty);
rd_full <= (full);
-- din_rdy <= din_rdy_i;
-- dout_vld <= dout_vld_i;
-- rd_empty <= not(dout_vld_i);
-- rd_full <= not(din_rdy_i);
rd_used <= rd_used_i(3 downto 0);
FIF_DMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADDR_BITS,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => WIDTH,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 1,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADDR_BITS,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
C_WR_DEPTH => FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADDR_BITS,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 3,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => din_vld,
rd_en => dout_rdy,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => rd_used_i,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
-- COMP_FIFO : entity fifo_generator_v12_0_5.fifo_generator_v12_0_5
-- generic map (
-- C_COMMON_CLOCK => 0,
-- C_COUNT_TYPE => 0,
-- C_DATA_COUNT_WIDTH => 10,
-- C_DEFAULT_VALUE => "BlankString",
-- C_DIN_WIDTH => 18,
-- C_DOUT_RST_VAL => "0",
-- C_DOUT_WIDTH => 18,
-- C_ENABLE_RLOCS => 0,
-- C_FAMILY => C_FAMILY,
-- C_FULL_FLAGS_RST_VAL => 1,
-- C_HAS_ALMOST_EMPTY => 0,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_BACKUP => 0,
-- C_HAS_DATA_COUNT => 0,
-- C_HAS_INT_CLK => 0,
-- C_HAS_MEMINIT_FILE => 0,
-- C_HAS_OVERFLOW => 0,
-- C_HAS_RD_DATA_COUNT => 0,
-- C_HAS_RD_RST => 0,
-- C_HAS_RST => 1,
-- C_HAS_SRST => 0,
-- C_HAS_UNDERFLOW => 0,
-- C_HAS_VALID => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_DATA_COUNT => 0,
-- C_HAS_WR_RST => 0,
-- C_IMPLEMENTATION_TYPE => 0,
-- C_INIT_WR_PNTR_VAL => 0,
-- C_MEMORY_TYPE => 1,
-- C_MIF_FILE_NAME => "BlankString",
-- C_OPTIMIZATION_MODE => 0,
-- C_OVERFLOW_LOW => 0,
-- C_PRELOAD_LATENCY => 1,
-- C_PRELOAD_REGS => 0,
-- C_PRIM_FIFO_TYPE => "4kx4",
-- C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
-- C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
-- C_PROG_EMPTY_TYPE => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
-- C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
-- C_PROG_FULL_TYPE => 0,
-- C_RD_DATA_COUNT_WIDTH => 10,
-- C_RD_DEPTH => 16,
-- C_RD_FREQ => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_UNDERFLOW_LOW => 0,
-- C_USE_DOUT_RST => 1,
-- C_USE_ECC => 0,
-- C_USE_EMBEDDED_REG => 0,
-- C_USE_PIPELINE_REG => 0,
-- C_POWER_SAVING_MODE => 0,
-- C_USE_FIFO16_FLAGS => 0,
-- C_USE_FWFT_DATA_COUNT => 0,
-- C_VALID_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_DATA_COUNT_WIDTH => 10,
-- C_WR_DEPTH => 16,
-- C_WR_FREQ => 1,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_WR_RESPONSE_LATENCY => 1,
-- C_MSGON_VAL => 1,
-- C_ENABLE_RST_SYNC => 1,
-- C_ERROR_INJECTION_TYPE => 0,
-- C_SYNCHRONIZER_STAGE => 2,
-- C_INTERFACE_TYPE => 1,
-- C_AXI_TYPE => 1,
-- C_HAS_AXI_WR_CHANNEL => 1,
-- C_HAS_AXI_RD_CHANNEL => 1,
-- C_HAS_SLAVE_CE => 0,
-- C_HAS_MASTER_CE => 0,
-- C_ADD_NGC_CONSTRAINT => 0,
-- C_USE_COMMON_OVERFLOW => 0,
-- C_USE_COMMON_UNDERFLOW => 0,
-- C_USE_DEFAULT_SETTINGS => 0,
-- C_AXI_ID_WIDTH => 1,
-- C_AXI_ADDR_WIDTH => 32,
-- C_AXI_DATA_WIDTH => 64,
-- C_AXI_LEN_WIDTH => 8,
-- C_AXI_LOCK_WIDTH => 1,
-- C_HAS_AXI_ID => 0,
-- C_HAS_AXI_AWUSER => 0,
-- C_HAS_AXI_WUSER => 0,
-- C_HAS_AXI_BUSER => 0,
-- C_HAS_AXI_ARUSER => 0,
-- C_HAS_AXI_RUSER => 0,
-- C_AXI_ARUSER_WIDTH => 1,
-- C_AXI_AWUSER_WIDTH => 1,
-- C_AXI_WUSER_WIDTH => 1,
-- C_AXI_BUSER_WIDTH => 1,
-- C_AXI_RUSER_WIDTH => 1,
-- C_HAS_AXIS_TDATA => 0,
-- C_HAS_AXIS_TID => 0,
-- C_HAS_AXIS_TDEST => 0,
-- C_HAS_AXIS_TUSER => 0,
-- C_HAS_AXIS_TREADY => 1,
-- C_HAS_AXIS_TLAST => 1,
-- C_HAS_AXIS_TSTRB => 0,
-- C_HAS_AXIS_TKEEP => 0,
-- C_AXIS_TDATA_WIDTH => 1,
-- C_AXIS_TID_WIDTH => 1,
-- C_AXIS_TDEST_WIDTH => 1,
-- C_AXIS_TUSER_WIDTH => 1,
-- C_AXIS_TSTRB_WIDTH => 1,
-- C_AXIS_TKEEP_WIDTH => 1,
-- C_WACH_TYPE => 0,
-- C_WDCH_TYPE => 0,
-- C_WRCH_TYPE => 0,
-- C_RACH_TYPE => 0,
-- C_RDCH_TYPE => 0,
-- C_AXIS_TYPE => 0,
-- C_IMPLEMENTATION_TYPE_WACH => 12,
-- C_IMPLEMENTATION_TYPE_WDCH => 11,
-- C_IMPLEMENTATION_TYPE_WRCH => 12,
-- C_IMPLEMENTATION_TYPE_RACH => 12,
-- C_IMPLEMENTATION_TYPE_RDCH => 11,
-- C_IMPLEMENTATION_TYPE_AXIS => 11,
-- C_APPLICATION_TYPE_WACH => 0,
-- C_APPLICATION_TYPE_WDCH => 0,
-- C_APPLICATION_TYPE_WRCH => 0,
-- C_APPLICATION_TYPE_RACH => 0,
-- C_APPLICATION_TYPE_RDCH => 0,
-- C_APPLICATION_TYPE_AXIS => 1,
-- C_PRIM_FIFO_TYPE_WACH => "512x36",
-- C_PRIM_FIFO_TYPE_WDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_WRCH => "512x36",
-- C_PRIM_FIFO_TYPE_RACH => "512x36",
-- C_PRIM_FIFO_TYPE_RDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_AXIS => "512x36",
-- C_USE_ECC_WACH => 0,
-- C_USE_ECC_WDCH => 0,
-- C_USE_ECC_WRCH => 0,
-- C_USE_ECC_RACH => 0,
-- C_USE_ECC_RDCH => 0,
-- C_USE_ECC_AXIS => 0,
-- C_ERROR_INJECTION_TYPE_WACH => 0,
-- C_ERROR_INJECTION_TYPE_WDCH => 0,
-- C_ERROR_INJECTION_TYPE_WRCH => 0,
-- C_ERROR_INJECTION_TYPE_RACH => 0,
-- C_ERROR_INJECTION_TYPE_RDCH => 0,
-- C_ERROR_INJECTION_TYPE_AXIS => 0,
-- C_DIN_WIDTH_WACH => 32,
-- C_DIN_WIDTH_WDCH => 64,
-- C_DIN_WIDTH_WRCH => 2,
-- C_DIN_WIDTH_RACH => 32,
-- C_DIN_WIDTH_RDCH => 64,
-- C_DIN_WIDTH_AXIS => 1,
-- C_WR_DEPTH_WACH => 16,
-- C_WR_DEPTH_WDCH => 1024,
-- C_WR_DEPTH_WRCH => 16,
-- C_WR_DEPTH_RACH => 16,
-- C_WR_DEPTH_RDCH => 1024,
-- C_WR_DEPTH_AXIS => 16,
-- C_WR_PNTR_WIDTH_WACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_WDCH => 10,
-- C_WR_PNTR_WIDTH_WRCH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RDCH => 10,
-- C_WR_PNTR_WIDTH_AXIS => ADDR_BITS,
-- C_HAS_DATA_COUNTS_WACH => 0,
-- C_HAS_DATA_COUNTS_WDCH => 0,
-- C_HAS_DATA_COUNTS_WRCH => 0,
-- C_HAS_DATA_COUNTS_RACH => 0,
-- C_HAS_DATA_COUNTS_RDCH => 0,
-- C_HAS_DATA_COUNTS_AXIS => 3,
-- C_HAS_PROG_FLAGS_WACH => 0,
-- C_HAS_PROG_FLAGS_WDCH => 0,
-- C_HAS_PROG_FLAGS_WRCH => 0,
-- C_HAS_PROG_FLAGS_RACH => 0,
-- C_HAS_PROG_FLAGS_RDCH => 0,
-- C_HAS_PROG_FLAGS_AXIS => 0,
-- C_PROG_FULL_TYPE_WACH => 0,
-- C_PROG_FULL_TYPE_WDCH => 0,
-- C_PROG_FULL_TYPE_WRCH => 0,
-- C_PROG_FULL_TYPE_RACH => 0,
-- C_PROG_FULL_TYPE_RDCH => 0,
-- C_PROG_FULL_TYPE_AXIS => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 15,
-- C_PROG_EMPTY_TYPE_WACH => 0,
-- C_PROG_EMPTY_TYPE_WDCH => 0,
-- C_PROG_EMPTY_TYPE_WRCH => 0,
-- C_PROG_EMPTY_TYPE_RACH => 0,
-- C_PROG_EMPTY_TYPE_RDCH => 0,
-- C_PROG_EMPTY_TYPE_AXIS => 0,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 13,
-- C_REG_SLICE_MODE_WACH => 0,
-- C_REG_SLICE_MODE_WDCH => 0,
-- C_REG_SLICE_MODE_WRCH => 0,
-- C_REG_SLICE_MODE_RACH => 0,
-- C_REG_SLICE_MODE_RDCH => 0,
-- C_REG_SLICE_MODE_AXIS => 0
-- )
-- PORT MAP (
-- backup => '0',
-- backup_marker => '0',
-- clk => '0',
-- rst => '0',
-- srst => '0',
-- wr_clk => '0',
-- wr_rst => '0',
-- rd_clk => '0',
-- rd_rst => '0',
-- din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
-- wr_en => '0',
-- rd_en => '0',
-- prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- int_clk => '0',
-- injectdbiterr => '0',
-- injectsbiterr => '0',
-- sleep => '0',
-- m_aclk => rd_clk,
-- s_aclk => wr_clk,
-- s_aresetn => rstn,
-- m_aclk_en => '0',
-- s_aclk_en => '0',
-- s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awvalid => '0',
-- s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_wlast => '0',
-- s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wvalid => '0',
-- s_axi_bready => '0',
-- m_axi_awready => '0',
-- m_axi_wready => '0',
-- m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bvalid => '0',
-- s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arvalid => '0',
-- s_axi_rready => '0',
-- m_axi_arready => '0',
-- m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_rlast => '0',
-- m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rvalid => '0',
-- s_axis_tvalid => din_vld,
-- s_axis_tready => open,
-- s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- --s_axis_tdata => din,
-- s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tlast => '1',
-- s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axis_tvalid => open,
-- m_axis_tready => m_axis_tready,
-- m_axis_tlast => m_axis_tlast,
-- axi_aw_injectsbiterr => '0',
-- axi_aw_injectdbiterr => '0',
-- axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_w_injectsbiterr => '0',
-- axi_w_injectdbiterr => '0',
-- axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_b_injectsbiterr => '0',
-- axi_b_injectdbiterr => '0',
-- axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- axi_ar_injectsbiterr => '0',
-- axi_ar_injectdbiterr => '0',
-- axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_r_injectsbiterr => '0',
-- axi_r_injectdbiterr => '0',
-- axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_injectsbiterr => '0',
-- axis_injectdbiterr => '0',
-- axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_wr_data_count => rd_used_i,
-- axis_rd_data_count => open
-- );
end generate NEW_INTRO3;
end rtl;
|
mit
|
506427fccf62be5b658d1997c7c16903
| 0.506701 | 3.057339 | false | false | false | false |
mitchsm/nvc
|
test/regress/proc10.vhd
| 5 | 636 |
entity proc10 is
end entity;
architecture test of proc10 is
begin
process is
variable x : integer;
variable v : bit_vector(7 downto 0);
procedure change(b : bit) is
begin
v(x) := b;
end procedure;
procedure change_after(b : bit; t : time) is
begin
wait_here: wait for 1 ns;
change: v(x) := b;
end procedure;
begin
v := X"00";
x := 1;
change('1');
assert v = X"02";
x := 7;
change_after('1', 10 ns);
assert v = X"82";
wait;
end process;
end architecture;
|
gpl-3.0
|
4071129cd9174d7cf7136f4cdea52bf8
| 0.481132 | 3.831325 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_input_args_module.vhd
| 1 | 18,086 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_input_args_module.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_s2m_adapter;
use axis_accelerator_adapter_v2_1_6.xd_iarg_s2s_adapter;
entity xd_input_args_module is
generic (
-- System generics:
C_FAMILY : string; -- Xilinx FPGA family
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_MAX_ARG_DWIDTH : integer;
C_MAX_ARG_AWIDTH : integer;
C_MAX_ARG_N_DIM : integer;
C_MAX_MB_DEPTH : integer;
C_MAX_N_IARGS : integer;
C_N_INPUT_ARGS : integer;
C_S_AXIS_TDATA_WIDTH : integer;
C_S_AXIS_TUSER_WIDTH : integer;
C_S_AXIS_TID_WIDTH : integer;
C_S_AXIS_TDEST_WIDTH : integer;
C_AP_IARG_TYPE : std_logic_vector;
C_AP_IARG_DWIDTH : std_logic_vector;
C_AP_IARG_MB_DEPTH : std_logic_vector;
C_AP_IARG_WIDTH : std_logic_vector;
C_AP_IARG_N_DIM : std_logic_vector;
C_AP_IARG_DIM_1 : std_logic_vector;
C_AP_IARG_DIM_2 : std_logic_vector;
C_AP_IARG_FORMAT_TYPE : std_logic_vector;
C_AP_IARG_FORMAT_FACTOR : std_logic_vector;
C_AP_IARG_FORMAT_DIM : std_logic_vector;
C_MTBF_STAGES : integer;
C_EXTRA_SYNCS : integer;
C_NONE : integer := 2);
port (
--- Slave AXI streams (input arguments)
S_AXIS_ACLK : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_ARESETN : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TVALID : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TREADY : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TDATA : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector(C_MAX_N_IARGS*(C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TKEEP : in std_logic_vector(C_MAX_N_IARGS*(C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
S_AXIS_TID : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER : in std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TUSER_WIDTH-1 downto 0);
dbg_stream_nwords : out std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
dbg_buffer_nwords : out std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
dbg_ap_start : in std_logic;
--- AP input arguments
ap_clk : in std_logic;
ap_rst_saclk : in std_logic;
ap_rst : in std_logic;
ap_iarg_rst : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
ap_iarg_addr : in std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_AWIDTH-1 downto 0);
ap_iarg_ce : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
ap_iarg_we : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
ap_iarg_din : in std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_iarg_dout : out std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
mb_iarg_rdy : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
mb_iarg_done : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_empty : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_full : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_used : out std_logic_vector(C_MAX_N_IARGS*4-1 downto 0);
status_iarg_n_words : out std_logic_vector(C_MAX_N_IARGS*(C_MAX_ARG_AWIDTH+1)-1 downto 0);
ap_fifo_iarg_dout : out std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
ap_fifo_iarg_read : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
ap_fifo_iarg_empty_n : out std_logic_vector(C_MAX_N_IARGS-1 downto 0));
end entity;
architecture rtl of xd_input_args_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
constant C_S_AXIS_TSTRB_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
constant C_S_AXIS_TKEEP_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
signal s_aclk : std_logic;
signal ap_rst_sync1_saclk : std_logic;
signal ap_rst_sync_saclk : std_logic;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF ap_rst_sync_saclk : SIGNAL IS "true";
ATTRIBUTE async_reg OF ap_rst_sync1_saclk : SIGNAL IS "true";
begin
s_aclk <= S_AXIS_ACLK(0);
-- Unused signal
status_iarg_n_words <= (others => '0');
-- prd1: PROCESS (s_aclk)
-- BEGIN
-- -- Register Stage #1
-- IF (s_aclk'event and s_aclk = '1') THEN
-- ap_rst_sync1_saclk <= ap_rst;
-- ap_rst_sync_saclk <= ap_rst_sync1_saclk;
-- END IF;
-- END PROCESS prd1;
IARGS_GEN : if (C_N_INPUT_ARGS > 0) generate
begin
INPUT_ARGS_GEN : for i in 0 to C_N_INPUT_ARGS-1 generate
constant IARG_TYPE : integer := get_int_element(C_AP_IARG_TYPE, i);
constant IARG_DWIDTH : integer := get_int_element(C_AP_IARG_DWIDTH, i);
constant IARG_MB_DEPTH : integer := get_int_element(C_AP_IARG_MB_DEPTH, i);
constant IARG_WIDTH : integer := get_int_element(C_AP_IARG_WIDTH, i);
constant IARG_N_DIM : integer := get_int_element(C_AP_IARG_N_DIM, i);
constant IARG_DIM_1 : integer := get_int_element(C_AP_IARG_DIM_1, i);
constant IARG_DIM_2 : integer := get_int_element(C_AP_IARG_DIM_2, i);
constant IARG_FORMAT_TYPE : integer := get_int_element(C_AP_IARG_FORMAT_TYPE, i);
constant IARG_FORMAT_FACTOR : integer := get_int_element(C_AP_IARG_FORMAT_FACTOR, i);
constant IARG_FORMAT_DIM : integer := get_int_element(C_AP_IARG_FORMAT_DIM, i);
function calc_arg_addr_width return integer is
variable addr_width : integer := 10;
variable N_elements : integer;
begin
if (IARG_TYPE = AP_ARG_MEM_MAP_TYPE) then -- Memory map interface
if (IARG_N_DIM = 1) then
N_elements := IARG_DIM_1;
addr_width := log2(N_elements);
elsif (IARG_N_DIM = 2) then
if (IARG_FORMAT_TYPE = FORMAT_TYPE_RESHAPE_BLOCK) then
N_elements := (IARG_DIM_1*IARG_DIM_2)/IARG_FORMAT_FACTOR;
else
N_elements := (IARG_DIM_1*IARG_DIM_2);
end if;
addr_width := log2(N_elements);
end if;
elsif (IARG_TYPE = AP_ARG_STREAM_TYPE) then -- FIFO interface
N_elements := IARG_DIM_1;
addr_width := log2(N_elements);
end if;
return addr_width;
end function calc_arg_addr_width;
constant IARG_AWIDTH : integer := calc_arg_addr_width;
begin
-- BRAM Interface towards accelerator
S2M_GEN : if (IARG_TYPE = AP_ARG_MEM_MAP_TYPE) generate
begin
IARG_AP_S2M_I : entity axis_accelerator_adapter_v2_1_6.xd_s2m_adapter
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_BRAM_TYPE => C_BRAM_TYPE,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_TUSER_WIDTH,
C_S_AXIS_TID_WIDTH => C_S_AXIS_TID_WIDTH,
C_S_AXIS_TDEST_WIDTH => C_S_AXIS_TDEST_WIDTH,
C_AP_ARG_DATA_WIDTH => IARG_DWIDTH,
C_AP_ARG_ADDR_WIDTH => IARG_AWIDTH,
C_MULTIBUFFER_DEPTH => IARG_MB_DEPTH,
C_AP_ARG_WIDTH => IARG_WIDTH,
C_AP_ARG_N_DIM => IARG_N_DIM,
C_AP_ARG_DIM_1 => IARG_DIM_1,
C_AP_ARG_DIM_2 => IARG_DIM_2,
C_AP_ARG_FORMAT_TYPE => IARG_FORMAT_TYPE,
C_AP_ARG_FORMAT_FACTOR => IARG_FORMAT_FACTOR,
C_AP_ARG_FORMAT_DIM => IARG_FORMAT_DIM,
C_EXTRA_SYNCS => C_EXTRA_SYNCS)
port map (
S_AXIS_ACLK => S_AXIS_ACLK(i),
S_AXIS_ARESETN => S_AXIS_ARESETN(i),
S_AXIS_TVALID => S_AXIS_TVALID(i),
S_AXIS_TREADY => S_AXIS_TREADY(i),
S_AXIS_TDATA => S_AXIS_TDATA(C_S_AXIS_TDATA_WIDTH*(i+1)-1 downto C_S_AXIS_TDATA_WIDTH*i),
S_AXIS_TSTRB => S_AXIS_TSTRB(C_S_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_S_AXIS_TSTRB_WIDTH*i),
S_AXIS_TKEEP => S_AXIS_TKEEP(C_S_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_S_AXIS_TKEEP_WIDTH*i),
S_AXIS_TLAST => S_AXIS_TLAST(i),
S_AXIS_TID => S_AXIS_TID(C_S_AXIS_TID_WIDTH*(i+1)-1 downto C_S_AXIS_TID_WIDTH*i),
S_AXIS_TDEST => S_AXIS_TDEST(C_S_AXIS_TDEST_WIDTH*(i+1)-1 downto C_S_AXIS_TDEST_WIDTH*i),
S_AXIS_TUSER => S_AXIS_TUSER(C_S_AXIS_TUSER_WIDTH*(i+1)-1 downto C_S_AXIS_TUSER_WIDTH*i),
dbg_stream_nwords => dbg_stream_nwords(16*(i+1)-1 downto 16*i),
dbg_buffer_nwords => dbg_buffer_nwords(16*(i+1)-1 downto 16*i),
dbg_ap_start => dbg_ap_start,
ap_clk => ap_clk,
ap_rst_sync => ap_rst_saclk,
ap_rst => ap_rst,
ap_arg_addr => ap_iarg_addr(IARG_AWIDTH-1+C_MAX_ARG_AWIDTH*i downto C_MAX_ARG_AWIDTH*i),
ap_arg_ce => ap_iarg_ce(i),
ap_arg_we => ap_iarg_we(i),
ap_arg_din => ap_iarg_din(IARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_arg_dout => ap_iarg_dout(IARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
mb_arg_rdy => mb_iarg_rdy(i),
mb_arg_done => mb_iarg_done(i),
-- Status info
status_empty => status_iarg_empty(i),
status_full => status_iarg_full(i),
status_used => status_iarg_used(4*(i+1)-1 downto 4*i));
-- Unused signals
ap_fifo_iarg_dout(IARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
ap_fifo_iarg_empty_n(i) <= '0';
end generate S2M_GEN;
-- FIFO Interface towards accelerator
S2S_GEN : if (IARG_TYPE = AP_ARG_STREAM_TYPE) generate
begin
IARG_AP_S2S_I : entity axis_accelerator_adapter_v2_1_6.xd_iarg_s2s_adapter
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_TUSER_WIDTH,
C_S_AXIS_TID_WIDTH => C_S_AXIS_TID_WIDTH,
C_S_AXIS_TDEST_WIDTH => C_S_AXIS_TDEST_WIDTH,
C_AP_ARG_DATA_WIDTH => IARG_DWIDTH,
C_AP_ARG_ADDR_WIDTH => IARG_AWIDTH,
C_MULTIBUFFER_DEPTH => IARG_MB_DEPTH)
port map (
S_AXIS_ACLK => S_AXIS_ACLK(i),
S_AXIS_ARESETN => S_AXIS_ARESETN(i),
S_AXIS_TVALID => S_AXIS_TVALID(i),
S_AXIS_TREADY => S_AXIS_TREADY(i),
S_AXIS_TDATA => S_AXIS_TDATA(C_S_AXIS_TDATA_WIDTH*(i+1)-1 downto C_S_AXIS_TDATA_WIDTH*i),
S_AXIS_TSTRB => S_AXIS_TSTRB(C_S_AXIS_TSTRB_WIDTH*(i+1)-1 downto C_S_AXIS_TSTRB_WIDTH*i),
S_AXIS_TKEEP => S_AXIS_TKEEP(C_S_AXIS_TKEEP_WIDTH*(i+1)-1 downto C_S_AXIS_TKEEP_WIDTH*i),
S_AXIS_TLAST => S_AXIS_TLAST(i),
S_AXIS_TID => S_AXIS_TID(C_S_AXIS_TID_WIDTH*(i+1)-1 downto C_S_AXIS_TID_WIDTH*i),
S_AXIS_TDEST => S_AXIS_TDEST(C_S_AXIS_TDEST_WIDTH*(i+1)-1 downto C_S_AXIS_TDEST_WIDTH*i),
S_AXIS_TUSER => S_AXIS_TUSER(C_S_AXIS_TUSER_WIDTH*(i+1)-1 downto C_S_AXIS_TUSER_WIDTH*i),
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_iarg_dout => ap_fifo_iarg_dout(IARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i),
ap_iarg_re => ap_fifo_iarg_read(i),
ap_iarg_empty_n => ap_fifo_iarg_empty_n(i),
mb_arg_rdy => mb_iarg_rdy(i),
mb_arg_done => mb_iarg_done(i));
-- Unused signals
status_iarg_empty(i) <= '1';
status_iarg_full(i) <= '0';
status_iarg_used(4*(i+1)-1 downto 4*i) <=(others => '0');
ap_iarg_dout(IARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
dbg_stream_nwords(16*(i+1)-1 downto 16*i) <= (others => '0');
dbg_buffer_nwords(16*(i+1)-1 downto 16*i) <= (others => '0');
end generate S2S_GEN;
ap_iarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto IARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
ap_fifo_iarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto IARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
end generate INPUT_ARGS_GEN;
IARGS_DEFAULT_GEN : if (C_N_INPUT_ARGS < C_MAX_N_IARGS) generate
constant IARG_DWIDTH : integer := get_int_element(C_AP_IARG_DWIDTH, C_N_INPUT_ARGS-1);
begin
INPUT_ARGS_HIGHER_GEN : for i in C_N_INPUT_ARGS to C_MAX_N_IARGS-1 generate
constant IARG_DWIDTH : integer := get_int_element(C_AP_IARG_DWIDTH, C_N_INPUT_ARGS-1);
begin
S_AXIS_TREADY(i) <= '0';
mb_iarg_rdy(i) <= '0';
ap_fifo_iarg_empty_n(i) <= '0';
status_iarg_empty(i) <= '0';
status_iarg_full(i) <= '0';
status_iarg_used(4*(i+1)-1 downto 4*i) <=(others => '0');
dbg_stream_nwords(16*(i+1)-1 downto 16*i) <= (others => '0');
dbg_buffer_nwords(16*(i+1)-1 downto 16*i) <= (others => '0');
ap_fifo_iarg_dout(IARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
ap_iarg_dout(IARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto C_MAX_ARG_DWIDTH*i) <= (others => '0');
ap_iarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto IARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
ap_fifo_iarg_dout(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*i downto IARG_DWIDTH+C_MAX_ARG_DWIDTH*i)<= (others => '0');
end generate INPUT_ARGS_HIGHER_GEN;
--ap_iarg_dout(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto C_MAX_ARG_DWIDTH*C_N_INPUT_ARGS) <= (others=>'0');
end generate IARGS_DEFAULT_GEN;
end generate IARGS_GEN;
end rtl;
|
mit
|
b3087e6267e9244919318c6c50445d68
| 0.561816 | 3.211863 | false | false | false | false |
mitchsm/nvc
|
test/sem/protected.vhd
| 3 | 3,698 |
entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_here); -- Error
end protected;
type bad1 is protected body
end protected body;
type bad2 is protected body -- Error
end protected body;
type integer is protected body -- Error
end protected body;
type now is protected body -- Error
end protected body;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
type SharedCounter is protected body -- Error
end protected body;
subtype s is SharedCounter; -- Error
shared variable x : integer; -- Error
shared variable y : SharedCounter; -- OK
shared variable y : SharedCounter := 1; -- Error
function make return SharedCounter is
variable result : SharedCounter;
begin
return result;
end function;
procedure proc(variable sh : in SharedCounter := make) is -- error
begin
end procedure;
begin
end architecture;
architecture a2 of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
procedure foo (x : in integer);
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure bar (x : in integer ) is
begin
null;
end procedure;
procedure foo (x : in integer ) is
begin
bar(x + 1);
end procedure;
end protected body;
shared variable x : SharedCounter; -- OK
begin
process is
begin
x.increment(2); -- OK
x.increment; -- OK
x.counter := 5; -- Error
x.decrement(1, 2); -- Error
assert x.value = 5; -- OK
end process;
process is
function get_value (x : in sharedcounter ) return integer is -- Error
begin
return x.value;
end function;
begin
end process;
bad_assignment: process
variable y : SharedCounter;
variable z : SharedCounter;
begin
y := z; -- Error
wait;
end process;
end architecture;
package issue85 is
type protected_t is protected
procedure add(argument : inout protected_t); -- OK
end protected protected_t;
end package;
package pkg is
type protected_t is protected
end protected protected_t;
end package;
package body pkg is
-- Missing body for protected_t
end package body;
|
gpl-3.0
|
d1c3a1633cdc5b219fc62b0abe2fc2db
| 0.581666 | 4.997297 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_m2s_converter.vhd
| 1 | 12,040 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_m2s_converter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-07-31 2.0 pvk Updated Tvalid generattion logic to remove stream
-- protocol error where tvalid was deasserting
-- tlast
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
entity xd_m2s_converter is
generic (
-- System generics:
C_FAMILY : string; -- Xilinx FPGA family
SIZE_WIDTH : integer;
AXI_DATA_WIDTH : integer;
AXI_ADDR_WIDTH : integer;
AXI_USER_WIDTH : integer;
AXI_ID_WIDTH : integer;
AXI_DEST_WIDTH : integer);
port (
axi_clk : in std_logic;
axi_rst : in std_logic;
axis_vld : out std_logic;
axis_rdy : in std_logic;
axis_data : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
axis_keep : out std_logic_vector((AXI_DATA_WIDTH/8)-1 downto 0);
axis_strb : out std_logic_vector((AXI_DATA_WIDTH/8)-1 downto 0);
axis_last : out std_logic;
axis_id : out std_logic_vector(AXI_ID_WIDTH-1 downto 0);
axis_dest : out std_logic_vector(AXI_DEST_WIDTH-1 downto 0);
axis_user : out std_logic_vector(AXI_USER_WIDTH-1 downto 0);
conv_size : in std_logic_vector(SIZE_WIDTH-1 downto 0);
conv_addr : out std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
conv_ce : out std_logic;
conv_we : out std_logic;
conv_last : out std_logic;
conv_rdy : in std_logic;
conv_data : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
host_oarg_tdest : in std_logic_vector(AXI_DEST_WIDTH-1 downto 0));
end entity;
architecture rtl of xd_m2s_converter is
constant STRB_WIDTH : integer := AXI_DATA_WIDTH/8;
type state_type is (
idle,
running, wait_last);
signal state : state_type;
constant SUBWORD_WIDTH : integer := log2(AXI_DATA_WIDTH/8);
constant WORD_CNT_WIDTH : integer := SIZE_WIDTH - SUBWORD_WIDTH;
constant WORD_CNT_LSB : integer := SUBWORD_WIDTH;
constant WORD_CNT_MSB : integer := SIZE_WIDTH-1;
signal word_cnt : unsigned(WORD_CNT_WIDTH-1 downto 0);
signal init_cnt : std_logic;
signal word_cnt_0 : std_logic;
signal word_cnt_1 : std_logic;
signal full_last_word : std_logic;
signal last_word : std_logic;
signal last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
--
signal conv_addr_i : unsigned(AXI_ADDR_WIDTH-1 downto 0);
signal conv_ce_i : std_logic;
signal conv_data_vld : std_logic;
signal conv_data_last : std_logic;
signal conv_data_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal fill_pipe : std_logic;
--
signal dout_vld : std_logic;
signal dout_last : std_logic;
signal dout_rdy : std_logic;
signal dout : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
signal dout_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
begin
-- Each time we send a stream out, we initialize to zero its buffer
conv_we <= '0';
-- count the words to read:
process(axi_clk)
variable aux : unsigned(WORD_CNT_WIDTH-1 downto 0);
begin
if(axi_clk'event and axi_clk = '1') then
if(init_cnt = '1') then
aux := unsigned(conv_size(WORD_CNT_MSB downto WORD_CNT_LSB));
word_cnt <= aux;
word_cnt_0 <= '0';
word_cnt_1 <= '0';
if(aux(WORD_CNT_WIDTH-1 downto 1) = 0) then
word_cnt_1 <= aux(0);
word_cnt_0 <= not(aux(0));
end if;
elsif(conv_ce_i = '1') then
word_cnt <= word_cnt - 1;
if(word_cnt = 2) then
word_cnt_1 <= '1';
else
word_cnt_1 <= '0';
end if;
word_cnt_0 <= word_cnt_1;
end if;
end if;
end process;
-- Address to access:
process(axi_clk)
variable aux : unsigned(WORD_CNT_WIDTH-1 downto 0);
begin
if(axi_clk'event and axi_clk = '1') then
if(init_cnt = '1') then
conv_addr_i <= (others => '0');
elsif(conv_ce_i = '1') then
conv_addr_i <= conv_addr_i + 1;
end if;
end if;
end process;
conv_addr <= std_logic_vector(conv_addr_i);
-- Last read; although last_strb seems complex, each bit generated should be
-- a simple LUT with 3 inputs (SUBWORD_WIDTH = 3)
process(axi_clk)
constant zeros : std_logic_vector(SUBWORD_WIDTH-1 downto 0) := (others => '0');
variable aux : integer range 0 to (2**SUBWORD_WIDTH)-1;
begin
if(axi_clk'event and axi_clk = '1') then
if(init_cnt = '1') then
aux := to_integer(unsigned(conv_size(SUBWORD_WIDTH-1 downto 0)));
if(aux = 0) then
full_last_word <= '1';
last_strb <= (others => '1');
else
full_last_word <= '0';
last_strb <= std_logic_vector(to_unsigned(2**aux-1, STRB_WIDTH));
end if;
end if;
end if;
end process;
last_word <= word_cnt_1 when (full_last_word = '1') else word_cnt_0;
-- This module behaves like a two-stage pipeline
-- first stage is BRAM outputs (from multibuffer)
-- second stage is te registered output of the module
-- TAP 1: BRAM output
process(axi_clk)
begin
if (axi_clk'event and axi_clk = '1') then
if (axi_rst = '1') then
conv_data_vld <= '0';
conv_data_last <= '0';
conv_data_strb <= (others => '0');
elsif(conv_data_vld = '0' or dout_vld = '0' or (dout_vld and dout_rdy) = '1') then
-- this tage happens if any of the following conditions:
-- 1.- stage is empty => refresh continous of the input values to the stage
-- 2.- next stage is empty => data in this stage move to next stage
-- 3.- pipeline moves => consumed data in last stage
conv_data_vld <= conv_ce_i;
conv_data_last <= last_word;
if(last_word = '1') then
conv_data_strb <= last_strb;
else
conv_data_strb <= (others => '1');
end if;
end if;
end if;
end process;
-- TAP 2: Output register.
process(axi_clk)
begin
if (axi_clk'event and axi_clk = '1') then
if (axi_rst = '1') then
dout_vld <= '0';
elsif(dout_vld = '0' or (dout_vld and dout_rdy) = '1') then
dout_vld <= conv_data_vld;
end if;
end if;
end process;
process(axi_clk)
begin
if (axi_clk'event and axi_clk = '1') then
if(dout_vld = '0' or (dout_vld and dout_rdy) = '1') then
dout <= conv_data;
dout_last <= conv_data_last;
dout_strb <= conv_data_strb;
end if;
end if;
end process;
-- Control of reads during filling the pipe:
process(axi_clk)
begin
if (axi_clk'event and axi_clk = '1') then
if (axi_rst = '1') then
fill_pipe <= '0';
else
if(dout_vld = '1') then -- last stage is busy
-- Stop if first stage is full or about to be filled (new data coming)
fill_pipe <= not(conv_data_vld or conv_ce_i);
elsif(conv_data_vld = '1') then -- second to last stage busy
-- if new data coming, stop reads
fill_pipe <= not(conv_ce_i);
else -- pipe is empty
fill_pipe <= '1';
end if;
end if;
end if;
end process;
-- FSM:
process(axi_clk, axi_rst)
begin
if(axi_rst = '1') then
state <= idle;
elsif(axi_clk'event and axi_clk = '1') then
case state is
when idle =>
if(conv_rdy = '1') then
state <= running;
end if;
when running =>
if(last_word = '1' and conv_ce_i = '1') then
--state <= idle;
state <= wait_last;
end if;
when wait_last =>
if(dout_last = '1' and axis_rdy = '1') then
state <= idle;
end if;
when others =>
end case;
end if;
end process;
process(state, conv_rdy, last_word, dout_vld, dout_rdy, fill_pipe)
begin
init_cnt <= '0';
conv_last <= '0';
conv_ce_i <= '0';
case state is
when idle =>
-- init_cnt <= conv_rdy;
init_cnt <= '1';
when running =>
conv_ce_i <= (dout_vld and dout_rdy) or fill_pipe;
conv_last <= last_word and ((dout_vld and dout_rdy) or fill_pipe);
when others =>
end case;
end process;
conv_ce <= conv_ce_i;
axis_vld <= dout_vld;
dout_rdy <= axis_rdy;
axis_data <= dout;
axis_keep <= dout_strb;
axis_strb <= dout_strb;
axis_last <= dout_last;
axis_id <= (others => '0');
axis_dest <= host_oarg_tdest;
axis_user <= (others => '0');
end rtl;
|
mit
|
8b6df03c33ac00ca27792762abe64eb7
| 0.565864 | 3.660687 | false | false | false | false |
praveendath92/securePUF
|
ipcore_dir/RMEM/simulation/RMEM_tb.vhd
| 1 | 4,298 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: RMEM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY RMEM_tb IS
END ENTITY;
ARCHITECTURE RMEM_tb_ARCH OF RMEM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
RMEM_synth_inst:ENTITY work.RMEM_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-2.0
|
44cab1b6d39c13329b5fe57ec94f7892
| 0.618427 | 4.676823 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_counter2.vhd
| 2 | 4,645 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter2.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter2 IS
PORT
(
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_counter2;
ARCHITECTURE SYN OF lpm_counter2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 525,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 10
)
PORT MAP (
clock => clock,
cnt_en => cnt_en,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "525"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "525"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
9374bd72b088263c4f78d48ef345f508
| 0.650807 | 3.617601 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab22.vhd
| 5 | 1,046 |
entity sub is
port (
i : in bit_vector(0 to 7);
o : out bit_vector(0 to 7) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab22 is
end entity;
architecture test of elab22 is
signal a : bit_vector(0 to 1);
signal b : bit_vector(0 to 5);
signal c : bit_vector(2 to 5);
signal d : bit_vector(0 to 3);
begin
sub_i: entity work.sub
port map (
i(0 to 1) => a,
i(2 to 7) => b,
o(0 to 3) => c,
o(4 to 7) => d );
process is
begin
assert c = "0000";
assert d = "0000";
wait for 2 ns;
assert c = "1111";
assert d = "1111";
a <= "11";
wait for 2 ns;
assert c = "0011";
assert d = "1111";
b <= "011110";
wait for 2 ns;
assert c = "0010";
assert d = "0001";
wait;
end process;
end architecture;
|
gpl-3.0
|
1fc8b9e079d9b80c33c064c50c440ea6
| 0.445507 | 3.644599 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/vhls/get/solution/syn/vhdl/get.vhd
| 4 | 28,259 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity get is
generic (
C_M_AXI_GMEM_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_ID_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_DATA_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_BUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_USER_VALUE : INTEGER := 0;
C_M_AXI_GMEM_CACHE_VALUE : INTEGER := 3;
C_M_AXI_GMEM_PROT_VALUE : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_gmem_AWVALID : OUT STD_LOGIC;
m_axi_gmem_AWREADY : IN STD_LOGIC;
m_axi_gmem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_AWUSER_WIDTH-1 downto 0);
m_axi_gmem_WVALID : OUT STD_LOGIC;
m_axi_gmem_WREADY : IN STD_LOGIC;
m_axi_gmem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH/8-1 downto 0);
m_axi_gmem_WLAST : OUT STD_LOGIC;
m_axi_gmem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_WUSER_WIDTH-1 downto 0);
m_axi_gmem_ARVALID : OUT STD_LOGIC;
m_axi_gmem_ARREADY : IN STD_LOGIC;
m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ARUSER_WIDTH-1 downto 0);
m_axi_gmem_RVALID : IN STD_LOGIC;
m_axi_gmem_RREADY : OUT STD_LOGIC;
m_axi_gmem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_RLAST : IN STD_LOGIC;
m_axi_gmem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_RUSER_WIDTH-1 downto 0);
m_axi_gmem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BVALID : IN STD_LOGIC;
m_axi_gmem_BREADY : OUT STD_LOGIC;
m_axi_gmem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_BUSER_WIDTH-1 downto 0);
data : IN STD_LOGIC_VECTOR (31 downto 0);
key : IN STD_LOGIC_VECTOR (31 downto 0);
val_r : OUT STD_LOGIC_VECTOR (31 downto 0);
val_r_ap_vld : OUT STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of get is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"get,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.500000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.437500,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=590,HLS_SYN_LUT=738}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (8 downto 0) := "000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (8 downto 0) := "001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (8 downto 0) := "010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_27 : BOOLEAN;
signal gmem_AWVALID : STD_LOGIC;
signal gmem_AWREADY : STD_LOGIC;
signal gmem_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WVALID : STD_LOGIC;
signal gmem_WREADY : STD_LOGIC;
signal gmem_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_WLAST : STD_LOGIC;
signal gmem_WID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARVALID : STD_LOGIC;
signal gmem_ARREADY : STD_LOGIC;
signal gmem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RVALID : STD_LOGIC;
signal gmem_RREADY : STD_LOGIC;
signal gmem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_RLAST : STD_LOGIC;
signal gmem_RID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BVALID : STD_LOGIC;
signal gmem_BREADY : STD_LOGIC;
signal gmem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal get_gmem_m_axi_U_ap_dummy_ce : STD_LOGIC;
signal gmem_addr_reg_110 : STD_LOGIC_VECTOR (31 downto 0);
signal data2_sum_cast_fu_100_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_reg_ioackin_gmem_ARREADY : STD_LOGIC := '0';
signal ap_sig_ioackin_gmem_ARREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_182 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_201 : BOOLEAN;
signal tmp_fu_76_p4 : STD_LOGIC_VECTOR (29 downto 0);
signal tmp_cast_fu_90_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_1_cast_fu_86_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal data2_sum_fu_94_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0);
component get_gmem_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
get_gmem_m_axi_U : component get_gmem_m_axi
generic map (
USER_DW => 32,
USER_AW => 32,
USER_MAXREQS => 5,
C_M_AXI_ID_WIDTH => C_M_AXI_GMEM_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_GMEM_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_GMEM_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_GMEM_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_GMEM_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_GMEM_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_GMEM_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_GMEM_BUSER_WIDTH,
C_USER_VALUE => C_M_AXI_GMEM_USER_VALUE,
C_PROT_VALUE => C_M_AXI_GMEM_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_GMEM_CACHE_VALUE)
port map (
AWVALID => m_axi_gmem_AWVALID,
AWREADY => m_axi_gmem_AWREADY,
AWADDR => m_axi_gmem_AWADDR,
AWID => m_axi_gmem_AWID,
AWLEN => m_axi_gmem_AWLEN,
AWSIZE => m_axi_gmem_AWSIZE,
AWBURST => m_axi_gmem_AWBURST,
AWLOCK => m_axi_gmem_AWLOCK,
AWCACHE => m_axi_gmem_AWCACHE,
AWPROT => m_axi_gmem_AWPROT,
AWQOS => m_axi_gmem_AWQOS,
AWREGION => m_axi_gmem_AWREGION,
AWUSER => m_axi_gmem_AWUSER,
WVALID => m_axi_gmem_WVALID,
WREADY => m_axi_gmem_WREADY,
WDATA => m_axi_gmem_WDATA,
WSTRB => m_axi_gmem_WSTRB,
WLAST => m_axi_gmem_WLAST,
WID => m_axi_gmem_WID,
WUSER => m_axi_gmem_WUSER,
ARVALID => m_axi_gmem_ARVALID,
ARREADY => m_axi_gmem_ARREADY,
ARADDR => m_axi_gmem_ARADDR,
ARID => m_axi_gmem_ARID,
ARLEN => m_axi_gmem_ARLEN,
ARSIZE => m_axi_gmem_ARSIZE,
ARBURST => m_axi_gmem_ARBURST,
ARLOCK => m_axi_gmem_ARLOCK,
ARCACHE => m_axi_gmem_ARCACHE,
ARPROT => m_axi_gmem_ARPROT,
ARQOS => m_axi_gmem_ARQOS,
ARREGION => m_axi_gmem_ARREGION,
ARUSER => m_axi_gmem_ARUSER,
RVALID => m_axi_gmem_RVALID,
RREADY => m_axi_gmem_RREADY,
RDATA => m_axi_gmem_RDATA,
RLAST => m_axi_gmem_RLAST,
RID => m_axi_gmem_RID,
RUSER => m_axi_gmem_RUSER,
RRESP => m_axi_gmem_RRESP,
BVALID => m_axi_gmem_BVALID,
BREADY => m_axi_gmem_BREADY,
BRESP => m_axi_gmem_BRESP,
BID => m_axi_gmem_BID,
BUSER => m_axi_gmem_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => get_gmem_m_axi_U_ap_dummy_ce,
I_ARVALID => gmem_ARVALID,
I_ARREADY => gmem_ARREADY,
I_ARADDR => gmem_ARADDR,
I_ARID => gmem_ARID,
I_ARLEN => gmem_ARLEN,
I_ARSIZE => gmem_ARSIZE,
I_ARLOCK => gmem_ARLOCK,
I_ARCACHE => gmem_ARCACHE,
I_ARQOS => gmem_ARQOS,
I_ARPROT => gmem_ARPROT,
I_ARUSER => gmem_ARUSER,
I_ARBURST => gmem_ARBURST,
I_ARREGION => gmem_ARREGION,
I_RVALID => gmem_RVALID,
I_RREADY => gmem_RREADY,
I_RDATA => gmem_RDATA,
I_RID => gmem_RID,
I_RUSER => gmem_RUSER,
I_RRESP => gmem_RRESP,
I_RLAST => gmem_RLAST,
I_AWVALID => gmem_AWVALID,
I_AWREADY => gmem_AWREADY,
I_AWADDR => gmem_AWADDR,
I_AWID => gmem_AWID,
I_AWLEN => gmem_AWLEN,
I_AWSIZE => gmem_AWSIZE,
I_AWLOCK => gmem_AWLOCK,
I_AWCACHE => gmem_AWCACHE,
I_AWQOS => gmem_AWQOS,
I_AWPROT => gmem_AWPROT,
I_AWUSER => gmem_AWUSER,
I_AWBURST => gmem_AWBURST,
I_AWREGION => gmem_AWREGION,
I_WVALID => gmem_WVALID,
I_WREADY => gmem_WREADY,
I_WDATA => gmem_WDATA,
I_WID => gmem_WID,
I_WUSER => gmem_WUSER,
I_WLAST => gmem_WLAST,
I_WSTRB => gmem_WSTRB,
I_BVALID => gmem_BVALID,
I_BREADY => gmem_BREADY,
I_BRESP => gmem_BRESP,
I_BID => gmem_BID,
I_BUSER => gmem_BUSER);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_gmem_ARREADY assign process. --
ap_reg_ioackin_gmem_ARREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_gmem_ARREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_gmem_ARREADY))) then
ap_reg_ioackin_gmem_ARREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = gmem_ARREADY)) then
ap_reg_ioackin_gmem_ARREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
gmem_addr_reg_110 <= data2_sum_cast_fu_100_p1(32 - 1 downto 0);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, gmem_RVALID, ap_sig_ioackin_gmem_ARREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_gmem_ARREADY))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
if (not((gmem_RVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(gmem_RVALID, ap_sig_cseq_ST_st9_fsm_8)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((gmem_RVALID = ap_const_logic_0)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(gmem_RVALID, ap_sig_cseq_ST_st9_fsm_8)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((gmem_RVALID = ap_const_logic_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_182 assign process. --
ap_sig_bdd_182_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_182 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_201 assign process. --
ap_sig_bdd_201_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_201 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_27 assign process. --
ap_sig_bdd_27_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_27 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_27)
begin
if (ap_sig_bdd_27) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_182)
begin
if (ap_sig_bdd_182) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_201)
begin
if (ap_sig_bdd_201) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_gmem_ARREADY assign process. --
ap_sig_ioackin_gmem_ARREADY_assign_proc : process(gmem_ARREADY, ap_reg_ioackin_gmem_ARREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_gmem_ARREADY)) then
ap_sig_ioackin_gmem_ARREADY <= gmem_ARREADY;
else
ap_sig_ioackin_gmem_ARREADY <= ap_const_logic_1;
end if;
end process;
data2_sum_cast_fu_100_p1 <= std_logic_vector(resize(unsigned(data2_sum_fu_94_p2),64));
data2_sum_fu_94_p2 <= std_logic_vector(unsigned(tmp_cast_fu_90_p1) + unsigned(tmp_1_cast_fu_86_p1));
get_gmem_m_axi_U_ap_dummy_ce <= ap_const_logic_1;
gmem_ARADDR <= gmem_addr_reg_110;
gmem_ARBURST <= ap_const_lv2_0;
gmem_ARCACHE <= ap_const_lv4_0;
gmem_ARID <= ap_const_lv1_0;
gmem_ARLEN <= ap_const_lv32_1;
gmem_ARLOCK <= ap_const_lv2_0;
gmem_ARPROT <= ap_const_lv3_0;
gmem_ARQOS <= ap_const_lv4_0;
gmem_ARREGION <= ap_const_lv4_0;
gmem_ARSIZE <= ap_const_lv3_0;
gmem_ARUSER <= ap_const_lv1_0;
-- gmem_ARVALID assign process. --
gmem_ARVALID_assign_proc : process(ap_reg_ioackin_gmem_ARREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_logic_0 = ap_reg_ioackin_gmem_ARREADY))) then
gmem_ARVALID <= ap_const_logic_1;
else
gmem_ARVALID <= ap_const_logic_0;
end if;
end process;
gmem_AWADDR <= ap_const_lv32_0;
gmem_AWBURST <= ap_const_lv2_0;
gmem_AWCACHE <= ap_const_lv4_0;
gmem_AWID <= ap_const_lv1_0;
gmem_AWLEN <= ap_const_lv32_0;
gmem_AWLOCK <= ap_const_lv2_0;
gmem_AWPROT <= ap_const_lv3_0;
gmem_AWQOS <= ap_const_lv4_0;
gmem_AWREGION <= ap_const_lv4_0;
gmem_AWSIZE <= ap_const_lv3_0;
gmem_AWUSER <= ap_const_lv1_0;
gmem_AWVALID <= ap_const_logic_0;
gmem_BREADY <= ap_const_logic_0;
-- gmem_RREADY assign process. --
gmem_RREADY_assign_proc : process(gmem_RVALID, ap_sig_cseq_ST_st9_fsm_8)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((gmem_RVALID = ap_const_logic_0)))) then
gmem_RREADY <= ap_const_logic_1;
else
gmem_RREADY <= ap_const_logic_0;
end if;
end process;
gmem_WDATA <= ap_const_lv32_0;
gmem_WID <= ap_const_lv1_0;
gmem_WLAST <= ap_const_logic_0;
gmem_WSTRB <= ap_const_lv4_0;
gmem_WUSER <= ap_const_lv1_0;
gmem_WVALID <= ap_const_logic_0;
tmp_1_cast_fu_86_p1 <= std_logic_vector(resize(unsigned(tmp_fu_76_p4),33));
tmp_cast_fu_90_p1 <= std_logic_vector(resize(unsigned(key),33));
tmp_fu_76_p4 <= data(31 downto 2);
val_r <= gmem_RDATA;
-- val_r_ap_vld assign process. --
val_r_ap_vld_assign_proc : process(gmem_RVALID, ap_sig_cseq_ST_st9_fsm_8)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((gmem_RVALID = ap_const_logic_0)))) then
val_r_ap_vld <= ap_const_logic_1;
else
val_r_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
4379fac6b1e597489d087003dcca5b1b
| 0.571322 | 3.134317 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_compare1.vhd
| 2 | 4,444 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare1.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare1;
ARCHITECTURE SYN OF lpm_compare1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "0000101011";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "43"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 43 0 0 10 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
48a5c467204941db249963f70e5413df
| 0.655941 | 3.70025 | false | false | false | false |
blutsvente/MIX
|
test/results/configuration/cfgfile/ent_t-rtl-a.vhd
| 1 | 6,206 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.1 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.1 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
component ent_c
-- No Generated Generics
-- Generated Generics for Entity ent_c
-- End of Generated Generics for Entity ent_c
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: ent_c
;
-- End of Generated Instance Port Map for inst_c
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
1d830308df69bdc9b4bc7e5121bb3bd3
| 0.638092 | 2.828624 | false | false | false | false |
mitchsm/nvc
|
test/regress/wait10.vhd
| 5 | 710 |
entity wait10 is
end entity;
architecture test of wait10 is
signal s : bit_vector(3 downto 0);
signal n : integer := 0;
begin
a: process is
variable cnt : integer := 0;
begin
wait on s(2 downto 1);
cnt := cnt + 1;
n <= cnt;
end process;
b: process is
begin
s <= "0000";
wait for 1 ns;
s <= "1001";
wait for 1 ns;
s <= "0101";
wait for 1 ns;
s <= "0010";
wait for 1 ns;
s(1) <= '0';
s(2) <= '1';
wait for 1 ns;
s(2) <= '0';
wait for 1 ns;
report integer'image(n);
assert n = 4;
wait;
end process;
end architecture;
|
gpl-3.0
|
c9561be14492c875a64f9560d0698ee2
| 0.45493 | 3.567839 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/given/ioblock3_e-rtl-a.vhd
| 1 | 11,204 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock3_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock3_e-rtl-a.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: ioblock3_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock3_e
--
architecture rtl of ioblock3_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_g_i --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic;
nand_in : in std_ulogic;
nand_out : out std_ulogic;
p_di : in std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic;
nand_in : in std_ulogic;
nand_out : out std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
component ioc_r_io3 --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io3
do : in std_ulogic_vector(3 downto 0);
en : in std_ulogic_vector(3 downto 0);
nand_dir : in std_ulogic;
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_r_io3
);
end component;
-- ---------
component ioc_r_iou --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_iou
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nand_dir : in std_ulogic;
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
p_pu : out std_ulogic;
pu : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ioc_r_iou
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal ioseldi_0 : std_ulogic;
signal ioseldi_1 : std_ulogic;
signal ioseldi_2 : std_ulogic;
signal ioseldi_3 : std_ulogic;
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_g_i_33
ioc_g_i_33: ioc_g_i
port map (
di => data_i33, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_33, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_i_33
-- Generated Instance Port Map for ioc_g_i_34
ioc_g_i_34: ioc_g_i
port map (
di => data_i34, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_34, -- data in from pad
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_i_34
-- Generated Instance Port Map for ioc_g_o_35
ioc_g_o_35: ioc_g_o
port map (
do => data_o35, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_do => pad_do_35, -- data out to pad
p_en => pad_en_35, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_o_35
-- Generated Instance Port Map for ioc_g_o_36
ioc_g_o_36: ioc_g_o
port map (
do => data_o36, -- io data
nand_dir => nand_dir, -- Direction (X17)
p_do => pad_do_36, -- data out to pad
p_en => pad_en_36, -- pad output enable
sel => iosel_bus -- io data
);
-- End of Generated Instance Port Map for ioc_g_o_36
-- Generated Instance Port Map for ioc_r_io3_39
ioc_r_io3_39: ioc_r_io3
port map (
do(0) => display_ls(0),
do(1) => display_ls(2),
do(2) => display_ls(4),
do(3) => display_ls(6),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_39, -- data in from pad
p_do => pad_do_39, -- data out to pad
p_en => pad_en_39, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
sel(1) => ioseldi_1, -- __I_BIT_TO_BUSPORT
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_r_io3_39
-- Generated Instance Port Map for ioc_r_io3_40
ioc_r_io3_40: ioc_r_io3
port map (
do(0) => display_ls(1),
do(1) => display_ls(3),
do(2) => display_ls(5),
do(3) => display_ls(7),
en(0) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_40, -- data in from pad
p_do => pad_do_40, -- data out to pad
p_en => pad_en_40, -- pad output enable
sel(0) => ioseldi_0, -- __I_BIT_TO_BUSPORT
sel(1) => ioseldi_1, -- __I_BIT_TO_BUSPORT
sel(2) => ioseldi_2, -- __I_BIT_TO_BUSPORT
sel(3) => ioseldi_3 -- __I_BIT_TO_BUSPORT
);
-- End of Generated Instance Port Map for ioc_r_io3_40
-- Generated Instance Port Map for ioc_r_iou_31
ioc_r_iou_31: ioc_r_iou
port map (
di => d9_di(0), -- d9io
do => d9_do(0), -- d9io
en => d9_en(0), -- d9io
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_31, -- data in from pad
p_do => pad_do_31, -- data out to pad
p_en => pad_en_31, -- pad output enable
p_pu => pad_pu_31, -- pull-up control
pu => d9_pu(0) -- d9io
);
-- End of Generated Instance Port Map for ioc_r_iou_31
-- Generated Instance Port Map for ioc_r_iou_32
ioc_r_iou_32: ioc_r_iou
port map (
di => d9_di(1), -- d9io
do => d9_do(1), -- d9io
en => d9_en(1), -- d9io
nand_dir => nand_dir, -- Direction (X17)
p_di => pad_di_32, -- data in from pad
p_do => pad_do_32, -- data out to pad
p_en => pad_en_32, -- pad output enable
p_pu => pad_pu_32, -- pull-up control
pu => d9_pu(1) -- d9io
);
-- End of Generated Instance Port Map for ioc_r_iou_32
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
e1bc472233055853bdb93e0f7fb650d3
| 0.588272 | 2.444687 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nreset/inst_ea_e-rtl-a.vhd
| 1 | 6,967 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ea_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ea_e-rtl-a.vhd,v 1.3 2006/06/26 08:39:43 wig Exp $
-- $Date: 2006/06/26 08:39:43 $
-- $Log: inst_ea_e-rtl-a.vhd,v $
-- Revision 1.3 2006/06/26 08:39:43 wig
-- Update more testcases (up to generic)
--
-- Revision 1.1 2004/04/06 10:50:21 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ea_e
--
architecture rtl of inst_ea_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eaa_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eaa_e
mbist_clut_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_fifo_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
reset_n : in std_ulogic;
reset_n_s : in std_ulogic
-- End of Generated Port for Entity inst_eaa_e
);
end component;
-- ---------
component inst_eab_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eab_e
-- End of Generated Generics for Entity inst_eab_e
port (
-- Generated Port for Entity inst_eab_e
nreset : in std_ulogic;
nreset_s : in std_ulogic;
v_select : in std_ulogic_vector(5 downto 0)
-- End of Generated Port for Entity inst_eab_e
);
end component;
-- ---------
component inst_eac_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eac_e
-- End of Generated Generics for Entity inst_eac_e
port (
-- Generated Port for Entity inst_eac_e
adp_bist_fail : out std_ulogic;
cp_laddr : in std_ulogic_vector(31 downto 0);
cp_lcmd : in std_ulogic_vector(6 downto 0);
cpu_bist_fail : out std_ulogic;
cvi_sbist_fail0 : in std_ulogic;
cvi_sbist_fail1 : in std_ulogic;
ema_bist_fail : out std_ulogic;
ga_sbist_fail0 : in std_ulogic;
ga_sbist_fail1 : in std_ulogic;
gpio_int : out std_ulogic_vector(4 downto 0);
ifu_bist_fail : out std_ulogic;
mcu_bist_fail : out std_ulogic;
nreset : in std_ulogic;
nreset_s : in std_ulogic;
pdu_bist_fail0 : out std_ulogic;
pdu_bist_fail1 : out std_ulogic;
tmu_dac_reset : out std_ulogic;
tsd_bist_fail : out std_ulogic
-- End of Generated Port for Entity inst_eac_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_bus_1 : std_ulogic_vector(5 downto 0);
signal cp_laddr : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cp_lcmd : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal gpio_int : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal tmu_dac_reset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
mix_logic0_0 <= '0';
mix_logic0_2 <= '0';
mix_logic0_bus_1 <= ( others => '0' );
cp_laddr(31 downto 1) <= p_mix_cp_laddr_31_1_gi(30 downto 0); -- __I_I_SLICE_PORT
cp_lcmd(6) <= p_mix_cp_lcmd_6_6_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_gpio_int_4_0_go <= gpio_int; -- __I_O_BUS_PORT
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
tmi_sbist_fail(11 downto 10) <= p_mix_tmi_sbist_fail_11_10_gi(1 downto 0); -- __I_I_SLICE_PORT
p_mix_tmi_sbist_fail_9_0_go(9 downto 0) <= tmi_sbist_fail(9 downto 0); -- __I_O_SLICE_PORT
p_mix_tmu_dac_reset_go <= tmu_dac_reset; -- __I_O_BIT_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eaa
inst_eaa: inst_eaa_e
port map (
mbist_clut_fail_o => tmi_sbist_fail(8),
mbist_fifo_fail_o => tmi_sbist_fail(9),
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_eaa
-- Generated Instance Port Map for inst_eab
inst_eab: inst_eab_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
v_select(0) => mix_logic0_0,
v_select(1) => mix_logic0_0,
v_select(2) => v_select(2),
v_select(3) => mix_logic0_0,
v_select(4) => mix_logic0_0, -- GuestBusLBC(memorymappedI/O)Interface
v_select(5) => v_select(5) -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
);
-- End of Generated Instance Port Map for inst_eab
-- Generated Instance Port Map for inst_eac
inst_eac: inst_eac_e
port map (
adp_bist_fail => tmi_sbist_fail(0),
cp_laddr(0) => mix_logic0_2, -- __I_BIT_TO_BUSPORT -- GuestBusLBC(memorymappedI/O)Interface
cp_laddr(31 downto 1) => cp_laddr(31 downto 1), -- GuestBusLBC(memorymappedI/O)InterfaceLBCinterfacetobeusecurrentlybyGuestBus
cp_lcmd(5 downto 0) => mix_logic0_bus_1, -- __W_PORT
cp_lcmd(6) => cp_lcmd(6), -- GuestBusLBC(memorymappedI/O)Interface
cpu_bist_fail => tmi_sbist_fail(1),
cvi_sbist_fail0 => tmi_sbist_fail(10),
cvi_sbist_fail1 => tmi_sbist_fail(11),
ema_bist_fail => tmi_sbist_fail(7),
ga_sbist_fail0 => tmi_sbist_fail(8),
ga_sbist_fail1 => tmi_sbist_fail(9),
gpio_int => gpio_int, -- GPIOWakeUPSignalsInterruptinputs
ifu_bist_fail => tmi_sbist_fail(6),
mcu_bist_fail => tmi_sbist_fail(2),
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
pdu_bist_fail0 => tmi_sbist_fail(3),
pdu_bist_fail1 => tmi_sbist_fail(4),
tmu_dac_reset => tmu_dac_reset, -- CADCTestModeRGBADAC
tsd_bist_fail => tmi_sbist_fail(5)
);
-- End of Generated Instance Port Map for inst_eac
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
08597fb24db01ae13f2097672a9ce540
| 0.63241 | 2.787915 | false | false | false | false |
blutsvente/MIX
|
test/results/configuration/ent_t-rtl-a.vhd
| 1 | 5,979 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Jul 4 05:34:51 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.5 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.5 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
component ent_c
-- No Generated Generics
-- Generated Generics for Entity ent_c
-- End of Generated Generics for Entity ent_c
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: ent_c
;
-- End of Generated Instance Port Map for inst_c
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
4fb1a478eb8a1c1f78107ecbc095aaca
| 0.633216 | 2.818953 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/rtl/afu.vhd
| 1 | 6,048 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.psl.all;
use work.functions.all;
use work.frame_package.all;
entity afu is
port (
ah_cvalid : out std_logic;
ah_ctag : out std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ah_ctagpar : out std_logic;
ah_com : out std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0);
ah_compar : out std_logic;
ah_cabt : out std_logic_vector(PSL_ABT_WIDTH - 1 downto 0);
ah_cea : out std_logic_vector(PSL_ADDRESS_WIDTH - 1 downto 0);
ah_ceapar : out std_logic;
ah_cch : out std_logic_vector(PSL_CH_WIDTH - 1 downto 0);
ah_csize : out std_logic_vector(PSL_SIZE_WIDTH - 1 downto 0);
ha_croom : in std_logic_vector(PSL_ROOM_WIDTH - 1 downto 0);
ha_brvalid : in std_logic;
ha_brtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_brtagpar : in std_logic;
ha_brad : in std_logic_vector(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
ah_brlat : out std_logic_vector(PSL_LATENCY_WIDTH - 1 downto 0);
ah_brdata : out std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
ah_brpar : out std_logic_vector((PSL_DATA_WIDTH - 1) / PSL_DOUBLE_WORD_WIDTH downto 0);
ha_bwvalid : in std_logic;
ha_bwtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_bwtagpar : in std_logic;
ha_bwad : in std_logic_vector(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
ha_bwdata : in std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
ha_bwpar : in std_logic_vector((PSL_DATA_WIDTH - 1) / PSL_DOUBLE_WORD_WIDTH downto 0);
ha_rvalid : in std_logic;
ha_rtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_rtagpar : in std_logic;
ha_response : in std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0);
ha_rcredits : in std_logic_vector(PSL_CREDITS_WIDTH - 1 downto 0);
ha_rcachestate : in std_logic_vector(PSL_CACHESTATE_WIDTH - 1 downto 0);
ha_rcachepos : in std_logic_vector(PSL_CACHEPOS_WIDTH - 1 downto 0);
ha_mmval : in std_logic;
ha_mmcfg : in std_logic;
ha_mmrnw : in std_logic;
ha_mmdw : in std_logic;
ha_mmad : in std_logic_vector(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0);
ha_mmadpar : in std_logic;
ha_mmdata : in std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
ha_mmdatapar : in std_logic;
ah_mmack : out std_logic;
ah_mmdata : out std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
ah_mmdatapar : out std_logic;
ha_jval : in std_logic;
ha_jcom : in std_logic_vector(PSL_JOB_COMMAND_WIDTH - 1 downto 0);
ha_jcompar : in std_logic;
ha_jea : in std_logic_vector(PSL_ADDRESS_WIDTH - 1 downto 0);
ha_jeapar : in std_logic;
ah_jrunning : out std_logic;
ah_jdone : out std_logic;
ah_jcack : out std_logic;
ah_jerror : out std_logic_vector(PSL_ERROR_WIDTH - 1 downto 0);
ah_jyield : out std_logic;
ah_tbreq : out std_logic;
ah_paren : out std_logic;
ha_pclock : in std_logic
);
end entity afu;
architecture logic of afu is
signal ha : frame_in;
signal ah : frame_out;
begin
----------------------------------------------------------------------------------------------------------------------- inputs
--ha.c.room <= ha_croom;
ha.b.rvalid <= ha_brvalid;
ha.b.rtag <= u(ha_brtag);
--ha.b.rtagpar <= ha_brtagpar;
ha.b.rad <= u(ha_brad);
ha.b.wvalid <= ha_bwvalid;
ha.b.wtag <= u(ha_bwtag);
--ha.b.wtagpar <= ha_bwtagpar;
ha.b.wad <= u(ha_bwad);
ha.b.wdata <= ha_bwdata;
--ha.b.wpar <= ha_bwpar;
ha.r.valid <= ha_rvalid;
ha.r.tag <= u(ha_rtag);
--ha.r.tagpar <= ha_rtagpar;
ha.r.response <= ha_response;
--ha.r.credits <= ha_rcredits;
--ha.r.cachestate <= ha_rcachestate;
--ha.r.cachepos <= ha_rcachepos;
ha.mm.val <= ha_mmval;
ha.mm.cfg <= ha_mmcfg;
ha.mm.rnw <= ha_mmrnw;
ha.mm.dw <= ha_mmdw;
ha.mm.ad <= u(ha_mmad);
--ha.mm.adpar <= ha_mmadpar;
ha.mm.data <= ha_mmdata;
--ha.mm.datapar <= ha_mmdatapar;
ha.j.com <= ha_jcom;
ha.j.val <= ha_jval;
--ha.j.compar <= ha_jcompar;
ha.j.ea <= u(ha_jea);
--ha.j.eapar <= ha_jeapar;
ha.j.pclock <= ha_pclock;
----------------------------------------------------------------------------------------------------------------------- outputs
ah_cvalid <= ah.c.valid;
ah_ctag <= slv(ah.c.tag);
ah_ctagpar <= '0'; --ah.c.tagpar;
ah_com <= ah.c.com;
ah_compar <= '0'; --ah.c.compar;
ah_cabt <= PTOB_PAGE; --ah.c.abt;
ah_cea <= slv(ah.c.ea);
ah_ceapar <= '0'; --ah.c.eapar;
ah_cch <= (others => '0'); --ah.c.ch;
ah_csize <= slv(ah.c.size);
ah_brlat <= slv(1, PSL_LATENCY_WIDTH); --ah.b.rlat;
ah_brdata <= ah.b.rdata;
ah_brpar <= (others => '0'); --ah.b.rpar;
ah_mmack <= ah.mm.ack;
ah_mmdata <= ah.mm.data;
ah_mmdatapar <= '0'; --ah.mm.datapar;
ah_jrunning <= ah.j.running;
ah_jdone <= ah.j.done;
ah_jcack <= '0'; --ah.j.ack;
ah_jerror <= (others => '0'); --ah.j.error;
ah_jyield <= '0'; --ah.j.yield;
ah_tbreq <= '0'; --ah.j.tbreq;
ah_paren <= '0'; --ah.j.paren;
f0 : entity work.frame port map (ha, ah);
end architecture logic;
|
bsd-2-clause
|
b1285bb347655d15ab8ce23f41e27181
| 0.491237 | 3.06383 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare13.vhd
| 1 | 4,446 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare13.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare13 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare13;
ARCHITECTURE SYN OF lpm_compare13 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "111110100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "500"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 500 0 0 9 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare13.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare13.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare13.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare13.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare13_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
0841005befb8cd26ec7660dc54d82db3
| 0.656095 | 3.701915 | false | false | false | false |
blutsvente/MIX
|
test/results/padio2/pads_eastnord-struct-a.vhd
| 1 | 23,351 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_eastnord
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pads_eastnord-struct-a.vhd,v 1.6 2007/03/05 15:29:26 wig Exp $
-- $Date: 2007/03/05 15:29:26 $
-- $Log: pads_eastnord-struct-a.vhd,v $
-- Revision 1.6 2007/03/05 15:29:26 wig
-- Updated testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of pads_eastnord
--
architecture struct of pads_eastnord is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc
-- No Generated Generics
port (
-- Generated Port for Entity ioc
bypass : in std_ulogic_vector(1 downto 0);
clk : in std_ulogic_vector(1 downto 0);
clockdr_i : in std_ulogic;
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(1 downto 0);
en : in std_ulogic_vector(1 downto 0);
enq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
iddq : in std_ulogic_vector(1 downto 0);
mode_1_i : in std_ulogic;
mode_2_i : in std_ulogic;
mode_3_i : in std_ulogic;
mux_sel_p : in std_ulogic_vector(1 downto 0);
oe : in std_ulogic_vector(1 downto 0);
pad : inout std_ulogic;
pd : in std_ulogic_vector(1 downto 0);
res_n : in std_ulogic;
scan_en_i : in std_ulogic;
scan_i : in std_ulogic;
scan_o : out std_ulogic;
serial_input_i : in std_ulogic;
serial_output_o : out std_ulogic;
shiftdr_i : in std_ulogic;
tck_i : in std_ulogic;
tenq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
updatedr_i : in std_ulogic
-- End of Generated Port for Entity ioc
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_1 : std_ulogic;
signal mix_logic1_10 : std_ulogic;
signal mix_logic1_11 : std_ulogic;
signal mix_logic1_12 : std_ulogic;
signal mix_logic1_13 : std_ulogic;
signal mix_logic1_14 : std_ulogic;
signal mix_logic1_15 : std_ulogic;
signal mix_logic1_16 : std_ulogic;
signal mix_logic1_17 : std_ulogic;
signal mix_logic1_2 : std_ulogic;
signal mix_logic1_3 : std_ulogic;
signal mix_logic1_4 : std_ulogic;
signal mix_logic1_48 : std_ulogic;
signal mix_logic1_49 : std_ulogic;
signal mix_logic1_5 : std_ulogic;
signal mix_logic1_50 : std_ulogic;
signal mix_logic1_51 : std_ulogic;
signal mix_logic1_52 : std_ulogic;
signal mix_logic1_53 : std_ulogic;
signal mix_logic1_54 : std_ulogic;
signal mix_logic1_55 : std_ulogic;
signal mix_logic1_56 : std_ulogic;
signal mix_logic1_57 : std_ulogic;
signal mix_logic1_58 : std_ulogic;
signal mix_logic1_59 : std_ulogic;
signal mix_logic1_6 : std_ulogic;
signal mix_logic1_60 : std_ulogic;
signal mix_logic1_61 : std_ulogic;
signal mix_logic1_62 : std_ulogic;
signal mix_logic1_63 : std_ulogic;
signal mix_logic1_64 : std_ulogic;
signal mix_logic1_65 : std_ulogic;
signal mix_logic1_7 : std_ulogic;
signal mix_logic1_8 : std_ulogic;
signal mix_logic1_9 : std_ulogic;
signal mix_logic0_0 : std_ulogic;
signal mix_logic0_1 : std_ulogic;
signal mix_logic0_16 : std_ulogic;
signal mix_logic0_17 : std_ulogic;
signal mix_logic0_18 : std_ulogic;
signal mix_logic0_19 : std_ulogic;
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_20 : std_ulogic;
signal mix_logic0_21 : std_ulogic;
signal mix_logic0_3 : std_ulogic;
signal mix_logic0_34 : std_ulogic;
signal mix_logic0_37 : std_ulogic;
signal mix_logic0_39 : std_ulogic;
signal mix_logic0_4 : std_ulogic;
signal mix_logic0_41 : std_ulogic;
signal mix_logic0_43 : std_ulogic;
signal mix_logic0_45 : std_ulogic;
signal mix_logic0_5 : std_ulogic;
signal mix_logic0_50 : std_ulogic;
signal mix_logic0_53 : std_ulogic;
signal mix_logic0_55 : std_ulogic;
signal mix_logic0_56 : std_ulogic;
signal mix_logic0_61 : std_ulogic;
signal mix_logic0_63 : std_ulogic;
signal clkf81 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal clockdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal dbo_o : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal default : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_1_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_2_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_3_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pmux_sel_por : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal res_f81_n : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_byp_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_iddq_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_sio_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_in_db2o_10 : std_ulogic;
signal s_in_db2o_11 : std_ulogic;
signal s_in_db2o_12 : std_ulogic;
signal s_in_db2o_13 : std_ulogic;
signal s_in_db2o_14 : std_ulogic;
signal s_in_db2o_15 : std_ulogic;
signal s_in_dbo_10 : std_ulogic;
signal s_in_dbo_11 : std_ulogic;
signal s_in_dbo_12 : std_ulogic;
signal s_in_dbo_13 : std_ulogic;
signal s_in_dbo_14 : std_ulogic;
signal s_in_dbo_15 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_10 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_11 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_12 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_13 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_14 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_15 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_10 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_11 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_12 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_13 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_14 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_15 : std_ulogic;
signal scan_en_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal shiftdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tck_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal updatedr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal varclk_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_1 <= '1';
mix_logic1_10 <= '1';
mix_logic1_11 <= '1';
mix_logic1_12 <= '1';
mix_logic1_13 <= '1';
mix_logic1_14 <= '1';
mix_logic1_15 <= '1';
mix_logic1_16 <= '1';
mix_logic1_17 <= '1';
mix_logic1_2 <= '1';
mix_logic1_3 <= '1';
mix_logic1_4 <= '1';
mix_logic1_48 <= '1';
mix_logic1_49 <= '1';
mix_logic1_5 <= '1';
mix_logic1_50 <= '1';
mix_logic1_51 <= '1';
mix_logic1_52 <= '1';
mix_logic1_53 <= '1';
mix_logic1_54 <= '1';
mix_logic1_55 <= '1';
mix_logic1_56 <= '1';
mix_logic1_57 <= '1';
mix_logic1_58 <= '1';
mix_logic1_59 <= '1';
mix_logic1_6 <= '1';
mix_logic1_60 <= '1';
mix_logic1_61 <= '1';
mix_logic1_62 <= '1';
mix_logic1_63 <= '1';
mix_logic1_64 <= '1';
mix_logic1_65 <= '1';
mix_logic1_7 <= '1';
mix_logic1_8 <= '1';
mix_logic1_9 <= '1';
mix_logic0_0 <= '0';
mix_logic0_1 <= '0';
mix_logic0_16 <= '0';
mix_logic0_17 <= '0';
mix_logic0_18 <= '0';
mix_logic0_19 <= '0';
mix_logic0_2 <= '0';
mix_logic0_20 <= '0';
mix_logic0_21 <= '0';
mix_logic0_3 <= '0';
mix_logic0_34 <= '0';
mix_logic0_37 <= '0';
mix_logic0_39 <= '0';
mix_logic0_4 <= '0';
mix_logic0_41 <= '0';
mix_logic0_43 <= '0';
mix_logic0_45 <= '0';
mix_logic0_5 <= '0';
mix_logic0_50 <= '0';
mix_logic0_53 <= '0';
mix_logic0_55 <= '0';
mix_logic0_56 <= '0';
mix_logic0_61 <= '0';
mix_logic0_63 <= '0';
clkf81 <= clkf81_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
clockdr_i <= clockdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
dbo_o_15_10_go(5 downto 0) <= dbo_o(15 downto 10); -- __I_O_SLICE_PORT
default <= default_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_1_i <= mode_1_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_2_i <= mode_2_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_3_i <= mode_3_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
pmux_sel_por <= pmux_sel_por_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
res_f81_n <= res_f81_n_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_byp_i <= rgbout_byp_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_iddq_i <= rgbout_iddq_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_sio_i <= rgbout_sio_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
scan_en_i <= scan_en_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
shiftdr_i <= shiftdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
tck_i <= tck_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
updatedr_i <= updatedr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
varclk_i <= varclk_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_db2o_10
ioc_db2o_10: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_50, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(10), -- padout (X2)
do(0) => db2o_i(10), -- padin (X2)
do(1) => mix_logic1_48, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_16, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_49, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_10, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_34,
scan_o => open,
serial_input_i => s_in_db2o_10,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_10
-- Generated Instance Port Map for ioc_db2o_11
ioc_db2o_11: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_53, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(11), -- padout (X2)
do(0) => db2o_i(11), -- padin (X2)
do(1) => mix_logic1_51, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_17, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_52, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_11, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_39,
scan_o => open,
serial_input_i => s_in_db2o_11,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_11
-- Generated Instance Port Map for ioc_db2o_12
ioc_db2o_12: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_56, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(12), -- padout (X2)
do(0) => db2o_i(12), -- padin (X2)
do(1) => mix_logic1_54, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_18, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_55, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_12, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_55,
scan_o => open,
serial_input_i => s_in_db2o_12,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_12
-- Generated Instance Port Map for ioc_db2o_13
ioc_db2o_13: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_59, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(13), -- padout (X2)
do(0) => db2o_i(13), -- padin (X2)
do(1) => mix_logic1_57, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_19, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_58, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_13, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_37,
scan_o => open,
serial_input_i => s_in_db2o_13,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_13
-- Generated Instance Port Map for ioc_db2o_14
ioc_db2o_14: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_62, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(14), -- padout (X2)
do(0) => db2o_i(14), -- padin (X2)
do(1) => mix_logic1_60, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_20, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_61, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_14, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_45,
scan_o => open,
serial_input_i => s_in_db2o_14,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_14
-- Generated Instance Port Map for ioc_db2o_15
ioc_db2o_15: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_65, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(15), -- padout (X2)
do(0) => db2o_i(15), -- padin (X2)
do(1) => mix_logic1_63, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_21, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_64, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_15, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_41,
scan_o => open,
serial_input_i => s_in_db2o_15,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_15
-- Generated Instance Port Map for ioc_dbo_10
ioc_dbo_10: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_2, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(10), -- padout
do(0) => dbo_i(10), -- padin (X2)
do(1) => mix_logic1_0, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_0, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_1, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_10, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_50,
scan_o => open,
serial_input_i => s_in_dbo_10,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_10
-- Generated Instance Port Map for ioc_dbo_11
ioc_dbo_11: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_5, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(11), -- padout
do(0) => dbo_i(11), -- padin (X2)
do(1) => mix_logic1_3, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_1, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_4, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_11, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_61,
scan_o => open,
serial_input_i => s_in_dbo_11,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_11
-- Generated Instance Port Map for ioc_dbo_12
ioc_dbo_12: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_8, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(12), -- padout
do(0) => dbo_i(12), -- padin (X2)
do(1) => mix_logic1_6, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_7, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_12, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_53,
scan_o => open,
serial_input_i => s_in_dbo_12,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_12
-- Generated Instance Port Map for ioc_dbo_13
ioc_dbo_13: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_11, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(13), -- padout
do(0) => dbo_i(13), -- padin (X2)
do(1) => mix_logic1_9, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_3, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_10, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_13, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_43,
scan_o => open,
serial_input_i => s_in_dbo_13,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_13
-- Generated Instance Port Map for ioc_dbo_14
ioc_dbo_14: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_14, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(14), -- padout
do(0) => dbo_i(14), -- padin (X2)
do(1) => mix_logic1_12, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_4, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_13, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_14, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_56,
scan_o => open,
serial_input_i => s_in_dbo_14,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_14
-- Generated Instance Port Map for ioc_dbo_15
ioc_dbo_15: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_17, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(15), -- padout
do(0) => dbo_i(15), -- padin (X2)
do(1) => mix_logic1_15, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_5, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_16, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_15, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_63,
scan_o => open,
serial_input_i => s_in_dbo_15,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_15
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3ec8ad8c4ab9c442379d4bc7821cf173
| 0.577363 | 2.263132 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/ioblock0_e-rtl-a.vhd
| 1 | 5,800 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock0_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock0_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:22 wig Exp $
-- $Date: 2006/07/05 10:01:22 $
-- $Log: ioblock0_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:22 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock0_e
--
architecture rtl of ioblock0_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc_g_i
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- Links ...
nand_out : out std_ulogic; -- Links ...
p_di : in std_ulogic; -- data in from pad
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- Links ...
nand_out : out std_ulogic; -- Links ...
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
--
-- Generated Signal List
--
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
constant nand_out_0_c : std_ulogic := '0';
signal nand_out_0 : std_ulogic;
signal nand_out_1 : std_ulogic;
signal nand_out_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
iosel_6 <= p_mix_iosel_6_gi; -- __I_I_BIT_PORT
iosel_7 <= p_mix_iosel_7_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
nand_out_0 <= nand_out_0_c;
p_mix_nand_out_2_go <= nand_out_2; -- __I_O_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_g_i_1
ioc_g_i_1: ioc_g_i
port map (
di => data_i1, -- io data
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_0, -- Links ...
nand_out => nand_out_1, -- Links ...
p_di => pad_di_1, -- data in from pad
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(6) => iosel_6, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(7) => iosel_7 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_g_i_1
-- Generated Instance Port Map for ioc_g_o_2
ioc_g_o_2: ioc_g_o
port map (
do => data_o1, -- io data
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_1, -- Links ...
nand_out => nand_out_2, -- Links ...
p_do => pad_do_2, -- data out to pad
p_en => pad_en_2, -- pad output enable
sel(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(6) => iosel_6, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(7) => iosel_7 -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_g_o_2
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
9c5143c26a0f41bc61759e5720d39474
| 0.580517 | 2.478632 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/bus/ioblock1_e-rtl-a.vhd
| 1 | 11,596 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock1_e-rtl-a.vhd,v 1.1 2004/04/06 10:44:22 wig Exp $
-- $Date: 2004/04/06 10:44:22 $
-- $Log: ioblock1_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:44:22 wig
-- Adding result/padio
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock1_e
--
architecture rtl of ioblock1_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_r_io --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(4 downto 0);
en : in std_ulogic_vector(4 downto 0);
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_r_io
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BUS_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_disp_2
ioc_disp_2: ioc_r_io
port map (
di => di2(0), -- io data
do(0) => disp2(0), -- io data
do(1) => display_ls_min(0), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(0), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(0), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(0), -- Display storage buffer 1 ms_min
en(0) => disp2_en(0), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_12, -- data in from pad
p_do => pad_do_12, -- data out to pad
p_en => pad_en_12, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_2
-- Generated Instance Port Map for ioc_disp_3
ioc_disp_3: ioc_r_io
port map (
di => di2(1), -- io data
do(0) => disp2(1), -- io data
do(1) => display_ls_min(1), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(1), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(1), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(1), -- Display storage buffer 1 ms_min
en(0) => disp2_en(1), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_13, -- data in from pad
p_do => pad_do_13, -- data out to pad
p_en => pad_en_13, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_3
-- Generated Instance Port Map for ioc_disp_4
ioc_disp_4: ioc_r_io
port map (
di => di2(3), -- io data
do(0) => disp2(3), -- io data
do(1) => display_ls_min(2), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(2), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(2), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(2), -- Display storage buffer 1 ms_min
en(0) => disp2_en(3), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_14, -- data in from pad
p_do => pad_do_14, -- data out to pad
p_en => pad_en_14, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_4
-- Generated Instance Port Map for ioc_disp_5
ioc_disp_5: ioc_r_io
port map (
di => di2(4), -- io data
do(0) => disp2(4), -- io data
do(1) => display_ls_min(3), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(3), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(3), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(3), -- Display storage buffer 1 ms_min
en(0) => disp2_en(4), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_15, -- data in from pad
p_do => pad_do_15, -- data out to pad
p_en => pad_en_15, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_5
-- Generated Instance Port Map for ioc_disp_6
ioc_disp_6: ioc_r_io
port map (
di => di2(5), -- io data
do(0) => disp2(5), -- io data
do(1) => display_ls_min(4), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(4), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(4), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(4), -- Display storage buffer 1 ms_min
en(0) => disp2_en(5), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_16, -- data in from pad
p_do => pad_do_16, -- data out to pad
p_en => pad_en_16, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_6
-- Generated Instance Port Map for ioc_disp_7
ioc_disp_7: ioc_r_io
port map (
di => di2(6), -- io data
do(0) => disp2(6), -- io data
do(1) => display_ls_min(5), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(5), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(5), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(5), -- Display storage buffer 1 ms_min
en(0) => disp2_en(6), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_17, -- data in from pad
p_do => pad_do_17, -- data out to pad
p_en => pad_en_17, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_7
-- Generated Instance Port Map for ioc_disp_8
ioc_disp_8: ioc_r_io
port map (
di => di2(7), -- io data
do(0) => disp2(7), -- io data
do(1) => display_ls_min(6), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(6), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(6), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(6), -- Display storage buffer 1 ms_min
en(0) => disp2_en(7), -- io data
en(1) => display_ls_en,
en(2) => display_ls_en, -- io_enable
en(3) => display_ms_en,
en(4) => display_ms_en, -- io_enable
p_di => pad_di_18, -- data in from pad
p_do => pad_do_18, -- data out to pad
p_en => pad_en_18, -- pad output enable
sel => iosel_disp -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_8
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
6bf070da8a4598e334c7fb242dcc2835
| 0.589514 | 2.49162 | false | false | false | false |
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/fifo_256x8_pa3.vhd
| 1 | 8,168 |
-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreUART/ CoreUARTapb UART core
--
--
-- Revision Information:
-- Date Description
-- Jun09 Revision 4.1
-- Aug10 Revision 4.2
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR Date Who Description
-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
-- sys clk (not baud clock). See note below.
-- Notes:
-- best viewed with tabstops set to "4"
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
ENTITY CU_TOP_FPGA_UART_fifo_256x8 IS
GENERIC(SYNC_RESET: INTEGER := 0);
PORT (
DO : OUT std_logic_vector(7 DOWNTO 0);
RCLOCK : IN std_logic;
WCLOCK : IN std_logic;
DI : IN std_logic_vector(7 DOWNTO 0);
WRB : IN std_logic;
RDB : IN std_logic;
RESET : IN std_logic;
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END ENTITY CU_TOP_FPGA_UART_fifo_256x8;
ARCHITECTURE translated OF CU_TOP_FPGA_UART_fifo_256x8 IS
COMPONENT CU_TOP_FPGA_UART_fifo_256x8_pa3
PORT (
DATA : IN std_logic_vector(7 DOWNTO 0);
Q : OUT std_logic_vector(7 DOWNTO 0);
WE : IN std_logic;
RE : IN std_logic;
WCLOCK : IN std_logic;
RCLOCK : IN std_logic;
FULL : OUT std_logic;
EMPTY : OUT std_logic;
RESET : IN std_logic;
AEMPTY : OUT std_logic;
AFULL : OUT std_logic;
LEVEL : IN std_logic_vector(7 DOWNTO 0));
END COMPONENT;
CONSTANT LEVEL : std_logic_vector(7 DOWNTO 0) := "11111111";
SIGNAL AEMPTY : std_logic;
SIGNAL AFULL : std_logic;
SIGNAL DO_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL DO_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL FULL_xhdl2 : std_logic;
SIGNAL EMPTY_xhdl3 : std_logic;
SIGNAL EQTH_xhdl4 : std_logic;
SIGNAL GEQTH_xhdl5 : std_logic;
BEGIN
DO <= DO_xhdl1;
FULL <= FULL_xhdl2;
EMPTY <= EMPTY_xhdl3;
PROCESS (RCLOCK)
BEGIN
IF (RCLOCK'EVENT AND RCLOCK = '1') THEN
DO_xhdl1 <= DO_0;
END IF;
END PROCESS;
CU_TOP_FPGA_UART_fifo_256x8_pa3_xhdl14 : CU_TOP_FPGA_UART_fifo_256x8_pa3
PORT MAP (
DATA => DI,
Q => DO_0,
WE => WRB,
RE => RDB,
WCLOCK => WCLOCK,
RCLOCK => RCLOCK,
AEMPTY => AEMPTY,
AFULL => GEQTH_xhdl5,
FULL => FULL_xhdl2,
EMPTY => EMPTY_xhdl3,
RESET => RESET,
LEVEL => LEVEL);
END ARCHITECTURE translated;
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
ENTITY CU_TOP_FPGA_UART_fifo_256x8_pa3 IS
PORT (
DATA : IN std_logic_vector(7 DOWNTO 0);
Q : OUT std_logic_vector(7 DOWNTO 0);
WE : IN std_logic;
RE : IN std_logic;
WCLOCK : IN std_logic;
RCLOCK : IN std_logic;
FULL : OUT std_logic;
EMPTY : OUT std_logic;
RESET : IN std_logic;
AEMPTY : OUT std_logic;
AFULL : OUT std_logic;
LEVEL : IN std_logic_vector(7 DOWNTO 0));
END ENTITY CU_TOP_FPGA_UART_fifo_256x8_pa3;
ARCHITECTURE translated OF CU_TOP_FPGA_UART_fifo_256x8_pa3 IS
component INV
port(A : in std_logic := 'U'; Y : out std_logic) ;
end component;
component FIFO4K18
port(AEVAL11, AEVAL10, AEVAL9, AEVAL8, AEVAL7, AEVAL6,
AEVAL5, AEVAL4, AEVAL3, AEVAL2, AEVAL1, AEVAL0, AFVAL11,
AFVAL10, AFVAL9, AFVAL8, AFVAL7, AFVAL6, AFVAL5, AFVAL4,
AFVAL3, AFVAL2, AFVAL1, AFVAL0, WD17, WD16, WD15, WD14,
WD13, WD12, WD11, WD10, WD9, WD8, WD7, WD6, WD5, WD4, WD3,
WD2, WD1, WD0, WW0, WW1, WW2, RW0, RW1, RW2, RPIPE, WEN,
REN, WBLK, RBLK, WCLK, RCLK, RESET, ESTOP, FSTOP : in
std_logic := 'U'; RD17, RD16, RD15, RD14, RD13, RD12,
RD11, RD10, RD9, RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1,
RD0, FULL, AFULL, EMPTY, AEMPTY : out std_logic) ;
end component;
component VCC
port( Y : out std_logic);
end component;
component GND
port( Y : out std_logic);
end component;
SIGNAL WEAP : std_logic;
SIGNAL VCC_0 : std_logic;
SIGNAL GND_0 : std_logic;
SIGNAL Q_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL FULL_xhdl2 : std_logic;
SIGNAL EMPTY_xhdl3 : std_logic;
SIGNAL AEMPTY_xhdl4 : std_logic;
SIGNAL AFULL_xhdl5 : std_logic;
BEGIN
Q <= Q_xhdl1;
FULL <= FULL_xhdl2;
EMPTY <= EMPTY_xhdl3;
AEMPTY <= AEMPTY_xhdl4;
AFULL <= AFULL_xhdl5;
VCC_1_net : VCC PORT MAP ( Y => VCC_0);
GND_1_net : GND PORT MAP ( Y => GND_0);
REBUBBLEA : INV PORT MAP ( A => RE, Y => WEAP);
FIFOBLOCK0 : FIFO4K18
PORT MAP (
AEVAL11 => GND_0,
AEVAL10 => GND_0,
AEVAL9 => GND_0,
AEVAL8 => GND_0,
AEVAL7 => GND_0,
AEVAL6 => GND_0,
AEVAL5 => GND_0,
AEVAL4 => GND_0,
AEVAL3 => VCC_0,
AEVAL2 => GND_0,
AEVAL1 => GND_0,
AEVAL0 => GND_0,
AFVAL11 => GND_0,
AFVAL10 => LEVEL(7),
AFVAL9 => LEVEL(6),
AFVAL8 => LEVEL(5),
AFVAL7 => LEVEL(4),
AFVAL6 => LEVEL(3),
AFVAL5 => LEVEL(2),
AFVAL4 => LEVEL(1),
AFVAL3 => LEVEL(0),
AFVAL2 => GND_0,
AFVAL1 => GND_0,
AFVAL0 => GND_0,
WD17 => GND_0,
WD16 => GND_0,
WD15 => GND_0,
WD14 => GND_0,
WD13 => GND_0,
WD12 => GND_0,
WD11 => GND_0,
WD10 => GND_0,
WD9 => GND_0,
WD8 => GND_0,
WD7 => DATA(7),
WD6 => DATA(6),
WD5 => DATA(5),
WD4 => DATA(4),
WD3 => DATA(3),
WD2 => DATA(2),
WD1 => DATA(1),
WD0 => DATA(0),
WW0 => VCC_0,
WW1 => VCC_0,
WW2 => GND_0,
RW0 => VCC_0,
RW1 => VCC_0,
RW2 => GND_0,
RPIPE => GND_0,
WEN => WE,
REN => WEAP,
WBLK => GND_0,
RBLK => GND_0,
WCLK => WCLOCK,
RCLK => RCLOCK,
RESET => RESET,
ESTOP => VCC_0,
FSTOP => VCC_0,
RD17 => open,
RD16 => open,
RD15 => open,
RD14 => open,
RD13 => open,
RD12 => open,
RD11 => open,
RD10 => open,
RD9 => open,
RD8 => open,
RD7 => Q_xhdl1(7),
RD6 => Q_xhdl1(6),
RD5 => Q_xhdl1(5),
RD4 => Q_xhdl1(4),
RD3 => Q_xhdl1(3),
RD2 => Q_xhdl1(2),
RD1 => Q_xhdl1(1),
RD0 => Q_xhdl1(0),
FULL => open,
AFULL => FULL_xhdl2,
EMPTY => EMPTY_xhdl3,
AEMPTY => AEMPTY_xhdl4);
END ARCHITECTURE translated;
|
mit
|
3ae10c1d183634e261db7ff69ce81ea9
| 0.459843 | 3.601411 | false | false | false | false |
mitchsm/nvc
|
test/regress/wait7.vhd
| 5 | 817 |
entity wait7 is
end entity;
architecture test of wait7 is
signal state : integer := 0;
signal x : integer := 0;
begin
wakeup: process is
begin
wait until x = 1;
state <= 1;
wait until x = 5;
state <= 2;
wait until x > 10;
state <= 3;
wait;
end process;
stim: process is
begin
x <= -1;
wait for 1 ns;
assert state = 0;
x <= 6;
wait for 1 ns;
assert state = 0;
x <= 1;
wait for 1 ns;
assert state = 1;
x <= 0;
wait for 1 ns;
assert state = 1;
x <= 5;
wait for 1 ns;
assert state = 2;
x <= 50;
wait for 1 ns;
assert state = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
3015f60261d7872c86933ef9600b7f33
| 0.445532 | 3.909091 | false | false | false | false |
blutsvente/MIX
|
test/results/configuration/cmdline/ent_a-rtl-a.vhd
| 1 | 7,578 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic; -- Use internally test1
port_aa_2 : out std_ulogic; -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 : out std_ulogic_vector(3 downto 0); -- Bus, single bits go to outside
port_aa_6 : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : out std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_ADD_MY_SIG : out std_test -- adding my own macro
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
--__I_COMPONENT_NOCOMPDEC__ inst_ab
--__I_COMPONENT_NOCOMPDEC__ inst_ac
component ent_ad
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- Use internally test2, no port generated __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae
-- No Generated Generics
-- Generated Generics for Entity ent_ae
-- End of Generated Generics for Entity ent_ae
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0); -- Use internally test2, no port generated
port_ae_5 : in std_ulogic_vector(3 downto 0); -- Bus, single bits go to outside
port_ae_6 : in std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_i_ae : in std_ulogic_vector(6 downto 0); -- Input Bus
sig_o_ae : out std_ulogic_vector(7 downto 0) -- Output Bus
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_ADD_MY_SIG : std_test;
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13, -- Create internal signal name
sig_ADD_MY_SIG => sig_ADD_MY_SIG -- adding my own macro
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
macro_sig => sig_ADD_MY_SIG, -- adding my own macro
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
53bdf04a40d32995ed94bc19696a76dc
| 0.64067 | 2.829724 | false | true | false | false |
mitchsm/nvc
|
test/lower/assign1.vhd
| 4 | 455 |
entity assign1 is
end entity;
architecture test of assign1 is
begin
process is
variable x : integer := 64;
variable y : integer := -4;
begin
wait for 4 ns;
assert x = 64;
assert y = -4;
x := y * 2;
assert x = -8;
x := 5;
y := 7;
assert x = 5;
assert y = 7;
wait for 1 ns;
assert x + y = 12;
wait;
end process;
end architecture;
|
gpl-3.0
|
655724ad8fd6c6b7f4c55c0e1e451175
| 0.465934 | 3.729508 | false | false | false | false |
mitchsm/nvc
|
test/regress/const1.vhd
| 5 | 474 |
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
gpl-3.0
|
a59cc0b38d2f86d3d210d79fb28482f6
| 0.514768 | 3.361702 | false | false | false | false |
blutsvente/MIX
|
test/results/genwidth/inst_a_e-rtl-a.vhd
| 1 | 3,255 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 16:29:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../genwidth.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
constant width : integer := 9; -- __I_PARAMETER
--
-- Generated Components
--
component inst_aa_e
generic (
-- Generated Generics for Entity inst_aa_e
width : integer := 8
-- End of Generated Generics for Entity inst_aa_e
);
port (
-- Generated Port for Entity inst_aa_e
y_p_i : out std_ulogic_vector(width - 1 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e
generic (
-- Generated Generics for Entity inst_ab_e
width : integer := 8
-- End of Generated Generics for Entity inst_ab_e
);
port (
-- Generated Port for Entity inst_ab_e
y_p0_i : in std_ulogic_vector(width - 1 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
component inst_ac_e
-- No Generated Generics
-- Generated Generics for Entity inst_ac_e
-- End of Generated Generics for Entity inst_ac_e
port (
-- Generated Port for Entity inst_ac_e
defwidth : in std_ulogic_vector(`dwidth - 1 downto 0)
-- End of Generated Port for Entity inst_ac_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal y_c422444 : std_ulogic_vector(width - 1 downto 0);
-- __I_NODRV_I signal y_defwidth : std_ulogic_vector(`dwidth - 1 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
generic map (
width => 9
)
port map (
y_p_i => y_c422444
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
generic map (
width => 9
)
port map (
y_p0_i => y_c422444
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: inst_ac_e
port map (
-- __I_NODRV_I defwidth => __nodrv__/y_defwidth
);
-- End of Generated Instance Port Map for inst_ac
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
8d498aeea37e7f77a736b74e2e0cdf40
| 0.603687 | 3.120805 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_ed_e-rtl-a.vhd
| 1 | 4,633 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ed_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:07 wig Exp $
-- $Date: 2004/04/06 10:50:07 $
-- $Log: inst_ed_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:07 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ed_e
--
architecture rtl of inst_ed_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eda_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eda_e
cgs_ramclk : out std_ulogic;
nreset : out std_ulogic;
nreset_s : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_eda_e
);
end component;
-- ---------
component inst_edb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_edb_e
acg_systime_init : in std_ulogic_vector(30 downto 0);
cgu_scani : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
cgu_scano : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ifu_gpio0_wkup : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ifu_gpio1_wkup : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ifu_gpio2_wkup : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nreset : in std_ulogic;
nreset_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_edb_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal acg_systime_init : std_ulogic_vector(30 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cgs_ramclk : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal gpio_int : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal itm_scani : std_ulogic_vector(70 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_scano : std_ulogic_vector(70 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal vclkl27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
acg_systime_init <= p_mix_acg_systime_init_30_0_gi; -- __I_I_BUS_PORT
p_mix_cgs_ramclk_go <= cgs_ramclk; -- __I_O_BIT_PORT
gpio_int(2 downto 0) <= p_mix_gpio_int_2_0_gi(2 downto 0); -- __I_I_SLICE_PORT
itm_scani(0) <= p_mix_itm_scani_0_0_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_nreset_go <= nreset; -- __I_O_BIT_PORT
p_mix_nreset_s_go <= nreset_s; -- __I_O_BIT_PORT
p_mix_tmi_scano_0_0_go <= tmi_scano(0); -- __I_O_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_vclkl27_go <= vclkl27; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eda
inst_eda: inst_eda_e
port map (
cgs_ramclk => cgs_ramclk, -- ClockSignalsESDRAMInterface
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_eda
-- Generated Instance Port Map for inst_edb
inst_edb: inst_edb_e
port map (
acg_systime_init => acg_systime_init, -- ADPinterfaceScan
cgu_scani => itm_scani(0),
cgu_scano => tmi_scano(0),
ifu_gpio0_wkup => gpio_int(0), -- GPIOWakeUPSignalsInterruptinputs
ifu_gpio1_wkup => gpio_int(1), -- GPIOWakeUPSignalsInterruptinputs
ifu_gpio2_wkup => gpio_int(2), -- GPIOWakeUPSignalsInterruptinputs
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_edb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
e7453b368c7cf233260a0362eca2a7ec
| 0.632851 | 3.008442 | false | false | false | false |
mitchsm/nvc
|
test/regress/shift1.vhd
| 4 | 1,126 |
entity shift1 is
end entity;
architecture test of shift1 is
begin
process is
variable b : bit_vector(3 downto 0);
variable c : bit_vector(0 to 3);
begin
b := "1011";
c := "1011";
assert (b sll 1) = "0110";
assert (c sll 1) = "0110";
assert (b srl 1) = "0101";
assert (c srl 1) = "0101";
assert (b sla 1) = "0111";
assert (c sla 1) = "0111";
assert (b sra 1) = "1101";
assert (c sra 1) = "1101";
assert (b rol 2) = "1110";
assert (c rol 2) = "1110";
assert (b ror 1) = "1101";
assert (c ror 1) = "1101";
assert (b srl -1) = "0110";
assert (c srl -1) = "0110";
assert (b sll -1) = "0101";
assert (c sll -1) = "0101";
assert (b sra -1) = "0111";
assert (c sra -1) = "0111";
assert (b sla -1) = "1101";
assert (c sla -1) = "1101";
assert (b ror -2) = "1110";
assert (c ror -2) = "1110";
assert (b rol -1) = "1101";
assert (c rol -1) = "1101";
wait;
end process;
end architecture;
|
gpl-3.0
|
59cc4d6881880208c11af1dd9ad9d290
| 0.457371 | 3.235632 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/MEM_WB_Register.vhd
| 2 | 2,412 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:26:22 11/22/2013
-- Design Name:
-- Module Name: MEM_WB_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEM_WB_Register is
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_REGS_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
REGS_READ_WRITE_IN : in STD_LOGIC := WRITE_REGS_NO;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_REGS_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
REGS_READ_WRITE_OUT : out STD_LOGIC := WRITE_REGS_NO;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT
);
end MEM_WB_Register;
architecture Behavioral of MEM_WB_Register is
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
NEW_PC_OUT <= NEW_PC_IN;
WRITE_REGS_NUM_OUT <= WRITE_REGS_NUM_IN;
ALU_RESULT_OUT <= ALU_RESULT_IN;
IH_REG_OUT <= IH_REG_IN;
DM_DATA_OUT <= DM_DATA_IN;
REGS_READ_WRITE_OUT <= REGS_READ_WRITE_IN;
REGS_WRITE_DATA_SRC_OUT <= REGS_WRITE_DATA_SRC_IN;
end if;
end process;
end Behavioral;
|
apache-2.0
|
aeddf5c68f6cc23ef052a5e8e0cc3b09
| 0.583748 | 3.286104 | false | false | false | false |
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