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freecores/minimips
|
miniMIPS/src/pps_di.vhd
| 1 | 25,818 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Instruction decoding stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity pps_di is
port (
clock : in std_logic;
reset : in std_logic;
stop_all : in std_logic; -- Unconditionnal locking of the outputs
clear : in std_logic; -- Clear the pipeline stage (nop in the outputs)
-- Asynchronous connexion with the register management and data bypass unit
adr_reg1 : out adr_reg_type; -- Address of the first register operand
adr_reg2 : out adr_reg_type; -- Address of the second register operand
use1 : out std_logic; -- Effective use of operand 1
use2 : out std_logic; -- Effective use of operand 2
stop_di : in std_logic; -- Unresolved detected : send nop in the pipeline
data1 : in bus32; -- Operand register 1
data2 : in bus32; -- Operand register 2
-- Datas from EI stage
EI_adr : in bus32; -- Address of the instruction
EI_instr : in bus32; -- The instruction to decode
EI_it_ok : in std_logic; -- Allow hardware interruptions
-- Synchronous output to EX stage
DI_bra : out std_logic; -- Branch decoded
DI_link : out std_logic; -- A link for that instruction
DI_op1 : out bus32; -- operand 1 for alu
DI_op2 : out bus32; -- operand 2 for alu
DI_code_ual : out alu_ctrl_type; -- Alu operation
DI_offset : out bus32; -- Offset for the address calculation
DI_adr_reg_dest : out adr_reg_type; -- Address of the destination register of the result
DI_ecr_reg : out std_logic; -- Effective writing of the result
DI_mode : out std_logic; -- Address mode (relative to pc or indexed to a register)
DI_op_mem : out std_logic; -- Memory operation request
DI_r_w : out std_logic; -- Type of memory operation (reading or writing)
DI_adr : out bus32; -- Address of the decoded instruction
DI_exc_cause : out bus32; -- Potential exception detected
DI_level : out level_type; -- Availability of the result for the data bypass
DI_it_ok : out std_logic -- Allow hardware interruptions
);
end entity;
architecture rtl of pps_di is
-- Enumeration type used for the micro-code of the instruction
type op_mode_type is (OP_NORMAL, OP_SPECIAL, OP_REGIMM, OP_COP0); -- selection du mode de l'instruction
type off_sel_type is (OFS_PCRL, OFS_NULL, OFS_SESH, OFS_SEXT); -- selection de la valeur de l'offset
type rdest_type is ( D_RT, D_RD, D_31, D_00); -- selection du registre destination
-- Record type containg the micro-code of an instruction
type micro_instr_type is
record
op_mode : op_mode_type; -- Instruction codop mode
op_code : bus6; -- Instruction codop
bra : std_logic; -- Branch instruction
link : std_logic; -- Branch with link : the return address is saved in a register
code_ual : alu_ctrl_type; -- Operation code for the alu
op_mem : std_logic; -- Memory operation needed
r_w : std_logic; -- Read/Write selection in memory
mode : std_logic; -- Address calculation from the current pc ('1') or the alu operand 1 ('0')
off_sel : off_sel_type; -- Offset source : PC(31..28) & Adresse & 00 || 0 || sgn_ext(Imm) & 00 || sgn_ext(Imm)
exc_cause : bus32; -- Unconditionnal exception cause to generate
cop_org1 : std_logic; -- Source register 1 : general register if 0, coprocessor register if 1
cop_org2 : std_logic; -- Source register 2 : general register if 0, coprocessor register if 1
cs_imm1 : std_logic; -- Use of immediat operand 1 instead of register bank
cs_imm2 : std_logic; -- Use of immediat operand 2 instead of register bank
imm1_sel : std_logic; -- Origine of immediat operand 1
imm2_sel : std_logic; -- Origine of immediat operand 2
level : level_type; -- Data availability stage for the bypass
ecr_reg : std_logic; -- Writing the result in a register
bank_des : std_logic; -- Register bank selection : GPR if 0, coprocessor system if 1
des_sel : rdest_type ; -- Destination register address : Rt, Rd, $31, $0
end record;
type micro_code_type is array (natural range <>) of micro_instr_type;
constant micro_code : micro_code_type :=
( -- Instruction decoding in micro-instructions table
(OP_SPECIAL, "100000", '0', '0', OP_ADD , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- ADD
(OP_NORMAL , "001000", '0', '0', OP_ADD , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '1', LVL_EX , '1', '0', D_RT), -- ADDI
(OP_NORMAL , "001001", '0', '0', OP_ADDU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- ADDIU
(OP_SPECIAL, "100001", '0', '0', OP_ADDU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- ADDU
(OP_SPECIAL, "100100", '0', '0', OP_AND , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- AND
(OP_NORMAL , "001100", '0', '0', OP_AND , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- ANDI
(OP_NORMAL , "000100", '1', '0', OP_EQU , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- BEQ
(OP_REGIMM , "000001", '1', '0', OP_LPOS , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BGEZ
(OP_REGIMM , "010001", '1', '1', OP_LPOS , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_31), -- BGEZAL
(OP_NORMAL , "000111", '1', '0', OP_SPOS , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BGTZ
(OP_NORMAL , "000110", '1', '0', OP_LNEG , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BLEZ
(OP_REGIMM , "000000", '1', '0', OP_SNEG , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BLTZ
(OP_REGIMM , "010000", '1', '1', OP_SNEG , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_31), -- BLTZAL
(OP_NORMAL , "000101", '1', '0', OP_NEQU , '0', '0', '1', OFS_SESH, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- BNE
(OP_SPECIAL, "001101", '0', '0', OP_OUI , '0', '0', '0', OFS_PCRL, IT_BREAK, '0', '0', '1', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- BREAK
(OP_COP0 , "000001", '0', '0', OP_OP2 , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_DI , '1', '1', D_00), -- COP0
(OP_NORMAL , "000010", '1', '0', OP_OUI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- J
(OP_NORMAL , "000011", '1', '1', OP_OUI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_31), -- JAL
(OP_SPECIAL, "001001", '1', '1', OP_OUI , '0', '0', '0', OFS_NULL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RD), -- JALR
(OP_SPECIAL, "001000", '1', '0', OP_OUI , '0', '0', '0', OFS_NULL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- JR
(OP_NORMAL , "001111", '0', '0', OP_LUI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- LUI
(OP_NORMAL , "100011", '0', '0', OP_OUI , '1', '0', '0', OFS_SEXT, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_MEM, '1', '0', D_RT), -- LW
(OP_NORMAL , "110000", '0', '0', OP_OUI , '1', '0', '0', OFS_SEXT, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_MEM, '1', '1', D_RT), -- LWC0
(OP_COP0 , "000000", '0', '0', OP_OP2 , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '1', '1', '0', '0', '0', LVL_DI , '1', '0', D_RD), -- MFC0
(OP_SPECIAL, "010000", '0', '0', OP_MFHI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_RD), -- MFHI
(OP_SPECIAL, "010010", '0', '0', OP_MFLO , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '1', '0', '0', LVL_EX , '1', '0', D_RD), -- MFLO
(OP_COP0 , "000100", '0', '0', OP_OP2 , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '0', '0', LVL_DI , '1', '1', D_RD), -- MTC0
(OP_SPECIAL, "010001", '0', '0', OP_MTHI , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- MTHI
(OP_SPECIAL, "010011", '0', '0', OP_MTLO , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- MTLO
(OP_SPECIAL, "011000", '0', '0', OP_MULT , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '0', '0', D_RT), -- MULT
(OP_SPECIAL, "011001", '0', '0', OP_MULTU, '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '0', '0', D_RT), -- MULT
(OP_SPECIAL, "100111", '0', '0', OP_NOR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- NOR
(OP_SPECIAL, "100101", '0', '0', OP_OR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- OR
(OP_NORMAL , "001101", '0', '0', OP_OR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT), -- ORI
(OP_SPECIAL, "000000", '0', '0', OP_SLL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '1', '0', LVL_EX , '1', '0', D_RD), -- SLL
(OP_SPECIAL, "000100", '0', '0', OP_SLL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SLLV
(OP_SPECIAL, "101010", '0', '0', OP_SLT , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SLT
(OP_NORMAL , "001010", '0', '0', OP_SLT , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '1', LVL_EX , '1', '0', D_RT), -- SLTI
(OP_NORMAL , "001011", '0', '0', OP_SLTU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '1', LVL_EX , '1', '0', D_RT), -- SLTIU
(OP_SPECIAL, "101011", '0', '0', OP_SLTU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SLTU
(OP_SPECIAL, "000011", '0', '0', OP_SRA , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '1', '0', LVL_EX , '1', '0', D_RD), -- SRA
(OP_SPECIAL, "000111", '0', '0', OP_SRA , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SRAV
(OP_SPECIAL, "000010", '0', '0', OP_SRL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '1', '0', '1', '0', LVL_EX , '1', '0', D_RD), -- SRL
(OP_SPECIAL, "000110", '0', '0', OP_SRL , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SRLV
(OP_SPECIAL, "100010", '0', '0', OP_SUB , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SUB
(OP_SPECIAL, "100011", '0', '0', OP_SUBU , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- SUBU
(OP_NORMAL , "101011", '0', '0', OP_OP2 , '1', '1', '0', OFS_SEXT, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- SW
(OP_NORMAL , "111000", '0', '0', OP_OP2 , '1', '1', '0', OFS_SEXT, IT_NOEXC, '0', '1', '0', '0', '0', '0', LVL_DI , '0', '0', D_RT), -- SWC0
(OP_SPECIAL, "001100", '0', '0', OP_OUI , '0', '0', '0', OFS_PCRL, IT_SCALL, '0', '0', '1', '1', '0', '0', LVL_DI , '0', '0', D_RT), -- SYSC
(OP_SPECIAL, "100110", '0', '0', OP_XOR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '0', '0', '0', LVL_EX , '1', '0', D_RD), -- XOR
(OP_NORMAL , "001110", '0', '0', OP_XOR , '0', '0', '0', OFS_PCRL, IT_NOEXC, '0', '0', '0', '1', '0', '0', LVL_EX , '1', '0', D_RT) -- XORI
);
-- Preparation of the synchronous outputs
signal PRE_bra : std_logic; -- Branch operation
signal PRE_link : std_logic; -- Branch with link
signal PRE_op1 : bus32; -- operand 1 of the ual
signal PRE_op2 : bus32; -- operand 2 of the ual
signal PRE_code_ual : alu_ctrl_type; -- Alu operation
signal PRE_offset : bus32; -- Address offset for calculation
signal PRE_adr_reg_dest : adr_reg_type; -- Destination register adress for result
signal PRE_ecr_reg : std_logic; -- Writing of result in the bank register
signal PRE_mode : std_logic; -- Address calculation with current pc
signal PRE_op_mem : std_logic; -- Memory access operation instruction
signal PRE_r_w : std_logic; -- Read/write selection in memory
signal PRE_exc_cause : bus32; -- Potential exception cause
signal PRE_level : level_type; -- Result availability stage for bypass
begin
-- Instruction decoding
process (EI_instr, EI_adr, data1, data2)
variable op_code : bus6; -- Effective codop of the instruction
variable op_mode : op_mode_type; -- Instruction mode
variable flag : boolean; -- Is true if valid instruction
variable instr : integer; -- Current micro-instruction adress
-- Instruction fields
variable rs : bus5;
variable rt : bus5;
variable rd : bus5;
variable shamt : bus5;
variable imm : bus16;
variable address : bus26;
begin
-- Selection of the instruction codop and its mode
case EI_instr(31 downto 26) is
when "000000" => -- special mode
op_mode := OP_SPECIAL;
op_code := EI_instr(5 downto 0);
when "000001" => -- regimm mode
op_mode := OP_REGIMM;
op_code := '0' & EI_instr(20 downto 16);
when "010000" => -- cop0 mode
op_mode := OP_COP0;
op_code := '0' & EI_instr(25 downto 21);
when others => -- normal mode
op_mode := OP_NORMAL;
op_code := EI_instr(31 downto 26);
end case;
-- Search the current instruction in the micro-code table
flag := false;
instr := 0;
for i in micro_code'range loop
if micro_code(i).op_mode=op_mode and micro_code(i).op_code=op_code then
flag := true; -- The instruction exists
instr := i; -- Index memorisation
end if;
end loop;
-- Read the instruction field
rs := EI_instr(25 downto 21);
rt := EI_instr(20 downto 16);
rd := EI_instr(15 downto 11);
shamt := EI_instr(10 downto 6);
imm := EI_instr(15 downto 0);
address := EI_instr(25 downto 0);
if not flag then -- Unknown instruction
-- Synchronous output preparation
PRE_bra <= '0'; -- Branch operation
PRE_link <= '0'; -- Branch with link
PRE_op1 <= (others => '0'); -- operand 1 of the ual
PRE_op2 <= (others => '0'); -- operand 2 of the ual
PRE_code_ual <= OP_OUI; -- Alu operation
PRE_offset <= (others => '0'); -- Address offset for calculation
PRE_adr_reg_dest <= (others => '0'); -- Destination register adress for result
PRE_ecr_reg <= '0'; -- Writing of result in the bank register
PRE_mode <= '0'; -- Address calculation with current pc
PRE_op_mem <= '0'; -- Memory access operation instruction
PRE_r_w <= '0'; -- Read/write selection in memory
PRE_exc_cause <= IT_ERINS; -- Potential exception cause
PRE_level <= LVL_DI; -- Result availability stage for bypass
-- Set asynchronous outputs
adr_reg1 <= (others => '0'); -- First operand register
adr_reg2 <= (others => '0'); -- Second operand register
use1 <= '0'; -- Effective use of operand 1
use2 <= '0'; -- Effective use of operand 2
else -- Valid instruction
-- Offset signal preparation
case micro_code(instr).off_sel is
when OFS_PCRL => -- PC(31..28) & Adresse & 00
PRE_offset <= EI_adr(31 downto 28) & address & "00";
when OFS_NULL => -- 0
PRE_offset <= (others => '0');
when OFS_SESH => -- sgn_ext(Imm) & 00
if imm(15)='1' then
PRE_offset <= "11111111111111" & imm & "00";
else
PRE_offset <= "00000000000000" & imm & "00";
end if;
when OFS_SEXT => -- sgn_ext(Imm)
if imm(15)='1' then
PRE_offset <= "1111111111111111" & imm;
else
PRE_offset <= "0000000000000000" & imm;
end if;
end case;
-- Alu operand preparation
if micro_code(instr).cs_imm1='0' then
-- Datas from register banks
PRE_op1 <= data1;
else
-- Immediate datas
if micro_code(instr).imm1_sel='0' then
PRE_op1 <= (others => '0'); -- Immediate operand = 0
else
PRE_op1 <= X"000000" & "000" & shamt; -- Immediate operand = shamt
end if;
end if;
if micro_code(instr).cs_imm2='0' then
-- Datas from register banks
PRE_op2 <= data2;
else
-- Immediate datas
if micro_code(instr).imm2_sel='0' then
PRE_op2 <= X"0000" & imm; -- Immediate operand = imm
else
if imm(15)='1' then -- Immediate operand = sgn_ext(imm)
PRE_op2 <= X"FFFF" & imm;
else
PRE_op2 <= X"0000" & imm;
end if;
end if;
end if;
-- Selection of destination register address
case micro_code(instr).des_sel is
when D_RT => PRE_adr_reg_dest <= micro_code(instr).bank_des & rt;
when D_RD => PRE_adr_reg_dest <= micro_code(instr).bank_des & rd;
when D_31 => PRE_adr_reg_dest <= micro_code(instr).bank_des & "11111";
when D_00 => PRE_adr_reg_dest <= micro_code(instr).bank_des & "00000";
end case;
-- Command signal affectation
PRE_bra <= micro_code(instr).bra; -- Branch operation
PRE_link <= micro_code(instr).link; -- Branch with link
PRE_code_ual <= micro_code(instr).code_ual; -- Alu operation
PRE_ecr_reg <= micro_code(instr).ecr_reg; -- Writing the result in a bank register
PRE_mode <= micro_code(instr).mode; -- Type of calculation for the address with current pc
PRE_op_mem <= micro_code(instr).op_mem; -- Memory operation needed
PRE_r_w <= micro_code(instr).r_w; -- Read/Write in memory selection
PRE_exc_cause <= micro_code(instr).exc_cause; -- Potential cause exception
PRE_level <= micro_code(instr).level;
-- Set asynchronous outputs
adr_reg1 <= micro_code(instr).cop_org1 & rs; -- First operand register address
adr_reg2 <= micro_code(instr).cop_org2 & rt; -- Second operand register address
use1 <= not micro_code(instr).cs_imm1; -- Effective use of operande 1
use2 <= not micro_code(instr).cs_imm2; -- Effective use of operande 2
end if;
end process;
-- Set the synchronous outputs
process (clock)
begin
if clock='1' and clock'event then
if reset='1' then
DI_bra <= '0';
DI_link <= '0';
DI_op1 <= (others => '0');
DI_op2 <= (others => '0');
DI_code_ual <= OP_OUI;
DI_offset <= (others => '0');
DI_adr_reg_dest <= (others => '0');
DI_ecr_reg <= '0';
DI_mode <= '0';
DI_op_mem <= '0';
DI_r_w <= '0';
DI_adr <= (others => '0');
DI_exc_cause <= IT_NOEXC;
DI_level <= LVL_DI;
DI_it_ok <= '0';
elsif stop_all='0' then
if clear='1' or stop_di='1' then
-- Nop instruction
DI_bra <= '0';
DI_link <= '0';
DI_op1 <= (others => '0');
DI_op2 <= (others => '0');
DI_code_ual <= OP_OUI;
DI_offset <= (others => '0');
DI_adr_reg_dest <= (others => '0');
DI_ecr_reg <= '0';
DI_mode <= '0';
DI_op_mem <= '0';
DI_r_w <= '0';
DI_adr <= EI_adr;
DI_exc_cause <= IT_NOEXC;
DI_level <= LVL_DI;
if clear='1' then
DI_it_ok <= '0';
else
DI_it_ok <= EI_it_ok;
end if;
else -- Noraml step
DI_bra <= PRE_bra;
DI_link <= PRE_link;
DI_op1 <= PRE_op1;
DI_op2 <= PRE_op2;
DI_code_ual <= PRE_code_ual;
DI_offset <= PRE_offset;
DI_adr_reg_dest <= PRE_adr_reg_dest;
DI_ecr_reg <= PRE_ecr_reg;
DI_mode <= PRE_mode;
DI_op_mem <= PRE_op_mem;
DI_r_w <= PRE_r_w;
DI_adr <= EI_adr;
DI_exc_cause <= PRE_exc_cause;
DI_level <= PRE_level;
DI_it_ok <= EI_it_ok;
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
f21a98e827f6e0f02b9546fb3c7da6da
| 0.444574 | 3.363471 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_semaphore_cyclic.vhd
| 1 | 2,449 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_semaphore_cyclic IS
END tb_semaphore_cyclic;
ARCHITECTURE behavior OF tb_semaphore_cyclic IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT semaphore_cyclic
generic (N_BITS : integer);
port (Clk : in std_logic;
Rst : in std_logic;
Request : in std_logic_vector (N_BITS-1 downto 0);
Grant : out std_logic_vector (N_BITS-1 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal Request : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal Grant : std_logic_vector(2 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: semaphore_cyclic
GENERIC MAP (N_BITS => 3)
PORT MAP (
Clk => Clk,
Rst => Rst,
Request => Request,
Grant => Grant
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
a1 :process
begin
Request(0) <= not Request(0);
wait for Clk_period * 5;
end process;
a2 :process
begin
Request(1) <= not Request(1);
wait for Clk_period * 6;
end process;
a3 :process
begin
Request(2) <= not Request(2);
wait for Clk_period * 7;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
ec5bc2c4e466e6522ebde539b2eb3c6b
| 0.642303 | 3.677177 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/bcf_bram32.vhd
| 1 | 2,573 |
----------------------------------------------------------------------------------
-- Company: University of Wuppertal
-- Engineer: Timon Heim
-- E-Mail: [email protected]
--
-- Project: IBL BOC firmware
-- Module: Block RAM
-- Description: Block RAM with Wishbone Slave Interface
----------------------------------------------------------------------------------
-- Changelog:
-- 20.02.2011 - Initial Version
----------------------------------------------------------------------------------
-- TODO:
-- 20.02.2011 - Add DMA capability
----------------------------------------------------------------------------------
-- Address Map:
-- 0x020 to 0x02F
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library work;
--use work.bocpack.all;
entity bram_wbs32 is
generic (
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 32
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic
);
end bram_wbs32;
architecture Behavioral of bram_wbs32 is
type ram_type is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM: ram_type;
signal ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
ADDR <= wb_adr_i(ADDR_WIDTH-1 downto 0);
bram: process (clk, rst)
begin
if (rst ='1') then
wb_ack_o <= '0';
for i in 0 to 2**ADDR_WIDTH-1 loop
RAM(i) <= conv_std_logic_vector(i,RAM(i)'length); -- "DEAD0001BEEF0001"
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH/2) <= conv_std_logic_vector(i,RAM(i)'length/2);
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH-4*4) <= x"DEAD";
RAM(i)(DATA_WIDTH-1-DATA_WIDTH/2 downto DATA_WIDTH-4*4-DATA_WIDTH/2) <= x"BEEF";
end loop;
elsif (clk'event and clk = '1') then
if (wb_stb_i = '1' and wb_cyc_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
RAM(conv_integer(ADDR)) <= wb_dat_i;
end if;
wb_dat_o <= RAM(conv_integer(ADDR)) ;
else
wb_ack_o <= '0';
end if;
end if;
end process bram;
end Behavioral;
|
gpl-3.0
|
84668d1a5d3bd5cdbf118cf7a8aa98d5
| 0.518072 | 3.088836 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/fe65p2_addon.vhd
| 2 | 16,786 |
--------------------------------------------
-- Project: FE65-P2 addon
-- Author: Timon Heim ([email protected])
-- Description: Attaches to serial port and controls FE65-P2 adapter
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity fe65p2_addon is
port (
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
-- TO FMC
clk_bx_o : out std_logic;
trig_o : out std_logic;
clk_cnfg_o : out std_logic;
en_pix_sr_cnfg_o : out std_logic;
ld_cnfg_o : out std_logic;
si_cnfg_o : out std_logic;
pix_d_cnfg_o : out std_logic;
clk_data_o : out std_logic;
rst_0_o : out std_logic;
rst_1_o : out std_logic;
dac_sclk_o : out std_logic;
dac_sdi_o : out std_logic;
dac_ld_o : out std_logic;
dac_cs_o : out std_logic;
inj_sw_o : out std_logic
);
end fe65p2_addon;
architecture behavioral of fe65p2_addon is
-- System signals
signal sys_rst : std_logic;
signal clk_40 : std_logic;
-- clocks
signal clk_bx_t : std_logic;
signal clk_cnfg_t : std_logic;
signal clk_data_t : std_logic;
signal en_bx_clk : std_logic;
signal en_conf_clk : std_logic;
signal en_data_clk : std_logic;
-- cmd deserialiser
signal yarr_cmd : std_logic;
signal cmd_count : unsigned(7 downto 0);
signal cmd_valid : std_logic;
signal cmd_sreg : std_logic_vector(31 downto 0);
-- cmd decoder
signal new_cmd : std_logic;
signal adr : std_logic_vector(15 downto 0);
signal payload : std_logic_vector(15 downto 0);
-- registers
signal conf_reg : std_logic_vector(159 downto 0);
signal pix_reg : std_logic_vector(255 downto 0);
signal static_reg : std_logic_vector(15 downto 0);
signal pulser_reg : std_logic_vector(15 downto 0);
signal latency : unsigned(8 downto 0);
signal dac_setting : std_logic_vector(15 downto 0);
signal trig_multiplier : unsigned(3 downto 0);
signal delay_setting : std_logic_vector(7 downto 0);
-- config serialiser
signal conf_load : std_logic_vector(7 downto 0);
signal conf_sreg_cnt : unsigned(7 downto 0);
signal conf_sreg : std_logic_vector(144 downto 0);
signal pix_sreg_cnt : unsigned(8 downto 0);
signal pix_sreg : std_logic_vector(255 downto 0);
signal en_pix_reg : std_logic;
-- inject & trigger
signal dig_inj : std_logic;
signal trigger : std_logic;
signal pulser_trig_t : std_logic_vector(40 downto 0);
signal inject_cnt : unsigned(8 downto 0);
signal trig_cnt : unsigned(4 downto 0);
signal en_inj : std_logic;
signal inj_sw_t : std_logic;
-- DAC
signal dac_load : std_logic_vector(15 downto 0);
signal dac_cs_t : std_logic;
signal dac_sreg_cnt : unsigned(7 downto 0);
signal dac_sreg : std_logic_vector(15 downto 0);
signal dac_sclk_t : std_logic;
component delay_line
generic (
width : positive := 8);
port (
clk : in std_logic;
rst : in std_logic;
input : IN std_logic;
output : OUT std_logic;
setting : IN std_logic_vector(width-1 downto 0) );
end component delay_line;
begin
sys_rst <= not rst_n;
clk_40 <= clk_i;
clk_bx_t <= clk_40;
clk_cnfg_t <= clk_40;
clk_data_t <= clk_rx_i;
-- Outputs
trig_o <= trigger;
en_pix_sr_cnfg_o <= en_pix_reg;
ld_cnfg_o <= conf_load(4) or conf_load(5) or conf_load(6) or conf_load(7) or dig_inj;
si_cnfg_o <= conf_sreg(144) or pix_sreg(255);
dac_sclk_o <= dac_sclk_t;
dac_sdi_o <= dac_sreg(15);
dac_ld_o <= not (dac_load(15) or dac_load(14) or dac_load(13) or dac_load(12) or dac_load(11) or
dac_load(10) or dac_load(9) or dac_load(8) or dac_load(7) or dac_load(6) or dac_load(5));
dac_cs_o <= dac_cs_t;
inj_sw_t <= '0' when (unsigned(pulser_trig_t) = 0) else '1';
-- Fine delay for pulser
cmp_inj_delay: delay_line
GENERIC MAP(
width => 7)
PORT MAP(
clk => clk_40,
rst => sys_rst,
input => inj_sw_t,
output => inj_sw_o,
setting => delay_setting(6 downto 0)
);
-- Static settings
en_data_clk <= static_reg(0);
en_bx_clk <= static_reg(1);
pix_d_cnfg_o <= static_reg(2);
en_inj <= static_reg(3);
rst_0_o <= not static_reg(4);
rst_1_o <= not static_reg(5);
yarr_cmd <= serial_in;
cmd_deserialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
cmd_sreg <= (others => '0');
cmd_count <= (others => '0');
cmd_valid <= '0';
elsif rising_edge(clk_40) then
cmd_sreg <= cmd_sreg(30 downto 0) & yarr_cmd;
if (cmd_count = TO_UNSIGNED(31,8)) then
cmd_count <= (others => '0');
cmd_valid <= '1';
elsif (cmd_count > 0) then
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
elsif (yarr_cmd = '1' and cmd_count = TO_UNSIGNED(0,8)) then -- start bit
cmd_count <= cmd_count + 1;
cmd_valid <= '0';
else
cmd_valid <= '0';
end if;
end if;
end process cmd_deserialiser;
cmd_decoder: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
new_cmd <= '0';
adr <= (others => '0');
payload <= (others => '0');
conf_reg <= (others => '0');
pix_reg <= (others => '0');
static_reg <= (others => '0');
pulser_reg <= (others => '0');
latency <= (others => '0');
dac_setting <= (others => '0');
trig_multiplier <= x"5";
delay_setting <= (others => '0');
elsif rising_edge(clk_40) then
new_cmd <= '0';
if (cmd_valid = '1') then
adr <= '0' & cmd_sreg(30 downto 16);
payload <= cmd_sreg(15 downto 0);
new_cmd <= '1';
end if;
-- pulses 1 clk cycle
pulser_reg <= (others => '0');
-- [0] : start shift conf reg
-- [1] : inject & trigger
-- [2] : start shift pixel reg
-- [3] : pulse load line
-- [4] : shift SR by one
-- [5] : load DAC
-- [6] : switch pulser
-- [7] : trigger (no inject)
if (new_cmd = '1') then
case (adr) is
-- Global Shift reg (145 bit)
when x"0000" => conf_reg(0) <= payload(0);
when x"0001" => conf_reg(1) <= payload(0);
when x"0002" => conf_reg(2) <= payload(0);
when x"0003" => conf_reg(6 downto 3) <= payload(3 downto 0);
when x"0004" => conf_reg(8 downto 7) <= payload(1 downto 0);
when x"0005" => conf_reg(9) <= payload(0);
when x"0006" => conf_reg(10) <= payload(0);
when x"0007" => conf_reg(11) <= payload(0);
when x"0008" => conf_reg(20 downto 12) <= payload(8 downto 0);
when x"0009" => conf_reg(36 downto 21) <= payload(15 downto 0);
when x"000a" => conf_reg(52 downto 37) <= payload(15 downto 0);
when x"000b" => conf_reg(56 downto 53) <= payload(3 downto 0);
when x"000c" => conf_reg(64 downto 57) <= payload(7 downto 0);
when x"000d" => conf_reg(72 downto 65) <= payload(7 downto 0);
when x"000e" => conf_reg(80 downto 73) <= payload(7 downto 0);
when x"000f" => conf_reg(88 downto 81) <= payload(7 downto 0);
when x"0010" => conf_reg(96 downto 89) <= payload(7 downto 0);
when x"0011" => conf_reg(104 downto 97) <= payload(7 downto 0);
when x"0012" => conf_reg(112 downto 105) <= payload(7 downto 0);
when x"0013" => conf_reg(120 downto 113) <= payload(7 downto 0);
when x"0014" => conf_reg(128 downto 121) <= payload(7 downto 0);
when x"0015" => conf_reg(136 downto 129) <= payload(7 downto 0);
when x"0016" => conf_reg(144 downto 137) <= payload(7 downto 0);
-- Pixel Shift reg (256 bit)
when x"0020" => pix_reg(15 downto 0) <= payload(15 downto 0);
when x"0021" => pix_reg(31 downto 16) <= payload(15 downto 0);
when x"0022" => pix_reg(47 downto 32) <= payload(15 downto 0);
when x"0023" => pix_reg(63 downto 48) <= payload(15 downto 0);
when x"0024" => pix_reg(79 downto 64) <= payload(15 downto 0);
when x"0025" => pix_reg(95 downto 80) <= payload(15 downto 0);
when x"0026" => pix_reg(111 downto 96) <= payload(15 downto 0);
when x"0027" => pix_reg(127 downto 112) <= payload(15 downto 0);
when x"0028" => pix_reg(143 downto 128) <= payload(15 downto 0);
when x"0029" => pix_reg(159 downto 144) <= payload(15 downto 0);
when x"002a" => pix_reg(175 downto 160) <= payload(15 downto 0);
when x"002b" => pix_reg(191 downto 176) <= payload(15 downto 0);
when x"002c" => pix_reg(207 downto 192) <= payload(15 downto 0);
when x"002d" => pix_reg(223 downto 208) <= payload(15 downto 0);
when x"002e" => pix_reg(239 downto 224) <= payload(15 downto 0);
when x"002f" => pix_reg(255 downto 240) <= payload(15 downto 0);
-- Modes
when x"0030" => static_reg <= payload;
when x"0031" => pulser_reg <= payload;
when x"0032" => latency <= unsigned(payload(8 downto 0));
when x"0033" => dac_setting <= payload(15 downto 0);
when x"0034" => trig_multiplier <= unsigned(payload(3 downto 0));
when x"0035" => delay_setting <= payload(7 downto 0);
when others =>
end case;
end if;
end if;
end process cmd_decoder;
conf_serialiser: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
conf_sreg_cnt <= (others => '0');
conf_sreg <= (others => '0');
en_conf_clk <= '0';
conf_load <= (others => '0');
pix_sreg_cnt <= (others => '0');
pix_sreg <= (others => '0');
en_pix_reg <= '0';
elsif rising_edge(clk_40) then
-- Configuration serialiser
conf_load(0) <= '0';
if (pulser_reg(0) = '1') then
conf_sreg_cnt <= TO_UNSIGNED(145, 8);
conf_sreg <= conf_reg(144 downto 0);
en_conf_clk <= '1';
elsif (conf_sreg_cnt = TO_UNSIGNED(1, 8)) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_load(0) <= '1';
en_conf_clk <= '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
elsif (conf_sreg_cnt > 0) then
conf_sreg <= conf_sreg(143 downto 0) & '0';
conf_sreg_cnt <= conf_sreg_cnt - 1;
en_conf_clk <= '1';
end if;
-- Pulse load line
if (pulser_reg(3) = '1') then
conf_load(0) <= '1';
end if;
-- Pixel sreg serialiser
en_pix_reg <= '0';
if (pulser_reg(2) = '1') then
pix_sreg_cnt <= TO_UNSIGNED(256, 9);
pix_sreg <= pix_reg(255 downto 0);
en_conf_clk <= '1';
en_pix_reg <= '1';
elsif (pix_sreg_cnt = TO_UNSIGNED(1, 9)) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
--conf_load <= '1';
en_pix_reg <= '0';
en_conf_clk <= '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
elsif (pix_sreg_cnt > 0) then
pix_sreg <= pix_sreg(254 downto 0) & '0';
pix_sreg_cnt <= pix_sreg_cnt - 1;
en_conf_clk <= '1';
en_pix_reg <= '1';
end if;
conf_load(1) <= conf_load(0);
conf_load(2) <= conf_load(1);
conf_load(3) <= conf_load(2);
conf_load(4) <= conf_load(3);
conf_load(5) <= conf_load(4);
conf_load(6) <= conf_load(5);
conf_load(7) <= conf_load(6);
end if;
end process conf_serialiser;
inject_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
inject_cnt <= (others => '0');
trig_cnt <= (others => '0');
elsif rising_edge(clk_40) then
dig_inj <= '0';
trigger <= '0';
pulser_trig_t(0) <= '0';
if (pulser_reg(1) = '1') then
inject_cnt <= TO_UNSIGNED((TO_INTEGER(latency) + 2), 9); -- Latency vonfig
if (en_inj = '0') then
dig_inj <= '1';
else
pulser_trig_t(0) <= '1';
end if;
elsif (inject_cnt > ((TO_INTEGER(latency) - 6))) then -- TODO change to pulse length
if (en_inj = '0') then
dig_inj <= '1';
end if;
inject_cnt <= inject_cnt - 1;
elsif ((inject_cnt <= (TO_INTEGER(trig_multiplier))) and inject_cnt > 1) then -- TODO change to trigger multiplier
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt = 1) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
trigger <= '1';
elsif (inject_cnt > 0) then
inject_cnt <= inject_cnt - 1;
dig_inj <= '0';
end if;
if (pulser_reg(7) = '1') then
trig_cnt <= TO_UNSIGNED((TO_INTEGER(trig_multiplier) + 1), 5);
elsif (trig_cnt > 0) then
trig_cnt <= trig_cnt - 1;
trigger <= '1';
end if;
end if;
end process inject_proc;
pulse_delay: for I in 1 to pulser_trig_t'length-1 generate
begin
delay_proc: process(clk_40)
begin
if (sys_rst = '1') then
pulser_trig_t(I) <= '0';
elsif rising_edge(clk_40) then
pulser_trig_t(I) <= pulser_trig_t(I-1);
end if;
end process delay_proc;
end generate;
dac_proc: process(clk_40, sys_rst)
begin
if (sys_rst = '1') then
dac_load <= (others => '0');
dac_cs_t <= '1';
dac_sreg_cnt <= (others => '0');
dac_sreg <= (others => '0');
dac_sclk_t <= '0';
elsif rising_edge(clk_40) then
dac_load(0) <= '0';
dac_cs_t <= '1';
if (pulser_reg(5) = '1') then
dac_sreg_cnt <= TO_UNSIGNED(160, 8);
dac_sreg <= dac_setting(15 downto 0);
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt = TO_UNSIGNED(1, 8)) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
dac_load(0) <= '1';
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_sclk_t <= '0';
dac_cs_t <= '0';
elsif (dac_sreg_cnt > 0) then
if ((dac_sreg_cnt mod 10) = 1) then
dac_sreg <= dac_sreg(14 downto 0) & '0';
end if;
if ((dac_sreg_cnt mod 5) = 1) then
dac_sclk_t <= not dac_sclk_t;
end if;
dac_sreg_cnt <= dac_sreg_cnt - 1;
dac_cs_t <= '0';
end if;
dac_load(1) <= dac_load(0);
dac_load(2) <= dac_load(1);
dac_load(3) <= dac_load(2);
dac_load(4) <= dac_load(3);
dac_load(5) <= dac_load(4);
dac_load(6) <= dac_load(5);
dac_load(7) <= dac_load(6);
dac_load(8) <= dac_load(7);
dac_load(9) <= dac_load(8);
dac_load(10) <= dac_load(9);
dac_load(11) <= dac_load(10);
dac_load(12) <= dac_load(11);
dac_load(13) <= dac_load(12);
dac_load(14) <= dac_load(13);
dac_load(15) <= dac_load(14);
end if;
end process dac_proc;
-- clock ddr2 buffers
conf_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_cnfg_o, -- 1-bit output data
C0 => clk_cnfg_t, -- 1-bit clock input
C1 => not clk_cnfg_t, -- 1-bit clock input
CE => en_conf_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
bx_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_bx_o, -- 1-bit output data
C0 => clk_bx_t, -- 1-bit clock input
C1 => not clk_bx_t, -- 1-bit clock input
CE => en_bx_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
data_clk_buf : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_data_o, -- 1-bit output data
C0 => clk_data_T, -- 1-bit clock input
C1 => not clk_data_t, -- 1-bit clock input
CE => en_data_clk, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => sys_rst, -- 1-bit reset input
S => open -- 1-bit set input
);
end behavioral;
|
gpl-3.0
|
ae7a420a699f356a6c2c578de7f5f9bb
| 0.541582 | 2.954241 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_phy_tx.vhd
| 1 | 3,055 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_phy_tx IS
END tb_phy_tx;
ARCHITECTURE behavior OF tb_phy_tx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT phy_tx
PORT(
clk : IN std_logic;
rst : IN std_logic;
PhyTxd : OUT std_logic_vector(3 downto 0);
PhyTxEn : OUT std_logic;
PhyTxClk : IN std_logic;
Led : OUT std_logic_vector(1 downto 0);
data : IN std_logic_vector(7 downto 0);
busPkt : IN std_logic;
busDesc : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal PhyTxClk : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal busPkt : std_logic := '0';
signal busDesc : std_logic := '0';
--Outputs
signal PhyTxd : std_logic_vector(3 downto 0);
signal PhyTxEn : std_logic;
signal Led : std_logic_vector(1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant PhyTxClk_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: phy_tx PORT MAP (
clk => clk,
rst => rst,
PhyTxd => PhyTxd,
PhyTxEn => PhyTxEn,
PhyTxClk => PhyTxClk,
Led => Led,
data => data,
busPkt => busPkt,
busDesc => busDesc
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
PhyTxClk_process :process
begin
PhyTxClk <= '0';
-- F-up the timing slightly
wait for PhyTxClk_period/2 - 1ns;
PhyTxClk <= '1';
wait for PhyTxClk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
data <= X"00";
busDesc <= '0';
busPkt <= '0';
wait for 5 ns;
rst <= '0';
wait for clk_period*4;
data <= X"A5";
busDesc <= '1';
busPkt <= '0';
wait for clk_period*4;
busDesc <= '0';
busPkt <= '1';
-- insert stimulus here
wait for clk_period*10;
data <= X"00";
busDesc <= '0';
busPkt <= '0';
wait;
end process;
END;
|
gpl-3.0
|
753c5ede9661056600fbc93f27b302f4
| 0.602291 | 3.589894 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/gn4124-core/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
| 2 | 22,920 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_pll_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n clock receiver modulefor serdes factors
-- from 2 to 8
-- Instantiates necessary clock buffers and PLL
-- Contains state machine to calibrate clock input delay line,
-- and perform bitslip if required.
-- Takes in 1 bit of differential data and deserialises this to
-- n bits for where this data is required
-- data is received LSB first
-- 0, 1, 2 ......
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_1_to_n_clk_pll_s2_diff is
generic (
PLLD : integer := 1; -- Parameter to set division for PLL
PLLX : integer := 2; -- Parameter to set multiplier for PLL (7 for video links, 2 for DDR etc)
CLKIN_PERIOD : real := 5.000; -- clock period (ns) of input clock on clkin_p
S : integer := 2; -- Parameter to set the serdes factor 1..8
BS : boolean := false; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic; -- Input from LVDS receiver pin
clkin_n : in std_logic; -- Input from LVDS receiver pin
reset : in std_logic; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0); -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0); -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic; -- IO Clock network
rx_serdesstrobe : out std_logic; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic; -- Global clock
rx_pll_lckd : out std_logic; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0); -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end serdes_1_to_n_clk_pll_s2_diff;
architecture arch_serdes_1_to_n_clk_pll_s2_diff of serdes_1_to_n_clk_pll_s2_diff is
signal P_clk : std_logic; -- P clock out to BUFIO2
signal buf_pll_fb_clk : std_logic; -- PLL feedback clock into BUFIOFB
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal mdataout : std_logic_vector(7 downto 0); --
signal cascade : std_logic; --
signal pd_edge : std_logic; --
signal busys : std_logic; --
signal busym : std_logic; --
signal rx_clk_in : std_logic; --
signal feedback : std_logic; --
signal buf_P_clk : std_logic; --
signal iob_data_in : std_logic; --
signal rx_bufg_pll_x1_int : std_logic;
signal rxioclk_int : std_logic;
signal rx_serdesstrobe_int : std_logic;
signal rx_pllout_xs_int : std_logic;
signal rx_pllout_x1 : std_logic;
signal rx_pll_lckd_int : std_logic;
signal state : integer range 0 to 9;
signal bslip : std_logic;
signal count : std_logic_vector(2 downto 0);
signal busyd : std_logic;
signal counter : std_logic_vector(11 downto 0);
signal clk_iserdes_data : std_logic_vector(S-1 downto 0);
signal cal_clk : std_logic;
signal rst_clk : std_logic;
signal rx_bufplllckd : std_logic;
signal not_rx_bufpll_lckd : std_logic;
signal busy_clk : std_logic;
signal enable : std_logic;
constant RX_SWAP_CLK : std_logic := '0'; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
rx_bufg_pll_x1 <= rx_bufg_pll_x1_int;
rxioclk <= rxioclk_int;
rx_serdesstrobe <= rx_serdesstrobe_int;
rx_pllout_xs <= rx_pllout_xs_int;
rx_pll_lckd <= rx_pll_lckd_int;
bitslip <= bslip;
iob_clk_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in);
iob_data_in <= rx_clk_in xor RX_SWAP_CLK; -- Invert clock as required
busy_clk <= busym;
datain <= clk_iserdes_data;
-- Bitslip and CAL state machine
process (rx_bufg_pll_x1_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
state <= 0;
enable <= '0';
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
elsif rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
busyd <= busy_clk;
if counter(5) = '1' then
enable <= '1';
end if;
if counter(11) = '1' then
state <= 0;
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
else
counter <= counter + 1;
if state = 0 and enable = '1' and busyd = '0' then
state <= 1;
elsif state = 1 then -- cal high
cal_clk <= '1'; state <= 2;
elsif state = 2 and busyd = '1' then -- wait for busy high
cal_clk <= '0'; state <= 3; -- cal low
elsif state = 3 and busyd = '0' then -- wait for busy low
rst_clk <= '1'; state <= 4; -- rst high
elsif state = 4 then -- rst low
rst_clk <= '0'; state <= 5;
elsif state = 5 and busyd = '0' then -- wait for busy low
state <= 6;
count <= "000";
elsif state = 6 then -- hang around
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 7 then
if BS = true and clk_iserdes_data /= pattern1 and clk_iserdes_data /= pattern2 then
bslip <= '1'; -- bitslip needed
state <= 8;
count <= "000";
else
state <= 9;
end if;
elsif state = 8 then
bslip <= '0'; -- bitslip low
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 9 then -- repeat after a delay
state <= 9;
end if;
end if;
end if;
end process;
loop0 : for i in 0 to (S - 1) generate -- Limit the output data bus to the most significant 'S' number of bits
clk_iserdes_data(i) <= mdataout(8+i-S);
end generate;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk_int, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x1_int, -- Fabric clock (GCLK) for control signals
CAL => cal_clk, -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => rst_clk, -- Reset delay line to 1/2 max in this case
BUSY => busym) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- <DEFAULT>, FIXED, VARIABLE
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
P_clk_bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => P_clk, -- P_clk input from IDELAY
IOCLK => open, -- Output Clock
DIVCLK => buf_P_clk, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
P_clk_bufio2fb_inst : BUFIO2FB generic map(
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => feedback, -- PLL generated Clock
O => buf_pll_fb_clk) ; -- PLL Output Feedback Clock
iserdes_m : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting in BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => pd_edge,
BITSLIP => bslip,
FABRICOUT => open,
DFB => open,
CFB0 => open,
CFB1 => open,
Q4 => mdataout(7),
Q3 => mdataout(6),
Q2 => mdataout(5),
Q1 => mdataout(4),
VALID => open,
INCDEC => open,
SHIFTOUT => cascade);
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => cascade,
BITSLIP => bslip,
FABRICOUT => open,
DFB => P_clk,
CFB0 => feedback,
CFB1 => open,
Q4 => mdataout(3),
Q3 => mdataout(2),
Q2 => mdataout(1),
Q1 => mdataout(0),
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge);
rx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 90.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => 7, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => 7, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => 7, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
-- COMPENSATION => "SOURCE_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
CLK_FEEDBACK => "CLKOUT0",
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => open, -- general output feedback signal
CLKOUT0 => rx_pllout_xs_int, -- x7 clock for transmitter
CLKOUT1 => open,
CLKOUT2 => rx_pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open, -- one of six general clock output signals
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => rx_pll_lckd_int, -- active high pll lock signal
CLKFBIN => buf_pll_fb_clk, -- clock feedback input
CLKIN1 => buf_P_clk, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_135 : BUFG port map (I => rx_pllout_x1, O => rx_bufg_pll_x1_int);
rx_bufpll_inst : BUFPLL generic map(
DIVIDE => S) -- PLLIN0 divide-by value to produce rx_serdesstrobe (1 to 8); default 1
port map (
PLLIN => rx_pllout_xs_int, -- PLL Clock input
GCLK => rx_bufg_pll_x1_int, -- Global Clock input
LOCKED => rx_pll_lckd_int, -- Clock0 locked input
IOCLK => rxioclk_int, -- Output PLL Clock
LOCK => rx_bufplllckd, -- BUFPLL Clock and strobe locked
serdesstrobe => rx_serdesstrobe_int) ; -- Output SERDES strobe
rx_bufpll_lckd <= rx_pll_lckd_int and rx_bufplllckd;
not_rx_bufpll_lckd <= not (rx_pll_lckd_int and rx_bufplllckd);
end arch_serdes_1_to_n_clk_pll_s2_diff;
|
gpl-3.0
|
271bf0ebe16ba6cdaf44c0b1122e69d1
| 0.502356 | 4.177907 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
bus_tail_strip.vhd
| 1 | 2,006 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Remove last @N_BYTES from data flying through Bus
entity bus_tail_strip is
generic (N_BYTES : integer);
port (Clk : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
PktOut : out std_logic;
DataOut : out std_logic_vector(7 downto 0));
end bus_tail_strip;
-- Operation:
-- Delay all signals and "and" incoming @PktIn with @PktOut to cut it early.
-- NOTE: input is registered which may not be necessary. Remove clocking of
-- delay*(0) to stop registering input.
architecture Behavioral of bus_tail_strip is
type byte_vec is array (0 to N_BYTES) of std_logic_vector(7 downto 0);
signal delayByte : byte_vec;
signal delayPkt : std_logic_vector(0 to N_BYTES);
begin
delayByte(0) <= DataIn when rising_edge(Clk);
delayPkt(0) <= PktIn when rising_edge(Clk);
delay_path : for i in 0 to N_BYTES - 1
generate
delayByte(i + 1) <= delayByte(i) when rising_edge(Clk);
delayPkt(i + 1) <= delayPkt(i) when rising_edge(Clk);
end generate delay_path;
DataOut <= delayByte(N_BYTES);
PktOut <= delayPkt(0) and delayPkt(N_BYTES);
end Behavioral;
|
gpl-3.0
|
f3c4a6d23acf969d54ecc0e80276846e
| 0.685942 | 3.640653 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/decode_8b10b/decode_8b10b_top.vhd
| 1 | 12,828 |
-------------------------------------------------------------------------------
--
-- Module : decode_8b10b_top.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Core wrapper file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY decode_8b10b;
USE decode_8b10b.decode_8b10b_pkg.ALL;
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
ENTITY decode_8b10b_top IS
GENERIC (
C_DECODE_TYPE : INTEGER := 0;
C_HAS_BPORTS : INTEGER := 0;
C_HAS_CE : INTEGER := 0;
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_SINIT : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_SINIT_VAL : STRING(1 TO 10) := "0000000000";
C_SINIT_VAL_B : STRING(1 TO 10) := "0000000000"
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
--------------------------------------------------------------------------------
-- Port Definitions:
--------------------------------------------------------------------------------
-- Mandatory Pins
-- CLK : Clock Input
-- DIN : Encoded Symbol Input
-- DOUT : Data Output, decoded data byte
-- KOUT : Command Output
-------------------------------------------------------------------------
-- Optional Pins
-- CE : Clock Enable
-- CE_B : Clock Enable (B port)
-- CLK_B : Clock Input (B port)
-- DIN_B : Encoded Symbol Input (B port)
-- DISP_IN : Disparity Input (running disparity in)
-- DISP_IN_B : Disparity Input (running disparity in) (B port)
-- SINIT : Synchronous Initialization. Resets core to known state.
-- SINIT_B : Synchronous Initialization. Resets core to known state.
-- (B port)
-- CODE_ERR : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set.
-- CODE_ERR_B : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set. (B port)
-- DISP_ERR : Disparity Error
-- DISP_ERR_B : Disparity Error (B port)
-- DOUT_B : Data Output, decoded data byte (B port)
-- KOUT_B : Command Output (B port)
-- ND : New Data
-- ND_B : New Data (B port)
-- RUN_DISP : Running Disparity
-- RUN_DISP_B : Running Disparity (B port)
-- SYM_DISP : Symbol Disparity
-- SYM_DISP_B : Symbol Disparity (B port)
-------------------------------------------------------------------------
END decode_8b10b_top;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_top IS
CONSTANT SINIT_DOUT : STRING(1 TO 8) := C_SINIT_VAL(1 TO 8);
CONSTANT SINIT_DOUT_B : STRING(1 TO 8) := C_SINIT_VAL_B(1 TO 8);
CONSTANT SINIT_RD : INTEGER := calc_init_val_rd(C_SINIT_VAL);
-- converts C_SINIT_VAL string to integer
CONSTANT SINIT_RD_B : INTEGER := calc_init_val_rd(C_SINIT_VAL_B);
-- converts C_SINIT_VAL_B string to integer
-- If C_HAS_BPORTS=1, the optional B ports are configured the same way as the
-- optional A ports. Otherwise, all the B ports are disabled.
CONSTANT C_HAS_CE_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_CE);
CONSTANT C_HAS_CODE_ERR_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_CODE_ERR);
CONSTANT C_HAS_DISP_ERR_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_DISP_ERR);
CONSTANT C_HAS_DISP_IN_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_DISP_IN);
CONSTANT C_HAS_ND_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_ND);
CONSTANT C_HAS_RUN_DISP_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_RUN_DISP);
CONSTANT C_HAS_SINIT_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_SINIT);
CONSTANT C_HAS_SYM_DISP_B : INTEGER := has_bport(C_HAS_BPORTS, C_HAS_SYM_DISP);
-------------------------------------------------------------------------------
-- BEGIN ARCHITECTURE
-------------------------------------------------------------------------------
BEGIN
dec : ENTITY decode_8b10b.decode_8b10b_rtl
GENERIC MAP (
C_DECODE_TYPE => C_DECODE_TYPE,
C_ELABORATION_DIR => "./../../src/",
C_HAS_BPORTS => C_HAS_BPORTS,
C_HAS_CE => C_HAS_CE,
C_HAS_CE_B => C_HAS_CE_B,
C_HAS_CODE_ERR => C_HAS_CODE_ERR,
C_HAS_CODE_ERR_B => C_HAS_CODE_ERR_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_IN_B => C_HAS_DISP_IN_B,
C_HAS_ND => C_HAS_ND,
C_HAS_ND_B => C_HAS_ND_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B,
C_HAS_SINIT => C_HAS_SINIT,
C_HAS_SINIT_B => C_HAS_SINIT_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B,
C_SINIT_DOUT => SINIT_DOUT,
C_SINIT_DOUT_B => SINIT_DOUT_B,
C_SINIT_KOUT => 0,
C_SINIT_KOUT_B => 0,
C_SINIT_RUN_DISP => SINIT_RD,
C_SINIT_RUN_DISP_B => SINIT_RD_B
)
PORT MAP(
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
KOUT => KOUT,
CE => CE,
CE_B => CE_B,
CLK_B => CLK_B,
DIN_B => DIN_B,
DISP_IN => DISP_IN,
DISP_IN_B => DISP_IN_B,
SINIT => SINIT,
SINIT_B => SINIT_B,
CODE_ERR => CODE_ERR,
CODE_ERR_B => CODE_ERR_B,
DISP_ERR => DISP_ERR,
DISP_ERR_B => DISP_ERR_B,
DOUT_B => DOUT_B,
KOUT_B => KOUT_B,
ND => ND,
ND_B => ND_B,
RUN_DISP => RUN_DISP,
RUN_DISP_B => RUN_DISP_B,
SYM_DISP => SYM_DISP,
SYM_DISP_B => SYM_DISP_B
);
--------------------------------------------------------------------------------
-- Generic Definitions:
--------------------------------------------------------------------------------
-- C_DECODE_TYPE : Implementation: 0=Slice based, 1=BlockRam
-- C_ELABORATION_DIR : Directory path for mif file
-- C_HAS_BPORTS : 1 indicates second decoder should be generated
-- C_HAS_CE : 1 indicates ce port is present
-- C_HAS_CE_B : 1 indicates ce_b port is present (if c_has_bports=1)
-- C_HAS_CODE_ERR : 1 indicates code_err port is present
-- C_HAS_CODE_ERR_B : 1 indicates code_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_ERR : 1 indicates disp_err port is present
-- C_HAS_DISP_ERR_B : 1 indicates disp_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_IN : 1 indicates disp_in port is present
-- C_HAS_DISP_IN_B : 1 indicates disp_in_b port is present
-- (if c_has_bports=1)
-- C_HAS_ND : 1 indicates nd port is present
-- C_HAS_ND_B : 1 indicates nd_b port is present (if c_has_bports=1)
-- C_HAS_RUN_DISP : 1 indicates run_disp port is present
-- C_HAS_RUN_DISP_B : 1 indicates run_disp_b port is present
-- (if c_has_bports=1)
-- C_HAS_SINIT : 1 indicates sinit port is present
-- C_HAS_SINIT_B : 1 indicates sinit_b port is present
-- (if c_has_bports=1)
-- C_HAS_SYM_DISP : 1 indicates sym_disp port is present
-- C_HAS_SYM_DISP_B : 1 indicates sym_disp_b port is present
-- (if c_has_bports=1)
-- C_SINIT_DOUT : 8-bit binary string, dout value when sinit is active
-- C_SINIT_DOUT_B : 8-bit binary string, dout_b value when sinit_b is
-- active
-- C_SINIT_KOUT : controls kout output when sinit is active
-- C_SINIT_KOUT_B : controls kout_b output when sinit_b is active
-- C_SINIT_RUN_DISP : Initializes run_disp (and disp_in) value to
-- positive(1) or negative(0)
-- C_SINIT_RUN_DISP_B : Initializes run_disp_b (and disp_in_b) value to
-- positive(1) or negative(0)
--------------------------------------------------------------------------------
END xilinx;
|
gpl-3.0
|
df8f7dbedeee2e457851112524bd4f30
| 0.478485 | 3.748685 | false | false | false | false |
cretingame/Yarr-fw
|
syn/xpressk7/ddr3_revA/top_level.vhd
| 1 | 18,986 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/27/2016 04:46:45 PM
-- Design Name:
-- Module Name: top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_level is
Port ( ---------------------------------------------------------------------------
-- Xilinx Hard IP Interface
-- . Clock and Resets
pcie_clk_p : in std_logic;
pcie_clk_n : in std_logic;
clk200_n : in STD_LOGIC;
clk200_p : in STD_LOGIC;
rst_n_i : in STD_LOGIC;
sys_rst_n_i : in STD_LOGIC;
-- . Serial I/F
pci_exp_txn : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txn ,
pci_exp_txp : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txp ,
pci_exp_rxn : in std_logic_vector(4-1 downto 0);--input wire [4 -1:0] pci_exp_rxn ,
pci_exp_rxp : in std_logic_vector(4-1 downto 0);
-- . IO
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (2 downto 0);
--front_led_o : out STD_LOGIC_VECTOR (3 downto 0);
-- . DDR3
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
--init_calib_complete : out std_logic;
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0)
);
end top_level;
architecture Behavioral of top_level is
constant AXI_BUS_WIDTH : integer := 64;
component simple_counter is
Port (
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
count_o : out STD_LOGIC_VECTOR (28 downto 0)
);
end component;
COMPONENT pcie_7x_0
PORT (
pci_exp_txp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_txn : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
user_clk_out : OUT STD_LOGIC;
user_reset_out : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
user_app_rdy : OUT STD_LOGIC;
tx_buf_av : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
tx_cfg_req : OUT STD_LOGIC;
tx_err_drop : OUT STD_LOGIC;
s_axis_tx_tready : OUT STD_LOGIC;
s_axis_tx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tx_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tx_tlast : IN STD_LOGIC;
s_axis_tx_tvalid : IN STD_LOGIC;
s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rx_tlast : OUT STD_LOGIC;
m_axis_rx_tvalid : OUT STD_LOGIC;
m_axis_rx_tready : IN STD_LOGIC;
m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
cfg_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_command : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_pcie_link_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_pmcsr_pme_en : OUT STD_LOGIC;
cfg_pmcsr_powerstate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pmcsr_pme_status : OUT STD_LOGIC;
cfg_received_func_lvl_rst : OUT STD_LOGIC;
cfg_interrupt : IN STD_LOGIC;
cfg_interrupt_rdy : OUT STD_LOGIC;
cfg_interrupt_assert : IN STD_LOGIC;
cfg_interrupt_di : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable : OUT STD_LOGIC;
cfg_interrupt_msixenable : OUT STD_LOGIC;
cfg_interrupt_msixfm : OUT STD_LOGIC;
cfg_interrupt_stat : IN STD_LOGIC;
cfg_pciecap_interrupt_msgnum : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_to_turnoff : OUT STD_LOGIC;
cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_bridge_serr_en : OUT STD_LOGIC;
cfg_slot_control_electromech_il_ctl_pulse : OUT STD_LOGIC;
cfg_root_control_syserr_corr_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_non_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_pme_int_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_received : OUT STD_LOGIC;
cfg_msg_received_err_cor : OUT STD_LOGIC;
cfg_msg_received_err_non_fatal : OUT STD_LOGIC;
cfg_msg_received_err_fatal : OUT STD_LOGIC;
cfg_msg_received_pm_as_nak : OUT STD_LOGIC;
cfg_msg_received_pm_pme : OUT STD_LOGIC;
cfg_msg_received_pme_to_ack : OUT STD_LOGIC;
cfg_msg_received_assert_int_a : OUT STD_LOGIC;
cfg_msg_received_assert_int_b : OUT STD_LOGIC;
cfg_msg_received_assert_int_c : OUT STD_LOGIC;
cfg_msg_received_assert_int_d : OUT STD_LOGIC;
cfg_msg_received_deassert_int_a : OUT STD_LOGIC;
cfg_msg_received_deassert_int_b : OUT STD_LOGIC;
cfg_msg_received_deassert_int_c : OUT STD_LOGIC;
cfg_msg_received_deassert_int_d : OUT STD_LOGIC;
cfg_msg_received_setslotpowerlimit : OUT STD_LOGIC;
cfg_vc_tcvc_map : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_rst_n : IN STD_LOGIC
);
END COMPONENT;
component app is
Generic(
AXI_BUS_WIDTH : integer := 64;
DMA_MEMORY_SELECTED : string := "DDR3"
);
Port ( clk_i : in STD_LOGIC;
sys_clk_n_i : IN STD_LOGIC;
sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
user_lnk_up_i : in STD_LOGIC;
user_app_rdy_i : in STD_LOGIC;
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
-- PCIe debug
tx_err_drop_i : in STD_LOGIC;
cfg_dstatus_i : in STD_LOGIC_VECTOR(15 DOWNTO 0);
--DDR3
ddr3_dq_io : inout std_logic_vector(63 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(7 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(7 downto 0);
--init_calib_complete_o : out std_logic;
ddr3_addr_o : out std_logic_vector(14 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(0 downto 0);
ddr3_ck_n_o : out std_logic_vector(0 downto 0);
ddr3_cke_o : out std_logic_vector(0 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_dm_o : out std_logic_vector(7 downto 0);
ddr3_odt_o : out std_logic_vector(0 downto 0);
--I/O
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
front_led_o : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
--Clocks
signal sys_clk : STD_LOGIC;
--signal clk200 : STD_LOGIC;
signal aclk : STD_LOGIC;
signal arstn_s : STD_LOGIC;
signal rst_s : STD_LOGIC;
--Wishbone bus
signal usr_led_s : std_logic_vector(3 downto 0);
--signal count_s : STD_LOGIC_VECTOR (28 downto 0);
-- AXI-stream bus to PCIE
signal s_axis_tx_tready_s : STD_LOGIC;
signal s_axis_tx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal s_axis_tx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal s_axis_tx_tlast_s : STD_LOGIC;
signal s_axis_tx_tvalid_s : STD_LOGIC;
signal s_axis_tx_tuser_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal m_axis_rx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal m_axis_rx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal m_axis_rx_tlast_s : STD_LOGIC;
signal m_axis_rx_tvalid_s : STD_LOGIC;
signal m_axis_rx_tready_s : STD_LOGIC;
signal m_axis_rx_tuser_s : STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIE signals
signal user_lnk_up_s : STD_LOGIC;
signal user_app_rdy_s : STD_LOGIC;
signal tx_err_drop_s : STD_LOGIC;
signal cfg_interrupt_s : STD_LOGIC;
signal cfg_interrupt_rdy_s : STD_LOGIC;
signal cfg_interrupt_assert_s : STD_LOGIC;
signal cfg_interrupt_di_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_do_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_mmenable_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal cfg_interrupt_msienable_s : STD_LOGIC;
signal cfg_interrupt_msixenable_s : STD_LOGIC;
signal cfg_interrupt_msixfm_s : STD_LOGIC;
signal cfg_interrupt_stat_s : STD_LOGIC;
signal cfg_pciecap_interrupt_msgnum_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIE ID
signal cfg_bus_number_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_device_number_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal cfg_function_number_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
--PCIE debug
signal cfg_dstatus_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
-- LVDS input to internal single
-- CLK_IBUFDS : IBUFDS
-- generic map(
-- IOSTANDARD => "DEFAULT"
-- )
-- port map(
-- I => clk200_p,
-- IB => clk200_n,
-- O => clk200
-- );
-- design_1_0: component design_1
-- port map (
-- CLK_IN_D_clk_n(0) => pcie_clk_n,
-- CLK_IN_D_clk_p(0) => pcie_clk_p,
-- IBUF_OUT(0) => sys_clk
-- );
refclk_ibuf : IBUFDS_GTE2
port map(
O => sys_clk,
ODIV2 => open,
I => pcie_clk_p,
IB => pcie_clk_n,
CEB => '0');
rst_s <= not rst_n_i;
arstn_s <= sys_rst_n_i or rst_n_i;
pcie_0 : pcie_7x_0
PORT MAP (
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
user_clk_out => aclk,
user_reset_out => open, -- TODO
user_lnk_up => user_lnk_up_s,
user_app_rdy => user_app_rdy_s,
tx_err_drop => tx_err_drop_s,
s_axis_tx_tready => s_axis_tx_tready_s,
s_axis_tx_tdata => s_axis_tx_tdata_s,
s_axis_tx_tkeep => s_axis_tx_tkeep_s,
s_axis_tx_tlast => s_axis_tx_tlast_s,
s_axis_tx_tvalid => s_axis_tx_tvalid_s,
s_axis_tx_tuser => s_axis_tx_tuser_s,
m_axis_rx_tdata => m_axis_rx_tdata_s,
m_axis_rx_tkeep => m_axis_rx_tkeep_s,
m_axis_rx_tlast => m_axis_rx_tlast_s,
m_axis_rx_tvalid => m_axis_rx_tvalid_s,
m_axis_rx_tready => m_axis_rx_tready_s,
m_axis_rx_tuser => m_axis_rx_tuser_s,
cfg_interrupt => cfg_interrupt_s,
cfg_interrupt_rdy => cfg_interrupt_rdy_s,
cfg_interrupt_assert => cfg_interrupt_assert_s,
cfg_interrupt_di => cfg_interrupt_di_s,
cfg_interrupt_do => cfg_interrupt_do_s,
cfg_interrupt_mmenable => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm => cfg_interrupt_msixfm_s,
cfg_interrupt_stat => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum_s,
cfg_dstatus => cfg_dstatus_s,
cfg_bus_number => cfg_bus_number_s,
cfg_device_number => cfg_device_number_s,
cfg_function_number => cfg_function_number_s,
sys_clk => sys_clk,
sys_rst_n => sys_rst_n_i
);
app_0:app
generic map(
AXI_BUS_WIDTH => 64,
DMA_MEMORY_SELECTED => "DDR3"
)
port map(
clk_i => aclk,
sys_clk_n_i => clk200_n,
sys_clk_p_i => clk200_p,
rst_i => rst_s,
user_lnk_up_i => user_lnk_up_s,
user_app_rdy_i => user_app_rdy_s,
-- AXI-Stream bus
m_axis_tx_tready_i => s_axis_tx_tready_s,
m_axis_tx_tdata_o => s_axis_tx_tdata_s,
m_axis_tx_tkeep_o => s_axis_tx_tkeep_s,
m_axis_tx_tlast_o => s_axis_tx_tlast_s,
m_axis_tx_tvalid_o => s_axis_tx_tvalid_s,
m_axis_tx_tuser_o => s_axis_tx_tuser_s,
s_axis_rx_tdata_i => m_axis_rx_tdata_s,
s_axis_rx_tkeep_i => m_axis_rx_tkeep_s,
s_axis_rx_tlast_i => m_axis_rx_tlast_s,
s_axis_rx_tvalid_i => m_axis_rx_tvalid_s,
s_axis_rx_tready_o => m_axis_rx_tready_s,
s_axis_rx_tuser_i => m_axis_rx_tuser_s,
-- PCIe interrupt config
cfg_interrupt_o => cfg_interrupt_s,
cfg_interrupt_rdy_i => cfg_interrupt_rdy_s,
cfg_interrupt_assert_o => cfg_interrupt_assert_s,
cfg_interrupt_di_o => cfg_interrupt_di_s,
cfg_interrupt_do_i => cfg_interrupt_do_s,
cfg_interrupt_mmenable_i => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable_i => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable_i => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm_i => cfg_interrupt_msixfm_s,
cfg_interrupt_stat_o => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum_o => cfg_pciecap_interrupt_msgnum_s,
-- PCIe ID
cfg_bus_number_i => cfg_bus_number_s,
cfg_device_number_i => cfg_device_number_s,
cfg_function_number_i => cfg_function_number_s,
-- PCIe debug
tx_err_drop_i => tx_err_drop_s,
cfg_dstatus_i => cfg_dstatus_s,
--DDR3
ddr3_dq_io => ddr3_dq,
ddr3_dqs_p_io => ddr3_dqs_p,
ddr3_dqs_n_io => ddr3_dqs_n,
--init_calib_complete_o => init_calib_complete,
ddr3_addr_o => ddr3_addr,
ddr3_ba_o => ddr3_ba,
ddr3_ras_n_o => ddr3_ras_n,
ddr3_cas_n_o => ddr3_cas_n,
ddr3_we_n_o => ddr3_we_n,
ddr3_reset_n_o => ddr3_reset_n,
ddr3_ck_p_o => ddr3_ck_p,
ddr3_ck_n_o => ddr3_ck_n,
ddr3_cke_o => ddr3_cke,
ddr3_cs_n_o => ddr3_cs_n,
ddr3_dm_o => ddr3_dm,
ddr3_odt_o => ddr3_odt,
--I/O
usr_sw_i => usr_sw_i,
usr_led_o => usr_led_s,
front_led_o => open--front_led_o
);
usr_led_o <= usr_led_s(2 downto 0);
--m_axis_rx_tready_s <= '1';
end Behavioral;
|
gpl-3.0
|
5dee30c292b2f5a85ca34e067e4c226c
| 0.539187 | 3.269502 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_bus_tail_strip.vhd
| 1 | 2,697 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_bus_tail_strip IS
END tb_bus_tail_strip;
ARCHITECTURE behavior OF tb_bus_tail_strip IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bus_tail_strip
generic (N_BYTES : integer);
port (Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
PktOut : out std_logic;
DataOut : out std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal PktIn : std_logic := '0';
signal DataIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal PktOut, PktOut_1 : std_logic;
signal DataOut, DataOut_1 : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
strip_3: bus_tail_strip
GENERIC MAP ( N_BYTES => 3 )
PORT MAP (
Clk => Clk,
Rst => Rst,
PktIn => PktIn,
DataIn => DataIn,
PktOut => PktOut_1,
DataOut => DataOut_1
);
strip_1: bus_tail_strip
GENERIC MAP ( N_BYTES => 1 )
PORT MAP (
Clk => Clk,
Rst => Rst,
PktIn => PktOut_1,
DataIn => DataOut_1,
PktOut => PktOut,
DataOut => DataOut
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
PktIn <= '1';
for i in 1 to 10 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait;
end process;
END;
|
gpl-3.0
|
6c503b8be18c95caba23db8a6a60be6d
| 0.612532 | 3.654472 | false | false | false | false |
techwoes/sump
|
logic_analyzer/la.vhd
| 2 | 5,947 |
----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependend IO modules and defines all inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity la is
Port(
resetSwitch : in std_logic;
xtalClock : in std_logic;
exClock : in std_logic;
input : in std_logic_vector(31 downto 0);
ready50 : out std_logic;
rx : in std_logic;
tx : inout std_logic;
an : OUT std_logic_vector(3 downto 0);
segment : OUT std_logic_vector(7 downto 0);
led : OUT std_logic_vector(7 downto 0);
switch : in std_logic_vector(1 downto 0);
ramIO1 : INOUT std_logic_vector(15 downto 0);
ramIO2 : INOUT std_logic_vector(15 downto 0);
ramA : OUT std_logic_vector(17 downto 0);
ramWE : OUT std_logic;
ramOE : OUT std_logic;
ramCE1 : OUT std_logic;
ramUB1 : OUT std_logic;
ramLB1 : OUT std_logic;
ramCE2 : OUT std_logic;
ramUB2 : OUT std_logic;
ramLB2 : OUT std_logic
);
end la;
architecture Behavioral of la is
COMPONENT clockman
PORT(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
END COMPONENT;
COMPONENT display
PORT(
data : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
an : OUT std_logic_vector(3 downto 0);
segment : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
COMPONENT core
PORT(
clock : IN std_logic;
extReset : IN std_logic;
cmd : IN std_logic_vector(39 downto 0);
execute : IN std_logic;
input : IN std_logic_vector(31 downto 0);
inputClock : IN std_logic;
sampleReady50 : OUT std_logic;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : IN std_logic_vector(31 downto 0);
memoryOut : OUT std_logic_vector(31 downto 0);
memoryRead : OUT std_logic;
memoryWrite : OUT std_logic
);
END COMPONENT;
COMPONENT sram
PORT(
clock : IN std_logic;
input : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0);
read : IN std_logic;
write : IN std_logic;
ramIO1 : INOUT std_logic_vector(15 downto 0);
ramIO2 : INOUT std_logic_vector(15 downto 0);
ramA : OUT std_logic_vector(17 downto 0);
ramWE : OUT std_logic;
ramOE : OUT std_logic;
ramCE1 : OUT std_logic;
ramUB1 : OUT std_logic;
ramLB1 : OUT std_logic;
ramCE2 : OUT std_logic;
ramUB2 : OUT std_logic;
ramLB2 : OUT std_logic
);
END COMPONENT;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (31 downto 0);
signal output : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 28; -- 100M / 28 / 115200 = 31 (5bit)
constant RATE : integer := 115200; -- maximum & base rate
begin
led(7 downto 0) <= exClock & "00" & switch & "000";
Inst_clockman: clockman PORT MAP(
clkin => xtalClock,
clk0 => clock
);
Inst_display: display PORT MAP(
data => memoryIn,
clock => clock,
an => an,
segment => segment
);
Inst_eia232: eia232
generic map (
FREQ => FREQ,
SCALE => TRXSCALE,
RATE => RATE
)
PORT MAP(
clock => clock,
reset => resetSwitch,
speed => switch,
rx => rx,
tx => tx,
cmd => cmd,
execute => execute,
data => output,
send => send,
busy => busy
);
Inst_core: core PORT MAP(
clock => clock,
extReset => resetSwitch,
cmd => cmd,
execute => execute,
input => input,
inputClock => exClock,
sampleReady50 => ready50,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write
);
Inst_sram: sram PORT MAP(
clock => clock,
input => memoryOut,
output => memoryIn,
read => read,
write => write,
ramA => ramA,
ramWE => ramWE,
ramOE => ramOE,
ramIO1 => ramIO1,
ramCE1 => ramCE1,
ramUB1 => ramUB1,
ramLB1 => ramLB1,
ramIO2 => ramIO2,
ramCE2 => ramCE2,
ramUB2 => ramUB2,
ramLB2 => ramLB2
);
end Behavioral;
|
gpl-2.0
|
ce0d1866529597ac82e864038996f11b
| 0.637969 | 3.292913 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sources_1/new/check_sensor.vhd
| 1 | 5,887 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.10.2017 23:26:55
-- Design Name:
-- Module Name: check_sensor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity check_sensor is
generic(sensor_position : pixel_position := (130, 50);
sensor_radius : integer range 16 downto 4 := 8);
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
pixel_cnt : in positive range 1 TO 1023;
line_cnt : in positive range 1 TO 1023;
pixel_data : in STD_LOGIC_VECTOR(23 downto 0);
pixel_data_ready : in STD_LOGIC;
----
sensor_data : out sensor;
sensor_data_ready : out STD_LOGIC);
end check_sensor;
architecture Behavioral of check_sensor is
type diff_array is array (0 to 31) of int8u;
signal px_colors : color_array;
signal all_points_ready : std_logic := '0';
signal new_value : std_logic := '0';
begin
fill_points : process(clk) is
variable i : integer range 0 to 4*sensor_radius - 1 := 0;
variable sighn : integer range -1 to 1 := -1;
variable index : integer range 31 downto 0 := 0;
variable old_pixel_cnt : positive range 1 TO 1024;
variable p : pixel;
variable p_sum, color_tmp : RGB_COLOR;
variable shifts : shift_position := (0, 2, 4, 5, 6, 7, 8, 8, 8, 8, 8, 7, 6, 5, 4, 2, 0);
begin
if (clk'event and clk = '0') then
if resetn = '0' then
new_value <= '0';
i := 0;
sighn := 1;
index := 0;
all_points_ready <= '0';
else
new_value <= '0'; -- neuen wert nur ein mal bei clk kommt
all_points_ready <= '0';
if (pixel_data_ready = '1' and pixel_cnt /= old_pixel_cnt) then
old_pixel_cnt := pixel_cnt; -- nur einen wert von pixel uebernehmen
-- wenn innerhalb sensor
if (line_cnt >= sensor_position.y - sensor_radius and line_cnt <= sensor_position.y + sensor_radius ) then
if (line_cnt = sensor_position.y - sensor_radius and pixel_cnt = sensor_position.x - 1) then
sighn := 1;
index := 0;
i := 0;
p_sum := (0, 0, 0);
end if;
-- und pixelreihenfolge von links nach rechts
if (pixel_cnt = sensor_position.x - 1 + sighn*shifts(i)) then --FIXME Vereinheitlichen Pixel faengt von 1 und nicht von 0
-- index wird von oben nach unten berechnet
color_tmp.r := to_integer(unsigned(pixel_data(7 downto 0)));
color_tmp.g := to_integer(unsigned(pixel_data(15 downto 8)));
color_tmp.b := to_integer(unsigned(pixel_data(23 downto 16)));
px_colors(index) <= color_tmp;
p.pos.x := pixel_cnt;
p.pos.y := line_cnt;
new_value <= '1';
--- Prozedur neues pixel Berechnung
p_sum := middle_value(color_tmp, p_sum);
--- End Prozedur
-- am Ende wenn alle Sensorpunkte durch sind
if index = 16 then
i := 0;
index := 0;
all_points_ready <= '1';
end if;
if sighn = 1 then -- erstes sighn = -1
index := 31 - i;
i := i + 1; -- fuer naechste runde
else
index := i;
end if;
sighn := -sighn; -- richtung wechsel
end if;
end if;
end if;
end if;
end if;
end process fill_points;
calc_sensor : process(clk) is
-- procedure calc_s(in_colors : in color_array; signal sensor_out : out sensor) is
-- variable values : diff_array;
-- begin
--
-- for i in 0 to 30 loop
-- values(i) := color_distance(in_colors(i), in_colors(i + 1));
-- end loop;
-- values(31) := color_distance(in_colors(31), in_colors(0));
--
-- end procedure calc_s;
variable values_1 : diff_array;
variable max_value : integer range -255 to 255 := 0;
variable min_value : integer range -255 to 255 := 0;
variable max_pos : integer range 0 to 31 := 0;
variable min_pos : integer range 0 to 31 := 0;
begin
if (clk'event and clk = '1') then
if resetn = '0' then
-- sensor_data_ready <= '0'; -- TODO rest initialisieren
else
sensor_data_ready <= '0';
--sensor_data <= (others => 'Z');
if all_points_ready = '1' then
-- calc_s(px_colors, sensor_data);
-- berechne diffs
max_value := color_distance(px_colors(31), px_colors(0));
min_value := max_value;
values_1(31) := max_value;
for i in 0 to 30 loop
values_1(i) := color_distance(px_colors(i), px_colors(i + 1));
if values_1(i) > max_value then
max_value := values_1(i);
max_pos := i;
end if;
if values_1(i) < min_value then
min_value := values_1(i);
min_pos := i;
end if;
end loop;
-- finde points
sensor_data.pos.x <= sensor_position.x;
sensor_data.pos.y <= sensor_position.y;
sensor_data.max_pos <= max_pos;
sensor_data.min_pos <= min_pos;
-- sensor_data.color <= p_sum;
sensor_data_ready <= '1';
end if;
end if;
end if;
end process calc_sensor;
end Behavioral;
|
gpl-3.0
|
07af7f2f2f3eb5b2427d2c371061db13
| 0.548836 | 3.199457 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/memc3_tb_top.vhd
| 4 | 29,611 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
gpl-3.0
|
49fa0c1c30048a3c38b1bc94cd1062ba
| 0.497113 | 3.308122 | false | false | false | false |
metaspace/ghdl_extra
|
clk/clk_exemple.vhdl
| 1 | 1,640 |
-- Fichier : clk_exemple.vhdl
-- created by Yann Guidon / ygdes.com
-- jeu. avril 15 15:28:24 CEST 2010
-- jeu. avril 15 21:05:36 CEST 2010
-- clk_exemple.vhdl : just an example for the use of the synchronised clock generator
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rt_utils.all;
entity clk_exemple is
-- rien
end entity;
architecture exemple of clk_exemple is
-- ne pas oublier d'initialiser clk
-- sinon l'horloge ne peut pas osciller
-- aussi, stop doit etre maintenu à '0'
signal clk, stop: std_ulogic:='0';
begin
-- instanciation de l'horloge :
horloge : entity work.rt_clk
generic map(ms => 500)
port map(clk => clk, stop => stop);
process(clk) is
variable compteur: integer := 0;
begin
if rising_edge(clk) then
compteur := compteur + 1;
if compteur > 10 then
stop <= '1';
end if;
end if;
end process;
observe_std_ulogic("clk",clk);
end exemple;
|
gpl-3.0
|
793246f6f59b759a38f2568717ebf68f
| 0.695732 | 3.572985 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Equalizer_Low_Test.vhd
| 1 | 3,579 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Equalizer_Low_Test is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Equalizer_Low_Test;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Equalizer_Low_Test is
constant sa1_1 : std_logic_vector(17 downto 0) := (x"8797") & "00";
constant sa2_1 : std_logic_vector(17 downto 0) := (x"38d6") & "00";
constant sa1_2 : std_logic_vector(17 downto 0) := (x"88f3") & "00";
constant sa2_2 : std_logic_vector(17 downto 0) := (x"38d0") & "00";
constant sa1_3 : std_logic_vector(16 downto 0) := "1" & (x"c524");
constant sa2_3 : std_logic_vector(16 downto 0) := "0" & (x"0dc5");
begin
Equalizer : entity work.Equalizer
generic map(DATA_WIDTH => 16,
DATA_FRACT => 15,
SCALE_WIDTH_1 => 16,
SCALE_FRACT_1 => 13,
SCALE_WIDTH_2 => 16,
SCALE_FRACT_2 => 13,
SCALE_WIDTH_3 => 16,
SCALE_FRACT_3 => 14,
SCALE_WIDTH_4 => 16,
SCALE_FRACT_4 => 14,
INTERNAL_IIR_WIDTH_1 => 24,
INTERNAL_IIR_FRACT_1 => 20,
INTERNAL_IIR_WIDTH_2 => 24,
INTERNAL_IIR_FRACT_2 => 20,
INTERNAL_IIR_WIDTH_3 => 24,
INTERNAL_IIR_FRACT_3 => 20,
COEFF_WIDTH_1 => 18,
COEFF_FRACT_1 => 16,
COEFF_WIDTH_2 => 18,
COEFF_FRACT_2 => 16,
COEFF_WIDTH_3 => 17,
COEFF_FRACT_3 => 14)
port map(clk => clk,
reset => reset,
x => input,
scale_1 => x"7fb2",
scale_2 => x"7fb2",
scale_3 => "0100000000000000",
scale_4 => "0100000000000000",
b0_1 => "00" & (x"41bd"),
b1_1 => "11" & (x"8784"),
b2_1 => "00" & (x"3799"),
a1_1 => std_logic_vector(-signed(sa1_1)),
a2_1 => std_logic_vector(-signed(sa2_1)),
b0_2 => "00" & (x"43bd"),
b1_2 => "11" & (x"88aa"),
b2_2 => "00" & (x"355d"),
a1_2 => std_logic_vector(-signed(sa1_2)),
a2_2 => std_logic_vector(-signed(sa2_2)),
b0_3 => (x"66f2") & "0",
b1_3 => (x"8a49") & "0",
b2_3 => (x"3499") & "0",
a1_3 => std_logic_vector(-signed(sa1_3)),
a2_3 => std_logic_vector(-signed(sa2_3)),
y => output);
end architecture;
|
mit
|
dc520e9692fdbcfaaf1bb19ca8c35b16
| 0.340598 | 4.07631 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/m_clk_sync.vhd
| 2 | 2,522 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/20/2017 02:26:29 PM
-- Design Name:
-- Module Name: m_clk_sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity m_clk_sync is
Generic (
data_width_g : integer := 29
);
Port ( rst0_i : in STD_LOGIC;
rst1_i : in STD_LOGIC;
clk0_i : in STD_LOGIC;
clk1_i : in STD_LOGIC;
data0_i : in STD_LOGIC_VECTOR (data_width_g-1 downto 0);
data1_o : out STD_LOGIC_VECTOR (data_width_g-1 downto 0));
end m_clk_sync;
architecture Behavioral of m_clk_sync is
COMPONENT cross_clock_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(28 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal data_s : std_logic_vector(data_width_g - 1 downto 0);
signal wr_en_s : std_logic;
signal empty_s : std_logic;
signal empty_n_s : std_logic;
begin
process(rst0_i,clk0_i)
begin
if rst0_i = '1' then
data_s <= (others=>'0');
wr_en_s <= '0';
elsif clk0_i'event and clk0_i = '1' then
data_s <= data0_i;
if data_s /= data0_i then
wr_en_s <= '1';
else
wr_en_s <= '0';
end if;
end if;
end process;
empty_n_s <= not empty_s;
your_instance_name : cross_clock_fifo
PORT MAP (
rst => rst0_i,
wr_clk => clk0_i,
rd_clk => clk1_i,
din => data0_i,
wr_en => wr_en_s,
rd_en => empty_n_s,
dout => data1_o,
full => open,
empty => empty_s
);
end Behavioral;
|
gpl-3.0
|
0bc55e6f1e37f653a19bc20c7af7e612
| 0.508723 | 3.50765 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sources_1/new/cam_move.vhd
| 1 | 5,380 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 18:52:36
-- Design Name:
-- Module Name: cam_move - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity cam_move is
Port(clk : in STD_LOGIC;
resetn : in STD_LOGIC;
hsync_in : in std_logic;
vsync_in : in std_logic;
href_in : in std_logic;
cam_pxdata : in STD_LOGIC_VECTOR(7 downto 0);
-----
cam_clk : out STD_LOGIC;
px_number : out natural range 0 to 1024 := 0;
line_number : out natural range 0 to 1024 := 0;
pixel_data : out std_logic_vector(23 downto 0);
pixel_data_ready : out STD_LOGIC;
sensor_data : out sensor_vector;
sensor_data_ready : out STD_LOGIC
);
end cam_move;
architecture Behavioral of cam_move is
signal tmp_pixel_data_ready : std_logic := '0';
signal tmp_pixel_data : std_logic_vector(23 downto 0);
signal x, y : integer range 0 to 1024 := 0;
signal pclk : STD_LOGIC;
constant pclk_to_clk_rate : integer := 2;
signal outbus_free : STD_LOGIC;
signal tmp_sensor_data_ready : STD_LOGIC_VECTOR(4 downto 0);
component get_mark_points
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
vsync : in STD_LOGIC;
href : in STD_LOGIC;
px_data : in STD_LOGIC_VECTOR(7 downto 0);
data_ready : out STD_LOGIC;
px_count_out, line_count_out : out natural;
px_data_out : out STD_LOGIC_VECTOR(23 downto 0));
end component;
component check_sensor is
generic(sensor_position : pixel_position := (130, 50);
sensor_radius : integer range 16 downto 4 := 8);
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
pixel_cnt : positive range 1 TO 1023;
line_cnt : positive range 1 TO 1023;
pixel_data : in STD_LOGIC_VECTOR(23 downto 0);
pixel_data_ready : in STD_LOGIC;
sensor_data : out sensor;
sensor_data_ready : out STD_LOGIC);
end component;
component sensor_gate is
Port(clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sensor_ready : in STD_LOGIC;
sensor_in : in sensor;
outbus_free : in STD_LOGIC;
sensor_out : out sensor_vector;
sensor_data_ready : out std_logic
);
end component;
begin
cam_clk <= pclk;
---- Ausgabe für wreiter
px_number <= x;
line_number <= y;
pixel_data <= tmp_pixel_data;
pixel_data_ready <= tmp_pixel_data_ready;
cam_to_pixel : get_mark_points
port map(
resetn => resetn,
clk => pclk,
vsync => vsync_in,
href => href_in,
px_data => cam_pxdata,
px_count_out => x,
line_count_out => y,
data_ready => tmp_pixel_data_ready,
px_data_out => tmp_pixel_data
);
generate_sensors : for i in 1 to 5 generate
signal tmp_sensor : sensor;
begin
sensor_inst : component check_sensor
generic map(sensor_position => (i*20, 50))
port map(
resetn => resetn,
clk => clk,
pixel_cnt => x,
line_cnt => y,
pixel_data => tmp_pixel_data,
pixel_data_ready => tmp_pixel_data_ready,
sensor_data => tmp_sensor,
sensor_data_ready => tmp_sensor_data_ready(i - 1)
);
sensor_gate_inst : component sensor_gate
port map(
clk => clk,
resetn => resetn,
sensor_ready => tmp_sensor_data_ready(i - 1),
sensor_in => tmp_sensor,
outbus_free => outbus_free,
sensor_out => sensor_data,
sensor_data_ready => sensor_data_ready
);
end generate generate_sensors;
pclk_pr : process(clk) is
variable n : integer := 0;
begin
if rising_edge(clk) then
if resetn = '0' then
n := 0;
pclk <= '0';
else
n := n + 1;
if n > pclk_to_clk_rate then
pclk <= '1';
else
pclk <= '0';
end if;
if n = 2*pclk_to_clk_rate then
n := 0;
end if;
end if;
end if;
end process pclk_pr;
check_bus : process(clk) is -- ist notwendig für clock Verschiebung
begin
if rising_edge(clk) then
if resetn = '0' then
outbus_free <= '0';
else
outbus_free <= not or_reduct(tmp_sensor_data_ready);
end if;
end if;
end process check_bus;
end Behavioral;
|
gpl-3.0
|
abaf612c24f981b8149e37016fc68f80
| 0.529554 | 3.442099 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_ctrl_regs.vhd
| 1 | 2,782 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_ctrl_regs IS
END tb_ctrl_regs;
ARCHITECTURE behavior OF tb_ctrl_regs IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ctrl_regs
PORT(
Clk : IN std_logic;
PktIn : IN std_logic;
DataIn : IN std_logic_vector(7 downto 0);
PktOut : OUT std_logic;
DataOut : OUT std_logic_vector(7 downto 0);
Regs : OUT std_logic_vector(79 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal PktIn : std_logic := '0';
signal DataIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal PktOut : std_logic;
signal DataOut : std_logic_vector(7 downto 0);
signal Regs : std_logic_vector(79 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ctrl_regs PORT MAP (
Clk => Clk,
PktIn => PktIn,
DataIn => DataIn,
PktOut => PktOut,
DataOut => DataOut,
Regs => Regs
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 200 ns;
PktIn <= '1';
wait for Clk_period * 8;
for i in 1 to 1 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
PktIn <= '1';
for i in 1 to 15 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
PktIn <= '1';
DataIn <= X"00";
wait for Clk_period * 7;
for i in 1 to 15 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*20;
wait;
end process;
END;
|
gpl-3.0
|
799c1e380847685ae6ad8e6ad7795844
| 0.622933 | 3.521519 | false | false | false | false |
Project-Bonfire/Bonfire
|
Packages/TB_Package_32_bit_credit_based_NI.vhd
| 1 | 12,325 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function CX_GEN(current_address, network_x, network_y : integer) return integer;
procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0));
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function CX_GEN(current_address, network_x, network_y: integer) return integer is
variable X, Y : integer := 0;
variable CN, CE, CW, CS : std_logic := '0';
variable CX : std_logic_vector(3 downto 0);
begin
X := current_address mod network_x;
Y := current_address / network_x;
if X /= 0 then
CW := '1';
end if;
if X /= network_x-1 then
CE := '1';
end if;
if Y /= 0 then
CN := '1';
end if;
if Y /= network_y-1 then
CS := '1';
end if;
CX := CS&CW&CE&CN;
return to_integer(unsigned(CX));
end CX_GEN;
procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0)) is
-- variables for random functions
constant DATA_WIDTH : integer := 32;
variable seed1 :positive := current_address+1;
variable seed2 :positive := current_address+1;
variable rand : real ;
--file handling variables
variable SEND_LINEVARIABLE : line;
file SEND_FILE : text;
variable RECEIVED_LINEVARIABLE : line;
file RECEIVED_FILE : text;
-- receiving variables
variable receive_source_node, receive_destination_node, receive_packet_id, receive_counter, receive_packet_length: integer;
-- sending variables
variable send_destination_node, send_counter, send_id_counter: integer:= 0;
variable send_packet_length: integer:= 8;
type state_type is (Idle, Header_flit, Body_flit, Body_flit_1, Tail_flit);
variable state : state_type;
variable frame_starting_delay : integer:= 0;
variable frame_counter: integer:= 0;
variable first_packet : boolean := True;
begin
file_open(RECEIVED_FILE,"received.txt",WRITE_MODE);
file_open(SEND_FILE,"sent.txt",WRITE_MODE);
enable <= '1';
state := Idle;
send_packet_length := min_packet_size;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size-1)))/100);
wait until clk'event and clk ='0';
address <= reconfiguration_address;
wait until clk'event and clk ='0';
write_byte_enable <= "1111";
data_write <= "00000000000000000000" & std_logic_vector(to_unsigned(CX_GEN(current_address, network_x, network_y), 4)) & std_logic_vector(to_unsigned(60, 8));
wait until clk'event and clk ='0';
write_byte_enable <= "0000";
data_write <= (others =>'0');
while true loop
-- read the flag status
address <= flag_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
--flag register is organized like this:
-- .-------------------------------------------------.
-- | N2P_empty | P2N_full | ...|
-- '-------------------------------------------------'
if data_read(31) = '0' then -- N2P is not empty, can receive flit
-- read the received data status
address <= counter_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
-- read the received data status
address <= reserved_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit
receive_destination_node := to_integer(unsigned(data_read(14 downto 8)))* network_x+to_integer(unsigned(data_read(7 downto 1)));
receive_source_node :=to_integer(unsigned(data_read(28 downto 22)))* network_x+to_integer(unsigned(data_read(21 downto 15)));
receive_counter := 1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit
if receive_counter = 1 then
receive_packet_length := to_integer(unsigned(data_read(28 downto 15)));
receive_packet_id := to_integer(unsigned(data_read(14 downto 1)));
end if;
receive_counter := receive_counter+1;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit
receive_counter := receive_counter+1;
write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id));
writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE);
end if;
elsif data_read(30) = '0' then -- P2N is not full, can send flit
if frame_counter >= frame_starting_delay then
if state = Idle and now < finish_time then
if frame_counter < frame_starting_delay+1 then
state := Header_flit;
send_counter := send_counter+1;
-- generating the destination address
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_x*network_y)-1));
while (send_destination_node = current_address) loop
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_x*network_y)-1));
end loop;
--generating the packet length
uniform(seed1, seed2, rand);
send_packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (send_packet_length < min_packet_size) then
send_packet_length:=min_packet_size;
end if;
if (send_packet_length > max_packet_size) then
send_packet_length:=max_packet_size;
end if;
-- this is the header flit
address <= reserved_address;
write_byte_enable <= "1111";
data_write <= "0000" & std_logic_vector(to_unsigned(current_address/network_x, 7)) & std_logic_vector(to_unsigned(current_address mod network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node/network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node mod network_x, 7));
write(SEND_LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(current_address) & " to " & integer'image(send_destination_node) & " with length: "& integer'image(send_packet_length) & " id: " & integer'image(send_id_counter));
writeline(SEND_FILE, SEND_LINEVARIABLE);
else
state := Idle;
end if;
elsif state = Header_flit then
-- first body flit
address <= reserved_address;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
else
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
end if;
send_counter := send_counter+1;
state := Body_flit;
elsif state = Body_flit then
-- rest of body flits
address <= reserved_address;
write_byte_enable <= "1111";
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
send_counter := send_counter+1;
if send_counter = send_packet_length-1 then
state := Tail_flit;
else
state := Body_flit;
end if;
elsif state = Tail_flit then
-- tail flit
address <= reserved_address;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & "0000000000000000000000000000";
first_packet := False;
else
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
end if;
send_counter := 0;
state := Idle;
send_id_counter := send_id_counter + 1;
if send_id_counter = 16384 then
send_id_counter := 0;
end if;
end if;
end if;
frame_counter := frame_counter + 1;
if frame_counter = frame_length then
frame_counter := 0;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size)))/100);
end if;
wait until clk'event and clk ='0';
end if;
end loop;
file_close(SEND_FILE);
file_close(RECEIVED_FILE);
end NI_control;
end TB_Package;
|
gpl-3.0
|
3ed72e64ece153b669af74be08608bbe
| 0.540527 | 4.216558 | false | false | false | false |
makestuff/umdkv2
|
vhdl/reset-ctrl/reset_ctrl.vhdl
| 1 | 1,972 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_ctrl is
generic (
RESET_DELAY : integer := 16
);
port(
clk_in : in std_logic;
hardReset_in : in std_logic;
softReset_in : in std_logic;
mdReset_out : out std_logic
);
end entity;
architecture rtl of reset_ctrl is
type StateType is (
S_IDLE,
S_WAIT_SOFT
);
-- Registers
signal state : StateType := S_IDLE;
signal state_next : StateType;
signal count : unsigned(RESET_DELAY-1 downto 0) := (others => '0');
signal count_next : unsigned(RESET_DELAY-1 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
state <= state_next;
count <= count_next;
end if;
end process;
-- State machine
process(state, count, hardReset_in, softReset_in)
begin
state_next <= state;
count_next <= count - 1;
mdReset_out <= hardReset_in;
case state is
when S_WAIT_SOFT =>
mdReset_out <= '1';
if ( count = 0 ) then
state_next <= S_IDLE;
end if;
when others =>
if ( softReset_in = '1' ) then
state_next <= S_WAIT_SOFT;
count_next <= (others => '1');
mdReset_out <= '1';
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
ccdab47cec22a522c7e0a0ff55534424
| 0.660243 | 3.243421 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/wb_rx_core.vhd
| 1 | 6,444 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX core
-- # Outputs are synchronous to wb_clk_i
-- ####################################
-- # Adress Map:
-- # Adr[3:0]:
-- # 0x0 : RX Enable Mask
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_rx_core is
generic (
g_NUM_RX : integer range 1 to 32 := 1
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end wb_rx_core;
architecture behavioral of wb_rx_core is
function log2_ceil(val : integer) return natural is
variable result : natural;
begin
for i in 0 to g_NUM_RX-1 loop
if (val <= (2 ** i)) then
result := i;
exit;
end if;
end loop;
return result;
end function;
constant c_ALL_ZEROS : std_logic_vector(g_NUM_RX-1 downto 0) := (others => '0');
component rr_arbiter
generic (
g_CHANNELS : integer := g_NUM_RX
);
port (
-- sys connect
clk_i : in std_logic;
rst_i : in std_logic;
-- requests
req_i : in std_logic_vector(g_CHANNELS-1 downto 0);
-- grants
gnt_o : out std_logic_vector(g_CHANNELS-1 downto 0)
);
end component rr_arbiter;
component fei4_rx_channel
port (
-- Sys connect
rst_n_i : in std_logic;
clk_160_i : in std_logic;
clk_640_i : in std_logic;
enable_i : in std_logic;
-- Input
rx_data_i : in std_logic;
trig_tag_i : in std_logic_vector(31 downto 0);
-- Output
rx_data_o : out std_logic_vector(25 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0);
rx_data_raw_o : out std_logic_vector(7 downto 0)
);
end component;
COMPONENT rx_channel_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
type rx_data_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(25 downto 0);
type rx_data_fifo_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(31 downto 0);
type rx_stat_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(7 downto 0);
signal rx_data : rx_data_array;
signal rx_valid : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_stat : rx_stat_array;
signal rx_data_raw : rx_stat_array;
signal rx_fifo_dout :rx_data_fifo_array;
signal rx_fifo_din : rx_data_fifo_array;
signal rx_fifo_full : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_empty : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_rden : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_rden_t : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_fifo_wren : std_logic_vector(g_NUM_RX-1 downto 0);
signal rx_enable : std_logic_vector(31 downto 0);
signal channel : integer range 0 to g_NUM_RX-1;
signal debug : std_logic_vector(31 downto 0);
begin
debug_o <= debug;
debug(7 downto 0) <= rx_stat(0);
debug(15 downto 8) <= rx_data_raw(0);
debug(16) <= rx_valid(0);
wb_proc: process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
rx_enable <= (others => '0');
wb_stall_o <= '0';
elsif rising_edge(wb_clk_i) then
wb_ack_o <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '1') then
if (wb_adr_i(3 downto 0) = x"0") then -- Set enable mask
wb_ack_o <= '1';
rx_enable <= wb_dat_i;
else
wb_ack_o <= '1';
end if;
else
if (wb_adr_i(3 downto 0) = x"0") then -- Read enable mask
wb_dat_o <= rx_enable;
wb_ack_o <= '1';
else
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end process wb_proc;
-- Arbiter
cmp_rr_arbiter : rr_arbiter port map (
clk_i => wb_clk_i,
rst_i => not rst_n_i,
req_i => not rx_fifo_empty,
gnt_o => rx_fifo_rden_t
);
--rx_valid_o <= '0' when (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) else '1';
--rx_data_o <= x"DEADBEEF" when (unsigned(rx_fifo_rden) = 0) else rx_fifo_dout(log2_ceil(to_integer(unsigned(rx_fifo_rden))));
reg_proc : process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_fifo_rden <= (others => '0');
rx_valid_o <= '0';
channel <= 0;
elsif rising_edge(wb_clk_i) then
rx_fifo_rden <= rx_fifo_rden_t;
channel <= log2_ceil(to_integer(unsigned(rx_fifo_rden_t)));
if (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) then
rx_valid_o <= '0';
rx_data_o <= x"DEADBEEF";
else
rx_valid_o <= '1';
rx_data_o <= rx_fifo_dout(channel);
end if;
end if;
end process reg_proc;
-- Generate Rx Channels
busy_o <= '0' when (rx_fifo_full = c_ALL_ZEROS) else '1';
rx_channels: for I in 0 to g_NUM_RX-1 generate
begin
cmp_fei4_rx_channel: fei4_rx_channel PORT MAP(
rst_n_i => rst_n_i,
clk_160_i => rx_clk_i,
clk_640_i => rx_serdes_clk_i,
enable_i => rx_enable(I),
rx_data_i => rx_data_i(I),
trig_tag_i => trig_tag_i,
rx_data_o => rx_data(I),
rx_valid_o => rx_valid(I),
rx_stat_o => rx_stat(I),
rx_data_raw_o => rx_data_raw(I)
);
rx_fifo_din(I) <= STD_LOGIC_VECTOR(TO_UNSIGNED(I,6)) & rx_data(I);
rx_fifo_wren(I) <= rx_valid(I) and rx_enable(I);
cmp_rx_channel_fifo : rx_channel_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => rx_clk_i,
rd_clk => wb_clk_i,
din => rx_fifo_din(I),
wr_en => rx_fifo_wren(I),
rd_en => rx_fifo_rden(I),
dout => rx_fifo_dout(I),
full => rx_fifo_full(I),
empty => rx_fifo_empty(I)
);
end generate;
end behavioral;
|
gpl-3.0
|
c37622337ef9ceb82c393464d62431da
| 0.595593 | 2.488992 | false | false | false | false |
starsheriff/papilio-one250
|
pong/img_gen.vhd
| 1 | 5,389 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:26:56 10/25/2015
-- Design Name:
-- Module Name: img_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity img_gen is
Port ( x_pos : in STD_LOGIC_VECTOR (9 downto 0);
y_pos : in STD_LOGIC_VECTOR (9 downto 0);
clk : in STD_LOGIC;
JOY_LEFT: in STD_LOGIC;
JOY_RIGHT: in STD_LOGIC;
video_on : in STD_LOGIC;
rgb : out STD_LOGIC_VECTOR (7 downto 0));
end img_gen;
architecture Behavioral of img_gen is
signal x,y : integer range 0 to 800;
signal mux:std_logic_vector(3 downto 0);
signal rgb_transient: STD_LOGIC_VECTOR(7 downto 0);
--wall
constant wall_l:integer :=10;--the distance between wall and left side of screen
constant wall_t:integer :=10;--the distance between wall and top side of screen
constant wall_k:integer :=10;--wall thickness
signal wall_on:std_logic;
signal rgb_wall:std_logic_vector(7 downto 0) := "00000000";
-- bar
signal bar_l,bar_l_next:integer :=100; --the distance between bar and left side of screen
constant bar_t:integer :=420;--the distance between bar and top side of screen
constant bar_k:integer :=10;--bar thickness
constant bar_w:integer:=120;--bar width
constant bar_v:integer:=10;--velocity of the bar
signal bar_on:std_logic;
--signal rgb_bar:std_logic_vector(2 downto 0);
--ball
signal ball_l,ball_l_next:integer :=100;--the distance between ball and left side of screen
signal ball_t,ball_t_next:integer :=100; --the distance between ball and top side of screen
constant ball_w:integer :=20;--ball Height
constant ball_u:integer :=20;--ball width
constant x_v,y_v:integer:=3;-- horizontal and vertical speeds of the ball
signal ball_on:std_logic;
constant rgb_ball:std_logic_vector(7 downto 0) := "11111000";
--refreshing(1/60)
signal refresh_reg,refresh_next:integer;
constant refresh_constant:integer:=416666;
signal refresh_tick:std_logic;
--ball animation
signal xv_reg,xv_next:integer:=3;--variable of the horizontal speed
signal yv_reg,yv_next:integer:=3;--variable of the vertical speed
begin
x <= to_integer(unsigned(x_pos));
y <= to_integer(unsigned(y_pos));
--rgb <= "11111111" when x<10 and video_on='1' else
-- "00000000";
-- refresh
process(clk)
begin
if rising_edge(clk) then
refresh_reg <= refresh_next;
end if;
end process;
refresh_next <= 0 when refresh_reg=refresh_constant else
refresh_reg+1;
refresh_tick <= '1' when refresh_reg=0 else '0';
-- register
process(clk)
begin
if rising_edge(clk) then
ball_l<=ball_l_next;
ball_t<=ball_t_next;
xv_reg<=xv_next;
yv_reg<=yv_next;
bar_l<=bar_l_next;
end if;
end process;
-- bar movement
process(refresh_tick, bar_l, JOY_LEFT, JOY_RIGHT)
begin
if rising_edge(refresh_tick) then
if JOY_LEFT='0' and bar_l > bar_v then
bar_l_next <= bar_l - bar_v;
elsif JOY_RIGHT='0' and bar_l < (639-bar_v-bar_w) then
bar_l_next <= bar_l + bar_v;
end if;
end if;
end process;
--ball animation
process(refresh_tick, ball_l, ball_t, xv_reg, yv_reg)
begin
--ball_l_next <= ball_l;
--ball_t_next <= ball_t;
--xv_next <= xv_reg;
--yv_next <= yv_reg;
if rising_edge(refresh_tick) then
if ball_t> 400 and ball_l > (bar_l -ball_u) and ball_l < (bar_l +120) then
yv_next <= -y_v; --ball goes up
elsif ball_t< 35 then
yv_next <= y_v; --ball goes down
end if;
if ball_l < 10 then
xv_next <= x_v;
elsif ball_l > 600 then
xv_next <= -x_v;
end if;
ball_l_next <= ball_l + xv_reg;
ball_t_next <= ball_t + yv_reg;
end if;
end process;
-- (old)wall_on <= '1' when x<10 or x>628 or y<10 or y>440 else '0';
wall_on <= '1' when x > wall_l and x < (640-wall_l) and y> wall_t and y < (wall_t+ wall_k) else
'0';
bar_on <= '1' when x > bar_l and x < (bar_l+bar_w) and y> bar_t and y < (bar_t+ bar_k) else
'0';
ball_on <= '1' when x > ball_l and x < (ball_l+ball_u) and y> ball_t and y < (ball_t+ ball_w) else
'0';
-- multiplexing final output
mux <= video_on & wall_on & bar_on & ball_on;
with mux select
rgb_transient <= "01110110" when "1000", --background
"11111111" when "1100", --wall
"11111000" when "1010", --bar
rgb_ball when "1001", --ball
"00000000" when others;
-- buffering the output
process(clk)
begin
if rising_edge(clk) then
rgb <= rgb_transient;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
0de5fbab57b68aadea7e677f9f763a1d
| 0.594544 | 3.343052 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/gn4124-core/dma_controller.vhd
| 2 | 19,703 |
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: DMA controller (dma_controller.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 0.2
--
-- description: Manages the DMA transfers.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 30-09-2010 (mcattin) Add status, error and abort
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
entity dma_controller is
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_o : out std_logic_vector(31 downto 0);
dma_ctrl_len_o : out std_logic_vector(31 downto 0);
dma_ctrl_start_l2p_o : out std_logic; -- To the L2P DMA master
dma_ctrl_start_p2l_o : out std_logic; -- To the P2L DMA master
dma_ctrl_start_next_o : out std_logic; -- To the P2L DMA master
dma_ctrl_byte_swap_o : out std_logic_vector(1 downto 0);
dma_ctrl_abort_o : out std_logic;
dma_ctrl_done_i : in std_logic;
dma_ctrl_error_i : in std_logic;
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i : in std_logic_vector(31 downto 0);
next_item_host_addr_h_i : in std_logic_vector(31 downto 0);
next_item_host_addr_l_i : in std_logic_vector(31 downto 0);
next_item_len_i : in std_logic_vector(31 downto 0);
next_item_next_l_i : in std_logic_vector(31 downto 0);
next_item_next_h_i : in std_logic_vector(31 downto 0);
next_item_attrib_i : in std_logic_vector(31 downto 0);
next_item_valid_i : in std_logic;
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i : in std_logic; -- Bus clock
wb_adr_i : in std_logic_vector(3 downto 0); -- Adress
wb_dat_o : out std_logic_vector(31 downto 0); -- Data in
wb_dat_i : in std_logic_vector(31 downto 0); -- Data out
wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wb_cyc_i : in std_logic; -- Read or write cycle
wb_stb_i : in std_logic; -- Read or write strobe
wb_we_i : in std_logic; -- Write
wb_ack_o : out std_logic -- Acknowledge
);
end dma_controller;
architecture behaviour of dma_controller is
------------------------------------------------------------------------------
-- Wishbone slave component declaration
------------------------------------------------------------------------------
component dma_controller_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
clk_i : in std_logic;
-- Port for std_logic_vector field: 'DMA engine control' in reg: 'DMACTRLR'
dma_ctrl_o : out std_logic_vector(31 downto 0);
dma_ctrl_i : in std_logic_vector(31 downto 0);
dma_ctrl_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA engine status' in reg: 'DMASTATR'
dma_stat_o : out std_logic_vector(31 downto 0);
dma_stat_i : in std_logic_vector(31 downto 0);
dma_stat_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address in the carrier' in reg: 'DMACSTARTR'
dma_cstart_o : out std_logic_vector(31 downto 0);
dma_cstart_i : in std_logic_vector(31 downto 0);
dma_cstart_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address (low) in the host' in reg: 'DMAHSTARTLR'
dma_hstartl_o : out std_logic_vector(31 downto 0);
dma_hstartl_i : in std_logic_vector(31 downto 0);
dma_hstartl_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address (high) in the host' in reg: 'DMAHSTARTHR'
dma_hstarth_o : out std_logic_vector(31 downto 0);
dma_hstarth_i : in std_logic_vector(31 downto 0);
dma_hstarth_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA read length in bytes' in reg: 'DMALENR'
dma_len_o : out std_logic_vector(31 downto 0);
dma_len_i : in std_logic_vector(31 downto 0);
dma_len_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pointer (low) to next item in list' in reg: 'DMANEXTLR'
dma_nextl_o : out std_logic_vector(31 downto 0);
dma_nextl_i : in std_logic_vector(31 downto 0);
dma_nextl_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pointer (high) to next item in list' in reg: 'DMANEXTHR'
dma_nexth_o : out std_logic_vector(31 downto 0);
dma_nexth_i : in std_logic_vector(31 downto 0);
dma_nexth_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA chain control' in reg: 'DMAATTRIBR'
dma_attrib_o : out std_logic_vector(31 downto 0);
dma_attrib_i : in std_logic_vector(31 downto 0);
dma_attrib_load_o : out std_logic
);
end component dma_controller_wb_slave;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_IDLE : std_logic_vector(2 downto 0) := "000";
constant c_DONE : std_logic_vector(2 downto 0) := "001";
constant c_BUSY : std_logic_vector(2 downto 0) := "010";
constant c_ERROR : std_logic_vector(2 downto 0) := "011";
constant c_ABORT : std_logic_vector(2 downto 0) := "100";
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- DMA controller registers
signal dma_ctrl : std_logic_vector(31 downto 0);
signal dma_stat : std_logic_vector(31 downto 0);
signal dma_cstart : std_logic_vector(31 downto 0);
signal dma_hstartl : std_logic_vector(31 downto 0);
signal dma_hstarth : std_logic_vector(31 downto 0);
signal dma_len : std_logic_vector(31 downto 0);
signal dma_nextl : std_logic_vector(31 downto 0);
signal dma_nexth : std_logic_vector(31 downto 0);
signal dma_attrib : std_logic_vector(31 downto 0);
signal dma_ctrl_load : std_logic;
signal dma_stat_load : std_logic;
signal dma_cstart_load : std_logic;
signal dma_hstartl_load : std_logic;
signal dma_hstarth_load : std_logic;
signal dma_len_load : std_logic;
signal dma_nextl_load : std_logic;
signal dma_nexth_load : std_logic;
signal dma_attrib_load : std_logic;
signal dma_ctrl_reg : std_logic_vector(31 downto 0);
signal dma_stat_reg : std_logic_vector(31 downto 0);
signal dma_cstart_reg : std_logic_vector(31 downto 0);
signal dma_hstartl_reg : std_logic_vector(31 downto 0);
signal dma_hstarth_reg : std_logic_vector(31 downto 0);
signal dma_len_reg : std_logic_vector(31 downto 0);
signal dma_nextl_reg : std_logic_vector(31 downto 0);
signal dma_nexth_reg : std_logic_vector(31 downto 0);
signal dma_attrib_reg : std_logic_vector(31 downto 0);
-- DMA controller FSM
type dma_ctrl_state_type is (DMA_IDLE, DMA_START_TRANSFER, DMA_TRANSFER,
DMA_START_CHAIN, DMA_CHAIN,
DMA_ERROR, DMA_ABORT);
signal dma_ctrl_current_state : dma_ctrl_state_type;
-- status signals
signal dma_status : std_logic_vector(2 downto 0);
signal dma_error_irq : std_logic;
signal dma_done_irq : std_logic;
begin
------------------------------------------------------------------------------
-- Wishbone slave instanciation
------------------------------------------------------------------------------
dma_controller_wb_slave_0 : dma_controller_wb_slave port map (
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
clk_i => clk_i,
dma_ctrl_o => dma_ctrl,
dma_ctrl_i => dma_ctrl_reg,
dma_ctrl_load_o => dma_ctrl_load,
dma_stat_o => open,
dma_stat_i => dma_stat_reg,
dma_stat_load_o => open,
dma_cstart_o => dma_cstart,
dma_cstart_i => dma_cstart_reg,
dma_cstart_load_o => dma_cstart_load,
dma_hstartl_o => dma_hstartl,
dma_hstartl_i => dma_hstartl_reg,
dma_hstartl_load_o => dma_hstartl_load,
dma_hstarth_o => dma_hstarth,
dma_hstarth_i => dma_hstarth_reg,
dma_hstarth_load_o => dma_hstarth_load,
dma_len_o => dma_len,
dma_len_i => dma_len_reg,
dma_len_load_o => dma_len_load,
dma_nextl_o => dma_nextl,
dma_nextl_i => dma_nextl_reg,
dma_nextl_load_o => dma_nextl_load,
dma_nexth_o => dma_nexth,
dma_nexth_i => dma_nexth_reg,
dma_nexth_load_o => dma_nexth_load,
dma_attrib_o => dma_attrib,
dma_attrib_i => dma_attrib_reg,
dma_attrib_load_o => dma_attrib_load
);
------------------------------------------------------------------------------
-- DMA controller registers
------------------------------------------------------------------------------
p_regs : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
dma_ctrl_reg <= (others => '0');
dma_stat_reg <= (others => '0');
dma_cstart_reg <= (others => '0');
dma_hstartl_reg <= (others => '0');
dma_hstarth_reg <= (others => '0');
dma_len_reg <= (others => '0');
dma_nextl_reg <= (others => '0');
dma_nexth_reg <= (others => '0');
dma_attrib_reg <= (others => '0');
elsif rising_edge(clk_i) then
-- Control register
if (dma_ctrl_load = '1') then
dma_ctrl_reg <= dma_ctrl;
end if;
-- Status register
dma_stat_reg(2 downto 0) <= dma_status;
dma_stat_reg(31 downto 3) <= (others => '0');
-- Target start address
if (dma_cstart_load = '1') then
dma_cstart_reg <= dma_cstart;
end if;
-- Host start address lowest 32-bit
if (dma_hstartl_load = '1') then
dma_hstartl_reg <= dma_hstartl;
end if;
-- Host start address highest 32-bit
if (dma_hstarth_load = '1') then
dma_hstarth_reg <= dma_hstarth;
end if;
-- DMA transfer length in byte
if (dma_len_load = '1') then
dma_len_reg <= dma_len;
end if;
-- next item address lowest 32-bit
if (dma_nextl_load = '1') then
dma_nextl_reg <= dma_nextl;
end if;
-- next item address highest 32-bit
if (dma_nexth_load = '1') then
dma_nexth_reg <= dma_nexth;
end if;
-- Chained DMA control
if (dma_attrib_load = '1') then
dma_attrib_reg <= dma_attrib;
end if;
-- next item received => start a new transfer
if (next_item_valid_i = '1') then
dma_ctrl_reg(0) <= '1';
dma_cstart_reg <= next_item_carrier_addr_i;
dma_hstartl_reg <= next_item_host_addr_l_i;
dma_hstarth_reg <= next_item_host_addr_h_i;
dma_len_reg <= next_item_len_i;
dma_nextl_reg <= next_item_next_l_i;
dma_nexth_reg <= next_item_next_h_i;
dma_attrib_reg <= next_item_attrib_i;
end if;
-- Start DMA, 1 tick pulse
if (dma_ctrl_reg(0) = '1') then
dma_ctrl_reg(0) <= '0';
end if;
end if;
end process p_regs;
dma_ctrl_byte_swap_o <= dma_ctrl_reg(3 downto 2);
------------------------------------------------------------------------------
-- IRQ output assignement
------------------------------------------------------------------------------
dma_ctrl_irq_o <= dma_error_irq & dma_done_irq;
------------------------------------------------------------------------------
-- DMA controller FSM
------------------------------------------------------------------------------
p_fsm : process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= c_IDLE;
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
elsif rising_edge(clk_i) then
case dma_ctrl_current_state is
when DMA_IDLE =>
-- Clear done irq to make it 1 tick pulse
dma_done_irq <= '0';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_START_TRANSFER =>
-- Clear abort signal
dma_ctrl_abort_o <= '0';
if (unsigned(dma_len_reg(31 downto 2)) = 0) then
-- Requesting a DMA of 0 word length gives a error
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
else
-- Start the DMA if the length is not 0
if (dma_attrib_reg(1) = '0') then
-- L2P transfer (from target to PCIe)
dma_ctrl_start_l2p_o <= '1';
elsif (dma_attrib_reg(1) = '1') then
-- P2L transfer (from PCIe to target)
dma_ctrl_start_p2l_o <= '1';
end if;
dma_ctrl_current_state <= DMA_TRANSFER;
dma_ctrl_carrier_addr_o <= dma_cstart_reg;
dma_ctrl_host_addr_h_o <= dma_hstarth_reg;
dma_ctrl_host_addr_l_o <= dma_hstartl_reg;
dma_ctrl_len_o <= dma_len_reg;
dma_status <= c_BUSY;
end if;
when DMA_TRANSFER =>
-- Clear start signals, to make them 1 tick pulses
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
if (dma_ctrl_reg(1) = '1') then
-- Transfer aborted
dma_ctrl_current_state <= DMA_ABORT;
elsif(dma_ctrl_error_i = '1') then
-- An error occurs !
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
elsif(dma_ctrl_done_i = '1') then
-- End of DMA transfer
if(dma_attrib_reg(0) = '1') then
-- More transfer in chained DMA
dma_ctrl_current_state <= DMA_START_CHAIN;
else
-- Was the last transfer
dma_status <= c_DONE;
dma_done_irq <= '1';
dma_ctrl_current_state <= DMA_IDLE;
end if;
end if;
when DMA_START_CHAIN =>
-- Catch the next item in host memory
dma_ctrl_current_state <= DMA_CHAIN;
dma_ctrl_host_addr_h_o <= dma_nexth_reg;
dma_ctrl_host_addr_l_o <= dma_nextl_reg;
dma_ctrl_len_o <= X"0000001C";
dma_ctrl_start_next_o <= '1';
when DMA_CHAIN =>
-- Clear start next signal, to make it 1 tick pulse
dma_ctrl_start_next_o <= '0';
if (dma_ctrl_reg(1) = '1') then
-- Transfer aborted
dma_ctrl_current_state <= DMA_ABORT;
elsif(dma_ctrl_error_i = '1') then
-- An error occurs !
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
elsif (next_item_valid_i = '1') then
-- next item received
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_ERROR =>
dma_status <= c_ERROR;
-- Clear error irq to make it 1 tick pulse
dma_error_irq <= '0';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_ABORT =>
dma_status <= c_ABORT;
dma_ctrl_abort_o <= '1';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when others =>
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= (others => '0');
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
end case;
end if;
end process p_fsm;
end behaviour;
|
gpl-3.0
|
0ee657b44f7127da0fbb04fb69efc0f8
| 0.495001 | 3.608608 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_eth_add_crc.vhd
| 1 | 2,957 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_eth_add_crc IS
END tb_eth_add_crc;
ARCHITECTURE behavior OF tb_eth_add_crc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT eth_add_crc
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
InPkt : IN std_logic;
InData : IN std_logic_vector(7 downto 0);
OutPkt : OUT std_logic;
OutData : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
function reversed(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end reversed;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal InPkt : std_logic := '0';
signal InData : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OutPkt : std_logic;
signal OutData : std_logic_vector(7 downto 0);
signal not_out, rev, rev_not : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
not_out <= not OutData;
rev <= reversed(OutData);
rev_not <= not rev;
-- Instantiate the Unit Under Test (UUT)
uut: eth_add_crc PORT MAP (
Clk => Clk,
Rst => Rst,
InPkt => InPkt,
InData => InData,
OutPkt => OutPkt,
OutData => OutData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 104 ns;
wait for Clk_period*10;
InPkt <= '1';
for i in 0 to 6 loop
InData <= X"55";
wait for Clk_period;
end loop;
InData <= X"d5";
wait for Clk_period;
for i in 0 to 63 loop
InData <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
-- InData <= x"00";
-- wait for Clk_period;
InPkt <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
c21335a64132de74b4d68d867929e84c
| 0.621914 | 3.516052 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/trigger.vhd
| 4 | 3,460 |
----------------------------------------------------------------------------------
-- trigger.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Complex 4 stage 32 channel trigger.
--
-- All commands are passed on to the stages. This file only maintains
-- the global trigger level and it outputs the run condition if it is set
-- by any of the stages.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity trigger is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0);
inputReady : in std_logic;
data : in STD_LOGIC_VECTOR (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in STD_LOGIC_VECTOR (3 downto 0);
wrValue : in STD_LOGIC_VECTOR (3 downto 0);
wrConfig : in STD_LOGIC_VECTOR (3 downto 0);
arm : in STD_LOGIC;
demuxed : in std_logic;
run : out STD_LOGIC
);
end trigger;
architecture Behavioral of trigger is
COMPONENT stage
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : IN std_logic;
data : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
reset : IN std_logic;
wrMask : IN std_logic;
wrValue : IN std_logic;
wrConfig : IN std_logic;
arm : IN std_logic;
level : in std_logic_vector(1 downto 0);
demuxed : IN std_logic;
run : OUT std_logic;
match : OUT std_logic
);
END COMPONENT;
signal stageRun, stageMatch: std_logic_vector(3 downto 0);
signal levelReg : std_logic_vector(1 downto 0);
begin
-- create stages
stages: for i in 0 to 3 generate
Inst_stage: stage PORT MAP(
input => input,
inputReady => inputReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrMask(i),
wrValue => wrValue(i),
wrConfig => wrConfig(i),
arm => arm,
level => levelReg,
demuxed => demuxed,
run => stageRun(i),
match => stageMatch(i)
);
end generate;
-- increase level on match
process(clock, arm)
variable tmp : std_logic;
begin
if arm = '1' then
levelReg <= "00";
elsif rising_edge(clock) then
tmp := stageMatch(0);
for i in 1 to 3 loop
tmp := tmp or stageMatch(i);
end loop;
if tmp = '1' then
levelReg <= levelReg + 1;
end if;
end if;
end process;
-- if any of the stages set run, capturing starts
process(stageRun)
variable tmp : std_logic;
begin
tmp := stageRun(0);
for i in 1 to 3 loop
tmp := tmp or stageRun(i);
end loop;
run <= tmp;
end process;
end Behavioral;
|
gpl-2.0
|
e3e5b7dd728c732070ea511271af17e3
| 0.610694 | 3.552361 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_Equalizer_Debugger.vhd
| 1 | 3,371 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_Equalizer_Debugger is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_Equalizer_Debugger;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_Equalizer_Debugger is
begin
Generic_Equalizer : entity work.Generic_Equalizer
generic map(NO_SECTIONS => 9,
INPUT_WIDTH => 16,
INPUT_FRACT => 14,
OUTPUT_WIDTH => 16,
OUTPUT_FRACT => 14,
SCALE_WIDTH => 16,
SCALE_FRACT => (14,14,14,14,14,14,14,14,14,14),
INTERNAL_WIDTH => 16,
INTERNAL_FRACT => 14,
COEFF_WIDTH_B => 16,
COEFF_FRACT_B => (14,14,14,14,14,14,14,14,14),
COEFF_WIDTH_A => 16,
COEFF_FRACT_A => (14,14,14,14,14,14,14,14,14))
port map(clk => clk,
reset => reset,
x => input,
scale => (x"4000"
& x"4001"
& x"4002"
& x"4003"
& x"4004"
& x"4005"
& x"4006"
& x"4007"
& x"4008"
& x"4009"),
b0 => (x"4010"
& x"4011"
& x"4012"
& x"4013"
& x"4014"
& x"4015"
& x"4016"
& x"4017"
& x"4018"),
b1 => (x"4020"
& x"0021"
& x"0022"
& x"0023"
& x"0024"
& x"0025"
& x"0026"
& x"0027"
& x"0028"),
b2 => (x"4030"
& x"0031"
& x"0032"
& x"0033"
& x"0034"
& x"0035"
& x"0036"
& x"0037"
& x"0038"),
a1 => (x"4040"
& x"0041"
& x"0042"
& x"0043"
& x"0044"
& x"0045"
& x"0046"
& x"0047"
& x"0048"),
a2 => (x"4050"
& x"0051"
& x"0052"
& x"0053"
& x"0054"
& x"0055"
& x"0056"
& x"0057"
& x"0058"),
y => output);
end architecture;
|
mit
|
4e1fc7f3ae63b1a81639c0a9dbdf7d54
| 0.261347 | 4.774788 | false | false | false | false |
freecores/minimips
|
miniMIPS/bench/bench_minimips.vhd
| 1 | 5,393 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
library IEEE;
use IEEE.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.pack_mips.all;
entity sim_minimips is
end;
architecture bench of sim_minimips is
component minimips is
port (
clock : in std_logic;
reset : in std_logic;
ram_req : out std_logic;
ram_adr : out bus32;
ram_r_w : out std_logic;
ram_data : inout bus32;
ram_ack : in std_logic;
it_mat : in std_logic
);
end component;
component ram is
generic (mem_size : natural := 256;
latency : time := 10 ns);
port(
req : in std_logic;
adr : in bus32;
data_inout : inout bus32;
r_w : in std_logic;
ready : out std_logic
);
end component;
component rom is
generic (mem_size : natural := 256;
start : natural := 0;
latency : time := 10 ns);
port(
adr : in bus32;
donnee : out bus32;
ack : out std_logic;
load : in std_logic;
fname : in string
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic;
signal it_mat : std_logic := '0';
-- Connexion with the code memory
signal load : std_logic;
signal fichier : string(1 to 7);
-- Connexion with the Ram
signal ram_req : std_logic;
signal ram_adr : bus32;
signal ram_r_w : std_logic;
signal ram_data : bus32;
signal ram_rdy : std_logic;
begin
U_minimips : minimips port map (
clock => clock,
reset => reset,
ram_req => ram_req,
ram_adr => ram_adr,
ram_r_w => ram_r_w,
ram_data => ram_data,
ram_ack => ram_rdy,
it_mat => it_mat
);
U_ram : ram port map (
req => ram_req,
adr => ram_adr,
data_inout => ram_data,
r_w => ram_r_w,
ready => ram_rdy
);
U_rom : rom port map (
adr => ram_adr,
donnee => ram_data,
ack => ram_rdy,
load => load,
fname => fichier
);
clock <= not clock after 20 ns;
reset <= '0', '1' after 5 ns, '0' after 70 ns;
ram_data <= (others => 'L');
process
variable command : line;
variable nomfichier : string(1 to 3);
begin
write (output, "Enter the filename : ");
readline(input, command);
read(command, nomfichier);
fichier <= nomfichier & ".bin";
load <= '1';
wait;
end process;
-- Memory Mapping
-- 0000 - 00FF ROM
process (ram_adr, ram_r_w, ram_data)
begin -- Emulation of an I/O controller
ram_data <= (others => 'Z');
case ram_adr is
when X"00001000" => -- declenche une lecture avec interruption
it_mat <= '1' after 1000 ns;
ram_rdy <= '1' after 5 ns;
when X"00001001" => -- fournit la donnee et lache l'it
it_mat <= '0';
ram_data <= X"FFFFFFFF";
ram_rdy <= '1' after 5 ns;
when others => ram_rdy <= 'L';
end case;
end process;
end bench;
|
gpl-2.0
|
18ee072ca584132252d2feb19f79ecf2
| 0.436121 | 4.490425 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Decimator/Decimator_tb.vhd
| 1 | 15,744 |
----------------------------------
-- testbench type 3 for --
-- multiplier/accumulator (MAC) --
-- for generic vector --
----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY decimator_tb IS
PORT(y:OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END decimator_tb;
ARCHITECTURE arch_decimator_tb OF
decimator_tb IS
COMPONENT Decimator is
Port ( input: in std_logic_vector(15 downto 0);
output: out std_logic_vector(15 downto 0);
clk :in std_logic;
reset:in std_logic
);
END COMPONENT Decimator;
SIGNAL x_tb_signal:STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL y_tb_signal:STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL clk_tb_signal:STD_LOGIC:='0';
SIGNAL reset_tb_signal:STD_LOGIC;
BEGIN
decimator_comp:
COMPONENT Decimator
PORT MAP(clk=>clk_tb_signal,
reset=>reset_tb_signal,
input=>x_tb_signal,
output=>y_tb_signal);
y <= y_tb_signal;
reset_tb_signal<='0',
'1' AFTER 15 ns,
'0' AFTER 25 ns;
x_tb_signal<="0000000000000000", -- 0
"0001000100010000" AFTER 20 ns, -- 0,5=64
"0010001000100000" AFTER 40 ns, -- -0,25=-32=224
"0011001100110000" AFTER 60 ns, -- 0,375=48
"0100010001000000" AFTER 80 ns, -- -0,75=-96=160
"0101010101010000" AFTER 100 ns, -- -0,25=-32=224
"0110011001100000" AFTER 120 ns, -- 0,375=48
"0111011101110000" AFTER 140 ns, -- -0,75=-96=160
"1000100010000000" AFTER 160 ns,
"1001100110010000" AFTER 180 ns,
"1010101010100000" AFTER 200 ns,
"1011101110110000" AFTER 220 ns,
"1100110011000000" AFTER 240 ns,
"1101110111010000" AFTER 260 ns,
"1110111011100000" AFTER 280 ns,
"1111111111110000" AFTER 300 ns,
"0000000000000000" AFTER 320 ns,
"0001000100010000" AFTER 340 ns, -- 0,5=64
"0010001000100000" AFTER 360 ns, -- -0,25=-32=224
"0011001100110000" AFTER 380 ns, -- 0,375=48
"0100010001000000" AFTER 400 ns, -- -0,75=-96=160
"0101010101010000" AFTER 420 ns, -- -0,25=-32=224
"0110011001100000" AFTER 440 ns, -- 0,375=48
"0111011101110000" AFTER 460 ns, -- -0,75=-96=160
"1000100010000000" AFTER 480 ns,
"1001100110010000" AFTER 500 ns,
"1010101010100000" AFTER 520 ns,
"1011101110110000" AFTER 540 ns,
"1100110011000000" AFTER 560 ns,
"1101110111010000" AFTER 580 ns,
"1110111011100000" AFTER 600 ns,
"1111111111110000" AFTER 620 ns,
"0000000000000000" AFTER 640 ns,
"0001000100010000" AFTER 660 ns, -- 0,5=64
"0010001000100000" AFTER 680 ns, -- -0,25=-32=224
"0011001100110000" AFTER 700 ns, -- 0,375=48
"0100010001000000" AFTER 720 ns, -- -0,75=-96=160
"0101010101010000" AFTER 740 ns, -- -0,25=-32=224
"0110011001100000" AFTER 760 ns, -- 0,375=48
"0111011101110000" AFTER 780 ns, -- -0,75=-96=160
"1000100010000000" AFTER 800 ns,
"1001100110010000" AFTER 820 ns,
"1010101010100000" AFTER 840 ns,
"1011101110110000" AFTER 860 ns,
"1100110011000000" AFTER 880 ns,
"1101110111010000" AFTER 900 ns,
"1110111011100000" AFTER 920 ns,
"1111111111110000" AFTER 940 ns,
"0000000000000000" AFTER 960 ns,
"0001000100010000" AFTER 980 ns, -- 0,5=64
"0010001000100000" AFTER 1000 ns, -- -0,25=-32=224
"0011001100110000" AFTER 1020 ns, -- 0,375=48
"0100010001000000" AFTER 1040 ns, -- -0,75=-96=160
"0101010101010000" AFTER 1060 ns, -- -0,25=-32=224
"0110011001100000" AFTER 1080 ns, -- 0,375=48
"0111011101110000" AFTER 1100 ns, -- -0,75=-96=160
"1000100010000000" AFTER 1120 ns,
"1001100110010000" AFTER 1140 ns,
"1010101010100000" AFTER 1160 ns,
"1011101110110000" AFTER 1180 ns,
"1100110011000000" AFTER 1200 ns,
"1101110111010000" AFTER 1220 ns,
"1110111011100000" AFTER 1240 ns,
"1111111111110000" AFTER 1260 ns,
"0000000000000000" AFTER 1280 ns, -- 0
"0001000100010000" AFTER 1300 ns, -- 0,5=64
"0010001000100000" AFTER 1320 ns, -- -0,25=-32=224
"0011001100110000" AFTER 1340 ns, -- 0,375=48
"0100010001000000" AFTER 1360 ns, -- -0,75=-96=160
"0101010101010000" AFTER 1380 ns, -- -0,25=-32=224
"0110011001100000" AFTER 1400 ns, -- 0,375=48
"0111011101110000" AFTER 1420 ns, -- -0,75=-96=160
"1000100010000000" AFTER 1440 ns,
"1001100110010000" AFTER 1460 ns,
"1010101010100000" AFTER 1480 ns,
"1011101110110000" AFTER 1500 ns,
"1100110011000000" AFTER 1520 ns,
"1101110111010000" AFTER 1540 ns,
"1110111011100000" AFTER 1560 ns,
"1111111111110000" AFTER 1580 ns,
"0000000000000000" AFTER 1600 ns,
"0001000100010000" AFTER 1620 ns, -- 0,5=64
"0010001000100000" AFTER 1640 ns, -- -0,25=-32=224
"0011001100110000" AFTER 1660 ns, -- 0,375=48
"0100010001000000" AFTER 1680 ns, -- -0,75=-96=160
"0101010101010000" AFTER 1700 ns, -- -0,25=-32=224
"0110011001100000" AFTER 1720 ns, -- 0,375=48
"0111011101110000" AFTER 1740 ns, -- -0,75=-96=160
"1000100010000000" AFTER 1760 ns,
"1001100110010000" AFTER 1780 ns,
"1010101010100000" AFTER 1800 ns,
"1011101110110000" AFTER 1820 ns,
"1100110011000000" AFTER 1840 ns,
"1101110111010000" AFTER 1860 ns,
"1110111011100000" AFTER 1880 ns,
"1111111111110000" AFTER 1900 ns,
"0000000000000000" AFTER 1920 ns,
"0001000100010000" AFTER 1940 ns, -- 0,5=64
"0010001000100000" AFTER 1960 ns, -- -0,25=-32=224
"0011001100110000" AFTER 1980 ns, -- 0,375=48
"0100010001000000" AFTER 2000 ns, -- -0,75=-96=160
"0101010101010000" AFTER 2020 ns, -- -0,25=-32=224
"0110011001100000" AFTER 2040 ns, -- 0,375=48
"0111011101110000" AFTER 2060 ns, -- -0,75=-96=160
"1000100010000000" AFTER 2080 ns,
"1001100110010000" AFTER 2100 ns,
"1010101010100000" AFTER 2120 ns,
"1011101110110000" AFTER 2140 ns,
"1100110011000000" AFTER 2160 ns,
"1101110111010000" AFTER 2180 ns,
"1110111011100000" AFTER 2200 ns,
"1111111111110000" AFTER 2220 ns,
"0000000000000000" AFTER 2240 ns,
"0001000100010000" AFTER 2260 ns, -- 0,5=64
"0010001000100000" AFTER 2280 ns, -- -0,25=-32=224
"0011001100110000" AFTER 2300 ns, -- 0,375=48
"0100010001000000" AFTER 2320 ns, -- -0,75=-96=160
"0101010101010000" AFTER 2340 ns, -- -0,25=-32=224
"0110011001100000" AFTER 2360 ns, -- 0,375=48
"0111011101110000" AFTER 2380 ns, -- -0,75=-96=160
"1000100010000000" AFTER 2400 ns,
"1001100110010000" AFTER 2420 ns,
"1010101010100000" AFTER 2440 ns,
"1011101110110000" AFTER 2460 ns,
"1100110011000000" AFTER 2480 ns,
"1101110111010000" AFTER 2500 ns,
"1110111011100000" AFTER 2520 ns,
"1111111111110000" AFTER 2540 ns,
"0000000000000000" AFTER 2560 ns, -- 0
"0001000100010000" AFTER 2580 ns, -- 0,5=64
"0010001000100000" AFTER 2600 ns, -- -0,25=-32=224
"0011001100110000" AFTER 2620 ns, -- 0,375=48
"0100010001000000" AFTER 2640 ns, -- -0,75=-96=160
"0101010101010000" AFTER 2660 ns, -- -0,25=-32=224
"0110011001100000" AFTER 2680 ns, -- 0,375=48
"0111011101110000" AFTER 2700 ns, -- -0,75=-96=160
"1000100010000000" AFTER 2720 ns,
"1001100110010000" AFTER 2740 ns,
"1010101010100000" AFTER 2760 ns,
"1011101110110000" AFTER 2780 ns,
"1100110011000000" AFTER 2800 ns,
"1101110111010000" AFTER 2820 ns,
"1110111011100000" AFTER 2840 ns,
"1111111111110000" AFTER 2860 ns,
"0000000000000000" AFTER 2880 ns,
"0001000100010000" AFTER 2900 ns, -- 0,5=64
"0010001000100000" AFTER 2920 ns, -- -0,25=-32=224
"0011001100110000" AFTER 2940 ns, -- 0,375=48
"0100010001000000" AFTER 2960 ns, -- -0,75=-96=160
"0101010101010000" AFTER 2980 ns, -- -0,25=-32=224
"0110011001100000" AFTER 3000 ns, -- 0,375=48
"0111011101110000" AFTER 3020 ns, -- -0,75=-96=160
"1000100010000000" AFTER 3040 ns,
"1001100110010000" AFTER 3060 ns,
"1010101010100000" AFTER 3080 ns,
"1011101110110000" AFTER 3100 ns,
"1100110011000000" AFTER 3120 ns,
"1101110111010000" AFTER 3140 ns,
"1110111011100000" AFTER 3160 ns,
"1111111111110000" AFTER 3180 ns,
"0000000000000000" AFTER 3200 ns,
"0001000100010000" AFTER 3220 ns, -- 0,5=64
"0010001000100000" AFTER 3240 ns, -- -0,25=-32=224
"0011001100110000" AFTER 3260 ns, -- 0,375=48
"0100010001000000" AFTER 3280 ns, -- -0,75=-96=160
"0101010101010000" AFTER 3300 ns, -- -0,25=-32=224
"0110011001100000" AFTER 3320 ns, -- 0,375=48
"0111011101110000" AFTER 3340 ns, -- -0,75=-96=160
"1000100010000000" AFTER 3360 ns,
"1001100110010000" AFTER 3380 ns,
"1010101010100000" AFTER 3400 ns,
"1011101110110000" AFTER 3420 ns,
"1100110011000000" AFTER 3440 ns,
"1101110111010000" AFTER 3460 ns,
"1110111011100000" AFTER 3480 ns,
"1111111111110000" AFTER 3500 ns,
"0000000000000000" AFTER 3520 ns,
"0001000100010000" AFTER 3540 ns, -- 0,5=64
"0010001000100000" AFTER 3560 ns, -- -0,25=-32=224
"0011001100110000" AFTER 3580 ns, -- 0,375=48
"0100010001000000" AFTER 3600 ns, -- -0,75=-96=160
"0101010101010000" AFTER 3620 ns, -- -0,25=-32=224
"0110011001100000" AFTER 3640 ns, -- 0,375=48
"0111011101110000" AFTER 3660 ns, -- -0,75=-96=160
"1000100010000000" AFTER 3680 ns,
"1001100110010000" AFTER 3700 ns,
"1010101010100000" AFTER 3720 ns,
"1011101110110000" AFTER 3740 ns,
"1100110011000000" AFTER 3760 ns,
"1101110111010000" AFTER 3780 ns,
"1110111011100000" AFTER 3800 ns,
"1111111111110000" AFTER 3820 ns,
"0000000000000000" AFTER 3840 ns, -- 0
"0001000100010000" AFTER 3860 ns, -- 0,5=64
"0010001000100000" AFTER 3880 ns, -- -0,25=-32=224
"0011001100110000" AFTER 3900 ns, -- 0,375=48
"0100010001000000" AFTER 3920 ns, -- -0,75=-96=160
"0101010101010000" AFTER 3940 ns, -- -0,25=-32=224
"0110011001100000" AFTER 3960 ns, -- 0,375=48
"0111011101110000" AFTER 3980 ns, -- -0,75=-96=160
"1000100010000000" AFTER 4000 ns,
"1001100110010000" AFTER 4020 ns,
"1010101010100000" AFTER 4040 ns,
"1011101110110000" AFTER 4060 ns,
"1100110011000000" AFTER 4080 ns,
"1101110111010000" AFTER 4100 ns,
"1110111011100000" AFTER 4120 ns,
"1111111111110000" AFTER 4140 ns,
"0000000000000000" AFTER 4160 ns,
"0001000100010000" AFTER 4180 ns, -- 0,5=64
"0010001000100000" AFTER 4200 ns, -- -0,25=-32=224
"0011001100110000" AFTER 4220 ns, -- 0,375=48
"0100010001000000" AFTER 4240 ns, -- -0,75=-96=160
"0101010101010000" AFTER 4260 ns, -- -0,25=-32=224
"0110011001100000" AFTER 4280 ns, -- 0,375=48
"0111011101110000" AFTER 4300 ns, -- -0,75=-96=160
"1000100010000000" AFTER 4320 ns,
"1001100110010000" AFTER 4340 ns,
"1010101010100000" AFTER 4360 ns,
"1011101110110000" AFTER 4380 ns,
"1100110011000000" AFTER 4400 ns,
"1101110111010000" AFTER 4420 ns,
"1110111011100000" AFTER 4440 ns,
"1111111111110000" AFTER 4460 ns,
"0000000000000000" AFTER 4480 ns,
"0001000100010000" AFTER 4500 ns, -- 0,5=64
"0010001000100000" AFTER 4520 ns, -- -0,25=-32=224
"0011001100110000" AFTER 4540 ns, -- 0,375=48
"0100010001000000" AFTER 4560 ns, -- -0,75=-96=160
"0101010101010000" AFTER 4580 ns, -- -0,25=-32=224
"0110011001100000" AFTER 4600 ns, -- 0,375=48
"0111011101110000" AFTER 4620 ns, -- -0,75=-96=160
"1000100010000000" AFTER 4640 ns,
"1001100110010000" AFTER 4660 ns,
"1010101010100000" AFTER 4680 ns,
"1011101110110000" AFTER 4700 ns,
"1100110011000000" AFTER 4720 ns,
"1101110111010000" AFTER 4740 ns,
"1110111011100000" AFTER 4760 ns,
"1111111111110000" AFTER 4780 ns,
"0000000000000000" AFTER 4800 ns,
"0001000100010000" AFTER 4820 ns, -- 0,5=64
"0010001000100000" AFTER 4840 ns, -- -0,25=-32=224
"0011001100110000" AFTER 4860 ns, -- 0,375=48
"0100010001000000" AFTER 4880 ns, -- -0,75=-96=160
"0101010101010000" AFTER 4900 ns, -- -0,25=-32=224
"0110011001100000" AFTER 4920 ns, -- 0,375=48
"0111011101110000" AFTER 4940 ns, -- -0,75=-96=160
"1000100010000000" AFTER 4960 ns,
"1001100110010000" AFTER 4980 ns,
"1010101010100000" AFTER 5000 ns,
"1011101110110000" AFTER 5020 ns,
"1100110011000000" AFTER 5040 ns,
"1101110111010000" AFTER 5060 ns,
"1110111011100000" AFTER 5080 ns,
"1111111111110000" AFTER 5100 ns;
clock_proc: process
begin
WAIT FOR 10 ns;
clk_tb_signal<=NOT(clk_tb_signal);
end process clock_proc ;
END arch_decimator_tb;
|
mit
|
13f471a2458f09eaa42239d664147c7c
| 0.530424 | 4.594106 | false | false | false | false |
Project-Bonfire/Bonfire
|
Packages/TB_Package_32_bit_credit_based_vc.vhd
| 1 | 17,549 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(network_size_x, source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal credit_counter_in_vc: in std_logic_vector(1 downto 0); signal valid_out_vc: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic;
signal credit_out_vc: out std_logic; signal valid_in_vc: in std_logic;
signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(network_size_x, source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
variable source_x, source_y, destination_x, destination_y: integer;
begin
-- We only need network_size_x for calculation of X and Y coordinates of a node!
source_x := source mod network_size_x;
source_y := source / network_size_x;
destination_x := destination mod network_size_x;
destination_y := destination / network_size_x;
Header_flit := Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)) &
XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal credit_counter_in_vc: in std_logic_vector(1 downto 0); signal valid_out_vc: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
variable vc: integer:= 0;
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
valid_out_vc <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
-- choose vc
uniform(seed1, seed2, rand);
if (integer(rand*2.0) > 1) then
vc := 1;
else
vc := 0;
end if;
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
valid_out_vc <= '0';
if vc = 0 then
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
else
while credit_counter_in_vc = 0 loop
wait until clk'event and clk ='0';
end loop;
end if;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
end loop;
--------------------------------------
if vc = 0 then
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter) & " vc: 0");
else
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter)& " vc: 1");
end if;
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(network_size_x, source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
if vc = 0 then
valid_out <= '1';
else
valid_out_vc <= '1';
end if;
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if vc = 0 then
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
else
if credit_counter_in_vc = "00" then
valid_out_vc <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in_vc'event and credit_counter_in_vc > 0;
wait until clk'event and clk ='0';
end if;
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
if vc = 0 then
valid_out <= '1';
else
valid_out_vc <= '1';
end if;
wait until clk'event and clk ='0';
end loop;
if vc = 0 then
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
else
if credit_counter_in_vc = "00" then
valid_out_vc <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in_vc'event and credit_counter_in_vc > 0;
wait until clk'event and clk ='0';
end if;
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
if vc = 0 then
valid_out <= '1';
else
valid_out_vc <= '1';
end if;
wait until clk'event and clk ='0';
if vc = 0 then
valid_out <= '0';
else
valid_out_vc <= '0';
end if;
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic;
signal credit_out_vc: out std_logic; signal valid_in_vc: in std_logic;
signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node_x_vc, source_node_y_vc, destination_node_x_vc, destination_node_y_vc: integer;
variable source_node_x, source_node_y, destination_node_x, destination_node_y, source_node, destination_node, P_length, packet_id, counter: integer;
variable source_node_vc, destination_node_vc, P_length_vc, packet_id_vc, counter_vc: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
variable VC : integer;
variable DIAGNOSIS_vector: std_logic_vector(12 downto 0);
begin
credit_out <= '1';
credit_out_vc <= '1';
counter := 0;
counter_vc := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
source_node_y := to_integer(unsigned(port_in(28 downto 22)));
source_node_x := to_integer(unsigned(port_in(21 downto 15)));
destination_node_y := to_integer(unsigned(port_in(14 downto 8)));
destination_node_x := to_integer(unsigned(port_in(7 downto 1)));
-- We only needs network_size_x for computing the node ID (convert from (X,Y) coordinate to Node ID)!
source_node := (source_node_y * network_size_x) + source_node_x;
destination_node := (destination_node_y * network_size_x) + destination_node_x;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter) & " vc: 0";
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id)& " vc: 0");
writeline(VEC_FILE, LINEVARIABLE);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity failure;
counter := 0;
end if;
elsif valid_in_vc = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter_vc := 1;
source_node_y_vc := to_integer(unsigned(port_in(28 downto 22)));
source_node_x_vc := to_integer(unsigned(port_in(21 downto 15)));
destination_node_y_vc := to_integer(unsigned(port_in(14 downto 8)));
destination_node_x_vc := to_integer(unsigned(port_in(7 downto 1)));
-- We only needs network_size_x for computing the node ID (convert from (X,Y) coordinate to Node ID)!
source_node_vc := (source_node_y_vc * network_size_x) + source_node_x_vc;
destination_node_vc := (destination_node_y_vc * network_size_x) + destination_node_x_vc;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
if counter_vc = 1 then
P_length_vc := to_integer(unsigned(port_in(28 downto 15)));
packet_id_vc := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter_vc := counter_vc+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter_vc := counter_vc+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node_vc) & " to " & integer'image(destination_node_vc) & " with length: "& integer'image(P_length_vc) & " counter: "& integer'image(counter_vc) & " vc: 1";
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node_vc) & " to: " & integer'image(destination_node_vc) & " length: "& integer'image(P_length_vc) & " actual length: "& integer'image(counter_vc) & " id: "& integer'image(packet_id_vc)& " vc: 1");
writeline(VEC_FILE, LINEVARIABLE);
assert (P_length=counter_vc) report "wrong packet size" severity warning;
assert (Node_ID=destination_node_vc) report "wrong packet destination " severity failure;
counter_vc := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
gpl-3.0
|
873b918737775219b3c3275ff137abed
| 0.585105 | 3.757011 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/tx-core/serial_port.vhd
| 1 | 1,917 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Serial Port
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_port is
generic (
g_PORT_WIDTH : integer := 32
);
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Input
enable_i : in std_logic;
data_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
data_valid_i : in std_logic;
-- Output
data_o : out std_logic;
data_read_o : out std_logic
);
end serial_port;
architecture behavioral of serial_port is
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
-- Signals
signal bit_count : unsigned(log2_ceil(g_PORT_WIDTH) downto 0);
signal sreg : std_logic_vector(g_PORT_WIDTH-1 downto 0);
begin
-- Tie offs
data_o <= sreg(g_PORT_WIDTH-1);
-- Serializer proc
serialize: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sreg <= (others => '0');
bit_count <= (others => '0');
data_read_o <= '0';
elsif rising_edge(clk_i) then
if (enable_i = '1') then
if (bit_count = g_PORT_WIDTH-1 and data_valid_i = '1') then
sreg <= data_i;
data_read_o <= '1';
bit_count <= (others => '0');
else
sreg <= sreg(g_PORT_WIDTH-2 downto 0) & '0';
data_read_o <= '0';
bit_count <= bit_count + 1;
end if;
else
sreg <= (others => '0');
data_read_o <= '0';
bit_count <= TO_UNSIGNED(g_PORT_WIDTH-1, bit_count'length);
end if;
end if;
end process serialize;
end behavioral;
|
gpl-3.0
|
c407482d04a61cb7fe11bc39b6a3452d
| 0.537298 | 3.033228 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/l2p_fifo.vhd
| 2 | 1,488 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY l2p_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END l2p_fifo;
ARCHITECTURE l2p_fifo_a OF l2p_fifo IS
COMPONENT l2p_fifo64
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
U0 : l2p_fifo64
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full
);
END l2p_fifo_a;
|
gpl-3.0
|
488d410e73fda97f5b67e2533717b661
| 0.609543 | 2.917647 | false | false | false | false |
openttp/openttp
|
software/system/src/fpga/vhdl/TTSCounterPPSCR.vhd
| 1 | 12,781 |
--------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.FRONTPANEL.all;
use work.TRIGGERS.OneShot;
use work.TICOUNTERS.TICounter32;
entity TTSCounterPPSCR is
port (
hi_in : in STD_LOGIC_VECTOR(7 downto 0);
hi_out : out STD_LOGIC_VECTOR(1 downto 0);
hi_inout : inout STD_LOGIC_VECTOR(15 downto 0);
hi_muxsel : out STD_LOGIC;
ct1b : in STD_LOGIC; -- GNSS
ct2b : in STD_LOGIC; -- GNSS
ct3b : in STD_LOGIC; -- GNSS
ct4b : in STD_LOGIC; -- external 1 pps
ct5b : in STD_LOGIC;
refpps: in STD_LOGIC; -- from the system REF
gpio : in STD_LOGIC; --
ppsout : out STD_LOGIC;
gpio_en: out STD_LOGIC;
led : out STD_LOGIC_VECTOR(7 downto 0);
cr1 : out STD_LOGIC;
cr2 : out STD_LOGIC;
clk100 : in STD_LOGIC
);
end TTSCounterPPSCR;
architecture arch of TTSCounterPPSCR is
component PPSToCR is
port (
trigger : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC
);
end component;
signal ti_clk : STD_LOGIC;
signal ok1 : STD_LOGIC_VECTOR(30 downto 0);
signal ok2 : STD_LOGIC_VECTOR(16 downto 0);
-- note that the multiplier of '17' is the number of WireOuts+TriggerOuts
signal ok2s : STD_LOGIC_VECTOR(17*14-1 downto 0);
-- WireIns
signal ep00wire : STD_LOGIC_VECTOR(15 downto 0); -- system control
-- WireOuts
signal ep20wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 1 reading MSB
signal ep21wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 1 reading LSB
signal ep22wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 2 reading
signal ep23wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 2 reading
signal ep24wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 3 reading
signal ep25wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 3 reading
signal ep26wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 4 reading
signal ep27wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 4 reading
signal ep28wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 5 reading
signal ep29wire : STD_LOGIC_VECTOR(15 downto 0); -- counter 5 reading
signal ep2awire : STD_LOGIC_VECTOR(15 downto 0); -- counter 6 reading
signal ep2bwire : STD_LOGIC_VECTOR(15 downto 0); -- counter 6 reading
signal ep2cwire : STD_LOGIC_VECTOR(15 downto 0); -- system status
-- TriggerOuts
signal ep60trig : STD_LOGIC_VECTOR(15 downto 0); -- counter trigger status
signal extclk : STD_LOGIC;
signal sysCtrl : STD_LOGIC_VECTOR(15 downto 0);
signal sysStat : STD_LOGIC_VECTOR(15 downto 0);
signal trigA : STD_LOGIC;
-- per TICounter signals
-- TIC1
signal trigB1 :STD_LOGIC;
signal tint1 :STD_LOGIC_VECTOR(31 downto 0);
signal dataReady1: STD_LOGIC;
signal ledPulse1: STD_LOGIC;
-- TIC2
signal trigB2 :STD_LOGIC;
signal tint2 :STD_LOGIC_VECTOR(31 downto 0);
signal dataReady2: STD_LOGIC;
signal ledPulse2: STD_LOGIC;
-- TIC3
signal trigB3 :STD_LOGIC;
signal tint3 :STD_LOGIC_VECTOR(31 downto 0);
signal dataReady3: STD_LOGIC;
signal ledPulse3: STD_LOGIC;
-- TIC4
signal trigB4 :STD_LOGIC;
signal tint4 :STD_LOGIC_VECTOR(31 downto 0);
signal dataReady4: STD_LOGIC;
signal ledPulse4: STD_LOGIC;
-- TIC5
signal trigB5 :STD_LOGIC;
signal tint5 :STD_LOGIC_VECTOR(31 downto 0);
signal dataReady5: STD_LOGIC;
signal ledPulse5: STD_LOGIC;
-- TIC6
signal trigB6 :STD_LOGIC;
signal tint6 :STD_LOGIC_VECTOR(31 downto 0);
signal dataReady6: STD_LOGIC;
signal ledPulse6: STD_LOGIC;
signal ct6b: STD_LOGIC; -- this is internally connected
-- DCM signals
signal clko0,clk180,clk270,clk2X,clk2x180,clk90,clkdv,clkfx,clkfx180,locked,psdone : STD_LOGIC;
signal status: STD_LOGIC_VECTOR(7 downto 0);
signal clkin,dssen,psclk,psen,psincdec,rst:STD_LOGIC;
begin
hi_muxsel <= '0'; -- required
-- DCM_SP: Digital Clock Manager
-- Spartan-6
-- Xilinx HDL Language Template, version 13.3
DCM_SP_200 : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 20, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 100.0, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLK0 => clko0, -- 1-bit output: 0 degree clock output
CLK180 => clk180, -- 1-bit output: 180 degree clock output
CLK270 => clk270, -- 1-bit output: 270 degree clock output
CLK2X => clk2X, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => clk2X180, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => clk90, -- 1-bit output: 90 degree clock output
CLKDV => clkdv, -- 1-bit output: Divided clock output
CLKFX => clkfx, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => clkfx180, -- 1-bit output: 180 degree CLKFX output
LOCKED => locked, -- 1-bit output: DCM_SP Lock Output
PSDONE => psdone, -- 1-bit output: Phase shift done output
STATUS => status, -- 8-bit output: DCM_SP status output
CLKFB => clko0, -- 1-bit input: Clock feedback input
CLKIN => clk100, -- 1-bit input: Clock input
DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
PSCLK => psclk, -- 1-bit input: Phase shift clock input
PSEN => psen, -- 1-bit input: Phase shift enable
PSINCDEC => psincdec, -- 1-bit input: Phase shift increment/decrement input
RST => rst -- 1-bit input: Active high reset input
);
extclk <= clkfx;
-- Common start trigger for all counters
chanATrig : OneShot port map (trigger=>refpps,clk=>extclk,pulse=>trigA);
-- TIC1
chan1BTrig: OneShot port map (trigger=>ct1b,clk=>extclk,pulse=>trigB1);
tic1 : TICounter32 port map (startTrig => trigA,stopTrig =>trigB1,clk=>extclk,
tint => tint1, dataReady => dataReady1, ledPulse => ledPulse1);
-- TIC2
chan2BTrig: OneShot port map (trigger=>ct2b,clk=>extclk,pulse=>trigB2);
tic2 : TICounter32 port map (startTrig => trigA,stopTrig =>trigB2,clk=>extclk,
tint => tint2, dataReady => dataReady2, ledPulse => ledPulse2);
-- TIC3
chan3BTrig: OneShot port map (trigger=>ct3b,clk=>extclk,pulse=>trigB3);
tic3 : TICounter32 port map (startTrig => trigA,stopTrig =>trigB3,clk=>extclk,
tint => tint3, dataReady => dataReady3, ledPulse => ledPulse3);
-- TIC4
-- TIC4 is triggered differently
-- Start comes from the external 1 PPS
-- Stop comes from the time-transfer GPS Rx 1 PPS
chan4BTrig: OneShot port map (trigger=>ct4b,clk=>extclk,pulse=>trigB4);
tic4 : TICounter32 port map (startTrig => trigB4,stopTrig =>trigB3,clk=>extclk,
tint => tint4, dataReady => dataReady4, ledPulse => ledPulse4);
-- TIC5
chan5BTrig: OneShot port map (trigger=>ct5b,clk=>extclk,pulse=>trigB5);
tic5 : TICounter32 port map (startTrig => trigA,stopTrig =>trigB5,clk=>extclk,
tint => tint5, dataReady => dataReady5, ledPulse => ledPulse5);
-- TIC6
chan6BTrig: OneShot port map (trigger=>ct6b,clk=>extclk,pulse=>trigB6);
tic6 : TICounter32 port map (startTrig => trigA,stopTrig =>trigB6,clk=>extclk,
tint => tint6, dataReady => dataReady6, ledPulse => ledPulse6);
-- 1 pps to ASCII carriage-return
ppscr1: PPSToCR port map (trigger=>refpps,clk=>clk100,serial_out=>cr1);
ppscr2: PPSToCR port map (trigger=>ct2b,clk=>clk100,serial_out=>cr2);
-- outputs to the host
ep21wire <= tint1(31 downto 16);
ep20wire <= tint1(15 downto 0);
ep23wire <= tint2(31 downto 16);
ep22wire <= tint2(15 downto 0);
ep25wire <= tint3(31 downto 16);
ep24wire <= tint3(15 downto 0);
ep27wire <= tint4(31 downto 16);
ep26wire <= tint4(15 downto 0);
ep29wire <= tint5(31 downto 16);
ep28wire <= tint5(15 downto 0);
ep2bwire <= tint6(31 downto 16);
ep2awire <= tint6(15 downto 0);
-- counter trigger state
ep60trig <= "0000000000" & dataReady6 & dataReady5 & dataReady4 & dataReady3 & dataReady2 & dataReady1;
-- system config/status
-- bit 2->0: pps out source
-- bit 3 : GPIO enabled
-- bit 4 : DCM locked
ep2cwire <= sysStat;
sysStat <= "00000000000" & locked & sysCtrl(3) & sysCtrl(2 downto 0);
-- system control register
-- bits 2->0 : selection of output 1 pps source
-- bit 3 : enable external I/O on GPIO pin
sysCtrl <= ep00wire; -- endpoints are registers, it seems
-- MUX to select pps out source
with (sysCtrl(2 downto 0)) select
ppsout <= ct1b when "001",
ct2b when "010", -- this is the default
ct3b when "011",
ct4b when "100",
ct5b when "101",
ct6b when "110",
refpps when others;
gpio_en <= sysCtrl(3);
-- gpio_en <= '1';
ct6b <= gpio; -- default setup is as input to the 6th counter. In other applications, it might be an input to something else
-- outputs to FPGA 'peripherals'
-- bits 0-5: counter 1 pps in
-- bit 6: ext_io_en (for debugging)
-- bit 7: DCM lock
led <= (not locked) & (not sysCtrl(3)) & (not ledPulse6) & (not ledPulse5) & (not ledPulse4) & (not ledPulse3) & (not ledPulse2) & (not ledPulse1);
-- Instantiate the okHost and connect endpoints
okHI : okHost port map (
hi_in=>hi_in, hi_out=>hi_out, hi_inout=>hi_inout,
ti_clk=>ti_clk, ok1=>ok1, ok2=>ok2);
okWO : okWireOR generic map (N=>14) port map (ok2=>ok2, ok2s=>ok2s);
-- WireOuts are updated synchronously with the host interface clock.
-- In particular, the counter readings have to cross a clock domain. This can be done without a synchronizer because
-- the counters are always read after a value has been stored in the counter's output register.
-- So, no synchronizers to cross the clock domains.
ep20 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 1*17-1 downto 0*17 ), ep_addr=>x"20", ep_datain=>ep20wire);
ep21 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 2*17-1 downto 1*17 ), ep_addr=>x"21", ep_datain=>ep21wire);
ep22 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 3*17-1 downto 2*17 ), ep_addr=>x"22", ep_datain=>ep22wire);
ep23 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 4*17-1 downto 3*17 ), ep_addr=>x"23", ep_datain=>ep23wire);
ep24 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 5*17-1 downto 4*17 ), ep_addr=>x"24", ep_datain=>ep24wire);
ep25 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 6*17-1 downto 5*17 ), ep_addr=>x"25", ep_datain=>ep25wire);
ep26 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 7*17-1 downto 6*17 ), ep_addr=>x"26", ep_datain=>ep26wire);
ep27 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 8*17-1 downto 7*17 ), ep_addr=>x"27", ep_datain=>ep27wire);
ep28 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 9*17-1 downto 8*17 ), ep_addr=>x"28", ep_datain=>ep28wire);
ep29 : okWireOut port map (ok1=>ok1, ok2=>ok2s( 10*17-1 downto 9*17 ), ep_addr=>x"29", ep_datain=>ep29wire);
ep2a : okWireOut port map (ok1=>ok1, ok2=>ok2s( 11*17-1 downto 10*17 ), ep_addr=>x"2a", ep_datain=>ep2awire);
ep2b : okWireOut port map (ok1=>ok1, ok2=>ok2s( 12*17-1 downto 11*17 ), ep_addr=>x"2b", ep_datain=>ep2bwire);
-- system status
ep2c : okWireOut port map (ok1=>ok1, ok2=>ok2s( 13*17-1 downto 12*17 ), ep_addr=>x"2c", ep_datain=>ep2cwire);
-- system control register
-- WireIns map between 0x00 and 0x1f
ep00 : okWireIn port map (ok1=>ok1, ep_addr=>x"00", ep_dataout=>ep00wire);
-- counter trigger state
ep60 : okTriggerOut port map (ok1=>ok1,ok2=>ok2s( 14*17-1 downto 13*17 ), ep_addr=>x"60", ep_clk=>extclk, ep_trigger=>ep60trig);
end arch;
|
mit
|
eeca1734fa49635b06f4cc68ebcfdc06
| 0.646663 | 3.08273 | false | false | false | false |
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/mig_wrapper/mig_wrapper.vhd
| 1 | 13,680 |
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Jakub Cabal <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/mig_ddr3_wrapper_virtex6
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity MIG_WRAPPER is
generic(
-- DO NOT CHANGE THESE VALUES!
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per Rank for phy.
BANK_WIDTH : integer := 3; -- # of memory Bank Address bits.
CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory.
CKE_WIDTH : integer := 1; -- # of CKE outputs to memory.
CS_WIDTH : integer := 1; -- # of unique CS outputs to memory.
DM_WIDTH : integer := 8; -- # of Data Mask bits.
DQ_WIDTH : integer := 64; -- # of Data (DQ) bits.
DQS_WIDTH : integer := 8; -- # of DQS/DQS# bits.
ROW_WIDTH : integer := 14; -- # of memory Row Address bits.
-- ONLY FOR SIMULATION
SIM_BYPASS_INIT_CAL : string := "OFF" -- # = "OFF" - Complete memory init & calibration sequence
-- # = "FAST" - Skip memory init & use abbreviated calib sequence
);
Port (
-- CLOCKS AND RESETS
CLK_REF_P : in std_logic;
CLK_REF_N : in std_logic;
ASYNC_RST : in std_logic;
USER_CLK_OUT : out std_logic;
USER_RST_OUT : out std_logic;
-- USER INTERFACE
MIG_ADDR : in std_logic_vector(24 downto 0);
MIG_READY : out std_logic;
MIG_RD_EN : in std_logic;
MIG_WR_EN : in std_logic;
MIG_WR_DATA : in std_logic_vector(511 downto 0);
MIG_RD_DATA : out std_logic_vector(511 downto 0);
MIG_RD_DATA_VLD : out std_logic;
-- DDR3 INTERFACE
DDR3_DQ : inout std_logic_vector(DQ_WIDTH-1 downto 0);
DDR3_DM : out std_logic_vector(DM_WIDTH-1 downto 0);
DDR3_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
DDR3_BA : out std_logic_vector(BANK_WIDTH-1 downto 0);
DDR3_RAS_N : out std_logic;
DDR3_CAS_N : out std_logic;
DDR3_WE_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_CS_N : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
DDR3_ODT : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
DDR3_CKE : out std_logic_vector(CKE_WIDTH-1 downto 0);
DDR3_DQS_P : inout std_logic_vector(DQS_WIDTH-1 downto 0);
DDR3_DQS_N : inout std_logic_vector(DQS_WIDTH-1 downto 0);
DDR3_CK_P : out std_logic_vector(CK_WIDTH-1 downto 0);
DDR3_CK_N : out std_logic_vector(CK_WIDTH-1 downto 0);
PHY_INIT_DONE : out std_logic
);
end MIG_WRAPPER;
architecture FULL of MIG_WRAPPER is
signal user_clk : std_logic;
signal user_rst : std_logic;
signal app_cmd_addr : std_logic_vector(27 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_cmd_en : std_logic;
signal app_cmd_rdy : std_logic;
signal app_wr_data : std_logic_vector(255 downto 0);
signal app_wr_data_end : std_logic;
signal app_wr_data_vld : std_logic;
signal app_wr_data_rdy : std_logic;
signal app_full_rdy : std_logic;
signal app_rd_data : std_logic_vector(255 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_vld : std_logic;
signal mig_wr_data2_reg_en : std_logic;
signal mig_wr_data2_reg : std_logic_vector(255 downto 0);
type state is (first_state, second_state);
signal present_state : state;
signal next_state : state;
begin
USER_CLK_OUT <= user_clk;
USER_RST_OUT <= user_rst;
app_full_rdy <= app_cmd_rdy AND app_wr_data_rdy;
app_cmd <= "00" & MIG_RD_EN;
app_cmd_addr <= MIG_ADDR & "000";
app_wr_data <= mig_wr_data2_reg WHEN (app_wr_data_end = '1') ELSE MIG_WR_DATA(255 downto 0);
-- -------------------------------------------------------------------------
-- MIG WRAPPER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
present_state_reg : process (user_clk)
begin
if (rising_edge(user_clk)) then
if (user_rst = '1') then
present_state <= first_state;
else
present_state <= next_state;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (present_state, MIG_WR_EN, MIG_RD_EN, app_full_rdy)
begin
case present_state is
when first_state =>
app_wr_data_end <= '0';
MIG_READY <= app_full_rdy;
if (MIG_WR_EN = '1' AND app_full_rdy = '1') then
app_cmd_en <= '1';
app_wr_data_vld <= '1';
mig_wr_data2_reg_en <= '1';
next_state <= second_state;
elsif (MIG_RD_EN = '1' AND app_full_rdy = '1') then
app_cmd_en <= '1';
app_wr_data_vld <= '0';
mig_wr_data2_reg_en <= '0';
next_state <= first_state;
else
app_cmd_en <= '0';
app_wr_data_vld <= '0';
mig_wr_data2_reg_en <= '0';
next_state <= first_state;
end if;
when second_state =>
app_cmd_en <= '0';
app_wr_data_end <= '1';
mig_wr_data2_reg_en <= '0';
MIG_READY <= '0';
if (app_full_rdy = '1') then
app_wr_data_vld <= '1';
next_state <= first_state;
else
app_wr_data_vld <= '0';
next_state <= second_state;
end if;
when others =>
app_cmd_en <= '0';
app_wr_data_end <= '0';
app_wr_data_vld <= '0';
mig_wr_data2_reg_en <= '0';
MIG_READY <= '0';
next_state <= first_state;
end case;
end process;
-- -------------------------------------------------------------------------
-- MIG WRAPPER WRITE DATA PART REGISTER
-- -------------------------------------------------------------------------
-- MIG SECOND WRITE DATA PART REGISTER
mig_wr_data2_reg_p : process (user_clk)
begin
if (rising_edge(user_clk)) then
if (user_rst = '1') then
mig_wr_data2_reg <= (others => '0');
elsif (mig_wr_data2_reg_en = '1') then
mig_wr_data2_reg <= MIG_WR_DATA(511 downto 256);
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- MIG WRAPPER READ REGISTERS
-- -------------------------------------------------------------------------
-- MIG READ DATA REGISTER
mig_rd_data_reg_p : process (user_clk)
begin
if (rising_edge(user_clk)) then
if (user_rst = '1') then
MIG_RD_DATA <= (others => '0');
elsif (app_rd_data_vld = '1') then
if (app_rd_data_end = '1') then
MIG_RD_DATA(511 downto 256) <= app_rd_data;
else
MIG_RD_DATA(255 downto 0) <= app_rd_data;
end if;
end if;
end if;
end process;
-- MIG READ DATA VALID REGISTER
mig_rd_data_vld_reg_p : process (user_clk)
begin
if (rising_edge(user_clk)) then
if (user_rst = '1') then
MIG_RD_DATA_VLD <= '0';
else
MIG_RD_DATA_VLD <= app_rd_data_end AND app_rd_data_vld;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- MIG DDR3 CORE MODULE EDITED FOR ML605 BOARD
-- -------------------------------------------------------------------------
mig_ddr3_core_i : entity work.mig_ddr3_core
generic map(
REFCLK_FREQ => 200.0,
MMCM_ADV_BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 6,
DIVCLK_DIVIDE => 1,
CLKOUT_DIVIDE => 3,
nCK_PER_CLK => 2,
tCK => 2500,
DEBUG_PORT => "OFF",
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
nCS_PER_RANK => nCS_PER_RANK,
DQS_CNT_WIDTH => 3,
RANK_WIDTH => 1,
BANK_WIDTH => BANK_WIDTH,
CK_WIDTH => CK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
COL_WIDTH => 10,
CS_WIDTH => CS_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DM_WIDTH => DM_WIDTH,
DQS_WIDTH => DQS_WIDTH,
ROW_WIDTH => ROW_WIDTH,
BURST_MODE => "8",
BM_CNT_WIDTH => 2,
ADDR_CMD_MODE => "1T",
ORDERING => "STRICT",
WRLVL => "ON",
PHASE_DETECT => "ON",
RTT_NOM => "60",
RTT_WR => "OFF",
OUTPUT_DRV => "HIGH",
REG_CTRL => "OFF",
nDQS_COL0 => 3,
nDQS_COL1 => 5,
nDQS_COL2 => 0,
nDQS_COL3 => 0,
DQS_LOC_COL0 => X"020100",
DQS_LOC_COL1 => X"0706050403",
DQS_LOC_COL2 => "0",
DQS_LOC_COL3 => "0",
tPRDI => 1000000,
tREFI => 7800000,
tZQI => 128000000,
ADDR_WIDTH => 28,
ECC => "OFF",
ECC_TEST => "OFF",
TCQ => 100,
DATA_WIDTH => 64,
PAYLOAD_WIDTH => 64,
RST_ACT_LOW => 0,
IODELAY_GRP => "IODELAY_MIG",
INPUT_CLK_TYPE => "DIFFERENTIAL",
STARVE_LIMIT => 2
)
port map(
clk_ref_p => CLK_REF_P,
clk_ref_n => CLK_REF_N,
ddr3_dq => DDR3_DQ,
ddr3_dm => DDR3_DM,
ddr3_addr => DDR3_ADDR,
ddr3_ba => DDR3_BA,
ddr3_ras_n => DDR3_RAS_N,
ddr3_cas_n => DDR3_CAS_N,
ddr3_we_n => DDR3_WE_N,
ddr3_reset_n => DDR3_RESET_N,
ddr3_cs_n => DDR3_CS_N,
ddr3_odt => DDR3_ODT,
ddr3_cke => DDR3_CKE,
ddr3_dqs_p => DDR3_DQS_P,
ddr3_dqs_n => DDR3_DQS_N,
ddr3_ck_p => DDR3_CK_P,
ddr3_ck_n => DDR3_CK_N,
phy_init_done => PHY_INIT_DONE,
app_wdf_wren => app_wr_data_vld,
app_wdf_data => app_wr_data,
app_wdf_mask => (others => '0'),
app_wdf_end => app_wr_data_end,
app_addr => app_cmd_addr,
app_cmd => app_cmd,
app_en => app_cmd_en,
app_rdy => app_cmd_rdy,
app_wdf_rdy => app_wr_data_rdy,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_vld,
ui_clk_sync_rst => user_rst,
ui_clk => user_clk,
sys_rst => ASYNC_RST
);
end FULL;
|
mit
|
b12e84ba146562fab9af02a9aad75f8e
| 0.430921 | 3.96292 | false | false | false | false |
Project-Bonfire/Bonfire
|
Packages/router_pack.vhd
| 1 | 5,478 |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package router_pack is
COMPONENT FIFO_credit_based
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
cur_addr_y, cur_addr_x: in std_logic_vector(6 downto 0);
dst_addr_y, dst_addr_x: in std_logic_vector(6 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
component NI is
generic(current_x : integer := 10; -- the current node's x
current_y : integer := 10; -- the current node's y
NI_depth : integer := 32;
NI_couter_size: integer:= 5; -- should be set to log2 of NI_depth
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- NI's memory mapped reserved
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the flag register
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- packet counter register address!
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- interrupt signal: disabled!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC
);
end component; --entity NI
end; --package body
|
gpl-3.0
|
4f810afd369ca11f4dfb61d13178b57e
| 0.564074 | 3.369004 | false | false | false | false |
metaspace/ghdl_extra
|
lfsr4/test_lfsr4.vhdl
| 1 | 1,858 |
-- file : test_lfsr4.vhdl
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
entity test_lfsr4 is
end test_lfsr4;
architecture test of test_lfsr4 is
constant c : integer := 8;
signal result, clk, reset : std_ulogic;
begin
dut : entity work.lfsr4
generic map(size => c)
port map (
clk => clk,
reset => reset,
din => '0',
s => result);
process
procedure clock is
begin
clk <= '1'; wait for 1 ns;
clk <= '0'; wait for 1 ns;
end procedure;
variable i, j, n0, n1 : integer;
variable l: line;
variable s: string(3 downto 1);
begin
clk <= '0';
reset <= '1';
wait for 1 ns;
reset <= '0';
wait for 1 ns;
for j in 1 to 3 loop
n0 := 0;
n1 := 0;
for i in 2 to 2**c loop
clock;
if result = '1' then
n1 := n1 + 1;
else
n0 := n0 + 1;
end if;
s:=std_ulogic'image(result);
write(l,s(2));
end loop;
writeline(output,l);
write(l,"0:"&integer'image(n0)&", 1:"&integer'image(n1));
writeline(output,l);
end loop;
wait;
end process;
end test;
|
gpl-3.0
|
e67216678d4ab8fa8a2e6f5d18526ed5
| 0.608719 | 3.539048 | false | true | false | false |
Project-Bonfire/Bonfire
|
RTL/base_line/xbar.vhd
| 20 | 1,004 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end;
|
gpl-3.0
|
6049fec8f5299e94f448592f22b1d1d6
| 0.59761 | 3.127726 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/core.vhd
| 4 | 7,374 |
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity core is
Port ( clock : in STD_LOGIC;
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
exClock : in std_logic;
external : in std_logic;
data : IN std_logic_vector(23 downto 0);
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : IN std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
clock : IN std_logic;
reset : in std_logic;
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
END COMPONENT;
COMPONENT rle_enc
PORT(
clock : IN std_logic;
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady: std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
|
gpl-2.0
|
013391129eccc951cecc138802702cc7
| 0.638053 | 3.488174 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/l2p_arbiter.vhd
| 1 | 9,240 |
-------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
-------------------------------------------------------------------------------
--
-- unit name: GN4124 core arbiter (arbiter.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.1
--
-- description: Arbitrates PCIe accesses between Wishbone master,
-- L2P DMA master and P2L DMA master
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Add FF on data path and
-- change valid request logic
-- 26.02.2014 (theim) Changed priority order (swapped LDM <-> PDM)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--use work.gn4124_core_pkg.all;
--use work.common_pkg.all;
entity l2p_arbiter is
generic(
axis_data_width_c : integer := 64
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
wbm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
wbm_arb_tlast_i : in std_logic;
wbm_arb_tvalid_i : in std_logic;
wbm_arb_tready_o : out std_logic;
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
pdm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
pdm_arb_tlast_i : in std_logic;
pdm_arb_tvalid_i : in std_logic;
pdm_arb_tready_o : out std_logic;
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
ldm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
ldm_arb_tlast_i : in std_logic;
ldm_arb_tvalid_i : in std_logic;
ldm_arb_tready_o : out std_logic;
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
axis_tx_tkeep_o : out STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
axis_tx_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
axis_tx_tlast_o : out STD_LOGIC;
axis_tx_tvalid_o : out STD_LOGIC;
axis_tx_tready_i : in STD_LOGIC;
---------------------------------------------------------
-- Debug
eop_do : out std_logic
);
end l2p_arbiter;
architecture rtl of l2p_arbiter is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal wbm_arb_req_valid : std_logic;
signal pdm_arb_req_valid : std_logic;
signal ldm_arb_req_valid : std_logic;
signal arb_wbm_gnt : std_logic;
signal arb_pdm_gnt : std_logic;
signal arb_ldm_gnt : std_logic;
signal eop : std_logic; -- End of packet
signal axis_tx_tvalid_t : std_logic;
signal axis_tx_tlast_t : std_logic;
signal axis_tx_tdata_t : std_logic_vector(axis_data_width_c - 1 downto 0);
signal axis_tx_tkeep_t : std_logic_vector(axis_data_width_c/8 - 1 downto 0);
constant c_RST_ACTIVE : std_logic := '0';
begin
-- A request is valid only if the access not already granted to another source
wbm_arb_req_valid <= wbm_arb_req_i and (not(arb_pdm_gnt) and not(arb_ldm_gnt));
pdm_arb_req_valid <= pdm_arb_req_i and (not(arb_wbm_gnt) and not(arb_ldm_gnt));
ldm_arb_req_valid <= ldm_arb_req_i and (not(arb_wbm_gnt) and not(arb_pdm_gnt));
eop_do <= eop;
-- Detect end of packet to delimit the arbitration phase
-- eop <= ((arb_wbm_gnt and not(wbm_arb_dframe_i) and wbm_arb_valid_i) or
-- (arb_pdm_gnt and not(pdm_arb_dframe_i) and pdm_arb_valid_i) or
-- (arb_ldm_gnt and not(ldm_arb_dframe_i) and ldm_arb_valid_i));
process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
eop <= '0';
elsif rising_edge(clk_i) then
if ((arb_wbm_gnt = '1' and wbm_arb_tlast_i = '1') or
(arb_pdm_gnt = '1' and pdm_arb_tlast_i = '1') or
(arb_ldm_gnt = '1' and ldm_arb_tlast_i = '1')) then
eop <= '1';
else
eop <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Arbitration is started when a valid request is present and ends when the
-- EOP condition is detected
--
-- Strict priority arbitration scheme
-- Highest : WBM request
-- : LDM request
-- Lowest : PDM request
-----------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif rising_edge(clk_i) then
--if (arb_req_valid = '1') then
if (eop = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (wbm_arb_req_valid = '1') then
arb_wbm_gnt <= '1';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (ldm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '1';
elsif (pdm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '1';
arb_ldm_gnt <= '0';
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
elsif rising_edge(clk_i) then
if arb_wbm_gnt = '1' then
axis_tx_tvalid_t <= wbm_arb_tvalid_i;
axis_tx_tlast_t <= wbm_arb_tlast_i;
axis_tx_tdata_t <= wbm_arb_tdata_i;
axis_tx_tkeep_t <= wbm_arb_tkeep_i;
elsif arb_pdm_gnt = '1' then
axis_tx_tvalid_t <= pdm_arb_tvalid_i;
axis_tx_tlast_t <= pdm_arb_tlast_i;
axis_tx_tdata_t <= pdm_arb_tdata_i;
axis_tx_tkeep_t <= pdm_arb_tkeep_i;
elsif arb_ldm_gnt = '1' then
axis_tx_tvalid_t <= ldm_arb_tvalid_i;
axis_tx_tlast_t <= ldm_arb_tlast_i;
axis_tx_tdata_t <= ldm_arb_tdata_i;
axis_tx_tkeep_t <= ldm_arb_tkeep_i;
else
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
axis_tx_tvalid_o <= '0';
axis_tx_tlast_o <= '0';
axis_tx_tdata_o <= (others => '0');
axis_tx_tkeep_o <= (others => '0');
elsif rising_edge(clk_i) then
axis_tx_tvalid_o <= axis_tx_tvalid_t;
axis_tx_tlast_o <= axis_tx_tlast_t;
axis_tx_tdata_o <= axis_tx_tdata_t;
axis_tx_tkeep_o <= axis_tx_tkeep_t;
end if;
end process;
arb_wbm_gnt_o <= arb_wbm_gnt;
arb_pdm_gnt_o <= arb_pdm_gnt;
arb_ldm_gnt_o <= arb_ldm_gnt;
wbm_arb_tready_o <= axis_tx_tready_i and arb_wbm_gnt;
pdm_arb_tready_o <= axis_tx_tready_i and arb_pdm_gnt;
ldm_arb_tready_o <= axis_tx_tready_i and arb_ldm_gnt;
axis_tx_tuser_o <= "0000";
end rtl;
|
gpl-3.0
|
11a60715b816ecd1173dc10ddf4cf910
| 0.504329 | 3.390826 | false | false | false | false |
metaspace/ghdl_extra
|
7segments/segment.vhdl
| 1 | 5,523 |
-- fichier : segment.vhdl
-- créé : lun. juin 21 14:58:36 CEST 2010
-- version ven. sept. 17 04:24:05 CEST 2010
-- version sam. sept. 18 08:36:49 CEST 2010
-- version mar. sept. 28 15:41:27 CEST 2010
-- segment.vhdl : package and architecture for 7-segment display
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fb_ghdl.all;
package segment is
type sulv2int_array is array (std_ulogic) of integer;
constant sul2int : sulv2int_array := (
'U' => 16#ff9400#, -- orange
'0' => 16#003000#, -- vert foncé
'1' => 16#4fff4f#, -- vert clair
others => 16#8b8b8b# -- gris foncé
);
constant oblique_haut : integer := -1;
constant oblique_bas : integer := 1;
procedure segment_point (x,y, h: integer; v: std_ulogic);
procedure segment_horizontal(x,y,w,h: integer; v: std_ulogic);
procedure segment_vertical (x,y,w,h: integer; v: std_ulogic);
procedure segment_oblique (x,y,w,h,dir: integer; v: std_ulogic);
end segment;
package body segment is
procedure segment_point(x,y,h: integer; v: std_ulogic) is
variable i,j, c: integer;
begin
c := sul2int(v);
-- carré :
for j in y to y+h loop
for i in x to x+h loop
pixel(j,i) := c;
end loop;
end loop;
end segment_point;
procedure segment_horizontal(x,y,w,h: integer; v: std_ulogic) is
variable i,j,t, c: integer;
begin
c := sul2int(v);
-- la ligne centrale, affichée une seule fois
for i in x to x+h loop
pixel(y,i) := c;
end loop;
for j in 1 to w loop
-- boucle sur la ligne du dessus
t := y-j;
for i in (x+j) to (x+h-j) loop
pixel(t,i) := c;
end loop;
-- boucle sur la ligne du dessous
t := y+j;
for i in (x+j) to (x+h-j) loop
pixel(t,i) := c;
end loop;
end loop;
end segment_horizontal;
procedure segment_vertical(x,y,w,h: integer; v: std_ulogic) is
variable i,j, c: integer;
begin
c := sul2int(v);
for j in 0 to w loop
-- triangle supérieur
for i in (x-j) to (x+j) loop
pixel(y+j,i) := c;
end loop;
-- triangle inférieur
for i in (x-j) to (x+j) loop
pixel(y+h-j,i) := c;
end loop;
end loop;
-- rectangle
for j in y+w to y+h-w loop
for i in x-w to x+w loop
pixel(j,i) := c;
end loop;
end loop;
end segment_vertical;
procedure segment_oblique(x,y,w,h,dir: integer; v: std_ulogic) is
variable i, j, a, b, c, y2: integer;
begin
a := 0;
b := w;
c := sul2int(v);
y2:=y;
for j in 0 to h loop
-- affiche une ligne horizontale
for i in a+x to b+x loop
pixel(y2,i) := c;
end loop;
-- passe à la ligne du dessous
y2 := y2+dir;
-- avance le début :
if j>w then a := a+1; end if;
-- avance la fin :
if b<h then b := b+1; end if;
end loop;
end segment_oblique;
end segment;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.segment.all;
use work.fb_ghdl.all;
entity seg7 is
generic(
x : integer; -- \ coordinates of left-top corner - minus girth
y : integer; -- /
s : integer := 70; -- length of the segments
g : integer := 7; -- girth/width of the segments
l : integer := 3 -- spacing between segments
);
port(seg : in std_ulogic_vector(6 downto 0));
begin
process is
begin
-- 1 < g < s
assert 1 < g report "segment trop fin" severity failure;
assert g < s report "segment trop épais" severity failure;
-- 0 < l < s
assert 0 < l report "espacement trop faible" severity failure;
assert l < s report "espacement trop grand" severity failure;
-- 3 < s < fby
assert 3 < s report "segment trop long" severity failure;
assert s < fby report "segment trop court" severity failure;
-- l < x < fbx1-(s+l)
assert l < x report "abscisse trop à gauche" severity failure;
assert x < fbx1-(s+l) report "abscisse trop à droite" severity failure;
-- l < y < fby1-(s+l+l+s+l)
assert l < y report "ordonnée trop haute" severity failure;
assert y < fby1-(s+l+l+s+l) report "ordonnée trop basse" severity failure;
wait;
end process;
end seg7;
architecture observe of seg7 is
begin
segment_horizontal(x+l ,y ,g,s, seg(0));
segment_vertical (x+l+s+l,y+l ,g,s, seg(1));
segment_vertical (x+l+s+l,y+l+s+l+l ,g,s, seg(2));
segment_horizontal(x+l ,y+l+s+l+l+s+l,g,s, seg(3));
segment_vertical (x ,y+l+s+l+l ,g,s, seg(4));
segment_vertical (x ,y+l ,g,s, seg(5));
segment_horizontal(x+l ,y+l+s+l ,g,s, seg(6));
end observe;
|
gpl-3.0
|
46f8c2f357d6186568eb1c1ae1d352ac
| 0.590595 | 3.063404 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_Equalizer.vhd
| 1 | 10,143 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- This file describes the implementation of a generic equalizer. This --
-- equaliser is made up out of N second order, direct IIR-filters with --
-- multipliers between. --
-- --
-- --
-- Generic: --
-- NO_SECTIONS - The number of second order sections that the equalizer --
-- - should be made up out of --
-- --
-- INPUT_WIDTH - The width of the input data --
-- INPUT_FRACT - The fractional width of the input data --
-- OUTPUT_WIDTH - The width of the output data --
-- OUTPUT_FRACT - The fractional width of the output data --
-- --
-- SCALE_WIDTH - The width of the scaling coefficients --
-- SCALE_FRACT - An array of the fractional widths of the scaling --
-- coefficients, starting with the first multiplier --
-- --
-- INTERNAL_WIDTH - The width of all internal registers --
-- INTERNAL_FRACT - The fractional width of all internal registers --
-- --
-- COEFF_WIDTH_B - The width of all B-coefficients in the IIR-filters --
-- COEFF_FRACT_B - An array of the fractional widths of all the --
-- B-coefficeints, starting with the first filter --
-- COEFF_WIDTH_A - The width of all A-coefficients in the IIR-filters --
-- COEFF_FRACT_A - An array of the fractional widths of all the --
-- A-coefficeints, starting with the first filter --
-- --
-- Input/Output: --
-- clk - System clock --
-- reset - Resets component when high --
-- x - Input --
-- --
-- scale - An array of all the scaling factors, put the scaling --
-- value for the first multiplier first --
-- --
-- b0 - An array of all the B0-coefficients, put the --
-- coefficient for the first filter first --
-- b1 - An array of all the B1-coefficients, put the --
-- coefficient for the first filter first --
-- b2 - An array of all the B2-coefficients, put the --
-- coefficient for the first filter first --
-- a1 - An array of all the A1-coefficients, put the --
-- coefficient for the first filter first --
-- a2 - An array of all the A2-coefficients, put the --
-- coefficient for the first filter first --
-- --
-- y - Output --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.filter_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_Equalizer is
generic (NO_SECTIONS : natural := 9;
INPUT_WIDTH : natural := 8;
INPUT_FRACT : natural := 6;
OUTPUT_WIDTH : natural := 8;
OUTPUT_FRACT : natural := 6;
SCALE_WIDTH : natural := 8;
SCALE_FRACT : natural_array := (6,6,6,6,6,6,6,6,6,6);
INTERNAL_WIDTH : natural := 14;
INTERNAL_FRACT : natural := 8;
COEFF_WIDTH_B : natural := 8;
COEFF_FRACT_B : natural_array := (6,6,6,6,6,6,6,6,6);
COEFF_WIDTH_A : natural := 8;
COEFF_FRACT_A : natural_array := (6,6,6,6,6,6,6,6,6));
port(clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(INPUT_WIDTH-1 downto 0);
scale : in std_logic_vector(SCALE_WIDTH*(NO_SECTIONS+1)-1 downto 0);
b0 : in std_logic_vector(COEFF_WIDTH_B*(NO_SECTIONS)-1 downto 0);
b1 : in std_logic_vector(COEFF_WIDTH_B*(NO_SECTIONS)-1 downto 0);
b2 : in std_logic_vector(COEFF_WIDTH_B*(NO_SECTIONS)-1 downto 0);
a1 : in std_logic_vector(COEFF_WIDTH_A*(NO_SECTIONS)-1 downto 0);
a2 : in std_logic_vector(COEFF_WIDTH_A*(NO_SECTIONS)-1 downto 0);
y : out std_logic_vector(OUTPUT_WIDTH-1 downto 0));
end Generic_Equalizer;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_Equalizer is
-- Type Declarations -----------------------------------------------------------
type scale_array is array(0 to NO_SECTIONS) of std_logic_vector(SCALE_WIDTH-1 downto 0);
type b_array is array(0 to NO_SECTIONS-1) of std_logic_vector(COEFF_WIDTH_B*3-1 downto 0);
type a_array is array(0 to NO_SECTIONS-1) of std_logic_vector(COEFF_WIDTH_A*2-1 downto 0);
type internal_array is array(0 to NO_SECTIONS-1) of std_logic_vector(INTERNAL_WIDTH-1 downto 0);
-- Signals ---------------------------------------------------------------------
signal s_scale : scale_array;
signal s_b : b_array;
signal s_a : a_array;
signal s_iir_input : internal_array;
signal s_iir_output : internal_array;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Set coefficients
gen_scale:
for i in 0 to NO_SECTIONS generate
s_scale(i) <= scale(SCALE_WIDTH*((NO_SECTIONS+1)-i)-1 downto SCALE_WIDTH*((NO_SECTIONS+1)-i-1));
end generate;
gen_coefficients:
for i in 0 to NO_SECTIONS-1 generate
s_b(i) <= b0(COEFF_WIDTH_B*(NO_SECTIONS-i)-1 downto COEFF_WIDTH_B*(NO_SECTIONS-i-1)) &
b1(COEFF_WIDTH_B*(NO_SECTIONS-i)-1 downto COEFF_WIDTH_B*(NO_SECTIONS-i-1)) &
b2(COEFF_WIDTH_B*(NO_SECTIONS-i)-1 downto COEFF_WIDTH_B*(NO_SECTIONS-i-1));
s_a(i) <= a1(COEFF_WIDTH_A*(NO_SECTIONS-i)-1 downto COEFF_WIDTH_A*(NO_SECTIONS-i-1)) &
a2(COEFF_WIDTH_A*(NO_SECTIONS-i)-1 downto COEFF_WIDTH_A*(NO_SECTIONS-i-1));
end generate;
-- First multiplier ----------------------------------------------------------
Multiplier_in : entity work.Multiplier_Saturate
generic map(X_WIDTH => INPUT_WIDTH,
X_FRACTION => INPUT_FRACT,
Y_WIDTH => SCALE_WIDTH,
Y_FRACTION => SCALE_FRACT(0),
S_WIDTH => INTERNAL_WIDTH,
S_FRACTION => INTERNAL_FRACT)
port map(x => x,
y => s_scale(0),
s => s_iir_input(0));
-- Filters -------------------------------------------------------------------
gen_filters:
for i in 0 to NO_SECTIONS-1 generate
Generic_IIR : entity work.Generic_IIR
generic map(ORDER => 2,
IN_WIDTH => INTERNAL_WIDTH,
IN_FRACT => INTERNAL_FRACT,
B_WIDTH => COEFF_WIDTH_B,
B_FRACT => COEFF_FRACT_B(i),
A_WIDTH => COEFF_WIDTH_A,
A_FRACT => COEFF_FRACT_A(i),
INTERNAL_WIDTH => INTERNAL_WIDTH,
INTERNAL_FRACT => INTERNAL_FRACT,
OUT_WIDTH => INTERNAL_WIDTH,
OUT_FRACT => INTERNAL_FRACT)
port map(clk => clk,
reset => reset,
x => s_iir_input(i),
B => s_b(i),
A => s_a(i),
y => s_iir_output(i));
end generate;
-- Multipliers ---------------------------------------------------------------
gen_multipliers:
for i in 1 to NO_SECTIONS-1 generate
Multiplier : entity work.Multiplier_Saturate
generic map(X_WIDTH => INTERNAL_WIDTH,
X_FRACTION => INTERNAL_FRACT,
Y_WIDTH => SCALE_WIDTH,
Y_FRACTION => SCALE_FRACT(i),
S_WIDTH => INTERNAL_WIDTH,
S_FRACTION => INTERNAL_FRACT)
port map(x => s_iir_output(i-1),
y => s_scale(i),
s => s_iir_input(i));
end generate;
-- Last multiplier -----------------------------------------------------------
Multiplier_out : entity work.Multiplier_Saturate
generic map(X_WIDTH => INTERNAL_WIDTH,
X_FRACTION => INTERNAL_FRACT,
Y_WIDTH => SCALE_WIDTH,
Y_FRACTION => SCALE_FRACT(NO_SECTIONS),
S_WIDTH => OUTPUT_WIDTH,
S_FRACTION => OUTPUT_FRACT)
port map(x => s_iir_output(NO_SECTIONS-1),
y => s_scale(NO_SECTIONS),
s => y);
end architecture;
|
mit
|
ae3fd39cfff9b17019e3d936b58437ae
| 0.410628 | 4.674194 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/tx-core/trigger_unit.vhd
| 1 | 7,340 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Trigger Logic
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trigger_unit is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Serial Trigger Out
trig_o : out std_logic;
trig_pulse_o : out std_logic;
-- Trigger In (async)
ext_trig_i : in std_logic;
-- Config
trig_word_i : in std_logic_vector(127 downto 0); -- Trigger command
trig_word_length_i : in std_logic_vector(31 downto 0);
trig_freq_i : in std_logic_vector(31 downto 0); -- Number of clock cycles between triggers
trig_time_i : in std_logic_vector(63 downto 0); -- Clock cycles
trig_count_i : in std_logic_vector(31 downto 0); -- Fixed number of triggers
trig_conf_i : in std_logic_vector(3 downto 0); -- Internal, external, pseudo random,
trig_en_i : in std_logic;
trig_abort_i : in std_logic;
trig_done_o : out std_logic
);
end trigger_unit;
architecture Behavioral of trigger_unit is
-- Signals
signal bit_count : unsigned(7 downto 0);
signal sreg : std_logic_vector(127 downto 0);
signal trig_pulse : std_logic;
-- Registers
signal trig_word : std_logic_vector(127 downto 0);
signal trig_word_length : std_logic_vector(31 downto 0);
signal trig_freq : std_logic_vector(31 downto 0);
signal trig_time : std_logic_vector(63 downto 0);
signal trig_count : std_logic_vector(31 downto 0);
signal trig_conf : stD_logic_vector(3 downto 0);
signal trig_en : std_logic;
constant c_DONE_DELAY : integer := 32;
signal trig_done : std_logic_vector(c_DONE_DELAY-1 downto 0);
-- Counters
signal stopwatch_cnt : unsigned(63 downto 0);
signal int_trig_cnt : unsigned(31 downto 0);
signal freq_cnt : unsigned(31 downto 0);
-- Sync
signal trig_en_d0 : std_logic;
signal trig_en_d1 : std_logic;
signal trig_en_pos : std_logic;
signal trig_en_neg : std_logic;
signal ext_trig_d0 : std_logic;
signal ext_trig_d1 : std_logic;
signal ext_trig_d2 : std_logic;
signal ext_trig_d3 : std_logic;
signal ext_trig_d4 : std_logic;
signal ext_trig_pos : std_logic;
constant c_DEADTIME : integer := 10; -- Deadtime moved to trigger logic
signal deadtime : unsigned(7 downto 0);
begin
-- Done conditions
done_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_done(0) <= '0';
elsif rising_edge(clk_i) then
if (trig_en = '0') then -- Reset done on disable
trig_done(0) <= '0';
elsif (trig_abort_i = '1') then -- Abort triggering
trig_done(0) <= '1';
elsif (trig_conf = x"0") then -- External, abot will set done
--trig_done(0) <= '0';
elsif (trig_conf = x"1") then -- Internal time
if (stopwatch_cnt = unsigned(trig_time)) then
trig_done(0) <= '1';
end if;
elsif (trig_conf = x"2") then -- Internal count
if (int_trig_cnt = unsigned(trig_count)) then
trig_done(0) <= '1';
end if;
--elsif (trig_conf = x"3") then -- Pseudo Random
else -- unknown conf
trig_done(0) <= '1';
end if;
end if;
end process done_proc;
-- Stopwatch
stopwatch_proc : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
stopwatch_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (trig_done(0) = '1') then
stopwatch_cnt <= (others => '0');
elsif (trig_en = '1') then
stopwatch_cnt <= stopwatch_cnt + 1;
end if;
end if;
end process stopwatch_proc;
-- Trigger count
int_trig_cnt_proc : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
int_trig_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (trig_done(0) = '1') then
int_trig_cnt <= (others => '0');
elsif (trig_en = '1' and trig_pulse = '1') then
int_trig_cnt <= int_trig_cnt + 1;
end if;
end if;
end process int_trig_cnt_proc;
-- Trigger Pulser
trig_pulse_o <= trig_pulse;
trig_pulse_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_pulse <= '0';
freq_cnt <= (others => '0');
elsif rising_edge(clk_i) then
if (trig_conf = x"0") then -- Pusling on External rising edge
if (trig_en = '1' and ext_trig_pos = '1' and trig_done(0) = '0') then
trig_pulse <= '1';
else
trig_pulse <= '0';
end if;
else -- Pulsing on requency counter
if (trig_done(0) = '1') then
trig_pulse <= '0';
freq_cnt <= (others => '0');
elsif (trig_en = '1') then
if (freq_cnt = unsigned(trig_freq)) then
freq_cnt <= (others => '0');
trig_pulse <= '1';
else
freq_cnt <= freq_cnt + 1;
trig_pulse <= '0';
end if;
end if;
end if;
end if;
end process trig_pulse_proc;
-- Tie offs
trig_o <= sreg(127);
-- Serializer proc
serialize: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sreg <= (others => '0');
bit_count <= (others => '0');
elsif rising_edge(clk_i) then
if (trig_pulse = '1') then
sreg <= trig_word;
bit_count <= (others => '0');
-- elsif (bit_count <= unsigned(trig_word_length(7 downto 0))) then
else
sreg <= sreg(126 downto 0) & '0';
-- bit_count <= bit_count + 1;
-- else
-- sreg <= (others => '0');
end if;
end if;
end process serialize;
-- Sync proc
sync_proc : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_word <= (others => '0');
trig_word_length <= (others => '0');
trig_freq <= (others => '0');
trig_time <= (others => '0');
trig_count <= (others => '0');
trig_conf <= (others => '0');
trig_en <= '0';
trig_done_o <= '0';
trig_done(c_DONE_DELAY-1 downto 1) <= (others => '0');
ext_trig_d0 <= '0';
ext_trig_d1 <= '0';
ext_trig_d2 <= '0';
ext_trig_d3 <= '0';
ext_trig_d4 <= '0';
ext_trig_pos <= '0';
trig_en_d0 <= '0';
trig_en_d1 <= '0';
trig_en_pos <= '0';
trig_en_neg <= '0';
deadtime <= (others => '0');
elsif rising_edge(clk_i) then
ext_trig_d0 <= ext_trig_i; -- async input
ext_trig_d1 <= ext_trig_d0;
ext_trig_d2 <= ext_trig_d1;
ext_trig_d3 <= ext_trig_d2;
ext_trig_d4 <= ext_trig_d3;
-- Triggered on pos edge of external signal and high longer than 25ns
if (ext_trig_d4 = '0' and ext_trig_d3 = '1' and deadtime = 0) then
ext_trig_pos <= '1';
deadtime <= to_unsigned(c_DEADTIME, 8);
else
ext_trig_pos <= '0';
end if;
trig_en_d0 <= trig_en_i;
trig_en_d1 <= trig_en_d0;
if (trig_en_d1 = '0' and trig_en_d0 = '1') then
trig_en_pos <= '1';
trig_en_neg <= '0';
elsif (trig_en_d1 = '1' and trig_en_d0 = '0') then
trig_en_pos <= '0';
trig_en_neg <= '1';
else
trig_en_neg <= '0';
trig_en_pos <= '0';
end if;
if (trig_en_pos = '1') then
trig_word <= trig_word_i;
trig_word_length <= trig_word_length_i;
trig_freq <= trig_freq_i;
trig_time <= trig_time_i;
trig_count <= trig_count_i;
trig_conf <= trig_conf_i;
trig_en <= '1';
elsif (trig_en_neg = '1') then
trig_en <= '0';
end if;
for I in 1 to c_DONE_DELAY-1 loop
trig_done(I) <= trig_done(I-1);
end loop;
trig_done_o <= trig_done(c_DONE_DELAY-1);
if (deadtime > 0) then
deadtime <= deadtime - 1;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
8463449a773052225f35ef94018d454f
| 0.577112 | 2.685693 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Top Level/AudioIO_tl.vhd
| 1 | 905 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AudioIO_tl is
port (
sampleButton : in std_logic;
vauxn : in std_logic;
vauxp : in std_logic;
leds : out std_logic_vector(15 downto 0);
clk : in std_logic;
reset : in std_logic
) ;
end entity ; -- AudioIO_tl
architecture arch of AudioIO_tl is
signal registerOutput : std_logic_vector(15 downto 0);
signal sampleOutput : std_logic_vector(15 downto 0);
begin
leds(14 downto 0) <= sampleOutput(14 downto 0);
leds(15) <= sampleButton;
sampler : entity work.ADSampler
port map (
vauxn => vauxn,
vauxp => vauxp,
output => sampleOutput,
clk => clk,
reset => reset
);
-- reg : entity work.Delay
-- generic map (
-- wordLength => 12
-- )
-- port map (
-- input => sampleOutput,
-- output => registerOutput,
--
-- clk => sampleButton,
-- reset => reset
-- );
end architecture ; -- arch
|
mit
|
c586f75c283b9c5a377455cf8adc7c05
| 0.648619 | 2.967213 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Equalizer_No_Change_Test.vhd
| 1 | 3,136 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Equalizer_No_Change_Test is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Equalizer_No_Change_Test;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Equalizer_No_Change_Test is
begin
Equalizer : entity work.Equalizer
generic map(DATA_WIDTH => 16,
DATA_FRACT => 15,
SCALE_WIDTH_1 => 16,
SCALE_FRACT_1 => 14,
SCALE_WIDTH_2 => 16,
SCALE_FRACT_2 => 14,
SCALE_WIDTH_3 => 16,
SCALE_FRACT_3 => 14,
SCALE_WIDTH_4 => 16,
SCALE_FRACT_4 => 14,
INTERNAL_IIR_WIDTH_1 => 24,
INTERNAL_IIR_FRACT_1 => 20,
INTERNAL_IIR_WIDTH_2 => 24,
INTERNAL_IIR_FRACT_2 => 20,
INTERNAL_IIR_WIDTH_3 => 24,
INTERNAL_IIR_FRACT_3 => 20,
COEFF_WIDTH_1 => 16,
COEFF_FRACT_1 => 14,
COEFF_WIDTH_2 => 16,
COEFF_FRACT_2 => 14,
COEFF_WIDTH_3 => 16,
COEFF_FRACT_3 => 14)
port map(clk => clk,
reset => reset,
x => input,
scale_1 => "0100000000000000",
scale_2 => "0100000000000000",
scale_3 => "0100000000000000",
scale_4 => "0100000000000000",
b0_1 => "0100000000000000",
b1_1 => "0000000000000000",
b2_1 => "0000000000000000",
a1_1 => "0000000000000000",
a2_1 => "0000000000000000",
b0_2 => "0100000000000000",
b1_2 => "0000000000000000",
b2_2 => "0000000000000000",
a1_2 => "0000000000000000",
a2_2 => "0000000000000000",
b0_3 => "0100000000000000",
b1_3 => "0000000000000000",
b2_3 => "0000000000000000",
a1_3 => "0000000000000000",
a2_3 => "0000000000000000",
y => output);
end architecture;
|
mit
|
96e2643bd6fc4938987f9bbca02212fe
| 0.33227 | 5.388316 | false | false | false | false |
techwoes/sump
|
logic-analyzer-orig/fpga/la-S3ESK.vhd
| 1 | 5,013 |
----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependend IO modules and defines all inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity la is
Port(
resetSwitch : in std_logic;
xtalClock : in std_logic;
exClock : in std_logic;
input : in std_logic_vector(31 downto 0);
rx : in std_logic;
tx : inout std_logic;
led : OUT std_logic_vector(7 downto 0);
switch : in std_logic_vector(1 downto 0)
);
end la;
architecture Behavioral of la is
COMPONENT clockman
PORT(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
COMPONENT core
PORT(
clock : IN std_logic;
extReset : IN std_logic;
cmd : IN std_logic_vector(39 downto 0);
execute : IN std_logic;
input : IN std_logic_vector(31 downto 0);
inputClock : IN std_logic;
sampleReady50 : OUT std_logic;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : IN std_logic_vector(31 downto 0);
memoryOut : OUT std_logic_vector(31 downto 0);
memoryRead : OUT std_logic;
memoryWrite : OUT std_logic
);
END COMPONENT;
COMPONENT sram_bram
PORT(
clock : IN std_logic;
input : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0);
read : IN std_logic;
write : IN std_logic
);
END COMPONENT;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (31 downto 0);
signal probeInput : std_logic_vector (31 downto 0);
signal output : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal test_counter : std_logic_vector (40 downto 0);
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 28; -- 100M / 28 / 115200 = 31 (5bit)
constant RATE : integer := 115200; -- maximum & base rate
begin
led(7 downto 0) <= exClock & resetSwitch & "0" & switch & "0" & rx & tx; --& "000";
-- test counter
process(clock)
begin
if rising_edge(clock) then
test_counter <= test_counter + 1;
end if;
end process;
probeInput <= input;
-- probeInput <= test_counter(40 downto 9); -- use this to connect a counter to the inputs
Inst_clockman: clockman PORT MAP(
clkin => xtalClock,
clk0 => clock
);
Inst_eia232: eia232
generic map (
FREQ => FREQ,
SCALE => TRXSCALE,
RATE => RATE
)
PORT MAP(
clock => clock,
reset => resetSwitch,
speed => switch,
rx => rx,
tx => tx,
cmd => cmd,
execute => execute,
data => output,
send => send,
busy => busy
);
Inst_core: core PORT MAP(
clock => clock,
extReset => resetSwitch,
cmd => cmd,
execute => execute,
input => probeInput,
inputClock => exClock,
--sampleReady50 => ready50,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write
);
Inst_sram: sram_bram PORT MAP(
clock => clock,
input => memoryOut,
output => memoryIn,
read => read,
write => write
);
end Behavioral;
|
gpl-2.0
|
6605357d89fb4b503e112cf812e8c89b
| 0.638939 | 3.483669 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
ethernet_control.vhd
| 1 | 1,427 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ethernet_control is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
cnt_23 : in STD_LOGIC;
cnt_22 : in STD_LOGIC;
PhyRstn : out STD_LOGIC);
end ethernet_control;
architecture Behavioral of ethernet_control is
begin
-- PHY requires reset to be asserted for 100 uS
phy_reset: process (clk)
variable done : STD_LOGIC := '0';
begin
if RISING_EDGE(clk) then
if done = '0' then
PhyRstn <= not cnt_22;
end if;
done := done or cnt_23;
if rst = '1' then
done := '0';
PhyRstn <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
5f7149d1af88cd6e5f778e5dd8a0dfa8
| 0.68185 | 3.480488 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/pps_ei.vhd
| 1 | 4,736 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Instruction extraction stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity pps_ei is
port (
clock : in std_logic;
reset : in std_logic;
clear : in std_logic; -- Clear the pipeline stage
stop_all : in std_logic; -- Evolution locking signal
-- Asynchronous inputs
stop_ei : in std_logic; -- Lock the EI_adr and Ei_instr registers
-- Bus controler interface
CTE_instr : in bus32; -- Instruction from the memory
ETC_adr : out bus32; -- Address to read in memory
-- Synchronous inputs from PF stage
PF_pc : in bus32; -- Current value of the pc
-- Synchronous outputs to DI stage
EI_instr : out bus32; -- Read interface
EI_adr : out bus32; -- Address from the read instruction
EI_it_ok : out std_logic -- Allow hardware interruptions
);
end pps_ei;
architecture rtl of pps_ei is
begin
ETC_adr <= PF_pc; -- Connexion of the PC to the memory address bus
-- Set the results
process (clock)
begin
if (clock='1' and clock'event) then
if reset='1' then
EI_instr <= INS_NOP;
EI_adr <= (others => '0');
EI_it_ok <= '0';
elsif stop_all='0' then
if clear='1' then
-- Clear the stage
EI_instr <= INS_NOP;
EI_it_ok <= '0';
elsif stop_ei='0' then
-- Normal evolution
EI_adr <= PF_pc;
EI_instr <= CTE_instr;
EI_it_ok <= '1';
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
d6e7fe39d98d757418e71bdacc551f9a
| 0.372255 | 5.692308 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Decimator/Mult.vhd
| 1 | 755 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity Mult is
generic (
wordLengthA : natural := 8;
wordLengthB : natural := 8;
wordLengthP : natural := 16
);
port (
a : in std_logic_vector(wordLengthA-1 downto 0);
b : in std_logic_vector(wordLengthB-1 downto 0);
p : out std_logic_vector(wordLengthP-1 downto 0)
);
end entity ; -- Mult
architecture arch of Mult is
signal product : signed(wordLengthA+wordLengthB-1 downto 0);
signal pEntire : std_logic_vector(wordLengthA+wordLengthB-1 downto 0);
begin
product <= (signed(a)*signed(b));
pEntire <= std_logic_vector(shift_left(product, 1));
p <= pEntire(wordLengthA+wordLengthB-1 downto wordLengthA+wordLengthB-wordLengthP);
end architecture ; -- arch
|
mit
|
5248940f7fdcc80b402b3207aebbae4a
| 0.713907 | 3.226496 | false | false | false | false |
makestuff/umdkv2
|
templates/fx2min/vhdl/top_level.vhdl
| 1 | 6,803 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity top_level is
generic (
RESET_INIT : std_logic := '0';
MAPRAM_INIT : std_logic := '0';
MAPRAM_FORCE : boolean := false;
NO_MONITOR : boolean := false
);
port (
-- FX2 interface -----------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2
fx2FifoSel_out : out std_logic; -- select FIFO: "0" for EP2OUT, "1" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2 has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2 has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- SDRAM signals -----------------------------------------------------------------------------
ramClk_out : out std_logic;
ramCmd_out : out std_logic_vector(2 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic;
-- MegaDrive interface -----------------------------------------------------------------------
mdReset_out : out std_logic;
mdDriveBus_out : out std_logic;
mdDTACK_out : out std_logic;
mdAddr_in : in std_logic_vector(22 downto 0);
mdData_io : inout std_logic_vector(15 downto 0);
mdOE_in : in std_logic;
mdAS_in : in std_logic;
mdLDSW_in : in std_logic;
mdUDSW_in : in std_logic;
-- SPI bus ---------------------------------------------------------------------------------
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic;
spiCS_out : out std_logic_vector(1 downto 0)
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Clock synthesis & reset
signal sysClk000 : std_logic;
signal sysClk180 : std_logic;
signal locked : std_logic;
signal reset : std_logic;
begin
-- CommFPGA module
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map (
clk_in => sysClk000,
reset_in => reset,
reset_out => open,
-- FX2 interface
fx2FifoSel_out => fx2FifoSel_out,
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- SDRAM application
umdkv2_app : entity work.umdkv2
generic map (
RESET_INIT => RESET_INIT,
MAPRAM_INIT => MAPRAM_INIT,
MAPRAM_FORCE => MAPRAM_FORCE,
NO_MONITOR => NO_MONITOR
)
port map (
clk_in => sysClk000,
reset_in => reset,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- SDRAM interface
ramCmd_out => ramCmd_out,
ramBank_out => ramBank_out,
ramAddr_out => ramAddr_out,
ramData_io => ramData_io,
ramLDQM_out => ramLDQM_out,
ramUDQM_out => ramUDQM_out,
-- MegaDrive interface
mdReset_out => mdReset_out,
mdDriveBus_out => mdDriveBus_out,
mdDTACK_out => mdDTACK_out,
mdAddr_in => mdAddr_in,
mdData_io => mdData_io,
mdOE_in => mdOE_in,
mdAS_in => mdAS_in,
mdLDSW_in => mdLDSW_in,
mdUDSW_in => mdUDSW_in,
-- SPI bus
spiClk_out => spiClk_out,
spiData_out => spiData_out,
spiData_in => spiData_in,
spiCS_out => spiCS_out
);
-- Generate the system clock from the FX2LP's 48MHz clock
clk_gen: entity work.clk_gen
port map (
clk_in => fx2Clk_in,
clk000_out => sysClk000,
clk180_out => sysClk180,
locked_out => locked
);
-- Drive system clock and sync reset
clk_drv: ODDR2
port map (
D0 => '1',
D1 => '0',
C0 => sysClk000,
C1 => sysClk180,
Q => ramClk_out
);
reset <= not(locked);
end architecture;
|
gpl-3.0
|
019f28a51ff2bdf126b7345782179b67
| 0.570778 | 3.354536 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/decode_8b10b/decode_8b10b_rtl.vhd
| 1 | 22,767 |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_rtl.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Top-level, synthesizable 8b/10b decoder core file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
LIBRARY decode_8b10b;
USE decode_8b10b.decode_8b10b_pkg.ALL;
-----------------------------------------------------------------------------
-- Entity Declaration
-----------------------------------------------------------------------------
ENTITY decode_8b10b_rtl IS
GENERIC (
C_DECODE_TYPE : INTEGER := 0;
C_ELABORATION_DIR : STRING := "./../../src/";
C_HAS_BPORTS : INTEGER := 0;
C_HAS_CE : INTEGER := 0;
C_HAS_CE_B : INTEGER := 0;
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_CODE_ERR_B : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_ERR_B : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_IN_B : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_ND_B : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_RUN_DISP_B : INTEGER := 0;
C_HAS_SINIT : INTEGER := 0;
C_HAS_SINIT_B : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_SYM_DISP_B : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_DOUT_B : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_KOUT_B : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0;
C_SINIT_RUN_DISP_B : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_rtl;
--------------------------------------------------------------------------------
-- Generic Definitions:
--------------------------------------------------------------------------------
-- C_DECODE_TYPE : Implementation: 0=Slice based, 1=BlockRam
-- C_ELABORATION_DIR : Directory path for mif file
-- C_HAS_BPORTS : 1 indicates second decoder should be generated
-- C_HAS_CE : 1 indicates ce port is present
-- C_HAS_CE_B : 1 indicates ce_b port is present (if c_has_bports=1)
-- C_HAS_CODE_ERR : 1 indicates code_err port is present
-- C_HAS_CODE_ERR_B : 1 indicates code_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_ERR : 1 indicates disp_err port is present
-- C_HAS_DISP_ERR_B : 1 indicates disp_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_IN : 1 indicates disp_in port is present
-- C_HAS_DISP_IN_B : 1 indicates disp_in_b port is present
-- (if c_has_bports=1)
-- C_HAS_ND : 1 indicates nd port is present
-- C_HAS_ND_B : 1 indicates nd_b port is present (if c_has_bports=1)
-- C_HAS_RUN_DISP : 1 indicates run_disp port is present
-- C_HAS_RUN_DISP_B : 1 indicates run_disp_b port is present
-- (if c_has_bports=1)
-- C_HAS_SINIT : 1 indicates sinit port is present
-- C_HAS_SINIT_B : 1 indicates sinit_b port is present
-- (if c_has_bports=1)
-- C_HAS_SYM_DISP : 1 indicates sym_disp port is present
-- C_HAS_SYM_DISP_B : 1 indicates sym_disp_b port is present
-- (if c_has_bports=1)
-- C_SINIT_DOUT : 8-bit binary string, dout value when sinit is active
-- C_SINIT_DOUT_B : 8-bit binary string, dout_b value when sinit_b is
-- active
-- C_SINIT_KOUT : controls kout output when sinit is active
-- C_SINIT_KOUT_B : controls kout_b output when sinit_b is active
-- C_SINIT_RUN_DISP : Initializes run_disp (and disp_in) value to
-- positive(1) or negative(0)
-- C_SINIT_RUN_DISP_B : Initializes run_disp_b (and disp_in_b) value to
-- positive(1) or negative(0)
--------------------------------------------------------------------------------
-- Port Definitions:
--------------------------------------------------------------------------------
-- Mandatory Pins
-- CLK : Clock Input
-- DIN : Encoded Symbol Input
-- DOUT : Data Output, decoded data byte
-- KOUT : Command Output
-------------------------------------------------------------------------
-- Optional Pins
-- CE : Clock Enable
-- CE_B : Clock Enable (B port)
-- CLK_B : Clock Input (B port)
-- DIN_B : Encoded Symbol Input (B port)
-- DISP_IN : Disparity Input (running disparity in)
-- DISP_IN_B : Disparity Input (running disparity in) (B port)
-- SINIT : Synchronous Initialization. Resets core to known state.
-- SINIT_B : Synchronous Initialization. Resets core to known state.
-- (B port)
-- CODE_ERR : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set.
-- CODE_ERR_B : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set. (B port)
-- DISP_ERR : Disparity Error
-- DISP_ERR_B : Disparity Error (B port)
-- DOUT_B : Data Output, decoded data byte (B port)
-- KOUT_B : Command Output (B port)
-- ND : New Data
-- ND_B : New Data (B port)
-- RUN_DISP : Running Disparity
-- RUN_DISP_B : Running Disparity (B port)
-- SYM_DISP : Symbol Disparity
-- SYM_DISP_B : Symbol Disparity (B port)
-------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_rtl IS
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
--convert C_SINIT_DOUT string to 8bit std_logic_vector
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
--convert C_SINIT_KOUT integer to std_logic
SIGNAL clk_b_i : STD_LOGIC := '0';
SIGNAL din_b_i : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ce_i : STD_LOGIC := '0';
SIGNAL ce_b_i : STD_LOGIC := '0';
SIGNAL disp_in_i : STD_LOGIC := '0';
SIGNAL disp_in_b_i : STD_LOGIC := '0';
SIGNAL sinit_i : STD_LOGIC := '0';
SIGNAL sinit_b_i : STD_LOGIC := '0';
SIGNAL code_err_i : STD_LOGIC := '0';
SIGNAL code_err_b_i : STD_LOGIC := '0';
SIGNAL disp_err_i : STD_LOGIC := '0';
SIGNAL disp_err_b_i : STD_LOGIC := '0';
SIGNAL dout_b_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT_B,8);
--convert C_SINIT_DOUT_B string to 8bit std_logic_vector
SIGNAL kout_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT_B);
--convert C_SINIT_KOUT_B integer to std_logic
SIGNAL nd_i : STD_LOGIC := '0';
SIGNAL nd_b_i : STD_LOGIC := '0';
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
--convert C_SINIT_RUN_DISP integer to std logic
SIGNAL run_disp_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP_B);
--convert C_SINIT_RUN_DISP_B integer to std logic
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
--convert C_SINIT_RUN_DISP integer to slv
SIGNAL sym_disp_b_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP_B,2);
--convert C_SINIT_RUN_DISP_B integer to slv
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
-----------------------------------------------------------------------------
-- LUT-based decoder
-----------------------------------------------------------------------------
glut : IF (C_DECODE_TYPE = 0) GENERATE
ldec : ENTITY decode_8b10b.decode_8b10b_lut
GENERIC MAP (
C_HAS_BPORTS => C_HAS_BPORTS,
C_HAS_CODE_ERR => C_HAS_CODE_ERR,
C_HAS_CODE_ERR_B => C_HAS_CODE_ERR_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_IN_B => C_HAS_DISP_IN_B,
C_HAS_ND => C_HAS_ND,
C_HAS_ND_B => C_HAS_ND_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B,
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_DOUT_B => C_SINIT_DOUT_B,
C_SINIT_KOUT => C_SINIT_KOUT,
C_SINIT_KOUT_B => C_SINIT_KOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP,
C_SINIT_RUN_DISP_B => C_SINIT_RUN_DISP_B
)
PORT MAP(
CLK => CLK,
DIN => DIN,
DOUT => dout_i,
KOUT => kout_i,
CE => ce_i,
DISP_IN => disp_in_i,
SINIT => sinit_i,
CODE_ERR => code_err_i,
DISP_ERR => disp_err_i,
ND => nd_i,
RUN_DISP => run_disp_i,
SYM_DISP => sym_disp_i,
CLK_B => clk_b_i,
DIN_B => din_b_i,
DOUT_B => dout_b_i,
KOUT_B => kout_b_i,
CE_B => ce_b_i,
DISP_IN_B => disp_in_b_i,
SINIT_B => sinit_b_i,
CODE_ERR_B => code_err_b_i,
DISP_ERR_B => disp_err_b_i,
ND_B => nd_b_i,
RUN_DISP_B => run_disp_b_i,
SYM_DISP_B => sym_disp_b_i
);
END GENERATE glut;
-----------------------------------------------------------------------------
-- BRAM-based decoder
-----------------------------------------------------------------------------
gbram : IF (C_DECODE_TYPE /= 0) GENERATE
bdec : ENTITY decode_8b10b.decode_8b10b_bram
GENERIC MAP (
C_ELABORATION_DIR => C_ELABORATION_DIR,
C_HAS_BPORTS => C_HAS_BPORTS,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_IN_B => C_HAS_DISP_IN_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B,
C_HAS_ND => C_HAS_ND,
C_HAS_ND_B => C_HAS_ND_B,
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_DOUT_B => C_SINIT_DOUT_B,
C_SINIT_KOUT => C_SINIT_KOUT,
C_SINIT_KOUT_B => C_SINIT_KOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP,
C_SINIT_RUN_DISP_B => C_SINIT_RUN_DISP_B
)
PORT MAP(
CLK => CLK,
DIN => DIN,
DOUT => dout_i,
KOUT => kout_i,
CE => ce_i,
DISP_IN => disp_in_i,
SINIT => sinit_i,
CODE_ERR => code_err_i,
DISP_ERR => disp_err_i,
ND => nd_i,
RUN_DISP => run_disp_i,
SYM_DISP => sym_disp_i,
CLK_B => clk_b_i,
DIN_B => din_b_i,
DOUT_B => dout_b_i,
KOUT_B => kout_b_i,
CE_B => ce_b_i,
DISP_IN_B => disp_in_b_i,
SINIT_B => sinit_b_i,
CODE_ERR_B => code_err_b_i,
DISP_ERR_B => disp_err_b_i,
ND_B => nd_b_i,
RUN_DISP_B => run_disp_b_i,
SYM_DISP_B => sym_disp_b_i
);
END GENERATE gbram;
---------------------------------------------------------------------------
-- Mandatory A Ports
---------------------------------------------------------------------------
DOUT <= dout_i;
KOUT <= kout_i;
---------------------------------------------------------------------------
-- Optional A Ports --tying off unused ports
---------------------------------------------------------------------------
--Inputs
--ce
gen : IF (C_HAS_CE/=0) GENERATE
ce_i <= CE;
END GENERATE gen;
ngen : IF (C_HAS_CE = 0) GENERATE
ce_i <= '1';
END GENERATE ngen;
--disp_in
gdi : IF (C_HAS_DISP_IN /= 0) GENERATE
disp_in_i <= DISP_IN;
END GENERATE gdi;
ngdi : IF (C_HAS_DISP_IN = 0) GENERATE
disp_in_i <= '0';
END GENERATE ngdi;
--sinit
gs : IF (C_HAS_SINIT /= 0) GENERATE
sinit_i <= SINIT;
END GENERATE gs;
ngs : IF (C_HAS_SINIT = 0) GENERATE
sinit_i <= '0';
END GENERATE ngs;
--Outputs
--nd
gnd : IF (C_HAS_ND /= 0) GENERATE
ASSERT (C_HAS_CE /= 0)
REPORT "Invalid configuration: ND port requires CE port"
SEVERITY WARNING;
ND <= nd_i;
END GENERATE gnd;
ngnd : IF (C_HAS_ND = 0) GENERATE
ND <= '0';
END GENERATE ngnd;
--code_err
gce : IF (C_HAS_CODE_ERR /= 0) GENERATE
CODE_ERR <= code_err_i;
END GENERATE gce;
ngce : IF (C_HAS_CODE_ERR = 0) GENERATE
CODE_ERR <= '0';
END GENERATE ngce;
--disp_err
gder : IF (C_HAS_DISP_ERR /= 0) GENERATE
DISP_ERR <= disp_err_i;
END GENERATE gder;
ngder : IF (C_HAS_DISP_ERR = 0) GENERATE
DISP_ERR <= '0';
END GENERATE ngder;
--run_disp
grd : IF (C_HAS_RUN_DISP /= 0) GENERATE
RUN_DISP <= run_disp_i;
END GENERATE grd;
ngrd : IF (C_HAS_RUN_DISP = 0) GENERATE
RUN_DISP <= '0';
END GENERATE ngrd;
--sym_disp
gsd : IF (C_HAS_SYM_DISP /= 0) GENERATE
SYM_DISP <= sym_disp_i;
END GENERATE gsd;
ngsd : IF (C_HAS_SYM_DISP = 0) GENERATE
SYM_DISP <= "00";
END GENERATE ngsd;
----------------------------------------------------------------------------
-- Optional B Ports -- tying off unused ports
----------------------------------------------------------------------------
--Mandatory B ports (if B ports are selected)
gbpt : IF (C_HAS_BPORTS /= 0) GENERATE
din_b_i <= DIN_B;
clk_b_i <= CLK_B;
DOUT_B <= dout_b_i;
KOUT_B <= kout_b_i;
END GENERATE gbpt;
ngbpt : IF (C_HAS_BPORTS = 0) GENERATE
din_b_i <= (OTHERS => '0');
clk_b_i <= '0';
DOUT_B <= (OTHERS => '0');
KOUT_B <= '0';
END GENERATE ngbpt;
--Inputs
--ce_b
genb : IF (C_HAS_CE_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
ce_b_i <= CE_B;
END GENERATE genb;
ngenb : IF (C_HAS_CE_B = 0 OR C_HAS_BPORTS = 0) GENERATE
ce_b_i <= '1';
END GENERATE ngenb;
ASSERT (NOT(C_HAS_CE_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate CE_B when C_HAS_BPORTS=0"
SEVERITY WARNING;
--disp_in_b
gdib : IF (C_HAS_DISP_IN_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
disp_in_b_i <= DISP_IN_B;
END GENERATE gdib;
ngdib : IF (C_HAS_DISP_IN_B = 0 OR C_HAS_BPORTS = 0) GENERATE
disp_in_b_i <= '0';
END GENERATE ngdib;
ASSERT (NOT(C_HAS_DISP_IN_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate DISP_IN_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--sinit_b
gsb : IF (C_HAS_SINIT_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
sinit_b_i <= SINIT_B;
END GENERATE gsb;
ngsb : IF (C_HAS_SINIT_B = 0 OR C_HAS_BPORTS = 0) GENERATE
sinit_b_i <= '0';
END GENERATE ngsb;
ASSERT (NOT(C_HAS_SINIT_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate SINIT_B when C_HAS_BPORTS=0"
SEVERITY WARNING;
--Outputs
--code_err_b
gceb : IF (C_HAS_CODE_ERR_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
CODE_ERR_B <= code_err_b_i;
END GENERATE gceb;
ngceb : IF (C_HAS_CODE_ERR_B = 0 OR C_HAS_BPORTS = 0) GENERATE
CODE_ERR_B <= '0';
END GENERATE ngceb;
ASSERT (NOT(C_HAS_CODE_ERR_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate CODE_ERR_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--disp_err_b
gdeb : IF (C_HAS_DISP_ERR_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
DISP_ERR_B <= disp_err_b_i;
END GENERATE gdeb;
ngdeb : IF (C_HAS_DISP_ERR_B = 0 OR C_HAS_BPORTS = 0) GENERATE
DISP_ERR_B <= '0';
END GENERATE ngdeb;
ASSERT (NOT(C_HAS_DISP_ERR_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate DISP_ERR_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--nd_b
gndb : IF (C_HAS_ND_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
ASSERT (C_HAS_CE_B /= 0)
REPORT "Invalid configuration: ND_B port requires CE_B port"
SEVERITY WARNING;
ND_B <= nd_b_i;
END GENERATE gndb;
ngndb : IF (C_HAS_ND_B = 0 OR C_HAS_BPORTS = 0) GENERATE
ND_B <= '0';
END GENERATE ngndb;
ASSERT (NOT(C_HAS_ND_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate ND_B when C_HAS_BPORTS=0"
SEVERITY WARNING;
--run_disp_b
grdb : IF (C_HAS_RUN_DISP_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
RUN_DISP_B <= run_disp_b_i;
END GENERATE grdb;
ngrdb : IF (C_HAS_RUN_DISP_B = 0 OR C_HAS_BPORTS = 0) GENERATE
RUN_DISP_B <= '0';
END GENERATE ngrdb;
ASSERT (NOT(C_HAS_RUN_DISP_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate RUN_DISP_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--sym_disp_b
gsdb : IF (C_HAS_SYM_DISP_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
SYM_DISP_B <= sym_disp_b_i;
END GENERATE gsdb;
ngsdb : IF (C_HAS_SYM_DISP_B = 0 OR C_HAS_BPORTS = 0) GENERATE
SYM_DISP_B <= "00";
END GENERATE ngsdb;
ASSERT (NOT(C_HAS_SYM_DISP_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate SYM_DISP_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
END xilinx;
|
gpl-3.0
|
1af165998dfd1ce051ea76b6652a1dcf
| 0.472219 | 3.491336 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/gn4124-core/wbmaster32.vhd
| 2 | 21,173 |
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: 32-bit Wishbone master (wbmaster32.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.2
--
-- description: Provides a Wishbone interface for single read and write
-- control and status registers
--
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 27-09-2010 (mcattin) Split wishbone and gn4124 clock domains
-- All signals crossing the clock domains are now going through fifos.
-- Dead times optimisation in packet generator.
-- 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.common_pkg.all;
entity wbmaster32 is
generic (
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From P2L packet decoder
--
-- Header
pd_wbm_hdr_start_i : in std_logic; -- Header strobe
pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_wbm_hdr_cid_i : in std_logic_vector(1 downto 0); -- Completion ID
pd_wbm_target_mrd_i : in std_logic; -- Target memory read
pd_wbm_target_mwr_i : in std_logic; -- Target memory write
--
-- Address
pd_wbm_addr_start_i : in std_logic; -- Address strobe
pd_wbm_addr_i : in std_logic_vector(31 downto 0); -- Target address (in byte) that will increment with data
-- increment = 4 bytes
--
-- Data
pd_wbm_data_valid_i : in std_logic; -- Indicates Data is valid
pd_wbm_data_last_i : in std_logic; -- Indicates end of the packet
pd_wbm_data_i : in std_logic_vector(31 downto 0); -- Data
pd_wbm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- Ready to accept target write
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
wbm_arb_valid_o : out std_logic; -- Read completion signals
wbm_arb_dframe_o : out std_logic; -- Toward the arbiter
wbm_arb_data_o : out std_logic_vector(31 downto 0);
wbm_arb_req_o : out std_logic;
arb_wbm_gnt_i : in std_logic;
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(30 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
wb_stall_i : in std_logic; -- Stall
wb_err_i : in std_logic; -- Error
wb_rty_i : in std_logic; -- Retry
wb_int_i : in std_logic -- Interrupt
);
end wbmaster32;
architecture behaviour of wbmaster32 is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
constant c_FROM_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Sync fifos
signal fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
signal to_wb_fifo_rd : std_logic;
signal to_wb_fifo_wr : std_logic;
signal to_wb_fifo_din : std_logic_vector(63 downto 0);
signal to_wb_fifo_dout : std_logic_vector(63 downto 0);
signal to_wb_fifo_rw : std_logic;
signal to_wb_fifo_data : std_logic_vector(31 downto 0);
signal to_wb_fifo_addr : std_logic_vector(30 downto 0);
signal from_wb_fifo_empty : std_logic;
signal from_wb_fifo_full : std_logic;
signal from_wb_fifo_rd : std_logic;
signal from_wb_fifo_wr : std_logic;
signal from_wb_fifo_din : std_logic_vector(31 downto 0);
signal from_wb_fifo_dout : std_logic_vector(31 downto 0);
-- Wishbone
type wishbone_state_type is (WB_IDLE, WB_READ_FIFO, WB_CYCLE, WB_WAIT_ACK);
signal wishbone_current_state : wishbone_state_type;
signal wb_ack_t : std_logic;
signal wb_err_t : std_logic;
signal wb_dat_i_t : std_logic_vector(31 downto 0);
signal wb_cyc_t : std_logic;
signal wb_dat_o_t : std_logic_vector(31 downto 0);
signal wb_stb_t : std_logic;
signal wb_adr_t : std_logic_vector(30 downto 0);
signal wb_we_t : std_logic;
signal wb_sel_t : std_logic_vector(3 downto 0);
signal wb_stall_t : std_logic;
signal wb_ack_timeout_cnt : unsigned(log2_ceil(g_ACK_TIMEOUT)-1 downto 0);
signal wb_ack_timeout : std_logic;
-- L2P packet generator
type l2p_read_cpl_state_type is (L2P_IDLE, L2P_HEADER, L2P_DATA);
signal l2p_read_cpl_current_state : l2p_read_cpl_state_type;
signal p2l_cid : std_logic_vector(1 downto 0);
signal s_l2p_header : std_logic_vector(31 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset for fifo
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst_n <= not(rst_n_i);
end generate;
------------------------------------------------------------------------------
-- Write frame from P2L decoder to fifo
------------------------------------------------------------------------------
-- ready to receive new target write if fifo not full
p_wr_rdy_o <= "00" when to_wb_fifo_full = '1' else "11";
-- pause transfer from GN4124 when fifo is full
p2l_rdy_o <= not(to_wb_fifo_full);
p_from_decoder : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
to_wb_fifo_din <= (others => '0');
to_wb_fifo_wr <= '0';
elsif rising_edge(clk_i) then
if (pd_wbm_target_mwr_i = '1' and pd_wbm_data_valid_i = '1') then
-- Target write
-- wishbone address is in 32-bit words and address from PCIe in byte
-- pd_wbm_addr_i(0) represent the BAR (0 = BAR0, 1 = BAR 2)
to_wb_fifo_din(62 downto 32) <= pd_wbm_addr_i(0) & pd_wbm_addr_i(31 downto 2);
to_wb_fifo_din(31 downto 0) <= pd_wbm_data_i;
to_wb_fifo_din(63) <= '1';
to_wb_fifo_wr <= '1';
elsif (pd_wbm_target_mrd_i = '1' and pd_wbm_addr_start_i = '1') then
-- Target read request
-- wishbone address is in 32-bit words and address from PCIe in byte
-- pd_wbm_addr_i(0) represent the BAR (0 = BAR0, 1 = BAR 2)
to_wb_fifo_din(62 downto 32) <= pd_wbm_addr_i(0) & pd_wbm_addr_i(31 downto 2);
to_wb_fifo_din(63) <= '0';
to_wb_fifo_wr <= '1';
else
to_wb_fifo_wr <= '0';
end if;
end if;
end process p_from_decoder;
------------------------------------------------------------------------------
-- Packet generator
------------------------------------------------------------------------------
-- Generates read completion with requested data
-- Single 32-bit word read only
-- Store CID for read completion packet
p_pkt_gen : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
p2l_cid <= (others => '0');
elsif rising_edge(clk_i) then
if (pd_wbm_hdr_start_i = '1') then
p2l_cid <= pd_wbm_hdr_cid_i;
end if;
end if;
end process p_pkt_gen;
--read completion header
s_l2p_header <= "000" --> Traffic Class
& '0' --> Reserved
& "0101" --> Read completion (Master read competition with data)
& "000000" --> Reserved
& "00" --> Completion Status
& '1' --> Last completion packet
& "00" --> Reserved
& '0' --> VC (Vitrual Channel)
& p2l_cid --> CID (Completion Identifer)
& "0000000001"; --> Length (Single 32-bit word read only)
------------------------------------------------------------------------------
-- L2P packet write FSM
------------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_req_o <= '0';
wbm_arb_data_o <= (others => '0');
wbm_arb_valid_o <= '0';
wbm_arb_dframe_o <= '0';
from_wb_fifo_rd <= '0';
elsif rising_edge(clk_i) then
case l2p_read_cpl_current_state is
when L2P_IDLE =>
wbm_arb_req_o <= '0';
wbm_arb_data_o <= (others => '0');
wbm_arb_valid_o <= '0';
wbm_arb_dframe_o <= '0';
if(from_wb_fifo_empty = '0' and p_rd_d_rdy_i = "11") then
-- generate a packet when read data in fifo and GN4124 ready to receive the packet
wbm_arb_req_o <= '1';
from_wb_fifo_rd <= '1';
l2p_read_cpl_current_state <= L2P_HEADER;
end if;
when L2P_HEADER =>
from_wb_fifo_rd <= '0';
if(arb_wbm_gnt_i = '1') then
wbm_arb_req_o <= '0';
wbm_arb_data_o <= s_l2p_header;
wbm_arb_valid_o <= '1';
wbm_arb_dframe_o <= '1';
l2p_read_cpl_current_state <= L2P_DATA;
end if;
when L2P_DATA =>
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_data_o <= from_wb_fifo_dout;
wbm_arb_dframe_o <= '0';
when others =>
l2p_read_cpl_current_state <= L2P_IDLE;
wbm_arb_req_o <= '0';
wbm_arb_data_o <= (others => '0');
wbm_arb_valid_o <= '0';
wbm_arb_dframe_o <= '0';
from_wb_fifo_rd <= '0';
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
-----------------------------------------------------------------------------
-- fifo for PCIe to WB transfer
cmp_fifo_to_wb : generic_async_fifo
generic map (
g_data_width => 64,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din,
we_i => to_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
clk_rd_i => wb_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
to_wb_fifo_rw <= to_wb_fifo_dout(63);
to_wb_fifo_addr <= to_wb_fifo_dout(62 downto 32); -- 31-bit
to_wb_fifo_data <= to_wb_fifo_dout(31 downto 0); -- 32-bit
-- fifo for WB to PCIe transfer
cmp_from_wb_fifo : generic_async_fifo
generic map (
g_data_width => 32,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_FROM_WB_FIFO_FULL_THRES)
port map (
rst_n_i => fifo_rst_n,
clk_wr_i => wb_clk_i,
d_i => from_wb_fifo_din,
we_i => from_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => from_wb_fifo_full,
wr_count_o => open,
clk_rd_i => clk_i,
q_o => from_wb_fifo_dout,
rd_i => from_wb_fifo_rd,
rd_empty_o => from_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
-----------------------------------------------------------------------------
-- Wishbone master FSM
-----------------------------------------------------------------------------
p_wb_fsm : process (wb_clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
wishbone_current_state <= WB_IDLE;
to_wb_fifo_rd <= '0';
wb_cyc_t <= '0';
wb_stb_t <= '0';
wb_we_t <= '0';
wb_sel_t <= "0000";
wb_dat_o_t <= (others => '0');
wb_adr_t <= (others => '0');
from_wb_fifo_din <= (others => '0');
from_wb_fifo_wr <= '0';
elsif rising_edge(wb_clk_i) then
case wishbone_current_state is
when WB_IDLE =>
-- stop writing to fifo
from_wb_fifo_wr <= '0';
-- clear bus
wb_cyc_t <= '0';
wb_stb_t <= '0';
wb_sel_t <= "0000";
-- Wait for a Wishbone cycle
if (to_wb_fifo_empty = '0') then
-- read requset in fifo (address, data and transfer type)
to_wb_fifo_rd <= '1';
wishbone_current_state <= WB_READ_FIFO;
end if;
when WB_READ_FIFO =>
-- read only one request in fifo (no block transfer)
to_wb_fifo_rd <= '0';
wishbone_current_state <= WB_CYCLE;
when WB_CYCLE =>
-- initate a bus cycle
wb_cyc_t <= '1';
wb_stb_t <= '1';
wb_we_t <= to_wb_fifo_rw;
wb_sel_t <= "1111";
wb_adr_t <= to_wb_fifo_addr;
--if (to_wb_fifo_rw = '1') then
wb_dat_o_t <= to_wb_fifo_data;
--end if;
-- wait for slave to ack
wishbone_current_state <= WB_WAIT_ACK;
when WB_WAIT_ACK =>
if wb_stall_t = '0' then
wb_stb_t <= '0';
end if;
if (wb_ack_t = '1') then
-- for read cycles write read data to fifo
if (wb_we_t = '0') then
from_wb_fifo_din <= wb_dat_i_t;
from_wb_fifo_wr <= '1';
end if;
-- end of the bus cycle
wb_cyc_t <= '0';
wishbone_current_state <= WB_IDLE;
elsif (wb_err_t = '1') or (wb_ack_timeout = '1') then
-- e.g. When trying to access unmapped wishbone addresses,
-- the wb crossbar asserts ERR. If ERR is not asserted when
-- accessing un-mapped addresses, a timeout makes sure the
-- transaction terminates.
if (wb_we_t = '0') then
from_wb_fifo_din <= (others => '1'); -- dummy data as the transaction failed
from_wb_fifo_wr <= '1';
end if;
-- end of the bus cycle
wb_cyc_t <= '0';
wishbone_current_state <= WB_IDLE;
end if;
when others =>
-- should not get here!
wishbone_current_state <= WB_IDLE;
wb_cyc_t <= '0';
wb_stb_t <= '0';
wb_we_t <= '0';
wb_sel_t <= "0000";
wb_dat_o_t <= (others => '0');
wb_adr_t <= (others => '0');
to_wb_fifo_rd <= '0';
from_wb_fifo_din <= (others => '0');
from_wb_fifo_wr <= '0';
end case;
end if;
end process p_wb_fsm;
wb_adr_o <= wb_adr_t;
wb_cyc_o <= wb_cyc_t;
wb_stb_o <= wb_stb_t;
wb_we_o <= wb_we_t;
wb_sel_o <= wb_sel_t;
wb_dat_i_t <= wb_dat_i;
wb_dat_o <= wb_dat_o_t;
wb_ack_t <= wb_ack_i;
wb_stall_t <= wb_stall_i;
wb_err_t <= wb_err_i;
-- ACK timeout
p_wb_ack_timeout_cnt : process (wb_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
wb_ack_timeout_cnt <= (others => '1');
elsif rising_edge(wb_clk_i) then
if wishbone_current_state = WB_WAIT_ACK then
if wb_ack_timeout_cnt /= 0 then
wb_ack_timeout_cnt <= wb_ack_timeout_cnt - 1;
end if;
else
wb_ack_timeout_cnt <= (others => '1');
end if;
end if;
end process p_wb_ack_timeout_cnt;
p_ack_timeout : process (wb_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
wb_ack_timeout <= '0';
elsif rising_edge(wb_clk_i) then
if wb_ack_timeout_cnt = 0 then
wb_ack_timeout <= '1';
else
wb_ack_timeout <= '0';
end if;
end if;
end process p_ack_timeout;
end behaviour;
|
gpl-3.0
|
ebcb54b9b505bc0c295e1b5521c9b13a
| 0.456714 | 3.659983 | false | false | false | false |
metaspace/ghdl_extra
|
clk/rt_clk.vhdl
| 1 | 3,189 |
-- Fichier : rt_clk.vhdl
-- created by Yann Guidon / ygdes.com
-- jeu. avril 15 20:13:20 CEST 2010
-- version lun. juin 21 14:30:07 CEST 2010 : timing modified
-- rt_clk.vhdl : clock generator that is synchronised with the host computer
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
package rt_utils is
procedure observe_std_ulogic
(name: string; s:std_ulogic);
procedure realtime_init(ms : integer);
attribute foreign of realtime_init :
procedure is "VHPIDIRECT realtime_init";
impure function realtime_delay return integer;
attribute foreign of realtime_delay :
function is "VHPIDIRECT realtime_delay";
procedure realtime_exit;
attribute foreign of realtime_exit :
procedure is "VHPIDIRECT realtime_exit";
end rt_utils;
package body rt_utils is
procedure observe_std_ulogic
(name: string; s:std_ulogic) is
begin
report name & "=" & std_ulogic'image(s);
end procedure;
-- fonctions vides, dont le code est en C :
procedure realtime_init(ms : integer) is
begin
assert false report "VHPI" severity failure;
end realtime_init;
impure function realtime_delay return integer is
begin
assert false report "VHPI" severity failure;
end realtime_delay;
procedure realtime_exit is
begin
assert false report "VHPI" severity failure;
end realtime_exit;
end rt_utils;
-----------------------------------------------------------
------------------ the clock ------------------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rt_utils.all;
entity rt_clk is
generic(
ms: integer:=500 -- default : 2*500ms=1s=1Hz
);
port(
clk : inout std_ulogic:='0';
-- clk est en mode "inout" pour qu'on puisse relire
-- sa derniere valeur afin de la modifier.
-- La valeur est initialisee a '0' car sinon
-- elle est a 'U' par defaut, valeur qui donne
-- elle-meme lorsqu'on effectue l'operation "not".
stop: in std_ulogic:='0'
-- mettre a '1' pour arreter la simulation
);
end entity;
architecture simple of rt_clk is
begin
process is
begin
realtime_init(ms);
-- report "setting real time interval to "
-- & integer'image(ms) & "ms";
while stop='0' loop
wait for ms * 1000 us;
while realtime_delay=0 loop
wait for 0 ns; -- tourne un peu a vide
end loop;
clk <= not clk;
end loop;
realtime_exit;
wait;
end process;
end simple;
|
gpl-3.0
|
66533fecfa8d7da5727c648e5cc02397
| 0.655691 | 3.870146 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/barrel.vhdl
| 1 | 926 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity barrel is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
I : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
Q2 : out std_logic_vector(3 downto 0)
);
end entity;
architecture arch of barrel is
signal Qt, Qt2 : std_logic_vector(3 downto 0):="0000";
begin
process(clk, se)
begin
if rising_edge(clk) then
if (se(0)='0' and se(1)='0') then
Qt<=I;
Qt2<=I;
elsif (se(0)='1' and se(1)='0') then
Qt<=I(3 downto 1)&"0";
Qt2<=I(3)&I(3 downto 1);
elsif (se(0)='0' and se(1)='1') then
Qt<=I(3 downto 2)&"00";
Qt2<=I(3)&I(3)&I(3 downto 2);
else
Qt<=I(3)&"000";
Qt2<=(others =>I(3));
end if;
end if;
end process;
Q<=Qt;
Q2<=Qt2;
end architecture;
|
gpl-3.0
|
04451aef110a24a40846ae59a4ee1438
| 0.530238 | 2.902821 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/disp_controller.vhd
| 1 | 9,444 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 01:28:25 03/22/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: disp_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity disp_controller is
port(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(7 downto 0);
data_count : in std_logic_vector(5 downto 0);
show_data : in std_logic;
get_data_o : out std_logic;
dout : out std_logic_vector(3 downto 0);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic
);
end disp_controller;
architecture Behavioral of disp_controller is
type t_state is (power_on1, power_on2, power_on3, power_on4, send1, send2, send3,
func_set, entry_mode, disp_on, disp_clear, clear_wait, addr_set, disp_data, idle);
signal state, state_next : t_state;
signal rs, rs_next : std_logic;
signal en, en_next : std_logic;
signal data, data_next : std_logic_vector(3 downto 0);
signal nibble, nibble_next : std_logic; -- 0 if high, 1 if low, high goes first
signal delay, delay_next : integer range 0 to 800000; -- up to 750000 cycles
signal send_mode, send_mode_next : integer range 0 to 10;
signal addr_mode, addr_mode_next : integer range 1 to 2;
signal data_cnt, data_cnt_next : unsigned(5 downto 0);
signal target_data_cnt : unsigned(5 downto 0);
signal get_data, get_data_next : std_logic;
signal d_low, d_high, d_low_next, d_high_next : std_logic_vector(3 downto 0);
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= power_on1;
rs <= '0';
data <= "0000";
delay <= 0;
nibble <= '0';
en <= '0';
send_mode <= 0;
addr_mode <= 1;
data_cnt <= (others => '0');
get_data <= '0';
d_low <= (others => '0');
d_high <= (others => '0');
else
state <= state_next;
rs <= rs_next;
data <= data_next;
delay <= delay_next;
nibble <= nibble_next;
en <= en_next;
send_mode <= send_mode_next;
addr_mode <= addr_mode_next;
data_cnt <= data_cnt_next;
get_data <= get_data_next;
d_low <= d_low_next;
d_high <= d_high_next;
end if;
end if;
end process;
routing : process (state, rs, data, delay, nibble, show_data, en, send_mode, addr_mode, data_cnt, get_data, d_low, d_high, din, data_count, target_data_cnt)
begin
state_next <= state;
rs_next <= rs;
data_next <= data;
delay_next <= delay;
nibble_next <= nibble;
en_next <= en;
send_mode_next <= send_mode;
addr_mode_next <= addr_mode;
data_cnt_next <= data_cnt;
get_data_next <= get_data;
d_low_next <= d_low;
d_high_next <= d_high;
case state is
when send1 =>
if delay = 3 then
en_next <= '1';
state_next <= send2;
delay_next <= 0;
else delay_next <= delay + 1;
end if;
when send2 =>
if delay = 12 then
en_next <= '0';
state_next <= send3;
delay_next <= 0;
else delay_next <= delay + 1;
end if;
when send3 =>
if delay = 3 then
case send_mode is
when 0 => state_next <= power_on2;
when 1 => state_next <= power_on3;
when 2 => state_next <= power_on4;
when 3 => state_next <= func_set;
when 4 => state_next <= entry_mode;
when 5 => state_next <= disp_on;
when 6 => state_next <= disp_clear;
when 7 => state_next <= addr_set;
when 8 => state_next <= disp_data;
when 9 => state_next <= idle;
when 10 => state_next <= clear_wait;
end case;
delay_next <= 0;
else delay_next <= delay + 1;
end if;
---INITIALIZATION---
when power_on1 =>
if delay = 770000 then
data_next <= "0011";
rs_next <= '0';
delay_next <= 0;
state_next <= send1;
else delay_next <= delay + 1;
end if;
when power_on2 =>
if delay = 210000 then
data_next <= "0011";
rs_next <= '0';
delay_next <= 0;
state_next <= send1;
send_mode_next <= 1;
else delay_next <= delay + 1;
end if;
when power_on3 =>
if delay = 7000 then
data_next <= "0011";
rs_next <= '0';
delay_next <= 0;
state_next <= send1;
send_mode_next <= 2;
else delay_next <= delay + 1;
end if;
when power_on4 =>
if delay = 3000 then
data_next <= "0010";
rs_next <= '0';
delay_next <= 0;
state_next <= send1;
send_mode_next <= 3;
else delay_next <= delay + 1;
end if;
---CONFIGURATION---
when func_set =>
if nibble = '0' then
if delay = 3000 then
data_next <= "0010";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
nibble_next <= '1';
else delay_next <= delay + 1;
end if;
else
if delay = 100 then
data_next <= "1000";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
send_mode_next <= 4;
nibble_next <= '0';
else delay_next <= delay + 1;
end if;
end if;
when entry_mode =>
if nibble = '0' then
if delay = 3000 then
data_next <= "0000";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
nibble_next <= '1';
else delay_next <= delay + 1;
end if;
else
if delay = 100 then
data_next <= "0100";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
send_mode_next <= 5;
nibble_next <= '0';
else delay_next <= delay + 1;
end if;
end if;
when disp_on =>
if nibble = '0' then
if delay = 3000 then
data_next <= "0000";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
nibble_next <= '1';
else delay_next <= delay + 1;
end if;
else
if delay = 100 then
data_next <= "1110";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
send_mode_next <= 6;
nibble_next <= '0';
else delay_next <= delay + 1;
end if;
end if;
when disp_clear =>
if nibble = '0' then
if delay = 3000 then
data_next <= "0000";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
nibble_next <= '1';
else delay_next <= delay + 1;
end if;
else
if delay = 100 then
data_next <= "0001";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
send_mode_next <= 10;
nibble_next <= '0';
else delay_next <= delay + 1;
end if;
end if;
when clear_wait =>
if delay = 90000 then
state_next <= idle;
delay_next <= 0;
else
delay_next <= delay + 1;
end if;
---WRITING DATA---
when addr_set =>
if nibble = '0' then
if delay = 0 then
case addr_mode is
when 1 => data_next <= "1000";
when 2 => data_next <= "1100";
end case;
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
nibble_next <= '1';
get_data_next <= '0';
else
delay_next <= delay + 1;
get_data_next <= '0';
end if;
else
if delay = 98 then
delay_next <= delay + 1;
if addr_mode = 1 then
get_data_next <= '1';
end if;
elsif delay = 100 then
data_next <= "0000";
rs_next <= '0';
state_next <= send1;
delay_next <= 0;
send_mode_next <= 8;
nibble_next <= '0';
get_data_next <= '0';
if addr_mode = 1 then
d_high_next <= din(7 downto 4);
d_low_next <= din(3 downto 0);
end if;
else
delay_next <= delay + 1;
get_data_next <= '0';
end if;
end if;
when disp_data =>
-- change address after 16 letters
if nibble = '0' then
if delay = 3000 then
data_next <= d_high;
rs_next <= '1';
state_next <= send1;
delay_next <= 0;
nibble_next <= '1';
get_data_next <= '0';
else
delay_next <= delay + 1;
get_data_next <= '0';
end if;
else
if delay = 98 then
delay_next <= delay + 1;
get_data_next <= '1';
elsif delay = 100 then
data_next <= d_low;
rs_next <= '1';
state_next <= send1;
delay_next <= 0;
nibble_next <= '0';
get_data_next <= '0';
d_high_next <= din(7 downto 4);
d_low_next <= din(3 downto 0);
if data_cnt = target_data_cnt - 1 then
send_mode_next <= 9;
elsif data_cnt = 15 then
send_mode_next <= 7;
addr_mode_next <= 2;
else
send_mode_next <= 8;
end if;
data_cnt_next <= data_cnt + 1;
else
delay_next <= delay + 1;
get_data_next <= '0';
end if;
end if;
when idle =>
if show_data = '1' then
--state_next <= disp_clear;
state_next <= addr_set;
addr_mode_next <= 1;
data_cnt_next <= "000000";
end if;
end case;
end process;
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
target_data_cnt <= "000000";
elsif show_data = '1' then
target_data_cnt <= unsigned(data_count);
else
target_data_cnt <= target_data_cnt;
end if;
end if;
end process;
lcd_rw <= '0';
lcd_rs <= rs;
lcd_e <= en;
dout <= data;
get_data_o <= get_data;
end Behavioral;
|
mit
|
9c55c6ffee87c2451b61bb36f78a2183
| 0.526366 | 2.904059 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/rotary.vhd
| 1 | 2,210 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 23:45:33 05/06/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: rotary - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rotary is
port(
clk : in std_logic;
rot_a : in std_logic;
rot_b : in std_logic;
up : out std_logic;
down : out std_logic
);
end rotary;
architecture Behavioral of rotary is
signal rotary_a_in : std_logic;
signal rotary_b_in : std_logic;
signal rotary_in : std_logic_vector(1 downto 0);
signal rotary_q1 : std_logic;
signal rotary_q2 : std_logic;
signal delay_rotary_q1 : std_logic;
signal rotary_event : std_logic;
signal rotary_left : std_logic;
signal qa0, qa1, qa2, qb0, qb1, qb2 : std_logic;
begin
rotary_filter: process(clk)
begin
if clk'event and clk='1' then
rotary_a_in <= rot_a;
rotary_b_in <= rot_b;
rotary_in <= rotary_b_in & rotary_a_in;
case rotary_in is
when "00" =>
rotary_q1 <= '0';
rotary_q2 <= rotary_q2;
when "01" =>
rotary_q1 <= rotary_q1;
rotary_q2 <= '0';
when "10" =>
rotary_q1 <= rotary_q1;
rotary_q2 <= '1';
when "11" =>
rotary_q1 <= '1';
rotary_q2 <= rotary_q2;
when others =>
rotary_q1 <= rotary_q1;
rotary_q2 <= rotary_q2;
end case;
end if;
end process;
direction: process(clk)
begin
if clk'event and clk='1' then
delay_rotary_q1 <= rotary_q1;
if rotary_q1='1' and delay_rotary_q1='0' then
rotary_event <= '1';
rotary_left <= rotary_q2;
else
rotary_event <= '0';
rotary_left <= rotary_left;
end if;
end if;
end process;
output: process(clk)
begin
if clk'event and clk='1' then
if rotary_event = '1' and rotary_left = '1' then
up <= '0';
down <= '1';
elsif rotary_event = '1' and rotary_left = '0' then
up <= '1';
down <= '0';
else
up <= '0';
down <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
55930aa144d5c8fad954edd5bb770734
| 0.557466 | 2.877604 | false | false | false | false |
LemurPwned/classic-fpga
|
machines/code_det_tb.vhdl
| 1 | 1,088 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity code_det_tb is
end entity;
architecture code_det_tb of code_det_tb is
component code_det is
port (
clk : in std_logic;
I : in std_logic_vector (3 downto 0);
O : out std_logic
);
end component;
signal clk : std_logic :='1';
signal O : std_logic :='0';
signal I : std_logic_vector(3 downto 0) :="0000";
constant period : time := 10 ns;
begin
mapping: code_det port map(clk=>clk, O=>O, I=>I);
clk_proc : process
begin
clk<= not clk;
wait for period/2;
end process;
stim_proc: process
begin
I<="0001";
wait for 10 ns;
I<="0011";
wait for 10 ns;
I<="1001";
wait for 10 ns;
I<="0001";
wait for 10 ns;
I<="1001";
wait for 10 ns;
I<="0111";
wait for 10 ns;
I<="0010";
wait for 10 ns;
I<="0001";
wait for 10 ns;
I<="0110";
wait for 10 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
d4906e654ea56adec6fec54e71ff34cd
| 0.568934 | 3.247761 | false | false | false | false |
freecores/yavga
|
vhdl/waveform_RAM.vhd
| 1 | 34,250 |
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity waveform_RAM is
port (
i_DIA : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Input
-- i_DIPA : in std_logic; -- 2-bit parity Input
-- i_ENA : in std_logic; -- RAM Enable Input
i_WEA : in std_logic; -- Write Enable Input
-- i_SSRA : in std_logic; -- Synchronous Set/Reset Input
i_clockA : in std_logic; -- Clock
i_ADDRA : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0); -- 10-bit Address Input
--o_DOA : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Output
-- o_DOPA : out std_logic -- 2-bit parity Output
--
i_DIB : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0); -- 16-bit Data Input
-- i_DIPB : in std_logic; -- 2-bit parity Input
-- i_ENB : in std_logic; -- RAM Enable Input
i_WEB : in std_logic; -- Write Enable Input
-- i_SSRB : in std_logic; -- Synchronous Set/Reset Input
i_clockB : in std_logic; -- Clock
i_ADDRB : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0); -- 10-bit Address Input
o_DOB : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0) -- 16-bit Data Output
-- o_DOPB : out std_logic -- 2-bit parity Output
);
end waveform_RAM;
architecture Behavioral of waveform_RAM is
constant c_ram_size : natural := 2**(c_WAVFRM_ADDR_BUS_W);
type t_ram is array (c_ram_size-1 downto 0) of
std_logic_vector (c_WAVFRM_DATA_BUS_W - 1 downto 0);
shared variable v_ram : t_ram := (
0 => X"1000" or X"00BF",
1 => X"1000" or X"00BE",
2 => X"1000" or X"00BD",
3 => X"1000" or X"00BD",
4 => X"1000" or X"00BC",
5 => X"1000" or X"00BB",
6 => X"1000" or X"00BB",
7 => X"1000" or X"00BA",
8 => X"1000" or X"00B9",
9 => X"1000" or X"00B9",
10 => X"1000" or X"00B8",
11 => X"1000" or X"00B7",
12 => X"1000" or X"00B7",
13 => X"1000" or X"00B6",
14 => X"1000" or X"00B5",
15 => X"1000" or X"00B5",
16 => X"1000" or X"00B4",
17 => X"1000" or X"00B3",
18 => X"1000" or X"00B3",
19 => X"1000" or X"00B2",
20 => X"1000" or X"00B1",
21 => X"1000" or X"00B1",
22 => X"1000" or X"00B0",
23 => X"1000" or X"00B0",
24 => X"1000" or X"00AF",
25 => X"1000" or X"00AE",
26 => X"1000" or X"00AE",
27 => X"1000" or X"00AD",
28 => X"1000" or X"00AD",
29 => X"1000" or X"00AC",
30 => X"1000" or X"00AB",
31 => X"1000" or X"00AB",
32 => X"1000" or X"00AA",
33 => X"1000" or X"00AA",
34 => X"1000" or X"00A9",
35 => X"1000" or X"00A9",
36 => X"1000" or X"00A8",
37 => X"1000" or X"00A8",
38 => X"1000" or X"00A7",
39 => X"1000" or X"00A7",
40 => X"1000" or X"00A6",
41 => X"1000" or X"00A6",
42 => X"1000" or X"00A5",
43 => X"1000" or X"00A5",
44 => X"1000" or X"00A4",
45 => X"1000" or X"00A4",
46 => X"1000" or X"00A3",
47 => X"1000" or X"00A3",
48 => X"1000" or X"00A2",
49 => X"1000" or X"00A2",
50 => X"1000" or X"00A2",
51 => X"1000" or X"00A1",
52 => X"1000" or X"00A1",
53 => X"1000" or X"00A1",
54 => X"1000" or X"00A0",
55 => X"1000" or X"00A0",
56 => X"1000" or X"00A0",
57 => X"1000" or X"009F",
58 => X"1000" or X"009F",
59 => X"1000" or X"009F",
60 => X"1000" or X"009E",
61 => X"1000" or X"009E",
62 => X"1000" or X"009E",
63 => X"1000" or X"009E",
64 => X"1000" or X"009E",
65 => X"1000" or X"009D",
66 => X"1000" or X"009D",
67 => X"1000" or X"009D",
68 => X"1000" or X"009D",
69 => X"1000" or X"009D",
70 => X"1000" or X"009D",
71 => X"1000" or X"009D",
72 => X"1000" or X"009D",
73 => X"1000" or X"009D",
74 => X"1000" or X"009D",
75 => X"1000" or X"009D",
76 => X"1000" or X"009D",
77 => X"1000" or X"009D",
78 => X"1000" or X"009D",
79 => X"1000" or X"009D",
80 => X"1000" or X"009D",
81 => X"1000" or X"009D",
82 => X"1000" or X"009D",
83 => X"1000" or X"009D",
84 => X"1000" or X"009D",
85 => X"1000" or X"009D",
86 => X"1000" or X"009E",
87 => X"1000" or X"009E",
88 => X"1000" or X"009E",
89 => X"1000" or X"009E",
90 => X"1000" or X"009E",
91 => X"1000" or X"009F",
92 => X"1000" or X"009F",
93 => X"1000" or X"009F",
94 => X"1000" or X"00A0",
95 => X"1000" or X"00A0",
96 => X"1000" or X"00A0",
97 => X"1000" or X"00A1",
98 => X"1000" or X"00A1",
99 => X"1000" or X"00A2",
100 => X"1000" or X"00A2",
101 => X"1000" or X"00A3",
102 => X"1000" or X"00A3",
103 => X"1000" or X"00A4",
104 => X"1000" or X"00A4",
105 => X"1000" or X"00A5",
106 => X"1000" or X"00A5",
107 => X"1000" or X"00A6",
108 => X"1000" or X"00A7",
109 => X"1000" or X"00A7",
110 => X"1000" or X"00A8",
111 => X"1000" or X"00A8",
112 => X"1000" or X"00A9",
113 => X"1000" or X"00AA",
114 => X"1000" or X"00AB",
115 => X"1000" or X"00AB",
116 => X"1000" or X"00AC",
117 => X"1000" or X"00AD",
118 => X"1000" or X"00AE",
119 => X"1000" or X"00AF",
120 => X"1000" or X"00AF",
121 => X"1000" or X"00B0",
122 => X"1000" or X"00B1",
123 => X"1000" or X"00B2",
124 => X"1000" or X"00B3",
125 => X"1000" or X"00B4",
126 => X"1000" or X"00B5",
127 => X"1000" or X"00B6",
128 => X"1000" or X"00B7",
129 => X"1000" or X"00B8",
130 => X"1000" or X"00B9",
131 => X"1000" or X"00BA",
132 => X"1000" or X"00BB",
133 => X"1000" or X"00BC",
134 => X"1000" or X"00BD",
135 => X"1000" or X"00BE",
136 => X"1000" or X"00C0",
137 => X"1000" or X"00C1",
138 => X"1000" or X"00C2",
139 => X"1000" or X"00C3",
140 => X"1000" or X"00C4",
141 => X"1000" or X"00C6",
142 => X"1000" or X"00C7",
143 => X"1000" or X"00C8",
144 => X"1000" or X"00C9",
145 => X"1000" or X"00CB",
146 => X"1000" or X"00CC",
147 => X"1000" or X"00CD",
148 => X"1000" or X"00CF",
149 => X"1000" or X"00D0",
150 => X"1000" or X"00D1",
151 => X"1000" or X"00D3",
152 => X"1000" or X"00D4",
153 => X"1000" or X"00D6",
154 => X"1000" or X"00D7",
155 => X"1000" or X"00D8",
156 => X"1000" or X"00DA",
157 => X"1000" or X"00DB",
158 => X"1000" or X"00DD",
159 => X"1000" or X"00DE",
160 => X"1000" or X"00E0",
161 => X"1000" or X"00E1",
162 => X"1000" or X"00E3",
163 => X"1000" or X"00E5",
164 => X"1000" or X"00E6",
165 => X"1000" or X"00E8",
166 => X"1000" or X"00E9",
167 => X"1000" or X"00EB",
168 => X"1000" or X"00EC",
169 => X"1000" or X"00EE",
170 => X"1000" or X"00F0",
171 => X"1000" or X"00F1",
172 => X"1000" or X"00F3",
173 => X"1000" or X"00F5",
174 => X"1000" or X"00F6",
175 => X"1000" or X"00F8",
176 => X"1000" or X"00FA",
177 => X"1000" or X"00FB",
178 => X"1000" or X"00FD",
179 => X"1000" or X"00FF",
180 => X"1000" or X"0100",
181 => X"1000" or X"0102",
182 => X"1000" or X"0104",
183 => X"1000" or X"0105",
184 => X"1000" or X"0107",
185 => X"1000" or X"0109",
186 => X"1000" or X"010B",
187 => X"1000" or X"010C",
188 => X"1000" or X"010E",
189 => X"1000" or X"0110",
190 => X"1000" or X"0111",
191 => X"1000" or X"0113",
192 => X"1000" or X"0115",
193 => X"1000" or X"0117",
194 => X"1000" or X"0118",
195 => X"1000" or X"011A",
196 => X"1000" or X"011C",
197 => X"1000" or X"011E",
198 => X"1000" or X"011F",
199 => X"1000" or X"0121",
200 => X"1000" or X"0123",
201 => X"1000" or X"0125",
202 => X"1000" or X"0126",
203 => X"1000" or X"0128",
204 => X"1000" or X"012A",
205 => X"1000" or X"012C",
206 => X"1000" or X"012D",
207 => X"1000" or X"012F",
208 => X"1000" or X"0131",
209 => X"1000" or X"0132",
210 => X"1000" or X"0134",
211 => X"1000" or X"0136",
212 => X"1000" or X"0138",
213 => X"1000" or X"0139",
214 => X"1000" or X"013B",
215 => X"1000" or X"013D",
216 => X"1000" or X"013E",
217 => X"1000" or X"0140",
218 => X"1000" or X"0142",
219 => X"1000" or X"0143",
220 => X"1000" or X"0145",
221 => X"1000" or X"0147",
222 => X"1000" or X"0148",
223 => X"1000" or X"014A",
224 => X"1000" or X"014B",
225 => X"1000" or X"014D",
226 => X"1000" or X"014F",
227 => X"1000" or X"0150",
228 => X"1000" or X"0152",
229 => X"1000" or X"0153",
230 => X"1000" or X"0155",
231 => X"1000" or X"0156",
232 => X"1000" or X"0158",
233 => X"1000" or X"0159",
234 => X"1000" or X"015B",
235 => X"1000" or X"015C",
236 => X"1000" or X"015E",
237 => X"1000" or X"015F",
238 => X"1000" or X"0161",
239 => X"1000" or X"0162",
240 => X"1000" or X"0163",
241 => X"1000" or X"0165",
242 => X"1000" or X"0166",
243 => X"1000" or X"0167",
244 => X"1000" or X"0169",
245 => X"1000" or X"016A",
246 => X"1000" or X"016B",
247 => X"1000" or X"016D",
248 => X"1000" or X"016E",
249 => X"1000" or X"016F",
250 => X"1000" or X"0170",
251 => X"1000" or X"0171",
252 => X"1000" or X"0173",
253 => X"1000" or X"0174",
254 => X"1000" or X"0175",
255 => X"1000" or X"0176",
256 => X"1000" or X"0177",
257 => X"1000" or X"0178",
258 => X"1000" or X"0179",
259 => X"1000" or X"017A",
260 => X"1000" or X"017B",
261 => X"1000" or X"017C",
262 => X"1000" or X"017D",
263 => X"1000" or X"017E",
264 => X"1000" or X"017F",
265 => X"1000" or X"0180",
266 => X"1000" or X"0181",
267 => X"1000" or X"0182",
268 => X"1000" or X"0183",
269 => X"1000" or X"0183",
270 => X"1000" or X"0184",
271 => X"1000" or X"0185",
272 => X"1000" or X"0186",
273 => X"1000" or X"0186",
274 => X"1000" or X"0187",
275 => X"1000" or X"0188",
276 => X"1000" or X"0188",
277 => X"1000" or X"0189",
278 => X"1000" or X"018A",
279 => X"1000" or X"018A",
280 => X"1000" or X"018B",
281 => X"1000" or X"018B",
282 => X"1000" or X"018C",
283 => X"1000" or X"018C",
284 => X"1000" or X"018D",
285 => X"1000" or X"018D",
286 => X"1000" or X"018D",
287 => X"1000" or X"018E",
288 => X"1000" or X"018E",
289 => X"1000" or X"018E",
290 => X"1000" or X"018F",
291 => X"1000" or X"018F",
292 => X"1000" or X"018F",
293 => X"1000" or X"018F",
294 => X"1000" or X"0190",
295 => X"1000" or X"0190",
296 => X"1000" or X"0190",
297 => X"1000" or X"0190",
298 => X"1000" or X"0190",
299 => X"1000" or X"0190",
300 => X"1000" or X"0190",
301 => X"1000" or X"0190",
302 => X"1000" or X"0190",
303 => X"1000" or X"0190",
304 => X"1000" or X"0190",
305 => X"1000" or X"0190",
306 => X"1000" or X"0190",
307 => X"1000" or X"018F",
308 => X"1000" or X"018F",
309 => X"1000" or X"018F",
310 => X"1000" or X"018F",
311 => X"1000" or X"018E",
312 => X"1000" or X"018E",
313 => X"1000" or X"018E",
314 => X"1000" or X"018D",
315 => X"1000" or X"018D",
316 => X"1000" or X"018D",
317 => X"1000" or X"018C",
318 => X"1000" or X"018C",
319 => X"1000" or X"018B",
320 => X"1000" or X"018B",
321 => X"1000" or X"018A",
322 => X"1000" or X"018A",
323 => X"1000" or X"0189",
324 => X"1000" or X"0188",
325 => X"1000" or X"0188",
326 => X"1000" or X"0187",
327 => X"1000" or X"0186",
328 => X"1000" or X"0186",
329 => X"1000" or X"0185",
330 => X"1000" or X"0184",
331 => X"1000" or X"0183",
332 => X"1000" or X"0183",
333 => X"1000" or X"0182",
334 => X"1000" or X"0181",
335 => X"1000" or X"0180",
336 => X"1000" or X"017F",
337 => X"1000" or X"017E",
338 => X"1000" or X"017D",
339 => X"1000" or X"017C",
340 => X"1000" or X"017B",
341 => X"1000" or X"017A",
342 => X"1000" or X"0179",
343 => X"1000" or X"0178",
344 => X"1000" or X"0177",
345 => X"1000" or X"0176",
346 => X"1000" or X"0175",
347 => X"1000" or X"0174",
348 => X"1000" or X"0173",
349 => X"1000" or X"0171",
350 => X"1000" or X"0170",
351 => X"1000" or X"016F",
352 => X"1000" or X"016E",
353 => X"1000" or X"016D",
354 => X"1000" or X"016B",
355 => X"1000" or X"016A",
356 => X"1000" or X"0169",
357 => X"1000" or X"0167",
358 => X"1000" or X"0166",
359 => X"1000" or X"0165",
360 => X"1000" or X"0163",
361 => X"1000" or X"0162",
362 => X"1000" or X"0161",
363 => X"1000" or X"015F",
364 => X"1000" or X"015E",
365 => X"1000" or X"015C",
366 => X"1000" or X"015B",
367 => X"1000" or X"0159",
368 => X"1000" or X"0158",
369 => X"1000" or X"0156",
370 => X"1000" or X"0155",
371 => X"1000" or X"0153",
372 => X"1000" or X"0152",
373 => X"1000" or X"0150",
374 => X"1000" or X"014F",
375 => X"1000" or X"014D",
376 => X"1000" or X"014B",
377 => X"1000" or X"014A",
378 => X"1000" or X"0148",
379 => X"1000" or X"0147",
380 => X"1000" or X"0145",
381 => X"1000" or X"0143",
382 => X"1000" or X"0142",
383 => X"1000" or X"0140",
384 => X"1000" or X"013E",
385 => X"1000" or X"013D",
386 => X"1000" or X"013B",
387 => X"1000" or X"0139",
388 => X"1000" or X"0138",
389 => X"1000" or X"0136",
390 => X"1000" or X"0134",
391 => X"1000" or X"0132",
392 => X"1000" or X"0131",
393 => X"1000" or X"012F",
394 => X"1000" or X"012D",
395 => X"1000" or X"012C",
396 => X"1000" or X"012A",
397 => X"1000" or X"0128",
398 => X"1000" or X"0126",
399 => X"1000" or X"0125",
400 => X"1000" or X"0123",
401 => X"1000" or X"0121",
402 => X"1000" or X"011F",
403 => X"1000" or X"011E",
404 => X"1000" or X"011C",
405 => X"1000" or X"011A",
406 => X"1000" or X"0118",
407 => X"1000" or X"0117",
408 => X"1000" or X"0115",
409 => X"1000" or X"0113",
410 => X"1000" or X"0111",
411 => X"1000" or X"0110",
412 => X"1000" or X"010E",
413 => X"1000" or X"010C",
414 => X"1000" or X"010B",
415 => X"1000" or X"0109",
416 => X"1000" or X"0107",
417 => X"1000" or X"0105",
418 => X"1000" or X"0104",
419 => X"1000" or X"0102",
420 => X"1000" or X"0100",
421 => X"1000" or X"00FF",
422 => X"1000" or X"00FD",
423 => X"1000" or X"00FB",
424 => X"1000" or X"00FA",
425 => X"1000" or X"00F8",
426 => X"1000" or X"00F6",
427 => X"1000" or X"00F5",
428 => X"1000" or X"00F3",
429 => X"1000" or X"00F1",
430 => X"1000" or X"00F0",
431 => X"1000" or X"00EE",
432 => X"1000" or X"00EC",
433 => X"1000" or X"00EB",
434 => X"1000" or X"00E9",
435 => X"1000" or X"00E8",
436 => X"1000" or X"00E6",
437 => X"1000" or X"00E5",
438 => X"1000" or X"00E3",
439 => X"1000" or X"00E1",
440 => X"1000" or X"00E0",
441 => X"1000" or X"00DE",
442 => X"1000" or X"00DD",
443 => X"1000" or X"00DB",
444 => X"1000" or X"00DA",
445 => X"1000" or X"00D8",
446 => X"1000" or X"00D7",
447 => X"1000" or X"00D6",
448 => X"1000" or X"00D4",
449 => X"1000" or X"00D3",
450 => X"1000" or X"00D1",
451 => X"1000" or X"00D0",
452 => X"1000" or X"00CF",
453 => X"1000" or X"00CD",
454 => X"1000" or X"00CC",
455 => X"1000" or X"00CB",
456 => X"1000" or X"00C9",
457 => X"1000" or X"00C8",
458 => X"1000" or X"00C7",
459 => X"1000" or X"00C6",
460 => X"1000" or X"00C4",
461 => X"1000" or X"00C3",
462 => X"1000" or X"00C2",
463 => X"1000" or X"00C1",
464 => X"1000" or X"00C0",
465 => X"1000" or X"00BE",
466 => X"1000" or X"00BD",
467 => X"1000" or X"00BC",
468 => X"1000" or X"00BB",
469 => X"1000" or X"00BA",
470 => X"1000" or X"00B9",
471 => X"1000" or X"00B8",
472 => X"1000" or X"00B7",
473 => X"1000" or X"00B6",
474 => X"1000" or X"00B5",
475 => X"1000" or X"00B4",
476 => X"1000" or X"00B3",
477 => X"1000" or X"00B2",
478 => X"1000" or X"00B1",
479 => X"1000" or X"00B0",
480 => X"1000" or X"00AF",
481 => X"1000" or X"00AF",
482 => X"1000" or X"00AE",
483 => X"1000" or X"00AD",
484 => X"1000" or X"00AC",
485 => X"1000" or X"00AB",
486 => X"1000" or X"00AB",
487 => X"1000" or X"00AA",
488 => X"1000" or X"00A9",
489 => X"1000" or X"00A8",
490 => X"1000" or X"00A8",
491 => X"1000" or X"00A7",
492 => X"1000" or X"00A7",
493 => X"1000" or X"00A6",
494 => X"1000" or X"00A5",
495 => X"1000" or X"00A5",
496 => X"1000" or X"00A4",
497 => X"1000" or X"00A4",
498 => X"1000" or X"00A3",
499 => X"1000" or X"00A3",
500 => X"1000" or X"00A2",
501 => X"1000" or X"00A2",
502 => X"1000" or X"00A1",
503 => X"1000" or X"00A1",
504 => X"1000" or X"00A0",
505 => X"1000" or X"00A0",
506 => X"1000" or X"00A0",
507 => X"1000" or X"009F",
508 => X"1000" or X"009F",
509 => X"1000" or X"009F",
510 => X"1000" or X"009E",
511 => X"1000" or X"009E",
512 => X"1000" or X"009E",
513 => X"1000" or X"009E",
514 => X"1000" or X"009E",
515 => X"1000" or X"009D",
516 => X"1000" or X"009D",
517 => X"1000" or X"009D",
518 => X"1000" or X"009D",
519 => X"1000" or X"009D",
520 => X"1000" or X"009D",
521 => X"1000" or X"009D",
522 => X"1000" or X"009D",
523 => X"1000" or X"009D",
524 => X"1000" or X"009D",
525 => X"1000" or X"009D",
526 => X"1000" or X"009D",
527 => X"1000" or X"009D",
528 => X"1000" or X"009D",
529 => X"1000" or X"009D",
530 => X"1000" or X"009D",
531 => X"1000" or X"009D",
532 => X"1000" or X"009D",
533 => X"1000" or X"009D",
534 => X"1000" or X"009D",
535 => X"1000" or X"009D",
536 => X"1000" or X"009E",
537 => X"1000" or X"009E",
538 => X"1000" or X"009E",
539 => X"1000" or X"009E",
540 => X"1000" or X"009E",
541 => X"1000" or X"009F",
542 => X"1000" or X"009F",
543 => X"1000" or X"009F",
544 => X"1000" or X"00A0",
545 => X"1000" or X"00A0",
546 => X"1000" or X"00A0",
547 => X"1000" or X"00A1",
548 => X"1000" or X"00A1",
549 => X"1000" or X"00A1",
550 => X"1000" or X"00A2",
551 => X"1000" or X"00A2",
552 => X"1000" or X"00A2",
553 => X"1000" or X"00A3",
554 => X"1000" or X"00A3",
555 => X"1000" or X"00A4",
556 => X"1000" or X"00A4",
557 => X"1000" or X"00A5",
558 => X"1000" or X"00A5",
559 => X"1000" or X"00A6",
560 => X"1000" or X"00A6",
561 => X"1000" or X"00A7",
562 => X"1000" or X"00A7",
563 => X"1000" or X"00A8",
564 => X"1000" or X"00A8",
565 => X"1000" or X"00A9",
566 => X"1000" or X"00A9",
567 => X"1000" or X"00AA",
568 => X"1000" or X"00AA",
569 => X"1000" or X"00AB",
570 => X"1000" or X"00AB",
571 => X"1000" or X"00AC",
572 => X"1000" or X"00AD",
573 => X"1000" or X"00AD",
574 => X"1000" or X"00AE",
575 => X"1000" or X"00AE",
576 => X"1000" or X"00AF",
577 => X"1000" or X"00B0",
578 => X"1000" or X"00B0",
579 => X"1000" or X"00B1",
580 => X"1000" or X"00B1",
581 => X"1000" or X"00B2",
582 => X"1000" or X"00B3",
583 => X"1000" or X"00B3",
584 => X"1000" or X"00B4",
585 => X"1000" or X"00B5",
586 => X"1000" or X"00B5",
587 => X"1000" or X"00B6",
588 => X"1000" or X"00B7",
589 => X"1000" or X"00B7",
590 => X"1000" or X"00B8",
591 => X"1000" or X"00B9",
592 => X"1000" or X"00B9",
593 => X"1000" or X"00BA",
594 => X"1000" or X"00BB",
595 => X"1000" or X"00BB",
596 => X"1000" or X"00BC",
597 => X"1000" or X"00BD",
598 => X"1000" or X"00BD",
599 => X"1000" or X"00BE",
600 => X"1000" or X"00BF",
601 => X"1000" or X"00BF",
602 => X"1000" or X"00C0",
603 => X"1000" or X"00C1",
604 => X"1000" or X"00C1",
605 => X"1000" or X"00C2",
606 => X"1000" or X"00C3",
607 => X"1000" or X"00C3",
608 => X"1000" or X"00C4",
609 => X"1000" or X"00C5",
610 => X"1000" or X"00C5",
611 => X"1000" or X"00C6",
612 => X"1000" or X"00C7",
613 => X"1000" or X"00C7",
614 => X"1000" or X"00C8",
615 => X"1000" or X"00C9",
616 => X"1000" or X"00C9",
617 => X"1000" or X"00CA",
618 => X"1000" or X"00CA",
619 => X"1000" or X"00CB",
620 => X"1000" or X"00CC",
621 => X"1000" or X"00CC",
622 => X"1000" or X"00CD",
623 => X"1000" or X"00CD",
624 => X"1000" or X"00CE",
625 => X"1000" or X"00CF",
626 => X"1000" or X"00CF",
627 => X"1000" or X"00D0",
628 => X"1000" or X"00D0",
629 => X"1000" or X"00D1",
630 => X"1000" or X"00D1",
631 => X"1000" or X"00D2",
632 => X"1000" or X"00D3",
633 => X"1000" or X"00D3",
634 => X"1000" or X"00D4",
635 => X"1000" or X"00D4",
636 => X"1000" or X"00D5",
637 => X"1000" or X"00D5",
638 => X"1000" or X"00D6",
639 => X"1000" or X"00D6",
640 => X"1000" or X"00D7",
641 => X"1000" or X"00D7",
642 => X"1000" or X"00D7",
643 => X"1000" or X"00D8",
644 => X"1000" or X"00D8",
645 => X"1000" or X"00D9",
646 => X"1000" or X"00D9",
647 => X"1000" or X"00DA",
648 => X"1000" or X"00DA",
649 => X"1000" or X"00DA",
650 => X"1000" or X"00DB",
651 => X"1000" or X"00DB",
652 => X"1000" or X"00DC",
653 => X"1000" or X"00DC",
654 => X"1000" or X"00DC",
655 => X"1000" or X"00DD",
656 => X"1000" or X"00DD",
657 => X"1000" or X"00DD",
658 => X"1000" or X"00DD",
659 => X"1000" or X"00DE",
660 => X"1000" or X"00DE",
661 => X"1000" or X"00DE",
662 => X"1000" or X"00DF",
663 => X"1000" or X"00DF",
664 => X"1000" or X"00DF",
665 => X"1000" or X"00DF",
666 => X"1000" or X"00E0",
667 => X"1000" or X"00E0",
668 => X"1000" or X"00E0",
669 => X"1000" or X"00E0",
670 => X"1000" or X"00E0",
671 => X"1000" or X"00E0",
672 => X"1000" or X"00E1",
673 => X"1000" or X"00E1",
674 => X"1000" or X"00E1",
675 => X"1000" or X"00E1",
676 => X"1000" or X"00E1",
677 => X"1000" or X"00E1",
678 => X"1000" or X"00E1",
679 => X"1000" or X"00E1",
680 => X"1000" or X"00E1",
681 => X"1000" or X"00E2",
682 => X"1000" or X"00E2",
683 => X"1000" or X"00E2",
684 => X"1000" or X"00E2",
685 => X"1000" or X"00E2",
686 => X"1000" or X"00E2",
687 => X"1000" or X"00E2",
688 => X"1000" or X"00E2",
689 => X"1000" or X"00E2",
690 => X"1000" or X"00E2",
691 => X"1000" or X"00E2",
692 => X"1000" or X"00E2",
693 => X"1000" or X"00E1",
694 => X"1000" or X"00E1",
695 => X"1000" or X"00E1",
696 => X"1000" or X"00E1",
697 => X"1000" or X"00E1",
698 => X"1000" or X"00E1",
699 => X"1000" or X"00E1",
700 => X"1000" or X"00E1",
701 => X"1000" or X"00E1",
702 => X"1000" or X"00E0",
703 => X"1000" or X"00E0",
704 => X"1000" or X"00E0",
705 => X"1000" or X"00E0",
706 => X"1000" or X"00E0",
707 => X"1000" or X"00E0",
708 => X"1000" or X"00DF",
709 => X"1000" or X"00DF",
710 => X"1000" or X"00DF",
711 => X"1000" or X"00DF",
712 => X"1000" or X"00DE",
713 => X"1000" or X"00DE",
714 => X"1000" or X"00DE",
715 => X"1000" or X"00DE",
716 => X"1000" or X"00DD",
717 => X"1000" or X"00DD",
718 => X"1000" or X"00DD",
719 => X"1000" or X"00DD",
720 => X"1000" or X"00DC",
721 => X"1000" or X"00DC",
722 => X"1000" or X"00DC",
723 => X"1000" or X"00DB",
724 => X"1000" or X"00DB",
725 => X"1000" or X"00DB",
726 => X"1000" or X"00DA",
727 => X"1000" or X"00DA",
728 => X"1000" or X"00DA",
729 => X"1000" or X"00D9",
730 => X"1000" or X"00D9",
731 => X"1000" or X"00D9",
732 => X"1000" or X"00D8",
733 => X"1000" or X"00D8",
734 => X"1000" or X"00D8",
735 => X"1000" or X"00D7",
736 => X"1000" or X"00D7",
737 => X"1000" or X"00D6",
738 => X"1000" or X"00D6",
739 => X"1000" or X"00D6",
740 => X"1000" or X"00D5",
741 => X"1000" or X"00D5",
742 => X"1000" or X"00D4",
743 => X"1000" or X"00D4",
744 => X"1000" or X"00D4",
745 => X"1000" or X"00D3",
746 => X"1000" or X"00D3",
747 => X"1000" or X"00D2",
748 => X"1000" or X"00D2",
749 => X"1000" or X"00D2",
750 => X"1000" or X"00D1",
751 => X"1000" or X"00D1",
752 => X"1000" or X"00D0",
753 => X"1000" or X"00D0",
754 => X"1000" or X"00CF",
755 => X"1000" or X"00CF",
756 => X"1000" or X"00CF",
757 => X"1000" or X"00CE",
758 => X"1000" or X"00CE",
759 => X"1000" or X"00CD",
760 => X"1000" or X"00CD",
761 => X"1000" or X"00CC",
762 => X"1000" or X"00CC",
763 => X"1000" or X"00CC",
764 => X"1000" or X"00CB",
765 => X"1000" or X"00CB",
766 => X"1000" or X"00CA",
767 => X"1000" or X"00CA",
768 => X"1000" or X"00C9",
769 => X"1000" or X"00C9",
770 => X"1000" or X"00C9",
771 => X"1000" or X"00C8",
772 => X"1000" or X"00C8",
773 => X"1000" or X"00C7",
774 => X"1000" or X"00C7",
775 => X"1000" or X"00C6",
776 => X"1000" or X"00C6",
777 => X"1000" or X"00C6",
778 => X"1000" or X"00C5",
779 => X"1000" or X"00C5",
780 => X"1000" or X"00C4",
781 => X"1000" or X"00C4",
782 => X"1000" or X"00C4",
783 => X"1000" or X"00C3",
784 => X"1000" or X"00C3",
785 => X"1000" or X"00C2",
786 => X"1000" or X"00C2",
787 => X"1000" or X"00C2",
788 => X"1000" or X"00C1",
789 => X"1000" or X"00C1",
790 => X"1000" or X"00C1",
791 => X"1000" or X"00C0",
792 => X"1000" or X"00C0",
793 => X"1000" or X"00BF",
794 => X"1000" or X"00BF",
795 => X"1000" or X"00BF",
796 => X"1000" or X"00BE",
797 => X"1000" or X"00BE",
798 => X"1000" or X"00BE",
799 => X"1000" or X"00BD",
800 => X"1000" or X"00BD",
others => X"1000" or X"0064"
);
begin
-- wave form or video-line memory
-- |------| |-------------------------------------------|
-- | P P | | D D D | D D D | D D D D D D D D D D |
-- |======| |===========================================|
-- |17 16 | | 15 14 13 | 12 11 10 | 9 8 7 6 5 4 3 2 1 0 |
-- |======| |===========================================|
-- | Free | | Reserv. | R G B | vert. pos. |
-- |------| |-------------------------------------------|
--
p_rw0_port : process (i_clockA)
begin
if rising_edge(i_clockA) then
if (true) then
if (i_WEA = '1') then
v_ram(conv_integer(i_ADDRA)) := i_DIA;
end if;
--o_DOA <= v_ram(conv_integer(i_ADDRA));
end if;
end if;
end process;
p_rw1_port : process (i_clockB)
begin
if rising_edge(i_clockB) then
if (true) then
o_DOB <= v_ram(conv_integer(i_ADDRB));
if (i_WEB = '1') then
v_ram(conv_integer(i_ADDRB)) := i_DIB;
end if;
end if;
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
5cda9fecb5feabe8f5d07f11fb52cc77
| 0.432964 | 2.647036 | false | false | false | false |
LemurPwned/classic-fpga
|
dff_tb.vhdl
| 1 | 767 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff_tb is
end entity;
architecture testbench of dff_tb is
component dff
port (
clk : in std_logic;
r : in std_logic;
D : in std_logic;
Q : out std_logic
);
end component;
signal clk, D : std_logic;
signal r : std_logic := '0';
signal Q : std_logic := '0';
for dff_0: dff use entity work.dff;
begin
dff_0 : dff port map (clk=>clk, r=>r, D=>D, Q=>Q);
process
begin
clk <='0';
wait for 5 ns;
clk <='1';
wait for 5 ns;
end process;
process
begin
D<='0';
wait for 10 ns;
D<='1';
r<='1';
wait for 10 ns;
D<='0';
r<='1';
wait for 10 ns;
D<='1';
r<='0';
wait;
end process;
end architecture;
|
gpl-3.0
|
1c4c730687adea2e49bcd14b1b92f6d2
| 0.554107 | 2.938697 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/barrel_tb.vhdl
| 1 | 991 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity barrel_tb is
end entity;
architecture barrel_tb of barrel_tb is
component barrel is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
I : in std_logic_vector(3 downto 0);
Q,Q2 : out std_logic_vector(3 downto 0)
);
end component;
for barrel_0 : barrel use entity work.barrel;
signal clk : std_logic :='1';
signal se : std_logic_vector(1 downto 0);
signal Q,Q2,I : std_logic_vector(3 downto 0);
constant period : time := 10 ns;
begin
barrel_0: barrel port map(clk=>clk, se=>se, I=>I, Q=>Q, Q2=>Q2);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc:
process
begin
I<="1001";
se<="00";
wait for 20 ns;
se<="01";
wait for 20 ns;
se<="10";
wait for 20 ns;
se<="11";
wait for 20 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
5ec716182fc1787305f47762a94719ef
| 0.592331 | 3.186495 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/sipo.vhdl
| 1 | 645 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
D : in std_logic_vector(3 downto 0);
Dl, Dr : in std_logic;
Q : out std_logic_vector(3 downto 0) :="0000"
);
end entity;
architecture behav of sipo is
signal Qt : std_logic_vector(3 downto 0) :="0000";
begin
process(clk, se)
begin
if rising_edge(clk) then
if se(0) = '0' then
Qt<=Dl&Qt(3 downto 1);
elsif se(1) = '1' then
Qt<=Qt(2 downto 0)&Dr;
else
Qt<=D;
end if;
end if;
end process;
Q<=Qt;
end architecture;
|
gpl-3.0
|
d361f01737992c44ba5e38b3677007f1
| 0.60155 | 2.905405 | false | false | false | false |
LemurPwned/classic-fpga
|
encoders/grey_tb.vhdl
| 1 | 611 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity grey_tb is
end entity;
architecture behav of grey_tb is
component grey is
port (
si : in std_logic_vector(2 downto 0);
so : out std_logic_vector(2 downto 0)
);
end component;
for grey_0 : grey use entity work.grey;
signal si, so : std_logic_vector(2 downto 0);
begin
grey_0: grey port map(si=>si, so=>so);
process
begin
si<="000";
wait for 5 ns;
si<="010";
wait for 5 ns;
si<="100";
wait for 5 ns;
si<="110";
wait for 5 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
d86bfe654503ec3372a7ff6bba464014
| 0.618658 | 3.133333 | false | false | false | false |
14bmkelley/Environmental-Mouse
|
nas_counter.vhdl
| 1 | 2,621 |
----------------------------------------------------------------------------------
-- Team: The Team Formally Known as Queen
-- Engineers: Brandon Kelley, Ignacio DeAnquin, Alan Nonaka and Anthony Velasquez
--
-- Create Date: December 3, 2015
-- Design Name: Environmental Mouse
-- Module Name: nas_counter.vhdl
-- Project Name: Environmental Mouse
-- Target Devices: Basys 3
-- Tool versions: Vivado 14.4
-- Description: This module controls the power of a PS/2 mouse, shutting it off
-- if it is found to be inactive.
-- Dependencies:
-- Hardware:
-- * Computer with Vivado software
-- * Basys 3 circuit board
-- * PS/2 mouse
-- * Jumper wires
-- * LEDs and resistors
-- * NPN Transistor
-- Software:
-- * Clock frequency divider
-- Version: 1.0.0
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Power checker port description
entity nas_counter is
port (
nas_data : in std_logic; -- Data used to reset counter
nas_clk : in std_logic; -- Clock used to keep processes in time
nas_btn : in std_logic; -- Button used to reset counter
nas_red : out std_logic; -- Signal used to show mouse is in off state
nas_yellow : out std_logic; -- Signal used to show mouse is in waiting state
nas_green : out std_logic -- Signal used to show mouse is in on state
);
end nas_counter;
-- Power checker architecture description
architecture nas_arch of nas_counter is
-- Signal used to track the state of the mouse
signal counter : integer := 0;
begin
-- Start the checker
check : process (nas_data, nas_clk, counter) begin
-- Only check on clock signal to keep time
if rising_edge(nas_clk) then
-- Reset counter if there is mouse data or the button is pressed
if nas_data = '0' or nas_btn = '1' then
counter <= 0;
-- Otherwise, increment counter
else
counter <= counter + 1;
end if;
end if;
-- Check for off state
if counter > 100000 then
nas_red <= '1';
else
nas_red <= '0';
end if;
-- Check for waiting state
if (counter < 100000) and (counter > 1000) then -- yellow
nas_yellow <= '1';
else
nas_yellow <= '0';
end if;
-- Check for on state
if (counter < 1000) then
nas_green <= '1';
else
nas_green <= '0';
end if;
end process check;
end nas_arch;
|
gpl-2.0
|
28f2d660213ebe95c8a35e6761382d2e
| 0.55475 | 4.1406 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/trans.vhdl
| 1 | 737 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity trans is
port (
A: in std_logic_vector (3 downto 0);
clk : in std_logic;
se : in std_logic;
C: out std_logic_vector(3 downto 0);
sum : out std_logic_vector(2 downto 0)
);
end entity;
architecture behav of trans is
signal a1,o: std_logic_vector(3 downto 0) := "0000";
signal ci: std_logic_vector(2 downto 0) :="000";
begin
process(clk)
begin
if rising_edge(clk) then
if se='1' then
a1<= A;
else
if a1(0) = '1' then
ci<=ci+1;
end if;
a1<= '0'&a1(3 downto 1);
o<=a1(0)&o(3 downto 1);
end if;
end if;
end process;
sum<=ci;
C<=o;
end architecture;
|
gpl-3.0
|
ed2da6964881d271f8ffe715deaab4a6
| 0.578019 | 2.890196 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/show_controller.vhd
| 1 | 9,056 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 01:28:25 03/22/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: show_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity show_controller is
generic(
addr_width : integer := 5; -- log2(number of regs)
reg_width : integer := 32 -- width of a reg
);
port(
clk : in std_logic;
reset : in std_logic;
up : in std_logic;
down : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
--get_data : in std_logic;
fifo_wr : out std_logic;
rf_addr : out std_logic_vector(addr_width - 1 downto 0);
show_dout : out std_logic_vector(7 downto 0);
data_count : out std_logic_vector(5 downto 0);
show_data : out std_logic
);
end show_controller;
architecture Behavioral of show_controller is
type t_state is (init, idle, take_data, send_data);
signal state, state_next : t_state;
signal reg_cnt, reg_cnt_next : integer range 0 to 31;
signal data_cnt, data_cnt_next : integer range 0 to 10;
signal delay, delay_next : integer range 0 to 200000000;
signal dout, dout_next : std_logic_vector(7 downto 0);
signal addr, addr_next : std_logic_vector(4 downto 0);
signal show, show_next : std_logic;
signal wr_en, wr_en_next : std_logic;
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= init;
reg_cnt <= 0;
delay <= 1;
data_cnt <= 0;
dout <= (others => '0');
addr <= (others => '0');
show <= '0';
wr_en <= '0';
else
state <= state_next;
reg_cnt <= reg_cnt_next;
delay <= delay_next;
data_cnt <= data_cnt_next;
dout <= dout_next;
addr <= addr_next;
show <= show_next;
wr_en <= wr_en_next;
end if;
end if;
end process;
routing : process (state, delay, reg_cnt, data_cnt, dout, rf_data, addr, show, up, down, wr_en)
begin
state_next <= state;
reg_cnt_next <= reg_cnt;
delay_next <= delay;
data_cnt_next <= data_cnt;
dout_next <= dout;
addr_next <= addr;
show_next <= show;
wr_en_next <= wr_en;
case state is
when init =>
if delay = 200000000 then
state_next <= take_data;
delay_next <= 0;
else
delay_next <= delay + 1;
end if;
when take_data =>
if delay = 150000 then
delay_next <= 0;
state_next <= send_data;
--show_next <= '1';
elsif delay = 0 then
addr_next <= std_logic_vector(to_unsigned(reg_cnt, addr_width));
delay_next <= delay + 1;
else
delay_next <= delay + 1;
end if;
when send_data =>
--show_next <= '0';
case data_cnt is
when 0 =>
dout_next <= "01010010";
wr_en_next <= '1';
data_cnt_next <= 1;
when 1 =>
dout_next <= "01000101";
wr_en_next <= '1';
data_cnt_next <= 2;
when 2 =>
dout_next <= "01000111";
wr_en_next <= '1';
data_cnt_next <= 3;
when 3 =>
case reg_cnt is
when 0|1|2|3|4|5|6|7|8|9 =>
dout_next <= "00110000";
when 10|11|12|13|14|15|16|17|18|19 =>
dout_next <= "00110001";
when 20|21|22|23|24|25|26|27|28|29 =>
dout_next <= "00110010";
when 30|31 =>
dout_next <= "00110011";
end case;
wr_en_next <= '1';
data_cnt_next <= 4;
when 4 =>
case reg_cnt is
when 0|10|20|30 =>
dout_next <= "00110000";
when 1|11|21|31 =>
dout_next <= "00110001";
when 2|12|22 =>
dout_next <= "00110010";
when 3|13|23 =>
dout_next <= "00110011";
when 4|14|24 =>
dout_next <= "00110100";
when 5|15|25 =>
dout_next <= "00110101";
when 6|16|26 =>
dout_next <= "00110110";
when 7|17|27 =>
dout_next <= "00110111";
when 8|18|28 =>
dout_next <= "00111000";
when 9|19|29 =>
dout_next <= "00111001";
end case;
wr_en_next <= '1';
data_cnt_next <= 5;
when 5 =>
dout_next <= "00111010";
wr_en_next <= '1';
data_cnt_next <= 6;
when 6 =>
--if get_data = '1' then
case rf_data(15 downto 12) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
wr_en_next <= '1';
data_cnt_next <= 7;
--end if;
when 7 =>
--if get_data = '1' then
case rf_data(11 downto 8) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
data_cnt_next <= 8;
wr_en_next <= '1';
--end if;
when 8 =>
--if get_data = '1' then
case rf_data(7 downto 4) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
wr_en_next <= '1';
data_cnt_next <= 9;
--end if;
when 9 =>
--if get_data = '1' then
case rf_data(3 downto 0) is
when "0000" => dout_next <= "00110000"; -- 30
when "0001" => dout_next <= "00110001";
when "0010" => dout_next <= "00110010";
when "0011" => dout_next <= "00110011";
when "0100" => dout_next <= "00110100";
when "0101" => dout_next <= "00110101";
when "0110" => dout_next <= "00110110";
when "0111" => dout_next <= "00110111";
when "1000" => dout_next <= "00111000";
when "1001" => dout_next <= "00111001"; -- 39
when "1010" => dout_next <= "01000001"; -- 41
when "1011" => dout_next <= "01000010";
when "1100" => dout_next <= "01000011";
when "1101" => dout_next <= "01000100";
when "1110" => dout_next <= "01000101";
when "1111" => dout_next <= "01000110"; -- 46
when others => dout_next <= "01011111"; -- _
end case;
wr_en_next <= '1';
data_cnt_next <= 10;
when 10 =>
--wr_en_next <= '1';
data_cnt_next <= 0;
state_next <= idle;
show_next <= '1';
--end if;
end case;
when idle =>
show_next <= '0';
wr_en_next <= '0';
if up = '1' then
state_next <= take_data;
if reg_cnt = 31 then
reg_cnt_next <= 0;
else
reg_cnt_next <= reg_cnt + 1;
end if;
elsif down = '1' then
state_next <= take_data;
if reg_cnt = 0 then
reg_cnt_next <= 31;
else
reg_cnt_next <= reg_cnt - 1;
end if;
end if;
end case;
end process;
show_data <= show;
show_dout <= dout;
rf_addr <= addr;
data_count <= "001010";
fifo_wr <= wr_en;
end Behavioral;
|
mit
|
f9b0ce4a7087a51779e39962c056ccc7
| 0.511374 | 3.067751 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/multi_oc.vhdl
| 1 | 709 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multi_oc is
port (
si : in std_logic_vector (3 downto 0);
se : in std_logic_vector (1 downto 0);
so : out std_logic
);
end entity;
architecture behav of multi_oc is
signal s0, s1, s2, s3 : std_logic;
signal sen : std_logic_vector(1 downto 0);
begin
sen <= not se;
s0 <= 'X' when (sen(0)='1' and sen(1)='1' and si(0) = '1') else '0';
s1 <= 'X' when (se(0)='1' and sen(1)='1' and si(2) = '1') else '0';
s2 <= 'X' when (sen(0)='1' and se(1)='1' and si(2) = '1') else '0';
s3 <= 'X' when (se(0)='1' and se(1)='1' and si(3) = '1') else '0';
so <= s0;
so <= s1;
s0 <= s2;
s0 <= s3;
end architecture;
|
gpl-3.0
|
4eec2395aba3fde00b20a59f2a9a52ec
| 0.557123 | 2.387205 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/top.vhd
| 1 | 12,164 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 21:50:03 03/21/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: top - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.std_logic_arith.all;
entity top is
generic(
reg_num : integer := 32; -- number of registers in register field
reg_width : integer := 16; -- register width in register field
baud_rate : integer := 19200;
data_bits : integer := 8; -- fifo is 8 bit, but a new one can be generated
stop_bits : real := 1.0
);
port(
clk : in std_logic;
reset : in std_logic;
rx : in std_logic;
tx : out std_logic ;
rot_a : in std_logic;
rot_b : in std_logic;
sw0 : in std_logic;
sw1 : in std_logic;
sw2 : in std_logic;
sw3 : in std_logic;
lcd_dout : out std_logic_vector(3 downto 0);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
renew_reg : in std_logic;
led : out std_logic_vector(7 downto 0)
);
end top;
architecture Behavioral of top is
component rate_generator is
generic(
dvsr : integer := 2604
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : out std_logic
);
end component;
component uart_rx is
generic(
dbits : integer := 8;
sb_ticks : integer := 16 -- 16 for 1 stop bit, 24 for 1.5, 32 for 2
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : in std_logic;
rx: in std_logic;
rx_data : out std_logic_vector((dbits-1) downto 0);
rx_done : out std_logic
);
end component;
component uart_tx is
generic(
dbits : integer := 8;
sb_ticks : integer := 16 -- 16 for 1 stop bit, 24 for 1.5, 32 for 2
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : in std_logic;
tx_start : in std_logic;
tx_data : in std_logic_vector((dbits-1) downto 0);
tx_done : out std_logic;
tx : out std_logic
);
end component;
COMPONENT fifo_rx
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_tx
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_uart IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_uart_long IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_uart_long3 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_uart_long_w_outp IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
component disp_controller
port(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(7 downto 0);
data_count : in std_logic_vector(5 downto 0);
show_data : in std_logic;
get_data_o : out std_logic;
dout : out std_logic_vector(3 downto 0);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic
);
end component;
component reg_file_controller is
generic(
reg_num : integer := 32;
reg_width : integer := 32;
rf_addr_w : integer := 5;
data_bits : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
rx_din : in std_logic_vector(data_bits - 1 downto 0);
renew : in std_logic;
rx_req : out std_logic;
tx_req : out std_logic;
rf_req : out std_logic;
tx_dout : out std_logic_vector(data_bits - 1 downto 0);
rf_dout : out std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0)
);
end component;
component register_file is
generic(
addr_width : integer := 5; -- log2(number of regs)
reg_width : integer := 32 -- width of a reg
);
port(
clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
wr_addr : in std_logic_vector(addr_width - 1 downto 0);
wr_data : in std_logic_vector(reg_width - 1 downto 0);
rd_addr : in std_logic_vector(addr_width - 1 downto 0);
rd_data : out std_logic_vector(reg_width - 1 downto 0);
rd_addr_2 : in std_logic_vector(addr_width - 1 downto 0);
rd_data_2 : out std_logic_vector(reg_width - 1 downto 0);
rd_addr_3 : in std_logic_vector(addr_width - 1 downto 0);
rd_data_3 : out std_logic_vector(reg_width - 1 downto 0)
);
end component;
component show_controller is
generic(
addr_width : integer := 5; -- log2(number of regs)
reg_width : integer := 32 -- width of a reg
);
port(
clk : in std_logic;
reset : in std_logic;
up : in std_logic;
down : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
fifo_wr : out std_logic;
rf_addr : out std_logic_vector(addr_width - 1 downto 0);
show_dout : out std_logic_vector(7 downto 0);
data_count : out std_logic_vector(5 downto 0);
show_data : out std_logic
);
end component;
component show_fifo_wide IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component rotary is
port(
clk : in std_logic;
rot_a : in std_logic;
rot_b : in std_logic;
up : out std_logic;
down : out std_logic
);
end component;
component switch_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
sw0 : in std_logic;
sw1 : in std_logic;
sw2 : in std_logic;
sw3 : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end component;
component led_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end component;
attribute box_type : string;
attribute box_type of fifo_uart_long : component is "black_box";
attribute box_type of fifo_uart_long3 : component is "black_box";
attribute box_type of show_fifo_wide : component is "black_box";
constant dvsr : integer := integer(round(real(50000000/(baud_rate*16))));
constant stop_bit_ticks : integer := integer(stop_bits*16.0);
constant rf_addr_w : integer := integer(ceil(log2(real(reg_num))));
signal b_edge : std_logic;
signal rx_data : std_logic_vector((data_bits-1) downto 0);
signal tx_data : std_logic_vector((data_bits-1) downto 0);
signal rx_done : std_logic;
signal tx_done : std_logic;
signal got_data : std_logic_vector(7 downto 0);
signal to_send_data : std_logic_vector(7 downto 0);
signal get_data : std_logic;
signal send_data : std_logic;
signal rx_full : std_logic;
signal tx_full : std_logic;
signal rx_empty : std_logic;
signal inv_in : std_logic;
signal inv_out : std_logic;
signal inv2_in : std_logic;
signal inv2_out : std_logic;
signal wr_rf : std_logic;
signal rf_wr_data : std_logic_vector(reg_width - 1 downto 0);
signal rf_wr_addr : std_logic_vector(rf_addr_w - 1 downto 0);
signal rf_rd_data : std_logic_vector(reg_width - 1 downto 0);
signal rf_rd_addr : std_logic_vector(rf_addr_w - 1 downto 0);
signal rf_rd_data2 : std_logic_vector(reg_width - 1 downto 0);
signal rf_rd_addr2 : std_logic_vector(rf_addr_w - 1 downto 0);
signal rf_rd_data3 : std_logic_vector(reg_width - 1 downto 0);
signal rf_rd_addr3 : std_logic_vector(rf_addr_w - 1 downto 0);
signal up : std_logic;
signal down : std_logic;
signal sh_ctrl_data : std_logic_vector(7 downto 0);
signal show_data : std_logic;
signal sh_get_data : std_logic;
signal data_count : std_logic_vector(5 downto 0);
signal show_wr_en : std_logic;
signal sh_ctrl_dout : std_logic_vector(7 downto 0);
signal show_full : std_logic;
signal show_empty : std_logic;
begin
inv_out <= not inv_in;
rate_gen_unit : rate_generator
generic map(dvsr => dvsr)
port map(clk => clk, reset => reset, b_edge => b_edge);
uart_rx_unit : uart_rx
generic map(dbits => data_bits, sb_ticks => stop_bit_ticks)
port map(clk => clk, reset => reset, b_edge => b_edge, rx => rx, rx_data => rx_data, rx_done => rx_done);
uart_tx_unit : uart_tx
generic map(dbits => data_bits, sb_ticks => stop_bit_ticks)
port map(clk => clk, reset => reset, b_edge => b_edge, tx_start => inv_out, tx_data => tx_data, tx_done => tx_done, tx => tx);
uart_rx_fifo : fifo_uart_long
port map(clk => clk, rst => reset, din => rx_data, wr_en => rx_done, rd_en => get_data, dout => got_data,
full => rx_full, empty => rx_empty);
uart_tx_fifo : fifo_uart_long3
port map(clk => clk, rst => reset, din => to_send_data, wr_en => send_data, rd_en => tx_done, dout => tx_data,
full => tx_full, empty => inv_in);
disp_ctrl : disp_controller
port map(clk => clk, reset => reset, din => sh_ctrl_dout, data_count => data_count, show_data => show_data,
get_data_o => sh_get_data, dout => lcd_dout, lcd_rs => lcd_rs, lcd_rw => lcd_rw, lcd_e => lcd_e);
rf_ctrl : reg_file_controller
generic map(reg_num => reg_num, reg_width => reg_width, rf_addr_w => rf_addr_w, data_bits => data_bits)
port map(clk => clk, reset => reset, rx_din => got_data, rx_req => get_data, renew => renew_reg,
tx_req => send_data, rf_req => wr_rf, tx_dout => to_send_data, rf_dout => rf_wr_data, rf_addr => rf_wr_addr
);
regfile : register_file
generic map(reg_width => reg_width, addr_width => rf_addr_w)
port map(clk => clk, reset => reset, wr_en => wr_rf, wr_addr => rf_wr_addr, rd_addr => rf_rd_addr,
wr_data => rf_wr_data, rd_data => rf_rd_data, rd_addr_2 => rf_rd_addr2, rd_data_2 => rf_rd_data2,
rd_addr_3 => rf_rd_addr3, rd_data_3 => rf_rd_data3);
show_ctrl : show_controller
generic map(reg_width => reg_width, addr_width => rf_addr_w)
port map(clk => clk, reset => reset, up => up, down => down, rf_data => rf_rd_data,
rf_addr => rf_rd_addr, show_dout => sh_ctrl_data, data_count => data_count, show_data => show_data, fifo_wr => show_wr_en);
show_ctrl_fifo : show_fifo_wide
port map(clk => clk, rst => reset, din => sh_ctrl_data, wr_en => show_wr_en, rd_en => sh_get_data, dout => sh_ctrl_dout,
full => show_full, empty => show_empty);
rot_ctrl : rotary
port map(clk => clk, rot_a => rot_a, rot_b => rot_b, up => up, down => down);
sw_ctrl : switch_controller
generic map(reg_width => reg_width, rf_addr_w => rf_addr_w)
port map(clk => clk, reset => reset, sw0 => sw0, sw1 => sw1, sw2 => sw2, sw3 => sw3,
rf_data => rf_rd_data2, rf_addr => rf_rd_addr2, led => led(3 downto 0));
l_ctrl : led_controller
generic map(reg_width => reg_width, rf_addr_w => rf_addr_w)
port map(clk => clk, reset => reset, rf_data => rf_rd_data3, rf_addr => rf_rd_addr3, led => led(7 downto 4));
end Behavioral;
|
mit
|
c3c39f1e7a9fa75b9667e0960b9b58c5
| 0.638112 | 2.784161 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/uart_tx.vhd
| 1 | 2,728 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 19:54:39 03/20/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: uart_tx - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart_tx is
generic(
dbits : integer := 8;
sb_ticks : integer := 16 -- 16 for 1 stop bit, 24 for 1.5, 32 for 2
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : in std_logic;
tx_start : in std_logic;
tx_data : in std_logic_vector((dbits-1) downto 0);
tx_done : out std_logic;
tx : out std_logic
);
end uart_tx;
architecture Behavioral of uart_tx is
type t_state is (idle, start, data, stop);
signal state, state_next : t_state;
signal s, s_next : unsigned(3 downto 0); -- number of sampling ticks; 16
signal n, n_next : unsigned(2 downto 0); -- number of bits sent
signal d, d_next : std_logic_vector((dbits-1) downto 0); -- data sent
signal tx_r, tx_next : std_logic;
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= idle;
s <= (others => '0');
n <= (others => '0');
d <= (others => '0');
tx_r <= '1';
else
state <= state_next;
s <= s_next;
n <= n_next;
d <= d_next;
tx_r <= tx_next;
end if;
end if;
end process;
routing : process (state, s, n, d, b_edge, tx_r, tx_start, tx_data)
begin
state_next <= state;
s_next <= s;
n_next <= n;
d_next <= d;
tx_next <= tx_r;
tx_done <= '0';
case state is
when idle =>
tx_next <= '1';
if tx_start = '1' then
state_next <= start;
s_next <= (others => '0');
d_next <= tx_data;
end if;
when start =>
tx_next <= '0';
if b_edge = '1' then
if s = 15 then
state_next <= data;
s_next <= (others => '0');
n_next <= (others => '0');
else
s_next <= s + 1;
end if;
end if;
when data =>
tx_next <= d(0);
if b_edge = '1' then
if s = 15 then
s_next <= (others => '0');
d_next <= '0' & d((dbits-1) downto 1);
if n = (dbits - 1) then
state_next <= stop;
else
n_next <= n + 1;
end if;
else
s_next <= s+1;
end if;
end if;
when stop =>
tx_next <= '1';
if b_edge = '1' then
if s = sb_ticks - 1 then
state_next <= idle;
tx_done <= '1';
else
s_next <= s + 1;
end if;
end if;
end case;
end process;
tx <= tx_r;
end Behavioral;
|
mit
|
9c75c7fdacd1d98904b822cf6eb65d29
| 0.506598 | 2.835759 | false | false | false | false |
LemurPwned/classic-fpga
|
encoders/grey.vhdl
| 1 | 809 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------
--BCD TO GREY DECODER
------------------------------------
entity grey is
port (
si : in std_logic_vector(2 downto 0);
so : out std_logic_vector(2 downto 0)
);
end entity;
architecture arch of grey is
signal nsi :std_logic_vector(2 downto 0);
signal n1, n2, n3, n4, n5, n6, n7 : std_logic;
begin
nsi <= not si;
--1,2,5,6
n1<= nsi(2) and nsi(1) and si(0);
n2<= nsi(2) and si(1) and nsi(0);
n3<= nsi(2) and si(1) and si(0);
n4<= si(2) and nsi(1) and nsi(0);
n5<= si(2) and nsi(1) and si(0);
n6<= si(2) and si(1) and nsi(0);
n7<= si(2) and si(1) and si(0);
so(0) <= n1 or n2 or n5 or n6;
so(1) <= n2 or n3 or n4 or n5;
so(2) <= n4 or n5 or n6 or n7;
end architecture;
|
gpl-3.0
|
dfda759af947736a2337d5605f31e204
| 0.545117 | 2.481595 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/reg_adder_tb.vhdl
| 1 | 881 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_adder_tb is
end entity;
architecture reg_adder_tb of reg_adder_tb is
component reg_adder is
port (
A, B: in std_logic_vector (3 downto 0);
clk : in std_logic;
se : in std_logic;
C: out std_logic_vector(3 downto 0);
over : out std_logic
);
end component;
signal A,B,C : std_logic_vector(3 downto 0):="0000";
signal clk, se, over : std_logic :='0';
constant period : time := 10 ns;
begin
uut: reg_adder port map (clk=>clk, A=>A, B=>B, C=>C, se=>se, over=>over);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc:
process
begin
se<='1';
A<="1101";
B<="0110";
wait for 20 ns;
se<='0';
wait for 100 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
fb263e3c04d9f0173872dbc22dd6c726
| 0.586833 | 3.124113 | false | false | false | false |
LemurPwned/classic-fpga
|
machines/seq_det_tb.vhdl
| 1 | 988 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seq_det_tb is
end entity;
architecture behav of seq_det_tb is
component seq_det is
port(
clk : in std_logic;
reset : in std_logic;
seq : in std_logic;
det : out std_logic
);
end component;
signal clk : std_logic :='1';
signal reset, det, seq : std_logic :='0';
constant period : time := 10 ns;
begin
mapping: seq_det port map (clk=>clk, reset=>reset, seq=>seq, det=>det);
clk_proc: process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc: process
begin
seq<='1';
wait for period;
seq<='1';
wait for period;
seq<='0';
wait for period;
seq<='1';
wait for period;
seq<='0';
wait for period;
seq<='1';
wait for period;
seq<='0';
wait for period;
seq<='1';
wait for period;
seq<='1';
wait for period;
seq<='1';
wait for period;
wait;
end process;
end architecture;
|
gpl-3.0
|
599940eca7f5a6248e7403e9442615fd
| 0.598178 | 3.25 | false | false | false | false |
LemurPwned/classic-fpga
|
compar.vhdl
| 1 | 1,036 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity compar is
port (
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
so_a : out std_logic;
so_b : out std_logic
);
end entity;
architecture behav of compar is
signal a_b, b_b,a_b1, b_b1,a_b2, b_b2,a_b3, b_b3, a_b4, b_b4: std_logic;
begin
a_b<='0';
b_b<='0';
a_b1<=(a(0) and (not b(0))) or (a_b and a(0)) or ((a_b and (not (b(0)))));
b_b1<=((not a(0)) and b(0)) or ((not a(0)) and b_b) or (b(0) and b_b);
a_b2<=(a(1) and (not b(1))) or (a_b1 and a(1)) or ((a_b1 and (not (b(1)))));
b_b2<=((not a(1)) and b(1)) or ((not a(1)) and b_b1) or (b(1) and b_b1);
a_b3<=(a(2) and (not b(2))) or (a_b2 and a(2)) or ((a_b2 and (not (b(1)))));
b_b3<=((not a(2)) and b(2)) or ((not a(2)) and b_b2) or (b(2) and b_b2);
a_b4<=(a(3) and (not b(3))) or (a_b3 and a(3)) or ((a_b3 and (not (b(3)))));
b_b4<=((not a(3)) and b(3)) or ((not a(3)) and b_b3) or (b(3) and b_b3);
so_a <= a_b4;
so_b <= b_b4;
end architecture;
|
gpl-3.0
|
73a9135acc17d2dae64013bd7128a03e
| 0.529923 | 2.007752 | false | false | false | false |
jandecaluwe/ca
|
myhdl/calc_next_age/tb.vhd
| 1 | 34,098 |
-- File: tb.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Dec 16 22:45:16 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity tb is
end entity tb;
architecture MyHDL of tb is
signal reset: std_logic;
signal live_count: unsigned(3 downto 0);
signal step: std_logic;
signal clock: std_logic;
signal age_out: std_logic;
signal dut_age: std_logic;
begin
TB_DUT_SEQ: process (clock, reset) is
variable survival: std_logic;
variable birth: std_logic;
begin
if (reset = '1') then
dut_age <= '0';
elsif rising_edge(clock) then
birth := stdl(live_count = 3);
survival := stdl((live_count = 2) or (live_count = 3));
if bool(step) then
if ((dut_age = '0') and bool(birth)) then
dut_age <= '1';
elsif ((dut_age = '1') and (not bool(survival))) then
dut_age <= '0';
end if;
end if;
end if;
end process TB_DUT_SEQ;
age_out <= dut_age;
TB_CLOCKGEN: process is
begin
reset <= '0';
clock <= '0';
wait for 10 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
while True loop
wait for 10 ns;
clock <= stdl((not bool(clock)));
end loop;
wait;
end process TB_CLOCKGEN;
TB_CHECK: process is
variable L: line;
variable expected_age: std_logic;
variable v: integer;
begin
expected_age := '0';
for i in 0 to 1000-1 loop
wait until falling_edge(clock);
write(L, bool(age_out));
writeline(output, L);
case i is
when 0 => v := 2;
when 1 => v := 7;
when 2 => v := 0;
when 3 => v := 6;
when 4 => v := 0;
when 5 => v := 2;
when 6 => v := 0;
when 7 => v := 7;
when 8 => v := 0;
when 9 => v := 3;
when 10 => v := 7;
when 11 => v := 6;
when 12 => v := 0;
when 13 => v := 8;
when 14 => v := 6;
when 15 => v := 5;
when 16 => v := 8;
when 17 => v := 3;
when 18 => v := 1;
when 19 => v := 0;
when 20 => v := 2;
when 21 => v := 7;
when 22 => v := 7;
when 23 => v := 0;
when 24 => v := 4;
when 25 => v := 4;
when 26 => v := 3;
when 27 => v := 6;
when 28 => v := 5;
when 29 => v := 0;
when 30 => v := 1;
when 31 => v := 5;
when 32 => v := 8;
when 33 => v := 6;
when 34 => v := 5;
when 35 => v := 5;
when 36 => v := 8;
when 37 => v := 6;
when 38 => v := 3;
when 39 => v := 1;
when 40 => v := 4;
when 41 => v := 5;
when 42 => v := 1;
when 43 => v := 6;
when 44 => v := 7;
when 45 => v := 4;
when 46 => v := 8;
when 47 => v := 0;
when 48 => v := 2;
when 49 => v := 1;
when 50 => v := 1;
when 51 => v := 4;
when 52 => v := 2;
when 53 => v := 7;
when 54 => v := 1;
when 55 => v := 6;
when 56 => v := 4;
when 57 => v := 7;
when 58 => v := 6;
when 59 => v := 2;
when 60 => v := 1;
when 61 => v := 2;
when 62 => v := 2;
when 63 => v := 6;
when 64 => v := 8;
when 65 => v := 4;
when 66 => v := 4;
when 67 => v := 7;
when 68 => v := 4;
when 69 => v := 3;
when 70 => v := 0;
when 71 => v := 3;
when 72 => v := 2;
when 73 => v := 4;
when 74 => v := 1;
when 75 => v := 2;
when 76 => v := 4;
when 77 => v := 5;
when 78 => v := 4;
when 79 => v := 4;
when 80 => v := 0;
when 81 => v := 1;
when 82 => v := 1;
when 83 => v := 1;
when 84 => v := 7;
when 85 => v := 8;
when 86 => v := 5;
when 87 => v := 6;
when 88 => v := 1;
when 89 => v := 2;
when 90 => v := 5;
when 91 => v := 7;
when 92 => v := 8;
when 93 => v := 4;
when 94 => v := 5;
when 95 => v := 0;
when 96 => v := 1;
when 97 => v := 7;
when 98 => v := 5;
when 99 => v := 6;
when 100 => v := 8;
when 101 => v := 5;
when 102 => v := 2;
when 103 => v := 7;
when 104 => v := 2;
when 105 => v := 4;
when 106 => v := 5;
when 107 => v := 4;
when 108 => v := 1;
when 109 => v := 8;
when 110 => v := 4;
when 111 => v := 7;
when 112 => v := 6;
when 113 => v := 8;
when 114 => v := 4;
when 115 => v := 8;
when 116 => v := 0;
when 117 => v := 3;
when 118 => v := 0;
when 119 => v := 5;
when 120 => v := 8;
when 121 => v := 8;
when 122 => v := 4;
when 123 => v := 3;
when 124 => v := 3;
when 125 => v := 3;
when 126 => v := 1;
when 127 => v := 2;
when 128 => v := 5;
when 129 => v := 3;
when 130 => v := 2;
when 131 => v := 2;
when 132 => v := 6;
when 133 => v := 6;
when 134 => v := 1;
when 135 => v := 1;
when 136 => v := 5;
when 137 => v := 5;
when 138 => v := 6;
when 139 => v := 6;
when 140 => v := 1;
when 141 => v := 3;
when 142 => v := 3;
when 143 => v := 4;
when 144 => v := 8;
when 145 => v := 8;
when 146 => v := 4;
when 147 => v := 3;
when 148 => v := 2;
when 149 => v := 4;
when 150 => v := 6;
when 151 => v := 7;
when 152 => v := 2;
when 153 => v := 5;
when 154 => v := 5;
when 155 => v := 0;
when 156 => v := 1;
when 157 => v := 2;
when 158 => v := 1;
when 159 => v := 4;
when 160 => v := 0;
when 161 => v := 0;
when 162 => v := 2;
when 163 => v := 6;
when 164 => v := 7;
when 165 => v := 6;
when 166 => v := 7;
when 167 => v := 0;
when 168 => v := 8;
when 169 => v := 2;
when 170 => v := 4;
when 171 => v := 5;
when 172 => v := 4;
when 173 => v := 7;
when 174 => v := 3;
when 175 => v := 3;
when 176 => v := 2;
when 177 => v := 6;
when 178 => v := 7;
when 179 => v := 7;
when 180 => v := 8;
when 181 => v := 0;
when 182 => v := 7;
when 183 => v := 8;
when 184 => v := 4;
when 185 => v := 1;
when 186 => v := 6;
when 187 => v := 5;
when 188 => v := 4;
when 189 => v := 4;
when 190 => v := 6;
when 191 => v := 4;
when 192 => v := 8;
when 193 => v := 0;
when 194 => v := 6;
when 195 => v := 2;
when 196 => v := 1;
when 197 => v := 3;
when 198 => v := 5;
when 199 => v := 5;
when 200 => v := 6;
when 201 => v := 2;
when 202 => v := 8;
when 203 => v := 4;
when 204 => v := 6;
when 205 => v := 0;
when 206 => v := 0;
when 207 => v := 6;
when 208 => v := 4;
when 209 => v := 0;
when 210 => v := 8;
when 211 => v := 7;
when 212 => v := 2;
when 213 => v := 3;
when 214 => v := 3;
when 215 => v := 8;
when 216 => v := 8;
when 217 => v := 5;
when 218 => v := 8;
when 219 => v := 4;
when 220 => v := 5;
when 221 => v := 8;
when 222 => v := 6;
when 223 => v := 6;
when 224 => v := 8;
when 225 => v := 7;
when 226 => v := 5;
when 227 => v := 2;
when 228 => v := 2;
when 229 => v := 2;
when 230 => v := 3;
when 231 => v := 6;
when 232 => v := 5;
when 233 => v := 5;
when 234 => v := 5;
when 235 => v := 6;
when 236 => v := 3;
when 237 => v := 6;
when 238 => v := 4;
when 239 => v := 8;
when 240 => v := 6;
when 241 => v := 5;
when 242 => v := 2;
when 243 => v := 8;
when 244 => v := 1;
when 245 => v := 8;
when 246 => v := 2;
when 247 => v := 4;
when 248 => v := 1;
when 249 => v := 8;
when 250 => v := 2;
when 251 => v := 5;
when 252 => v := 8;
when 253 => v := 2;
when 254 => v := 6;
when 255 => v := 6;
when 256 => v := 2;
when 257 => v := 4;
when 258 => v := 7;
when 259 => v := 6;
when 260 => v := 8;
when 261 => v := 0;
when 262 => v := 6;
when 263 => v := 7;
when 264 => v := 2;
when 265 => v := 5;
when 266 => v := 6;
when 267 => v := 1;
when 268 => v := 3;
when 269 => v := 4;
when 270 => v := 1;
when 271 => v := 2;
when 272 => v := 7;
when 273 => v := 1;
when 274 => v := 4;
when 275 => v := 2;
when 276 => v := 6;
when 277 => v := 6;
when 278 => v := 1;
when 279 => v := 3;
when 280 => v := 3;
when 281 => v := 5;
when 282 => v := 0;
when 283 => v := 8;
when 284 => v := 5;
when 285 => v := 7;
when 286 => v := 8;
when 287 => v := 1;
when 288 => v := 6;
when 289 => v := 3;
when 290 => v := 1;
when 291 => v := 4;
when 292 => v := 0;
when 293 => v := 7;
when 294 => v := 4;
when 295 => v := 7;
when 296 => v := 2;
when 297 => v := 5;
when 298 => v := 3;
when 299 => v := 6;
when 300 => v := 1;
when 301 => v := 6;
when 302 => v := 0;
when 303 => v := 0;
when 304 => v := 1;
when 305 => v := 8;
when 306 => v := 3;
when 307 => v := 2;
when 308 => v := 5;
when 309 => v := 1;
when 310 => v := 8;
when 311 => v := 1;
when 312 => v := 1;
when 313 => v := 4;
when 314 => v := 2;
when 315 => v := 6;
when 316 => v := 2;
when 317 => v := 2;
when 318 => v := 7;
when 319 => v := 0;
when 320 => v := 5;
when 321 => v := 5;
when 322 => v := 2;
when 323 => v := 0;
when 324 => v := 8;
when 325 => v := 2;
when 326 => v := 3;
when 327 => v := 5;
when 328 => v := 8;
when 329 => v := 2;
when 330 => v := 8;
when 331 => v := 0;
when 332 => v := 6;
when 333 => v := 5;
when 334 => v := 0;
when 335 => v := 8;
when 336 => v := 6;
when 337 => v := 6;
when 338 => v := 4;
when 339 => v := 8;
when 340 => v := 7;
when 341 => v := 5;
when 342 => v := 6;
when 343 => v := 1;
when 344 => v := 1;
when 345 => v := 7;
when 346 => v := 8;
when 347 => v := 6;
when 348 => v := 1;
when 349 => v := 4;
when 350 => v := 4;
when 351 => v := 8;
when 352 => v := 4;
when 353 => v := 6;
when 354 => v := 7;
when 355 => v := 4;
when 356 => v := 3;
when 357 => v := 5;
when 358 => v := 3;
when 359 => v := 4;
when 360 => v := 3;
when 361 => v := 5;
when 362 => v := 6;
when 363 => v := 1;
when 364 => v := 3;
when 365 => v := 1;
when 366 => v := 7;
when 367 => v := 1;
when 368 => v := 2;
when 369 => v := 8;
when 370 => v := 6;
when 371 => v := 1;
when 372 => v := 4;
when 373 => v := 6;
when 374 => v := 6;
when 375 => v := 7;
when 376 => v := 8;
when 377 => v := 8;
when 378 => v := 8;
when 379 => v := 0;
when 380 => v := 4;
when 381 => v := 6;
when 382 => v := 2;
when 383 => v := 0;
when 384 => v := 5;
when 385 => v := 4;
when 386 => v := 7;
when 387 => v := 2;
when 388 => v := 7;
when 389 => v := 2;
when 390 => v := 3;
when 391 => v := 5;
when 392 => v := 4;
when 393 => v := 1;
when 394 => v := 2;
when 395 => v := 8;
when 396 => v := 8;
when 397 => v := 3;
when 398 => v := 8;
when 399 => v := 4;
when 400 => v := 5;
when 401 => v := 3;
when 402 => v := 0;
when 403 => v := 8;
when 404 => v := 0;
when 405 => v := 0;
when 406 => v := 6;
when 407 => v := 5;
when 408 => v := 4;
when 409 => v := 6;
when 410 => v := 0;
when 411 => v := 0;
when 412 => v := 5;
when 413 => v := 3;
when 414 => v := 2;
when 415 => v := 1;
when 416 => v := 2;
when 417 => v := 7;
when 418 => v := 0;
when 419 => v := 6;
when 420 => v := 1;
when 421 => v := 0;
when 422 => v := 2;
when 423 => v := 0;
when 424 => v := 0;
when 425 => v := 4;
when 426 => v := 4;
when 427 => v := 0;
when 428 => v := 0;
when 429 => v := 3;
when 430 => v := 7;
when 431 => v := 5;
when 432 => v := 7;
when 433 => v := 2;
when 434 => v := 1;
when 435 => v := 4;
when 436 => v := 1;
when 437 => v := 4;
when 438 => v := 3;
when 439 => v := 7;
when 440 => v := 6;
when 441 => v := 1;
when 442 => v := 8;
when 443 => v := 7;
when 444 => v := 6;
when 445 => v := 1;
when 446 => v := 2;
when 447 => v := 2;
when 448 => v := 6;
when 449 => v := 3;
when 450 => v := 6;
when 451 => v := 8;
when 452 => v := 3;
when 453 => v := 6;
when 454 => v := 8;
when 455 => v := 6;
when 456 => v := 4;
when 457 => v := 4;
when 458 => v := 3;
when 459 => v := 5;
when 460 => v := 2;
when 461 => v := 0;
when 462 => v := 4;
when 463 => v := 4;
when 464 => v := 7;
when 465 => v := 3;
when 466 => v := 2;
when 467 => v := 4;
when 468 => v := 6;
when 469 => v := 8;
when 470 => v := 1;
when 471 => v := 5;
when 472 => v := 5;
when 473 => v := 7;
when 474 => v := 8;
when 475 => v := 0;
when 476 => v := 5;
when 477 => v := 1;
when 478 => v := 4;
when 479 => v := 1;
when 480 => v := 3;
when 481 => v := 2;
when 482 => v := 5;
when 483 => v := 0;
when 484 => v := 2;
when 485 => v := 2;
when 486 => v := 6;
when 487 => v := 2;
when 488 => v := 5;
when 489 => v := 6;
when 490 => v := 1;
when 491 => v := 0;
when 492 => v := 8;
when 493 => v := 1;
when 494 => v := 2;
when 495 => v := 6;
when 496 => v := 4;
when 497 => v := 3;
when 498 => v := 0;
when 499 => v := 7;
when 500 => v := 8;
when 501 => v := 0;
when 502 => v := 5;
when 503 => v := 7;
when 504 => v := 7;
when 505 => v := 7;
when 506 => v := 2;
when 507 => v := 6;
when 508 => v := 8;
when 509 => v := 3;
when 510 => v := 4;
when 511 => v := 0;
when 512 => v := 2;
when 513 => v := 8;
when 514 => v := 0;
when 515 => v := 6;
when 516 => v := 1;
when 517 => v := 0;
when 518 => v := 0;
when 519 => v := 5;
when 520 => v := 1;
when 521 => v := 2;
when 522 => v := 7;
when 523 => v := 7;
when 524 => v := 5;
when 525 => v := 3;
when 526 => v := 1;
when 527 => v := 8;
when 528 => v := 0;
when 529 => v := 3;
when 530 => v := 7;
when 531 => v := 3;
when 532 => v := 8;
when 533 => v := 2;
when 534 => v := 0;
when 535 => v := 8;
when 536 => v := 0;
when 537 => v := 6;
when 538 => v := 7;
when 539 => v := 4;
when 540 => v := 3;
when 541 => v := 4;
when 542 => v := 8;
when 543 => v := 6;
when 544 => v := 4;
when 545 => v := 8;
when 546 => v := 4;
when 547 => v := 0;
when 548 => v := 7;
when 549 => v := 5;
when 550 => v := 4;
when 551 => v := 2;
when 552 => v := 4;
when 553 => v := 2;
when 554 => v := 5;
when 555 => v := 4;
when 556 => v := 3;
when 557 => v := 7;
when 558 => v := 4;
when 559 => v := 2;
when 560 => v := 3;
when 561 => v := 3;
when 562 => v := 1;
when 563 => v := 2;
when 564 => v := 0;
when 565 => v := 5;
when 566 => v := 6;
when 567 => v := 7;
when 568 => v := 4;
when 569 => v := 0;
when 570 => v := 8;
when 571 => v := 3;
when 572 => v := 4;
when 573 => v := 2;
when 574 => v := 4;
when 575 => v := 7;
when 576 => v := 4;
when 577 => v := 2;
when 578 => v := 5;
when 579 => v := 7;
when 580 => v := 6;
when 581 => v := 7;
when 582 => v := 3;
when 583 => v := 8;
when 584 => v := 4;
when 585 => v := 6;
when 586 => v := 8;
when 587 => v := 1;
when 588 => v := 5;
when 589 => v := 4;
when 590 => v := 6;
when 591 => v := 7;
when 592 => v := 5;
when 593 => v := 6;
when 594 => v := 7;
when 595 => v := 4;
when 596 => v := 1;
when 597 => v := 4;
when 598 => v := 2;
when 599 => v := 0;
when 600 => v := 4;
when 601 => v := 6;
when 602 => v := 6;
when 603 => v := 7;
when 604 => v := 2;
when 605 => v := 2;
when 606 => v := 0;
when 607 => v := 6;
when 608 => v := 4;
when 609 => v := 7;
when 610 => v := 7;
when 611 => v := 1;
when 612 => v := 7;
when 613 => v := 8;
when 614 => v := 2;
when 615 => v := 0;
when 616 => v := 5;
when 617 => v := 8;
when 618 => v := 6;
when 619 => v := 0;
when 620 => v := 2;
when 621 => v := 6;
when 622 => v := 2;
when 623 => v := 1;
when 624 => v := 2;
when 625 => v := 3;
when 626 => v := 8;
when 627 => v := 7;
when 628 => v := 8;
when 629 => v := 1;
when 630 => v := 0;
when 631 => v := 7;
when 632 => v := 8;
when 633 => v := 4;
when 634 => v := 8;
when 635 => v := 6;
when 636 => v := 8;
when 637 => v := 2;
when 638 => v := 7;
when 639 => v := 2;
when 640 => v := 2;
when 641 => v := 7;
when 642 => v := 2;
when 643 => v := 6;
when 644 => v := 8;
when 645 => v := 8;
when 646 => v := 1;
when 647 => v := 4;
when 648 => v := 8;
when 649 => v := 0;
when 650 => v := 5;
when 651 => v := 6;
when 652 => v := 5;
when 653 => v := 5;
when 654 => v := 8;
when 655 => v := 6;
when 656 => v := 3;
when 657 => v := 4;
when 658 => v := 6;
when 659 => v := 8;
when 660 => v := 6;
when 661 => v := 6;
when 662 => v := 0;
when 663 => v := 3;
when 664 => v := 4;
when 665 => v := 5;
when 666 => v := 2;
when 667 => v := 2;
when 668 => v := 4;
when 669 => v := 5;
when 670 => v := 0;
when 671 => v := 3;
when 672 => v := 6;
when 673 => v := 4;
when 674 => v := 3;
when 675 => v := 0;
when 676 => v := 3;
when 677 => v := 2;
when 678 => v := 3;
when 679 => v := 1;
when 680 => v := 7;
when 681 => v := 6;
when 682 => v := 1;
when 683 => v := 6;
when 684 => v := 2;
when 685 => v := 1;
when 686 => v := 7;
when 687 => v := 8;
when 688 => v := 4;
when 689 => v := 5;
when 690 => v := 7;
when 691 => v := 3;
when 692 => v := 1;
when 693 => v := 8;
when 694 => v := 1;
when 695 => v := 6;
when 696 => v := 3;
when 697 => v := 3;
when 698 => v := 4;
when 699 => v := 0;
when 700 => v := 1;
when 701 => v := 6;
when 702 => v := 4;
when 703 => v := 6;
when 704 => v := 7;
when 705 => v := 3;
when 706 => v := 8;
when 707 => v := 7;
when 708 => v := 3;
when 709 => v := 3;
when 710 => v := 5;
when 711 => v := 2;
when 712 => v := 7;
when 713 => v := 1;
when 714 => v := 5;
when 715 => v := 1;
when 716 => v := 8;
when 717 => v := 4;
when 718 => v := 4;
when 719 => v := 8;
when 720 => v := 8;
when 721 => v := 4;
when 722 => v := 4;
when 723 => v := 0;
when 724 => v := 8;
when 725 => v := 7;
when 726 => v := 0;
when 727 => v := 7;
when 728 => v := 1;
when 729 => v := 6;
when 730 => v := 7;
when 731 => v := 4;
when 732 => v := 7;
when 733 => v := 7;
when 734 => v := 8;
when 735 => v := 6;
when 736 => v := 3;
when 737 => v := 6;
when 738 => v := 5;
when 739 => v := 0;
when 740 => v := 8;
when 741 => v := 5;
when 742 => v := 2;
when 743 => v := 6;
when 744 => v := 1;
when 745 => v := 4;
when 746 => v := 1;
when 747 => v := 8;
when 748 => v := 8;
when 749 => v := 6;
when 750 => v := 5;
when 751 => v := 6;
when 752 => v := 3;
when 753 => v := 4;
when 754 => v := 0;
when 755 => v := 4;
when 756 => v := 2;
when 757 => v := 2;
when 758 => v := 2;
when 759 => v := 3;
when 760 => v := 6;
when 761 => v := 4;
when 762 => v := 5;
when 763 => v := 6;
when 764 => v := 6;
when 765 => v := 1;
when 766 => v := 6;
when 767 => v := 0;
when 768 => v := 2;
when 769 => v := 3;
when 770 => v := 3;
when 771 => v := 3;
when 772 => v := 3;
when 773 => v := 7;
when 774 => v := 8;
when 775 => v := 4;
when 776 => v := 0;
when 777 => v := 8;
when 778 => v := 8;
when 779 => v := 1;
when 780 => v := 4;
when 781 => v := 4;
when 782 => v := 4;
when 783 => v := 2;
when 784 => v := 2;
when 785 => v := 6;
when 786 => v := 0;
when 787 => v := 7;
when 788 => v := 7;
when 789 => v := 0;
when 790 => v := 4;
when 791 => v := 4;
when 792 => v := 5;
when 793 => v := 4;
when 794 => v := 2;
when 795 => v := 8;
when 796 => v := 0;
when 797 => v := 1;
when 798 => v := 1;
when 799 => v := 7;
when 800 => v := 3;
when 801 => v := 0;
when 802 => v := 8;
when 803 => v := 6;
when 804 => v := 0;
when 805 => v := 3;
when 806 => v := 2;
when 807 => v := 8;
when 808 => v := 1;
when 809 => v := 7;
when 810 => v := 7;
when 811 => v := 5;
when 812 => v := 1;
when 813 => v := 0;
when 814 => v := 6;
when 815 => v := 5;
when 816 => v := 3;
when 817 => v := 3;
when 818 => v := 0;
when 819 => v := 4;
when 820 => v := 4;
when 821 => v := 0;
when 822 => v := 6;
when 823 => v := 0;
when 824 => v := 2;
when 825 => v := 7;
when 826 => v := 0;
when 827 => v := 2;
when 828 => v := 3;
when 829 => v := 8;
when 830 => v := 5;
when 831 => v := 7;
when 832 => v := 5;
when 833 => v := 7;
when 834 => v := 1;
when 835 => v := 4;
when 836 => v := 8;
when 837 => v := 8;
when 838 => v := 8;
when 839 => v := 3;
when 840 => v := 2;
when 841 => v := 1;
when 842 => v := 3;
when 843 => v := 3;
when 844 => v := 5;
when 845 => v := 5;
when 846 => v := 1;
when 847 => v := 5;
when 848 => v := 5;
when 849 => v := 4;
when 850 => v := 1;
when 851 => v := 0;
when 852 => v := 2;
when 853 => v := 8;
when 854 => v := 3;
when 855 => v := 0;
when 856 => v := 4;
when 857 => v := 4;
when 858 => v := 4;
when 859 => v := 5;
when 860 => v := 1;
when 861 => v := 5;
when 862 => v := 5;
when 863 => v := 0;
when 864 => v := 1;
when 865 => v := 1;
when 866 => v := 7;
when 867 => v := 7;
when 868 => v := 5;
when 869 => v := 4;
when 870 => v := 5;
when 871 => v := 8;
when 872 => v := 7;
when 873 => v := 7;
when 874 => v := 7;
when 875 => v := 3;
when 876 => v := 1;
when 877 => v := 4;
when 878 => v := 1;
when 879 => v := 7;
when 880 => v := 6;
when 881 => v := 1;
when 882 => v := 0;
when 883 => v := 3;
when 884 => v := 2;
when 885 => v := 1;
when 886 => v := 4;
when 887 => v := 8;
when 888 => v := 6;
when 889 => v := 3;
when 890 => v := 7;
when 891 => v := 4;
when 892 => v := 5;
when 893 => v := 7;
when 894 => v := 2;
when 895 => v := 8;
when 896 => v := 5;
when 897 => v := 7;
when 898 => v := 4;
when 899 => v := 1;
when 900 => v := 1;
when 901 => v := 7;
when 902 => v := 5;
when 903 => v := 3;
when 904 => v := 6;
when 905 => v := 5;
when 906 => v := 1;
when 907 => v := 8;
when 908 => v := 6;
when 909 => v := 8;
when 910 => v := 3;
when 911 => v := 0;
when 912 => v := 0;
when 913 => v := 7;
when 914 => v := 3;
when 915 => v := 3;
when 916 => v := 7;
when 917 => v := 1;
when 918 => v := 3;
when 919 => v := 3;
when 920 => v := 7;
when 921 => v := 4;
when 922 => v := 5;
when 923 => v := 2;
when 924 => v := 8;
when 925 => v := 7;
when 926 => v := 0;
when 927 => v := 4;
when 928 => v := 8;
when 929 => v := 1;
when 930 => v := 2;
when 931 => v := 7;
when 932 => v := 3;
when 933 => v := 6;
when 934 => v := 8;
when 935 => v := 7;
when 936 => v := 7;
when 937 => v := 7;
when 938 => v := 6;
when 939 => v := 2;
when 940 => v := 6;
when 941 => v := 6;
when 942 => v := 6;
when 943 => v := 4;
when 944 => v := 5;
when 945 => v := 8;
when 946 => v := 4;
when 947 => v := 4;
when 948 => v := 2;
when 949 => v := 8;
when 950 => v := 0;
when 951 => v := 1;
when 952 => v := 8;
when 953 => v := 2;
when 954 => v := 1;
when 955 => v := 4;
when 956 => v := 8;
when 957 => v := 8;
when 958 => v := 1;
when 959 => v := 3;
when 960 => v := 8;
when 961 => v := 1;
when 962 => v := 7;
when 963 => v := 3;
when 964 => v := 4;
when 965 => v := 6;
when 966 => v := 2;
when 967 => v := 3;
when 968 => v := 5;
when 969 => v := 8;
when 970 => v := 1;
when 971 => v := 6;
when 972 => v := 5;
when 973 => v := 4;
when 974 => v := 5;
when 975 => v := 2;
when 976 => v := 7;
when 977 => v := 8;
when 978 => v := 0;
when 979 => v := 2;
when 980 => v := 4;
when 981 => v := 0;
when 982 => v := 3;
when 983 => v := 0;
when 984 => v := 0;
when 985 => v := 5;
when 986 => v := 1;
when 987 => v := 8;
when 988 => v := 0;
when 989 => v := 2;
when 990 => v := 0;
when 991 => v := 6;
when 992 => v := 8;
when 993 => v := 1;
when 994 => v := 6;
when 995 => v := 1;
when 996 => v := 0;
when 997 => v := 5;
when 998 => v := 2;
when others => v := 4;
end case;
if ((age_out = '0') and (v = 3)) then
expected_age := '1';
end if;
if ((age_out = '1') and (not ((v = 2) or (v = 3)))) then
expected_age := '0';
end if;
live_count <= to_unsigned(v, 4);
step <= '1';
wait until rising_edge(clock);
wait for 1 ns;
assert (age_out = expected_age)
report "*** AssertionError ***"
severity error;
end loop;
assert False report "End of Simulation" severity Failure;
wait;
end process TB_CHECK;
end architecture MyHDL;
|
mit
|
f9447a639afe90215ecdc829b4c1aaa4
| 0.296968 | 3.937413 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/uart_rx.vhd
| 1 | 2,507 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 15:19:51 03/20/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: uart_rx - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart_rx is
generic(
dbits : integer := 8;
sb_ticks : integer := 16 -- 16 for 1 stop bit, 24 for 1.5, 32 for 2
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : in std_logic;
rx: in std_logic;
rx_data : out std_logic_vector((dbits-1) downto 0);
rx_done : out std_logic
);
end uart_rx;
architecture Behavioral of uart_rx is
type t_state is (idle, start, data, stop);
signal state, state_next : t_state;
signal s, s_next : unsigned(3 downto 0); -- number of sampling ticks; 7 for start; 15 for data
signal n, n_next : unsigned(2 downto 0); -- number of bits received
signal d, d_next : std_logic_vector((dbits-1) downto 0); -- data received
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= idle;
s <= (others => '0');
n <= (others => '0');
d <= (others => '0');
else
state <= state_next;
s <= s_next;
n <= n_next;
d <= d_next;
end if;
end if;
end process;
routing : process (state, s, n, d, rx, b_edge)
begin
state_next <= state;
s_next <= s;
n_next <= n;
d_next <= d;
rx_done <= '0';
case state is
when idle =>
if rx = '0' then
state_next <= start;
s_next <= (others => '0');
end if;
when start =>
if b_edge = '1' then
if s = 7 then
state_next <= data;
s_next <= (others => '0');
n_next <= (others => '0');
else
s_next <= s + 1;
end if;
end if;
when data =>
if b_edge = '1' then
if s = 15 then
s_next <= (others => '0');
d_next <= rx & d((dbits-1) downto 1);
if n = (dbits - 1) then
state_next <= stop;
else
n_next <= n + 1;
end if;
else
s_next <= s + 1;
end if;
end if;
when stop =>
if b_edge = '1' then
if s = sb_ticks - 1 then
state_next <= idle;
rx_done <= '1';
else
s_next <= s + 1;
end if;
end if;
end case;
end process;
rx_data <= d;
end Behavioral;
|
mit
|
4af07b3f17ef5f120182cce762da7858
| 0.513363 | 2.949412 | false | false | false | false |
juvasquezg/geany-hacking
|
data/filetypes.vhdl
| 5 | 2,985 |
# For complete documentation of this file, please see Geany's main documentation
[styling]
# Edit these in the colorscheme .conf file instead
default=default
comment=comment
comment_line_bang=comment_line
number=number_1
string=string_1
operator=operator
identifier=identifier_1
stringeol=string_eol
keyword=keyword_1
stdoperator=operator
attribute=attribute
stdfunction=function
stdpackage=preprocessor
stdtype=type
userword=keyword_2
[keywords]
# all items must be in one line
keywords=access after alias all architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map new next null of on open others out package port postponed procedure process pure range record register reject report return select severity shared signal subtype then to transport type unaffected units until use variable wait when while with
operators=abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
attributes=left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length delayed stable quiet transaction event active last_event last_active last_value driving driving_value simple_name path_name instance_name
std_functions=now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
std_packages=std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
std_types=boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
userwords=
[settings]
# default extension used when saving files
extension=vhd
# the following characters are these which a "word" can contains, see documentation
#wordchars=_abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
# single comments, like # in this file
comment_single=--
# multiline comments
#comment_open=
#comment_close=
# set to false if a comment character/string should start at column 0 of a line, true uses any
# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
#command_example();
# setting to false would generate this
# command_example();
# This setting works only for single line comments
comment_use_indent=true
# context action command (please see Geany's main documentation for details)
context_action_cmd=
[indentation]
#width=4
# 0 is spaces, 1 is tabs, 2 is tab & spaces
#type=1
|
gpl-2.0
|
9a9f5b608be3f234a6b39a65b85db6a6
| 0.818425 | 4.157382 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/multiplex_1_tb.vhdl
| 1 | 1,330 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplex_1_tb is
end entity;
architecture behav of multiplex_1_tb is
component multiplex_1
port (
smi : in std_logic_vector(6 downto 0);
smo : out std_logic;
se : in std_logic_vector(2 downto 0)
);
end component;
for multiplex_1_0 : multiplex_1 use entity work.multiplex_1;
signal smi : std_logic_vector (6 downto 0);
signal se : std_logic_vector (2 downto 0);
signal smo : std_logic;
begin
multiplex_1_0: multiplex_1 port map (smi=>smi, smo=>smo, se=>se);
process
begin
smi <= "1111011";
se <= "000";
wait for 5 ns;
se <= "001";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "011";
wait for 5 ns;
se <= "100";
wait for 5 ns;
smi <= "1110111";
se <= "000";
wait for 5 ns;
se <= "001";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "011";
wait for 5 ns;
se <= "100";
wait for 5 ns;
se <= "101";
wait for 5 ns;
se <= "110";
wait for 5 ns;
se <= "111";
wait for 5 ns;
smi <= "1011111";
se <= "000";
wait for 5 ns;
se <= "110";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "111";
wait for 5 ns;
se <= "101";
wait for 5 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
49830447e415dc2e76db02288c1ba01f
| 0.550376 | 3.064516 | false | false | false | false |
LemurPwned/classic-fpga
|
abs_1_tb.vhdl
| 1 | 1,030 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity abs_1_tb is
end entity;
architecture behav of abs_1_tb is
component abs_1
port (
si : in std_logic_vector(4 downto 0);
smo : out std_logic_vector(4 downto 0);
se : in std_logic_vector(0 downto 0);
s : in std_logic_vector(0 downto 0)
);
end component;
for abs_1_0 : abs_1 use entity work.abs_1;
signal si : std_logic_vector(4 downto 0) :="00000";
signal smo: std_logic_vector(4 downto 0);
signal se, s :std_logic_vector (0 downto 0);
begin
abs_1_0 : abs_1 port map (si=>si, smo=>smo, se=>se, s=>s);
process
begin
si<="10011";
se<="1";
s<="1";
wait for 5 ns;
si<="10011";
se<="0";
s<="1";
wait for 5 ns;
si<="10000";
se<="0";
s<="1";
wait for 5 ns;
si<="11011";
se<="0";
s<="1";
wait for 5 ns;
si<="11011";
se<="1";
s<="0";
wait for 5 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
055b6766305f2c12afeb8e16c122350d
| 0.534951 | 3.029412 | false | false | false | false |
LemurPwned/classic-fpga
|
encoders/one_hot_tb.vhdl
| 1 | 731 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity one_hot_tb is
end entity;
architecture behav of one_hot_tb is
component one_hot
port(
si : in std_logic_vector (6 downto 0);
so : out std_logic_vector (2 downto 0)
);
end component;
for one_hot_0 : one_hot use entity work.one_hot;
signal si : std_logic_vector(6 downto 0) := "0000000";
signal so : std_logic_vector(2 downto 0);
begin
one_hot_0 : one_hot port map (si=>si, so=>so);
process
begin
si<="0000000";
wait for 5 ns;
si<="0000001";
wait for 5 ns;
si<="0000100";
wait for 5 ns;
si<="0100000";
wait for 5 ns;
si<="1000000";
wait for 5 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
b405009843e2a0ceed7a39762b6d3150
| 0.632011 | 3.084388 | false | false | false | false |
LemurPwned/classic-fpga
|
counters/ring_counter.vhdl
| 1 | 717 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ring_counter is
port (
clk : in std_logic;
Q, Q2 : out std_logic_vector(3 downto 0)
);
end entity;
architecture ring_counter of ring_counter is
signal Qt1 : std_logic_vector(3 downto 0) :="0001";
signal Qt2 : std_logic_vector(3 downto 0) :="0000";
begin
process(clk)
begin
if rising_edge(clk) then
--Qt1 is one hot, Qt2 is Johnson
Qt1(0)<=Qt1(3);
Qt1(1)<=Qt1(0);
Qt1(2)<=Qt1(1);
Qt1(3)<=Qt1(2);
Qt2(0)<=not Qt2(3);
Qt2(1)<=Qt2(0);
Qt2(2)<=Qt2(1);
Qt2(3)<=Qt2(2);
end if;
end process;
Q<=Qt1;
Q2<=Qt2;
end architecture;
|
gpl-3.0
|
2102dd1ee6f728ad7a7bd69c24feff3e
| 0.569038 | 2.747126 | false | false | false | false |
LemurPwned/classic-fpga
|
abs_1.vhdl
| 1 | 2,019 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity abs_1 is
port (
si : in std_logic_vector(4 downto 0);
smo : out std_logic_vector(4 downto 0);
se : in std_logic_vector (0 downto 0);
s : in std_logic_vector (0 downto 0)
);
end entity;
architecture behav of abs_1 is
signal nsi : std_logic_vector(4 downto 0);
signal sum, sum2 : std_logic_vector(4 downto 0);
signal c : std_logic := '1';
signal t,f,g : std_logic := '0';
signal nse : std_logic_vector(0 downto 0);
signal smo1, smo2 : std_logic_vector(4 downto 0);
begin
-- s = 1 for convert
-- se = 1 select u1
nsi <= not si;
nse <= not se;
sum(0) <= si(0) xor s(0);
sum(1) <= si(1) xor s(0);
sum(2) <= si(2) xor s(0);
sum(3) <= si(3) xor s(0);
sum(4) <= si(4) xor s(0);
sum2(0) <= nsi(0) xor (not se(0));
sum2(1) <= nsi(1) xor nsi(0);
sum2(2) <= nsi(2) xor (nsi(0) and nsi(1));
sum2(3) <= nsi(3) xor (nsi(0) and nsi(1) and nsi(2));
sum2(4) <= nsi(4) xor (nsi(0) and nsi(1) and nsi(2) and nsi(3));
smo1(0) <= se(0) and sum(0);
smo1(1) <= se(0) and sum(1);
smo1(2) <= se(0) and sum(2);
smo1(3) <= se(0) and sum(3);
smo1(4) <= se(0) and sum(4);
smo2(0) <= nse(0) and sum2(0);
smo2(1) <= nse(0) and sum2(1);
smo2(2) <= nse(0) and sum2(2);
smo2(3) <= nse(0) and sum2(3);
smo2(4) <= nse(0) and sum2(4);
smo <= smo1 or smo2;
--c <='1';
--sum(0) <= nsi(0) xor c;
--t <= nsi(0) and c;
--sum(1) <= nsi(1) xor t;
--f <= nsi(1) and t;
--sum(2) <= nsi(2) xor f;
--g <= nsi(2) and f;
--sum(3) <= nsi(3) xor g;
--smo <= sum;
----only U2 for now
--sum(0) <= nsi(0) xor c;
--t <= sum(0) and c;
--sum(1) <= nsi(1) xor t;
--t <= sum(0) and sum(1);
--sum(2) <= nsi(2) xor t;
--t <= sum(2) and sum(1) and sum(1);
--sum(3) <= nsi(3) xor t;
--t <= sum(3) and t;
--smo(3) <= sum(3);
--smo(2) <= sum(2);
--smo(1) <= sum(1);
--smo(0) <= sum(0);
--smo <= nsi(3 downto 0);
end architecture;
|
gpl-3.0
|
2d29661fda3d5bea2cc06c1486aec4a2
| 0.509658 | 2.334104 | false | false | false | false |
LemurPwned/classic-fpga
|
memory/hist_tb.vhdl
| 1 | 1,398 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hist_tb is
end entity;
architecture hist_tb of hist_tb is
component hist is
port (
clk : in std_logic;
se : in std_logic;
z_addr : in std_logic_vector(1 downto 0);
i_addr : in std_logic_vector(1 downto 0);
we : in std_logic;
D : in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end component;
signal z_addr : std_logic_vector(1 downto 0):="00";
signal i_addr : std_logic_vector(1 downto 0):="00";
signal clk : std_logic :='1';
signal we, se : std_logic :='0';
signal Q, D : std_logic_vector(3 downto 0) := "0000";
constant period : time := 10 ns;
begin
mapping: hist port map(clk=>clk, se=>se, i_addr=>i_addr, z_addr=>z_addr,
we=>we, Q=>Q, D=>D);
clk_proc :
process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc : process
begin
we<='1';
se<='0';
wait for 20 ns;
se<='1';
wait for 40 ns;
se<='0';
wait for 20 ns;
i_addr<="10";
z_addr<="10";
wait for 10 ns;
se<='1';
wait for 40 ns;
i_addr<="00";
wait for 30 ns;
z_addr<="00";
se<='0';
wait for 10 ns;
i_addr<="10";
se<='1';
wait for 30 ns;
se<='0';
wait for 10 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
2e2750c0debc99416d3d388315a7f239
| 0.565093 | 3.019438 | false | false | false | false |
LemurPwned/classic-fpga
|
encoders/one_hot.vhdl
| 1 | 798 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity one_hot is
port(
si : in std_logic_vector (6 downto 0);
so : out std_logic_vector (2 downto 0)
);
end entity;
architecture behav of one_hot is
signal si_1 : std_logic_vector(6 downto 0);
begin
si_1 <= si;
so(0) <= si_1(0) or si_1(2) or si_1(4) or si_1(6);
so(1) <= si_1(1) or si_1(2) or si_1(5) or si_1(6);
so(2) <= si_1(3) or si_1(4) or si_1(5) or si_1(6);
--C LSB
--so(0) = (nso_1(2) and nso_1(1) and so_1(0)) and (nso_1(2) and so_1(1) and so_1(0)) and (so_1(2) and nso_1(1) and so_1(0)) and (so_1(2) and so_1(1) and so_1(0));
--so(1) = (nso_1(2) and so_1(1) and nso_1(0)) and (so_1(2) and so_1(1) and nso_1(0)) and (so_1(2) and so_1(1) and so_1(0));
--so(2) = (nso_1())
end architecture;
|
gpl-3.0
|
7c5c9cfe5553aa2339e1f1d3809ced81
| 0.571429 | 2.030534 | false | false | false | false |
WebClub-NITK/Hacktoberfest-2k17
|
vhdl/sqrt.vhd
| 2 | 1,542 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_unsigned.ALL;
entity squart is port(
clock : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(3 downto 0)); end squart;
architecture behaviour of squart is
signal part_done : std_logic := '0';
signal part_count : integer := 3;
signal result : std_logic_vector(4 downto 0) := "00000";
signal partialq : std_logic_vector(5 downto 0) := "000000";
begin
part_done_1: process(clock, data_in, part_done)
begin
if(clock'event and clock='1')then
if(part_done='0')then
if(part_count>=0)then
partialq(1 downto 0) <= data_in((part_count*2)+ 1 downto part_count*2);
part_done <= '1'; else
data_out <= result(3 downto 0);
end if;
part_count <= part_count - 1;
elsif(part_done='1')then
if((result(3 downto 0) & "01") <= partialq)then
result <= result(3 downto 0) & '1';
partialq(5 downto 2) <= partialq(3 downto 0) - (result(1 downto 0)&"01");
else
result <= result(3 downto 0) & '0';
partialq(5 downto 2) <= partialq(3 downto 0);
end if;
part_done <= '0';
end if;
end if;
end process;
end behaviour;
|
mit
|
25c51a1746e323b26bde49f42d398dd4
| 0.485733 | 3.742718 | false | false | false | false |
LemurPwned/classic-fpga
|
counters/counter.vhdl
| 1 | 716 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(
clk, res_as, up : in std_logic;
count : out std_logic_vector (3 downto 0)
);
end entity;
architecture behav of counter is
signal Q : std_logic_vector (3 downto 0) := "0000";
signal N : std_logic_vector (3 downto 0) := "1001";
signal t : std_logic;
begin
process (clk, res_as)
begin
if res_as = '1' or (Q(2)='1' and Q(0)='1') then
Q<=(others=>'0');
elsif rising_edge(clk) then
if up='1' then
Q<=Q+1;
elsif up='0' then
Q<=Q-1;
end if;
end if;
end process;
count <= Q;
end architecture;
|
gpl-3.0
|
921988fa26defd658bf88c6ce73f4e83
| 0.547486 | 3.210762 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/reg_file_controller.vhd
| 1 | 13,266 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 01:28:25 03/22/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: reg_file_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity reg_file_controller is
generic(
reg_num : integer := 32;
reg_width : integer := 32;
rf_addr_w : integer := 5;
data_bits : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
rx_din : in std_logic_vector(data_bits - 1 downto 0);
renew : in std_logic;
--led : out std_logic_vector(7 downto 0);
rx_req : out std_logic;
tx_req : out std_logic;
rf_req : out std_logic;
tx_dout : out std_logic_vector(data_bits - 1 downto 0);
rf_dout : out std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0)
);
end reg_file_controller;
architecture Behavioral of reg_file_controller is
constant iter : integer := integer(round(real(reg_width/4))) + 1;
type t_state is (idle, idle2, send_req, last, last2, parse, ignore);
signal state, state_next : t_state;
signal req_cnt, req_cnt_next : integer range 0 to 4;
signal reg_cnt, reg_cnt_next : integer range 0 to 31;
signal parse_mode, parse_mode_next : integer range 0 to 8; --iter;
signal tx_data, tx_data_next : std_logic_vector(data_bits - 1 downto 0);
signal tx_en, tx_en_next : std_logic;
signal rx_en, rx_en_next : std_logic;
signal reg_data, reg_data_next : std_logic_vector(15 downto 0);
signal din: std_logic_vector(7 downto 0);
signal rf_en, rf_en_next : std_logic;
signal addr, addr_next : std_logic_vector(rf_addr_w - 1 downto 0);
signal ren_sig : std_logic;
signal q0, q1, q2 : std_logic;
signal delay, delay_next : integer;
signal ig_first, ig_first_next : std_logic;
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= idle;
req_cnt <= 0;
reg_cnt <= 0;
parse_mode <= 0;
tx_data <=(others => '0');
tx_en <= '0';
rx_en <= '0';
reg_data <=(others => '0');
delay <= 0;
rf_en <= '0';
addr <=(others => '0');
ig_first <= '0';
else
state <= state_next;
req_cnt <= req_cnt_next;
reg_cnt <= reg_cnt_next;
parse_mode <= parse_mode_next;
tx_data <= tx_data_next;
tx_en <= tx_en_next;
rx_en <= rx_en_next;
reg_data <= reg_data_next;
delay <= delay_next;
rf_en <= rf_en_next;
addr <= addr_next;
ig_first <= ig_first_next;
end if;
end if;
end process;
routing : process (state, req_cnt, tx_data, tx_en, delay, reg_cnt, parse_mode, rx_en, reg_data, din, rf_en, addr, ig_first, ren_sig)
begin
state_next <= state;
req_cnt_next <= req_cnt;
reg_cnt_next <= reg_cnt;
parse_mode_next <= parse_mode;
tx_data_next <= tx_data;
tx_en_next <= tx_en;
rx_en_next <= rx_en;
reg_data_next <= reg_data;
delay_next <= delay;
rf_en_next <= rf_en;
addr_next <= addr;
ig_first_next <= ig_first;
case state is
when idle =>
if delay = 100000 then
state_next <= send_req;
delay_next <= 0;
tx_en_next <= '0';
else
delay_next <= delay + 1;
tx_en_next <= '0';
end if;
when send_req =>
case req_cnt is
when 0 =>
tx_data_next <= "01000000"; -- 40 = @
req_cnt_next <= 1;
tx_en_next <= '1';
when 1 =>
tx_data_next <= "01010010"; -- 52 = R
req_cnt_next <= 2;
tx_en_next <= '1';
when 2 =>
case reg_cnt is
when 0 =>
tx_data_next <= "00110000";
req_cnt_next <= 4;
tx_en_next <= '1';
when 1 =>
tx_data_next <= "00110001";
req_cnt_next <= 4;
tx_en_next <= '1';
when 2 =>
tx_data_next <= "00110010";
req_cnt_next <= 4;
tx_en_next <= '1';
when 3 =>
tx_data_next <= "00110011";
req_cnt_next <= 4;
tx_en_next <= '1';
when 4 =>
tx_data_next <= "00110100";
req_cnt_next <= 4;
tx_en_next <= '1';
when 5 =>
tx_data_next <= "00110101";
req_cnt_next <= 4;
tx_en_next <= '1';
when 6 =>
tx_data_next <= "00110110";
req_cnt_next <= 4;
tx_en_next <= '1';
when 7 =>
tx_data_next <= "00110111";
req_cnt_next <= 4;
tx_en_next <= '1';
when 8 =>
tx_data_next <= "00111000";
req_cnt_next <= 4;
tx_en_next <= '1';
when 9 =>
tx_data_next <= "00111001";
req_cnt_next <= 4;
tx_en_next <= '1';
when 10 =>
tx_data_next <= "01000001"; -- A
req_cnt_next <= 4;
tx_en_next <= '1';
when 11 =>
tx_data_next <= "01000010"; -- B
req_cnt_next <= 4;
tx_en_next <= '1';
when 12 =>
tx_data_next <= "01000011"; -- C
req_cnt_next <= 4;
tx_en_next <= '1';
when 13 =>
tx_data_next <= "01000100"; -- D
req_cnt_next <= 4;
tx_en_next <= '1';
when 14 =>
tx_data_next <= "01000101"; -- E
req_cnt_next <= 4;
tx_en_next <= '1';
when 15 =>
tx_data_next <= "01000110"; -- F
req_cnt_next <= 4;
tx_en_next <= '1';
when 16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31 =>
tx_data_next <= "00110001";
req_cnt_next <= 3;
tx_en_next <= '1';
end case;
when 3 =>
case reg_cnt is
when 16 =>
tx_data_next <= "00110000";
req_cnt_next <= 4;
tx_en_next <= '1';
when 17 =>
tx_data_next <= "00110001";
req_cnt_next <= 4;
tx_en_next <= '1';
when 18 =>
tx_data_next <= "00110010";
req_cnt_next <= 4;
tx_en_next <= '1';
when 19 =>
tx_data_next <= "00110011";
req_cnt_next <= 4;
tx_en_next <= '1';
when 20 =>
tx_data_next <= "00110100";
req_cnt_next <= 4;
tx_en_next <= '1';
when 21 =>
tx_data_next <= "00110101";
req_cnt_next <= 4;
tx_en_next <= '1';
when 22 =>
tx_data_next <= "00110110";
req_cnt_next <= 4;
tx_en_next <= '1';
when 23 =>
tx_data_next <= "00110111";
req_cnt_next <= 4;
tx_en_next <= '1';
when 24 =>
tx_data_next <= "00111000";
req_cnt_next <= 4;
tx_en_next <= '1';
when 25 =>
tx_data_next <= "00111001";
req_cnt_next <= 4;
tx_en_next <= '1';
when 26 =>
tx_data_next <= "01000001"; -- A
req_cnt_next <= 4;
tx_en_next <= '1';
when 27 =>
tx_data_next <= "01000010"; -- B
req_cnt_next <= 4;
tx_en_next <= '1';
when 28 =>
tx_data_next <= "01000011"; -- C
req_cnt_next <= 4;
tx_en_next <= '1';
when 29 =>
tx_data_next <= "01000100"; -- D
req_cnt_next <= 4;
tx_en_next <= '1';
when 30 =>
tx_data_next <= "01000101"; -- E
req_cnt_next <= 4;
tx_en_next <= '1';
when 31 =>
tx_data_next <= "01000110"; -- F
req_cnt_next <= 4;
tx_en_next <= '1';
when others => NULL;
end case;
when 4 =>
tx_data_next <= "00001010"; -- 10 = LF (\n)
req_cnt_next <= 0;
tx_en_next <= '1';
if reg_cnt = 31 then
state_next <= last;
reg_cnt_next <= 0;
else
state_next <= send_req;
reg_cnt_next <= reg_cnt + 1;
end if;
end case;
when last =>
state_next <= last2;
tx_data_next <= "00000000";
tx_en_next <= '1';
when last2 =>
if delay = 150000000 then
if ig_first = '1' then
state_next <= ignore;
else
state_next <= parse;
end if;
reg_cnt_next <= 0;
tx_en_next <= '0';
delay_next <= 0;
else delay_next <= delay + 1;
end if;
when ignore =>
if delay = 4 then
delay_next <= 0;
rx_en_next <= '0';
state_next <= parse;
else
delay_next <= delay + 1;
rx_en_next <= '1';
end if;
when parse =>
case parse_mode is
when 0 =>
if delay = 1 then
delay_next <= 0;
rx_en_next <= '0';
parse_mode_next <= 1;
addr_next <= std_logic_vector(to_unsigned(reg_cnt, rf_addr_w));
else
rx_en_next <= '1';
delay_next <= delay + 1;
end if;
when 1 =>
case din is
when "00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"|"00111000"|"00111001" =>
reg_data_next(15 downto 12) <= din(3 downto 0);
parse_mode_next <= 2;
when "01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000110" =>
reg_data_next(15 downto 12) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 2;
when "01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100110" =>
reg_data_next(15 downto 12) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 2;
when others => parse_mode_next <= 0;
end case;
when 2 =>
if delay = 1 then
delay_next <= 0;
rx_en_next <= '0';
parse_mode_next <= 3;
else
rx_en_next <= '1';
delay_next <= delay + 1;
end if;
when 3 =>
case din is
when "00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"|"00111000"|"00111001" =>
reg_data_next(11 downto 8) <= din(3 downto 0);
parse_mode_next <= 4;
when "01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000110" =>
reg_data_next(11 downto 8) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 4;
when "01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100110" =>
reg_data_next(11 downto 8) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 4;
when others => parse_mode_next <= 2;
end case;
when 4 =>
if delay = 1 then
delay_next <= 0;
rx_en_next <= '0';
parse_mode_next <= 5;
else
rx_en_next <= '1';
delay_next <= delay + 1;
end if;
when 5 =>
case din is
when "00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"|"00111000"|"00111001" =>
reg_data_next(7 downto 4) <= din(3 downto 0);
parse_mode_next <= 6;
when "01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000110" =>
reg_data_next(7 downto 4) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 6;
when "01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100110" =>
reg_data_next(7 downto 4) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 6;
when others => parse_mode_next <= 4;
end case;
when 6 =>
if delay = 1 then
delay_next <= 0;
rx_en_next <= '0';
parse_mode_next <= 7;
else
rx_en_next <= '1';
delay_next <= delay + 1;
end if;
when 7 =>
case din is
when "00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"|"00111000"|"00111001" =>
reg_data_next(3 downto 0) <= din(3 downto 0);
parse_mode_next <= 8;
when "01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000110" =>
reg_data_next(3 downto 0) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 8;
when "01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100110" =>
reg_data_next(3 downto 0) <= std_logic_vector(unsigned(din(3 downto 0)) + 9);
parse_mode_next <= 8;
when others => parse_mode_next <= 6;
end case;
when 8 =>
if delay = 2 then
rx_en_next <= '0';
parse_mode_next <= 0;
if reg_cnt = 31 then
state_next <= idle2;
delay_next <= integer'low;
reg_cnt_next <= 0;
else
state_next <= parse;
delay_next <= 0;
reg_cnt_next <= reg_cnt + 1;
end if;
else
rx_en_next <= '1';
delay_next <= delay + 1;
end if;
end case;
when idle2 =>
if delay = integer'high then
state_next <= idle;
delay_next <= 0;
else
if ren_sig = '1' then
state_next <= idle;
delay_next <= 0;
else
delay_next <= delay + 1;
end if;
end if;
tx_en_next <= '0';
rf_en_next <= '0';
ig_first_next <= '1';
end case;
end process;
renew_deb: process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
q0 <= '0';
q1 <= '0';
q2 <= '0';
else
q0 <= renew;
q1 <= q0;
q2 <= q1;
end if;
end if;
end process;
ren_sig <= q0 and q1 and (not q2);
tx_dout <= tx_data;
tx_req <= tx_en;
rx_req <= rx_en;
rf_req <= rf_en;
rf_addr <= addr;
rf_dout <= reg_data;
din <= rx_din;
end Behavioral;
|
mit
|
75e2453a7fe716a376aab2bee392beff
| 0.50701 | 2.942768 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/switch_controller.vhd
| 1 | 1,507 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 12:57:00 05/08/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: switch_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
sw0 : in std_logic;
sw1 : in std_logic;
sw2 : in std_logic;
sw3 : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end switch_controller;
architecture Behavioral of switch_controller is
begin
rf_addr <= "01010";
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
led(3 downto 0) <= "0000";
else
if rf_data(3) = '1' then
led(0) <= sw0;
else
led(0) <= '0';
end if;
if rf_data(7) = '1' then
led(1) <= sw1;
else
led(1) <= '0';
end if;
if rf_data(11) = '1' then
led(2) <= sw2;
else
led(2) <= '0';
end if;
if rf_data(15) = '1' then
led(3) <= sw3;
else
led(3) <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
cd596db34c182963576e28e23e19cb48
| 0.523557 | 2.937622 | false | false | false | false |
LemurPwned/classic-fpga
|
machines/seq_det.vhdl
| 1 | 1,145 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seq_det is
port(
clk : in std_logic;
reset : in std_logic;
seq : in std_logic;
det : out std_logic
);
end entity;
architecture seq_det of seq_det is
type state_type is (A,B,C,D);
signal state : state_type := A;
begin
process(clk)
begin
if reset='1' then
det<='0';
state<=A;
elsif rising_edge(clk) then
case state is
when A =>
det<='0';
if seq = '0' then
state<=A;
else
state<=B;
end if;
when B =>
if seq = '0' then
state<=C;
else
state<=B;
end if;
when C =>
if seq = '0' then
state<=A;
else
state<=D;
end if;
when D=>
if seq = '0' then
state<=C;
else
state<=A;
det<='1';
end if;
when others => NULL;
end case;
end if;
end process;
end architecture;
|
gpl-3.0
|
29f04afae0fa2acad34e51bda601360e
| 0.425328 | 3.90785 | false | false | false | false |
14bmkelley/Environmental-Mouse
|
clk_div.vhdl
| 1 | 1,786 |
----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: bryan mealy
--
-- Create Date: 15:27:40 12/27/2010
-- Design Name:
-- Module Name: clk_div.vhd
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This divides the input clock frequency into a slower
-- frequency. The frequency is set by the the MAX_COUNT
-- constant in the declarative region of the architecture.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------------
-- Module to divide the clock
-----------------------------------------------------------------------
entity clk_div2 is
Port (clk : in std_logic;
sclk : out std_logic);
end clk_div2;
architecture my_clk_div of clk_div2 is
constant max_count : integer := (3000); --changed from 3000000 on 12/3/15 by The Group Formerly Known as Queen
signal tmp_clk : std_logic := '0';
begin
my_div: process (clk,tmp_clk)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = MAX_COUNT) then
tmp_clk <= not tmp_clk;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
sclk <= tmp_clk;
end process my_div;
end my_clk_div;
|
gpl-2.0
|
776d325b862429e2a0f79523dc89585d
| 0.451848 | 4.420792 | false | false | false | false |
LemurPwned/classic-fpga
|
memory/lifo_tb.vhdl
| 1 | 1,086 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lifo_tb is
end entity;
architecture lifo_tb of lifo_tb is
component lifo is
port (
x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0);
clk : in std_logic;
wr : in std_logic;
empty, full : out std_logic
);
end component;
signal x : std_logic_vector(3 downto 0) := "0000";
signal y : std_logic_vector(3 downto 0) := "0000";
signal clk : std_logic := '1';
signal wr : std_logic := '0';
signal empty : std_logic := '0';
signal full : std_logic := '0';
constant period : time := 10 ns;
begin
mapping: lifo port map(clk=>clk, x=>x, y=>y, wr=>wr,
empty=>empty, full=>full);
clk_proc : process
begin
clk <= not clk;
wait for period/2;
end process;
stim_proc: process
begin
wait for 3 ns;
x<="0100";
wr<='1';
wait for period;
x<="1100";
wait for period;
wr<='0';
wait for period;
--wr<='0';
--re<='1';
wait;
end process;
end architecture;
|
gpl-3.0
|
e574100b55764fdd80900176a1006f02
| 0.594843 | 3.129683 | false | false | false | false |
LemurPwned/classic-fpga
|
counters/ring_counter_tb.vhdl
| 1 | 572 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ring_counter_tb is
end entity;
architecture ring_counter_tb of ring_counter_tb is
component ring_counter is
port (
clk : in std_logic;
Q, Q2 : out std_logic_vector(3 downto 0)
);
end component;
signal clk : std_logic :='1';
signal Q, Q2 : std_logic_vector(3 downto 0);
constant period : time:= 10 ns;
begin
uut: ring_counter port map (clk=>clk, Q=>Q, Q2=>Q2);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
end architecture;
|
gpl-3.0
|
b22aad718ec616190ca09c85f1cf360c
| 0.674825 | 3.042553 | false | false | false | false |
freecores/yavga
|
vhdl/yavga_pkg.vhd
| 1 | 6,696 |
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package yavga_pkg is
-- Declare constants
-- chars address and data bus size
constant c_CHR_ADDR_BUS_W : integer := 11;
constant c_CHR_DATA_BUS_W : integer := 32;
constant c_CHR_WE_BUS_W : integer := 4;
-- internal used chars address and data bus size
constant c_INTCHR_ADDR_BUS_W : integer := 13;
constant c_INTCHR_DATA_BUS_W : integer := 8;
-- internal ROM chmaps address and data bus
constant c_INTCHMAP_ADDR_BUS_W : integer := 11;
constant c_INTCHMAP_DATA_BUS_W : integer := 8;
-- waveform address and data bus size
constant c_WAVFRM_ADDR_BUS_W : integer := 10;
constant c_WAVFRM_DATA_BUS_W : integer := 16;
constant c_GRID_SIZE : std_logic_vector(6 downto 0) := "1111111";
constant c_GRID_BIT : integer := 6;
--
-- horizontal timing signals (in pixels count )
constant c_H_DISPLAYpx : integer := 800;
constant c_H_BACKPORCHpx : integer := 63; -- also 60;
constant c_H_SYNCTIMEpx : integer := 120;
constant c_H_FRONTPORCHpx : integer := 56; --also 60;
constant c_H_PERIODpx : integer := c_H_DISPLAYpx +
c_H_BACKPORCHpx +
c_H_SYNCTIMEpx +
c_H_FRONTPORCHpx;
constant c_H_COUNT_W : integer := 11; -- = ceil(ln2(c_H_PERIODpx))
--
-- vertical timing signals (in lines count)
constant c_V_DISPLAYln : integer := 600;
constant c_V_BACKPORCHln : integer := 23;
constant c_V_SYNCTIMEln : integer := 6;
constant c_V_FRONTPORCHln : integer := 37;
constant c_V_PERIODln : integer := c_V_DISPLAYln +
c_V_BACKPORCHln +
c_V_SYNCTIMEln +
c_V_FRONTPORCHln;
constant c_V_COUNT_W : integer := 10; -- = ceil(ln2(c_V_PERIODln))
constant c_X_W : integer := c_H_COUNT_W;
constant c_Y_W : integer := c_V_COUNT_W;
-- constant c_CHARS_WIDTH: std_logic_vector(2 downto 0) := "111";
-- constant c_CHARS_HEIGHT: std_logic_vector(3 downto 0) := "1111";
-- constant c_CHARS_COLS: std_logic_vector(6 downto 0) := "1100011";
-- constant c_CHARS_ROWS: std_logic_vector(5 downto 0) := "100100";
-- to manage the background and cursor colors
constant c_CFG_BG_CUR_COLOR_ADDR : std_logic_vector(12 downto 0) := "0000001101100"; -- 108 BG:5..3 CUR:2..0
-- to manage the cursor position
constant c_CFG_CURS_XY1 : std_logic_vector(12 downto 0) := "0000001101101"; -- 109
constant c_CFG_CURS_XY2 : std_logic_vector(12 downto 0) := "0000001101110"; -- 110
constant c_CFG_CURS_XY3 : std_logic_vector(12 downto 0) := "0000001101111"; -- 111
end yavga_pkg;
package body yavga_pkg is
end yavga_pkg;
|
bsd-3-clause
|
0766cfad08de29bd78d3658539553c6d
| 0.452061 | 4.656467 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/led_controller.vhd
| 1 | 2,156 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 14:34:10 05/08/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: led_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity led_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end led_controller;
architecture Behavioral of led_controller is
type t_state is (read1, read2, read3, idle);
signal state, state_next : t_state;
signal delay, delay_next : integer range 0 to 2147483647;
signal addr, addr_next : std_logic_vector(rf_addr_w - 1 downto 0);
signal sum, sum_next : std_logic_vector(reg_width - 1 downto 0);
begin
registers : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
state <= idle;
delay <= 0;
addr <= (others => '0');
sum <= (others => '0');
else
state <= state_next;
delay <= delay_next;
addr <= addr_next;
sum <= sum_next;
end if;
end if;
end process;
--reg 5 & 17 or 0
routing : process (state, delay, rf_data, addr, sum)
begin
state_next <= state;
delay_next <= delay;
addr_next <= addr;
sum_next <= sum;
case state is
when read1 =>
sum_next <= rf_data;
addr_next <= "10001";
state_next <= read2;
when read2 =>
sum_next <= sum and rf_data;
addr_next <= "00000";
state_next <= read3;
when read3 =>
sum_next <= sum or rf_data;
state_next <= idle;
when idle =>
if delay = 100 then
delay_next <= 0;
state_next <= read1;
addr_next <= "00101";
else delay_next <= delay + 1;
end if;
end case;
end process;
led <= sum(3 downto 0);
rf_addr <= addr;
end Behavioral;
|
mit
|
d6a7edd9cf6460349a34566eb1481372
| 0.569109 | 3.129173 | false | false | false | false |
freecores/yavga
|
vhdl/chars_RAM.vhd
| 1 | 12,750 |
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity chars_RAM is
port (
i_clock_rw : in std_logic; -- Write Clock
i_EN_rw : in std_logic; -- Write RAM Enable Input
i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0); -- Write Enable Input
i_ADDR_rw : in std_logic_vector(10 downto 0); -- Write 11-bit Address Input
i_DI_rw : in std_logic_vector(31 downto 0); -- Write 32-bit Data Input
o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input
i_SSR : in std_logic; -- Synchronous Set/Reset Input
i_clock_r : in std_logic; -- Read Clock
i_EN_r : in std_logic;
i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input
o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output
);
end chars_RAM;
architecture Behavioral of chars_RAM is
signal s0_DO_r : std_logic_vector(7 downto 0);
signal s1_DO_r : std_logic_vector(7 downto 0);
signal s2_DO_r : std_logic_vector(7 downto 0);
signal s3_DO_r : std_logic_vector(7 downto 0);
constant c_ram_size : natural := 2**(c_CHR_ADDR_BUS_W);
type t_ram is array (c_ram_size-1 downto 0) of
std_logic_vector (c_INTCHR_DATA_BUS_W - 1 downto 0);
shared variable v_ram0 : t_ram := (
27 => X"05", -- config "bg and curs color" (108/4 = 27)
768 => X"00", 769 => X"04", 770 => X"08", 771 => X"0C",
772 => X"10", 773 => X"14", 774 => X"18", 775 => X"1C",
1024 => X"20", 1025 => X"24", 1026 => X"28", 1027 => X"2C",
1028 => X"30", 1029 => X"34", 1030 => X"38", 1031 => X"3C",
1032 => X"40", 1033 => X"44", 1034 => X"48", 1035 => X"4C",
1036 => X"50", 1037 => X"54", 1038 => X"58", 1039 => X"5C",
1040 => X"60", 1041 => X"64", 1042 => X"68", 1043 => X"6C",
1044 => X"70", 1045 => X"74", 1046 => X"78", 1047 => X"7C",
1126 => X"53", -- S
1127 => X"72", -- r
1128 => X"6D", -- m
1129 => X"20", --
1130 => X"64", -- d
1131 => X"6D", -- m
1132 => X"65", -- e
1133 => X"61", -- a
1134 => X"6E", -- n
others => X"00"
);
shared variable v_ram1 : t_ram := (
27 => X"07", -- config "xy coords spans on three bytes" (108/4 = 27)
768 => X"01", 769 => X"05", 770 => X"09", 771 => X"0D",
772 => X"11", 773 => X"15", 774 => X"19", 775 => X"1D",
1024 => X"21", 1025 => X"25", 1026 => X"29", 1027 => X"2D",
1028 => X"31", 1029 => X"35", 1030 => X"39", 1031 => X"3D",
1032 => X"41", 1033 => X"45", 1034 => X"49", 1035 => X"4D",
1036 => X"51", 1037 => X"55", 1038 => X"59", 1039 => X"5D",
1040 => X"61", 1041 => X"65", 1042 => X"69", 1043 => X"6D",
1044 => X"71", 1045 => X"75", 1046 => X"79", 1047 => X"7D",
1126 => X"61", -- a
1127 => X"6F", -- o
1128 => X"61", -- a
1129 => X"2D", -- -
1130 => X"72", -- r
1131 => X"74", -- t
1132 => X"74", -- t
1133 => X"70", -- p
1134 => X"65", -- e
others => X"00"
);
shared variable v_ram2 : t_ram := (
27 => X"09", -- config "xy coords spans on three bytes" (108/4 = 27)
768 => X"02", 769 => X"06", 770 => X"0A", 771 => X"0E",
772 => X"12", 773 => X"16", 774 => X"1A", 775 => X"1E",
1024 => X"22", 1025 => X"26", 1026 => X"2A", 1027 => X"2E",
1028 => X"32", 1029 => X"36", 1030 => X"3A", 1031 => X"3E",
1032 => X"42", 1033 => X"46", 1034 => X"4A", 1035 => X"4E",
1036 => X"52", 1037 => X"56", 1038 => X"5A", 1039 => X"5E",
1040 => X"62", 1041 => X"66", 1042 => X"6A", 1043 => X"6E",
1044 => X"72", 1045 => X"76", 1046 => X"7A", 1047 => X"7E",
1126 => X"6E", -- n
1127 => X"20", --
1128 => X"74", -- t
1129 => X"20", --
1130 => X"6F", -- o
1131 => X"40", -- @
1132 => X"73", -- s
1133 => X"65", -- e
1134 => X"74", -- t
others => X"00"
);
shared variable v_ram3 : t_ram := (
27 => X"5E", -- config "xy coords spans on three bytes" (108/4 = 27)
768 => X"03", 769 => X"07", 770 => X"0B", 771 => X"0F",
772 => X"13", 773 => X"17", 774 => X"1B", 775 => X"1F",
1024 => X"23", 1025 => X"27", 1026 => X"2B", 1027 => X"2F",
1028 => X"33", 1029 => X"37", 1030 => X"3B", 1031 => X"3F",
1032 => X"43", 1033 => X"47", 1034 => X"4B", 1035 => X"4F",
1036 => X"53", 1037 => X"57", 1038 => X"5B", 1039 => X"5F",
1040 => X"63", 1041 => X"67", 1042 => X"6B", 1043 => X"6F",
1044 => X"73", 1045 => X"77", 1046 => X"7B", 1047 => X"7F",
1126 => X"64", -- d
1127 => X"41", -- A
1128 => X"6F", -- o
1129 => X"73", -- s
1130 => X"61", -- a
1131 => X"6E", -- n
1132 => X"63", -- c
1133 => X"2E", -- .
1134 => X"20", --
others => X"00"
);
begin
p_rw0_port : process (i_clock_rw)
begin
if rising_edge(i_clock_rw) then
if i_SSR = '1' then
o_DI_rw(31 downto 24) <= (others => '0');
elsif (i_EN_rw = '1') then
o_DI_rw(31 downto 24) <= v_ram0(conv_integer(i_ADDR_rw));
if (i_WE_rw(0) = '1') then
v_ram0(conv_integer(i_ADDR_rw)) := i_DI_rw(31 downto 24);
end if;
end if;
end if;
end process;
p_rw1_port : process (i_clock_rw)
begin
if rising_edge(i_clock_rw) then
if i_SSR = '1' then
o_DI_rw(23 downto 16) <= (others => '0');
elsif (i_EN_rw = '1') then
o_DI_rw(23 downto 16) <= v_ram1(conv_integer(i_ADDR_rw));
if (i_WE_rw(1) = '1') then
v_ram1(conv_integer(i_ADDR_rw)) := i_DI_rw(23 downto 16);
end if;
end if;
end if;
end process;
p_rw2_port : process (i_clock_rw)
begin
if rising_edge(i_clock_rw) then
if i_SSR = '1' then
o_DI_rw(15 downto 8) <= (others => '0');
elsif (i_EN_rw = '1') then
o_DI_rw(15 downto 8) <= v_ram2(conv_integer(i_ADDR_rw));
if (i_WE_rw(2) = '1') then
v_ram2(conv_integer(i_ADDR_rw)) := i_DI_rw(15 downto 8);
end if;
end if;
end if;
end process;
p_rw3_port : process (i_clock_rw)
begin
if rising_edge(i_clock_rw) then
if i_SSR = '1' then
o_DI_rw(7 downto 0) <= (others => '0');
elsif (i_EN_rw = '1') then
o_DI_rw(7 downto 0) <= v_ram3(conv_integer(i_ADDR_rw));
if (i_WE_rw(3) = '1') then
v_ram3(conv_integer(i_ADDR_rw)) := i_DI_rw(7 downto 0);
end if;
end if;
end if;
end process;
p_ro0_port : process (i_clock_r)
begin
if rising_edge(i_clock_r) then
if i_SSR = '1' then
s0_DO_r <= (others => '0');
elsif (i_EN_r = '1') then
s0_DO_r <= v_ram0(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
end if;
end if;
end process;
p_ro1_port : process (i_clock_r)
begin
if rising_edge(i_clock_r) then
if i_SSR = '1' then
s1_DO_r <= (others => '0');
elsif (i_EN_r = '1') then
s1_DO_r <= v_ram1(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
end if;
end if;
end process;
p_ro2_port : process (i_clock_r)
begin
if rising_edge(i_clock_r) then
if i_SSR = '1' then
s2_DO_r <= (others => '0');
elsif (i_EN_r = '1') then
s2_DO_r <= v_ram2(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
end if;
end if;
end process;
p_ro3_port : process (i_clock_r)
begin
if rising_edge(i_clock_r) then
if i_SSR = '1' then
s3_DO_r <= (others => '0');
elsif (i_EN_r = '1') then
s3_DO_r <= v_ram3(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
end if;
end if;
end process;
o_DO_r <=
s0_DO_r when i_ADDR_r(1 downto 0) = "00" else
s1_DO_r when i_ADDR_r(1 downto 0) = "01" else
s2_DO_r when i_ADDR_r(1 downto 0) = "10" else
s3_DO_r when i_ADDR_r(1 downto 0) = "11" else
(others => 'X');
end Behavioral;
|
bsd-3-clause
|
713b95a330ab8b742f7f9c9c8ffc8d28
| 0.420392 | 3.375695 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/piso_tb.vhdl
| 1 | 999 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity piso_tb is
end entity;
architecture behav of piso_tb is
component piso is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
D : in std_logic_vector(3 downto 0);
Din : in std_logic;
Q : out std_logic :='0'
);
end component;
for piso_0 : piso use entity work.piso;
signal clk, Din, Q : std_logic :='0';
signal D : std_logic_vector(3 downto 0);
signal se : std_logic_vector(1 downto 0);
constant period : time := 10 ns;
begin
piso_0 : piso port map (clk=>clk, se=>se, D=>D, Din=>Din, Q=>Q);
clk_process:
process
begin
clk <= not clk;
wait for period/2;
end process;
stim_proc:
process
begin
D<="1101";
se<="01";
wait for 5 ns;
se<="10";
wait for 50 ns;
se<="01";
wait for 10 ns;
Din<='1';
se<="10";
wait for 80 ns;
wait ;
end process;
end architecture;
|
gpl-3.0
|
42ee8397cd9a0e965338a70fb54b6b76
| 0.575576 | 3.212219 | false | false | false | false |
LemurPwned/classic-fpga
|
memory/hist.vhdl
| 1 | 1,097 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hist is
port (
clk : in std_logic;
se : in std_logic;
z_addr : in std_logic_vector(1 downto 0);
i_addr : in std_logic_vector(1 downto 0);
we : in std_logic;
D : in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end entity;
architecture hist of hist is
type ram_type is array(6 downto 0) of std_logic_vector(3 downto 0);
signal ram : ram_type := ("0000","0000","0000","0000","0000","0000","0000");
signal Qt : std_logic_vector(3 downto 0) :="0000";
begin
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
if se = '1' then
--1 for increment, 0 for zeroing
Q<=ram(conv_integer(i_addr)) + 1;
ram(conv_integer((i_addr)))<=ram(conv_integer((i_addr))) + 1;
elsif se = '0' then
--addr<=z_addr;
Q<=ram(conv_integer((z_addr)));
ram(conv_integer((z_addr)))<="0000";
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
b901ff5da78f1537a9306b8e11d030b3
| 0.571559 | 3.188953 | false | false | false | false |
elainemielas/CVUT_THESIS
|
Spartan-3E/rate_generator.vhd
| 1 | 1,715 |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 15:21:19 03/20/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: rate_generator - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rate_generator is
generic(
dvsr : integer := 2604
-- divisor = 50000000 / (16 * baud)
-- 1200 -> 2604 +
-- 2400 -> 1302 +
-- 4800 -> 651 +
-- 9600 -> 326
-- 19200 -> 163
-- 38400 -> 81
-- 57600 -> 54 +
-- 115200 -> 27 +
-- 230400 -> 14
-- 460800 -> 7
-- 500000 -> 6
-- 576000 -> 5
-- 921600 -> 3
-- 1000000 -> 3 +
-- 1152000 -> 3
-- 1500000 -> 2 +
-- 2000000 -> 2
-- 2500000 -> 1
-- 3000000 -> 1 +
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : out std_logic
);
end rate_generator;
architecture Behavioral of rate_generator is
signal b_count : integer range 1 to dvsr := 1;
begin
b_clock : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
b_count <= 1;
b_edge <= '0';
elsif b_count = dvsr then
b_count <= 1;
b_edge <= '1';
else
b_count <= b_count + 1;
b_edge <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
3427f5d21315ddf1ea152bdda5135547
| 0.553353 | 3.369352 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/sipo_tb.vhdl
| 1 | 997 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo_tb is
end entity;
architecture arch of sipo_tb is
component sipo is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
D : in std_logic_vector(3 downto 0);
Dl, Dr : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end component;
for sipo_0 : sipo use entity work.sipo;
signal clk : std_logic :='1';
signal Q, D : std_logic_vector(3 downto 0);
signal Dl, Dr : std_logic;
signal se : std_logic_vector(1 downto 0);
constant period : time := 10 ns;
begin
sipo_0 : sipo port map (clk=>clk, D=>D, Dr=>Dr, Dl=>Dl, Q=>Q, se=>se);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc:
process
begin
se<="00";
D<="1011";
Dl<='1';
Dr<='1';
wait for 35 ns;
se<="01";
wait for 20 ns;
se<="11";
wait for 15 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
920448c28fc0191c7a1879f5a2463a61
| 0.591775 | 3.039634 | false | false | false | false |
LemurPwned/classic-fpga
|
memory/lifo.vhdl
| 1 | 1,095 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lifo is
port (
x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) :="0000";
clk : in std_logic;
wr : in std_logic; -- wr =1 to write wr = 0 to read
empty, full : out std_logic :='0'
);
end entity;
architecture lifo of lifo is
type ram_type is array(5 downto 0) of std_logic_vector(3 downto 0);
signal lifo : ram_type :=("0000","0000","0000","0000","0000","0000");
signal last : integer range -1 to 5 := -1;
begin
process(clk)
begin
if rising_edge(clk) then
if wr = '1' then
if last < 5 then
lifo(last+1)<=x;
last <= last +1;
if last = 5 then
full <= '1';
end if;
end if;
elsif wr = '0' then
if last > -1 then
y<=lifo(last);
last <= last -1;
if last = -1 then
empty <= '1';
end if;
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
ede7722d4872ee603a170a7b13178ffb
| 0.523288 | 3.390093 | false | false | false | false |
LemurPwned/classic-fpga
|
machines/compar_fsm.vhdl
| 1 | 1,473 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity compar_fsm is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector(1 downto 0);
--this is pair of bits of two numbers, a0b0, a1b1, etc.., easier to process
o: out std_logic_vector(1 downto 0)
-- 00 is equal, 10 a is bigger, 01 b is bigger
);
end entity;
architecture compar_fsm of compar_fsm is
type state_type is (A,B,C);
signal state : state_type := C;
begin
process(clk)
begin
if reset = '1' then
state<=C;
o<="00";
elsif rising_edge(clk) then
case state is
when C =>
o<="00";
if (ab(0)='1' and ab(1)='0') then
state<=B;
o<="01";
elsif (ab(0)='0' and ab(1)='1') then
state<=A;
o<="10";
else
state<=C;
end if;
when B =>
o<="01";
if (ab(0)='0' and ab(1)='1') then
state<=A;
o<="10";
else
state<=B;
o<="01";
end if;
when A =>
o<="10";
if (ab(0)='1' and ab(1)='0') then
state<=B;
o<="01";
else
state<=A;
o<="10";
end if;
when others => NULL;
end case;
end if;
end process;
end architecture;
|
gpl-3.0
|
c63b0d0690297ab14814f281e2d6ec74
| 0.430414 | 3.64604 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/reg_adder.vhdl
| 1 | 769 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_adder is
port (
A, B: in std_logic_vector (3 downto 0);
clk : in std_logic;
se : in std_logic;
C: out std_logic_vector(3 downto 0);
over : out std_logic
);
end entity;
architecture reg_adder of reg_adder is
signal a1,b1, o: std_logic_vector(3 downto 0) := "0000";
signal c1, ci: std_logic :='0';
begin
process(clk)
begin
if rising_edge(clk) then
if se='1' then
a1<= A;
b1<= B;
else
c1<=a1(0) xor b1(0) xor ci;
ci<=a1(0) and b1(0);
a1<= '0'&a1(3 downto 1);
b1<= '0'&b1(3 downto 1);
o<=c1&o(3 downto 1);
end if;
end if;
end process;
over<=ci;
C<=o;
end architecture;
|
gpl-3.0
|
9d739cf8d1296c032c915140387582b0
| 0.564369 | 2.72695 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/multi_oc_tb.vhdl
| 1 | 781 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multi_oc_tb is
end entity;
architecture behav of multi_oc_tb is
component multi_oc
port(
si : in std_logic_vector (3 downto 0);
se : in std_logic_vector (1 downto 0);
so : out std_logic
);
end component;
for multi_oc_0 : multi_oc use entity work.multi_oc;
signal si : std_logic_vector (3 downto 0);
signal se : std_logic_vector (1 downto 0);
signal so : std_logic;
begin
multi_oc_0 : multi_oc port map (si=>si, se=>se, so=>so);
process
begin
si<="1110";
se<="10";
wait for 5 ns;
si<="1110";
se<="00";
wait for 5 ns;
si<="1110";
se<="01";
wait for 5 ns;
si<="1110";
se<="11";
wait for 5 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
131b8b123fbdc577fc0c5600aef73a4d
| 0.614597 | 2.980916 | false | false | false | false |
LemurPwned/classic-fpga
|
multiplexers_registers/piso.vhdl
| 1 | 584 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity piso is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
D : in std_logic_vector(3 downto 0);
Din : in std_logic;
Q : out std_logic :='0'
);
end entity;
architecture arch of piso is
signal Qt : std_logic_vector (3 downto 0) := "0000";
begin
process(clk)
begin
if rising_edge(clk) then
if se(0) = '1' then
Qt<= D;
else
Qt(3 downto 0)<= Qt(2 downto 0) & Din;
end if;
end if;
Q<=Qt(3);
end process;
end architecture;
|
gpl-3.0
|
78dd2cded8f05b48238b8ee27e5ceea9
| 0.599315 | 2.979592 | false | false | false | false |
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