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cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/p2l_dma_bench.vhd
| 1 | 24,348 |
library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
entity p2l_dma_bench is
generic (
constant period : time := 100 ns;
constant axis_data_width_c : integer := 64;
constant wb_address_width_c : integer := 12;
constant wb_data_width_c : integer := 64
);
--port ();
end p2l_dma_bench;
architecture Behavioral of p2l_dma_bench is
signal clk_tbs : STD_LOGIC;
signal rst_tbs : STD_LOGIC;
signal rst_n_tbs : STD_LOGIC;
-- Test bench specific signals
signal step : integer;
-- From the DMA controller
signal dma_ctrl_target_addr_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_host_addr_h_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_host_addr_l_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_len_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_start_p2l_tbs : std_logic;
signal dma_ctrl_start_next_tbs : std_logic;
signal dma_ctrl_done_s : std_logic;
signal dma_ctrl_error_s : std_logic;
signal dma_ctrl_byte_swap_tbs : std_logic_vector(2 downto 0);
signal dma_ctrl_abort_tbs : std_logic;
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
--signal pd_pdm_hdr_start_tbs : std_logic; -- Header strobe
--signal pd_pdm_hdr_length_tbs : std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
--signal pd_pdm_hdr_cid_tbs : std_logic_vector(1 downto 0); -- Completion ID
signal pd_pdm_master_cpld_tbs : std_logic; -- Master read completion with data
signal pd_pdm_master_cpln_tbs : std_logic; -- Master read completion without data
--
-- Data
signal pd_pdm_data_valid_tbs : std_logic; -- Indicates Data is valid
signal pd_pdm_data_valid_w_tbs: std_logic_vector(1 downto 0);
signal pd_pdm_data_last_tbs : std_logic; -- Indicates end of the packet
signal pd_pdm_data_tbs : std_logic_vector(wb_data_width_c-1 downto 0); -- Data
signal pd_pdm_be_tbs : std_logic_vector(7 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L control
signal p2l_rdy_s : std_logic; -- De-asserted to pause transfer already in progress
signal rx_error_s : std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
signal pdm_arb_tvalid_s : std_logic; -- Read completion signals
signal pdm_arb_tlast_s : std_logic; -- Toward the arbiter
signal pdm_arb_tdata_s : std_logic_vector(wb_data_width_c-1 downto 0);
signal pdm_arb_tkeep_s : std_logic_vector(7 downto 0);
signal pdm_arb_req_s : std_logic;
signal arb_pdm_gnt_tbs : std_logic;
-- DMA Interface (Pipelined Wishbone)
signal p2l_dma_adr_s : std_logic_vector(32-1 downto 0);
signal p2l_dma_dat_s2m_s : std_logic_vector(wb_data_width_c-1 downto 0);
signal p2l_dma_dat_m2s_s : std_logic_vector(wb_data_width_c-1 downto 0);
signal p2l_dma_sel_s : std_logic_vector(7 downto 0);
signal p2l_dma_cyc_s : std_logic;
signal p2l_dma_stb_s : std_logic;
signal p2l_dma_we_s : std_logic;
signal p2l_dma_ack_s : std_logic;
signal p2l_dma_stall_tbs : std_logic;
signal l2p_dma_cyc_tbs : std_logic;
---------------------------------------------------------
-- To the DMA controller
signal next_item_carrier_addr_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_h_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_l_s : std_logic_vector(31 downto 0);
signal next_item_len_s : std_logic_vector(31 downto 0);
signal next_item_next_l_s : std_logic_vector(31 downto 0);
signal next_item_next_h_s : std_logic_vector(31 downto 0);
signal next_item_attrib_s : std_logic_vector(31 downto 0);
signal next_item_valid_s : std_logic;
component p2l_dma_master is
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(31 downto 0);
dma_ctrl_len_i : in std_logic_vector(31 downto 0);
dma_ctrl_start_p2l_i : in std_logic;
dma_ctrl_start_next_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
--pd_pdm_hdr_start_i : in std_logic; -- Header strobe
--pd_pdm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
--pd_pdm_hdr_cid_i : in std_logic_vector(1 downto 0); -- Completion ID
pd_pdm_master_cpld_i : in std_logic; -- Master read completion with data
pd_pdm_master_cpln_i : in std_logic; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i : in std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_i: in std_logic_vector(1 downto 0); -- Indicates Data is valid
pd_pdm_data_last_i : in std_logic; -- Indicates end of the packet
pd_pdm_data_i : in std_logic_vector(63 downto 0); -- Data
pd_pdm_be_i : in std_logic_vector(7 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o : out std_logic; -- De-asserted to pause transfer already in progress
rx_error_o : out std_logic; -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o : out std_logic; -- Read completion signals
pdm_arb_tlast_o : out std_logic; -- Toward the arbiter
pdm_arb_tdata_o : out std_logic_vector(63 downto 0);
pdm_arb_tkeep_o : out std_logic_vector(7 downto 0);
pdm_arb_req_o : out std_logic;
arb_pdm_gnt_i : in std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i : in std_logic; -- Bus clock
p2l_dma_adr_o : out std_logic_vector(31 downto 0); -- Adress
p2l_dma_dat_i : in std_logic_vector(63 downto 0); -- Data in
p2l_dma_dat_o : out std_logic_vector(63 downto 0); -- Data out
p2l_dma_sel_o : out std_logic_vector(7 downto 0); -- Byte select
p2l_dma_cyc_o : out std_logic; -- Read or write cycle
p2l_dma_stb_o : out std_logic; -- Read or write strobe
p2l_dma_we_o : out std_logic; -- Write
p2l_dma_ack_i : in std_logic; -- Acknowledge
p2l_dma_stall_i : in std_logic; -- for pipelined Wishbone
l2p_dma_cyc_i : in std_logic; -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o : out std_logic_vector(31 downto 0);
next_item_host_addr_h_o : out std_logic_vector(31 downto 0);
next_item_host_addr_l_o : out std_logic_vector(31 downto 0);
next_item_len_o : out std_logic_vector(31 downto 0);
next_item_next_l_o : out std_logic_vector(31 downto 0);
next_item_next_h_o : out std_logic_vector(31 downto 0);
next_item_attrib_o : out std_logic_vector(31 downto 0);
next_item_valid_o : out std_logic
);
end component;
component bram_wbs is
generic (
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 64
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(wb_address_width_c-1 downto 0);
wb_dat_i : in std_logic_vector(wb_data_width_c-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(wb_data_width_c-1 downto 0);
wb_ack_o : out std_logic
);
end component;
begin
clk_p: process
begin
clk_tbs <= '1';
wait for period/2;
clk_tbs <= '0';
wait for period/2;
end process clk_p;
reset_p: process
begin
rst_tbs <= '1';
rst_n_tbs <= '0';
wait for period;
rst_tbs <= '0';
rst_n_tbs <= '1';
wait;
end process reset_p;
stimuli_p: process
begin
step <= 1;
dma_ctrl_target_addr_tbs <= (others => '0');
dma_ctrl_host_addr_h_tbs <= (others => '0');
dma_ctrl_host_addr_l_tbs <= (others => '0');
dma_ctrl_len_tbs <= (others => '0');
dma_ctrl_start_p2l_tbs <= '0';
dma_ctrl_start_next_tbs <= '0';
dma_ctrl_byte_swap_tbs <= (others => '0');
dma_ctrl_abort_tbs <= '0';
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
--pd_pdm_hdr_start_tbs <= '0'; -- Header strobe
--pd_pdm_hdr_length_tbs <= (others => '0'); -- Packet length in 32-bit words multiples
--pd_pdm_hdr_cid_tbs <= (others => '0'); -- Completion ID
pd_pdm_master_cpld_tbs <= '0'; -- Master read completion with data
pd_pdm_master_cpln_tbs <= '0'; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0'; -- Indicates end of the packet
pd_pdm_data_tbs <= (others => '0'); -- Data
pd_pdm_be_tbs <= (others => '0'); -- Byte Enable for data
arb_pdm_gnt_tbs <= '0';
p2l_dma_stall_tbs <= '0';
l2p_dma_cyc_tbs <= '0';
wait for period;
dma_ctrl_target_addr_tbs <= X"00000010";
dma_ctrl_host_addr_h_tbs <= X"00000001";
dma_ctrl_host_addr_l_tbs <= X"0000005A";
dma_ctrl_len_tbs <= X"00000040";
dma_ctrl_start_p2l_tbs <= '0';
dma_ctrl_start_next_tbs <= '0';
dma_ctrl_byte_swap_tbs <= (others => '0');
dma_ctrl_abort_tbs <= '0';
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
--pd_pdm_hdr_start_tbs <= '0'; -- Header strobe
--pd_pdm_hdr_length_tbs <= "00" & X"01"; -- Packet length in 32-bit words multiples
--pd_pdm_hdr_cid_tbs <= (others => '0'); -- Completion ID
pd_pdm_master_cpld_tbs <= '1'; -- Master read completion with data
pd_pdm_master_cpln_tbs <= '0'; -- Master read completion without data
--
-- Data
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0'; -- Indicates end of the packet
pd_pdm_data_tbs <= (others => '0'); -- Data
pd_pdm_be_tbs <= (others => '0'); -- Byte Enable for data
arb_pdm_gnt_tbs <= '1';
p2l_dma_stall_tbs <= '0';
l2p_dma_cyc_tbs <= '0';
wait for period;
step <= 2;
dma_ctrl_start_p2l_tbs <= '1';
wait for period;
dma_ctrl_start_p2l_tbs <= '0';
wait for period;
wait for period;
wait for period;
wait for period;
step <= 3;
dma_ctrl_start_p2l_tbs <= '0';
pd_pdm_data_valid_tbs <= '1'; -- Indicates Data is valid
pd_pdm_data_valid_w_tbs <= "11";
pd_pdm_data_last_tbs <= '0'; -- Indicates end of the packet
pd_pdm_data_tbs <= X"DEADBEEF00000000"; -- Header
pd_pdm_be_tbs <= X"FF"; -- Byte Enable for data
wait for period;
step <= 4;
pd_pdm_data_tbs <= X"DEADBABE00000001"; -- Adresse
wait for period;
step <= 5;
pd_pdm_data_tbs <= X"BABECACA00000002"; -- Data
wait for period;
step <= 6;
pd_pdm_data_tbs <= X"BABECACA00000003"; -- Data
wait for period;
step <= 7;
pd_pdm_data_tbs <= X"BABECACA00000004"; -- Data
wait for period;
step <= 8;
pd_pdm_data_tbs <= X"BABECACA00000005"; -- Data
wait for period;
step <= 9;
pd_pdm_data_tbs <= X"BABECACA00000006"; -- Data
wait for period;
step <= 10;
pd_pdm_data_last_tbs <= '1';
pd_pdm_data_tbs <= X"DEADC4C400000007"; -- Data
wait for period;
step <= 11;
pd_pdm_data_valid_w_tbs <= "00";
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0';
-- wait for period;
-- wait for period;
-- wait for period;
-- step <= 20;
-- dma_ctrl_len_tbs <= X"00000020";
-- dma_ctrl_start_next_tbs <= '1';
-- wait for period;
-- step <= 21;
-- dma_ctrl_start_next_tbs <= '0';
-- wait for period;
-- step <= 22;
-- wait for period;
-- step <= 23;
-- wait for period;
-- step <= 24;
-- pd_pdm_data_tbs <= X"0000000300000360";
-- pd_pdm_data_valid_tbs <= '1';
-- pd_pdm_data_valid_w_tbs <= "11";
-- wait for period;
-- step <= 25;
-- pd_pdm_data_tbs <= X"000004E0922d1000";
-- wait for period;
-- step <= 26;
-- pd_pdm_data_tbs <= X"0000000403a57038";
-- wait for period;
-- step <= 27;
-- pd_pdm_data_tbs <= X"CACA000000000001";
-- pd_pdm_data_last_tbs <= '1';
-- wait for period;
-- step <= 28;
-- pd_pdm_data_tbs <= X"CACA1000000000CC";
-- pd_pdm_data_valid_w_tbs <= "00";
-- pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
-- pd_pdm_data_last_tbs <= '0';
wait for period;
wait for period;
wait for period;
step <= 12;
dma_ctrl_len_tbs <= X"0000001C";
dma_ctrl_start_next_tbs <= '1';
wait for period;
step <= 13;
dma_ctrl_start_next_tbs <= '0';
wait for period;
step <= 14;
wait for period;
step <= 15;
wait for period;
step <= 16;
pd_pdm_data_tbs <= X"BEEF0001BEEF0000";
pd_pdm_data_valid_tbs <= '1';
pd_pdm_data_valid_w_tbs <= "11";
wait for period;
step <= 17;
pd_pdm_data_tbs <= X"BEEF0003BEEF0002";
wait for period;
step <= 18;
pd_pdm_data_tbs <= X"BEEF0005BEEF0004";
wait for period;
step <= 18;
pd_pdm_data_tbs <= X"BEEF0007BEEF0006";
pd_pdm_data_valid_w_tbs <= "01";
pd_pdm_data_last_tbs <= '1';
wait for period;
step <= 19;
pd_pdm_data_tbs <= X"BEEF0009BEEF0008";
pd_pdm_data_valid_w_tbs <= "00";
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0';
wait for period;
wait for period;
wait for period;
step <= 22;
dma_ctrl_len_tbs <= X"0000001C";
dma_ctrl_start_next_tbs <= '1';
wait for period;
step <= 23;
dma_ctrl_start_next_tbs <= '0';
wait for period;
step <= 24;
wait for period;
step <= 25;
wait for period;
step <= 26;
pd_pdm_data_tbs <= X"DEAD0001DEAD0000";
pd_pdm_data_valid_tbs <= '1';
pd_pdm_data_valid_w_tbs <= "11";
wait for period;
step <= 0;
pd_pdm_data_tbs <= X"0000000000000000";
pd_pdm_data_valid_w_tbs <= "00";
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0';
wait for period;
step <= 27;
pd_pdm_data_tbs <= X"DEAD0003DEAD0002";
pd_pdm_data_valid_w_tbs <= "11";
pd_pdm_data_valid_tbs <= '1';
wait for period;
step <= 28;
pd_pdm_data_tbs <= X"DEAD0005DEAD0004";
wait for period;
step <= 28;
pd_pdm_data_tbs <= X"DEAD0007DEAD0006";
pd_pdm_data_valid_w_tbs <= "01";
pd_pdm_data_last_tbs <= '1';
wait for period;
step <= 29;
pd_pdm_data_tbs <= X"DEAD0009DEAD0008";
pd_pdm_data_valid_w_tbs <= "00";
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0';
wait for period;
wait for period;
wait for period;
step <= 32;
dma_ctrl_len_tbs <= X"0000001C";
dma_ctrl_start_next_tbs <= '1';
wait for period;
step <= 33;
dma_ctrl_start_next_tbs <= '0';
wait for period;
step <= 34;
wait for period;
step <= 35;
wait for period;
step <= 36;
pd_pdm_data_tbs <= X"BEEF000EBABE0000";
pd_pdm_data_valid_tbs <= '1';
pd_pdm_data_last_tbs <= '1';
pd_pdm_data_valid_w_tbs <= "01";
wait for period;
step <= 0;
pd_pdm_data_tbs <= X"0000000000000000";
pd_pdm_data_valid_w_tbs <= "00";
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0';
wait for period;
step <= 37;
pd_pdm_data_tbs <= X"BABE0002BABE0001";
pd_pdm_data_valid_w_tbs <= "11";
wait for period;
step <= 38;
pd_pdm_data_tbs <= X"BABE0004BABE0003";
wait for period;
step <= 38;
pd_pdm_data_tbs <= X"BABE0006BABE0005";
pd_pdm_data_last_tbs <= '1';
wait for period;
step <= 39;
pd_pdm_data_tbs <= X"BEEF0009BEEF0008";
pd_pdm_data_valid_w_tbs <= "00";
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0';
wait for period;
wait for period;
wait for period;
step <= 42;
dma_ctrl_len_tbs <= X"0000001C";
dma_ctrl_start_next_tbs <= '1';
wait for period;
step <= 43;
dma_ctrl_start_next_tbs <= '0';
wait for period;
step <= 44;
wait for period;
step <= 45;
wait for period;
step <= 46;
pd_pdm_data_tbs <= X"BEEF0000BEEF000A";
pd_pdm_data_valid_tbs <= '1';
pd_pdm_data_valid_w_tbs <= "10";
wait for period;
step <= 47;
pd_pdm_data_tbs <= X"BEEF0002BEEF0001";
pd_pdm_data_valid_w_tbs <= "11";
wait for period;
step <= 48;
pd_pdm_data_tbs <= X"BEEF0004BEEF0003";
wait for period;
step <= 48;
pd_pdm_data_tbs <= X"BEEF0006BEEF0005";
pd_pdm_data_valid_w_tbs <= "11";
pd_pdm_data_last_tbs <= '1';
wait for period;
step <= 49;
pd_pdm_data_tbs <= X"BEEF0009BEEF0008";
pd_pdm_data_valid_w_tbs <= "00";
pd_pdm_data_valid_tbs <= '0'; -- Indicates Data is valid
pd_pdm_data_last_tbs <= '0';
wait;
end process stimuli_p;
-----------------------------------------------------------------------------
-- P2L DMA master
-----------------------------------------------------------------------------
dut1 : p2l_dma_master
generic map(
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP => false
)
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_tbs,
rst_n_i => rst_n_tbs,
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i => dma_ctrl_target_addr_tbs,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_tbs,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_tbs,
dma_ctrl_len_i => dma_ctrl_len_tbs,
dma_ctrl_start_p2l_i => dma_ctrl_start_p2l_tbs,
dma_ctrl_start_next_i => dma_ctrl_start_next_tbs,
dma_ctrl_done_o => dma_ctrl_done_s,
dma_ctrl_error_o => dma_ctrl_error_s,
dma_ctrl_byte_swap_i => dma_ctrl_byte_swap_tbs,
dma_ctrl_abort_i => dma_ctrl_abort_tbs,
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
--pd_pdm_hdr_start_i => pd_pdm_hdr_start_tbs, -- Header strobe
--pd_pdm_hdr_length_i => pd_pdm_hdr_length_tbs,-- Packet length in 32-bit words multiples
--pd_pdm_hdr_cid_i => pd_pdm_hdr_cid_tbs,-- Completion ID
pd_pdm_master_cpld_i => pd_pdm_master_cpld_tbs, -- Master read completion with data
pd_pdm_master_cpln_i => pd_pdm_master_cpln_tbs, -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i => pd_pdm_data_valid_tbs, -- Indicates Data is valid
pd_pdm_data_valid_w_i => pd_pdm_data_valid_w_tbs, -- Indicates Data is valid
pd_pdm_data_last_i => pd_pdm_data_last_tbs, -- Indicates end of the packet
pd_pdm_data_i => pd_pdm_data_tbs, -- Data
pd_pdm_be_i => pd_pdm_be_tbs, -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o => p2l_rdy_s, -- De-asserted to pause transfer already in progress
rx_error_o => rx_error_s, -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o => pdm_arb_tvalid_s, -- Read completion signals
pdm_arb_tlast_o => pdm_arb_tlast_s, -- Toward the arbiter
pdm_arb_tdata_o => pdm_arb_tdata_s,
pdm_arb_tkeep_o => pdm_arb_tkeep_s,
pdm_arb_req_o => pdm_arb_req_s,
arb_pdm_gnt_i => arb_pdm_gnt_tbs,
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i => clk_tbs,-- Bus clock
p2l_dma_adr_o => p2l_dma_adr_s, -- Adress
p2l_dma_dat_i => p2l_dma_dat_s2m_s, -- Data in
p2l_dma_dat_o => p2l_dma_dat_m2s_s, -- Data out
p2l_dma_sel_o => p2l_dma_sel_s, -- Byte select
p2l_dma_cyc_o => p2l_dma_cyc_s, -- Read or write cycle
p2l_dma_stb_o => p2l_dma_stb_s, -- Read or write strobe
p2l_dma_we_o => p2l_dma_we_s, -- Write
p2l_dma_ack_i => p2l_dma_ack_s, -- Acknowledge
p2l_dma_stall_i => p2l_dma_stall_tbs, -- for pipelined Wishbone
l2p_dma_cyc_i => l2p_dma_cyc_tbs, -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o => next_item_carrier_addr_s,
next_item_host_addr_h_o => next_item_host_addr_h_s,
next_item_host_addr_l_o => next_item_host_addr_l_s,
next_item_len_o => next_item_len_s,
next_item_next_l_o => next_item_next_l_s,
next_item_next_h_o => next_item_next_h_s,
next_item_attrib_o => next_item_attrib_s,
next_item_valid_o => next_item_valid_s
);
dut2:bram_wbs
generic map (
ADDR_WIDTH => wb_address_width_c,
DATA_WIDTH => wb_data_width_c
)
port map (
-- SYS CON
clk => clk_tbs,
rst => rst_tbs,
-- Wishbone Slave in
wb_adr_i => p2l_dma_adr_s(wb_address_width_c - 1 downto 0),
wb_dat_i => p2l_dma_dat_m2s_s,
wb_we_i => p2l_dma_we_s,
wb_stb_i => p2l_dma_stb_s,
wb_cyc_i => p2l_dma_cyc_s,
wb_lock_i => p2l_dma_stb_s,
-- Wishbone Slave out
wb_dat_o => p2l_dma_dat_s2m_s,
wb_ack_o => p2l_dma_ack_s
);
end Behavioral;
|
gpl-3.0
|
e92f87a6478e8dd8bc550c34da11149d
| 0.52148 | 3.113555 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/decoder.vhd
| 4 | 3,167 |
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (
opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigval : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigcfg : out STD_LOGIC_VECTOR (3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out STD_LOGIC;
wrFlags : out std_logic;
arm : out STD_LOGIC;
reset : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
51c4f18389fc68d45287c577c17639fd
| 0.586675 | 3.503319 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/sync.vhd
| 4 | 3,203 |
----------------------------------------------------------------------------------
-- sync.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Synchronizes input with clock on rising or falling edge and does some
-- optional preprocessing. (Noise filter and demux.)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0));
end sync;
architecture Behavioral of sync is
COMPONENT demux
PORT(
input : IN std_logic_vector(15 downto 0);
input180 : IN std_logic_vector(15 downto 0);
clock : IN std_logic;
output : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT filter
PORT(
input : IN std_logic_vector(31 downto 0);
input180 : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
output : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal filteredInput, demuxedInput, synchronizedInput, synchronizedInput180: std_logic_vector (31 downto 0);
begin
Inst_demux: demux PORT MAP(
input => synchronizedInput(15 downto 0),
input180 => synchronizedInput180(15 downto 0),
clock => clock,
output => demuxedInput
);
Inst_filter: filter PORT MAP(
input => synchronizedInput,
input180 => synchronizedInput180,
clock => clock,
output => filteredInput
);
-- synch input guarantees use of iob ff on spartan 3 (as filter and demux do)
process (clock)
begin
if rising_edge(clock) then
synchronizedInput <= input;
end if;
if falling_edge(clock) then
synchronizedInput180 <= input;
end if;
end process;
-- add another pipeline step for input selector to not decrease maximum clock rate
process (clock)
begin
if rising_edge(clock) then
if enableDemux = '1' then
output <= demuxedInput;
else
if enableFilter = '1' then
output <= filteredInput;
else
if falling = '1' then
output <= synchronizedInput180;
else
output <= synchronizedInput;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
cf4f4f58ca1917e69dd96e6d955cc5d5
| 0.641586 | 3.840528 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/init_mem_pattern_ctr.vhd
| 20 | 25,087 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: init_mem_pattern_ctr.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel has a small FSM to control the operation of
-- mcb_traffic_gen module.It first fill up the memory with a selected
-- DATA pattern and then starts the memory testing state.
-- Reference:
-- Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
-- and the fixed_bl_o is fixed at 64 if data_mode_o == PRBS and FAMILY == "SPARTAN6"
-- The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
-- 1.2 05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY init_mem_pattern_ctr IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
TST_MEM_INSTR_MODE : STRING := "R_W_INSTR_MODE";
MEM_BURST_LEN : INTEGER := 8;
CMD_PATTERN : STRING := "CGEN_ALL";
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
CMD_SEED_VALUE : std_logic_vector(31 downto 0) := X"12345678";
DATA_SEED_VALUE : std_logic_vector(31 downto 0) := X"ca345675";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
PORT_MODE : STRING := "BI_MODE";
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
mcb_cmd_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_en_i : IN STD_LOGIC;
mcb_cmd_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_wr_en_i : IN STD_LOGIC;
vio_modify_enable : IN STD_LOGIC;
vio_data_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_addr_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_bl_mode_value : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
vio_fixed_bl_value : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_init_done_i : IN STD_LOGIC;
cmp_error : IN STD_LOGIC;
run_traffic_o : OUT STD_LOGIC;
start_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_o : OUT STD_LOGIC;
addr_mode_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_o : OUT STD_LOGIC;
fixed_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END init_mem_pattern_ctr;
ARCHITECTURE trans OF init_mem_pattern_ctr IS
constant IDLE : std_logic_vector(4 downto 0) := "00001";
constant INIT_MEM_WRITE : std_logic_vector(4 downto 0) := "00010";
constant INIT_MEM_READ : std_logic_vector(4 downto 0) := "00100";
constant TEST_MEM : std_logic_vector(4 downto 0) := "01000";
constant CMP_ERROR1 : std_logic_vector(4 downto 0) := "10000";
constant BRAM_ADDR : std_logic_vector(1 downto 0) := "00";
constant FIXED_ADDR : std_logic_vector(2 downto 0) := "001";
constant PRBS_ADDR : std_logic_vector(2 downto 0) := "010";
constant SEQUENTIAL_ADDR : std_logic_vector(2 downto 0) := "011";
constant BRAM_INSTR_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_INSTR_MODE : std_logic_vector(3 downto 0) := "0001";
constant FIXED_INSTR_MODE_WITH_REFRESH : std_logic_vector(3 downto 0) := "0110";
constant R_W_INSTR_MODE : std_logic_vector(3 downto 0) := "0010";
constant RP_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0011";
constant R_RP_W_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0100";
constant R_RP_W_WP_REF_INSTR_MODE : std_logic_vector(3 downto 0) := "0101";
constant BRAM_BL_MODE : std_logic_vector(1 downto 0) := "00";
constant FIXED_BL_MODE : std_logic_vector(1 downto 0) := "01";
constant PRBS_BL_MODE : std_logic_vector(1 downto 0) := "10";
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
constant RD_INSTR : std_logic_vector(2 downto 0) := "001";
constant RDP_INSTR : std_logic_vector(2 downto 0) := "011";
constant WR_INSTR : std_logic_vector(2 downto 0) := "000";
constant WRP_INSTR : std_logic_vector(2 downto 0) := "010";
constant REFRESH_INSTR : std_logic_vector(2 downto 0) := "100";
constant NOP_WR_INSTR : std_logic_vector(2 downto 0) := "101";
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL mcb_init_done_reg : STD_LOGIC;
SIGNAL mcb_init_done_reg1 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL mcb_cmd_en_r : STD_LOGIC;
SIGNAL mcb_cmd_bl_r : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL end_addr_reached : STD_LOGIC;
SIGNAL run_traffic : STD_LOGIC;
SIGNAL current_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fix_bl_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL data_mode_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL addr_mode_sel : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_mode : STD_LOGIC_VECTOR(2 DOWNTO 0);
-- SIGNAL data_mode1 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL FIXEDBL : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL FIXED_BL_VALUE : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL bram_mode_enable : STD_LOGIC;
SIGNAL syn1_vio_data_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL syn1_vio_addr_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL test_mem_instr_mode : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_mode_o_xhdl0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL data_mode_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
test_mem_instr_mode <= "0000" when TST_MEM_INSTR_MODE = "BRAM_INSTR_MODE" else
"0001" when (TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") OR
(TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") else
"0010" when TST_MEM_INSTR_MODE = "R_W_INSTR_MODE" else
"0011" when (TST_MEM_INSTR_MODE = "RP_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6") else
"0100" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6")else
"0101" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_REF_INSTR_MODE"AND
FAMILY = "SPARTAN6") else
"0010" ;
-- Drive referenced outputs
bl_mode_o <= bl_mode_o_xhdl0;
FIXEDBL <= "000000";
xhdl1 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned(DWIDTH/8,11));
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (DWIDTH >= 256 AND DWIDTH <= 576) THEN
INC_COUNTS <= "00000100000";
ELSIF ((DWIDTH >= 128) AND (DWIDTH <= 224)) THEN
INC_COUNTS <= "00000010000";
ELSIF ((DWIDTH = 64) OR (DWIDTH = 96)) THEN
INC_COUNTS <= "00000001000";
ELSIF (DWIDTH = 32) THEN
INC_COUNTS <= "00000000100";
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_address <= BEGIN_ADDRESS;
ELSIF (
-- ((mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND ((PORT_MODE = "WR_MODE") OR (PORT_MODE = "BI_MODE")))) OR
(mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE"))) OR
(mcb_wr_en_i = '1' AND (current_state = IDLE AND PORT_MODE = "RD_MODE" ))
) THEN
current_address <= current_address + ("000000000000000000000" & INC_COUNTS);
ELSE
current_address <= current_address;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(29 DOWNTO 24) >= end_boundary_addr(29 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (current_address(23 DOWNTO 16) >= end_boundary_addr(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (current_address(15 DOWNTO 8) >= end_boundary_addr(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
upper_end_matched <= '0';
ELSIF (mcb_cmd_en_i = '1') THEN
upper_end_matched <= AC3_G_E3 AND AC2_G_E2 AND AC1_G_E1;
END IF;
END IF;
END PROCESS;
FIXED_BL_VALUE <= "0000010" WHEN ((FAMILY = "VIRTEX6") AND ((MEM_BURST_LEN = 8) OR (MEM_BURST_LEN = 0))) ELSE
"0000001" WHEN ((FAMILY = "VIRTEX6") AND (MEM_BURST_LEN = 4)) ELSE
('0' & FIXEDBL);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_boundary_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(END_ADDRESS)) - (DWIDTH / 8) + 1),32));
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(7 DOWNTO 0) >= end_boundary_addr(7 DOWNTO 0)) THEN
lower_end_matched <= '1';
ELSE
lower_end_matched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_i = '1') THEN
mcb_cmd_bl_r <= mcb_cmd_bl_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 32)) OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 64)) OR
(upper_end_matched = '1' AND DWIDTH = 128 AND FAMILY = "SPARTAN6") OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "VIRTEX6")) THEN
end_addr_reached <= '1';
ELSE
end_addr_reached <= '0';
END IF;
END IF;
END PROCESS;
fixed_addr_o <= "00000000000000000001001000110100";
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mcb_init_done_reg1 <= mcb_init_done_i;
mcb_init_done_reg <= mcb_init_done_reg1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_o <= run_traffic;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_state <= "00001";
ELSE
current_state <= next_state;
END IF;
END IF;
END PROCESS;
start_addr_o <= BEGIN_ADDRESS;
end_addr_o <= END_ADDRESS;
cmd_seed_o <= CMD_SEED_VALUE;
data_seed_o <= DATA_SEED_VALUE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
syn1_vio_data_mode_value <= "011";
syn1_vio_addr_mode_value <= "011";
ELSIF (vio_modify_enable = '1') THEN
syn1_vio_data_mode_value <= vio_data_mode_value;
syn1_vio_addr_mode_value <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
data_mode_sel <= DATA_MODE; --"0101" ADDR_DATA_MODE;
addr_mode_sel <= "011";
ELSIF (vio_modify_enable = '1') THEN
data_mode_sel <= '0' & syn1_vio_data_mode_value(2 DOWNTO 0);
addr_mode_sel <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i = '1') OR (FAMILY = "VIRTEX6")) THEN
fix_bl_value <= FIXED_BL_VALUE(5 DOWNTO 0);
ELSIF (vio_modify_enable = '1') THEN
fix_bl_value <= vio_fixed_bl_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1' OR (FAMILY = "VIRTEX6")) THEN
IF (FAMILY = "VIRTEX6") THEN
bl_mode_sel <= FIXED_BL_MODE;
ELSE
bl_mode_sel <= PRBS_BL_MODE;
END IF;
ELSIF (vio_modify_enable = '1') THEN
bl_mode_sel <= vio_bl_mode_value;
END IF;
END IF;
END PROCESS;
data_mode_o <= data_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_reg <= data_mode_sel;
addr_mode_o <= addr_mode;
IF (syn1_vio_addr_mode_value = 0 AND vio_modify_enable = '1') THEN
bram_mode_enable <= '1';
ELSE
bram_mode_enable <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (FIXED_BL_VALUE,fix_bl_value,bram_mode_enable,test_mem_instr_mode, current_state, mcb_init_done_reg, end_addr_reached, cmp_error, bl_mode_sel, addr_mode_sel, data_mode_reg,bl_mode_o_xhdl0)
BEGIN
load_seed_o <= '0';
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
addr_mode <= (others => '0');
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
instr_mode_o <= (others => '0');
ELSE
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
bl_mode_o_xhdl0 <= (others => '0');
ELSE
bl_mode_o_xhdl0 <= FIXED_BL_MODE;
END IF;
-- data_mode1 <= WALKING1_DATA_MODE;
IF (FAMILY = "VIRTEX6") THEN
fixed_bl_o <= FIXED_BL_VALUE(5 downto 0); --"000010"; --2
-- PRBS mode
else if (data_mode_reg(2 downto 0) = "111" and FAMILY = "SPARTAN6") then
fixed_bl_o <= "000000";-- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
mode_load_o <= '0';
run_traffic <= '0';
next_state <= IDLE;
IF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
CASE current_state IS
WHEN IDLE =>
IF (mcb_init_done_reg = '1') THEN
IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
next_state <= INIT_MEM_WRITE;
mode_load_o <= '1';
run_traffic <= '0';
load_seed_o <= '1';
ELSIF (PORT_MODE = "RD_MODE" AND end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
run_traffic <= '1';
load_seed_o <= '1';
END IF;
ELSE
next_state <= IDLE;
run_traffic <= '0';
load_seed_o <= '0';
END IF;
WHEN INIT_MEM_WRITE =>
IF (end_addr_reached = '1' AND EYE_TEST = "FALSE") THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
run_traffic <= '1';
ELSE
next_state <= INIT_MEM_WRITE;
run_traffic <= '1';
mode_load_o <= '0';
load_seed_o <= '0';
IF (EYE_TEST = "TRUE") THEN
addr_mode <= FIXED_ADDR;
ELSIF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
addr_mode <= "000";
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
END IF;
WHEN INIT_MEM_READ =>
IF (end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
ELSE
next_state <= INIT_MEM_READ;
run_traffic <= '0';
mode_load_o <= '0';
load_seed_o <= '0';
END IF;
WHEN TEST_MEM =>
IF (cmp_error = '1') THEN
next_state <= CMP_ERROR1;
ELSE
next_state <= TEST_MEM;
END IF;
run_traffic <= '1';
IF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") THEN
fixed_instr_o <= WR_INSTR;
ELSIF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
if (FAMILY = "VIRTEX6") then
fixed_bl_o <= fix_bl_value; --"000010"; 2
else if ((data_mode_reg = "0111") and (FAMILY = "SPARTAN6")) then
fixed_bl_o <= "000000"; -- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
bl_mode_o_xhdl0 <= bl_mode_sel;
IF (bl_mode_o_xhdl0 = PRBS_BL_MODE) THEN
addr_mode <= PRBS_ADDR;
ELSE
addr_mode <= addr_mode_sel;
END IF;
IF (PORT_MODE = "BI_MODE") THEN
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_RP_W_WP_REF_INSTR_MODE;--FIXED_INSTR_MODE;--R_W_INSTR_MODE;--R_RP_W_WP_INSTR_MODE;--R_W_INSTR_MODE;
--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
ELSIF (PORT_MODE = "RD_MODE" OR PORT_MODE = "WR_MODE") THEN
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
WHEN CMP_ERROR1 =>
next_state <= CMP_ERROR1;
bl_mode_o_xhdl0 <= bl_mode_sel;
fixed_instr_o <= RD_INSTR;
addr_mode <= SEQUENTIAL_ADDR;
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_W_INSTR_MODE;--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
run_traffic <= '1';
WHEN OTHERS =>
next_state <= IDLE;
END CASE;
END PROCESS;
END trans;
|
gpl-3.0
|
a1a67a775c5a58fa942ebabce312b580
| 0.507673 | 3.69361 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/sim_tb_top.vhd
| 2 | 35,045 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
constant C3_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000004ff", x"04ffffff");
constant C3_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000300", x"03000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr3_ctrl_spec_bank3_32b_32b is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_reset_n : out std_logic; c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p1_cmd_en : std_logic;
signal c3_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p1_cmd_empty : std_logic;
signal c3_p1_cmd_full : std_logic;
signal c3_p1_wr_en : std_logic;
signal c3_p1_wr_mask : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
signal c3_p1_wr_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_wr_full : std_logic;
signal c3_p1_wr_empty : std_logic;
signal c3_p1_wr_count : std_logic_vector(6 downto 0);
signal c3_p1_wr_underrun : std_logic;
signal c3_p1_wr_error : std_logic;
signal c3_p1_rd_en : std_logic;
signal c3_p1_rd_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_rd_full : std_logic;
signal c3_p1_rd_empty : std_logic;
signal c3_p1_rd_count : std_logic_vector(6 downto 0);
signal c3_p1_rd_overflow : std_logic;
signal c3_p1_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr3_ctrl_spec_bank3_32b_32b generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error,
c3_p1_cmd_clk => (c3_clk0),
c3_p1_cmd_en => c3_p1_cmd_en,
c3_p1_cmd_instr => c3_p1_cmd_instr,
c3_p1_cmd_bl => c3_p1_cmd_bl,
c3_p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
c3_p1_cmd_empty => c3_p1_cmd_empty,
c3_p1_cmd_full => c3_p1_cmd_full,
c3_p1_wr_clk => (c3_clk0),
c3_p1_wr_en => c3_p1_wr_en,
c3_p1_wr_mask => c3_p1_wr_mask,
c3_p1_wr_data => c3_p1_wr_data,
c3_p1_wr_full => c3_p1_wr_full,
c3_p1_wr_empty => c3_p1_wr_empty,
c3_p1_wr_count => c3_p1_wr_count,
c3_p1_wr_underrun => c3_p1_wr_underrun,
c3_p1_wr_error => c3_p1_wr_error,
c3_p1_rd_clk => (c3_clk0),
c3_p1_rd_en => c3_p1_rd_en,
c3_p1_rd_data => c3_p1_rd_data,
c3_p1_rd_full => c3_p1_rd_full,
c3_p1_rd_empty => c3_p1_rd_empty,
c3_p1_rd_count => c3_p1_rd_count,
c3_p1_rd_overflow => c3_p1_rd_overflow,
c3_p1_rd_error => c3_p1_rd_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C3_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C3_p1_DATA_MODE,
C_p1_END_ADDRESS => C3_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C3_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C3_p1_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p1_mcb_cmd_en_o => c3_p1_cmd_en,
p1_mcb_cmd_instr_o => c3_p1_cmd_instr,
p1_mcb_cmd_bl_o => c3_p1_cmd_bl,
p1_mcb_cmd_addr_o => c3_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c3_p1_cmd_full,
p1_mcb_wr_en_o => c3_p1_wr_en,
p1_mcb_wr_mask_o => c3_p1_wr_mask,
p1_mcb_wr_data_o => c3_p1_wr_data,
p1_mcb_wr_full_i => c3_p1_wr_full,
p1_mcb_wr_fifo_counts => c3_p1_wr_count,
p1_mcb_rd_en_o => c3_p1_rd_en,
p1_mcb_rd_data_i => c3_p1_rd_data,
p1_mcb_rd_empty_i => c3_p1_rd_empty,
p1_mcb_rd_fifo_counts => c3_p1_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
gpl-3.0
|
e7a69fce50132772aa9a5396c2cb9c9f
| 0.451733 | 3.312069 | false | false | false | false |
starsheriff/papilio-one250
|
uart_2/main.vhd
| 1 | 802 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_transmitter is
Port(
clk : in STD_LOGIC;
data_out : out STD_LOGIC;
debug_out : out STD_LOGIC
);
end serial_transmitter;
architecture Behavioral of serial_transmitter is
signal shiftreg : std_logic_vector(15 downto 0) := "1111111010110100";
signal counter : std_logic_vector(12 downto 0) := (others => '0');
begin
data_out <= shiftreg(0);
debug_out <= shiftreg(0);
process(clk)
begin
if rising_edge(clk) then
if counter=3332 then
shiftreg <= shiftreg(0) & shiftreg(15 downto 1);
counter <= (others => '0');
else
counter <= counter + 1;
end if; -- counter
end if; -- rising_edge
end process;
end Behavioral;
|
gpl-2.0
|
3a54a1d940068b766195bc74ee25db63
| 0.65212 | 3.486957 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/l2p_dma_master.vhd
| 2 | 25,186 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Rewritten on basis from Matthieu Cattin,
-- # taken from the gn4124-core on ohwr.org
-- ####################################
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
use work.common_pkg.all;
entity l2p_dma_master is
generic (
g_BYTE_SWAP : boolean := true;
axis_data_width_c : integer := 64;
wb_address_width_c : integer := 64;
wb_data_width_c : integer := 64
);
port (
-- GN4124 core clk and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- From PCIe IP core
l2p_rid_i : in std_logic_vector(16-1 downto 0);
-- From the DMA controller
dma_ctrl_target_addr_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_len_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_start_l2p_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
-- To the arbiter (L2P data)
ldm_arb_tvalid_o : out std_logic;
ldm_arb_tlast_o : out std_logic;
ldm_arb_tdata_o : out std_logic_vector(axis_data_width_c-1 downto 0);
ldm_arb_tkeep_o : out std_logic_vector(axis_data_width_c/8-1 downto 0);
ldm_arb_tready_i : in std_logic;
ldm_arb_req_o : out std_logic;
arb_ldm_gnt_i : in std_logic;
-- L2P channel control
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l2p_rdy_i : in std_logic; -- De-asserted to pause transdert already in progress
tx_error_i : in std_logic; -- Asserted when unexpected or malformed paket received
-- DMA Interface (Pipelined Wishbone)
l2p_dma_clk_i : in std_logic;
l2p_dma_adr_o : out std_logic_vector(wb_address_width_c-1 downto 0);
l2p_dma_dat_i : in std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_dat_o : out std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_sel_o : out std_logic_vector(3 downto 0);
l2p_dma_cyc_o : out std_logic;
l2p_dma_stb_o : out std_logic;
l2p_dma_we_o : out std_logic;
l2p_dma_ack_i : in std_logic;
l2p_dma_stall_i : in std_logic;
p2l_dma_cyc_i : in std_logic; -- P2L dma WB cycle for bus arbitration
--DMA Debug
l2p_current_state_do : out std_logic_vector (2 downto 0);
l2p_data_cnt_do : out unsigned(12 downto 0);
l2p_len_cnt_do : out unsigned(12 downto 0);
l2p_timeout_cnt_do : out unsigned(12 downto 0);
wb_timeout_cnt_do : out unsigned(12 downto 0);
-- Data FIFO
data_fifo_rd_do : out std_logic;
data_fifo_wr_do : out std_logic;
data_fifo_empty_do : out std_logic;
data_fifo_full_do : out std_logic;
data_fifo_dout_do : out std_logic_vector(axis_data_width_c-1 downto 0);
data_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0);
-- Addr FIFO
addr_fifo_rd_do : out std_logic;
addr_fifo_wr_do : out std_logic;
addr_fifo_empty_do : out std_logic;
addr_fifo_full_do : out std_logic;
addr_fifo_dout_do : out std_logic_vector(wb_address_width_c-1 downto 0);
addr_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0)
);
end l2p_dma_master;
architecture behavioral of l2p_dma_master is
---------------------
-- Components
---------------------
component l2p_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic
);
end component;
---------------------
-- Constants
---------------------
constant c_L2P_MAX_PAYLOAD : integer := 32;
constant c_ADDR_FIFO_FULL_THRES : integer := 700;
constant c_DATA_FIFO_FULL_THRES : integer := 700;
constant c_TIMEOUT : integer := 2000;
---------------------
-- Signals
---------------------
signal fifo_rst : std_logic;
signal fifo_rst_t : std_logic;
-- Axi-Stream
--signal ldm_arb_tready_s: std_logic;
-- Data FIFO
signal data_fifo_rd : std_logic;
signal data_fifo_wr : std_logic;
signal data_fifo_empty : std_logic;
signal data_fifo_empty_t : std_logic;
signal data_fifo_full : std_logic;
signal data_fifo_dout : std_logic_vector(axis_data_width_c-1 downto 0);
signal data_fifo_dout_1 : std_logic_vector(axis_data_width_c-1 downto 0);
signal data_fifo_din : std_logic_vector(axis_data_width_c-1 downto 0);
-- Addr FIFO
signal addr_fifo_rd : std_logic;
signal addr_fifo_wr : std_logic;
signal addr_fifo_empty : std_logic;
signal addr_fifo_full : std_logic;
signal addr_fifo_dout : std_logic_vector(wb_address_width_c-1 downto 0);
signal addr_fifo_din : std_logic_vector(axis_data_width_c-1 downto 0);
-- L2P FSM
type l2p_dma_state_type is (L2P_IDLE, L2P_SETUP, L2P_HEADER_0, L2P_HEADER_1,
L2P_SETUP_DATA, L2P_DATA,
L2P_LAST_DATA, L2P_ERROR);
signal l2p_dma_current_state : l2p_dma_state_type;
-- L2P packets
signal s_l2p_header : std_logic_vector(axis_data_width_c-1 downto 0);
signal l2p_len_cnt : unsigned(12 downto 0);
signal l2p_address_h : std_logic_vector(32-1 downto 0); -- TODO remove
signal l2p_address_l : std_logic_vector(32-1 downto 0);
signal l2p_data_cnt : unsigned(12 downto 0);
signal l2p_64b_address : std_logic;
signal l2p_len_header : unsigned(12 downto 0);
signal l2p_byte_swap : std_logic_vector(2 downto 0);
signal l2p_last_packet : std_logic;
signal l2p_lbe_header : std_logic_vector(3 downto 0);
signal ldm_arb_data_l : std_logic_vector(axis_data_width_c-1 downto 0);
--signal ldm_arb_data_32 : std_logic_vector(axis_data_width_c-1 downto 0);
signal ldm_arb_valid : std_logic;
signal data_fifo_valid : std_logic;
signal addr_fifo_valid : std_logic;
signal byte_swap_c : STD_LOGIC_VECTOR (1 downto 0);
-- Counter
signal target_addr_cnt : std_logic_vector(32-1 downto 0);
signal dma_length_cnt : unsigned(12 downto 0);
signal l2p_timeout_cnt : unsigned(12 downto 0);
signal wb_timeout_cnt : unsigned(12 downto 0);
-- Wishbone
signal l2p_dma_cyc_t : std_logic;
signal l2p_dma_stb_t : std_logic;
signal wb_ack_cnt : unsigned(12 downto 0);
signal wb_read_cnt : unsigned(12 downto 0);
signal l2p_cyc_start : std_logic;
signal wb_cyc_start : std_logic;
signal l2p_cyc_cnt : unsigned(12 downto 0);
signal wb_cyc_cnt : unsigned(12 downto 0);
begin
--DEBUG
l2p_data_cnt_do <= l2p_data_cnt;
l2p_len_cnt_do <= l2p_len_cnt;
l2p_timeout_cnt_do <= l2p_timeout_cnt;
wb_timeout_cnt_do <= wb_timeout_cnt;
with l2p_dma_current_state select l2p_current_state_do <=
"000" when L2P_IDLE,
"001" when L2P_SETUP,
"010" when L2P_HEADER_0,
"011" when L2P_HEADER_1,
"100" when L2P_SETUP_DATA,
"101" when L2P_DATA,
"110" when L2P_LAST_DATA,
"111" when L2P_ERROR;
-- Data FIFO
data_fifo_rd_do <= data_fifo_rd;
data_fifo_wr_do <= data_fifo_wr;
data_fifo_empty_do <= data_fifo_empty;
data_fifo_full_do <= data_fifo_full;
data_fifo_dout_do <= data_fifo_dout;
data_fifo_din_do <= data_fifo_din;
-- Addr FIFO
addr_fifo_rd_do <= addr_fifo_rd;
addr_fifo_wr_do <= addr_fifo_wr;
addr_fifo_empty_do <= addr_fifo_empty;
addr_fifo_full_do <= addr_fifo_full;
addr_fifo_dout_do <= addr_fifo_dout;
addr_fifo_din_do <= addr_fifo_din;
byte_swap_c <= "11";
fifo_rst <= not rst_n_i or fifo_rst_t;
ldm_arb_tvalid_o <= ldm_arb_valid;
ldm_arb_tdata_o <= ldm_arb_data_l;
l2p_64b_address <= '0' when l2p_address_h = X"00000000" else '1';
delay_p : process(clk_i)
begin
if rising_edge(clk_i) then
--ldm_arb_tready_s <= ldm_arb_tready_i;
data_fifo_empty_t <= data_fifo_empty;
end if;
end process delay_p;
---------------------
-- L2P FSM
---------------------
p_l2p_fsm : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
l2p_dma_current_state <= L2P_IDLE;
ldm_arb_req_o <= '0';
data_fifo_rd <= '0';
dma_ctrl_done_o <= '0';
l2p_edb_o <= '0';
l2p_timeout_cnt <= (others => '0');
fifo_rst_t <= '0';
data_fifo_valid <= '0';
elsif rising_edge(clk_i) then
case l2p_dma_current_state is
when L2P_IDLE =>
l2p_timeout_cnt <= (others => '0');
l2p_edb_o <= '0';
fifo_rst_t <= '0';
ldm_arb_req_o <= '0';
data_fifo_rd <= '0';
data_fifo_valid <= '0';
dma_ctrl_done_o <= '0';
data_fifo_valid <= '0';
if (dma_ctrl_start_l2p_i = '1') then
l2p_dma_current_state <= L2P_SETUP;
end if;
when L2P_SETUP =>
data_fifo_rd <= '0';
data_fifo_valid <= '0';
l2p_timeout_cnt <= (others => '0');
if (l2p_rdy_i = '1') then
l2p_dma_current_state <= L2P_HEADER_0;
ldm_arb_req_o <= '1'; -- Request bus
end if;
when L2P_HEADER_0 =>
if (arb_ldm_gnt_i = '1') then
ldm_arb_req_o <= '0'; -- Bus has been granted
-- Send header
l2p_dma_current_state <= L2P_HEADER_1;
end if;
when L2P_HEADER_1 =>
if (ldm_arb_tready_i = '1') then
l2p_dma_current_state <= L2P_DATA;
end if;
when L2P_DATA =>
if (data_fifo_empty = '0' and l2p_rdy_i = '1' and ldm_arb_tready_i = '1') then
data_fifo_rd <= '1';
else
data_fifo_rd <= '0';
end if;
if (data_fifo_rd = '1' and data_fifo_empty = '0' and l2p_data_cnt = 2 and l2p_64b_address = '1') then
l2p_dma_current_state <= L2P_LAST_DATA;
end if;
if (data_fifo_rd = '1' and data_fifo_empty = '0' and l2p_data_cnt = 1 and l2p_64b_address = '0') then
l2p_dma_current_state <= L2P_LAST_DATA;
data_fifo_rd <= '0'; -- Don't read too much
end if;
-- Error condition, abort transfer
--if (tx_error_i = '1' or l2p_timeout_cnt > c_TIMEOUT or wb_timeout_cnt > c_TIMEOUT or dma_ctrl_abort_i = '1') then
if (tx_error_i = '1' or l2p_timeout_cnt > c_TIMEOUT or dma_ctrl_abort_i = '1') then
l2p_dma_current_state <= L2P_ERROR;
end if;
-- Timeout counter
if (data_fifo_empty = '1' or l2p_rdy_i = '1' or ldm_arb_tready_i = '1') then
l2p_timeout_cnt <= l2p_timeout_cnt + 1;
else
l2p_timeout_cnt <= (others => '0');
end if;
when L2P_LAST_DATA =>
data_fifo_rd <= '0';
data_fifo_valid <= '0';
if (dma_ctrl_abort_i = '1' or tx_error_i = '1') then
l2p_dma_current_state <= L2P_IDLE;
dma_ctrl_done_o <= '1';
elsif (l2p_last_packet = '0') then
l2p_dma_current_state <= L2P_SETUP;
else
l2p_dma_current_state <= L2P_IDLE;
dma_ctrl_done_o <= '1';
end if;
when L2P_ERROR =>
l2p_edb_o <= '1';
fifo_rst_t <= '1';
l2p_dma_current_state <= L2P_IDLE;
when others =>
l2p_dma_current_state <= L2P_IDLE;
end case;
end if;
end process p_l2p_fsm;
data_reorder : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fifo_dout_1 <= (others => '0');
elsif (clk_i'event and clk_i = '1') then
if (l2p_dma_current_state = L2P_HEADER_1) then
data_fifo_dout_1(63 downto 32) <= f_byte_swap(true,l2p_address_l, byte_swap_c); -- for unswapping
elsif (data_fifo_rd = '1') then
--data_0_s <= data_i;
--data_1_s <= data_0_s;
data_fifo_dout_1 <= data_fifo_dout;
end if;
end if;
end process data_reorder;
to_arbiter : process(l2p_dma_current_state,l2p_byte_swap,data_fifo_dout,s_l2p_header,l2p_address_h,l2p_address_l,data_fifo_rd,data_fifo_empty)
begin
case l2p_dma_current_state is
when L2P_IDLE|L2P_SETUP =>
ldm_arb_data_l <= (others => '0');
ldm_arb_tlast_o <= '0';
ldm_arb_valid <= '0';
ldm_arb_tkeep_o <= x"FF";
when L2P_HEADER_0 =>
ldm_arb_data_l <= s_l2p_header;
ldm_arb_tlast_o <= '0';
ldm_arb_valid <= '1';
ldm_arb_tkeep_o <= x"FF";
when L2P_HEADER_1 =>
ldm_arb_data_l <= l2p_address_l & l2p_address_h;
ldm_arb_tlast_o <= '0';
if (l2p_64b_address = '1') then
ldm_arb_valid <= '1';
else
ldm_arb_valid <= '0';
end if;
ldm_arb_tkeep_o <= x"FF";
when L2P_DATA =>
if (l2p_64b_address = '1') then
--ldm_arb_data_l <= f_byte_swap_64(g_BYTE_SWAP, data_fifo_dout, l2p_byte_swap);
ldm_arb_data_l <= f_byte_swap(true, data_fifo_dout(63 downto 32), byte_swap_c) & f_byte_swap(true, data_fifo_dout(31 downto 0), byte_swap_c);
else
ldm_arb_data_l <= f_byte_swap(true, data_fifo_dout (31 downto 0), byte_swap_c) & f_byte_swap(true, data_fifo_dout_1 (63 downto 32), byte_swap_c);
--ldm_arb_data_l <= data_fifo_dout (31 downto 0) & data_fifo_dout_1 (63 downto 32);
end if;
ldm_arb_tlast_o <= '0';
ldm_arb_valid <= data_fifo_rd and not data_fifo_empty;
ldm_arb_tkeep_o <= x"FF";
when L2P_LAST_DATA =>
if (l2p_64b_address = '1') then
ldm_arb_data_l <= f_byte_swap(true, data_fifo_dout(63 downto 32), byte_swap_c) & f_byte_swap(true, data_fifo_dout(31 downto 0), byte_swap_c);
ldm_arb_tkeep_o <= x"FF";
else
ldm_arb_data_l <= f_byte_swap(true, data_fifo_dout (31 downto 0), byte_swap_c) & f_byte_swap(true, data_fifo_dout_1 (63 downto 32), byte_swap_c);
ldm_arb_tkeep_o <= x"0F";
end if;
ldm_arb_tlast_o <= '1';
ldm_arb_valid <= '1';
when others =>
ldm_arb_data_l <= x"DEADBEEF" & x"DEADBEEF";
ldm_arb_tlast_o <= '0';
ldm_arb_valid <= '0';
ldm_arb_tkeep_o <= x"FF";
end case;
end process to_arbiter;
---------------------
--- Paket Generator
---------------------
-- 01:00.0 Memory controller: Xilinx Corporation Device 7024
s_l2p_header(63 downto 48) <= l2p_rid_i;--X"0100"; --H1 Requester ID
s_l2p_header(47 downto 40) <= X"00"; --H1 Tag
s_l2p_header(39 downto 32) <= X"0f" when l2p_len_header = 1 else X"ff"; -- LBE (Last Byte Enable) & FBE (First Byte Enable)
s_l2p_header(31 downto 29) <= "011" when l2p_64b_address = '1' else "010"; -- H0 FMT
s_l2p_header(28 downto 24) <= "00000"; -- H0 type Memory request
s_l2p_header(23 downto 16) <= X"00"; -- some unused bits
s_l2p_header(15 downto 10) <= "000000"; --H0 unused bits
s_l2p_header(9 downto 0) <= STD_LOGIC_VECTOR(l2p_len_header(9 downto 0)); --> Length (in 32-bit words)
-- 0x000 => 1024 words (4096 bytes)
p_pkt_gen : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
l2p_len_cnt <= (others => '0');
l2p_data_cnt <= (others => '0');
l2p_address_h <= (others => '0');
l2p_address_l <= (others => '0');
l2p_len_header <= (others => '0');
l2p_byte_swap <= (others => '0');
l2p_last_packet <= '0';
elsif rising_edge(clk_i) then
if (l2p_dma_current_state = L2P_IDLE) then
l2p_len_cnt <= unsigned(dma_ctrl_len_i(15 downto 3)); -- That's it
l2p_address_h <= dma_ctrl_host_addr_h_i;
l2p_address_l <= dma_ctrl_host_addr_l_i;
l2p_byte_swap <= dma_ctrl_byte_swap_i;
l2p_last_packet <= '0';
elsif (l2p_dma_current_state = L2P_SETUP) then
if (l2p_len_cnt > c_L2P_MAX_PAYLOAD/2) then
l2p_data_cnt <= TO_UNSIGNED(c_L2P_MAX_PAYLOAD/2, 13);
l2p_len_header <= TO_UNSIGNED(c_L2P_MAX_PAYLOAD, 13);
l2p_last_packet <= '0';
elsif (l2p_len_cnt = c_L2P_MAX_PAYLOAD/2) then
l2p_data_cnt <= TO_UNSIGNED(c_L2P_MAX_PAYLOAD/2, 13);
l2p_len_header <= TO_UNSIGNED(c_L2P_MAX_PAYLOAD, 13);
l2p_last_packet <= '1';
else
l2p_data_cnt <= l2p_len_cnt;
l2p_len_header <= l2p_len_cnt(11 downto 0) & "0";
l2p_last_packet <= '1';
end if;
--elsif (l2p_dma_current_state = L2P_HEADER) then
--elsif (l2p_dma_current_state = L2P_ADDR_H) then
elsif (l2p_dma_current_state = L2P_HEADER_1) then
--l2p_data_cnt <= l2p_data_cnt -1;
elsif (l2p_dma_current_state = L2P_DATA) then
if (data_fifo_empty = '0' and data_fifo_rd = '1') then
--if (ldm_arb_valid = '1') then
l2p_data_cnt <= l2p_data_cnt - 1;
end if;
elsif (l2p_dma_current_state = L2P_LAST_DATA) then
if (l2p_last_packet = '0') then
-- Increase Address
-- TODO Not overflow safe !
l2p_address_l <= STD_LOGIC_VECTOR(unsigned(l2p_address_l) + (c_L2P_MAX_PAYLOAD * 4));
l2p_len_cnt <= l2p_len_cnt - c_L2P_MAX_PAYLOAD/2;
else
l2p_len_cnt <= (others => '0');
end if;
end if;
end if;
end process p_pkt_gen;
---------------------
-- Address Counter
---------------------
p_target_cnt : process (clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
target_addr_cnt <= (others => '0');
dma_length_cnt <= (others => '0');
dma_ctrl_error_o <= '0';
addr_fifo_wr <= '0';
addr_fifo_din <= (others => '0');
elsif rising_edge(clk_i) then
-- New Transfer started
if (l2p_dma_current_state = L2P_ERROR) then
target_addr_cnt <= (others => '0');
dma_ctrl_error_o <= '1';
addr_fifo_wr <= '0';
dma_length_cnt <= (others => '0');
elsif (dma_ctrl_start_l2p_i = '1') then
if (l2p_dma_current_state = L2P_IDLE) then
-- dma target adrr is byte address, need 32bit address
target_addr_cnt(31 downto 29) <= "000";
target_addr_cnt(28 downto 0) <= dma_ctrl_target_addr_i(31 downto 3);
-- dma target length is in byte, need 32bit
dma_length_cnt <= unsigned(dma_ctrl_len_i(15 downto 3)); -- That's it
dma_ctrl_error_o <= '0';
else
target_addr_cnt <= (others => '0');
dma_length_cnt <= (others => '0');
dma_ctrl_error_o <= '1';
end if;
addr_fifo_wr <= '0';
elsif (dma_length_cnt > 0) and (addr_fifo_full = '0') then
addr_fifo_wr <= '1';
target_addr_cnt <= STD_LOGIC_VECTOR(unsigned(target_addr_cnt) + 1);
dma_length_cnt <= dma_length_cnt - 1;
addr_fifo_din <= X"00000000" & target_addr_cnt; -- TODO
else
addr_fifo_wr <= '0';
dma_ctrl_error_o <= '0';
end if;
end if;
end process p_target_cnt;
---------------------
-- Wishbone Master
---------------------
-- Tie offs
l2p_dma_cyc_o <= l2p_dma_cyc_t;
l2p_dma_stb_o <= l2p_dma_stb_t; --and not addr_fifo_empty;
l2p_dma_dat_o <= (others => '0');
l2p_dma_we_o <= '0';
addr_fifo_valid <= not(addr_fifo_empty or l2p_dma_stall_i or data_fifo_full or p2l_dma_cyc_i);
p_wb_master : process (l2p_dma_clk_i, rst_n_i, wb_read_cnt)
begin
if (rst_n_i = '0') then
l2p_dma_stb_t <= '0';
l2p_dma_cyc_t <= '0';
l2p_dma_sel_o <= (others => '0');
addr_fifo_rd <= '0';
wb_read_cnt <= (others => '0');
wb_ack_cnt <= (others => '0');
l2p_dma_adr_o <= (others => '0');
wb_timeout_cnt <= (others => '0');
elsif rising_edge(l2p_dma_clk_i) then
l2p_dma_sel_o <= (others => '1');
l2p_dma_adr_o <= addr_fifo_dout;
if (addr_fifo_valid = '1') then
addr_fifo_rd <= '1';
else
addr_fifo_rd <= '0';
end if;
if (addr_fifo_rd = '1' and addr_fifo_empty = '0') then
l2p_dma_stb_t <= '1';
else
l2p_dma_stb_t <= '0';
end if;
if (l2p_dma_stb_t = '1' and l2p_dma_ack_i = '0' and l2p_dma_cyc_t = '1') then
wb_read_cnt <= wb_read_cnt + 1;
elsif (l2p_dma_stb_t = '0' and l2p_dma_ack_i = '1' and l2p_dma_cyc_t = '1') then
wb_read_cnt <= wb_read_cnt - 1;
end if;
if (addr_fifo_valid = '1') then
l2p_dma_cyc_t <= '1';
elsif (wb_read_cnt = 0) then
l2p_dma_cyc_t <= '0';
end if;
-- Timeout counter
if (l2p_dma_current_state = L2P_DATA and l2p_dma_ack_i = '0') then
wb_timeout_cnt <= wb_timeout_cnt + 1;
else
wb_timeout_cnt <= (others => '0');
end if;
end if;
end process p_wb_master;
-- Receive data
data_rec_proc : process(l2p_dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fifo_din <= x"DEADBABE" & x"DEADBABE";
data_fifo_wr <= '0';
elsif rising_edge(l2p_dma_clk_i) then
if (l2p_dma_cyc_t = '1') then
data_fifo_din <= l2p_dma_dat_i;
data_fifo_wr <= l2p_dma_ack_i;
else
data_fifo_din <= x"BABEDEAD" & x"BABEDEAD";
data_fifo_wr <= '0';
end if;
end if;
end process data_rec_proc;
---------------------
-- FIFOs
---------------------
cmp_addr_fifo : l2p_fifo
port map (
rst => fifo_rst,
wr_clk => clk_i,
rd_clk => l2p_dma_clk_i,
din => addr_fifo_din,
wr_en => addr_fifo_wr,
rd_en => addr_fifo_rd,
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(c_ADDR_FIFO_FULL_THRES, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(c_ADDR_FIFO_FULL_THRES-50, 10)),
dout => addr_fifo_dout,
full => open,
empty => addr_fifo_empty,
valid => open,
prog_full => addr_fifo_full
);
cmp_data_fifo : l2p_fifo
port map (
rst => fifo_rst,
wr_clk => l2p_dma_clk_i,
rd_clk => clk_i,
din => data_fifo_din,
wr_en => data_fifo_wr,
rd_en => data_fifo_rd,
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(c_DATA_FIFO_FULL_THRES, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(c_DATA_FIFO_FULL_THRES-50, 10)),
dout => data_fifo_dout,
full => open,
empty => data_fifo_empty,
valid => open,
prog_full => data_fifo_full
);
end behavioral;
|
gpl-3.0
|
06a0e0b4fa184d265685af3e2de5322a
| 0.502501 | 3.05063 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
mdio_set_100Full.vhd
| 1 | 3,230 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mdio_set_100Full is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
mdio_op : out STD_LOGIC;
mdio_addr : out STD_LOGIC_VECTOR (4 downto 0);
data_i : in STD_LOGIC_VECTOR (15 downto 0);
data_o : out STD_LOGIC_VECTOR (15 downto 0);
mdio_busy : in STD_LOGIC;
mdio_kick : out STD_LOGIC;
mnl_addr : in STD_LOGIC_VECTOR (4 downto 0);
mnl_trgr : in STD_LOGIC;
cfg_busy : out STD_LOGIC);
end mdio_set_100Full;
architecture Behavioral of mdio_set_100Full is
type state_t is (wait_rdy, write_caps, read_status, check_status, retry, done);
-- wait rdy
-- write abilities
-- loop reading autoneg done
-- restart autoneg, go back one
-- Initial setting to kick off state machine
signal state : state_t := wait_rdy;
signal trgt : state_t := write_caps;
signal NEXT_state, NEXT_trgt : state_t;
begin
cfg_busy <= '0' when state = done else '1';
fsm: process (state, mdio_busy, data_i, trgt, mnl_addr, mnl_trgr)
begin
NEXT_state <= state;
NEXT_trgt <= trgt;
mdio_op <= '0';
mdio_addr <= ( others => '0' );
mdio_kick <= '0';
data_o <= ( others => '0' );
case state is
when wait_rdy =>
if mdio_busy = '0' then
NEXT_state <= trgt;
end if;
when write_caps =>
NEXT_state <= wait_rdy;
NEXT_trgt <= read_status;
mdio_op <= '1';
mdio_addr <= b"00100";
data_o <= X"0181";
mdio_kick <= '1';
when read_status =>
NEXT_state <= wait_rdy;
NEXT_trgt <= check_status;
mdio_op <= '0';
mdio_addr <= b"11111";
mdio_kick <= '1';
when check_status =>
if data_i(12) = '0' then -- autoneg not done
NEXT_state <= read_status;
else
if data_i(4 downto 2) = b"110" then
NEXT_state <= done;
else
NEXT_state <= retry;
end if;
end if;
when retry =>
NEXT_state <= wait_rdy;
NEXT_trgt <= read_status;
mdio_op <= '1';
mdio_addr <= b"00000";
data_o <= X"8000";
mdio_kick <= '1';
when done =>
mdio_addr <= mnl_addr;
mdio_kick <= mnl_trgr;
end case;
end process;
fsm_next: process (clk)
begin
if RISING_EDGE(clk) then
state <= NEXT_state;
trgt <= NEXT_trgt;
if rst = '1' then
state <= wait_rdy;
trgt <= write_caps;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
5db96b5ccc0a3a701664a2e034138aed
| 0.601238 | 2.955169 | false | false | false | false |
metaspace/ghdl_extra
|
int_bool/test_bool.vhdl
| 1 | 672 |
-- test_bool.vhdl
use work.int_ops.all;
entity test_bool is end test_bool;
architecture test of test_bool is
begin
process
variable a, b, c : integer;
begin
b := 5; c := 12;
a := b nand c; report "nand: " & integer'image(a);
a := b and c; report " and: " & integer'image(a);
a := b nor c; report " nor: " & integer'image(a);
a := b or c; report " or : " & integer'image(a);
a := b xor c; report " xor: " & integer'image(a);
a := b sll c; report " sll: " & integer'image(a);
a := b srl c; report " srl: " & integer'image(a);
a := b sra c; report " sra: " & integer'image(a);
wait;
end process;
end test;
|
gpl-3.0
|
b6a6ff66f51b2eefb837ca7927f1b21a
| 0.547619 | 2.765432 | false | true | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/l2p_dma_bench.vhd
| 1 | 13,324 |
library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
entity l2p_dma_bench is
generic (
constant period : time := 100 ns;
constant axis_data_width_c : integer := 64;
constant wb_address_width_c : integer := 12;
constant wb_data_width_c : integer := 64
);
--port ();
end l2p_dma_bench;
architecture Behavioral of l2p_dma_bench is
signal clk_tbs : STD_LOGIC;
signal rst_tbs : STD_LOGIC;
signal rst_n_tbs : STD_LOGIC;
-- Test bench specific signals
signal step : integer range 1 to 10;
signal debug_time : integer;
-- From the DMA controller
signal dma_ctrl_target_addr_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_host_addr_h_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_host_addr_l_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_len_tbs : std_logic_vector(32-1 downto 0);
signal dma_ctrl_start_l2p_tbs : std_logic;
signal dma_ctrl_done_s : std_logic;
signal dma_ctrl_error_s : std_logic;
signal dma_ctrl_byte_swap_tbs : std_logic_vector(2 downto 0);
signal dma_ctrl_abort_tbs : std_logic;
-- To the arbiter (L2P data)
signal ldm_arb_tvalid_s : std_logic;
signal ldm_arb_tlast_s : std_logic;
signal ldm_arb_tdata_s : std_logic_vector(axis_data_width_c-1 downto 0);
signal ldm_arb_tkeep_s : std_logic_vector(axis_data_width_c/8-1 downto 0);
signal ldm_arb_tready_tbs : std_logic;
signal ldm_arb_req_s : std_logic;
signal arb_ldm_gnt_tbs : std_logic;
-- L2P channel control
signal l2p_edb_s : std_logic; -- Asserted when transfer is aborted
signal l2p_rdy_tbs : std_logic; -- De-asserted to pause transdert already in progress
signal l2p_64b_address_tbs : std_logic;
signal tx_error_tbs : std_logic; -- Asserted when unexpected or malformed paket received
-- DMA Interface (Pipelined Wishbone)
signal l2p_dma_adr_s : std_logic_vector(wb_data_width_c-1 downto 0);
signal l2p_dma_dat_s2m_s : std_logic_vector(wb_data_width_c-1 downto 0);
signal l2p_dma_dat_s2m_tbs : std_logic_vector(wb_data_width_c-1 downto 0);
signal l2p_dma_dat_m2s_s : std_logic_vector(wb_data_width_c-1 downto 0);
signal l2p_dma_sel_s : std_logic_vector(3 downto 0);
signal l2p_dma_cyc_s : std_logic;
signal l2p_dma_stb_s : std_logic;
signal l2p_dma_we_s : std_logic;
signal l2p_dma_ack_s : std_logic;
signal l2p_dma_ack_tbs : std_logic;
signal l2p_dma_stall_tbs : std_logic;
signal p2l_dma_cyc_tbs : std_logic; -- P2L dma WB cycle for bus arbitration
component l2p_dma_master is
generic (
g_BYTE_SWAP : boolean := false;
axis_data_width_c : integer := 64;
wb_address_width_c : integer := 64;
wb_data_width_c : integer := 64
);
port (
-- GN4124 core clk and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- From PCIe IP core
l2p_rid_i : in std_logic_vector(16-1 downto 0);
-- From the DMA controller
dma_ctrl_target_addr_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_h_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_host_addr_l_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_len_i : in std_logic_vector(32-1 downto 0);
dma_ctrl_start_l2p_i : in std_logic;
dma_ctrl_done_o : out std_logic;
dma_ctrl_error_o : out std_logic;
dma_ctrl_byte_swap_i : in std_logic_vector(2 downto 0);
dma_ctrl_abort_i : in std_logic;
-- To the arbiter (L2P data)
ldm_arb_tvalid_o : out std_logic;
ldm_arb_tlast_o : out std_logic;
ldm_arb_tdata_o : out std_logic_vector(axis_data_width_c-1 downto 0);
ldm_arb_tkeep_o : out std_logic_vector(axis_data_width_c/8-1 downto 0);
ldm_arb_tready_i : in std_logic;
ldm_arb_req_o : out std_logic;
arb_ldm_gnt_i : in std_logic;
-- L2P channel control
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l2p_rdy_i : in std_logic; -- De-asserted to pause transdert already in progress
tx_error_i : in std_logic; -- Asserted when unexpected or malformed paket received
-- DMA Interface (Pipelined Wishbone)
l2p_dma_clk_i : in std_logic;
l2p_dma_adr_o : out std_logic_vector(wb_address_width_c-1 downto 0);
l2p_dma_dat_i : in std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_dat_o : out std_logic_vector(wb_data_width_c-1 downto 0);
l2p_dma_sel_o : out std_logic_vector(3 downto 0);
l2p_dma_cyc_o : out std_logic;
l2p_dma_stb_o : out std_logic;
l2p_dma_we_o : out std_logic;
l2p_dma_ack_i : in std_logic;
l2p_dma_stall_i : in std_logic;
p2l_dma_cyc_i : in std_logic; -- P2L dma WB cycle for bus arbitration
--DMA Debug
l2p_current_state_do : out std_logic_vector (2 downto 0);
l2p_data_cnt_do : out unsigned(12 downto 0);
l2p_len_cnt_do : out unsigned(12 downto 0);
l2p_timeout_cnt_do : out unsigned(12 downto 0);
wb_timeout_cnt_do : out unsigned(12 downto 0);
-- Data FIFO
data_fifo_rd_do : out std_logic;
data_fifo_wr_do : out std_logic;
data_fifo_empty_do : out std_logic;
data_fifo_full_do : out std_logic;
data_fifo_dout_do : out std_logic_vector(axis_data_width_c-1 downto 0);
data_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0);
-- Addr FIFO
addr_fifo_rd_do : out std_logic;
addr_fifo_wr_do : out std_logic;
addr_fifo_empty_do : out std_logic;
addr_fifo_full_do : out std_logic;
addr_fifo_dout_do : out std_logic_vector(wb_address_width_c-1 downto 0);
addr_fifo_din_do : out std_logic_vector(axis_data_width_c-1 downto 0)
);
end component;
component bram_wbs is
generic (
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 32
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(wb_address_width_c-1 downto 0);
wb_dat_i : in std_logic_vector(wb_data_width_c-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(wb_data_width_c-1 downto 0);
wb_ack_o : out std_logic
);
end component;
begin
clk_p: process
begin
clk_tbs <= '1';
wait for period/2;
clk_tbs <= '0';
wait for period/2;
end process clk_p;
reset_p: process
begin
rst_tbs <= '1';
rst_n_tbs <= '0';
wait for period;
rst_tbs <= '0';
rst_n_tbs <= '1';
wait;
end process reset_p;
time_p: process
begin
debug_time <= 0;
wait for period;
loop
debug_time <= debug_time + 1;
wait for period;
end loop;
end process time_p;
wb_stimuli_p : process
variable counter : unsigned (15 downto 0);
begin
counter := to_unsigned(0,16);
l2p_dma_dat_s2m_tbs <= (others => '0');
l2p_dma_ack_tbs <= '0';
while counter <= to_unsigned(32,16) loop
if l2p_dma_cyc_s = '1' and (debug_time < 20 or debug_time > 25) then
wait for period;
--step_ddr <= 3;
l2p_dma_dat_s2m_tbs <= X"dead" & std_logic_vector(counter) & X"beef" & std_logic_vector(counter);
l2p_dma_ack_tbs <= '1';
counter := counter + 1;
else
wait for period;
l2p_dma_dat_s2m_tbs <= (others => '0');
l2p_dma_ack_tbs <= '0';
end if;
end loop;
l2p_dma_dat_s2m_tbs <= (others => '0');
l2p_dma_ack_tbs <= '0';
wait;
end process wb_stimuli_p;
stimuli_p: process
begin
step <= 1;
ldm_arb_tready_tbs <= '1'; -- Asserted when GN4124 is ready to receive master write
l2p_rdy_tbs <= '1'; -- De-asserted to pause transdert already in progress
l2p_64b_address_tbs <= '0';
tx_error_tbs <= '0'; -- Asserted when unexpected or malformed paket received
dma_ctrl_target_addr_tbs <= X"00000000";
dma_ctrl_host_addr_h_tbs <= X"00000000";
dma_ctrl_host_addr_l_tbs <= X"00000000";
dma_ctrl_len_tbs <= X"00000000";
dma_ctrl_start_l2p_tbs <= '0';
dma_ctrl_byte_swap_tbs <= "000";
dma_ctrl_abort_tbs <= '0';
arb_ldm_gnt_tbs <= '1';
l2p_dma_stall_tbs <= '0';
p2l_dma_cyc_tbs <= '0'; -- P2L dma WB cycle for bus arbitration
wait for period;
wait for period;
step <= 2;
ldm_arb_tready_tbs <= '1'; -- Asserted when GN4124 is ready to receive master write
l2p_rdy_tbs <= '1'; -- De-asserted to pause transdert already in progress
tx_error_tbs <= '0'; -- Asserted when unexpected or malformed paket received
dma_ctrl_target_addr_tbs <= X"00000000";
dma_ctrl_host_addr_h_tbs <= X"00000000";
dma_ctrl_host_addr_l_tbs <= X"c57334d0";
dma_ctrl_len_tbs <= X"00000100";
dma_ctrl_start_l2p_tbs <= '1';
dma_ctrl_byte_swap_tbs <= "000";
dma_ctrl_abort_tbs <= '0';
arb_ldm_gnt_tbs <= '1';
l2p_dma_stall_tbs <= '0';
p2l_dma_cyc_tbs <= '0'; -- P2L dma WB cycle for bus arbitration
wait for period;
step <= 3;
ldm_arb_tready_tbs <= '1'; -- Asserted when GN4124 is ready to receive master write
l2p_rdy_tbs <= '1'; -- De-asserted to pause transdert already in progress
tx_error_tbs <= '0'; -- Asserted when unexpected or malformed paket received
--dma_ctrl_target_addr_tbs <= X"00000010";
--dma_ctrl_host_addr_h_tbs <= X"00000000";
--dma_ctrl_host_addr_l_tbs <= X"0000005A";
--dma_ctrl_len_tbs <= X"00000080";
dma_ctrl_start_l2p_tbs <= '0';
dma_ctrl_byte_swap_tbs <= "000";
dma_ctrl_abort_tbs <= '0';
arb_ldm_gnt_tbs <= '1';
l2p_dma_stall_tbs <= '0';
p2l_dma_cyc_tbs <= '0'; -- P2L dma WB cycle for bus arbitration
wait for period;
step <= 4;
wait for period;
step <= 5;
wait for 20*period;
step <= 6;
wait for period;
step <= 7;
--ldm_arb_tready_tbs <= '0';
wait for period;
step <= 8;
--ldm_arb_tready_tbs <= '1';
wait;
end process stimuli_p;
-----------------------------------------------------------------------------
-- L2P DMA master
-----------------------------------------------------------------------------
dut1 : l2p_dma_master
port map
(
clk_i => clk_tbs,
rst_n_i => rst_n_tbs,
l2p_rid_i => X"0010",
dma_ctrl_target_addr_i => dma_ctrl_target_addr_tbs,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_tbs,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_tbs,
dma_ctrl_len_i => dma_ctrl_len_tbs,
dma_ctrl_start_l2p_i => dma_ctrl_start_l2p_tbs,
dma_ctrl_done_o => dma_ctrl_done_s,
dma_ctrl_error_o => dma_ctrl_error_s,
dma_ctrl_byte_swap_i => dma_ctrl_byte_swap_tbs,
dma_ctrl_abort_i => dma_ctrl_abort_tbs,
ldm_arb_tvalid_o => ldm_arb_tvalid_s,
ldm_arb_tlast_o => ldm_arb_tlast_s,
ldm_arb_tdata_o => ldm_arb_tdata_s,
ldm_arb_tkeep_o => ldm_arb_tkeep_s,
ldm_arb_req_o => ldm_arb_req_s,
arb_ldm_gnt_i => arb_ldm_gnt_tbs,
l2p_edb_o => l2p_edb_s,
ldm_arb_tready_i => ldm_arb_tready_tbs,
l2p_rdy_i => l2p_rdy_tbs,
--l2p_64b_address_i => l2p_64b_address_tbs,
tx_error_i => tx_error_tbs,
l2p_dma_clk_i => clk_tbs,
l2p_dma_adr_o => l2p_dma_adr_s,
l2p_dma_dat_i => l2p_dma_dat_s2m_tbs,--l2p_dma_dat_s2m_s,
l2p_dma_dat_o => l2p_dma_dat_m2s_s,
l2p_dma_sel_o => l2p_dma_sel_s,
l2p_dma_cyc_o => l2p_dma_cyc_s,
l2p_dma_stb_o => l2p_dma_stb_s,
l2p_dma_we_o => l2p_dma_we_s,
l2p_dma_ack_i => l2p_dma_ack_tbs,--l2p_dma_ack_s,
l2p_dma_stall_i => l2p_dma_stall_tbs,
p2l_dma_cyc_i => p2l_dma_cyc_tbs
);
dut2:bram_wbs
generic map (
ADDR_WIDTH => wb_address_width_c,
DATA_WIDTH => wb_data_width_c
)
port map (
-- SYS CON
clk => clk_tbs,
rst => rst_tbs,
-- Wishbone Slave in
wb_adr_i => l2p_dma_adr_s(wb_address_width_c - 1 downto 0),
wb_dat_i => l2p_dma_dat_m2s_s,
wb_we_i => l2p_dma_we_s,
wb_stb_i => l2p_dma_stb_s,
wb_cyc_i => l2p_dma_cyc_s,
wb_lock_i => l2p_dma_stb_s,
-- Wishbone Slave out
wb_dat_o => l2p_dma_dat_s2m_s,
wb_ack_o => l2p_dma_ack_s
);
end Behavioral;
|
gpl-3.0
|
ddea79a3a1ee30c01c7479fc91385517
| 0.552612 | 2.833688 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/banc.vhd
| 1 | 4,778 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Register bank --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pack_mips.all;
entity banc is
port (
clock : in bus1;
reset : in bus1;
-- Register addresses to read
reg_src1 : in bus5;
reg_src2 : in bus5;
-- Register address to write and its data
reg_dest : in bus5;
donnee : in bus32;
-- Write signal
cmd_ecr : in bus1;
-- Bank outputs
data_src1 : out bus32;
data_src2 : out bus32
);
end banc;
architecture rtl of banc is
-- The register bank
type tab_reg is array (1 to 31) of bus32;
signal registres : tab_reg;
signal adr_src1 : integer range 0 to 31;
signal adr_src2 : integer range 0 to 31;
signal adr_dest : integer range 0 to 31;
begin
adr_src1 <= to_integer(unsigned(reg_src1));
adr_src2 <= to_integer(unsigned(reg_src2));
adr_dest <= to_integer(unsigned(reg_dest));
data_src1 <= (others => '0') when adr_src1=0 else
registres(adr_src1);
data_src2 <= (others => '0') when adr_src2=0 else
registres(adr_src2);
process(clock)
begin
if clock = '1' and clock'event then
if reset='1' then
for i in 1 to 31 loop
registres(i) <= (others => '0');
end loop;
elsif cmd_ecr = '1' and adr_dest /= 0 then
-- The data is saved
registres(adr_dest) <= donnee;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
1667db5f66c0dedbcf83b72f29828476
| 0.356007 | 5.667853 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sources_1/imports/sources_1/cam_pkg.vhd
| 1 | 4,474 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.11.2012 05:36:01
-- Design Name:
-- Module Name: cam_pkg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use ieee.std_logic_arith.all;
package CAM_PKG is
constant Image_Width : positive := 480;
constant Image_Hight : positive := 640;
constant bytes_per_px : positive := 3;
subtype int8u is integer range 0 to 255;
type RGB_COLOR is record
r : integer range 0 TO 255;
g : integer range 0 TO 255;
b : integer range 0 TO 255;
end record;
type pixel_position is record
x : integer range 1 TO Image_Width;
y : integer range 1 TO Image_Hight;
end record;
type pixel is record
pos : pixel_position;
color : RGB_COLOR;
end record;
type sensor is record
pos : pixel_position;
color : RGB_COLOR;
max_pos : integer range 0 to 31;
min_pos : integer range 0 to 31;
end record;
subtype sensor_vector is std_logic_vector(63 downto 0);
type positions_array is array (31 downto 0) of pixel_position;
type color_array is array (31 downto 0) of RGB_COLOR;
type shift_position is array (16 downto 0) of integer range 0 to 8; --- FIXME größe 3 bit
function log2(n : natural) return natural;
function middle_value(v1 : in RGB_COLOR; v2 : in RGB_COLOR) return RGB_COLOR;
function color_distance(Pixel0 : in RGB_COLOR; Pixel1 : in RGB_COLOR) return integer;
function sensor2vector(sensor_t : sensor) return sensor_vector;
function vector2sensor(slv : sensor_vector) return sensor;
function or_reduct(slv : in std_logic_vector) return std_logic;
end package CAM_PKG;
package body CAM_PKG is
-----------------------------------------------------------------------------
function log2(n : natural) return natural is
begin
for i in 0 to 31 loop
if (2 ** i) >= n then
return i;
end if;
end loop;
return 32;
end log2;
function middle_value(v1 : in RGB_COLOR; v2 : in RGB_COLOR) return RGB_COLOR is
variable r : RGB_COLOR;
begin
r.r := (v1.r + v2.r)/2;
r.g := (v1.g + v2.g)/2;
r.b := (v1.b + v2.b)/2;
return r;
end function middle_value;
function color_distance(Pixel0 : in RGB_COLOR; Pixel1 : in RGB_COLOR) return integer is
begin
return (((Pixel0.r + Pixel0.g + Pixel0.b) - (Pixel1.r + Pixel1.g + Pixel1.b)));
end function color_distance;
function sensor2vector(sensor_t : sensor) return sensor_vector is
variable slv : sensor_vector;
begin
slv(63 downto 52) := std_logic_vector(to_unsigned(sensor_t.pos.x, 12));
slv(51 downto 40) := std_logic_vector(to_unsigned(sensor_t.pos.y, 12));
slv(39 downto 32) := std_logic_vector(to_unsigned(sensor_t.color.r, 8));
slv(31 downto 24) := std_logic_vector(to_unsigned(sensor_t.color.g, 8));
slv(23 downto 16) := std_logic_vector(to_unsigned(sensor_t.color.b, 8));
slv(15 downto 8) := std_logic_vector(to_signed(sensor_t.max_pos, 8));
slv(7 downto 0) := std_logic_vector(to_signed(sensor_t.min_pos, 8));
return slv;
end;
function vector2sensor(slv : sensor_vector) return sensor is
variable sensor_t : sensor;
begin
sensor_t.pos.x := to_integer(unsigned(slv(63 downto 52))); -- FIXME prüfen ob richtig funktioniert
sensor_t.pos.y := to_integer(unsigned(slv(51 downto 40)));
sensor_t.color.r := to_integer(unsigned(slv(39 downto 32)));
sensor_t.color.r := to_integer(unsigned(slv(31 downto 24)));
sensor_t.color.r := to_integer(unsigned(slv(23 downto 16)));
sensor_t.max_pos := to_integer(signed(slv(15 downto 08)));
sensor_t.min_pos := to_integer(signed(slv(07 downto 00)));
return sensor_t;
end;
function or_reduct(slv : in std_logic_vector) return std_logic is
variable res_v : std_logic;
begin
res_v := '0';
for i in slv'range loop
res_v := res_v or slv(i);
end loop;
return res_v;
end function;
--ENTITY orn IS
--GENERIC (n : INTEGER := 4);
--PORT (x : IN STD_LOGIC_VECTOR(1 TO n);
--f : OUT STD_LOGIC);
--END orn;
--
--ARCHITECTURE dataflow OF orn IS
--SIGNAL tmp : STD_LOGIC_VECTOR(1 TO n);
--BEGIN
--tmp <= (OTHERS => '0');
--f <= '0' WHEN x = tmp ELSE '1';
--END dataflow;
end package body CAM_PKG;
|
gpl-3.0
|
be357bbdf1bacb34c1407d9c08cb0ee4
| 0.636567 | 3.010767 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/base_line/allocator.vhd
| 11 | 12,730 |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end allocator;
architecture behavior of allocator is
-- so the idea is that we should have counters that keep track of credit!
signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0);
signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0);
signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0);
signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0);
signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0);
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
signal X_N_N, X_N_E, X_N_W, X_N_S, X_N_L: std_logic;
signal X_E_N, X_E_E, X_E_W, X_E_S, X_E_L: std_logic;
signal X_W_N, X_W_E, X_W_W, X_W_S, X_W_L: std_logic;
signal X_S_N, X_S_E, X_S_W, X_S_S, X_S_L: std_logic;
signal X_L_N, X_L_E, X_L_W, X_L_S, X_L_L: std_logic;
signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic;
signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic;
signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic;
signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic;
signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic;
component arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L:in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L:out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end component;
component arbiter_out is
port ( reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y:in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L :out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end component;
begin
-- sequential part
process(clk, reset)
begin
if reset = '0' then
-- we start with all full cradit
credit_counter_N_out <= (others=>'1');
credit_counter_E_out <= (others=>'1');
credit_counter_W_out <= (others=>'1');
credit_counter_S_out <= (others=>'1');
credit_counter_L_out <= (others=>'1');
elsif clk'event and clk = '1' then
credit_counter_N_out <= credit_counter_N_in;
credit_counter_E_out <= credit_counter_E_in;
credit_counter_W_out <= credit_counter_W_in;
credit_counter_S_out <= credit_counter_S_in;
credit_counter_L_out <= credit_counter_L_in;
end if;
end process;
-- The combionational part
grant_N_N <= grant_N_N_sig and not empty_N;
grant_N_E <= grant_N_E_sig and not empty_E;
grant_N_W <= grant_N_W_sig and not empty_W;
grant_N_S <= grant_N_S_sig and not empty_S;
grant_N_L <= grant_N_L_sig and not empty_L;
grant_E_N <= grant_E_N_sig and not empty_N;
grant_E_E <= grant_E_E_sig and not empty_E;
grant_E_W <= grant_E_W_sig and not empty_W;
grant_E_S <= grant_E_S_sig and not empty_S;
grant_E_L <= grant_E_L_sig and not empty_L;
grant_W_N <= grant_W_N_sig and not empty_N;
grant_W_E <= grant_W_E_sig and not empty_E;
grant_W_W <= grant_W_W_sig and not empty_W;
grant_W_S <= grant_W_S_sig and not empty_S;
grant_W_L <= grant_W_L_sig and not empty_L;
grant_S_N <= grant_S_N_sig and not empty_N;
grant_S_E <= grant_S_E_sig and not empty_E;
grant_S_W <= grant_S_W_sig and not empty_W;
grant_S_S <= grant_S_S_sig and not empty_S;
grant_S_L <= grant_S_L_sig and not empty_L;
grant_L_N <= grant_L_N_sig and not empty_N;
grant_L_E <= grant_L_E_sig and not empty_E;
grant_L_W <= grant_L_W_sig and not empty_W;
grant_L_S <= grant_L_S_sig and not empty_S;
grant_L_L <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
-- this process handels the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out
)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
arb_N_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_N_N, Req_X_E=> req_N_E, Req_X_W=>req_N_W, Req_X_S=>req_N_S, Req_X_L=>req_N_L,
X_N=>X_N_N, X_E=>X_N_E, X_W=>X_N_W, X_S=>X_N_S, X_L=>X_N_L);
arb_E_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_E_N, Req_X_E=> req_E_E, Req_X_W=>req_E_W, Req_X_S=>req_E_S, Req_X_L=>req_E_L,
X_N=>X_E_N, X_E=>X_E_E, X_W=>X_E_W, X_S=>X_E_S, X_L=>X_E_L);
arb_W_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_W_N, Req_X_E=> req_W_E, Req_X_W=>req_W_W, Req_X_S=>req_W_S, Req_X_L=>req_W_L,
X_N=>X_W_N, X_E=>X_W_E, X_W=>X_W_W, X_S=>X_W_S, X_L=>X_W_L);
arb_S_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_S_N, Req_X_E=> req_S_E, Req_X_W=>req_S_W, Req_X_S=>req_S_S, Req_X_L=>req_S_L,
X_N=>X_S_N, X_E=>X_S_E, X_W=>X_S_W, X_S=>X_S_S, X_L=>X_S_L);
arb_L_X: arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_L_N, Req_X_E=> req_L_E, Req_X_W=>req_L_W, Req_X_S=>req_L_S, Req_X_L=>req_L_L,
X_N=>X_L_N, X_E=>X_L_E, X_W=>X_L_W, X_S=>X_L_S, X_L=>X_L_L);
-- Y is N now
arb_X_N: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_N, X_E_Y => X_E_N, X_W_Y => X_W_N, X_S_Y => X_S_N, X_L_Y => X_L_N,
credit => credit_counter_N_out,
grant_Y_N => grant_N_N_sig,
grant_Y_E => grant_N_E_sig,
grant_Y_W => grant_N_W_sig,
grant_Y_S => grant_N_S_sig,
grant_Y_L => grant_N_L_sig);
-- Y is E now
arb_X_E: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_E, X_E_Y => X_E_E, X_W_Y => X_W_E, X_S_Y => X_S_E, X_L_Y => X_L_E,
credit => credit_counter_E_out,
grant_Y_N => grant_E_N_sig,
grant_Y_E => grant_E_E_sig,
grant_Y_W => grant_E_W_sig,
grant_Y_S => grant_E_S_sig,
grant_Y_L => grant_E_L_sig);
-- Y is W now
arb_X_W: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_W, X_E_Y => X_E_W, X_W_Y => X_W_W, X_S_Y => X_S_W, X_L_Y => X_L_W,
credit => credit_counter_W_out,
grant_Y_N => grant_W_N_sig,
grant_Y_E => grant_W_E_sig,
grant_Y_W => grant_W_W_sig,
grant_Y_S => grant_W_S_sig,
grant_Y_L => grant_W_L_sig);
-- Y is S now
arb_X_S: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_S, X_E_Y => X_E_S, X_W_Y => X_W_S, X_S_Y => X_S_S, X_L_Y => X_L_S,
credit => credit_counter_S_out,
grant_Y_N => grant_S_N_sig,
grant_Y_E => grant_S_E_sig,
grant_Y_W => grant_S_W_sig,
grant_Y_S => grant_S_S_sig,
grant_Y_L => grant_S_L_sig);
-- Y is L now
arb_X_L: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_L, X_E_Y => X_E_L, X_W_Y => X_W_L, X_S_Y => X_S_L, X_L_Y => X_L_L,
credit => credit_counter_L_out,
grant_Y_N => grant_L_N_sig,
grant_Y_E => grant_L_E_sig,
grant_Y_W => grant_L_W_sig,
grant_Y_S => grant_L_S_sig,
grant_Y_L => grant_L_L_sig);
valid_N <= grant_N;
valid_E <= grant_E;
valid_W <= grant_W;
valid_S <= grant_S;
valid_L <= grant_L;
END;
|
gpl-3.0
|
f017ed52e7d09fb2cabe8f14fa8fc73f
| 0.539513 | 2.542441 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
debouncer.vhd
| 2 | 1,921 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Input debouncer and stabilisation circuit
-- use to make sure inputs from buttons don't jump around
entity debouncer is
port (Clk : in std_logic;
Input : in std_logic;
Output : out std_logic);
end debouncer;
-- Operation:
-- There are two stages of input flop-flops followed by a counter
-- signal must stay high for 128 cycles of @Clk to make @Output
-- go high as well.
-- Output goes low as soon as output of second stage (@Input after
-- two clock cycles) goes low.
architecture Behavioral of debouncer is
signal stage_1, stage_2 : std_logic;
signal counter : std_logic_vector(7 downto 0);
begin
Output <= counter(7);
stage_1 <= Input when RISING_EDGE(Clk);
stage_2 <= stage_1 when RISING_EDGE(Clk);
cnt : process (Clk)
begin
if RISING_EDGE(Clk) then
if stage_2 = '1' and counter(7) = '0' then
counter <= counter + 1;
end if;
if stage_2 = '0' then
counter <= ( others => '0' );
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9fc2cec0da7acf397d5b6ba2b2c9bf31
| 0.661114 | 3.872984 | false | false | false | false |
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/data_generator/data_generator.vhd
| 1 | 15,837 |
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Jakub Cabal <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/mig_ddr3_wrapper_virtex6
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity DATA_GENERATOR is
Port (
-- CLOCKS AND RESETS
CLK : in std_logic;
RST : in std_logic;
-- USER INTERFACE TO UART MODULE
UART_WR_DATA : out std_logic_vector(7 downto 0);
UART_WR_EN : out std_logic;
UART_BUSY : in std_logic;
UART_RD_DATA : in std_logic_vector(7 downto 0);
UART_RD_DATA_VLD : in std_logic;
UART_FRAME_ERROR : in std_logic;
-- MIG WRAPPER INTERFACE
MIG_ADDR : out std_logic_vector(24 downto 0);
MIG_READY : in std_logic;
MIG_RD_EN : out std_logic;
MIG_WR_EN : out std_logic;
MIG_WR_DATA : out std_logic_vector(511 downto 0);
MIG_RD_DATA : in std_logic_vector(511 downto 0);
MIG_RD_DATA_VLD : in std_logic
);
end DATA_GENERATOR;
architecture FULL of DATA_GENERATOR is
constant TEST_ADDR : unsigned(24 downto 0) := "0000000000000000011111111";
constant TEST_DATA : std_logic_vector(511 downto 0)
:= X"00000000111111112222222233333333444444445555555566666666777777778888888899999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEE01234567";
signal generator_mode : std_logic_vector(2 downto 0);
signal uart_data_reg : std_logic_vector(31 downto 0);
signal uart_data_reg_sel : std_logic_vector(1 downto 0);
signal uart_data_reg_en : std_logic;
signal uart_rd_data_reg : std_logic_vector(7 downto 0);
signal uart_rd_data_reg_en : std_logic;
signal cnt_rst : std_logic;
signal mig_addr_sig : unsigned(24 downto 0);
signal cnt_wr_req : unsigned(31 downto 0);
signal cnt_rd_req : unsigned(31 downto 0);
signal cnt_rd_resp : unsigned(31 downto 0);
signal mig_rd_data_part : std_logic_vector(31 downto 0);
signal sel_data_part_reg_en : std_logic;
signal sel_data_part : std_logic_vector(3 downto 0);
signal sel_data_part_int : integer range 0 to 15;
signal test_wr_data_for_seq : unsigned(511 downto 0);
signal mig_wr_en_sig : std_logic;
signal mig_rd_en_sig : std_logic;
type state is (idle, one_request, seq_request, load_data, select_data, send_byte_0, send_byte_1, send_byte_2, send_byte_3);
signal scmdp_pstate : state;
signal scmdp_nstate : state;
begin
-- -------------------------------------------------------------------------
-- SIMPLE CMD PROTOCOL (SCMDP) FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
scmdp_pstate_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
scmdp_pstate <= idle;
else
scmdp_pstate <= scmdp_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (scmdp_pstate, UART_FRAME_ERROR, UART_RD_DATA_VLD, UART_RD_DATA, UART_BUSY, uart_data_reg, uart_rd_data_reg)
begin
UART_WR_DATA <= X"00";
UART_WR_EN <= '0';
generator_mode <= "000";
cnt_rst <= '0';
uart_data_reg_sel <= "00";
uart_data_reg_en <= '0';
uart_rd_data_reg_en <= '0';
sel_data_part_reg_en <= '0';
case scmdp_pstate is
when idle =>
if (UART_FRAME_ERROR = '0' AND UART_RD_DATA_VLD = '1') then
case UART_RD_DATA(7 downto 4) is
when X"0" =>
scmdp_nstate <= one_request;
when X"1" =>
scmdp_nstate <= seq_request;
when X"2" =>
scmdp_nstate <= load_data;
when X"3" =>
scmdp_nstate <= select_data;
when others =>
scmdp_nstate <= idle;
end case;
uart_rd_data_reg_en <= '1';
else
uart_rd_data_reg_en <= '0';
scmdp_nstate <= idle;
end if;
when one_request =>
case uart_rd_data_reg(3 downto 0) is
when X"1" => -- ONE WRITE
generator_mode <= "001";
cnt_rst <= '0';
when X"2" => -- ONE READ
generator_mode <= "010";
cnt_rst <= '0';
when X"F" => -- RESET ALL COUNTERS
generator_mode <= "000";
cnt_rst <= '1';
when others =>
generator_mode <= "000";
cnt_rst <= '0';
end case;
scmdp_nstate <= idle;
when seq_request =>
case uart_rd_data_reg(3 downto 0) is
when X"1" => -- SEQ WRITE
generator_mode <= "011";
when X"2" => -- SEQ READ
generator_mode <= "100";
when X"3" => -- SEQ READ AND WRITE (1:1) - SAME ADDRESS FOR ONE READ AND WRITE CYCLE
generator_mode <= "101";
when others =>
generator_mode <= "000";
end case;
if (UART_FRAME_ERROR = '0' AND UART_RD_DATA_VLD = '1') then
if (UART_RD_DATA = X"10") then -- STOP SEQ TEST
scmdp_nstate <= idle;
else
scmdp_nstate <= seq_request;
end if;
else
scmdp_nstate <= seq_request;
end if;
when select_data =>
sel_data_part_reg_en <= '1';
scmdp_nstate <= idle;
when load_data =>
case uart_rd_data_reg(3 downto 0) is
when X"1" => -- CNT_WR_REQ
uart_data_reg_sel <= "01";
when X"2" => -- CNT_RD_REQ
uart_data_reg_sel <= "10";
when X"3" => -- CNT_RD_RESP
uart_data_reg_sel <= "11";
when X"4" => -- LAST_RD_DATA_PART
uart_data_reg_sel <= "00";
when others =>
uart_data_reg_sel <= "00";
end case;
uart_data_reg_en <= '1';
scmdp_nstate <= send_byte_0;
when send_byte_0 =>
UART_WR_DATA <= uart_data_reg(31 downto 24);
UART_WR_EN <= '1';
if (UART_BUSY = '0') then
scmdp_nstate <= send_byte_1;
else
scmdp_nstate <= send_byte_0;
end if;
when send_byte_1 =>
UART_WR_DATA <= uart_data_reg(23 downto 16);
UART_WR_EN <= '1';
if (UART_BUSY = '0') then
scmdp_nstate <= send_byte_2;
else
scmdp_nstate <= send_byte_1;
end if;
when send_byte_2 =>
UART_WR_DATA <= uart_data_reg(15 downto 8);
UART_WR_EN <= '1';
if (UART_BUSY = '0') then
scmdp_nstate <= send_byte_3;
else
scmdp_nstate <= send_byte_2;
end if;
when send_byte_3 =>
UART_WR_DATA <= uart_data_reg(7 downto 0);
UART_WR_EN <= '1';
if (UART_BUSY = '0') then
scmdp_nstate <= idle;
else
scmdp_nstate <= send_byte_3;
end if;
when others =>
scmdp_nstate <= idle;
end case;
end process;
-- UART READ DATA REGISTER
uart_rd_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_rd_data_reg <= (others => '0');
elsif (uart_rd_data_reg_en = '1') then
uart_rd_data_reg <= UART_RD_DATA;
end if;
end if;
end process;
-- UART DATA REGISTER
uart_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_data_reg <= (others => '0');
elsif (uart_data_reg_en = '1') then
case uart_data_reg_sel is
when "00" =>
uart_data_reg <= mig_rd_data_part;
when "01" =>
uart_data_reg <= std_logic_vector(cnt_wr_req);
when "10" =>
uart_data_reg <= std_logic_vector(cnt_rd_req);
when "11" =>
uart_data_reg <= std_logic_vector(cnt_rd_resp);
when others =>
uart_data_reg <= (others => '0');
end case;
end if;
end if;
end process;
-- SEL DATA PART REGISTER
sel_data_part_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sel_data_part <= (others => '0');
elsif (sel_data_part_reg_en = '1') then
sel_data_part <= uart_rd_data_reg(3 downto 0);
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- MIG DATA GENERATOR
-- -------------------------------------------------------------------------
MIG_ADDR <= std_logic_vector(mig_addr_sig);
MIG_WR_EN <= mig_wr_en_sig;
MIG_RD_EN <= mig_rd_en_sig;
test_wr_data_for_seq <= cnt_wr_req & cnt_wr_req & cnt_wr_req & cnt_wr_req &
cnt_wr_req & cnt_wr_req & cnt_wr_req & cnt_wr_req &
cnt_wr_req & cnt_wr_req & cnt_wr_req & cnt_wr_req &
cnt_wr_req & cnt_wr_req & cnt_wr_req & cnt_wr_req;
-- MIG DATA GENERATOR REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1' OR cnt_rst = '1') then
mig_addr_sig <= (others => '0');
MIG_WR_DATA <= (others => '0');
mig_wr_en_sig <= '0';
mig_rd_en_sig <= '0';
cnt_wr_req <= (others => '0');
cnt_rd_req <= (others => '0');
elsif (MIG_READY = '1') then
case generator_mode is
when "000" => -- IDLE
mig_addr_sig <= (others => '0');
MIG_WR_DATA <= (others => '0');
mig_wr_en_sig <= '0';
mig_rd_en_sig <= '0';
cnt_wr_req <= cnt_wr_req;
cnt_rd_req <= cnt_rd_req;
when "001" => -- ONE WRITE
mig_addr_sig <= TEST_ADDR;
MIG_WR_DATA <= TEST_DATA;
mig_wr_en_sig <= '1';
mig_rd_en_sig <= '0';
cnt_wr_req <= cnt_wr_req + 1;
cnt_rd_req <= cnt_rd_req;
when "010" => -- ONE READ
mig_addr_sig <= TEST_ADDR;
MIG_WR_DATA <= (others => '0');
mig_wr_en_sig <= '0';
mig_rd_en_sig <= '1';
cnt_wr_req <= cnt_wr_req;
cnt_rd_req <= cnt_rd_req + 1;
when "011" => -- SEQ WRITE
mig_addr_sig <= mig_addr_sig + 1; -- SEQ ADDR
MIG_WR_DATA <= std_logic_vector(test_wr_data_for_seq);
mig_wr_en_sig <= '1';
mig_rd_en_sig <= '0';
cnt_wr_req <= cnt_wr_req + 1;
cnt_rd_req <= cnt_rd_req;
when "100" => -- SEQ READ
mig_addr_sig <= mig_addr_sig + 1; -- SEQ ADDR
MIG_WR_DATA <= (others => '0');
mig_wr_en_sig <= '0';
mig_rd_en_sig <= '1';
cnt_wr_req <= cnt_wr_req;
cnt_rd_req <= cnt_rd_req + 1;
when "101" => -- SEQ READ AND WRITE (1:1) - SAME ADDRESS FOR ONE READ AND WRITE CYCLE
MIG_WR_DATA <= std_logic_vector(test_wr_data_for_seq);
if (mig_wr_en_sig = '1') then
mig_addr_sig <= mig_addr_sig;
mig_wr_en_sig <= '0';
mig_rd_en_sig <= '1';
cnt_wr_req <= cnt_wr_req;
cnt_rd_req <= cnt_rd_req + 1;
else
mig_addr_sig <= mig_addr_sig + 1;
mig_wr_en_sig <= '1';
mig_rd_en_sig <= '0';
cnt_wr_req <= cnt_wr_req + 1;
cnt_rd_req <= cnt_rd_req;
end if ;
when others =>
mig_addr_sig <= (others => '0');
MIG_WR_DATA <= (others => '0');
mig_wr_en_sig <= '0';
mig_rd_en_sig <= '0';
cnt_wr_req <= cnt_wr_req;
cnt_rd_req <= cnt_rd_req;
end case;
end if;
end if;
end process;
sel_data_part_int <= to_integer(unsigned(sel_data_part));
-- MIG DATA RECEIVER REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1' OR cnt_rst = '1') then
cnt_rd_resp <= (others => '0');
mig_rd_data_part <= (others => '0');
elsif (MIG_RD_DATA_VLD = '1') then
cnt_rd_resp <= cnt_rd_resp + 1;
mig_rd_data_part <= MIG_RD_DATA((32*sel_data_part_int)+31 downto (32*sel_data_part_int));
end if;
end if;
end process;
end FULL;
|
mit
|
62112033b9399072bc58940e566c00d2
| 0.42969 | 4.107106 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_IIR_SO.vhd
| 1 | 10,031 |
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- Implementation of a discrete-time, second-order, direct-form I IIR filter. --
-- This filter uses fixed point arithmetic to do it's calculations and can be --
-- described by the following mathematical formula: --
-- Y[k] = B0*X[k] + B1*X[k-1] + B2*X[k-2] + A1*Y[k-1] + A2*Y[k-1] --
-- --
-- --
-- Generic: --
-- IN_WIDTH - The width of the input signal --
-- IN_FRACT - The width of the fractional part of the input signal --
-- COEFFICIENT_WIDTH - The width of the filter coefficients --
-- COEFFICIENT_FRACT - The width of the fractional part of the filter --
-- coefficients --
-- INTERNAL_WIDTH - The width of internal states of the filter --
-- INTERNAL_FRACT - The width of the fractional part of internal states in --
-- the filter --
-- OUT_WIDTH - The width of the output signal --
-- OUT_FRACT - The width of the fractional part of the output signal --
-- --
-- --
-- Input/Output: --
-- clk - System clock --
-- reset - Asynchronous reset that resets when high --
-- x - Input signal to be filtered --
-- B0 - Coefficient --
-- B1 - Coefficient --
-- B2 - Coefficient --
-- A1 - Coefficient --
-- A2 - Coefficient --
-- y - Output signal --
-- --
-- --
-- Internal Constants: --
-- N - Number of coefficients, this number is three for a --
-- second order filter and should not be changed. The --
-- constant is mearly there to simplify creation of --
-- higher order filters. Note that for this to be done --
-- successfully, you have to increase the number of --
-- coefficients as well. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_IIR_SO is
generic (IN_WIDTH : natural := 16;
IN_FRACT : natural := 15;
COEFFICIENT_WIDTH : natural := 16;
COEFFICIENT_FRACT : natural := 15;
INTERNAL_WIDTH : natural := 32;
INTERNAL_FRACT : natural := 30;
OUT_WIDTH : natural := 16;
OUT_FRACT : natural := 15);
port(clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(IN_WIDTH-1 downto 0);
B0 : in std_logic_vector(COEFFICIENT_WIDTH-1 downto 0);
B1 : in std_logic_vector(COEFFICIENT_WIDTH-1 downto 0);
B2 : in std_logic_vector(COEFFICIENT_WIDTH-1 downto 0);
A1 : in std_logic_vector(COEFFICIENT_WIDTH-1 downto 0);
A2 : in std_logic_vector(COEFFICIENT_WIDTH-1 downto 0);
y : out std_logic_vector(OUT_WIDTH-1 downto 0));
end Generic_IIR_SO;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_IIR_SO is
-- Constants
constant N : natural := 3; -- Number of x-coefficients
constant IN_INT : natural := IN_WIDTH - IN_FRACT;
constant COEFFICIENT_INT : natural := COEFFICIENT_WIDTH - COEFFICIENT_FRACT;
constant INTERNAL_INT : natural := INTERNAL_WIDTH - INTERNAL_FRACT;
constant OUT_INT : natural := OUT_WIDTH - OUT_FRACT;
constant PRODUCT_WIDTH : natural := COEFFICIENT_WIDTH + INTERNAL_WIDTH;
constant PRODUCT_FRACT : natural := COEFFICIENT_FRACT + INTERNAL_FRACT;
constant PRODUCT_INT : natural := PRODUCT_WIDTH - PRODUCT_FRACT;
-- Type declarations
type array_coeffecient is array(0 to N-1) of std_logic_vector(COEFFICIENT_WIDTH-1 downto 0);
type array_internal is array(0 to N-1) of std_logic_vector(INTERNAL_WIDTH-1 downto 0);
-- Coefficients
signal coefficients_b : array_coeffecient;
signal coefficients_a : array_coeffecient;
-- Signal Declarations
signal input_copy : std_logic_vector(INTERNAL_WIDTH-1 downto 0);
signal my_inputs : array_internal := (others => (others => '0'));
signal my_outputs : array_internal := (others => (others => '0'));
signal my_mults_in : array_internal := (others => (others => '0'));
signal my_mults_out : array_internal := (others => (others => '0'));
signal my_sum_in : array_internal := (others => (others => '0'));
signal my_sum_out : array_internal := (others => (others => '0'));
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Assign coefficients
coefficients_b(0) <= B0;
coefficients_b(1) <= B1;
coefficients_b(2) <= B2;
coefficients_a(1) <= A1;
coefficients_a(2) <= A2;
-- Prepare input to fit into internal bit width
input_copy(INTERNAL_WIDTH-1 downto INTERNAL_FRACT + IN_INT) <= (others => x(IN_WIDTH-1));
input_copy(INTERNAL_FRACT + IN_INT-1 downto INTERNAL_FRACT - IN_FRACT) <= x;
input_copy(INTERNAL_FRACT - IN_FRACT-1 downto 0) <= (others => x(IN_WIDTH-1));
-- Shift input and ouput
VectorRegisterIn0 : entity work.VectorRegister
generic map (
wordLength => INTERNAL_WIDTH)
port map (
input => input_copy,
output => my_inputs(0),
clk => clk,
reset => reset);
my_outputs(0) <= my_sum_out(0);
gen_shifts:
for i in 0 to N-2 generate
VectorRegisterIn : entity work.VectorRegister
generic map (
wordLength => INTERNAL_WIDTH)
port map (
input => my_inputs(i),
output => my_inputs(i+1),
clk => clk,
reset => reset);
VectorRegisterOut : entity work.VectorRegister
generic map (
wordLength => INTERNAL_WIDTH)
port map (
input => my_outputs(i),
output => my_outputs(i+1),
clk => clk,
reset => reset);
end generate gen_shifts;
-- Multiply the input with coefficients
gen_mults_in:
for i in 0 to N-1 generate
Multiplier_in : entity work.Multiplier
generic map(X_WIDTH => INTERNAL_WIDTH,
X_FRACTION => INTERNAL_FRACT,
Y_WIDTH => COEFFICIENT_WIDTH,
Y_FRACTION => COEFFICIENT_FRACT,
S_WIDTH => INTERNAL_WIDTH,
S_FRACTION => INTERNAL_FRACT)
port map(x => my_inputs(i),
y => coefficients_b(i),
s => my_mults_in(i));
end generate gen_mults_in;
-- Add the input multiplications together
my_sum_in(N-1) <= my_mults_in(N-1);
gen_adds_in:
for i in 0 to N-2 generate
AdderSat_in : entity work.AdderSat
generic map(wordLength => INTERNAL_WIDTH)
port map(a => my_mults_in(i),
b => my_sum_in(i+1),
s => my_sum_in(i));
end generate gen_adds_in;
-- Add the output multiplications together
my_sum_out(N-1) <= my_mults_out(N-1);
AdderSat_0 : entity work.AdderSat
generic map(wordLength => INTERNAL_WIDTH)
port map(a => my_sum_in(0),
b => my_sum_out(1),
s => my_sum_out(0));
gen_adds_out:
for i in 1 to N-2 generate
AdderSat_out : entity work.AdderSat
generic map(wordLength => INTERNAL_WIDTH)
port map(a => my_mults_out(i),
b => my_sum_out(i+1),
s => my_sum_out(i));
end generate gen_adds_out;
-- Multiply the output with coefficients
gen_mults_out:
for i in 1 to N-1 generate
Multiplier_out : entity work.Multiplier
generic map(X_WIDTH => INTERNAL_WIDTH,
X_FRACTION => INTERNAL_FRACT,
Y_WIDTH => COEFFICIENT_WIDTH,
Y_FRACTION => COEFFICIENT_FRACT,
S_WIDTH => INTERNAL_WIDTH,
S_FRACTION => INTERNAL_FRACT)
port map(x => my_outputs(i),
y => coefficients_a(i),
s => my_mults_out(i));
end generate gen_mults_out;
-- Output the result
y <= my_outputs(0)(INTERNAL_FRACT + OUT_INT-1 downto INTERNAL_FRACT - OUT_FRACT);
end behaviour;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
|
mit
|
38b031a0970c3d3459e2d3386e670e06
| 0.451401 | 4.648285 | false | false | false | false |
metaspace/ghdl_extra
|
io_port/telecran.vhdl
| 1 | 2,557 |
-- Fichier : telecran.vhdl
-- création : dim. oct. 31 13:00:03 CET 2010
-- An example program using the "buttons" package
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library work; use work.boutons.all; -- boutons
use work.fb_ghdl.all; -- framebuffer
use work.rt_utils.all; -- horloge
library ieee; use ieee.std_logic_1164.all;
entity telecran is end telecran;
architecture tele of telecran is
signal clk, stop : std_ulogic := '0';
begin
-- instanciation de l'horloge :
horloge : entity work.rt_clk
generic map(ms => 10)
port map(clk => clk, stop => stop);
process(clk)
variable couleur : integer := -1; -- couleur initiale : blanc
variable l : integer := 10; -- longueur des côtés du carré
-- coordonnées d'origine : au centre de l'écran
variable x : integer := fbx/2;
variable y : integer := fby/2;
procedure dessine_carre is
variable i,j : integer;
begin
for i in 0 to l-1 loop
for j in 0 to l-1 loop
pixel(y+i,x+j) := couleur;
end loop;
end loop;
couleur := couleur - 1; -- change lentement la couleur;
end procedure;
variable b1, b2, b3, b4 : std_ulogic;
begin
lecture_boutons(b1, b2, b3, b4);
if b1='1' then -- aller à gauche : décrémenter x
if x > 0 then
x := x-1;
end if;
else
if b2='1' then -- aller à droite : incrémenter x
if x < (fbx1-l) then
x := x+1;
end if;
else
if b3='1' then -- aller en haut : décrémenter y
if y > 0 then
y := y-1;
end if;
else
if b4='1' then -- aller en bas : incrémenter y
if y < (fby1-l) then
y := y+1;
end if;
end if;
end if;
end if;
end if;
-- affiche en continu le carré :
dessine_carre;
end process;
end tele;
|
gpl-3.0
|
8c86c9390ed1cef7542a7c2a908ee5f4
| 0.605822 | 3.491758 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/IPFIRDecimator.vhd
| 1 | 1,309 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity IPFIRDecimator is
port (
input : in std_logic_vector(11 downto 0);
output : out std_logic_vector(15 downto 0);
clk : in std_logic;
reset : in std_logic
);
end entity ; -- IPFIRDecimator
architecture arch of IPFIRDecimator is
COMPONENT fir_compiler_0
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
signal inputValid : std_logic;
signal inputReady : std_logic;
signal filterOutput : std_logic_vector(15 downto 0);
signal outputValid : std_logic;
signal resetn : std_logic;
begin
inputValid <= clk and inputReady;
resetn <= not(reset);
FIR : fir_compiler_0
port map (
aclk => clk,
aresetn => resetn,
s_axis_data_tvalid => inputValid,
s_axis_data_tready => inputReady,
s_axis_data_tdata => input,
m_axis_data_tdata => filterOutput,
m_axis_data_tvalid => outputValid
);
OutputReg : entity work.Delay
port map (
input => filterOutput,
output => output,
clk => outputValid,
reset => reset
);
end architecture ; -- arch
|
mit
|
f30bda7f52bfcc200197af6024f29dc6
| 0.683728 | 2.934978 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_bus_get_last_nbits.vhd
| 1 | 2,441 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_bus_get_last_nbits IS
END tb_bus_get_last_nbits;
ARCHITECTURE behavior OF tb_bus_get_last_nbits IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bus_get_last_nbits
GENERIC (N_BITS : integer);
PORT( Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
Value : out std_logic_vector(N_BITS - 1 downto 0);
ValueEn : out std_logic);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal PktIn : std_logic := '0';
signal DataIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Value : std_logic_vector(8 downto 0);
signal ValueEn : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bus_get_last_nbits
GENERIC MAP ( N_BITS => 9 )
PORT MAP (
Clk => Clk,
Rst => Rst,
PktIn => PktIn,
DataIn => DataIn,
Value => Value,
ValueEn => ValueEn
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
PktIn <= '1';
for i in 1 to 10 loop
DataIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
e898034ccc0452d2f973ee0cb07b4377
| 0.630889 | 3.547965 | false | false | false | false |
Project-Bonfire/Bonfire
|
Packages/router_pack_vc.vhd
| 1 | 7,820 |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package router_pack is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
valid_in_vc: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_en_vc_N : in std_logic;
read_en_vc_E : in std_logic;
read_en_vc_W : in std_logic;
read_en_vc_S : in std_logic;
read_en_vc_L : in std_logic;
credit_out: out std_logic;
credit_out_vc: out std_logic;
empty_out: out std_logic;
empty_out_vc: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
Data_out_vc: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- vc signals
credit_in_vc_N, credit_in_vc_E, credit_in_vc_W, credit_in_vc_S, credit_in_vc_L: in std_logic;
req_N_N_vc, req_N_E_vc, req_N_W_vc, req_N_S_vc, req_N_L_vc: in std_logic;
req_E_N_vc, req_E_E_vc, req_E_W_vc, req_E_S_vc, req_E_L_vc: in std_logic;
req_W_N_vc, req_W_E_vc, req_W_W_vc, req_W_S_vc, req_W_L_vc: in std_logic;
req_S_N_vc, req_S_E_vc, req_S_W_vc, req_S_S_vc, req_S_L_vc: in std_logic;
req_L_N_vc, req_L_E_vc, req_L_W_vc, req_L_S_vc, req_L_L_vc: in std_logic;
empty_vc_N, empty_vc_E, empty_vc_W, empty_vc_S, empty_vc_L: in std_logic;
valid_vc_N, valid_vc_E, valid_vc_W, valid_vc_S, valid_vc_L : out std_logic;
grant_N_N_vc, grant_N_E_vc, grant_N_W_vc, grant_N_S_vc, grant_N_L_vc: out std_logic;
grant_E_N_vc, grant_E_E_vc, grant_E_W_vc, grant_E_S_vc, grant_E_L_vc: out std_logic;
grant_W_N_vc, grant_W_E_vc, grant_W_W_vc, grant_W_S_vc, grant_W_L_vc: out std_logic;
grant_S_N_vc, grant_S_E_vc, grant_S_W_vc, grant_S_S_vc, grant_S_L_vc: out std_logic;
grant_L_N_vc, grant_L_E_vc, grant_L_W_vc, grant_L_S_vc, grant_L_L_vc: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
cur_addr_y, cur_addr_x: in std_logic_vector(6 downto 0);
dst_addr_y, dst_addr_x: in std_logic_vector(6 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
North_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_vc_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (9 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT NI_vc is
generic(current_x : integer := 10; -- the current node's x
current_y : integer := 10; -- the current node's y
NI_depth : integer := 32;
NI_couter_size: integer:= 5; -- should be set to log2 of NI_depth
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111110"; -- NI's memory mapped reserved VC_0
reserved_address_vc : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- NI's memory mapped reserved for VC_1
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the flag register
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- packet counter register address!
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- interrupt signal: disabled!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
credit_in_vc: in std_logic;
valid_out_vc: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
credit_out_vc: out std_logic;
valid_in_vc: in std_logic;
RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC
);
end COMPONENT; --entity NI_vc
end; --package body
|
gpl-3.0
|
ccb2e0de536400dc0b470f4556eff872
| 0.558568 | 3.083596 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/p2l_decoder_bench.vhd
| 1 | 20,931 |
library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
use work.wshexp_core_pkg.all;
entity p2l_decoder_bench is
generic (
constant period : time := 100 ns;
constant axis_data_width_c : integer := 64;
constant axis_rx_tkeep_width_c : integer := 64/8;
constant axis_rx_tuser_width_c : integer := 22;
constant wb_address_width_c : integer := 64;
constant wb_data_width_c : integer := 32
);
--port ();
end p2l_decoder_bench;
architecture Behavioral of p2l_decoder_bench is
signal clk_tbs : STD_LOGIC;
signal rst_tbs : STD_LOGIC;
-- Slave AXI-Stream
signal s_axis_rx_tdata_tbs : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tkeep_tbs : STD_LOGIC_VECTOR (axis_rx_tkeep_width_c - 1 downto 0);
signal s_axis_rx_tlast_tbs : STD_LOGIC;
signal s_axis_rx_ready_s : STD_LOGIC;
signal s_axis_rx_tuser_tbs : STD_LOGIC_VECTOR (axis_rx_tuser_width_c - 1 downto 0);
signal s_axis_rx_tvalid_tbs : STD_LOGIC;
-- To the wishbone master
signal pd_wbm_address_s : STD_LOGIC_VECTOR(63 downto 0);
signal pd_wbm_data_s : STD_LOGIC_VECTOR(31 downto 0);
signal pd_wbm_valid_s : std_logic;
signal wbm_pd_ready_tbs : std_logic;
signal pd_op_s : STD_LOGIC_VECTOR(2 downto 0);
signal pd_header_type_s : STD_LOGIC;
signal pd_payload_length_s : STD_LOGIC_VECTOR(9 downto 0);
-- L2P DMA
signal pd_pdm_data_valid_s : std_logic; -- Indicates Data is valid
signal pd_pdm_data_last_s : std_logic; -- Indicates end of the packet
signal pd_pdm_data_s : std_logic_vector(63 downto 0); -- Data
signal pd_pdm_keep_s : std_logic_vector(7 downto 0);
type tlp_type_t is (MRd,MRdLk,MWr,IORd,IOWr,CfgRd0,CfgWr0,CfgRd1,CfgWr1,TCfgRd,TCfgWr,Msg,MsgD,Cpl,CplD,CplLk,CplDLk,LPrfx,unknown);
type header_t is (H3DW,H4DW);
signal byte_swap_c : STD_LOGIC_VECTOR (1 downto 0);
type bool_t is (false,true);
-- Test bench specific signals
signal step : integer;
procedure axis_data_p (
tlp_type_i : in tlp_type_t;
header_type_i : in header_t;
address_i : in STD_LOGIC_VECTOR(wb_address_width_c-1 downto 0);
data_i : in STD_LOGIC_VECTOR(64-1 downto 0);
length_i : in STD_LOGIC_VECTOR(10-1 downto 0);
rx_data_0 : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
rx_data_1 : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
rx_data_2 : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0)
) is
begin
rx_data_0(63 downto 48) := X"0000"; --H1 Requester ID
rx_data_0(47 downto 40) := X"00"; --H1 Tag
if length_i = "00" & X"01" then
rx_data_0(39 downto 32) := X"0f"; --H1 Tag and Last DW BE and 1st DW BE see ch. 2.2.5 pcie spec
else
rx_data_0(39 downto 32) := X"ff";
end if;
case tlp_type_i is
when MRd =>
if header_type_i = H3DW then
rx_data_0(31 downto 29) := "000"; -- H0 FMT
else
rx_data_0(31 downto 29) := "001"; -- H0 FMT
end if;
rx_data_0(28 downto 24) := "00000"; -- H0 type Memory request
when MWr =>
if header_type_i = H3DW then
rx_data_0(31 downto 29) := "010"; -- H0 FMT
else
rx_data_0(31 downto 29) := "011"; -- H0 FMT
end if;
rx_data_0(28 downto 24) := "00000"; -- H0 type Memory request
when CplD =>
rx_data_0(31 downto 29) := "010"; -- H0 FMT
rx_data_0(28 downto 24) := "01010"; -- H0 type Memory request
when others =>
end case;
rx_data_0(23 downto 16) := X"00"; -- some unused bits
rx_data_0(15 downto 10) := "000000"; --H0 unused bits
rx_data_0(9 downto 0) := length_i; --H0 length H & length L
if header_type_i = H3DW then
rx_data_1(63 downto 32) := data_i(31 downto 0); --D0 Data
rx_data_1(31 downto 0) := address_i(31 downto 0); --H2 Adress
rx_data_2 := (others => '0');
else
rx_data_1(63 downto 32) := address_i(31 downto 0); --H3 Adress L (Last 4 bit must always pull at zero, byte to 8 byte)
rx_data_1(31 downto 0) := address_i(63 downto 32); --H2 Adress H
rx_data_2 := data_i;
end if;
end axis_data_p;
Component p2l_decoder is
Port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
-- Slave AXI-Stream
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR (64 - 1 downto 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR (64/8 - 1 downto 0);
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR (21 downto 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
-- To the wishbone master
pd_wbm_address_o : out STD_LOGIC_VECTOR(63 downto 0);
pd_wbm_data_o : out STD_LOGIC_VECTOR(31 downto 0);
pd_wbm_valid_o : out std_logic;
pd_wbm_hdr_rid_o : out std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_cid_o : out std_logic_vector(15 downto 0); -- Completer ID
pd_wbm_hdr_tag_o : out std_logic_vector(7 downto 0);
pd_wbm_target_mrd_o : out std_logic; -- Target memory read
pd_wbm_target_mwr_o : out std_logic; -- Target memory write
wbm_pd_ready_i : in std_logic;
--wbm_pd_done_i : in std_logic;
pd_op_o : out STD_LOGIC_VECTOR(2 downto 0);
pd_header_type_o : out STD_LOGIC;
pd_payload_length_o : out STD_LOGIC_VECTOR(9 downto 0);
-- L2P DMA
pd_pdm_data_valid_o : out std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_o : out std_logic_vector(1 downto 0);
pd_pdm_data_last_o : out std_logic; -- Indicates end of the packet
pd_pdm_keep_o : out std_logic_vector(7 downto 0);
pd_pdm_data_o : out std_logic_vector(63 downto 0); -- Data
--debug outputs
states_do : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
begin
byte_swap_c <= "11";
clk_p: process
begin
clk_tbs <= '1';
wait for period/2;
clk_tbs <= '0';
wait for period/2;
end process clk_p;
reset_p: process
begin
rst_tbs <= '1';
wait for period;
rst_tbs <= '0';
wait;
end process reset_p;
stimuli_p: process
variable data_0 : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
variable data_1 : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
variable data_2 : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
begin
step <= 1;
s_axis_rx_tdata_tbs <= (others => '0');
s_axis_rx_tkeep_tbs <= (others => '0');
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= (others => '0');
s_axis_rx_tvalid_tbs <= '0';
wbm_pd_ready_tbs <= '1';
wait for period;
wait for period;
step <= 2;
axis_data_p (MWr,H3DW,X"0000000000000000",X"00000000" & X"BEEF5A5A","00" & X"01",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"e4004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 3;
s_axis_rx_tdata_tbs <= data_1;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '1';
s_axis_rx_tuser_tbs <= "10" & X"e4004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 4;
s_axis_rx_tdata_tbs <= X"0000000000000001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wbm_pd_ready_tbs <= '0';
wait for period;
step <= 5;
s_axis_rx_tdata_tbs <= X"0000000000000001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
wait for period;
wbm_pd_ready_tbs <= '1';
wait for period;
step <= 6;
axis_data_p (MRd,H3DW,X"0000000000000000",X"00000000" & X"5A5AEFBE","00" & X"00",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "00" & X"e4004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 7;
s_axis_rx_tdata_tbs <= data_1;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '1';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
s_axis_rx_tdata_tbs <= X"0000000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
wait for period;
step <= 8;
wait for period;
wait for period;
wait for period;
step <= 9;
wbm_pd_ready_tbs <= '0';
wait for period;
step <= 10;
axis_data_p (MWr,H3DW,X"0000000000000000",X"00000000" & X"BEEF5A5A","00" & X"01",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"e4004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
wait for period;
wbm_pd_ready_tbs <= '1';
wait for period;
step <= 11;
s_axis_rx_tdata_tbs <= data_1;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '1';
s_axis_rx_tvalid_tbs <= '1';
s_axis_rx_tuser_tbs <= "10" & X"e4004";
wait for period;
step <= 12;
s_axis_rx_tdata_tbs <= X"0000000000000001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wbm_pd_ready_tbs <= '0';
wait for period;
step <= 13;
s_axis_rx_tdata_tbs <= X"0000000000000001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
wait for period;
wbm_pd_ready_tbs <= '1';
wait for period;
wait for period;
step <= 17;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"04",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 18;
s_axis_rx_tdata_tbs <= data_1;
wait for period;
s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
wait for period;
s_axis_rx_tdata_tbs <= X"0400CACA" & X"0300EFBE";
s_axis_rx_tkeep_tbs <= X"0F";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 19;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"02",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 20;
s_axis_rx_tdata_tbs <= data_1;
--wait for period;
--s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
wait for period;
s_axis_rx_tdata_tbs <= X"0400CACA" & X"0300EFBE";
s_axis_rx_tkeep_tbs <= X"0F";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 30;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"01",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 31;
s_axis_rx_tdata_tbs <= data_1;
--wait for period;
--s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 40;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"05",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 41;
s_axis_rx_tdata_tbs <= data_1;
wait for period;
s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
wait for period;
s_axis_rx_tdata_tbs <= X"0400EFBE" & X"0300EFBE";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 42;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
step <= 60;
s_axis_rx_tdata_tbs <= X"000000204a000002";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 61;
s_axis_rx_tdata_tbs <= X"701b000001000038";
wait for period;
step <= 62;
s_axis_rx_tdata_tbs <= X"2b55629a0060bfbd";
s_axis_rx_tkeep_tbs <= X"0F";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 63;
s_axis_rx_tdata_tbs <= X"0000000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tvalid_tbs <= '0';
wait for 2*period;
step <= 64;
s_axis_rx_tdata_tbs <= X"000000184a000006";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 65;
s_axis_rx_tdata_tbs <= X"0300000001000040";
wait for period;
step <= 66;
s_axis_rx_tdata_tbs <= X"00000000d0040000";
wait for period;
step <= 67;
s_axis_rx_tdata_tbs <= X"0200000000000000";
wait for period;
step <= 68;
s_axis_rx_tdata_tbs <= X"0d1e7fc900000000";
s_axis_rx_tkeep_tbs <= X"0F";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 0;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
step <= 10;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"01",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 11;
s_axis_rx_tdata_tbs <= data_1;
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 0;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
step <= 20;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"02",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 21;
s_axis_rx_tdata_tbs <= data_1;
--s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 22;
s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
s_axis_rx_tkeep_tbs <= X"0F";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 0;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
step <= 30;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"03",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 31;
s_axis_rx_tdata_tbs <= data_1;
--s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 32;
s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 0;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
step <= 40;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"04",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 41;
s_axis_rx_tdata_tbs <= data_1;
wait for period;
s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
wait for period;
s_axis_rx_tdata_tbs <= X"0400EFBE" & X"0300EFBE";
s_axis_rx_tkeep_tbs <= X"0F";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 0;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
step <= 50;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"05",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 51;
s_axis_rx_tdata_tbs <= data_1;
wait for period;
s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
wait for period;
s_axis_rx_tdata_tbs <= X"0400EFBE" & X"0300EFBE";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 60;
axis_data_p (CplD,H3DW,X"0000000000000010",X"5A5AEFBE" & X"0000EFBE","00" & X"06",data_0,data_1,data_2);
s_axis_rx_tdata_tbs <= data_0;
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60004";
s_axis_rx_tvalid_tbs <= '1';
wait for period;
step <= 61;
s_axis_rx_tdata_tbs <= data_1;
wait for period;
s_axis_rx_tdata_tbs <= X"0200EFBE" & X"0100EFBE";
wait for period;
s_axis_rx_tdata_tbs <= X"0400EFBE" & X"0300EFBE";
wait for period;
s_axis_rx_tdata_tbs <= X"0600EFBE" & X"0500EFBE";
s_axis_rx_tkeep_tbs <= X"0F";
s_axis_rx_tlast_tbs <= '1';
wait for period;
step <= 0;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait for period;
step <= 100;
s_axis_rx_tdata_tbs <= X"000F000000A00001";
s_axis_rx_tkeep_tbs <= X"FF";
s_axis_rx_tlast_tbs <= '0';
s_axis_rx_tuser_tbs <= "11" & X"60000";
s_axis_rx_tvalid_tbs <= '0';
wait;
end process stimuli_p;
dut1:p2l_decoder
port map(
clk_i => clk_tbs,
rst_i => rst_tbs,
-- Slave AXI-Stream
s_axis_rx_tdata_i => s_axis_rx_tdata_tbs,
s_axis_rx_tkeep_i => s_axis_rx_tkeep_tbs,
s_axis_rx_tlast_i => s_axis_rx_tlast_tbs,
s_axis_rx_tready_o => s_axis_rx_ready_s,
s_axis_rx_tuser_i => s_axis_rx_tuser_tbs,
s_axis_rx_tvalid_i => s_axis_rx_tvalid_tbs,
-- To the wishbone master
pd_wbm_address_o => pd_wbm_address_s,
pd_wbm_data_o => pd_wbm_data_s,
pd_pdm_keep_o => pd_pdm_keep_s,
pd_wbm_valid_o => pd_wbm_valid_s,
wbm_pd_ready_i => wbm_pd_ready_tbs,
pd_op_o => pd_op_s,
pd_header_type_o => pd_header_type_s,
pd_payload_length_o => pd_payload_length_s,
-- L2P DMA
pd_pdm_data_valid_o => pd_pdm_data_valid_s,
pd_pdm_data_last_o => pd_pdm_data_last_s,
pd_pdm_data_o => pd_pdm_data_s
);
end Behavioral;
|
gpl-3.0
|
280b6800e1a5fe17475a3b29d67ae91a
| 0.538101 | 2.745769 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Utilities/SimpleDecimator.vhd
| 1 | 1,152 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity SimpleDecimator is
generic (
wordLength : natural := 8;
divider : natural := 2
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
reset : in std_logic;
clk : in std_logic
);
end entity ; -- SimpleDecimator
architecture arch of SimpleDecimator is
type reg_type is record
vector : std_logic_vector(wordLength-1 downto 0);
end record;
signal r, rin : reg_type;
signal decimatedClk : std_logic;
begin
output <= r.vector;
-- Create a decimated (slow) clock via ClockDivider:
decimator : entity work.ClockDivider
generic map(
divider => divider
)
port map(
reset => reset,
clk => clk,
clkOut => decimatedClk
);
-- Let the clocked process trigger on the slow clock.
clk_proc : process( decimatedClk )
begin
if(rising_edge(decimatedClk)) then
r <= rin;
end if;
end process ; -- clk_proc
comb_proc : process( r, rin, input )
variable v : reg_type;
begin
v := r;
v.vector := input;
rin <= v;
end process ; -- comb_proc
end architecture ; -- arch
|
mit
|
8ecfc2b0d092bcf678f3165180e54859
| 0.673611 | 3.121951 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/DACInterface.vhdl
| 1 | 2,373 |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity dac_interface is
generic(
DATA_WIDTH : natural := 12
);
port(
reset : in std_logic;
clk : in std_logic;
data_input : in std_logic_vector(DATA_WIDTH-1 downto 0);
write_data : in std_logic;
serial_data : out std_logic; -- SDI
latch_data : out std_logic; -- LDAC'
hardware_shutdown : out std_logic; -- SHDN'
finished : out std_logic;
chip_select : out std_logic
);
end entity;
architecture behavioural of dac_interface is
type state_t is (sleep, config, data);
type reg_t is record
state : state_t;
counter : natural range 0 to DATA_WIDTH;
data_input : std_logic_vector(DATA_WIDTH-1 downto 0);
serial_data : std_logic;
chip_select : std_logic;
finished : std_logic;
end record;
signal r, rin : reg_t;
begin
clocked_proc: process(reset, clk)
begin
if reset = '1' then
r.state <= sleep;
r.counter <= 0;
r.chip_select <= '1';
r.serial_data <= '0';
r.finished <= '0';
elsif falling_edge(clk) then
r <= rin;
end if;
end process;
combinatoric_proc: process(r, rin, write_data, data_input)
variable v : reg_t;
begin
v := r;
case r.state is
when sleep =>
v.chip_select := '1';
if(write_data='1') then
v.data_input := data_input;
v.counter:=0;
v.state:=config;
v.finished := '0';
end if;
when config =>
v.counter := r.counter +1;
if(r.counter=0) then
-- Enable the chip select.
v.chip_select:='0';
v.serial_data:='0'; -- Write to channel A
-- r.counter = 1 is don't care.
elsif(r.counter=2)then
v.serial_data:='0'; -- Select 2x gain.
elsif(r.counter=3)then
v.serial_data:='1'; -- Output power-down control bit.
v.counter:=0;
v.state:=data;
end if;
when data =>
v.counter := r.counter +1;
v.serial_data := r.data_input(DATA_WIDTH-1-r.counter);
if r.counter=11 then
v.state:= sleep;
v.finished := '1';
end if ;
when others =>
v.state := sleep;
v.counter := 0;
v.chip_select := '1';
v.serial_data := '0';
v.data_input := (others => '0');
v.finished := '0';
end case;
rin <= v;
end process;
finished <= r.finished;
serial_data <= r.serial_data;
chip_select <= r.chip_select;
latch_data <='0';
hardware_shutdown <= '1';
end architecture;
|
mit
|
8ed2d77dff24aa2042ede9bde758a4d7
| 0.598399 | 2.756098 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
stat_compress.vhd
| 1 | 1,543 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity stat_compress is
port (Clk : in std_logic;
Value : in std_logic_vector (63 downto 0);
KickIn : in std_logic;
Statistic : out std_logic_vector (8 downto 0);
KickOut : out std_logic);
end stat_compress;
architecture Behavioral of stat_compress is
signal compressLogic : std_logic_vector (8 downto 0);
begin
compressLogic <= b"1" & X"FF" when Value(63 downto 24) /= X"00000" else
b"1" & Value(23 downto 16) when Value(23 downto 16) /= X"00" else
b"0" & Value(15 downto 8);
Statistic <= compressLogic when rising_edge(Clk);
KickOut <= KickIn when rising_edge(Clk);
end Behavioral;
|
gpl-3.0
|
5245abf6e0a105faf365e23fc251881a
| 0.666883 | 3.745146 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/p2l_decoder.vhd
| 1 | 15,027 |
library IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
entity p2l_decoder is
Port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
-- From Slave AXI-Stream
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR (64 - 1 downto 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR (64/8 - 1 downto 0);
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR (21 downto 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
-- To the wishbone master
pd_wbm_address_o : out STD_LOGIC_VECTOR(63 downto 0);
pd_wbm_data_o : out STD_LOGIC_VECTOR(31 downto 0);
pd_wbm_valid_o : out std_logic;
pd_wbm_hdr_rid_o : out std_logic_vector(15 downto 0); -- Requester ID
pd_wbm_hdr_tag_o : out std_logic_vector(7 downto 0);
pd_wbm_target_mrd_o : out std_logic; -- Target memory read
pd_wbm_target_mwr_o : out std_logic; -- Target memory write
wbm_pd_ready_i : in std_logic;
-- to L2P DMA
pd_pdm_data_valid_o : out std_logic; -- Indicates Data is valid
pd_pdm_data_valid_w_o : out std_logic_vector(1 downto 0);
pd_pdm_data_last_o : out std_logic; -- Indicates end of the packet
pd_pdm_keep_o : out std_logic_vector(7 downto 0);
pd_pdm_data_o : out std_logic_vector(63 downto 0); -- Data
--debug outputs
states_do : out STD_LOGIC_VECTOR(3 downto 0);
pd_op_o : out STD_LOGIC_VECTOR(2 downto 0);
pd_header_type_o : out STD_LOGIC;
pd_payload_length_o : out STD_LOGIC_VECTOR(9 downto 0)
);
end p2l_decoder;
architecture Behavioral of p2l_decoder is
constant axis_data_width_c : integer := 64;
constant address_mask_c : STD_LOGIC_VECTOR(64-1 downto 0) := X"00000000" & X"000FFFFF"; -- depends on pcie memory size
constant fmt_h3dw_nodata_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "000";
constant fmt_h3dw_data_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "001";
constant fmt_h4dw_nodata_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "010";
constant fmt_h4dw_data_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "011";
constant fmt_tlp_prefix_c : STD_LOGIC_VECTOR (3 - 1 downto 0):= "100";
constant tlp_type_Mr_c : STD_LOGIC_VECTOR (5 - 1 downto 0):= "00000";
constant tlp_type_Cpl_c : STD_LOGIC_VECTOR (5 - 1 downto 0):= "01010";
type state_t is (idle,hd0_rx, hd1_rx, lastdata_rx, data_rx);
signal state_s : state_t;
signal previous_state_s : state_t;
signal payload_length_s : STD_LOGIC_VECTOR(9 downto 0);
signal bar_hit_s : STD_LOGIC_VECTOR(6 downto 0);
type tlp_type_t is (MRd,MRdLk,MWr,IORd,IOWr,CfgRd0,CfgWr0,CfgRd1,CfgWr1,TCfgRd,TCfgWr,Msg,MsgD,Cpl,CplD,CplLk,CplDLk,LPrfx,unknown);
signal tlp_type_s : tlp_type_t;
type header_t is (H3DW,H4DW);
signal header_type_s : header_t;
type bool_t is (false,true);
signal payload_s : bool_t;
signal tlp_prefix : bool_t;
signal address_s : STD_LOGIC_VECTOR(64-1 downto 0);
signal data_s : STD_LOGIC_VECTOR(32-1 downto 0);
signal s_axis_rx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal s_axis_rx_tkeep_1_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal s_axis_rx_tuser_s : STD_LOGIC_VECTOR (21 downto 0);
signal s_axis_rx_tvalid_s : STD_LOGIC;
signal s_axis_rx_tlast_s : STD_LOGIC;
signal s_axis_rx_tready_s : STD_LOGIC;
signal s_axis_rx_tlast_1_s : STD_LOGIC;
signal s_axis_rx_tdata_0_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tdata_1_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal pd_pdm_keep_0_s : std_logic_vector(7 downto 0);
signal pd_pdm_keep_1_s : std_logic_vector(7 downto 0);
signal pd_op_s : STD_LOGIC_VECTOR(2 downto 0);
signal pd_wbm_hdr_rid_s : std_logic_vector(15 downto 0); -- Requester ID
--signal pd_wbm_hdr_cid_s : std_logic_vector(15 downto 0); -- Completer ID
signal pd_wbm_hdr_tag_s : std_logic_vector(7 downto 0);
signal pd_wbm_target_mrd_s : std_logic; -- Target memory read
signal pd_wbm_target_mwr_s : std_logic;
signal data_cnt_s : unsigned(9 downto 0);
signal byte_swap_c : STD_LOGIC_VECTOR (1 downto 0);
begin
byte_swap_c <= "11";
state_p:process(rst_i,clk_i)
begin
if rst_i = '1' then
--if s_axis_rx_tvalid_i = '1' then
state_s <= idle;
--end if;
elsif clk_i = '1' and clk_i'event then
case state_s is
when idle =>
state_s <= hd0_rx;
when hd0_rx =>
if s_axis_rx_tvalid_s = '1' then
state_s <= hd1_rx; --
end if;
when hd1_rx =>
--if s_axis_rx_tvalid_s = '0' then
--state_s <= hd1_rx;
if s_axis_rx_tvalid_s = '1' then
if s_axis_rx_tvalid_i = '1' and s_axis_rx_tlast_i = '1' then
state_s <= lastdata_rx;
elsif s_axis_rx_tlast_s = '0' then
state_s <= data_rx; -- TODO: MORE DATA
elsif s_axis_rx_tlast_s = '1' then
--if (tlp_type_s = MRd or tlp_type_s = MWr) then
--state_s <= wait_done;
--else
state_s <= hd0_rx;
--end if;
end if;
end if;
when lastdata_rx =>
state_s <= hd0_rx;
when data_rx =>
if s_axis_rx_tlast_i = '1' then
state_s <= lastdata_rx;
end if;
end case;
end if;
end process state_p;
delay_p: process(clk_i,rst_i)
begin
if rst_i = '1' then
s_axis_rx_tdata_s <= (others => '0');
s_axis_rx_tkeep_s <= (others => '0');
s_axis_rx_tuser_s <= (others => '0');
s_axis_rx_tvalid_s <= '0';
s_axis_rx_tlast_s <= '0';
previous_state_s <= hd1_rx;
elsif clk_i = '1' and clk_i'event then
s_axis_rx_tdata_s <= s_axis_rx_tdata_i;
s_axis_rx_tkeep_s <= s_axis_rx_tkeep_i;
s_axis_rx_tkeep_1_s <= s_axis_rx_tkeep_s;
s_axis_rx_tuser_s <= s_axis_rx_tuser_i;
s_axis_rx_tvalid_s <= s_axis_rx_tvalid_i;
s_axis_rx_tlast_s <= s_axis_rx_tlast_i;
s_axis_rx_tlast_1_s <= s_axis_rx_tlast_s;
previous_state_s <= state_s;
end if;
end process delay_p;
data_counter_p : process(clk_i,rst_i)
begin
if rst_i = '1' then
data_cnt_s <= (others => '0');
elsif clk_i = '1' and clk_i'event then
case state_s is
when hd0_rx =>
data_cnt_s <= unsigned(s_axis_rx_tdata_s(9 downto 0));
when hd1_rx =>
data_cnt_s <= data_cnt_s - 1;
when data_rx =>
if s_axis_rx_tvalid_s = '1' then
--if s_axis_rx_tkeep_s = X"0F" then
--data_cnt_s <= data_cnt_s - 1;
--elsif s_axis_rx_tkeep_s = X"FF" then
data_cnt_s <= data_cnt_s - 2;
--end if;
end if;
when lastdata_rx =>
if s_axis_rx_tvalid_s = '1' then
if s_axis_rx_tkeep_s = X"0F" then
data_cnt_s <= data_cnt_s - 1;
elsif s_axis_rx_tkeep_s = X"FF" then
data_cnt_s <= data_cnt_s - 2;
end if;
end if;
when others =>
end case;
end if;
end process data_counter_p;
reg_p: process(rst_i,clk_i)
begin
if rst_i = '1' then
address_s <= (others => '0');
tlp_type_s <= unknown;
header_type_s <= H4DW;
data_s <= (others => '0');
pd_wbm_hdr_rid_s <= (others => '0');
pd_wbm_hdr_tag_s <= (others => '0');
pd_wbm_target_mrd_s <= '0';
pd_wbm_target_mwr_s <= '0';
elsif clk_i = '1' and clk_i'event then
case state_s is
when idle =>
address_s <= (others => '0');
tlp_type_s <= unknown;
header_type_s <= H4DW;
data_s <= (others => '0');
pd_wbm_hdr_rid_s <= (others => '0');
pd_wbm_hdr_tag_s <= (others => '0');
pd_wbm_target_mrd_s <= '0';
pd_wbm_target_mwr_s <= '0';
when hd0_rx =>
bar_hit_s <= s_axis_rx_tuser_s(8 downto 2);
payload_length_s <= s_axis_rx_tdata_s(9 downto 0);
pd_wbm_hdr_rid_s <= s_axis_rx_tdata_s(63 downto 48);
pd_wbm_target_mrd_s <= '0';
pd_wbm_target_mwr_s <= '0';
case s_axis_rx_tdata_s(31 downto 24) is
when "00000000" =>
tlp_type_s <= MRd;
header_type_s <= H3DW;
pd_wbm_target_mrd_s <= '1';
when "00100000" =>
tlp_type_s <= MRd;
header_type_s <= H4DW;
when "00000001" =>
tlp_type_s <= MRdLk;
header_type_s <= H3DW;
when "00100001" =>
tlp_type_s <= MRdLk;
header_type_s <= H4DW;
when "01000000" =>
tlp_type_s <= MWr;
header_type_s <= H3DW;
pd_wbm_target_mwr_s <= '1';
when "01100000" =>
tlp_type_s <= MWr;
header_type_s <= H4DW;
when "00000010" =>
tlp_type_s <= IORd;
header_type_s <= H3DW;
when "01000010" =>
tlp_type_s <= IOWr;
header_type_s <= H3DW;
when "00000100" =>
tlp_type_s <= CfgRd0;
header_type_s <= H3DW;
when "01000100" =>
tlp_type_s <= CfgWr0;
header_type_s <= H3DW;
when "00000101" =>
tlp_type_s <= CfgRd1;
header_type_s <= H3DW;
when "01000101" =>
tlp_type_s <= CfgWr1;
header_type_s <= H3DW;
when "00011011" =>
tlp_type_s <= TCfgRd;
header_type_s <= H3DW;
when "01011011" =>
tlp_type_s <= TCfgWr;
header_type_s <= H3DW;
when "00001010" =>
tlp_type_s <= Cpl;
header_type_s <= H3DW;
when "01001010" =>
tlp_type_s <= CplD;
header_type_s <= H3DW;
when "00001011" =>
tlp_type_s <= CplLk;
header_type_s <= H3DW;
when "01001011" =>
tlp_type_s <= CplDLk;
header_type_s <= H3DW;
when others =>
if s_axis_rx_tdata_s(31 downto 27) = "00110" then
tlp_type_s <= Msg;
header_type_s <= H4DW;
elsif s_axis_rx_tdata_s(31 downto 27) = "01110" then
tlp_type_s <= MsgD;
header_type_s <= H4DW;
elsif s_axis_rx_tdata_s(31 downto 28) = "1000" then
tlp_type_s <= LPrfx;
header_type_s <= H3DW;
else
tlp_type_s <= unknown;
header_type_s <= H4DW;
end if;
end case;
when hd1_rx =>
if header_type_s = H3DW then -- d0h2_rx
--wb_dat_o_s <= X"00000000" & s_axis_rx_tdata_s(63 downto 32); -- 64bit
address_s <= X"00000000" & s_axis_rx_tdata_s(31 downto 0) and address_mask_c; -- see 2.2.4.1. in pcie spec
address_s(1 downto 0) <= "00";
data_s <= s_axis_rx_tdata_s(63 downto 32);
else -- H4DW h3h2_rx
address_s(63 downto 32) <= s_axis_rx_tdata_s(31 downto 0) and address_mask_c(63 downto 32);
address_s(31 downto 0) <= s_axis_rx_tdata_s(63 downto 36) & "0000" and address_mask_c(31 downto 0);
end if;
when data_rx =>
when lastdata_rx =>
when others =>
end case;
end if;
end process reg_p;
pd_header_type_o <= '1' when header_type_s = H4DW else '0';
pd_wbm_hdr_rid_o <= pd_wbm_hdr_rid_s;
pd_wbm_hdr_tag_o <= pd_wbm_hdr_tag_s;
pd_wbm_target_mrd_o <= pd_wbm_target_mrd_s;
pd_wbm_target_mwr_o <= pd_wbm_target_mwr_s;
p2l_data_delay_p : process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
--if (s_axis_rx_tvalid_i = '1') then
s_axis_rx_tdata_0_s <= s_axis_rx_tdata_i;
s_axis_rx_tdata_1_s <= s_axis_rx_tdata_0_s;
pd_pdm_keep_0_s <= s_axis_rx_tkeep_i;
pd_pdm_keep_1_s <= pd_pdm_keep_0_s;
--end if;
end if;
end process p2l_data_delay_p;
pd_pdm_data_o <=
f_byte_swap(true,data_s, byte_swap_c) & f_byte_swap(true,data_s, byte_swap_c) when payload_length_s = "0000000001" else
f_byte_swap(true, s_axis_rx_tdata_0_s(31 downto 0), byte_swap_c) & f_byte_swap(true, s_axis_rx_tdata_1_s(63 downto 32), byte_swap_c);
pd_pdm_data_valid_o <= s_axis_rx_tvalid_s when (state_s = data_rx or state_s = lastdata_rx) and pd_op_s = "011"
else '0';
pd_pdm_data_last_o <=
s_axis_rx_tlast_s when ( state_s = lastdata_rx and s_axis_rx_tkeep_i = X"0F" and pd_op_s = "011") else
'1' when s_axis_rx_tkeep_1_s = X"FF" and s_axis_rx_tlast_1_s = '1'and pd_op_s = "011" else
'0';
pd_pdm_data_valid_w_o(1) <=
s_axis_rx_tvalid_s when (state_s = data_rx or state_s = lastdata_rx) and pd_op_s = "011" and pd_pdm_keep_0_s(3 downto 0) = X"F" else
'0';
pd_pdm_data_valid_w_o(0) <=
s_axis_rx_tvalid_s when (state_s = data_rx or state_s = lastdata_rx) and pd_op_s = "011" and pd_pdm_keep_1_s(7 downto 4) = X"F" else
'1' when pd_op_s = "011" and s_axis_rx_tlast_s = '1' and state_s = hd0_rx else
'1' when s_axis_rx_tkeep_1_s = X"FF" and s_axis_rx_tlast_1_s = '1'and pd_op_s = "011" else
'0';
pd_pdm_keep_o <= pd_pdm_keep_0_s(3 downto 0) & pd_pdm_keep_1_s(7 downto 4);
pd_wbm_valid_o <= '1' when previous_state_s = hd1_rx and s_axis_rx_tlast_1_s = '1' and (pd_op_s = "001" or pd_op_s = "010") else '0';
s_axis_rx_tready_s <= wbm_pd_ready_i;
s_axis_rx_tready_o <= s_axis_rx_tready_s;
pd_payload_length_o <= payload_length_s;
pd_wbm_address_o <= address_s;
pd_wbm_data_o <= f_byte_swap(true,data_s, byte_swap_c);
pd_op_o <= pd_op_s;
debug_output_p:process (state_s,header_type_s,tlp_type_s)
begin
case tlp_type_s is
when MRd =>
pd_op_s <= "001";
when MWr =>
pd_op_s <= "010";
when CplD =>
pd_op_s <= "011";
when others =>
pd_op_s <= "000";
end case;
case state_s is
when idle =>
states_do <= "0000";
when hd0_rx =>
states_do <= "0001";
when hd1_rx =>
states_do <= "0010";
when data_rx =>
states_do <= "0011";
when lastdata_rx =>
states_do <= "0100";
end case;
end process debug_output_p;
end;
|
gpl-3.0
|
55502be2fa7dbabf5e44a22a5336ce47
| 0.515073 | 2.823032 | false | false | false | false |
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/uart/comp/uart_parity.vhd
| 1 | 2,884 |
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_PARITY is
Generic (
DATA_WIDTH : integer := 8;
PARITY_TYPE : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
PARITY_OUT : out std_logic
);
end UART_PARITY;
architecture FULL of UART_PARITY is
begin
-- -------------------------------------------------------------------------
-- PARITY BIT GENERATOR
-- -------------------------------------------------------------------------
even_parity_g : if (PARITY_TYPE = "even") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '0';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
odd_parity_g : if (PARITY_TYPE = "odd") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '1';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
mark_parity_g : if (PARITY_TYPE = "mark") generate
PARITY_OUT <= '1';
end generate;
space_parity_g : if (PARITY_TYPE = "space") generate
PARITY_OUT <= '0';
end generate;
end FULL;
|
mit
|
6ab55bbe60f7ddcab529b40a915a5a6b
| 0.581831 | 4.356495 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/gn4124-core/spartan6/serdes_1_to_n_data_s2_se.vhd
| 2 | 22,872 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_s2_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with se inputs
-- Takes in 1 bit of se data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_1_to_n_data_s2_se is
generic (
USE_PD : boolean := false; -- Parameter to set generation of phase detector logic
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic; -- Set generation of phase detector logic
datain : in std_logic_vector(D-1 downto 0); -- Input from se receiver pin
rxioclk : in std_logic; -- IO Clock network
rxserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset line
gclk : in std_logic; -- Global clock
bitslip : in std_logic; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0); -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0); -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_s2_se;
architecture arch_serdes_1_to_n_data_s2_se of serdes_1_to_n_data_s2_se is
signal ddly_m : std_logic_vector(D-1 downto 0); -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0); -- Slave output from IODELAY1
signal cascade : std_logic_vector(D-1 downto 0);
signal busys : std_logic_vector(D-1 downto 0);
signal rx_data_in : std_logic_vector(D-1 downto 0);
signal rx_data_in_fix : std_logic_vector(D-1 downto 0);
signal state : integer range 0 to 8;
signal busyd : std_logic_vector(D-1 downto 0);
signal cal_data_sint : std_logic;
signal ce_data_inta : std_logic;
signal busy_data : std_logic_vector(D-1 downto 0);
signal busy_data_d : std_logic;
signal counter : std_logic_vector(8 downto 0);
signal enable : std_logic;
signal pd_edge : std_logic_vector(D-1 downto 0);
signal cal_data_slave : std_logic;
signal cal_data_master : std_logic;
signal valid_data : std_logic_vector(D-1 downto 0);
signal valid_data_d : std_logic;
signal rst_data : std_logic;
signal mdataout : std_logic_vector((8*D)-1 downto 0);
signal pdcounter : std_logic_vector(4 downto 0);
signal inc_data : std_logic;
signal ce_data : std_logic_vector(D-1 downto 0);
signal inc_data_int : std_logic;
signal incdec_data : std_logic_vector(D-1 downto 0);
signal incdec_data_d : std_logic;
signal flag : std_logic;
signal mux : std_logic_vector(D-1 downto 0);
signal incdec_data_or : std_logic_vector(D downto 0);
signal valid_data_or : std_logic_vector(D downto 0);
signal busy_data_or : std_logic_vector(D downto 0);
signal incdec_data_im : std_logic_vector(D-1 downto 0);
signal valid_data_im : std_logic_vector(D-1 downto 0);
signal all_ce : std_logic_vector(D-1 downto 0);
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0'); -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
busy_data <= busys;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d;
cal_data_slave <= cal_data_sint;
process (gclk, reset)
begin
if reset = '1' then
state <= 0;
cal_data_master <= '0';
cal_data_sint <= '0';
counter <= (others => '0');
enable <= '0';
counter <= (others => '0');
mux <= (0 => '1', others => '0');
elsif gclk'event and gclk = '1' then
counter <= counter + 1;
if counter(8) = '1' then
counter <= "000000000";
end if;
if counter(5) = '1' then
enable <= '1';
end if;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0';
cal_data_sint <= '0';
rst_data <= '0';
if busy_data_d = '0' then
state <= 1;
end if;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1';
cal_data_sint <= '1';
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2;
end if;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0';
cal_data_sint <= '0';
if busy_data_d = '0' then
rst_data <= '1';
state <= 3;
end if;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0';
if busy_data_d = '0' then
state <= 4;
end if;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5;
end if;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1';
state <= 6;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1);
end if;
end if;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0';
state <= 7;
end if;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0';
if busy_data_d = '0' then
state <= 4;
end if;
end if;
end if;
end process;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000";
ce_data_inta <= '0';
flag <= '0';
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D);
if use_phase_detector = '1' then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D);
valid_data_d <= valid_data_or(D);
if ce_data_inta = '1' then
ce_data <= mux;
else
ce_data <= (others => '0');
end if;
if state = 7 then
flag <= '0';
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000";
ce_data_inta <= '0';
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1';
inc_data_int <= '1';
pdcounter <= "10000";
flag <= '0';
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1';
inc_data_int <= '0';
pdcounter <= "10000";
flag <= '0';
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0';
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1;
end if;
else
ce_data_inta <= '0';
end if;
else
ce_data <= all_ce;
inc_data_int <= debug_in(1);
end if;
end if;
end process;
inc_data <= inc_data_int;
incdec_data_or(0) <= '0'; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0';
busy_data_or(0) <= '0';
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i); -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i); -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i); -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i); -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i); -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0);
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i); -- Invert signals as required
iob_clk_in : IBUF port map (
I => datain(i),
O => rx_data_in(i));
loop2 : if (USE_PD = true) generate --Two oserdes are needed
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND" , -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" , -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i) , -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
end generate;
loop3 : if (USE_PD /= true) generate -- Only one oserdes is needed
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
-- SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => rx_data_in_fix(i),--ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => '0',
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => open);
end generate;
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j);
end generate;
end generate;
end arch_serdes_1_to_n_data_s2_se;
|
gpl-3.0
|
6f1cfb5f286e7f89473dfb9ffdf79166
| 0.474598 | 4.132249 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/base_line/Router_32_bit_credit_based.vhd
| 1 | 12,068 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.math_real."ceil";
--use IEEE.math_real."log2";
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
use work.router_pack.all;
entity router_credit_based is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
NoC_size_x: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end router_credit_based;
architecture behavior of router_credit_based is
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_N(14 downto 8),
dst_addr_x => FIFO_D_out_N(7 downto 1),
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_E(14 downto 8),
dst_addr_x => FIFO_D_out_E(7 downto 1),
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_W(14 downto 8),
dst_addr_x => FIFO_D_out_W(7 downto 1),
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_S(14 downto 8),
dst_addr_x => FIFO_D_out_S(7 downto 1),
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (Rxy_rst => Rxy_rst, Cx_rst => Cx_rst)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3),
cur_addr_y => std_logic_vector(to_unsigned(current_address / NoC_size_x,7)),
cur_addr_x => std_logic_vector(to_unsigned(current_address mod NoC_size_x,7)),
dst_addr_y => FIFO_D_out_L(14 downto 8),
dst_addr_x => FIFO_D_out_L(7 downto 1),
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
gpl-3.0
|
cdb9740259844d7171340975033ae566
| 0.518147 | 2.941262 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/decode_8b10b/decode_8b10b_disp.vhd
| 1 | 7,641 |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_disp.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Block memory-based Decoder disparity logic
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY decode_8b10b;
USE decode_8b10b.decode_8b10b_pkg.ALL;
------------------------------------------------------------------------------
--Entity Declaration
------------------------------------------------------------------------------
ENTITY decode_8b10b_disp IS
GENERIC(
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_RUN_DISP : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0
);
PORT(
CE : IN STD_LOGIC := '0';
CLK : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SYM_DISP : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
USER_SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0')
);
END decode_8b10b_disp;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_disp IS
----------------------------------------------------------------------------
-- Signal Declarations
----------------------------------------------------------------------------
SIGNAL run_disp_q : STD_LOGIC := '0';
SIGNAL run_disp_d : STD_LOGIC := '0';
SIGNAL disp_in_q : STD_LOGIC := '0';
SIGNAL disp_err_i : STD_LOGIC := '0';
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
gmndi : IF (C_HAS_DISP_IN/=1 AND (C_HAS_RUN_DISP = 1 OR
C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1)) GENERATE
-- store the current running disparity in run_disp_q as a mux selector for
-- the next code's run_disp and disp_err
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_q <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSE
run_disp_q <= run_disp_d AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- mux the sym_disp bus and decode it into disp_err and run_disp
gde1 : IF (C_HAS_DISP_ERR = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (run_disp_q, SYM_DISP)
BEGIN
IF (run_disp_q = '1') THEN
disp_err_i <= SYM_DISP(3);
ELSE
disp_err_i <= SYM_DISP(1);
END IF;
END PROCESS;
END GENERATE gde1;
grd1 : IF (C_HAS_RUN_DISP = 1 OR C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1) GENERATE
PROCESS (run_disp_q, SYM_DISP)
BEGIN
IF (run_disp_q = '1') THEN
run_disp_d <= SYM_DISP(2);
ELSE
run_disp_d <= SYM_DISP(0);
END IF;
END PROCESS;
END GENERATE grd1;
END GENERATE gmndi;
gmdi: IF (C_HAS_DISP_IN = 1 AND (C_HAS_RUN_DISP = 1 OR
C_HAS_SYM_DISP = 1 OR
C_HAS_DISP_ERR = 1)) GENERATE
-- use the current disp_in as a mux selector for the next code's run_disp
-- and disp_err
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_in_q <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSE
disp_in_q <= DISP_IN AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- mux the sym_disp bus and decode it into disp_err and run_disp
gde2 : IF (C_HAS_DISP_ERR = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (disp_in_q, SYM_DISP)
BEGIN
IF (disp_in_q = '1') THEN
disp_err_i <= SYM_DISP(3);
ELSE
disp_err_i <= SYM_DISP(1);
END IF;
END PROCESS;
END GENERATE gde2;
grd2 : IF (C_HAS_RUN_DISP = 1 OR C_HAS_SYM_DISP = 1) GENERATE
PROCESS (disp_in_q, SYM_DISP)
BEGIN
IF (disp_in_q = '1') THEN
run_disp_d <= SYM_DISP(2);
ELSE
run_disp_d <= SYM_DISP(0);
END IF;
END PROCESS;
END GENERATE grd2;
END GENERATE gmdi;
-- map internal signals to outputs
DISP_ERR <= disp_err_i;
RUN_DISP <= run_disp_d;
USER_SYM_DISP(1) <= disp_err_i;
USER_SYM_DISP(0) <= run_disp_d;
END xilinx;
|
gpl-3.0
|
9dc5d767a9ca5e6e1d52c2bcc530f8dc
| 0.483575 | 4.152717 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/StructuralDecimator.vhd
| 1 | 7,117 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity StructuralDecimator is
port (
clk: in std_logic;
reset: in std_logic;
input: in std_logic_vector(15 downto 0);
output: out std_logic_vector(15 downto 0)
);
end entity ; -- StructuralDecimator
architecture arch of StructuralDecimator is
constant internalWordLength : natural := 16;
constant internalFractions : natural := 15;
constant internalSumWordLength : natural := 30;
constant internalSumFractions : natural := 19;
signal out_stage1: std_logic_vector(internalWordLength-1 downto 0);
signal out_stage2: std_logic_vector(internalWordLength-1 downto 0);
signal out_stage3: std_logic_vector(internalWordLength-1 downto 0);
signal out_stage4: std_logic_vector(15 downto 0);
signal fir1_out : std_logic_vector(internalWordLength-1 downto 0);
signal fir2_out : std_logic_vector(internalWordLength-1 downto 0);
signal fir3_out : std_logic_vector(internalWordLength-1 downto 0);
signal fir4_out : std_logic_vector(15 downto 0);
signal clk1: std_logic;
signal clk2: std_logic;
signal clk3: std_logic;
signal clk4: std_logic;
signal clk5: std_logic;
begin
clk_1: entity work.ClockDivider
generic map(
divider => 128 -- 44100*2^11/(44100*2^4)=2^7
)
port map(
reset => reset,
clk => clk,
clkOut=>clk1 --(44100*2^4)
);
clk_2: entity work.ClockDivider
generic map(
divider => 2
)
port map(
reset => reset,
clk => clk1, -- (44100*2^4)
clkOut=>clk2 -- (44100*2^3)
);
clk_3: entity work.ClockDivider
generic map(
divider => 2
)
port map(
reset => reset,
clk => clk2, --(44100*2^3)
clkOut=>clk3 --(44100*2^2)
);
clk_4: entity work.ClockDivider
generic map(
divider => 2
)
port map(
reset => reset,
clk => clk3, --(44100*2^2)
clkOut=>clk4 --(44100*2^1)
);
clk_5: entity work.ClockDivider
generic map(
divider => 2
)
port map(
reset => reset,
clk => clk4, --(44100*2^1)
clkOut=>clk5 --(44100*2^0)
);
downsampler1: entity work.VectorRegister
generic map(
wordLength => internalWordLength
)
port map(
input=> fir1_out,
output=> out_stage1,
clk=>clk2, --(44100*2^3)
reset=> reset
);
downsampler2: entity work.VectorRegister
generic map(
wordLength => internalWordLength
)
port map(
input=> fir2_out,
output=> out_stage2,
clk=>clk3, --(44100*2^2)
reset=> reset
);
downsampler3: entity work.VectorRegister
generic map(
wordLength => internalWordLength
)
port map(
input=> fir3_out,
output=> out_stage3,
clk=>clk4, --(44100*2^1)
reset=> reset
);
downsampler4: entity work.VectorRegister
generic map(
wordLength => 16
)
port map(
input=> fir4_out,
output=> out_stage4,
clk=>clk5, --(44100*2^0)
reset=> reset
);
fiter_1: entity work.FIR
generic map(
wordLength => internalWordLength,
fractionalBits => internalFractions,
coeffWordLength => 16,
coeffFractionalBits => 15,
sumWordLength => internalSumWordLength,
sumFractionalBits => internalSumFractions,
outputWordLength => internalWordLength,
outputFractionalBits => internalFractions,
order => 6,
coefficients => (
-0.03167724609375,
0.0,
0.2816619873046875,
0.4999847412109375,
0.2816619873046875,
0.0,
-0.03167724609375
)
)
port map(
input=> input,
output=> fir1_out,
clk => clk1, --(44100*2^4)
reset => reset
);
--Stage 2
fiter_2: entity work.FIR
generic map(
wordLength => internalWordLength,
fractionalBits => internalFractions,
coeffWordLength => 16,
coeffFractionalBits => 15,
sumWordLength => internalSumWordLength,
sumFractionalBits => internalSumFractions,
outputWordLength => internalWordLength,
outputFractionalBits => internalFractions,
order => 6,
coefficients => (
-0.0329742431640625,
0.0,
0.2829132080078125,
0.4999847412109375,
0.2829132080078125,
0.0,
-0.0329742431640625
)
)
port map(
input=> out_stage1,
output=> fir2_out,
clk => clk2, -- (44100*2^3)
reset => reset
);
--Stage 3
fiter_3: entity work.FIR
generic map(
wordLength => internalWordLength,
fractionalBits => internalFractions,
coeffWordLength => 16,
coeffFractionalBits => 15,
sumWordLength => internalSumWordLength,
sumFractionalBits => internalSumFractions,
outputWordLength => internalWordLength,
outputFractionalBits => internalFractions,
order => 6,
coefficients => (
-0.0388641357421875,
0.0,
0.287811279296875,
0.4999847412109375,
0.287811279296875,
0.0,
-0.0388641357421875
)
)
port map(
input=> out_stage2,
output=> fir3_out,
clk => clk3, --(44100*2^2)
reset => reset
);
--Stage 4
fiter_4: entity work.FIR
generic map(
wordLength => internalWordLength,
fractionalBits => internalFractions,
coeffWordLength => 16,
coeffFractionalBits => 15,
sumWordLength => internalSumWordLength,
sumFractionalBits => internalSumFractions,
outputWordLength => 16,
outputFractionalBits => 15,
order => 14,
coefficients => (
-0.01043701171875,
0.0,
0.03179931640625,
0.0,
-0.0837554931640625,
0.0,
0.3102569580078125,
0.4999847412109375,
0.3102569580078125,
0.0,
-0.0837554931640625,
0.0,
0.03179931640625,
0.0,
-0.01043701171875
)
)
port map(
input=> out_stage3,
output=> fir4_out,
clk => clk4,
reset => reset
);
output<= out_stage4;
end architecture ; -- arch
|
mit
|
426d9ac8bba256ee6132d937419ca0a8
| 0.515105 | 3.919053 | false | false | false | false |
Project-Bonfire/Bonfire
|
Packages/TB_Package_32_bit_credit_based.vhd
| 1 | 13,226 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
--function log2(i : integer) return integer;
function Header_gen(network_size_x, source, destination: integer ) return std_logic_vector ;
function Body_1_gen(Packet_length, packet_id: integer ) return std_logic_vector ;
function Body_gen(Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
-- gen_bit_reversed_packet needs fixing !!!
--procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
-- finish_time: in time; signal clk: in std_logic;
-- signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
-- signal port_in: out std_logic_vector);
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(network_size_x, source, destination: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
variable source_x, source_y, destination_x, destination_y: integer;
begin
-- We only need network_size_x for calculation of X and Y coordinates of a node!
source_x := source mod network_size_x;
source_y := source / network_size_x;
destination_x := destination mod network_size_x;
destination_y := destination / network_size_x;
Header_flit := Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)) &
XOR_REDUCE(Header_type & std_logic_vector(to_unsigned(source_y,7)) & std_logic_vector(to_unsigned(source_x,7)) &
std_logic_vector(to_unsigned(destination_y,7)) & std_logic_vector(to_unsigned(destination_x,7)));
return Header_flit;
end Header_gen;
function Body_1_gen(Packet_length, packet_id: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)) &
XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Packet_length, 14))& std_logic_vector(to_unsigned(packet_id, 14)));
return Body_flit;
end Body_1_gen;
function Body_gen(Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size_x, network_size_y, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive := source+1;
variable seed2 :positive := source+1;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - Packet_length-1)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 16384 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/100);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size_x*network_size_y)-1));
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0'; -- On negative edge of clk (for syncing purposes)
port_in <= Header_gen(network_size_x, source, destination_id); -- Generating the header flit of the packet (All packets have a header flit)!
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
-- The reason for -3 is that we have packet length of Packet_length, now if you exclude header and tail
-- it would be Packet_length-2 to enumerate them, you can count from 0 to Packet_length-3.
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Each packet can have no body flits or one or more than body flits.
if I = 0 then
port_in <= Body_1_gen(Packet_length, id_counter);
else
port_in <= Body_gen(integer(rand*1000.0));
end if;
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
-- Wait until next router/NI has at least enough space for one flit in its input FIFO
wait until credit_counter_in'event and credit_counter_in > 0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
-- Close the packet with a tail flit (All packets have one tail flit)!
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure get_packet(network_size_x, DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node_x, source_node_y, destination_node_x, destination_node_y, source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1';
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
source_node_y := to_integer(unsigned(port_in(28 downto 22)));
source_node_x := to_integer(unsigned(port_in(21 downto 15)));
destination_node_y := to_integer(unsigned(port_in(14 downto 8)));
destination_node_x := to_integer(unsigned(port_in(7 downto 1)));
-- We only needs network_size_x for computing the node ID (convert from (X,Y) coordinate to Node ID)!
source_node := (source_node_y * network_size_x) + source_node_x;
destination_node := (destination_node_y * network_size_x) + destination_node_x;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
if counter = 1 then
P_length := to_integer(unsigned(port_in(28 downto 15)));
packet_id := to_integer(unsigned(port_in(15 downto 1)));
end if;
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Node: " & integer'image(Node_ID) & " Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
end TB_Package;
|
gpl-3.0
|
e3c195cfcbb7b43b50ce92711506a39a
| 0.611069 | 3.758454 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/rle_enc.vhd
| 4 | 3,391 |
----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Run Length Encoder
--
-- If enabled, encode the incoming data with the following scheme:
-- The MSB (bit 31) is used as a flag for the encoding.
-- If the MSB is clear, the datum represents "regular" data
-- if set, the datum represents the number of repetitions of the previous data
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rle_enc is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (31 downto 0);
validIn : in STD_LOGIC;
enable : in STD_LOGIC;
dataOut : out STD_LOGIC_VECTOR (31 downto 0);
validOut : out STD_LOGIC);
end rle_enc;
architecture Behavioral of rle_enc is
signal old: std_logic_vector(30 downto 0);
signal dout: std_logic_vector(31 downto 0);
signal ctr: std_logic_vector(30 downto 0);
signal valid, valout: std_logic;
begin
dataOut <= dataIn when (enable = '0') else dout;
validOut <= validIn when (enable = '0') else valout;
-- shift register
process(clock, reset)
begin
if (reset = '1') then
valid <= '0';
elsif rising_edge(clock) then
if (validIn = '1') then
old <= dataIn(30 downto 0);
valid <= '1';
end if;
end if;
end process;
-- RLE encoder
process(clock, reset)
begin
if (reset = '1') then
ctr <= (others => '0');
elsif rising_edge(clock) then
valout <= '0'; --default
if (enable = '0') then
ctr <= (others => '0');
elsif (valid = '1') AND (validIn = '1') then
if (old = dataIn(30 downto 0)) then
if (ctr = 0) then -- write first datum of series
dout <= '0' & dataIn(30 downto 0); -- discard MSB, which is used for encoding a count
valout <= '1';
elsif (ctr = "111111111111111111111111111111") then -- ctr overflow
dout <= '1' & ctr; -- write count
valout <= '1';
ctr <= (others => '0'); -- reset count, so "series" starts again.
end if;
ctr <= ctr + 1;
else -- series complete, write count (or data, if series was 0 or 1 long)
valout <= '1';
ctr <= (others => '0');
if (ctr > 1) then -- TODO: try if /=0 AND /=1 is faster than >1
dout <= '1' & ctr;
else
dout <= '0' & old;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
478327544ecbbf8121d74f98ce1df2c9
| 0.588912 | 3.599788 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/bcf_bram_wbs.vhd
| 2 | 2,666 |
----------------------------------------------------------------------------------
-- Company: University of Wuppertal
-- Engineer: Timon Heim
-- E-Mail: [email protected]
--
-- Project: IBL BOC firmware
-- Module: Block RAM
-- Description: Block RAM with Wishbone Slave Interface
----------------------------------------------------------------------------------
-- Changelog:
-- 20.02.2011 - Initial Version
----------------------------------------------------------------------------------
-- TODO:
-- 20.02.2011 - Add DMA capability
----------------------------------------------------------------------------------
-- Address Map:
-- 0x020 to 0x02F
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library work;
--use work.bocpack.all;
entity bram_wbs is
generic (
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 32
);
port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_lock_i : in std_logic; -- nyi
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic
);
end bram_wbs;
architecture Behavioral of bram_wbs is
type ram_type is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM: ram_type;
signal ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal wb_ack_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_cyc_s : std_logic;
begin
ADDR <= wb_adr_i(ADDR_WIDTH-1 downto 0);
bram: process (clk, rst)
begin
if (rst ='1') then
wb_ack_o <= '0';
for i in 0 to 2**ADDR_WIDTH-1 loop
RAM(i) <= conv_std_logic_vector(i,RAM(i)'length); -- "DEAD0001BEEF0001"
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH/2) <= conv_std_logic_vector(i,RAM(i)'length/2);
RAM(i)(DATA_WIDTH-1 downto DATA_WIDTH-4*4) <= x"DEAD";
RAM(i)(DATA_WIDTH-1-DATA_WIDTH/2 downto DATA_WIDTH-4*4-DATA_WIDTH/2) <= x"BEEF";
end loop;
elsif (clk'event and clk = '1') then
if (wb_stb_i = '1' and wb_cyc_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
RAM(conv_integer(ADDR)) <= wb_dat_i;
end if;
wb_dat_o <= RAM(conv_integer(ADDR)) ;
else
wb_ack_o <= '0';
end if;
end if;
end process bram;
end Behavioral;
|
gpl-3.0
|
2b0884a85bbc1517c79132d26990dee7
| 0.520255 | 3.082081 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
counter64.vhd
| 1 | 1,477 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Binary wrap-around counter
entity counter is
generic (N_BITS : integer);
port (Clk : in std_logic;
Rst : in std_logic;
Cnt : out std_logic_vector (N_BITS - 1 downto 0));
end counter;
-- Operation:
-- Increase input from 0 to 2^N_BITS - 1 then start from zero again
architecture Behavioral of counter is
signal count : std_logic_vector (N_BITS - 1 downto 0);
begin
Cnt <= count;
inc : process (Clk)
begin
if RISING_EDGE(Clk) then
count <= count + 1;
if Rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
134b77ee569c04af6951799bf131d3d4
| 0.664861 | 3.806701 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/decode_8b10b/decode_8b10b_lut_base.vhd
| 1 | 31,504 |
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_lut_base.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : LUT-based Single-port Base Decoder for decoding 8b/10b
-- encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
LIBRARY decode_8b10b;
USE decode_8b10b.decode_8b10b_pkg.ALL;
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
ENTITY decode_8b10b_lut_base IS
GENERIC (
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
DISP_IN : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
ND : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_lut_base;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_lut_base IS
-----------------------------------------------------------------------------
-- Type Declarations
-----------------------------------------------------------------------------
TYPE disparity IS (neg, pos, zero, invalid, specneg, specpos) ;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
-- set the default decoder output for invalid codes
CONSTANT DEFAULTB5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11111" ;
CONSTANT DEFAULTB3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111" ;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
SIGNAL code_err_i : STD_LOGIC := '0';
SIGNAL symrd : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b6_disp : disparity := zero;
SIGNAL b4_disp : disparity := zero;
SIGNAL b5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := DEFAULTB5;
SIGNAL b3 : STD_LOGIC_VECTOR(7 DOWNTO 5) := DEFAULTB3;
SIGNAL k : STD_LOGIC := '0';
SIGNAL k28 : STD_LOGIC := '0';
ALIAS b6 : STD_LOGIC_VECTOR(5 DOWNTO 0) IS DIN(5 DOWNTO 0) ; --iedcba
ALIAS b4 : STD_LOGIC_VECTOR(3 DOWNTO 0) IS DIN(9 DOWNTO 6) ; --jhgf
ALIAS a : STD_LOGIC IS DIN(0) ;
ALIAS b : STD_LOGIC IS DIN(1) ;
ALIAS c : STD_LOGIC IS DIN(2) ;
ALIAS d : STD_LOGIC IS DIN(3) ;
ALIAS e : STD_LOGIC IS DIN(4) ;
ALIAS i : STD_LOGIC IS DIN(5) ;
ALIAS f : STD_LOGIC IS DIN(6) ;
ALIAS g : STD_LOGIC IS DIN(7) ;
ALIAS h : STD_LOGIC IS DIN(8) ;
ALIAS j : STD_LOGIC IS DIN(9) ;
--Signals for calculating code_error
SIGNAL p04 : STD_LOGIC := '0';
SIGNAL p13 : STD_LOGIC := '0';
SIGNAL p22 : STD_LOGIC := '0';
SIGNAL p31 : STD_LOGIC := '0';
SIGNAL p40 : STD_LOGIC := '0';
SIGNAL fghj : STD_LOGIC := '0';
SIGNAL eifgh : STD_LOGIC := '0';
SIGNAL sK28 : STD_LOGIC := '0';
SIGNAL e_i : STD_LOGIC := '0';
SIGNAL ighj : STD_LOGIC := '0';
SIGNAL i_ghj : STD_LOGIC := '0';
SIGNAL kx7 : STD_LOGIC := '0';
SIGNAL invr6 : STD_LOGIC := '0';
SIGNAL pdbr6 : STD_LOGIC := '0';
SIGNAL ndbr6 : STD_LOGIC := '0';
SIGNAL pdur6 : STD_LOGIC := '0';
SIGNAL pdbr4 : STD_LOGIC := '0';
SIGNAL ndrr4 : STD_LOGIC := '0';
SIGNAL ndur6 : STD_LOGIC := '0';
SIGNAL ndbr4 : STD_LOGIC := '0';
SIGNAL pdrr4 : STD_LOGIC := '0';
SIGNAL fgh : STD_LOGIC := '0';
SIGNAL invby_a : STD_LOGIC := '0';
SIGNAL invby_b : STD_LOGIC := '0';
SIGNAL invby_c : STD_LOGIC := '0';
SIGNAL invby_d : STD_LOGIC := '0';
SIGNAL invby_e : STD_LOGIC := '0';
SIGNAL invby_f : STD_LOGIC := '0';
SIGNAL invby_g : STD_LOGIC := '0';
SIGNAL invby_h : STD_LOGIC := '0';
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
-----------------------------------------------------------------------------
-- Conditionally tie optional ports to internal signals
-----------------------------------------------------------------------------
----New Data-----------------------------------------------------------------
gnd : IF (C_HAS_ND = 1) GENERATE
----Update the New Data output-------------------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF ((CE = '1') AND (SINIT = '1')) THEN
ND <= '0' AFTER TFF;
ELSE
ND <= CE AFTER TFF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gnd ;
----Code Error---------------------------------------------------------------
gcerr : IF (C_HAS_CODE_ERR = 1) GENERATE
----Update CODE_ERR output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
CODE_ERR <= '0' AFTER TFF;
ELSE
CODE_ERR <= code_err_i AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
END GENERATE gcerr ;
-- The following code uses notation and logic from the 8b/10b specification
-------------------------------------------------------------------------------
-- Set the value of k28 signal
-------------------------------------------------------------------------------
k28 <= NOT((c OR d OR e OR i) OR NOT(h XOR j)) ;
-------------------------------------------------------------------------------
-- Do the 6B/5B conversion
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000110" => b5 <= "00000" ; --D.0
WHEN "111001" => b5 <= "00000" ; --D.0
WHEN "010001" => b5 <= "00001" ; --D.1
WHEN "101110" => b5 <= "00001" ; --D.1
WHEN "010010" => b5 <= "00010" ; --D.2
WHEN "101101" => b5 <= "00010" ; --D.2
WHEN "100011" => b5 <= "00011" ; --D.3
WHEN "010100" => b5 <= "00100" ; --D.4
WHEN "101011" => b5 <= "00100" ; --D.4
WHEN "100101" => b5 <= "00101" ; --D.5
WHEN "100110" => b5 <= "00110" ; --D.6
WHEN "000111" => b5 <= "00111" ; --D.7
WHEN "111000" => b5 <= "00111" ; --D.7
WHEN "011000" => b5 <= "01000" ; --D.8
WHEN "100111" => b5 <= "01000" ; --D.8
WHEN "101001" => b5 <= "01001" ; --D.9
WHEN "101010" => b5 <= "01010" ; --D.10
WHEN "001011" => b5 <= "01011" ; --D.11
WHEN "101100" => b5 <= "01100" ; --D.12
WHEN "001101" => b5 <= "01101" ; --D.13
WHEN "001110" => b5 <= "01110" ; --D.14
WHEN "000101" => b5 <= "01111" ; --D.15
WHEN "111010" => b5 <= "01111" ; --D.15
WHEN "110110" => b5 <= "10000" ; --D.16
WHEN "001001" => b5 <= "10000" ; --D.16
WHEN "110001" => b5 <= "10001" ; --D.17
WHEN "110010" => b5 <= "10010" ; --D.18
WHEN "010011" => b5 <= "10011" ; --D.19
WHEN "110100" => b5 <= "10100" ; --D.20
WHEN "010101" => b5 <= "10101" ; --D.21
WHEN "010110" => b5 <= "10110" ; --D.22
WHEN "010111" => b5 <= "10111" ; --D/K.23
WHEN "101000" => b5 <= "10111" ; --D/K.23
WHEN "001100" => b5 <= "11000" ; --D.24
WHEN "110011" => b5 <= "11000" ; --D.24
WHEN "011001" => b5 <= "11001" ; --D.25
WHEN "011010" => b5 <= "11010" ; --D.26
WHEN "011011" => b5 <= "11011" ; --D/K.27
WHEN "100100" => b5 <= "11011" ; --D/K.27
WHEN "011100" => b5 <= "11100" ; --D.28
WHEN "111100" => b5 <= "11100" ; --K.28
WHEN "000011" => b5 <= "11100" ; --K.28
WHEN "011101" => b5 <= "11101" ; --D/K.29
WHEN "100010" => b5 <= "11101" ; --D/K.29
WHEN "011110" => b5 <= "11110" ; --D.30
WHEN "100001" => b5 <= "11110" ; --D.30
WHEN "110101" => b5 <= "11111" ; --D.31
WHEN "001010" => b5 <= "11111" ; --D.31
WHEN OTHERS => b5 <= DEFAULTB5 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 6B block
-------------------------------------------------------------------------------
PROCESS (b6)
BEGIN
CASE b6 IS
WHEN "000000" => b6_disp <= neg ; --invalid ;
WHEN "000001" => b6_disp <= neg ; --invalid ;
WHEN "000010" => b6_disp <= neg ; --invalid ;
WHEN "000011" => b6_disp <= neg ; --K.28
WHEN "000100" => b6_disp <= neg ; --invalid ;
WHEN "000101" => b6_disp <= neg ; --D.15
WHEN "000110" => b6_disp <= neg ; --D.0
WHEN "000111" => b6_disp <= specneg; --D.7
WHEN "001000" => b6_disp <= neg ; --invalid ;
WHEN "001001" => b6_disp <= neg ; --D.16
WHEN "001010" => b6_disp <= neg ; --D.31
WHEN "001011" => b6_disp <= zero ; --D.11
WHEN "001100" => b6_disp <= neg ; --D.24
WHEN "001101" => b6_disp <= zero ; --D.13
WHEN "001110" => b6_disp <= zero ; --D.14
WHEN "001111" => b6_disp <= pos ; --invalid ;
WHEN "010000" => b6_disp <= neg ; --invalid ;
WHEN "010001" => b6_disp <= neg ; --D.1
WHEN "010010" => b6_disp <= neg ; --D.2
WHEN "010011" => b6_disp <= zero ; --D.19
WHEN "010100" => b6_disp <= neg ; --D.4
WHEN "010101" => b6_disp <= zero ; --D.21
WHEN "010110" => b6_disp <= zero ; --D.22
WHEN "010111" => b6_disp <= pos ; --D.23
WHEN "011000" => b6_disp <= neg ; --D.8
WHEN "011001" => b6_disp <= zero ; --D.25
WHEN "011010" => b6_disp <= zero ; --D.26
WHEN "011011" => b6_disp <= pos ; --D.27
WHEN "011100" => b6_disp <= zero ; --D.28
WHEN "011101" => b6_disp <= pos ; --D.29
WHEN "011110" => b6_disp <= pos ; --D.30
WHEN "011111" => b6_disp <= pos ; --invalid ;
WHEN "100000" => b6_disp <= neg ; --invalid ;
WHEN "100001" => b6_disp <= neg ; --D.30 ;
WHEN "100010" => b6_disp <= neg ; --D.29 ;
WHEN "100011" => b6_disp <= zero ; --D.3
WHEN "100100" => b6_disp <= neg ; --D.27
WHEN "100101" => b6_disp <= zero ; --D.5
WHEN "100110" => b6_disp <= zero ; --D.6
WHEN "100111" => b6_disp <= pos ; --D.8
WHEN "101000" => b6_disp <= neg ; --D.23
WHEN "101001" => b6_disp <= zero ; --D.9
WHEN "101010" => b6_disp <= zero ; --D.10
WHEN "101011" => b6_disp <= pos ; --D.4
WHEN "101100" => b6_disp <= zero ; --D.12
WHEN "101101" => b6_disp <= pos ; --D.2
WHEN "101110" => b6_disp <= pos ; --D.1
WHEN "101111" => b6_disp <= pos ; --invalid ;
WHEN "110000" => b6_disp <= neg ; --invalid ;
WHEN "110001" => b6_disp <= zero ; --D.17
WHEN "110010" => b6_disp <= zero ; --D.18
WHEN "110011" => b6_disp <= pos ; --D.24
WHEN "110100" => b6_disp <= zero ; --D.20
WHEN "110101" => b6_disp <= pos ; --D.31
WHEN "110110" => b6_disp <= pos ; --D.16
WHEN "110111" => b6_disp <= pos ; --invalid ;
WHEN "111000" => b6_disp <= specpos; --D.7
WHEN "111001" => b6_disp <= pos ; --D.0
WHEN "111010" => b6_disp <= pos ; --D.15
WHEN "111011" => b6_disp <= pos ; --invalid ;
WHEN "111100" => b6_disp <= pos ; --K.28
WHEN "111101" => b6_disp <= pos ; --invalid ;
WHEN "111110" => b6_disp <= pos ; --invalid ;
WHEN "111111" => b6_disp <= pos ; --invalid ;
WHEN OTHERS => b6_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Do the 3B/4B conversion
-------------------------------------------------------------------------------
PROCESS (b4, k28)
BEGIN
CASE b4 IS
WHEN "0010" => b3 <= "000" ; --D/K.x.0
WHEN "1101" => b3 <= "000" ; --D/K.x.0
WHEN "1001" =>
IF (k28 = '0')
THEN b3 <= "001" ; --D/K.x.1
ELSE b3 <= "110" ; --K28.6
END IF ;
WHEN "0110" =>
IF (k28 = '1')
THEN b3 <= "001" ; --K.28.1
ELSE b3 <= "110" ; --D/K.x.6
END IF ;
WHEN "1010" =>
IF (k28 = '0')
THEN b3 <= "010" ; --D/K.x.2
ELSE b3 <= "101" ; --K28.5
END IF ;
WHEN "0101" =>
IF (k28 = '1')
THEN b3 <= "010" ; --K28.2
ELSE b3 <= "101" ; --D/K.x.5
END IF ;
WHEN "0011" => b3 <= "011" ; --D/K.x.3
WHEN "1100" => b3 <= "011" ; --D/K.x.3
WHEN "0100" => b3 <= "100" ; --D/K.x.4
WHEN "1011" => b3 <= "100" ; --D/K.x.4
WHEN "0111" => b3 <= "111" ; --D.x.7
WHEN "1000" => b3 <= "111" ; --D.x.7
WHEN "1110" => b3 <= "111" ; --D/K.x.7
WHEN "0001" => b3 <= "111" ; --D/K.x.7
WHEN OTHERS => b3 <= DEFAULTB3 ; --CODE VIOLATION!
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Disparity for the 4B block
-------------------------------------------------------------------------------
PROCESS (b4)
BEGIN
CASE b4 IS
WHEN "0000" => b4_disp <= neg ;
WHEN "0001" => b4_disp <= neg ;
WHEN "0010" => b4_disp <= neg ;
WHEN "0011" => b4_disp <= specneg;
WHEN "0100" => b4_disp <= neg ;
WHEN "0101" => b4_disp <= zero ;
WHEN "0110" => b4_disp <= zero ;
WHEN "0111" => b4_disp <= pos ;
WHEN "1000" => b4_disp <= neg ;
WHEN "1001" => b4_disp <= zero ;
WHEN "1010" => b4_disp <= zero ;
WHEN "1011" => b4_disp <= pos ;
WHEN "1100" => b4_disp <= specpos;
WHEN "1101" => b4_disp <= pos ;
WHEN "1110" => b4_disp <= pos ;
WHEN "1111" => b4_disp <= pos ;
WHEN OTHERS => b4_disp <= zero ;
END CASE ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Special Code for calculating symrd[3:0]
--
-- +---------+---------+-------+------------+-------+------------+
-- | | | symrd |
-- | | | + Start Disp | - Start Disp |
-- | b6_disp | b4_disp | Error | NewRunDisp | Error | NewRunDisp |
-- +---------+---------+-------+------------+-------+------------+
-- | + | + | 1 | 1 | 1 | 1 |
-- | + | - | 1 | 0 | 0 | 0 |
-- | + | 0 | 1 | 1 | 0 | 1 |
-- | - | + | 0 | 1 | 1 | 1 |
-- | - | - | 1 | 0 | 1 | 0 |
-- | - | 0 | 0 | 0 | 1 | 0 |
-- | 0 | + | 1 | 1 | 0 | 1 |
-- | 0 | - | 0 | 0 | 1 | 0 |
-- | 0 | 0 | 0 | 1 | 0 | 0 |
-- +---------+---------+-------+------------+-------+------------+
--
-------------------------------------------------------------------------------
PROCESS (b4_disp, b6_disp)
BEGIN
CASE b6_disp IS
WHEN pos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "1000";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1101"; --Ex: D1.3-
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000";
WHEN zero => symrd(3 DOWNTO 0) <= "1101";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN neg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "0111";
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "0010"; --Ex: D1.3+
WHEN zero => symrd(3 DOWNTO 0) <= "0010";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN zero =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101";
WHEN neg => symrd(3 DOWNTO 0) <= "0010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D11.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D11.3-
WHEN zero => symrd(3 DOWNTO 0) <= "0100";
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specpos =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1111";
WHEN neg => symrd(3 DOWNTO 0) <= "0010"; --Ex: D7.0+
WHEN specpos=> symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.3+
WHEN specneg=> symrd(3 DOWNTO 0) <= "1010";
WHEN zero => symrd(3 DOWNTO 0) <= "0111"; --Ex: D7.5+
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN specneg =>
CASE b4_disp IS
WHEN pos => symrd(3 DOWNTO 0) <= "1101"; --Ex: D7.0-
WHEN neg => symrd(3 DOWNTO 0) <= "1010";
WHEN specpos=> symrd(3 DOWNTO 0) <= "1111";
WHEN specneg=> symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.3-
WHEN zero => symrd(3 DOWNTO 0) <= "1000"; --Ex: D7.5-
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
WHEN OTHERS => symrd(3 DOWNTO 0) <= "XXXX";
END CASE;
END PROCESS;
-- the new running disparity is calculated from the input disparity
-- and the disparity of the 10-bit word
grdi : IF (C_HAS_DISP_IN = 1 AND C_HAS_RUN_DISP=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (DISP_IN = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdi;
-- the new running disparity is calculated from the old running disparity
-- and the disparity of the 10-bit word. run_disp is also used to
-- calculate disp_err and sym_disp when disp_in is not present
grdni : IF (C_HAS_DISP_IN /= 1 AND (C_HAS_RUN_DISP=1 OR
C_HAS_DISP_ERR=1 OR
C_HAS_SYM_DISP=1)) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
run_disp_i <= bint_2_sl(C_SINIT_RUN_DISP) AFTER TFF;
ELSIF (run_disp_i = '1') THEN
run_disp_i <= symrd(2) AFTER TFF;
ELSE
run_disp_i <= symrd(0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE grdni;
gde : IF (C_HAS_DISP_ERR = 1) GENERATE
-- the new disparity error is calculated from the old running disparity
-- and the error information from the 10-bit word
gdei : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (DISP_IN='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdei;
gdeni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
disp_err <= '0' AFTER TFF;
ELSIF (run_disp_i='1') THEN
disp_err <= symrd(3) AFTER TFF;
ELSE
disp_err <= symrd(1) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gdeni;
END GENERATE gde;
gsd : IF (C_HAS_SYM_DISP = 1) GENERATE
gsdi : IF (C_HAS_DISP_IN = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (DISP_IN='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdi;
gsdni : IF (C_HAS_DISP_IN /= 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK='1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
sym_disp_i <= conv_std_logic_vector(C_SINIT_RUN_DISP,2) AFTER TFF;
ELSIF (run_disp_i='1') THEN
sym_disp_i <= symrd(3 DOWNTO 2) AFTER TFF;
ELSE
sym_disp_i <= symrd(1 DOWNTO 0) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gsdni;
END GENERATE gsd;
-- map internal signals to outputs
run_disp <= run_disp_i;
sym_disp <= sym_disp_i;
-------------------------------------------------------------------------------
-- Decode the K codes
-------------------------------------------------------------------------------
PROCESS (c, d, e, i, g, h, j)
BEGIN
k <= (c AND d AND e AND i) OR NOT(c OR d OR e OR i) OR
((e XOR i) AND ((i AND g AND h AND j) OR
NOT(i OR g OR h OR j))) ;
END PROCESS ;
-------------------------------------------------------------------------------
-- Update the outputs on the clock
-------------------------------------------------------------------------------
----Update DOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
dout_i <= str_to_slv(C_SINIT_DOUT, 8) AFTER TFF ;
ELSE
dout_i <= (b3 & b5) AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
DOUT <= dout_i;
----Update KOUT output-------------------
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
kout_i <= bint_2_sl(C_SINIT_KOUT) AFTER TFF;
ELSE
kout_i <= k AFTER TFF;
END IF;
END IF ;
END IF ;
END PROCESS ;
KOUT <= kout_i;
-------------------------------------------------------------------------------
-- Calculate code_error (uses notation from IBM spec)
-------------------------------------------------------------------------------
bitcount: PROCESS (DIN)
BEGIN
CASE DIN(3 DOWNTO 0) IS
WHEN "0000" => p04 <= '1';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0001" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0010" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0011" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0100" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "0101" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0110" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "0111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1000" => p04 <= '0';
p13 <= '1';
p22 <= '0';
p31 <= '0';
p40 <= '0';
WHEN "1001" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1010" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1011" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1100" => p04 <= '0';
p13 <= '0';
p22 <= '1';
p31 <= '0';
p40 <= '0';
WHEN "1101" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1110" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '1';
p40 <= '0';
WHEN "1111" => p04 <= '0';
p13 <= '0';
p22 <= '0';
p31 <= '0';
p40 <= '1';
WHEN OTHERS => NULL;
END CASE;
END PROCESS bitcount;
fghj <= (f AND g AND h AND j) OR (NOT f AND NOT g AND NOT h AND NOT j);
eifgh <= (e AND i AND f AND g AND h) OR (NOT e AND NOT i AND NOT f AND NOT g
AND NOT h);
sk28 <= (c AND d AND e AND i) OR (NOT c AND NOT d AND NOT e AND NOT i);
e_i <= (e AND NOT i) OR (NOT e AND i);
ighj <= (i AND g AND h AND j) OR (NOT i AND NOT g AND NOT h AND NOT j);
i_ghj <= (NOT i AND g AND h AND j) OR (i AND NOT g AND NOT h AND NOT j);
kx7 <= e_i AND ighj;
invr6 <= p40 OR p04 OR (p31 AND e AND i) OR (p13 AND NOT e AND NOT i);
pdbr6 <= (p31 AND (e OR i)) OR (p22 AND e AND i) OR p40;
ndbr6 <= (p13 AND (NOT e OR NOT i)) OR (p22 AND NOT e AND NOT i) OR p04;
pdur6 <= pdbr6 OR (d AND e AND i);
pdbr4 <= (f AND g AND (h OR j)) OR ((f OR g) AND h AND j);
ndrr4 <= pdbr4 OR (f AND g);
ndur6 <= ndbr6 OR (NOT d AND NOT e AND NOT i);
fgh <= (f AND g AND h) OR (NOT f AND NOT g AND NOT h);
ndbr4 <= (NOT f AND NOT g AND (NOT h OR NOT j)) OR ((NOT f OR NOT g) AND
NOT h AND NOT j);
pdrr4 <= ndbr4 OR (NOT f AND NOT g);
invby_a <= invr6;
invby_b <= fghj;
invby_c <= eifgh;
invby_d <= (NOT sk28 AND i_ghj);
invby_e <= (sk28 AND fgh);
invby_f <= (kx7 AND NOT pdbr6 AND NOT ndbr6);
invby_g <= (pdur6 AND ndrr4);
invby_h <= (ndur6 AND pdrr4);
--Update internal code error signal
code_err_i <= invby_a OR invby_b OR invby_c OR invby_d OR invby_e OR invby_f OR
invby_g OR invby_h;
END xilinx ;
|
gpl-3.0
|
b3cbd73b5a33d4625b57a21e39a715c7
| 0.404933 | 3.617407 | false | false | false | false |
makestuff/umdkv2
|
vhdl/spi-funnel/spi_funnel.vhdl
| 1 | 4,941 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_funnel is
port(
clk_in : in std_logic;
reset_in : in std_logic;
-- CPU I/O
cpuByteWide_in : in std_logic;
cpuWrData_in : in std_logic_vector(15 downto 0);
cpuWrValid_in : in std_logic;
cpuRdData_out : out std_logic_vector(15 downto 0);
cpuRdStrobe_in : in std_logic;
-- Sending SPI data
sendData_out : out std_logic_vector(7 downto 0);
sendValid_out : out std_logic;
sendReady_in : in std_logic;
-- Receiving SPI data
recvData_in : in std_logic_vector(7 downto 0);
recvValid_in : in std_logic;
recvReady_out : out std_logic
);
end entity;
architecture rtl of spi_funnel is
type SStateType is (
S_WRITE_MSB,
S_WRITE_LSB
);
type RStateType is (
S_WAIT_MSB,
S_WAIT_LSB
);
signal sstate : SStateType := S_WRITE_MSB;
signal sstate_next : SStateType;
signal rstate : RStateType := S_WAIT_MSB;
signal rstate_next : RStateType;
signal byteWide : std_logic := '0';
signal byteWide_next : std_logic;
signal lsb : std_logic_vector(7 downto 0) := (others => '0');
signal lsb_next : std_logic_vector(7 downto 0);
signal readData : std_logic_vector(15 downto 0) := (others => '0');
signal readData_next : std_logic_vector(15 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
sstate <= S_WRITE_MSB;
rstate <= S_WAIT_MSB;
lsb <= (others => '0');
readData <= (others => '0');
byteWide <= '0';
else
sstate <= sstate_next;
rstate <= rstate_next;
lsb <= lsb_next;
readData <= readData_next;
byteWide <= byteWide_next;
end if;
end if;
end process;
-- Send state machine
process(sstate, lsb, cpuWrData_in, cpuWrValid_in, sendReady_in, cpuByteWide_in, cpuRdStrobe_in, byteWide)
begin
sstate_next <= sstate;
sendValid_out <= '0';
lsb_next <= lsb;
byteWide_next <= byteWide;
case sstate is
-- Now send the LSB to SPI and return:
when S_WRITE_LSB =>
sendData_out <= lsb;
if ( sendReady_in = '1' ) then
sendValid_out <= '1';
sstate_next <= S_WRITE_MSB;
end if;
-- When the CPU writes a word, send the MSB to SPI:
when others =>
sendData_out <= x"55";
if ( cpuByteWide_in = '1' ) then
-- We're sending single bytes rather than 16-bit words. Note
-- the lack of byte auto-read.
if ( cpuWrValid_in = '1' ) then
-- Write next word
sendData_out <= cpuWrData_in(15 downto 8);
sendValid_out <= '1';
byteWide_next <= '1';
end if;
else
-- We're sending 16-bit words rather than single bytes. Note
-- the word auto-read.
if ( cpuWrValid_in = '1' ) then
-- Write next word
sstate_next <= S_WRITE_LSB;
sendData_out <= cpuWrData_in(15 downto 8);
sendValid_out <= '1';
lsb_next <= cpuWrData_in(7 downto 0);
byteWide_next <= '0';
elsif ( cpuRdStrobe_in = '1' ) then
-- Auto-fetch next word when reading
sstate_next <= S_WRITE_LSB;
sendData_out <= x"FF";
sendValid_out <= '1';
lsb_next <= x"FF";
byteWide_next <= '0';
end if;
end if;
end case;
end process;
-- Receive state machine
process(rstate, readData, recvData_in, recvValid_in, byteWide)
begin
rstate_next <= rstate;
readData_next <= readData;
case rstate is
-- Wait for the LSB to arrive:
when S_WAIT_LSB =>
if ( recvValid_in = '1' ) then
rstate_next <= S_WAIT_MSB;
readData_next(7 downto 0) <= recvData_in;
end if;
-- When bytes arrive over SPI, present them (as bytes or words) to the CPU
when others =>
if ( recvValid_in = '1' ) then
if ( byteWide = '1' ) then
-- We're receiving single bytes rather than 16-bit words
readData_next <= recvData_in & x"AA"; --"XXXXXXXX";
else
-- We're receiving 16-bit words rather than single bytes
rstate_next <= S_WAIT_LSB;
readData_next(15 downto 8) <= recvData_in;
end if;
end if;
end case;
end process;
cpuRdData_out <= readData;
recvReady_out <= '1'; -- ready for data from 8-bit side
end architecture;
|
gpl-3.0
|
cee3fa9dfe4d79a24b7f862c9ab92bed
| 0.628618 | 3.14914 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/sram.vhd
| 3 | 2,642 |
----------------------------------------------------------------------------------
-- sram.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple SRAM interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram is
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic;
ramIO1 : INOUT std_logic_vector(15 downto 0);
ramIO2 : INOUT std_logic_vector(15 downto 0);
ramA : OUT std_logic_vector(17 downto 0);
ramWE : OUT std_logic;
ramOE : OUT std_logic;
ramCE1 : OUT std_logic;
ramUB1 : OUT std_logic;
ramLB1 : OUT std_logic;
ramCE2 : OUT std_logic;
ramUB2 : OUT std_logic;
ramLB2 : OUT std_logic
);
end sram;
architecture Behavioral of sram is
signal address : std_logic_vector (17 downto 0);
begin
-- static memory configuration
ramCE1 <= not '1';
ramUB1 <= not '1';
ramLB1 <= not '1';
ramCE2 <= not '1';
ramUB2 <= not '1';
ramLB2 <= not '1';
-- assign signals
ramA <= address;
ramWE <= not write;
ramOE <= not (not write);
output <= ramIO2 & ramIO1;
-- memory io interface state controller
process(write, input)
begin
if write = '1' then
ramIO1 <= input(15 downto 0);
ramIO2 <= input(31 downto 16);
else
ramIO1 <= (others => 'Z');
ramIO2 <= (others => 'Z');
end if;
end process;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
e7cb4fe76691d0b339647d2d69f01a82
| 0.604845 | 3.555855 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Arithmetic/Mult_tb.vhd
| 1 | 2,881 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:26:19 03/07/2014
-- Design Name:
-- Module Name: Z:/SourceSim/Source/Arithmetic/Mult_tb.vhd
-- Project Name: SoundboxSim
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Mult
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.math_real.all;
use work.fixed_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Mult_tb IS
generic (
X_WIDTH : natural := 14;
X_FRACTION : natural := 8;
Y_WIDTH : natural := 16;
Y_FRACTION : natural := 7;
S_WIDTH : natural := 17;
S_FRACTION : natural := 6
);
END entity;
ARCHITECTURE behavior OF Mult_tb IS
--Inputs
signal a : std_logic_vector(X_WIDTH-1 downto 0) := (others => '0');
signal b : std_logic_vector(Y_WIDTH-1 downto 0) := (others => '0');
--Outputs
signal p : std_logic_vector(S_WIDTH-1 downto 0);
constant clock_period : time := 50 ns;
signal a_real_in : real;
signal b_real_in : real;
signal a_real : real;
signal b_real : real;
signal p_real : real;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.Multiplier
generic map (
X_WIDTH => X_WIDTH,
X_FRACTION => X_FRACTION,
Y_WIDTH => Y_WIDTH,
Y_FRACTION => Y_FRACTION,
S_WIDTH => S_WIDTH,
S_FRACTION => S_FRACTION
)
port map (
x => a,
y => b,
s => p
);
-- Stimulus process
stim_proc: process
begin
a_real_in <= 0.0;
b_real_in <= 0.0;
wait for clock_period;
a_real_in <= 1.0;
b_real_in <= 0.5;
wait for clock_period;
a_real_in <= 0.5;
b_real_in <= 0.5;
wait for clock_period;
a_real_in <= -0.5;
b_real_in <= 0.1;
wait for clock_period;
a_real_in <= -0.5;
b_real_in <= -0.25;
wait for clock_period;
a_real_in <= fixed_to_real(x"ffff", X_FRACTION);
b_real_in <= fixed_to_real(x"ffff", Y_FRACTION);
wait;
end process;
a_real <= fixed_to_real(a, X_FRACTION);
b_real <= fixed_to_real(b, Y_FRACTION);
p_real <= fixed_to_real(p, S_FRACTION);
a <= real_to_fixed(a_real_in, X_WIDTH, X_FRACTION);
b <= real_to_fixed(b_real_in, Y_WIDTH, Y_FRACTION);
END;
|
mit
|
af243d6acc9212cada1c0008f6552d58
| 0.591461 | 3.097849 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_eth_rx.vhd
| 1 | 4,216 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_eth_rx IS
END tb_eth_rx;
ARCHITECTURE behavior OF tb_eth_rx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ethernet_receive
PORT(
clk : IN std_logic;
rst : IN std_logic;
PhyRxd : IN std_logic_vector(3 downto 0);
PhyRxDv : IN std_logic;
PhyRxClk : IN std_logic;
Led : OUT std_logic_vector(4 downto 0);
-- Some temporary debug stuff
value : out std_logic_vector(15 downto 0);
sw : in std_logic_vector(7 downto 0);
data : OUT std_logic_vector(7 downto 0);
busPkt : OUT std_logic;
busDesc : OUT std_logic
);
END COMPONENT;
COMPONENT phy_tx
PORT(
clk : IN std_logic;
rst : IN std_logic;
PhyTxClk : IN std_logic;
data : IN std_logic_vector(7 downto 0);
busPkt : IN std_logic;
busDesc : IN std_logic;
PhyTxd : OUT std_logic_vector(3 downto 0);
PhyTxEn : OUT std_logic;
PhyTxEr : OUT std_logic;
Led : OUT std_logic_vector(1 downto 0);
-- Some temporary debug stuff
value : out std_logic_vector(15 downto 0);
sw : in std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal PhyRxd, PhyTxd : std_logic_vector(3 downto 0) := (others => '0');
signal PhyRxDv, PhyTxEn : std_logic := '0';
signal PhyRxClk : std_logic := '0';
--Outputs
signal Led : std_logic_vector(4 downto 0);
signal data : std_logic_vector(7 downto 0);
signal busPkt, PhyTxEr : std_logic;
signal busDesc : std_logic;
signal LedTx : std_logic_vector(1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant PhyRxClk_period : time := 42 ns;
signal clk_o : std_logic;
BEGIN
clk_o <= transport clk after 8 ns;
-- Instantiate the Unit Under Test (UUT)
uut: ethernet_receive PORT MAP (
clk => clk,
rst => rst,
PhyRxd => PhyRxd,
PhyRxDv => PhyRxDv,
PhyRxClk => PhyRxClk,
Led => Led,
data => data,
busPkt => busPkt,
busDesc => busDesc,
sw => ( others => '0' )
);
Inst_phy_tx: phy_tx PORT MAP(
clk => clk,
rst => rst,
PhyTxd => PhyTxd,
PhyTxEn => PhyTxEn,
PhyTxClk => PhyRxClk,
PhyTxEr => PhyTxEr,
Led => LedTx,
data => data,
busPkt => busPkt,
busDesc => busDesc,
sw => ( others => '0' )
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
PhyRxClk_process :process
begin
PhyRxClk <= '0';
wait for PhyRxClk_period/2;
PhyRxClk <= '1';
wait for PhyRxClk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for PhyRxClk_period * 2;
-- hold reset state for 100 ns.
rst <= '0';
wait for PhyRxClk_period * 10;
PhyRxDv <= '1';
PhyRxd <= b"0001";
wait for PhyRxClk_period;
PhyRxd <= b"0001";
wait for PhyRxClk_period;
for i in 0 to 15 loop
PhyRxd <= CONV_std_logic_vector(i, 4);
wait for PhyRxClk_period;
end loop;
PhyRxd <= b"0001";
wait for PhyRxClk_period;
PhyRxd <= b"0001";
wait for PhyRxClk_period;
PhyRxDv <= '0';
PhyRxd <= ( others => '0' );
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
1e42fcacc245c0d0575c6d03f44b0a8f
| 0.616461 | 3.427642 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
stat_writer.vhd
| 1 | 2,604 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity stat_writer is
port (Clk : in std_logic;
Rst : in std_logic;
MemWe : out std_logic_vector(0 downto 0);
MemAddr : out std_logic_vector(8 downto 0);
MemDin : out std_logic_vector(35 downto 0);
MemDout : in std_logic_vector(35 downto 0);
Value : in std_logic_vector(8 downto 0);
Kick : in std_logic);
end stat_writer;
architecture Behavioral of stat_writer is
type state_t is (ZERO_OUT, IDLE, READ_OLD, WRITE_NEW);
signal state, NEXT_state : state_t;
signal addr, NEXT_addr : std_logic_vector(8 downto 0);
begin
MemAddr <= addr;
NEXT_fsm : process (state, addr, MemDout, Value, Kick)
begin
NEXT_state <= state;
NEXT_addr <= addr;
MemDin <= MemDout + 1;
MemWe <= "0";
case state is
when ZERO_OUT =>
NEXT_addr <= addr + 1;
MemWe <= "1";
MemDin <= (others => '0');
if addr = b"1" & X"FF" then
NEXT_state <= IDLE;
end if;
when IDLE =>
if Kick = '1' then
NEXT_state <= READ_OLD;
NEXT_addr <= Value;
end if;
when READ_OLD =>
NEXT_state <= WRITE_NEW;
when WRITE_NEW =>
NEXT_state <= IDLE;
MemWe <= "1";
end case;
end process;
fsm : process (Clk)
begin
if rising_edge(Clk) then
state <= NEXT_state;
addr <= NEXT_addr;
if Rst = '1' then
state <= ZERO_OUT;
addr <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
b66124b9b59281cfbe1252d543301744
| 0.548387 | 3.915789 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sim_1/new/s_top.vhd
| 1 | 4,234 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 19:03:41
-- Design Name:
-- Module Name: s_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity s_top is
end s_top;
architecture Behavioral of s_top is
signal reset : std_logic := '1';
signal clk, clk_out : std_logic := '0';
signal pclk, cam_hsync, cam_vsync, cam_href : std_logic := '0';
signal px_data : std_logic_vector(7 downto 0);
signal data_to_wreiter_ready : std_logic := '0';
signal data_to_wreiter : std_logic_vector(23 downto 0);
signal x, y : integer := 0;
signal tmp_sensor : sensor_vector;
signal tmp_sensor_ready : std_logic := '0';
component sim_tb_bmpread
port(resetn : in std_logic;
pclk : in std_logic;
pixel_data : out std_logic_vector(7 downto 0);
pixel_out_hsync, pixel_out_vsync, pixel_out_href : out std_logic);
end component;
component cam_move is
Port(clk : in STD_LOGIC;
resetn : in STD_LOGIC;
hsync_in : in std_logic;
vsync_in : in std_logic;
href_in : in std_logic;
cam_pxdata : in STD_LOGIC_VECTOR(7 downto 0);
-----
cam_clk : out STD_LOGIC;
px_number : out natural range 0 to 1024 := 0;
line_number : out natural range 0 to 1024 := 0;
pixel_data : out std_logic_vector(23 downto 0);
pixel_data_ready : out STD_LOGIC;
sensor_data : out sensor_vector;
sensor_data_ready : out STD_LOGIC
);
end component;
component bmp_wreiter is
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
start_frame : in STD_LOGIC;
x, y : in positive;
pixel_data : in std_logic_vector(23 downto 0);
pixel_data_ready : in STD_LOGIC;
sensor_data : in sensor_vector;
sensor_data_ready : in STD_LOGIC);
end component;
begin
input : sim_tb_bmpread
port map(
resetn => reset,
pclk => pclk,
pixel_data => px_data,
pixel_out_hsync => cam_hsync,
pixel_out_vsync => cam_vsync,
pixel_out_href => cam_href
);
modul : cam_move
port map(clk => clk,
resetn => reset,
hsync_in => cam_hsync,
vsync_in => cam_vsync,
href_in => cam_href,
cam_pxdata => px_data,
---
cam_clk => pclk,
px_number => x,
line_number => y,
pixel_data => data_to_wreiter,
pixel_data_ready => data_to_wreiter_ready,
sensor_data => tmp_sensor,
sensor_data_ready => tmp_sensor_ready
);
output : bmp_wreiter
port map(
resetn => reset,
clk => clk,
start_frame => cam_vsync,
x => x,
y => y,
pixel_data => data_to_wreiter,
pixel_data_ready => data_to_wreiter_ready,
sensor_data => tmp_sensor,
sensor_data_ready => tmp_sensor_ready
);
clk <= not clk after 10 ns;
reset <= '0', '1' after 20 ns;
end Behavioral;
|
gpl-3.0
|
29711f51c21e4593c9a82da8426a942a
| 0.485829 | 3.807554 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/pack_mips.vhd
| 1 | 15,609 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Enumerations and components declarations --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pack_mips is
-- Type signal on n bits
subtype bus64 is std_logic_vector(63 downto 0);
subtype bus33 is std_logic_vector(32 downto 0);
subtype bus32 is std_logic_vector(31 downto 0);
subtype bus31 is std_logic_vector(30 downto 0);
subtype bus26 is std_logic_vector(25 downto 0);
subtype bus24 is std_logic_vector(23 downto 0);
subtype bus16 is std_logic_vector(15 downto 0);
subtype bus8 is std_logic_vector(7 downto 0);
subtype bus6 is std_logic_vector(5 downto 0);
subtype bus5 is std_logic_vector(4 downto 0);
subtype bus4 is std_logic_vector(3 downto 0);
subtype bus2 is std_logic_vector(1 downto 0);
subtype bus1 is std_logic;
-- Address of a register type
subtype adr_reg_type is std_logic_vector(5 downto 0);
-- Coding of the level of data availability for UR
subtype level_type is std_logic_vector(1 downto 0);
constant LVL_DI : level_type := "11"; -- Data available from the op2 of DI stage
constant LVL_EX : level_type := "10"; -- Data available from the data_ual register of EX stage
constant LVL_MEM : level_type := "01"; -- Data available from the data_ecr register of MEM stage
constant LVL_REG : level_type := "00"; -- Data available only in the register bank
-- Different values of cause exceptions
constant IT_NOEXC : bus32 := X"00000000";
constant IT_ITMAT : bus32 := X"00000001";
constant IT_OVERF : bus32 := X"00000002";
constant IT_ERINS : bus32 := X"00000004";
constant IT_BREAK : bus32 := X"00000008";
constant IT_SCALL : bus32 := X"00000010";
-- Operation type of the coprocessor system (only the low 16 bits are valid)
constant SYS_NOP : bus32 := X"0000_0000";
constant SYS_MASK : bus32 := X"0000_0001";
constant SYS_UNMASK : bus32 := X"0000_0002";
constant SYS_ITRET : bus32 := X"0000_0004";
-- Type for the alu control
subtype alu_ctrl_type is std_logic_vector(27 downto 0);
-- Arithmetical operations
constant OP_ADD : alu_ctrl_type := "1000000000000000000000000000"; -- op1 + op2 sign
constant OP_ADDU : alu_ctrl_type := "0100000000000000000000000000"; -- op1 + op2 non sign
constant OP_SUB : alu_ctrl_type := "0010000000000000000000000000"; -- op1 - op2 sign
constant OP_SUBU : alu_ctrl_type := "0001000000000000000000000000"; -- op1 - op2 non signe
-- Logical operations
constant OP_AND : alu_ctrl_type := "0000100000000000000000000000"; -- et logique
constant OP_OR : alu_ctrl_type := "0000010000000000000000000000"; -- ou logique
constant OP_XOR : alu_ctrl_type := "0000001000000000000000000000"; -- ou exclusif logique
constant OP_NOR : alu_ctrl_type := "0000000100000000000000000000"; -- non ou logique
-- Tests : result to one if ok
constant OP_SLT : alu_ctrl_type := "0000000010000000000000000000"; -- op1 < op2 (sign)
constant OP_SLTU : alu_ctrl_type := "0000000001000000000000000000"; -- op1 < op2 (non sign)
constant OP_EQU : alu_ctrl_type := "0000000000100000000000000000"; -- op1 = op2
constant OP_NEQU : alu_ctrl_type := "0000000000010000000000000000"; -- op1 /= op2
constant OP_SNEG : alu_ctrl_type := "0000000000001000000000000000"; -- op1 < 0
constant OP_SPOS : alu_ctrl_type := "0000000000000100000000000000"; -- op1 > 0
constant OP_LNEG : alu_ctrl_type := "0000000000000010000000000000"; -- op1 <= 0
constant OP_LPOS : alu_ctrl_type := "0000000000000001000000000000"; -- op1 >= 0
-- Multiplications
constant OP_MULT : alu_ctrl_type := "0000000000000000100000000000"; -- op1 * op2 sign (chargement des poids faibles)
constant OP_MULTU : alu_ctrl_type := "0000000000000000010000000000"; -- op1 * op2 non sign (chargement des poids faibles)
-- Shifts
constant OP_SLL : alu_ctrl_type := "0000000000000000001000000000"; -- decallage logique a gauche
constant OP_SRL : alu_ctrl_type := "0000000000000000000100000000"; -- decallage logique a droite
constant OP_SRA : alu_ctrl_type := "0000000000000000000010000000"; -- decallage arithmetique a droite
constant OP_LUI : alu_ctrl_type := "0000000000000000000001000000"; -- met en poids fort la valeur immediate
-- Access to internal registers
constant OP_MFHI : alu_ctrl_type := "0000000000000000000000100000"; -- lecture des poids forts
constant OP_MFLO : alu_ctrl_type := "0000000000000000000000010000"; -- lecture des poids faibles
constant OP_MTHI : alu_ctrl_type := "0000000000000000000000001000"; -- ecriture des poids forts
constant OP_MTLO : alu_ctrl_type := "0000000000000000000000000100"; -- ecriture des poids faibles
-- Operations which do nothing but are useful
constant OP_OUI : alu_ctrl_type := "0000000000000000000000000010"; -- met a 1 le bit de poids faible en sortie
constant OP_OP2 : alu_ctrl_type := "0000000000000000000000000001"; -- recopie l'operande 2 en sortie
-- Starting boot address (after reset)
constant ADR_INIT : bus32 := X"00000000";
constant INS_NOP : bus32 := X"00000000";
-- Internal component of the pipeline stage
component alu
port (
clock : in bus1;
reset : in bus1;
op1 : in bus32;
op2 : in bus32;
ctrl : in alu_ctrl_type;
res : out bus32;
overflow : out bus1
);
end component;
-- Pipeline stage components
component pps_pf
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
bra_cmd : in bus1;
bra_cmd_pr : in bus1;
bra_adr : in bus32;
exch_cmd : in bus1;
exch_adr : in bus32;
stop_pf : in bus1;
PF_pc : out bus32
);
end component;
component pps_ei
port (
clock : in bus1;
reset : in bus1;
clear : in bus1;
stop_all : in bus1;
stop_ei : in bus1;
CTE_instr : in bus32;
ETC_adr : out bus32;
PF_pc : in bus32;
EI_instr : out bus32;
EI_adr : out bus32;
EI_it_ok : out bus1
);
end component;
component pps_di
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
adr_reg1 : out adr_reg_type;
adr_reg2 : out adr_reg_type;
use1 : out bus1;
use2 : out bus1;
stop_di : in bus1;
data1 : in bus32;
data2 : in bus32;
EI_adr : in bus32;
EI_instr : in bus32;
EI_it_ok : in bus1;
DI_bra : out bus1;
DI_link : out bus1;
DI_op1 : out bus32;
DI_op2 : out bus32;
DI_code_ual : out alu_ctrl_type;
DI_offset : out bus32;
DI_adr_reg_dest : out adr_reg_type;
DI_ecr_reg : out bus1;
DI_mode : out bus1;
DI_op_mem : out bus1;
DI_r_w : out bus1;
DI_adr : out bus32;
DI_exc_cause : out bus32;
DI_level : out level_type;
DI_it_ok : out bus1
);
end component;
component pps_ex
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
DI_bra : in bus1;
DI_link : in bus1;
DI_op1 : in bus32;
DI_op2 : in bus32;
DI_code_ual : in alu_ctrl_type;
DI_offset : in bus32;
DI_adr_reg_dest : in adr_reg_type;
DI_ecr_reg : in bus1;
DI_mode : in bus1;
DI_op_mem : in bus1;
DI_r_w : in bus1;
DI_adr : in bus32;
DI_exc_cause : in bus32;
DI_level : in level_type;
DI_it_ok : in bus1;
EX_adr : out bus32;
EX_bra_confirm : out bus1;
EX_data_ual : out bus32;
EX_adresse : out bus32;
EX_adr_reg_dest : out adr_reg_type;
EX_ecr_reg : out bus1;
EX_op_mem : out bus1;
EX_r_w : out bus1;
EX_exc_cause : out bus32;
EX_level : out level_type;
EX_it_ok : out bus1
);
end component;
component pps_mem
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
MTC_data : out bus32;
MTC_adr : out bus32;
MTC_r_w : out bus1;
MTC_req : out bus1;
CTM_data : in bus32;
EX_adr : in bus32;
EX_data_ual : in bus32;
EX_adresse : in bus32;
EX_adr_reg_dest : in adr_reg_type;
EX_ecr_reg : in bus1;
EX_op_mem : in bus1;
EX_r_w : in bus1;
EX_exc_cause : in bus32;
EX_level : in level_type;
EX_it_ok : in bus1;
MEM_adr : out bus32;
MEM_adr_reg_dest : out adr_reg_type;
MEM_ecr_reg : out bus1;
MEM_data_ecr : out bus32;
MEM_exc_cause : out bus32;
MEM_level : out level_type;
MEM_it_ok : out bus1
);
end component;
component renvoi
port (
adr1 : in adr_reg_type;
adr2 : in adr_reg_type;
use1 : in bus1;
use2 : in bus1;
data1 : out bus32;
data2 : out bus32;
alea : out bus1;
DI_level : in level_type;
DI_adr : in adr_reg_type;
DI_ecr : in bus1;
DI_data : in bus32;
EX_level : in level_type;
EX_adr : in adr_reg_type;
EX_ecr : in bus1;
EX_data : in bus32;
MEM_level : in level_type;
MEM_adr : in adr_reg_type;
MEM_ecr : in bus1;
MEM_data : in bus32;
interrupt : in bus1;
write_data : out bus32;
write_adr : out bus5;
write_GPR : out bus1;
write_SCP : out bus1;
read_adr1 : out bus5;
read_adr2 : out bus5;
read_data1_GPR : in bus32;
read_data1_SCP : in bus32;
read_data2_GPR : in bus32;
read_data2_SCP : in bus32
);
end component;
component banc
port (
clock : in bus1;
reset : bus1;
reg_src1 : in bus5;
reg_src2 : in bus5;
reg_dest : in bus5;
donnee : in bus32;
cmd_ecr : in bus1;
data_src1 : out bus32;
data_src2 : out bus32
);
end component;
component bus_ctrl
port
(
clock : bus1;
reset : bus1;
interrupt : in std_logic;
adr_from_ei : in bus32;
instr_to_ei : out bus32;
req_from_mem : in bus1;
r_w_from_mem : in bus1;
adr_from_mem : in bus32;
data_from_mem : in bus32;
data_to_mem : out bus32;
req_to_ram : out std_logic;
adr_to_ram : out bus32;
r_w_to_ram : out bus1;
ack_from_ram : in bus1;
data_inout_ram : inout bus32;
stop_all : out bus1
);
end component;
component syscop
port
(
clock : in bus1;
reset : in bus1;
MEM_adr : in bus32;
MEM_exc_cause : in bus32;
MEM_it_ok : in bus1;
it_mat : in bus1;
interrupt : out bus1;
vecteur_it : out bus32;
write_data : in bus32;
write_adr : in bus5;
write_SCP : in bus1;
read_adr1 : in bus5;
read_adr2 : in bus5;
read_data1 : out bus32;
read_data2 : out bus32
);
end component;
component predict
generic (
nb_record : integer := 3
);
port (
clock : in std_logic;
reset : in std_logic;
PF_pc : in std_logic_vector(31 downto 0);
DI_bra : in std_logic;
DI_adr : in std_logic_vector(31 downto 0);
EX_bra_confirm : in std_logic;
EX_adr : in std_logic_vector(31 downto 0);
EX_adresse : in std_logic_vector(31 downto 0);
EX_uncleared : in std_logic;
PR_bra_cmd : out std_logic;
PR_bra_bad : out std_logic;
PR_bra_adr : out std_logic_vector(31 downto 0);
PR_clear : out std_logic
);
end component;
component minimips
port (
clock : in bus1;
reset : in bus1;
ram_req : out bus1;
ram_adr : out bus32;
ram_r_w : out bus1;
ram_data : inout bus32;
ram_ack : in bus1;
it_mat : in bus1
);
end component;
end pack_mips;
|
gpl-2.0
|
64755a55729ef6265d15c0e63f7fee65
| 0.505926 | 3.934711 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
dbg_termination.vhd
| 1 | 2,466 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dbg_termination is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
pkt : in STD_LOGIC;
desc : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
led : out STD_LOGIC_VECTOR(1 downto 0);
value : out STD_LOGIC_VECTOR(15 downto 0));
end dbg_termination;
architecture Behavioral of dbg_termination is
signal ctrl, oldPkt : STD_LOGIC;
begin
ctrl <= pkt when sw(7) = '0'
else desc;
oldPkt <= pkt when RISING_EDGE(clk);
bothTest : process (clk)
variable prev : STD_LOGIC := '0';
begin
if RISING_EDGE(clk) then
prev := prev or (pkt and desc);
led(0) <= prev;
if rst = '1' then
prev := '0';
end if;
end if;
end process;
zeroTest : process (clk)
variable prev : STD_LOGIC := '0';
begin
if RISING_EDGE(clk) then
-- if desc = '1' and data = "00000000" then
if pkt = '1' and sw = "1111" then
prev := '1';
else
prev := prev;
end if;
led(1) <= prev;
if rst = '1' then
prev := '0';
end if;
end if;
end process;
main: process (clk)
variable cnt : STD_LOGIC_VECTOR(7 downto 0);
begin
if RISING_EDGE(clk) then
if ctrl = '1' then
if cnt(7 downto 1) = sw(6 downto 0) then
if cnt(0) = '0' then
value(15 downto 8) <= data;
else
value(7 downto 0) <= data;
end if;
end if;
cnt := cnt + 1;
end if;
if oldPkt = '1' and pkt = '0' then
cnt := (others => '0');
end if;
if rst = '1' then
value <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
132245064f598c2d4abc26cf820be2b4
| 0.609895 | 3.101887 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_FIR.vhd
| 1 | 4,175 |
------------------------------------------------------
-------------------------------------------------------
-- Description: --
-- Implementation of a generic direct FIR-filter --
-- Note that the lower N_WIDTH-1 bits will be --
-- binals --
-- --
-- Input/Output: --
-- WIDTH - Width of input and output --
-- N - Number of coefficients --
-- clk - Clock --
-- clk_en - Clock enable, takes input when high --
-- x - Input, WIDTH bits --
-- y - Output, WIDTH bits --
-- --
-- Internal Constants --
-- N_WIDTH - Width of the coefficients --
-- N_BINALS - Number of binals in the coefficients --
-------------------------------------------------------
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_FIR is
generic (WIDTH : integer := 8;
N : integer := 10);
port(clk : in std_logic;
clk_en : in std_logic;
x : in std_logic_vector(WIDTH-1 downto 0);
y : out std_logic_vector(WIDTH-1 downto 0));
end Generic_FIR;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_FIR is
-- Constants
constant N_WIDTH : integer := 8;
constant N_BINALS : integer := 6;
-- Type declarations
type array_input is array(0 to N-1) of std_logic_vector(WIDTH-1 downto 0);
type array_coeffecient is array(0 to N-1) of std_logic_vector( N_WIDTH-1 downto 0);
type array_result is array(0 to N-1) of signed (WIDTH + N_WIDTH-1 downto 0);
-- Coefficients
constant coefficients : array_coeffecient := ("01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000",
"01000000");
-- Signal Declarations
signal my_inputs : array_input := (others => (others => '0'));
signal my_mults : array_result := (others => (others => '0'));
signal my_sum : array_result := (others => (others => '0'));
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Shift the input registers
p_shift_inputs : process(clk)
begin
if(rising_edge(clk)) then
if(clk_en = '1') then
my_inputs(0) <= x;
my_inputs(1 to N-1) <= my_inputs(0 to N-2);
end if;
end if;
end process p_shift_inputs;
-- Multiply the input with coefficients
gen_mults:
for i in 0 to N-1 generate
my_mults(i) <= signed(my_inputs(i)) * signed(coefficients(i));
end generate gen_mults;
-- Add the multiplications together
my_sum(N-1) <= my_mults(N-1);
gen_adds:
for i in 0 to N-2 generate
my_sum(i) <= my_sum(i+1) + my_mults(i);
end generate gen_adds;
-- Output the result
y <= std_logic_vector(my_sum(0)(WIDTH+N_BINALS-1 downto N_BINALS));
end behaviour;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
|
mit
|
9ce6e28ca23851a55c4e5f1e0839d9f4
| 0.358802 | 5.271465 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/base_line/NI.vhd
| 1 | 14,622 |
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_x : integer := 10; -- the current node's x
current_y : integer := 10; -- the current node's y
NI_depth : integer := 32;
NI_couter_size: integer:= 5; -- should be set to log2 of NI_depth
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- NI's memory mapped reserved
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the flag register
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- packet counter register address!
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- interrupt signal: disabled!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC
);
end; --entity NI
architecture logic of NI is
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
-- this old address is put here to make it compatible with Plasma processor!
signal old_address: std_logic_vector(31 downto 2);
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal P2N_write_en: std_logic;
type MEM is array (0 to NI_depth-1) of std_logic_vector(31 downto 0);
signal P2N_FIFO, P2N_FIFO_in : MEM;
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO, N2P_FIFO_in : MEM;
signal N2P_Data_out : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= (others=>'0');
P2N_FIFO_write_pointer <= (others=>'0');
P2N_FIFO <= (others => (others=>'0'));
credit_counter_out <= "11";
packet_length_counter_out <= "00000000000000";
state <= IDLE;
packet_counter_out <= "00000000000000";
------------------------------------------------
N2P_FIFO <= (others => (others=>'0'));
N2P_FIFO_read_pointer <= (others=>'0');
N2P_FIFO_write_pointer <= (others=>'0');
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO <= P2N_FIFO_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO <= N2P_FIFO_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
-- If PE wants to send data to NoC via NI (data is valid)
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
process(storage, P2N_FIFO_write_pointer, P2N_FIFO) begin
P2N_FIFO_in <= P2N_FIFO;
P2N_FIFO_in(to_integer(unsigned(P2N_FIFO_write_pointer))) <= storage;
end process;
FIFO_Data_out <= P2N_FIFO(to_integer(unsigned(P2N_FIFO_read_pointer)));
-- Write pointer update process (after each write operation, write pointer is rotated one bit to the left)
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1' then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer +1 ;
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
-- Read pointer update process (after each read operation, read pointer is rotated one bit to the left)
process(P2N_FIFO_read_pointer, grant)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' then
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer +1;
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
-- Process for updating full and empty signals
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer - 1 then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out)
begin
-- Some initializations
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
TX <= "001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT_1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT_1 =>
if credit_counter_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - 1;
if packet_length_counter_out > 2 then
state_in <= BODY_FLIT;
else
state_in <= TAIL_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
packet_length_counter_in <= packet_length_counter_out - 1;
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
process(RX, N2P_FIFO_write_pointer, N2P_FIFO) begin
N2P_FIFO_in <= N2P_FIFO;
N2P_FIFO_in(to_integer(unsigned(N2P_FIFO_write_pointer))) <= RX;
end process;
N2P_Data_out <= N2P_FIFO(to_integer(unsigned(N2P_FIFO_read_pointer)));
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer + 1;
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer + 1;
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer-1 then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & "000000000000000000000000000000";
irq_out <= '0';
end; --architecture logic
|
gpl-3.0
|
58f0f7029da2fc12b8b84a73f2855758
| 0.583778 | 3.290279 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/tx-core/tx_channel.vhd
| 1 | 2,614 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Single tx_channel
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_channel is
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data In
wb_dat_i : in std_logic_vector(31 downto 0);
wb_wr_en_i : in std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic;
tx_enable_i : in std_logic;
-- Status
tx_underrun_o : out std_logic;
tx_overrun_o : out std_logic;
tx_almost_full_o : out std_logic;
tx_empty_o : out std_logic
);
end tx_channel;
architecture rtl of tx_channel is
-- Components
component serial_port
generic (
g_PORT_WIDTH : integer := 32
);
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Input
enable_i : in std_logic;
data_i : in std_logic_vector(31 downto 0);
data_valid_i : in std_logic;
-- Output
data_o : out std_logic;
data_read_o : out std_logic
);
end component;
component tx_fifo
port (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
end component;
signal tx_fifo_rd : std_logic;
signal tx_fifo_wr : std_logic;
signal tx_fifo_din : std_logic_vector(31 downto 0);
signal tx_fifo_dout : std_logic_vector(31 downto 0);
signal tx_fifo_full : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
begin
-- Write to FiFo
tx_fifo_wr <= wb_wr_en_i;
tx_fifo_din <= wb_dat_i;
-- Status outputs
tx_underrun_o <= tx_fifo_rd and tx_fifo_empty;
tx_overrun_o <= tx_fifo_wr and tx_fifo_full;
tx_almost_full_o <= tx_fifo_almost_full;
tx_empty_o <= tx_fifo_empty;
cmp_sport: serial_port PORT MAP(
clk_i => tx_clk_i,
rst_n_i => rst_n_i,
enable_i => tx_enable_i,
data_i => tx_fifo_dout,
data_valid_i => not tx_fifo_empty,
data_o => tx_data_o,
data_read_o => tx_fifo_rd
);
cmp_tx_fifo : tx_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => wb_clk_i,
rd_clk => tx_clk_i,
din => tx_fifo_din,
wr_en => tx_fifo_wr,
rd_en => tx_fifo_rd,
dout => tx_fifo_dout,
full => tx_fifo_full,
empty => tx_fifo_empty,
prog_full => tx_fifo_almost_full
);
end rtl;
|
gpl-3.0
|
34976dec755542f6b3893c3f4f65ae95
| 0.58378 | 2.595829 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/NI.vhd
| 1 | 23,907 |
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use ieee.std_logic_misc.all;
entity NI_vc is
generic(current_x : integer := 10; -- the current node's x
current_y : integer := 10; -- the current node's y
NI_depth : integer := 32;
NI_couter_size: integer:= 5; -- should be set to log2 of NI_depth
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111110"; -- NI's memory mapped reserved VC_0
reserved_address_vc : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; -- NI's memory mapped reserved for VC_1
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the flag register
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- packet counter register address!
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- interrupt signal: disabled!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
credit_in_vc: in std_logic;
valid_out_vc: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
credit_out_vc: out std_logic;
valid_in_vc: in std_logic;
RX: in std_logic_vector(31 downto 0) -- data recieved form the NoC
);
end; --entity NI_vc
architecture logic of NI_vc is
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
-- this old address is put here to make it compatible with Plasma processor!
signal old_address: std_logic_vector(31 downto 2);
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal P2N_write_en: std_logic;
type MEM is array (0 to NI_depth-1) of std_logic_vector(31 downto 0);
signal P2N_FIFO, P2N_FIFO_in : MEM;
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal credit_counter_vc_in, credit_counter_vc_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(13 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(13 downto 0);
signal grant,grant_vc : std_logic;
signal vc_select_in, vc_select_out: std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT_1, BODY_FLIT, TAIL_FLIT);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO, N2P_FIFO_in : MEM;
signal N2P_FIFO_vc, N2P_FIFO_vc_in : MEM;
signal N2P_Data_out : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_FIFO_vc_read_pointer, N2P_FIFO_vc_read_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_FIFO_vc_write_pointer, N2P_FIFO_vc_write_pointer_in: std_logic_vector(NI_couter_size-1 downto 0);
signal N2P_full, N2P_empty, N2P_full_vc, N2P_empty_vc: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_read_en_vc, N2P_read_en_vc_in, N2P_write_en, N2P_write_en_vc: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
begin
CLK_proc: process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= (others=>'0');
P2N_FIFO_write_pointer <= (others=>'0');
P2N_FIFO <= (others => (others=>'0'));
credit_counter_out <= "11";
credit_counter_vc_out <= "11";
packet_length_counter_out <= "00000000000000";
state <= IDLE;
packet_counter_out <= "00000000000000";
------------------------------------------------
N2P_FIFO <= (others => (others=>'0'));
N2P_FIFO_vc <= (others => (others=>'0'));
N2P_FIFO_read_pointer <= (others=>'0');
N2P_FIFO_write_pointer <= (others=>'0');
N2P_FIFO_vc_read_pointer <= (others=>'0');
N2P_FIFO_vc_write_pointer <= (others=>'0');
credit_out <= '0';
credit_out_vc <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
N2P_read_en_vc <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
vc_select_out <= '0';
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
credit_counter_vc_out <= credit_counter_vc_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO <= P2N_FIFO_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO <= N2P_FIFO_in;
end if;
if N2P_write_en_vc = '1' then
--write into the memory
N2P_FIFO_vc <= N2P_FIFO_vc_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
N2P_FIFO_vc_write_pointer <= N2P_FIFO_vc_write_pointer_in;
N2P_FIFO_vc_read_pointer <= N2P_FIFO_vc_read_pointer_in;
credit_out <= '0';
credit_out_vc <= '0';
N2P_read_en <= N2P_read_en_in;
N2P_read_en_vc <= N2P_read_en_vc_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
if N2P_read_en_vc = '1' then
credit_out_vc <= '1';
end if;
flag_register <= flag_register_in;
vc_select_out <= vc_select_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
P2N_wbe:process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
-- If PE wants to send data to NoC via NI (data is valid)
if enable = '1' and (address = reserved_address or address = reserved_address_vc) then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------
-- P2N FIFO handler
process(storage, P2N_FIFO_write_pointer, P2N_FIFO) begin
P2N_FIFO_in <= P2N_FIFO;
P2N_FIFO_in(to_integer(unsigned(P2N_FIFO_write_pointer))) <= storage;
end process;
FIFO_Data_out <= P2N_FIFO(to_integer(unsigned(P2N_FIFO_read_pointer)));
-----------------------------------------------------------------------------------------------
-- Write pointer update process (after each write operation, write pointer is rotated one bit to the left)
P2N_wp: process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1' then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer +1 ;
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
-----------------------------------------------------------------------------------------------
-- Read pointer update process (after each read operation, read pointer is rotated one bit to the left)
P2N_rp: process(P2N_FIFO_read_pointer, grant, grant_vc)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' or grant_vc = '1' then
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer +1;
end if;
end process;
-----------------------------------------------------------------------------------------------
P2N_write_en_proc:process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------
-- Process for updating full and empty signals
P2N_empy_full:process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer - 1 then
P2N_full <= '1';
end if;
end process;
--------------------------------------------------------------------------------
VC_0_credit_counter:process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
VC_1_credit_counter:process (credit_in_vc, credit_counter_vc_out, grant_vc)begin
credit_counter_vc_in <= credit_counter_vc_out;
if credit_in_vc = '1' and grant_vc = '1' then
credit_counter_vc_in <= credit_counter_vc_out;
elsif credit_in_vc = '1' and credit_counter_vc_out < 3 then
credit_counter_vc_in <= credit_counter_vc_out + 1;
elsif grant_vc = '1' and credit_counter_vc_out > 0 then
credit_counter_vc_in <= credit_counter_vc_out - 1;
end if;
end process;
--------------------------------------------------------------------------------
Packet_generator: process(P2N_empty, state, credit_counter_out,
credit_counter_vc_out,
packet_length_counter_out, packet_counter_out,
FIFO_Data_out, vc_select_out)
begin
-- Some initializations
vc_select_in <= vc_select_out;
TX <= (others => '0');
grant<= '0';
grant_vc<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if FIFO_Data_out(14) = '1' then
if credit_counter_vc_out /= "00" and P2N_empty = '0' then
grant_vc<= '1';
vc_select_in <= '1';
TX <= "001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT_1;
else
state_in <= HEADER_FLIT;
end if;
else
if credit_counter_out /= "00" and P2N_empty = '0' then
grant<= '1';
vc_select_in <= '0';
TX <= "001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0) & XOR_REDUCE("001" & std_logic_vector(to_unsigned(current_y, 7)) & std_logic_vector(to_unsigned(current_x, 7)) & FIFO_Data_out(13 downto 0));
state_in <= BODY_FLIT_1;
else
state_in <= HEADER_FLIT;
end if;
end if;
when BODY_FLIT_1 =>
if vc_select_out = '0' then
if credit_counter_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
else
if credit_counter_vc_out /= "00" and P2N_empty = '0'then
packet_length_counter_in <= (FIFO_Data_out(27 downto 14))-2;
grant_vc <= '1';
TX <= "010" &FIFO_Data_out(27 downto 14) & packet_counter_out & XOR_REDUCE( "010" &FIFO_Data_out(27 downto 14) & packet_counter_out);
state_in <= BODY_FLIT;
else
state_in <= BODY_FLIT_1;
end if;
end if;
when BODY_FLIT =>
if vc_select_out = '0' then
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - 1;
if packet_length_counter_out > 2 then
state_in <= BODY_FLIT;
else
state_in <= TAIL_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
else
if credit_counter_vc_out /= "00" and P2N_empty = '0'then
grant_vc<= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - 1;
if packet_length_counter_out > 2 then
state_in <= BODY_FLIT;
else
state_in <= TAIL_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
end if;
when TAIL_FLIT =>
if vc_select_out = '0' then
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
packet_length_counter_in <= packet_length_counter_out - 1;
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
vc_select_in <= '0';
else
state_in <= TAIL_FLIT;
end if;
else
if credit_counter_vc_out /= "00" and P2N_empty = '0' then
grant_vc<= '1';
packet_length_counter_in <= packet_length_counter_out - 1;
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
vc_select_in <= '0';
else
state_in <= TAIL_FLIT;
end if;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
valid_out_vc <= grant_vc;
--------------------------------------------------------------------------------
vc0_N2P_wr_FIFO_data: process(RX, N2P_FIFO_write_pointer, N2P_FIFO) begin
N2P_FIFO_in <= N2P_FIFO;
N2P_FIFO_in(to_integer(unsigned(N2P_FIFO_write_pointer))) <= RX;
end process;
vc1_N2P_wr_FIFO_data:process(RX, N2P_FIFO_vc_write_pointer, N2P_FIFO_vc) begin
N2P_FIFO_vc_in <= N2P_FIFO_vc;
N2P_FIFO_vc_in(to_integer(unsigned(N2P_FIFO_vc_write_pointer))) <= RX;
end process;
--------------------------------------------------------------------------------
N2P_rd_FIFO_data: process(address, N2P_FIFO_read_pointer, N2P_FIFO_vc_read_pointer, N2P_FIFO, N2P_FIFO_vc)
begin
if address = reserved_address then
N2P_Data_out <= N2P_FIFO(to_integer(unsigned(N2P_FIFO_read_pointer)));
else
N2P_Data_out <= N2P_FIFO_vc(to_integer(unsigned(N2P_FIFO_vc_read_pointer)));
end if;
end process;
--------------------------------------------------------------------------------
N2P_read_enable:process(address, write_byte_enable, N2P_empty, N2P_empty_vc)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
if address = reserved_address_vc and write_byte_enable = "0000" and N2P_empty_vc = '0' then
N2P_read_en_vc_in <= '1';
else
N2P_read_en_vc_in <= '0';
end if;
end process;
--------------------------------------------------------------------------------
vc0_N2P_wr_pointer:process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer + 1;
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
vc1_N2P_wr_pointer:process(N2P_write_en_vc, N2P_FIFO_vc_write_pointer)begin
if N2P_write_en_vc= '1'then
N2P_FIFO_vc_write_pointer_in <= N2P_FIFO_vc_write_pointer + 1;
else
N2P_FIFO_vc_write_pointer_in <= N2P_FIFO_vc_write_pointer;
end if;
end process;
--------------------------------------------------------------------------------
vc0_N2P_rd_pointer:process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer + 1;
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
vc1_N2P_rd_pointer:process(N2P_read_en_vc, N2P_empty_vc, N2P_FIFO_vc_read_pointer)begin
if (N2P_read_en_vc = '1' and N2P_empty_vc = '0') then
N2P_FIFO_vc_read_pointer_in <= N2P_FIFO_vc_read_pointer + 1;
else
N2P_FIFO_vc_read_pointer_in <= N2P_FIFO_vc_read_pointer;
end if;
end process;
--------------------------------------------------------------------------------
vc0_N2P_wr_en: process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
vc1_N2P_wr_en: process(N2P_full_vc, valid_in_vc) begin
if (valid_in_vc = '1' and N2P_full_vc ='0') then
N2P_write_en_vc <= '1';
else
N2P_write_en_vc <= '0';
end if;
end process;
--------------------------------------------------------------------------------
vc0_N2P_empty_full: process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer-1 then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
vc1_N2P_empty_full: process(N2P_FIFO_vc_write_pointer, N2P_FIFO_vc_read_pointer) begin
if N2P_FIFO_vc_read_pointer = N2P_FIFO_vc_write_pointer then
N2P_empty_vc <= '1';
else
N2P_empty_vc <= '0';
end if;
if N2P_FIFO_vc_write_pointer = N2P_FIFO_vc_read_pointer-1 then
N2P_full_vc <= '1';
else
N2P_full_vc <= '0';
end if;
end process;
--------------------------------------------------------------------------------
date_rd: process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if (old_address = reserved_address and N2P_read_en = '1') or
(old_address = reserved_address_vc and N2P_read_en_vc = '1') then
data_read <= N2P_Data_out;
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
else
data_read <= (others => 'U');
end if;
end process;
-- we have to double check if we need this counter
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
if N2P_write_en_vc = '1' and RX(31 downto 29) = "001" and N2P_read_en_vc = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en_vc = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_write_en_vc = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & N2P_empty_vc & "00000000000000000000000000000";
irq_out <= '0';
end; --architecture logic
|
gpl-3.0
|
b98786e1dee295abe7a82cff9c20631d
| 0.534655 | 3.358668 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/virtual_channel/flit_tracker.vhd
| 14 | 2,969 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- This module Monitors the links status along side with the valid data value
-- in case there is a valid flit on the link, the module produces a log entery
-- in the tracker_file location.
--
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end;
architecture behavior of flit_tracker is
begin
process(clk)
variable source_id, destination_id, Packet_length, packet_id: integer;
variable xor_check : std_logic;
-- file handeling
file trace_file : text is out tracker_file;
variable LINEVARIABLE : line;
begin
Packet_length := 0;
destination_id := 0;
source_id := 0;
packet_id := 0;
if clk'event and clk = '1' then -- checks the link status on the rising edge of the clock!
if unsigned(RX) /= to_unsigned(0, RX'length) and valid_in = '1' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
Packet_length := to_integer(unsigned(RX(28 downto 17)));
destination_id := to_integer(unsigned(RX(16 downto 13)));
source_id := to_integer(unsigned(RX(12 downto 9)));
packet_id := to_integer(unsigned(RX(8 downto 1)));
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id));
else
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "B flit at " & time'image(now));
else
write(LINEVARIABLE, "B flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "T flit at " & time'image(now));
else
write(LINEVARIABLE, "T flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
end if;
end if;
end if;
end process;
end;
|
gpl-3.0
|
f694400c56d699fc6608b047996ce1da
| 0.620411 | 3.277042 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sim_1/new/bmp_wreiter.vhd
| 1 | 2,567 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 20:50:53
-- Design Name:
-- Module Name: bmp_wreiter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Ändert gelesene BMP datei und schreibt es in neues BMP.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use work.sim_bmppack.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity bmp_wreiter is
GENERIC(byte_per_pixel : natural := 3);
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
start_frame : in STD_LOGIC;
x, y : in natural;
pixel_data : in std_logic_vector(23 downto 0);
pixel_data_ready : in STD_LOGIC;
sensor_data : in sensor_vector;
sensor_data_ready : in STD_LOGIC);
end bmp_wreiter;
architecture Behavioral of bmp_wreiter is
signal file_writed : std_logic := '0';
signal ImageWidth, ImageHeight, x_old : natural := 0;
signal px_data_tmp : std_logic_vector(23 downto 0) := (others => '0');
begin
writer : process is
variable tmp_sensor_vec : sensor_vector;
variable tmp_sensor : sensor;
begin
wait until rising_edge(clk);
if resetn = '1' then
if (x /= x_old) then
x_old <= x;
if (pixel_data_ready = '1') then -- selber bild abbilden
SetPixel(x, y, pixel_data);
end if;
if (sensor_data_ready = '1' ) then -- sensor abbilden
tmp_sensor := vector2sensor(sensor_data);
px_data_tmp (7 downto 0) <= conv_std_logic_vector(tmp_sensor.color.r, 8);
px_data_tmp (15 downto 8) <= conv_std_logic_vector(tmp_sensor.color.g, 8);
px_data_tmp (23 downto 16) <= conv_std_logic_vector(tmp_sensor.color.b, 8);
end if;
if (y = 640) then -- FIXME ende schreiben, dann
DrawCross(tmp_sensor.pos.x, tmp_sensor.pos.y, px_data_tmp);
if file_writed = '0' then
report "write File...";
WriteFile(" ..\..\test_out.bmp");
file_writed <= '1';
report "File is written.";
end if;
wait;
end if;
end if;
end if;
end process writer;
end Behavioral;
|
gpl-3.0
|
9e1192347242486a4fb6fab8cacbab39
| 0.547332 | 3.346806 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sources_1/new/get_mark_points.vhd
| 1 | 2,565 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 19:54:01
-- Design Name:
-- Module Name: get_mark_points - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity get_mark_points is
GENERIC(byte_per_pixel : natural := 3;
width : natural := 480;
hight : natural := 640);
PORT(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
vsync : in STD_LOGIC;
href : in STD_LOGIC;
px_data : in STD_LOGIC_VECTOR(7 downto 0);
--- out
data_ready : out STD_LOGIC; -- auf steigende flanke clk, data abnehmen
px_count_out, line_count_out : out positive;
px_data_out : out STD_LOGIC_VECTOR(byte_per_pixel*8 - 1 downto 0)
);
end get_mark_points;
architecture Behavioral of get_mark_points is
signal bit_number : natural := 0;
begin
byte_counts : process(clk)
variable px_count, line_count : natural := 0;
begin
if (clk'event and clk = '0') then
if resetn = '0' then
px_data_out <= (others => '0');
data_ready <= '0';
else
-- VSYNC
if (vsync = '1') then
px_count := 0;
line_count := 0;
end if;
data_ready <= '0';
if (href = '1') then
case bit_number is
when 0 => px_data_out(23 downto 16) <= px_data;
when 1 => px_data_out(15 downto 8) <= px_data;
when 2 => px_data_out(7 downto 0) <= px_data;
when others =>
end case;
if ( bit_number = byte_per_pixel - 1) then
px_count := px_count + 1;
bit_number <= 0;
data_ready <= '1';
else
bit_number <= bit_number + 1;
end if;
else
px_count := 0;
bit_number <= 0;
end if;
if px_count = width then
line_count := line_count + 1;
end if;
px_count_out <= px_count;
line_count_out <= line_count;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
07f7782ec62dad7c72f6f8c2b765a12b
| 0.534893 | 3.348564 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/pps_mem.vhd
| 1 | 7,200 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Memory access stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.pack_mips.all;
entity pps_mem is
port
(
clock : in std_logic;
reset : in std_logic;
stop_all : in std_logic; -- Unconditionnal locking of the outputs
clear : in std_logic; -- Clear the pipeline stage
-- Interface with the control bus
MTC_data : out bus32; -- Data to write in memory
MTC_adr : out bus32; -- Address for memory
MTC_r_w : out std_logic; -- Read/Write in memory
MTC_req : out std_logic; -- Request access to memory
CTM_data : in bus32; -- Data from memory
-- Datas from Execution stage
EX_adr : in bus32; -- Instruction address
EX_data_ual : in bus32; -- Result of alu operation
EX_adresse : in bus32; -- Result of the calculation of the address
EX_adr_reg_dest : in adr_reg_type; -- Destination register address for the result
EX_ecr_reg : in std_logic; -- Effective writing of the result
EX_op_mem : in std_logic; -- Memory operation needed
EX_r_w : in std_logic; -- Type of memory operation (read or write)
EX_exc_cause : in bus32; -- Potential exception cause
EX_level : in level_type; -- Availability stage for the result for bypassing
EX_it_ok : in std_logic; -- Allow hardware interruptions
-- Synchronous outputs for bypass unit
MEM_adr : out bus32; -- Instruction address
MEM_adr_reg_dest : out adr_reg_type; -- Destination register address
MEM_ecr_reg : out std_logic; -- Writing of the destination register
MEM_data_ecr : out bus32; -- Data to write (from alu or memory)
MEM_exc_cause : out bus32; -- Potential exception cause
MEM_level : out level_type; -- Availability stage for the result for bypassing
MEM_it_ok : out std_logic -- Allow hardware interruptions
);
end pps_mem;
architecture rtl of pps_mem is
signal tmp_data_ecr : bus32; -- Selection of the data source (memory or alu)
begin
-- Bus controler connexions
MTC_adr <= EX_adresse; -- Connexion of the address
MTC_r_w <= EX_r_w; -- Connexion of R/W
MTC_data <= EX_data_ual; -- Connexion of the data bus
MTC_req <= EX_op_mem and not clear; -- Connexion of the request (if there is no clearing of the pipeline)
-- Preselection of the data source for the outputs
tmp_data_ecr <= CTM_data when EX_op_mem = '1' else EX_data_ual;
-- Set the synchronous outputs
process (clock)
begin
if clock = '1' and clock'event then
if reset = '1' then
MEM_adr <= (others => '0');
MEM_adr_reg_dest <= (others => '0');
MEM_ecr_reg <= '0';
MEM_data_ecr <= (others => '0');
MEM_exc_cause <= IT_NOEXC;
MEM_level <= LVL_DI;
MEM_it_ok <= '0';
elsif stop_all = '0' then
if clear = '1' then -- Clear the stage
MEM_adr <= EX_adr;
MEM_adr_reg_dest <= (others => '0');
MEM_ecr_reg <= '0';
MEM_data_ecr <= (others => '0');
MEM_exc_cause <= IT_NOEXC;
MEM_level <= LVL_DI;
MEM_it_ok <= '0';
else -- Normal evolution
MEM_adr <= EX_adr;
MEM_adr_reg_dest <= EX_adr_reg_dest;
MEM_ecr_reg <= EX_ecr_reg;
MEM_data_ecr <= tmp_data_ecr;
MEM_exc_cause <= EX_exc_cause;
MEM_level <= EX_level;
MEM_it_ok <= EX_it_ok;
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
fc582a8e364b4ea7d018a2b32e8a96da
| 0.406389 | 5.179856 | false | false | false | false |
metaspace/ghdl_extra
|
lfsr4/lfsr4.vhdl
| 1 | 14,905 |
-- file : lfsr4.vhdl
-- parameterised LFSR generator
-- data from http://www.physics.otago.ac.nz/px/research/electronics/papers/technical-reports/lfsr_table.pdf
-- version oct. 8 01:09:20 CEST 2010
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity lfsr4 is
generic(
size : integer := 8
);
port(
clk, reset, din : in std_logic := '0';
lfsr : inout std_ulogic_vector(size downto 1);
init_val : in std_ulogic_vector(size downto 1) := (1=>'1', others=>'0'); -- leave "open" or connect to a constant only
s : out std_logic
);
end lfsr4;
architecture fibonacci of lfsr4 is
constant first_poly : integer := 5;
constant last_poly : integer := 786;
type poly_array_type is array(first_poly to last_poly, 0 to 2) of integer;
constant poly4_array : poly_array_type := (
(4, 3, 2),
(5, 3, 2),
(6, 5, 4),
(6, 5, 4),
(8, 6, 5),
(9, 7, 6),
(10, 9, 7),
(11, 8, 6),
(12, 10, 9),
(13, 11, 9),
(14, 13, 11),
(14, 13, 11),
(16, 15, 14),
(17, 16, 13),
(18, 17, 14),
(19, 16, 14),
(20, 19, 16),
(19, 18, 17),
(22, 20, 18),
(23, 21, 20),
(24, 23, 22),
(25, 24, 20),
(26, 25, 22),
(27, 24, 22),
(28, 27, 25),
(29, 26, 24),
(30, 29, 28),
(30, 26, 25),
(32, 29, 27),
(31, 30, 26),
(34, 28, 27),
(35, 29, 28),
(36, 33, 31),
(37, 33, 32),
(38, 35, 32),
(37, 36, 35),
(40, 39, 38),
(40, 37, 35),
(42, 38, 37),
(42, 39, 38),
(44, 42, 41),
(40, 39, 38),
(46, 43, 42),
(44, 41, 39),
(45, 44, 43),
(48, 47, 46),
(50, 48, 45),
(51, 49, 46),
(52, 51, 47),
(51, 48, 46),
(54, 53, 49),
(54, 52, 49),
(55, 54, 52),
(57, 53, 52),
(57, 55, 52),
(58, 56, 55),
(60, 59, 56),
(59, 57, 56),
(62, 59, 58),
(63, 61, 60),
(64, 62, 61),
(60, 58, 57),
(66, 65, 62),
(67, 63, 61),
(67, 64, 63),
(69, 67, 65),
(70, 68, 66),
(69, 63, 62),
(71, 70, 69),
(71, 70, 67),
(74, 72, 69),
(74, 72, 71),
(75, 72, 71),
(77, 76, 71),
(77, 76, 75),
(78, 76, 71),
(79, 78, 75),
(78, 76, 73),
(81, 79, 76),
(83, 77, 75),
(84, 83, 77),
(84, 81, 80),
(86, 82, 80),
(80, 79, 77),
(86, 84, 83),
(88, 87, 85),
(90, 86, 83),
(90, 87, 86),
(91, 90, 87),
(93, 89, 88),
(94, 90, 88),
(90, 87, 86),
(95, 93, 91),
(97, 91, 90),
(95, 94, 92),
(98, 93, 92),
(100, 95, 94),
(99, 97, 96),
(102, 99, 94),
(103, 94, 93),
(104, 99, 98),
(105, 101, 100),
(105, 99, 98),
(103, 97, 96),
(107, 105, 104),
(109, 106, 104),
(109, 107, 104),
(108, 106, 101),
(111, 110, 108),
(113, 112, 103),
(110, 108, 107),
(114, 111, 110),
(116, 115, 112),
(116, 113, 112),
(116, 111, 110),
(118, 114, 111),
(120, 116, 113),
(121, 120, 116),
(122, 119, 115),
(119, 118, 117),
(120, 119, 118),
(124, 122, 119),
(126, 124, 120),
(127, 126, 121),
(128, 125, 124),
(129, 128, 125),
(129, 128, 123),
(130, 127, 123),
(131, 125, 124),
(133, 129, 127),
(132, 131, 129),
(134, 133, 128),
(136, 133, 126),
(137, 131, 130),
(136, 134, 131),
(139, 136, 132),
(140, 135, 128),
(141, 139, 132),
(141, 140, 138),
(142, 140, 137),
(144, 140, 139),
(144, 143, 141),
(145, 143, 136),
(145, 143, 141),
(142, 140, 139),
(148, 147, 142),
(150, 149, 148),
(150, 149, 146),
(149, 148, 145),
(153, 149, 145),
(151, 150, 148),
(153, 151, 147),
(155, 152, 151),
(153, 152, 150),
(156, 153, 148),
(158, 157, 155),
(159, 158, 155),
(158, 155, 154),
(160, 157, 156),
(159, 158, 152),
(162, 157, 156),
(164, 163, 156),
(165, 163, 161),
(162, 159, 152),
(164, 163, 161),
(169, 166, 161),
(169, 166, 165),
(169, 165, 161),
(171, 168, 165),
(169, 166, 165),
(173, 171, 169),
(167, 165, 164),
(175, 174, 172),
(176, 171, 170),
(178, 177, 175),
(173, 170, 168),
(180, 175, 174),
(181, 176, 174),
(179, 176, 175),
(177, 176, 175),
(184, 182, 177),
(180, 178, 177),
(182, 181, 180),
(186, 183, 182),
(187, 184, 183),
(188, 184, 177),
(187, 185, 184),
(190, 178, 177),
(189, 186, 184),
(192, 191, 190),
(193, 192, 187),
(194, 187, 185),
(195, 193, 188),
(193, 190, 183),
(198, 195, 190),
(198, 197, 195),
(199, 198, 195),
(198, 196, 195),
(202, 196, 195),
(201, 200, 194),
(203, 200, 196),
(201, 197, 196),
(206, 201, 198),
(207, 205, 199),
(207, 206, 204),
(207, 206, 198),
(203, 201, 200),
(209, 208, 205),
(211, 208, 207),
(213, 211, 209),
(212, 210, 209),
(215, 213, 209),
(213, 212, 211),
(217, 211, 210),
(218, 215, 211),
(211, 210, 208),
(219, 215, 213),
(220, 217, 214),
(221, 219, 218),
(222, 217, 212),
(224, 220, 215),
(223, 219, 216),
(223, 218, 217),
(226, 217, 216),
(228, 225, 219),
(224, 223, 222),
(229, 227, 224),
(228, 223, 221),
(232, 229, 224),
(232, 225, 223),
(234, 229, 226),
(229, 228, 226),
(236, 233, 230),
(237, 236, 233),
(238, 232, 227),
(237, 235, 232),
(237, 233, 232),
(241, 236, 231),
(242, 238, 235),
(243, 240, 235),
(244, 241, 239),
(245, 244, 235),
(245, 243, 238),
(238, 234, 233),
(248, 245, 242),
(247, 245, 240),
(249, 247, 244),
(251, 247, 241),
(252, 247, 246),
(253, 252, 247),
(253, 252, 250),
(254, 251, 246),
(255, 251, 250),
(254, 252, 249),
(257, 253, 249),
(253, 252, 250),
(257, 255, 254),
(258, 254, 253),
(261, 258, 252),
(263, 255, 254),
(263, 262, 260),
(265, 260, 259),
(264, 261, 259),
(267, 264, 258),
(268, 263, 262),
(267, 263, 260),
(265, 264, 260),
(270, 266, 263),
(272, 271, 266),
(272, 267, 265),
(266, 265, 264),
(275, 273, 270),
(274, 271, 265),
(277, 274, 273),
(278, 275, 274),
(278, 275, 271),
(280, 277, 272),
(278, 277, 272),
(278, 276, 271),
(279, 278, 276),
(280, 278, 275),
(285, 276, 271),
(285, 282, 281),
(287, 278, 277),
(286, 285, 277),
(288, 287, 285),
(286, 280, 279),
(291, 289, 285),
(292, 287, 282),
(292, 291, 285),
(293, 291, 290),
(292, 287, 285),
(296, 293, 292),
(294, 290, 287),
(295, 293, 288),
(290, 288, 287),
(299, 296, 292),
(297, 293, 290),
(297, 291, 290),
(303, 302, 293),
(303, 299, 298),
(305, 303, 299),
(305, 303, 299),
(306, 299, 293),
(307, 302, 299),
(309, 305, 302),
(308, 306, 304),
(307, 302, 301),
(312, 310, 306),
(311, 305, 300),
(314, 306, 305),
(309, 305, 304),
(315, 313, 310),
(313, 312, 310),
(318, 317, 308),
(319, 317, 316),
(319, 316, 314),
(321, 320, 305),
(322, 320, 313),
(321, 320, 318),
(323, 320, 315),
(325, 323, 316),
(325, 322, 319),
(323, 321, 319),
(326, 323, 321),
(328, 323, 322),
(329, 325, 321),
(325, 321, 320),
(331, 329, 325),
(333, 330, 327),
(333, 328, 325),
(335, 332, 329),
(336, 331, 327),
(336, 335, 332),
(332, 329, 323),
(337, 336, 329),
(336, 330, 327),
(341, 340, 331),
(338, 335, 333),
(338, 334, 333),
(343, 341, 337),
(344, 339, 335),
(344, 337, 336),
(344, 341, 340),
(347, 344, 343),
(340, 337, 336),
(348, 345, 343),
(346, 341, 339),
(349, 346, 344),
(349, 341, 340),
(354, 350, 349),
(349, 347, 346),
(355, 347, 346),
(351, 350, 344),
(358, 352, 350),
(359, 335, 334),
(360, 357, 354),
(360, 351, 344),
(362, 356, 355),
(363, 359, 352),
(360, 359, 356),
(362, 359, 352),
(365, 363, 358),
(361, 359, 351),
(367, 359, 358),
(368, 367, 365),
(369, 368, 363),
(369, 365, 357),
(371, 366, 365),
(369, 368, 366),
(374, 368, 367),
(371, 369, 368),
(376, 374, 369),
(374, 365, 363),
(375, 370, 369),
(377, 374, 366),
(380, 379, 376),
(379, 375, 364),
(382, 378, 374),
(378, 369, 368),
(383, 381, 379),
(381, 380, 376),
(385, 379, 378),
(387, 385, 374),
(384, 380, 379),
(388, 380, 377),
(390, 389, 385),
(386, 382, 379),
(392, 391, 386),
(392, 387, 386),
(390, 389, 384),
(392, 390, 389),
(392, 387, 385),
(393, 392, 384),
(397, 390, 388),
(398, 397, 395),
(399, 392, 389),
(399, 398, 393),
(398, 395, 394),
(400, 398, 397),
(398, 397, 388),
(402, 397, 393),
(402, 400, 398),
(407, 403, 401),
(406, 404, 402),
(407, 406, 400),
(408, 401, 399),
(409, 404, 401),
(407, 406, 403),
(405, 401, 398),
(413, 411, 406),
(414, 411, 407),
(416, 414, 407),
(417, 415, 403),
(415, 414, 404),
(412, 410, 407),
(419, 417, 416),
(421, 416, 412),
(420, 418, 414),
(422, 417, 415),
(422, 421, 418),
(415, 414, 412),
(422, 421, 416),
(426, 425, 417),
(422, 421, 419),
(419, 417, 415),
(430, 428, 426),
(429, 428, 419),
(430, 428, 422),
(429, 423, 422),
(430, 426, 423),
(432, 431, 430),
(436, 435, 431),
(436, 432, 421),
(437, 436, 431),
(439, 437, 436),
(440, 433, 430),
(440, 437, 435),
(442, 437, 433),
(435, 432, 431),
(441, 439, 438),
(442, 439, 431),
(446, 441, 438),
(444, 442, 437),
(446, 440, 438),
(443, 438, 434),
(450, 441, 435),
(448, 447, 446),
(449, 447, 438),
(449, 445, 444),
(453, 449, 444),
(454, 445, 433),
(454, 449, 446),
(453, 448, 445),
(457, 454, 447),
(459, 455, 451),
(460, 455, 454),
(457, 451, 450),
(456, 455, 452),
(460, 455, 441),
(463, 462, 457),
(460, 455, 452),
(466, 461, 456),
(464, 459, 453),
(467, 464, 460),
(468, 462, 461),
(469, 468, 465),
(470, 469, 461),
(470, 467, 465),
(465, 463, 456),
(471, 467, 466),
(475, 468, 466),
(470, 462, 461),
(477, 474, 472),
(475, 472, 470),
(473, 467, 464),
(480, 472, 471),
(477, 476, 473),
(479, 477, 474),
(483, 482, 470),
(479, 469, 468),
(481, 478, 472),
(485, 483, 478),
(487, 485, 484),
(484, 483, 480),
(485, 483, 481),
(488, 485, 480),
(491, 485, 484),
(490, 488, 483),
(493, 489, 481),
(494, 486, 480),
(494, 491, 480),
(493, 488, 486),
(495, 489, 487),
(494, 493, 488),
(499, 494, 490),
(499, 497, 496),
(498, 497, 494),
(502, 501, 500),
(502, 490, 483),
(500, 497, 493),
(501, 494, 491),
(504, 501, 494),
(505, 500, 495),
(506, 502, 501),
(501, 500, 498),
(509, 503, 501),
(510, 507, 504),
(505, 503, 500),
(511, 509, 507),
(511, 508, 501),
(514, 511, 509),
(515, 507, 505),
(516, 515, 507),
(517, 511, 507),
(509, 507, 503),
(519, 514, 512),
(518, 509, 507),
(521, 517, 510),
(523, 519, 515),
(524, 521, 519),
(525, 521, 517),
(526, 520, 518),
(526, 522, 517),
(528, 525, 522),
(527, 523, 520),
(529, 525, 519),
(529, 528, 522),
(531, 530, 529),
(533, 529, 527),
(533, 529, 527),
(533, 531, 529),
(536, 535, 527),
(537, 536, 533),
(535, 534, 529),
(537, 534, 529),
(537, 531, 528),
(540, 539, 533),
(538, 536, 532),
(538, 535, 531),
(539, 537, 532),
(545, 544, 538),
(543, 540, 534),
(545, 543, 538),
(546, 545, 533),
(546, 533, 529),
(550, 547, 542),
(550, 547, 532),
(550, 549, 542),
(551, 546, 543),
(551, 546, 545),
(549, 546, 540),
(552, 551, 550),
(553, 549, 544),
(557, 552, 550),
(554, 551, 549),
(558, 552, 550),
(560, 558, 551),
(561, 554, 549),
(563, 561, 558),
(564, 559, 554),
(564, 561, 560),
(563, 557, 556),
(558, 557, 551),
(568, 559, 557),
(563, 558, 552),
(569, 566, 561),
(571, 564, 560),
(569, 567, 563),
(569, 565, 560),
(572, 570, 569),
(573, 572, 563),
(575, 574, 569),
(562, 556, 555),
(572, 570, 567),
(579, 576, 574),
(575, 574, 568),
(579, 576, 571),
(581, 577, 575),
(581, 571, 570),
(583, 582, 577),
(584, 581, 579),
(586, 581, 576),
(577, 572, 571),
(586, 585, 579),
(588, 587, 578),
(587, 585, 582),
(591, 573, 568),
(588, 585, 584),
(586, 584, 583),
(594, 593, 586),
(592, 591, 590),
(588, 585, 583),
(597, 592, 591),
(593, 591, 590),
(599, 590, 589),
(600, 597, 589),
(596, 594, 591),
(600, 599, 597),
(600, 598, 589),
(600, 598, 595),
(602, 599, 591),
(600, 598, 595),
(606, 602, 585),
(601, 600, 597),
(602, 600, 599),
(609, 607, 601),
(607, 602, 598),
(609, 603, 594),
(613, 612, 607),
(614, 609, 608),
(614, 602, 597),
(612, 608, 607),
(615, 604, 598),
(614, 611, 610),
(619, 618, 611),
(616, 615, 609),
(612, 610, 605),
(614, 613, 612),
(617, 615, 612),
(620, 617, 613),
(623, 621, 613),
(622, 617, 613),
(626, 617, 616),
(627, 624, 623),
(628, 626, 623),
(625, 623, 617),
(629, 619, 613),
(632, 631, 626),
(631, 629, 627),
(631, 625, 621),
(632, 628, 623),
(636, 628, 623),
(637, 633, 632),
(636, 635, 629),
(638, 637, 626),
(640, 636, 622),
(636, 633, 632),
(641, 640, 632),
(634, 633, 632),
(641, 637, 634),
(635, 634, 633),
(646, 643, 642),
(647, 626, 625),
(648, 644, 638),
(644, 635, 632),
(646, 638, 637),
(647, 643, 641),
(646, 645, 643),
(649, 643, 640),
(653, 639, 638),
(646, 638, 637),
(656, 650, 649),
(651, 648, 646),
(657, 655, 644),
(657, 656, 648),
(657, 650, 649),
(659, 656, 650),
(655, 652, 649),
(662, 660, 649),
(661, 659, 654),
(664, 659, 656),
(664, 660, 649),
(658, 656, 651),
(667, 665, 664),
(669, 665, 664),
(669, 665, 662),
(667, 666, 661),
(666, 664, 663),
(671, 665, 660),
(674, 672, 669),
(675, 671, 664),
(674, 673, 669),
(675, 673, 663),
(676, 667, 661),
(679, 650, 645),
(678, 672, 670),
(681, 679, 675),
(682, 677, 672),
(681, 671, 666),
(684, 682, 681),
(684, 674, 673),
(682, 675, 673),
(682, 674, 669),
(686, 683, 681),
(687, 683, 680),
(689, 685, 678),
(687, 686, 678),
(691, 685, 678),
(691, 681, 677),
(694, 691, 686),
(694, 686, 673),
(689, 685, 681),
(690, 689, 688),
(698, 689, 684),
(698, 695, 694),
(699, 697, 685),
(701, 699, 695),
(702, 696, 691),
(701, 699, 692),
(704, 698, 697),
(697, 695, 692),
(702, 699, 692),
(706, 704, 703),
(708, 706, 705),
(709, 696, 695),
(704, 703, 700),
(709, 708, 707),
(706, 703, 696),
(709, 707, 701),
(714, 711, 708),
(706, 705, 704),
(716, 710, 701),
(717, 716, 713),
(711, 710, 707),
(718, 712, 709),
(720, 713, 712),
(721, 718, 707),
(717, 710, 707),
(719, 716, 711),
(720, 719, 716),
(725, 722, 721),
(721, 719, 716),
(726, 725, 724),
(726, 724, 718),
(726, 715, 711),
(729, 725, 723),
(729, 728, 725),
(731, 726, 725),
(724, 721, 720),
(733, 728, 727),
(730, 728, 723),
(736, 733, 732),
(730, 729, 727),
(731, 723, 721),
(737, 728, 716),
(738, 733, 732),
(741, 738, 730),
(742, 731, 730),
(743, 733, 731),
(740, 738, 737),
(738, 733, 728),
(743, 741, 737),
(744, 743, 733),
(748, 743, 742),
(746, 741, 734),
(750, 748, 740),
(749, 732, 731),
(748, 745, 740),
(742, 740, 735),
(754, 745, 743),
(755, 747, 740),
(756, 751, 750),
(757, 746, 741),
(757, 756, 750),
(757, 747, 734),
(760, 759, 758),
(761, 755, 745),
(754, 749, 747),
(761, 759, 758),
(760, 755, 754),
(757, 747, 744),
(763, 760, 759),
(764, 751, 749),
(763, 762, 760),
(768, 765, 756),
(765, 756, 754),
(767, 766, 764),
(767, 765, 763),
(767, 760, 758),
(771, 769, 768),
(773, 764, 759),
(776, 767, 761),
(775, 762, 759),
(776, 771, 769),
(775, 772, 764),
(779, 765, 764),
(780, 779, 773),
(782, 776, 773),
(778, 775, 771),
(780, 776, 775),
(782, 780, 771));
begin
process (clk, reset)
begin
if reset = '1' then
lfsr <= init_val;
else
if rising_edge(clk) then
lfsr(1) <= lfsr(size)
xor lfsr(poly4_array(size,0))
xor lfsr(poly4_array(size,1))
xor lfsr(poly4_array(size,2))
xor din;
lfsr(size downto 2) <= lfsr(size-1 downto 1);
end if;
end if;
end process;
s <= lfsr(1);
end fibonacci;
|
gpl-3.0
|
0c375e1e99d89031f63680cea55a6f49
| 0.53586 | 2.192557 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
mdio_ctrl.vhd
| 1 | 5,913 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Theory of operation:
-- 1. set input values
-- 2. wait for busy to go '0'
-- 3. set kick to '1'
-- 4. wait for busy to go '0'; for reads data_o is valid on the same clock; for writes MDIO is done
entity mdio_ctrl is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- counter bits
cnt_5 : in STD_LOGIC;
cnt_23 : in STD_LOGIC;
-- external I/O
mdc : out STD_LOGIC;
mdio_i : in STD_LOGIC;
mdio_o : out STD_LOGIC;
mdio_t : out STD_LOGIC;
-- client interface
op : in STD_LOGIC; -- '0' - read; '1' - write
addr : in STD_LOGIC_VECTOR( 4 downto 0); -- address of register
data_i : in STD_LOGIC_VECTOR(15 downto 0); -- register value for write
data_o : out STD_LOGIC_VECTOR(15 downto 0); -- register value for read
busy : out STD_LOGIC; -- core is busy
kick : in STD_LOGIC -- start processing the operation
);
end mdio_ctrl;
architecture Behavioral of mdio_ctrl is
-- MDC is driven by cnt5 (period: 640ns, edge: 320ns | min: 400/180ns)
-- state changes happen on MDC falling edge
-- Operation:
-- 1. after each reset wait for at least 50ms (we wait at least 84ms - cnt_23)
-- 2. wait for command -> kick to go high
type state_t is (wait_rst_done_b1, -- wait for cnt_23 to go high
wait_rst_done_b0, -- wait for cnt_23 to go low
idle, -- do nothing, wait for command
preable, -- preable -> 32x '1'
start_of_frame, -- sof -> 0 1
op_code, -- opcode -> 1 0 read; 0 1 write
phy_addr, -- phy_addr -> 5x 0
reg_addr, -- reg_addr -> 5x b
turn_around,
read_in,
write_out);
signal state, next_state : state_t := wait_rst_done_b1;
signal cnt, next_cnt : integer range 0 to 31;
signal value, next_value : STD_LOGIC_VECTOR(0 to 15);
-- 'mdio_i' value latched on rising edge of MDC
-- (state transitions on falling edge which is too far - PHY holds value for 300ns only)
signal bit_in : STD_LOGIC;
-- detection of falling edge of MDC
signal MDIO_clk, prev_MDIO_clk : STD_LOGIC := '0';
-- latched inputs
signal m_op : STD_LOGIC;
signal m_addr : STD_LOGIC_VECTOR(0 to 4); -- swap direction here to make it easier
signal m_data : STD_LOGIC_VECTOR(0 to 15); -- to iterate over the vector with cnt
signal m_kick : STD_LOGIC;
begin
busy <= '0' when state = idle and m_kick = '0' else '1';
data_o <= value;
-- Async state machine
NEXT_fsm: process (next_state, state, next_cnt, cnt, mdio_i, cnt_23, value, bit_in,
m_kick, m_op, m_addr, m_data)
begin
mdio_o <= '0';
mdio_t <= '0';
next_state <= state;
next_cnt <= cnt + 1;
next_value <= value;
case state is
when wait_rst_done_b1 =>
if cnt_23 = '1' then
next_state <= wait_rst_done_b0;
end if;
when wait_rst_done_b0 =>
if cnt_23 = '0' then
next_state <= idle;
end if;
when idle =>
if m_kick = '1' then
next_state <= preable;
next_cnt <= 0;
end if;
when preable =>
if cnt = 31 then
next_state <= start_of_frame;
next_cnt <= 0;
end if;
mdio_o <= '1';
when start_of_frame =>
mdio_o <= CONV_std_logic_vector(cnt, 1)(0);
if CONV_std_logic_vector(cnt, 1)(0) = '1' then
next_state <= op_code;
next_cnt <= 0;
end if;
when op_code =>
mdio_o <= not m_op xor CONV_std_logic_vector(cnt, 1)(0);
if CONV_std_logic_vector(cnt, 1)(0) = '1' then
next_state <= phy_addr;
next_cnt <= 0;
end if;
when phy_addr =>
mdio_o <= '0';
if cnt = 4 then
next_state <= reg_addr;
next_cnt <= 0;
end if;
when reg_addr =>
mdio_o <= m_addr(cnt);
if cnt = 4 then
next_state <= turn_around;
next_cnt <= 0;
end if;
when turn_around =>
mdio_o <= 'Z';
mdio_t <= '1';
if CONV_std_logic_vector(cnt, 1)(0) = '1' then
if m_op = '0' then
next_state <= read_in;
else
next_state <= write_out;
end if;
next_cnt <= 0;
end if;
when read_in =>
mdio_o <= 'Z';
mdio_t <= '1';
next_value(cnt) <= bit_in;
if cnt = 15 then
next_state <= idle;
end if;
when write_out =>
mdio_o <= m_data(cnt);
if cnt = 15 then
next_state <= idle;
end if;
end case;
end process;
fsm: process (clk)
begin
if RISING_EDGE(clk) then
if state = idle and kick = '1' then
m_op <= op;
m_addr <= addr;
m_data <= data_i;
m_kick <= '1';
end if;
if MDIO_clk = '0' and prev_MDIO_clk = '1' then
state <= next_state;
cnt <= next_cnt;
value <= next_value;
m_kick <= '0';
end if;
if MDIO_clk = '1' and prev_MDIO_clk = '0' then
bit_in <= mdio_i;
end if;
if rst = '1' then
state <= wait_rst_done_b1;
cnt <= 0;
end if;
end if;
end process;
-- Genearate clock
MDIO_clk <= cnt_5;
prev_MDIO_clk <= cnt_5 when RISING_EDGE(clk);
mdc <= MDIO_clk;
end Behavioral;
|
gpl-3.0
|
d66b31705fab5c3be228dbc3abf75975
| 0.575512 | 2.868996 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/alu.vhd
| 1 | 9,981 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Arithmetical and logical unit --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity alu is
port
(
clock : in bus1;
reset : in bus1;
op1 : in bus32; -- Operand 1
op2 : in bus32; -- Operand 2
ctrl : in alu_ctrl_type; -- Opearator control
res : out bus32; -- The result is 32 bit long
overflow : out bus1 -- Overflow of the result
);
end alu;
architecture rtl of alu is
-- Signals to pre-process the operands
signal efct_op1, efct_op2 : bus33; -- Effective operands of the adder (33 bits)
signal comp_op2 : bus1; -- Select the opposite of operand 2
signal igno_op2 : bus1; -- Ignore op 2 (put zeros)
signal sign_op1 : bus1; -- High bit of op 1
signal sign_op2 : bus1; -- High bit of op 2
signal signe : bus1; -- Signed operation (bit sign extension)
signal shift_val : natural range 0 to 31; -- Value of the shift
-- Signals for internal results
signal res_shl, res_shr : bus32; -- Results of left and right shifter
signal res_lui : bus32; -- Result of Load Upper Immediate
signal res_add : bus33; -- Result of the adder
signal carry : bus33; -- Carry for the adder
signal nul : bus1; -- Check if the adder result is zero
signal hilo : bus64; -- Internal registers to store the multiplication operation
signal tmp_hilo : bus64; -- Internal registers to store the multiplication operation (synchronised)
begin
-- Process if the operation is signed compliant
signe <= '1' when (ctrl=OP_ADD or ctrl=OP_SUB or ctrl=OP_SLT or ctrl=OP_SNEG or ctrl=OP_SPOS or ctrl=OP_LNEG or ctrl=OP_LPOS)
else
'0';
sign_op1 <= signe and op1(31);
sign_op2 <= signe and op2(31);
-- Selection of the value of the second operand : op2 or -op2 (ie not op2 + 1)
comp_op2 <= '1' when -- The opposite of op2 is used
(ctrl=OP_SUB or ctrl=OP_SUBU) -- Opposite of the operand 2 to obtain a substraction
or (ctrl=OP_SLT or ctrl=OP_SLTU) -- Process the difference to check the lesser than operation for the operands
or (ctrl=OP_EQU or ctrl=OP_NEQU) -- Process the difference to check the equality of the operands
else
'0'; -- by default, op2 is used
igno_op2 <= '1' when -- Op 2 will be zero (when comp_op2='0')
(ctrl=OP_SPOS or ctrl=OP_LNEG) -- Process if the op1 is nul with op1+0
else
'0';
-- Effective signals for the adder
efct_op2 <= not (sign_op2 & op2) when (comp_op2='1') else -- We take the opposite of op2 to get -op2 (we will add 1 with the carry)
(others => '0') when (igno_op2='1') else -- Op2 is zero
(sign_op2 & op2); -- by default we use op2 (33 bits long)
efct_op1 <= sign_op1 & op1;
-- Execution of the addition
carry <= X"00000000" & comp_op2; -- Carry to one when -op2 is needed
res_add <= std_logic_vector(unsigned(efct_op1) + unsigned(efct_op2) + unsigned(carry));
nul <= '1' when (res_add(31 downto 0)=X"00000000") else '0'; -- Check the nullity of the result
-- Value of the shift for the programmable shifter
shift_val <= to_integer(unsigned(op1(4 downto 0)));
res_shl <= bus32(shift_left(unsigned(op2), shift_val));
res_shr <= not bus32(shift_right(unsigned(not op2) , shift_val)) when (ctrl=OP_SRA and op2(31)='1') else
bus32(shift_right(unsigned(op2), shift_val));
res_lui <= op2(15 downto 0) & X"0000";
-- Affectation of the hilo register if necessary
tmp_hilo <= std_logic_vector(signed(op1)*signed(op2)) when (ctrl=OP_MULT) else
std_logic_vector(unsigned(op1)*unsigned(op2)) when (ctrl=OP_MULTU) else
op1 & hilo(31 downto 0) when (ctrl=OP_MTHI) else
hilo(63 downto 32) & op1 when (ctrl=OP_MTLO) else
(others => '0');
-- Check the overflows
overflow <= '1' when ((ctrl=OP_ADD and op1(31)=efct_op2(31) and op1(31)/=res_add(31))
or (ctrl=OP_SUB and op1(31)/=op2(31) and op1(31)/=res_add(31))) else
'0'; -- Only ADD and SUB can overflow
-- Result affectation
res <=
-- Arithmetical operations
res_add(31 downto 0) when (ctrl=OP_ADD or ctrl=OP_ADDU or ctrl=OP_SUB or ctrl=OP_SUBU) else
-- Logical operations
op1 and op2 when (ctrl=OP_AND) else
op1 or op2 when (ctrl=OP_OR) else
op1 nor op2 when (ctrl=OP_NOR) else
op1 xor op2 when (ctrl=OP_XOR) else
-- Different tests : the result is one when the test is succesful
(0 => res_add(32), others=>'0') when (ctrl=OP_SLTU or ctrl=OP_SLT) else
(0 => nul, others=>'0') when (ctrl=OP_EQU) else
(0 => not nul, others=>'0') when (ctrl=OP_NEQU) else
(0 => op1(31), others=>'0') when (ctrl=OP_SNEG) else
(0 => not (op1(31) or nul), others=>'0') when (ctrl=OP_SPOS) else
(0 => (op1(31) or nul), others=>'0') when (ctrl=OP_LNEG) else
(0 => not op1(31), others=>'0') when (ctrl=OP_LPOS) else
-- Shifts
res_shl when (ctrl=OP_SLL) else
res_shr when (ctrl=OP_SRL or ctrl=OP_SRA) else
res_lui when (ctrl=OP_LUI) else
-- Internal registers
hilo(63 downto 32) when (ctrl=OP_MFHI) else
hilo(31 downto 0) when (ctrl=OP_MFLO or ctrl=OP_MULT or ctrl=OP_MULTU) else
op1 when (ctrl=OP_MTHI or ctrl=OP_MTLO) else
op2 when (ctrl=OP_OP2) else
-- Always true
X"00000001" when (ctrl=OP_OUI) else
-- Unknown operation or nul result desired
(others => '0');
-- Save the hilo register
process (clock)
begin
if clock = '1' and clock'event then
if reset = '1' then
hilo <= (others => '0');
elsif (ctrl = OP_MULT) or (ctrl = OP_MULTU) or (ctrl = OP_MTLO) or (ctrl = OP_MTHI) then
hilo <= tmp_hilo;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
9d2096341e1873828c8a4e060275d4ab
| 0.446849 | 4.510167 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sources_1/new/sensor_gate.vhd
| 1 | 1,720 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.11.2017 10:57:34
-- Design Name:
-- Module Name: sensor_gate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity sensor_gate is
Port(clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sensor_ready : in STD_LOGIC;
sensor_in : in sensor;
outbus_free : in STD_LOGIC;
sensor_out : out sensor_vector;
sensor_data_ready : out std_logic
);
end sensor_gate;
architecture Behavioral of sensor_gate is
begin
convert : process(clk) is
begin
if rising_edge(clk) then
if resetn = '0' then
sensor_out <= (others => 'Z');
sensor_data_ready <= 'Z';
else
sensor_out <= (others => 'Z');
sensor_data_ready <= 'Z';
if (sensor_ready = '1') then
if outbus_free = '1' then
sensor_out <= sensor2vector(sensor_in);
sensor_data_ready <= '1';
end if;
end if;
end if;
end if;
end process convert;
end Behavioral;
|
gpl-3.0
|
03eeaa01099e25707d4537cc9be78b49
| 0.55814 | 3.651805 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Decimator/FIR.vhd
| 1 | 1,805 |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fixed_pkg.all;
use work.filter_pkg.all;
entity FIR is
generic (
wordLength : natural := 16;
order : natural := 3;
coefficients : coefficient_array := (0.0, 0.0, 0.0, 0.0)
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
);
end entity ; -- FIR
architecture arch of FIR is
type signalArray is array(0 to order) of std_logic_vector(wordLength-1 downto 0);
type sumArray is array(0 to order) of std_logic_vector((wordLength*2)-1 downto 0);
signal inputs : signalArray := (others => (others => '0'));
signal gainedInputs : sumArray := (others => (others => '0'));
signal sums : sumArray := (others => (others => '0'));
begin
inputs(0) <= input;
output <= sums(0)(wordLength*2-1 downto wordLength);
sums(order) <= gainedInputs(order);
delays : for i in 0 to order-1 generate
-- Delay stages
delay : entity work.VectorRegister
generic map (
wordLength => wordLength
)
port map (
input => inputs(i),
output => inputs(i+1),
clk => clk,
reset => reset
);
-- Output summation
adder : entity work.AdderSat
generic map (
wordLength => wordLength*2
)
port map (
a => gainedInputs(i),
b => sums(i+1),
s => sums(i)
);
end generate ; -- delays
multiplication : for i in 0 to order generate
-- Coefficient multiplication
mult : entity work.Mult
generic map (
wordLengthA => wordLength,
wordLengthB => wordLength,
wordLengthP => wordLength*2
)
port map (
a => inputs(i),
b => real_to_fixed(coefficients(i), wordLength),
p => gainedInputs(i)
);
end generate;
end architecture ; -- arch
|
mit
|
870d34e89e6284b16a3b28a61ffcabb4
| 0.644321 | 3.12825 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/ddr3k7-core/ddr3_ctrl_pkg.vhd
| 1 | 8,282 |
--==============================================================================
--! @file ddr3_ctrl_pkg.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- DDR3 Controller Package
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! DDR3 controller package
--------------------------------------------------------------------------------
--! @details
--! Contains DDR3 controller core top level component declaration.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 12.08.2011 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Entity declaration for ddr3_ctrl_pkg
--==============================================================================
package ddr3_ctrl_pkg is
--==============================================================================
--! Functions declaration
--==============================================================================
function f_qword_swap_256 (
constant enable : boolean;
signal din : std_logic_vector(255 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function f_qword_swap_512 (
constant enable : boolean;
signal din : std_logic_vector(511 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector;
--==============================================================================
--! Components declaration
--==============================================================================
COMPONENT fifo_315x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(604 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(604 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_27x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(29-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(29-1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_4x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(37-1 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(37-1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_256x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
component qword_swap_512 is
Port ( qword_swap : in STD_LOGIC_VECTOR (2 downto 0);
din : in STD_LOGIC_VECTOR (511 downto 0);
dout : out STD_LOGIC_VECTOR (511 downto 0));
end component;
component byte_swap_64 is
Port ( qword_swap : in STD_LOGIC_VECTOR (2 downto 0);
din : in STD_LOGIC_VECTOR (63 downto 0);
dout : out STD_LOGIC_VECTOR (63 downto 0));
end component;
end ddr3_ctrl_pkg;
package body ddr3_ctrl_pkg is
-----------------------------------------------------------------------------
-- QWORD swap function
--
-- enable | byte_swap | din | dout
-- false | XX | ABCD | ABCD
-- true | 00 | ABCD | ABCD
-- true | 01 | ABCD | BADC
-- true | 10 | ABCD | CDAB
-- true | 11 | ABCD | DCBA
-----------------------------------------------------------------------------
function f_qword_swap_256 (
constant enable : boolean;
signal din : std_logic_vector(255 downto 0);
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(255 downto 0);
begin
if (enable = true) then
case byte_swap is
when "00" =>
dout := din;
when "01" =>
dout := din(191 downto 128)
& din(255 downto 192)
& din(63 downto 0)
& din(127 downto 64);
when "10" =>
dout := din(127 downto 0)
& din(255 downto 128);
when "11" =>
dout := din(63 downto 0)
& din(127 downto 64)
& din(191 downto 128)
& din(255 downto 192);
when others =>
dout := din;
end case;
else
dout := din;
end if;
return dout;
end function f_qword_swap_256;
-----------------------------------------------------------------------------
-- QWORD swap function
--
-- enable | byte_swap | din | dout
-- false | XXX | ABCDEFGH | ABCDEFGH
-- true | 000 | ABCDEFGH | ABCDEFGH
-- true | 001 | ABCDEFGH | BADCFEHG
-- true | 010 | ABCDEFGH | CDABGHEF
-- true | 011 | ABCDEFGH | DCBAHGFE
-- true | 100 | ABCDEFGH | EFGHABCD
-- true | 101 | ABCDEFGH | FEHGBADC
-- true | 110 | ABCDEFGH | GHEFCDAB
-- true | 111 | ABCDEFGH | HGFEDCBA
-----------------------------------------------------------------------------
function f_qword_swap_512 (
constant enable : boolean;
signal din : std_logic_vector(511 downto 0);
signal byte_swap : std_logic_vector(2 downto 0))
return std_logic_vector is
variable dout : std_logic_vector(511 downto 0);
begin
if (enable = true) then
if byte_swap(2) = '0' then
dout := f_qword_swap_256(true, din(511 downto 256), byte_swap(1 downto 0)) & f_qword_swap_256(true, din(255 downto 0), byte_swap(1 downto 0));
else
dout := f_qword_swap_256(true, din(255 downto 0), byte_swap(1 downto 0)) & f_qword_swap_256(true, din(511 downto 256), byte_swap(1 downto 0));
end if;
else
dout := din;
end if;
return dout;
end function f_qword_swap_512;
end ddr3_ctrl_pkg;
|
gpl-3.0
|
ea4100bf452d1deb155e675a44c9ff4b
| 0.449891 | 4.553051 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/la-S3ESK.vhd
| 2 | 5,544 |
----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependend IO modules and defines all inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity la is
Port(
resetSwitch : in std_logic;
xtalClock : in std_logic;
exClock : in std_logic;
input : in std_logic_vector(31 downto 0);
rx : in std_logic;
tx : inout std_logic;
led : OUT std_logic_vector(7 downto 0);
switch : in std_logic_vector(1 downto 0)
);
end la;
architecture Behavioral of la is
component debounce IS
GENERIC(
counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END component ;
COMPONENT clockman
PORT(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
END COMPONENT;
COMPONENT eia232
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
PORT(
clock : IN std_logic;
reset : in std_logic;
speed : IN std_logic_vector(1 downto 0);
rx : IN std_logic;
data : IN std_logic_vector(31 downto 0);
send : IN std_logic;
tx : OUT std_logic;
cmd : OUT std_logic_vector(39 downto 0);
execute : OUT std_logic;
busy : OUT std_logic
);
END COMPONENT;
COMPONENT core
PORT(
clock : IN std_logic;
extReset : IN std_logic;
cmd : IN std_logic_vector(39 downto 0);
execute : IN std_logic;
input : IN std_logic_vector(31 downto 0);
inputClock : IN std_logic;
sampleReady50 : OUT std_logic;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : IN std_logic_vector(31 downto 0);
memoryOut : OUT std_logic_vector(31 downto 0);
memoryRead : OUT std_logic;
memoryWrite : OUT std_logic
);
END COMPONENT;
COMPONENT sram_bram
PORT(
clock : IN std_logic;
input : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0);
read : IN std_logic;
write : IN std_logic
);
END COMPONENT;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (31 downto 0);
signal probeInput : std_logic_vector (31 downto 0);
signal output : std_logic_vector (31 downto 0);
signal clock : std_logic;
signal read, write, execute, send, busy : std_logic;
signal test_counter : std_logic_vector (40 downto 0);
signal rst_dbc : std_logic;
constant FREQ : integer := 100000000; -- limited to 100M by onboard SRAM
constant TRXSCALE : integer := 28; -- 100M / 28 / 115200 = 31 (5bit)
constant RATE : integer := 115200; -- maximum & base rate
begin
led(7 downto 0) <= exClock & resetSwitch & "0" & switch & "0" & rx & tx; --& "000";
-- test counter
process(clock)
begin
if rising_edge(clock) then
test_counter <= test_counter + 1;
end if;
end process;
--probeInput <= input;
probeInput <= test_counter(40 downto 9); -- use this to connect a counter to the inputs
Inst_clockman: clockman PORT MAP(
clkin => xtalClock,
clk0 => clock
);
inst_debounce: debounce
generic map (
counter_size => 19
)
port map (
clk => clock,
button => resetswitch,
result => rst_dbc
);
Inst_eia232: eia232
generic map (
FREQ => FREQ,
SCALE => TRXSCALE,
RATE => RATE
)
PORT MAP(
clock => clock,
--reset => resetSwitch,
reset => rst_dbc,
speed => switch,
rx => rx,
tx => tx,
cmd => cmd,
execute => execute,
data => output,
send => send,
busy => busy
);
Inst_core: core PORT MAP(
clock => clock,
--extReset => resetSwitch,
extReset => rst_dbc,
cmd => cmd,
execute => execute,
input => probeInput,
inputClock => exClock,
--sampleReady50 => ready50,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write
);
Inst_sram: sram_bram PORT MAP(
clock => clock,
input => memoryOut,
output => memoryIn,
read => read,
write => write
);
end Behavioral;
|
gpl-2.0
|
a2cf92b55e67cb86d40f838ad64e2772
| 0.637266 | 3.458515 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Decimator/Decimator.vhd
| 1 | 4,322 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity Decimator is
generic(wordLength : natural := 16);
port (
clk: in std_logic;
reset: in std_logic;
input: in std_logic_vector(wordLength-1 downto 0);
output: out std_logic_vector(wordLength-1 downto 0)
);
end entity ; -- Decimator
architecture arch of Decimator is
signal out_stage1: std_logic_vector(wordLength-1 downto 0);
signal out_stage2: std_logic_vector(wordLength-1 downto 0);
signal out_stage3: std_logic_vector(wordLength-1 downto 0);
signal out_stage4: std_logic_vector(wordLength-1 downto 0);
signal fir1_out : std_logic_vector(wordLength-1 downto 0);
signal fir2_out : std_logic_vector(wordLength-1 downto 0);
signal fir3_out : std_logic_vector(wordLength-1 downto 0);
signal fir4_out : std_logic_vector(wordLength-1 downto 0);
signal clk1: std_logic;
signal clk2: std_logic;
signal clk3: std_logic;
signal clk4: std_logic;
signal clk5: std_logic;
begin
clk_1:entity work.ClockDivider
generic map(divider => 71) -- 50M/(44100*2^4)=70.861
port map(
reset => reset,
clk => clk,
clkOut=>clk1 --(44100*2^4)
);
--Stage 1
fiter_1:entity work.FIR
generic map( wordLength=>wordLength,
order => 6,
coefficients => (
-0.03173828125,
0.0,
0.28173828125,
0.5,
0.28173828125,
0.0,
-0.03173828125
)
)
port map(
input=> input,
output=> fir1_out,
clk => clk1, --(44100*2^4)
reset => reset
);
clk_2:entity work.ClockDivider
generic map(divider => 2)
port map(
reset => reset,
clk => clk1, -- (44100*2^4)
clkOut=>clk2 -- (44100*2^3)
);
downsampler1:entity work.VectorRegister
generic map(wordLength => 16)
port map(
input=> fir1_out,
output=> out_stage1,
clk=>clk2, --(44100*2^3)
reset=> reset
);
--Stage 2
fiter_2:entity work.FIR
generic map( wordLength=>wordLength,
order => 6,
coefficients => (
-0.033203125,
0.0,
0.28271484375,
0.5,
0.28271484375,
0.0,
-0.033203125
)
)
port map(
input=> out_stage1,
output=> fir2_out,
clk => clk2, -- (44100*2^3)
reset => reset
);
clk_3:entity work.ClockDivider
generic map(divider => 2)
port map(
reset => reset,
clk => clk2, --(44100*2^3)
clkOut=>clk3 --(44100*2^2)
);
downsampler2:entity work.VectorRegister
generic map(wordLength => 16)
port map(
input=> fir2_out,
output=> out_stage2,
clk=>clk3, --(44100*2^2)
reset=> reset
);
--Stage 3
fiter_3:entity work.FIR
generic map( wordLength=>wordLength,
order => 6,
coefficients => (
-0.0390625,
0.0,
0.28759765625,
0.5,
0.28759765625,
0.0,
-0.0390625
)
)
port map(
input=> out_stage2,
output=> fir3_out,
clk => clk3, --(44100*2^2)
reset => reset
);
clk_4:entity work.ClockDivider
generic map(divider => 2)
port map(
reset => reset,
clk => clk3, --(44100*2^2)
clkOut=>clk4 --(44100*2^1)
);
downsampler3:entity work.VectorRegister
generic map(wordLength => 16)
port map(
input=> fir3_out,
output=> out_stage3,
clk=>clk4, --(44100*2^1)
reset=> reset
);
--Stage 4
fiter_4:entity work.FIR
generic map( wordLength=>wordLength,
order => 14,
coefficients => (
-0.01025390625,
0.0,
0.03173828125,
0.0,
-0.083984375,
0.0,
0.31005859375,
0.5,
0.31005859375,
0.0,
-0.083984375,
0.0,
0.03173828125,
0.0,
-0.01025390625
)
)
port map(
input=> out_stage3,
output=> fir4_out,
clk => clk4,
reset => reset
);
clk_5:entity work.ClockDivider
generic map(divider => 2)
port map(
reset => reset,
clk => clk4, --(44100*2^1)
clkOut=>clk5 --(44100*2^0)
);
downsampler4:entity work.VectorRegister
generic map(wordLength => 16)
port map(
input=> fir4_out,
output=> out_stage4,
clk=>clk5, --(44100*2^0)
reset=> reset
);
output<= out_stage4;
end architecture ; -- arch
|
mit
|
b53616824ebee4c5358f232b607a3cad
| 0.567793 | 2.92027 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/renvoi.vhd
| 1 | 9,328 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Bypass unit --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity renvoi is
port (
-- Register access signals
adr1 : in adr_reg_type; -- Operand 1 address
adr2 : in adr_reg_type; -- Operand 2 address
use1 : in std_logic; -- Operand 1 utilisation
use2 : in std_logic; -- Operand 2 utilisation
data1 : out bus32; -- First register value
data2 : out bus32; -- Second register value
alea : out std_logic; -- Unresolved hazards detected
-- Bypass signals of the intermediary datas
DI_level : in level_type; -- Availability level of the data
DI_adr : in adr_reg_type; -- Register destination of the result
DI_ecr : in std_logic; -- Writing register request
DI_data : in bus32; -- Data to used
EX_level : in level_type; -- Availability level of the data
EX_adr : in adr_reg_type; -- Register destination of the result
EX_ecr : in std_logic; -- Writing register request
EX_data : in bus32; -- Data to used
MEM_level : in level_type; -- Availability level of the data
MEM_adr : in adr_reg_type; -- Register destination of the result
MEM_ecr : in std_logic; -- Writing register request
MEM_data : in bus32; -- Data to used
interrupt : in std_logic; -- Exceptions or interruptions
-- Connexion to the differents bank of register
-- Writing commands for writing in the registers
write_data : out bus32; -- Data to write
write_adr : out bus5; -- Address of the register to write
write_GPR : out std_logic; -- Selection in the internal registers
write_SCP : out std_logic; -- Selection in the coprocessor system registers
-- Reading commands for Reading in the registers
read_adr1 : out bus5; -- Address of the first register to read
read_adr2 : out bus5; -- Address of the second register to read
read_data1_GPR : in bus32; -- Value of operand 1 from the internal registers
read_data2_GPR : in bus32; -- Value of operand 2 from the internal registers
read_data1_SCP : in bus32; -- Value of operand 1 from the coprocessor system registers
read_data2_SCP : in bus32 -- Value of operand 2 from the coprocessor system registers
);
end renvoi;
architecture rtl of renvoi is
signal dep_r1 : level_type; -- Dependency level for operand 1
signal dep_r2 : level_type; -- Dependency level for operand 2
signal read_data1 : bus32; -- Data contained in the register asked by operand 1
signal read_data2 : bus32; -- Data contained in the register asked by operand 2
signal res_reg, res_mem, res_ex, res_di : std_logic;
signal resolution : bus4; -- Verification of the resolved hazards
signal idx1, idx2 : integer range 0 to 3;
begin
-- Connexion of the writing command signals
write_data <= MEM_data;
write_adr <= MEM_adr(4 downto 0);
write_GPR <= not MEM_adr(5) and MEM_ecr when interrupt = '0' else -- The high bit to 0 selects the internal registers
'0';
write_SCP <= MEM_adr(5) and MEM_ecr; -- The high bit to 1 selects the coprocessor system registers
-- Connexion of the writing command signals
read_adr1 <= adr1(4 downto 0); -- Connexion of the significative address bits
read_adr2 <= adr2(4 downto 0); -- Connexion of the significative address bits
-- Evaluation of the level of dependencies
dep_r1 <= LVL_REG when adr1(4 downto 0)="00000" or use1='0' else -- No dependency with register 0
LVL_DI when adr1=DI_adr and DI_ecr ='1' else -- Dependency with DI stage
LVL_EX when adr1=EX_adr and EX_ecr ='1' else -- Dependency with DI stage
LVL_MEM when adr1=MEM_adr and MEM_ecr='1' else -- Dependency with DI stage
LVL_REG; -- No dependency detected
dep_r2 <= LVL_REG when adr2(4 downto 0)="00000" or use2='0' else -- No dependency with register 0
LVL_DI when adr2=DI_adr and DI_ecr ='1' else -- Dependency with DI stage
LVL_EX when adr2=EX_adr and EX_ecr ='1' else -- Dependency with DI stage
LVL_MEM when adr2=MEM_adr and MEM_ecr='1' else -- Dependency with DI stage
LVL_REG; -- No dependency detected
-- Elaboration of the signals with the datas form the bank registers
read_data1 <= read_data1_GPR when adr1(5)='0' else -- Selection of the internal registers
read_data1_SCP when adr1(5)='1' else -- Selection of the coprocessor registers
(others => '0');
read_data2 <= read_data2_GPR when adr2(5)='0' else -- Selection of the internal registers
read_data2_SCP when adr2(5)='1' else -- Selection of the coprocessor registers
(others => '0');
-- Bypass the datas (the validity is tested later when detecting the hazards)
data1 <= read_data1 when dep_r1=LVL_REG else
MEM_data when dep_r1=LVL_MEM else
EX_data when dep_r1=LVL_EX else
DI_data;
data2 <= read_data2 when dep_r2=LVL_REG else
MEM_data when dep_r2=LVL_MEM else
EX_data when dep_r2=LVL_EX else
DI_data;
-- Detection of a potential unresolved hazard
res_reg <= '1'; -- This hazard is always resolved
res_mem <= '1' when MEM_level>=LVL_MEM else '0';
res_ex <= '1' when EX_level >=LVL_EX else '0';
res_di <= '1' when DI_level >=LVL_DI else '0';
-- Table defining the resolved hazard for each stage
resolution <= res_di & res_ex & res_mem & res_reg;
-- Verification of the validity of the transmitted datas (test the good resolution of the hazards)
idx1 <= to_integer(unsigned(dep_r1(1 downto 0)));
idx2 <= to_integer(unsigned(dep_r2(1 downto 0)));
alea <= not resolution(idx1) or not resolution(idx2);
end rtl;
|
gpl-2.0
|
608b5dcd751ec01670b20995a74c33ff
| 0.498285 | 4.744659 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/controller.vhd
| 4 | 4,417 |
----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Controls the capturing & readback operation.
--
-- If no other operation has been activated, the controller samples data
-- into the memory. When the run signal is received, it continues to do so
-- for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
-- This allows to capture data from before the trigger match which is a nice
-- feature.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity controller is
Port ( clock : in STD_LOGIC;
reset : in std_logic;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputReady : in std_logic;
run : in std_logic;
wrSize : in std_logic;
data : in STD_LOGIC_VECTOR (31 downto 0);
busy : in std_logic;
send : out std_logic;
output : out STD_LOGIC_VECTOR (31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end controller;
architecture Behavioral of controller is
type CONTROLLER_STATES is (SAMPLE, DELAY, READ, READWAIT);
signal fwd, bwd : std_logic_vector (15 downto 0);
signal ncounter, counter: std_logic_vector (17 downto 0);
signal nstate, state : CONTROLLER_STATES;
signal sendReg : std_logic;
begin
output <= memoryIn;
memoryOut <= input;
send <= sendReg;
-- synchronization and reset logic
process(run, clock, reset)
begin
if reset = '1' then
state <= SAMPLE;
elsif rising_edge(clock) then
state <= nstate;
counter <= ncounter;
end if;
end process;
-- FSM to control the controller action
process(state, run, counter, fwd, inputReady, bwd, busy)
begin
case state is
-- default mode: sample data from input to memory
when SAMPLE =>
if run = '1' then
nstate <= DELAY;
else
nstate <= state;
end if;
ncounter <= (others => '0');
memoryWrite <= inputReady;
memoryRead <= '0';
sendReg <= '0';
-- keep sampling for 4 * fwd + 4 samples after run condition
when DELAY =>
if counter = fwd & "11" then
ncounter <= (others => '0');
nstate <= READ;
else
if inputReady = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
memoryWrite <= inputReady;
memoryRead <= '0';
sendReg <= '0';
-- read back 4 * bwd + 4 samples after DELAY
-- go into wait state after each sample to give transmitter time
when READ =>
if counter = bwd & "11" then
ncounter <= (others => '0');
nstate <= SAMPLE;
else
ncounter <= counter + 1;
nstate <= READWAIT;
end if;
memoryWrite <= '0';
memoryRead <= '1';
sendReg <= '1';
-- wait for the transmitter to become ready again
when READWAIT =>
if busy = '0' and sendReg = '0' then
nstate <= READ;
else
nstate <= state;
end if;
ncounter <= counter;
memoryWrite <= '0';
memoryRead <= '0';
sendReg <= '0';
end case;
end process;
-- set speed and size registers if indicated
process(clock)
begin
if rising_edge(clock) then
if wrSize = '1' then
fwd <= data(31 downto 16);
bwd <= data(15 downto 0);
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
5371745bad70a7fdec1ca392e585b5a4
| 0.606294 | 3.811044 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/trigger-logic/wb_trigger_logic.vhd
| 1 | 9,266 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Trigger logic core
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
-- # Adress Map:
-- # 0x0 - Trigger Mask [3:0] ext, [7:4] int, [8] eudet
-- # 0x1 - Trigger tag mode
-- # 0 = trigger counter
-- # 1 = clk_i timestamp
-- # 2 = eudet input
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_trigger_logic is
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
int_trig_i : in std_logic_vector(3 downto 0);
int_trig_o : out std_logic;
int_busy_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0)
);
end wb_trigger_logic;
architecture rtl of wb_trigger_logic is
-- Components
component synchronizer
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end component;
component eudet_tlu
port (
-- Sys connect
clk_i : IN std_logic;
rst_n_i : IN std_logic;
-- Eudet signals
eudet_trig_i : IN std_logic;
eudet_rst_i : IN std_logic;
eudet_busy_o : OUT std_logic;
eudet_clk_o : OUT std_logic;
-- From logic
busy_i : IN std_logic;
simple_mode_i : IN std_logic;
-- To logic
trig_o : OUT std_logic;
rst_o : OUT std_logic;
trig_tag_o : OUT std_logic_vector(15 downto 0)
);
end component;
signal C_DEADTIME : integer := 300; -- clk_i cycles
-- Registers
signal trig_mask : std_logic_vector(31 downto 0);
signal trig_tag_mode : std_logic_vector(7 downto 0);
-- Local signals
signal sync_ext_trig_i : std_logic_vector(3 downto 0);
signal sync_ext_busy_i : std_logic;
signal master_trig_t : std_logic;
signal master_trig_d1 : std_logic;
signal master_trig_d2 : std_logic;
signal master_trig_sel_edge : std_logic;
signal master_trig_pos_edge : std_logic;
signal master_trig_neg_edge : std_logic;
signal master_busy_t : std_logic;
signal eudet_trig_t : std_logic;
signal eudet_trig_tag_t : std_logic_vector(15 downto 0);
signal trig_counter : unsigned (31 downto 0);
signal timestamp_cnt : unsigned(31 downto 0);
signal local_reset : std_logic;
signal deadtime_cnt : unsigned(15 downto 0);
signal busy_t : std_logic;
begin
-- WB interface
wb_proc: process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
trig_mask <= x"00000010"; -- auto enable internal
trig_tag_mode <= x"01";
elsif rising_edge(wb_clk_i) then
wb_ack_o <= '0';
wb_dat_o <= (others => '0');
local_reset <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
case (wb_adr_i(7 downto 0)) is
when x"00" =>
trig_mask <= wb_dat_i;
when x"01" =>
trig_tag_mode <= wb_dat_i(7 downto 0);
when x"FF" =>
local_reset <= '1'; -- Pulse local reset
when others =>
end case;
else
case (wb_adr_i(7 downto 0)) is
when x"00" =>
wb_dat_o <= trig_mask;
when others =>
wb_dat_o <= x"DEADBEEF";
end case;
end if;
end if;
end if;
end process wb_proc;
-- Sync inputs
trig_inputs: for I in 0 to 3 generate
begin
cmp_sync_trig: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => ext_trig_i(I), sync_out => sync_ext_trig_i(I));
end generate trig_inputs;
cmp_sync_busy: synchronizer port map(clk_i => clk_i, rst_n_i => rst_n_i, async_in => ext_busy_i, sync_out => sync_ext_busy_i);
master_busy_t <= sync_ext_busy_i or int_busy_i or busy_t;
-- Apply trigger mask to inputs
master_trig_t <= (sync_ext_trig_i(0) and trig_mask(0))
or (sync_ext_trig_i(1) and trig_mask(1))
or (sync_ext_trig_i(2) and trig_mask(2))
or (sync_ext_trig_i(3) and trig_mask(3))
or (int_trig_i(0) and trig_mask(4))
or (int_trig_i(1) and trig_mask(5))
or (int_trig_i(2) and trig_mask(6))
or (int_trig_i(3) and trig_mask(7))
or (eudet_trig_t and trig_mask(8));
-- find edge
master_trig_sel_edge <= master_trig_pos_edge; -- TODO hardcoded
edge_proc: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
master_trig_d1 <= '0';
master_trig_d2 <= '0';
master_trig_pos_edge <= '0';
master_trig_neg_edge <= '0';
elsif rising_edge(clk_i) then
master_trig_d1 <= master_trig_t;
master_trig_d2 <= master_trig_d1;
master_trig_pos_edge <= '0';
master_trig_neg_edge <= '0';
if (master_trig_d2 = '0' and master_trig_d1 = '1') then
master_trig_pos_edge <= '1';
end if;
if (master_trig_d1 = '0' and master_trig_d2 = '1') then
master_trig_neg_edge <= '1';
end if;
end if;
end process edge_proc;
-- trig tag gen
trig_tag_proc: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_tag <= (others => '0');
trig_counter <= (others => '0');
timestamp_cnt <= (others => '0');
elsif rising_edge(clk_i) then
-- TODO need reset
if (local_reset = '1') then
trig_counter <= (others => '0');
elsif (master_trig_sel_edge = '1') then
trig_counter <= trig_counter + 1;
end if;
if (local_reset = '1') then
timestamp_cnt <= (others => '0');
else
timestamp_cnt <= timestamp_cnt + 1;
end if;
if (master_trig_sel_edge = '1' and master_busy_t = '0') then
case (trig_tag_mode) is
when x"00" =>
trig_tag <= std_logic_vector(trig_counter);
when x"01" =>
trig_tag <= std_logic_vector(timestamp_cnt);
when x"02" =>
trig_tag <= x"0000" & eudet_trig_tag_t;
when others =>
trig_tag <= x"DEADBEEF";
end case;
end if;
end if;
end process trig_tag_proc;
-- Output proc
out_proc: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ext_trig_o <= '0';
ext_busy_o <= '0';
int_trig_o <= '0';
deadtime_cnt <= (others => '0');
busy_t <= '0';
elsif rising_edge(clk_i) then
if (master_busy_t = '0') then
ext_trig_o <= master_trig_sel_edge;
int_trig_o <= master_trig_sel_edge;
ext_busy_o <= '0';
else
ext_busy_o <= '1';
end if;
if (master_trig_sel_edge = '1') then
deadtime_cnt <= TO_UNSIGNED(C_DEADTIME, 16);
end if;
if (deadtime_cnt > 0) then
deadtime_cnt <= deadtime_cnt - 1;
busy_t <= '1';
else
busy_t <= '0';
end if;
end if;
end process out_proc;
cmp_eudet_tlu: eudet_tlu
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
eudet_trig_i => eudet_trig_i,
eudet_rst_i => eudet_rst_i,
eudet_busy_o => eudet_busy_o,
eudet_clk_o => eudet_clk_o,
busy_i => '0',
simple_mode_i => '0',
trig_o => eudet_trig_t,
rst_o => open,
trig_tag_o => eudet_trig_tag_t
);
end rtl;
|
gpl-3.0
|
5496cb59e68ca8b11f053d170f5f7444
| 0.471401 | 3.451024 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_stat_reader.vhd
| 1 | 3,424 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_stat_reader IS
END tb_stat_reader;
ARCHITECTURE behavior OF tb_stat_reader IS
COMPONENT stat_reader
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
Trgr : IN std_logic;
MemAddr : OUT std_logic_vector(8 downto 0);
MemData : IN std_logic_vector(35 downto 0);
ByteOut : OUT std_logic_vector(7 downto 0);
ByteEna : OUT std_logic;
ReaderBusy : IN std_logic
);
END COMPONENT;
COMPONENT uart_tx
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
FreqEn : IN std_logic;
Byte : IN std_logic_vector(7 downto 0);
Kick : IN std_logic;
RsTx : OUT std_logic;
Busy : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '1';
signal Trgr : std_logic := '0';
signal MemData : std_logic_vector(35 downto 0) := X"582ABCDEF";
signal ReaderBusy : std_logic := '0';
signal FreqEn : std_logic := '0';
signal Byte : std_logic_vector(7 downto 0) := X"AA";
signal Kick : std_logic := '0';
--Outputs
signal MemAddr : std_logic_vector(8 downto 0);
signal ByteOut : std_logic_vector(7 downto 0);
signal ByteEna : std_logic;
signal RsTx : std_logic;
signal Busy : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
Byte <= ByteOut;
Kick <= ByteEna;
ReaderBusy <= Busy;
-- Instantiate the Unit Under Test (UUT)
uut: stat_reader PORT MAP (
Clk => Clk,
Rst => Rst,
Trgr => Trgr,
MemAddr => MemAddr,
MemData => MemData,
ByteOut => ByteOut,
ByteEna => ByteEna,
ReaderBusy => ReaderBusy
);
uut2: uart_tx PORT MAP (
Clk => Clk,
Rst => Rst,
FreqEn => FreqEn,
Byte => Byte,
Kick => Kick,
RsTx => RsTx,
Busy => Busy
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Frequenct enable process
Freq_process :process
begin
FreqEn <= '0';
wait for Clk_period * 2;
FreqEn <= '1';
wait for Clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
Rst <= '0';
Trgr <= '1';
wait for 100 ns;
Trgr <= '0';
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
e558bdae9039c136ba0efe7e61e90b44
| 0.585572 | 3.559252 | false | false | false | false |
makestuff/umdkv2
|
vhdl/spi-funnel/tb_unit/spi_funnel_tb.vhdl
| 1 | 6,114 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_funnel_tb is
end entity;
architecture behavioural of spi_funnel_tb is
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
signal cpuWrData : std_logic_vector(15 downto 0);
signal cpuWrValid : std_logic;
signal cpuRdData : std_logic_vector(15 downto 0);
signal cpuByteWide : std_logic;
signal sendData : std_logic_vector(7 downto 0);
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0);
signal recvValid : std_logic;
signal recvReady : std_logic;
signal spiClk : std_logic;
signal spiDataOut : std_logic;
signal spiDataIn : std_logic;
begin
-- Instantiate the memory arbiter for testing
uut: entity work.spi_funnel
port map(
clk_in => sysClk,
reset_in => reset,
-- CPU I/O
cpuByteWide_in => cpuByteWide,
cpuWrData_in => cpuWrData,
cpuWrValid_in => cpuWrValid,
cpuRdData_out => cpuRdData,
cpuRdStrobe_in => '0',
-- Sending SPI data
sendData_out => sendData,
sendValid_out => sendValid,
sendReady_in => sendReady,
-- Receiving SPI data
recvData_in => recvData,
recvValid_in => recvValid,
recvReady_out => recvReady
);
-- SPI master
spi_master : entity work.spi_master
generic map(
SLOW_COUNT => "111011", -- spiClk = sysClk/120 (400kHz @48MHz)
FAST_COUNT => "000000", -- spiClk = sysClk/2 (24MHz @48MHz)
BIT_ORDER => '1' -- MSB first
)
port map(
clk_in => sysClk,
reset_in => reset,
-- Send pipe
turbo_in => '1',
suppress_in => '0',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
-- Receive pipe
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
-- SPI interface
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset one cycle after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
process
begin
cpuByteWide <= 'X';
cpuWrData <= (others => 'X');
cpuWrValid <= '0';
spiDataIn <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
cpuWrData <= x"0306";
cpuByteWide <= '0';
cpuWrValid <= '1';
wait until rising_edge(sysClk);
cpuWrData <= (others => 'X');
cpuByteWide <= 'X';
cpuWrValid <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
cpuWrData <= x"55CA";
cpuByteWide <= '1';
cpuWrValid <= '1';
wait until rising_edge(sysClk);
cpuWrData <= (others => 'X');
cpuByteWide <= 'X';
cpuWrValid <= '0';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
--cpuByteWide <= '1';
--cpuWrData <= x"0055";
--cpuWrValid <= '1';
--wait until rising_edge(sysClk);
--cpuWrData <= (others => 'X');
--cpuWrValid <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
92b0c2000bcb71520671f572702f1b0f
| 0.675172 | 3.357496 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_mdio_ctrl.vhd
| 1 | 3,158 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_mdio_ctrl IS
END tb_mdio_ctrl;
ARCHITECTURE behavior OF tb_mdio_ctrl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mdio_ctrl
PORT(
clk : IN std_logic;
rst : IN std_logic;
cnt_5 : IN std_logic;
cnt_23 : IN std_logic;
mdc : OUT std_logic;
mdio_i : IN std_logic;
mdio_o : OUT std_logic;
mdio_t : OUT std_logic;
op : IN std_logic;
addr : IN std_logic_vector(4 downto 0);
data_i : IN std_logic_vector(15 downto 0);
data_o : OUT std_logic_vector(15 downto 0);
busy : OUT std_logic;
kick : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal cnt64 : std_logic_vector(63 downto 0) := ( others => '0' );
signal mdio_i : std_logic := '0';
signal op : std_logic := '0';
signal addr : std_logic_vector(4 downto 0) := (others => '0');
signal data_i : std_logic_vector(15 downto 0) := (others => '0');
signal kick : std_logic := '0';
--Outputs
signal mdc : std_logic;
signal mdio_o : std_logic;
signal mdio_t : std_logic;
signal data_o : std_logic_vector(15 downto 0);
signal busy : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mdio_ctrl PORT MAP (
clk => clk,
rst => rst,
cnt_5 => cnt64(5),
cnt_23 => cnt64(8),
mdc => mdc,
mdio_i => mdio_i,
mdio_o => mdio_o,
mdio_t => mdio_t,
op => op,
addr => addr,
data_i => data_i,
data_o => data_o,
busy => busy,
kick => kick
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
cnt_64_p :process
begin
cnt64 <= cnt64 + 8;
wait for clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
wait for 5us;
kick <= '1';
wait for clk_period;
kick <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
4c59f15f6698667f297d96dde5b9293a
| 0.586764 | 3.474147 | false | false | false | false |
metaspace/ghdl_extra
|
lfsr4/BIST_signature.vhdl
| 1 | 3,916 |
-- file : BIST_signature.vhdl
-- version : jeu. nov. 4 00:49:28 CET 2010
-- This file shows a LFSR+MISR architecture with (simulated) decimated output.
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std; use std.textio.all;
entity BIST_signature is
end BIST_signature;
architecture BIST of BIST_signature is
signal result, clk, reset : std_ulogic;
signal operandes : std_ulogic_vector(66 downto 1);
signal result_dut, result_ref,
sign_dut, sign_ref : std_ulogic_vector(33 downto 1);
begin
-- the test vector generator
lfsr : entity work.lfsr4
generic map(size => 66)
port map (
clk => clk,
reset => reset,
lfsr => operandes);
-- reference add/sub unit
reference: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
-- A-B = A+(-B) = A+(not B + 1) :
if (operandes(1) = '1') then
substractend := not substractend;
end if;
-- calcule l'addition avec les retenues
res := unsigned(addend) + unsigned(substractend);
-- écrit la retenue sortante mais pas entrante
result_ref <= std_ulogic_vector(res(34 downto 2));
end process;
-- add/sub with a fault
faulty: process(operandes) is
variable addend, substractend : std_ulogic_vector(34 downto 1);
variable res : unsigned(34 downto 1);
begin
addend := '0' & operandes(66 downto 35) & '1';
substractend := '0' & operandes(34 downto 2);
if (operandes(1) = '1') then
substractend := not substractend;
end if;
res := unsigned(addend) + unsigned(substractend);
-- fault injection :
if (operandes(34 downto 28) = "0110110") then
res(33) := '1';
end if;
result_dut <= std_ulogic_vector(res(34 downto 2));
end process;
signref : process(result_ref, reset, clk)
begin
-- reflected polynomial : 33 32 29 27 => 1 2 5 7
if reset = '1' then
sign_ref <= (1=>'1', others=>'0');
else
if rising_edge(clk) then
sign_ref <= result_ref
xor ((sign_ref(1) xor sign_ref(2)
xor sign_ref(5) xor sign_ref(7))
& sign_ref(33 downto 2));
end if;
end if;
end process;
signdut : process(result_dut, reset, clk)
begin
if reset = '1' then
sign_dut <= (1=>'1', others=>'0');
else
if rising_edge(clk) then
sign_dut <= result_dut
xor ((sign_dut(1) xor sign_dut(2)
xor sign_dut(5) xor sign_dut(7))
& sign_dut(33 downto 2));
end if;
end if;
end process;
process
variable r : std_ulogic;
variable u : string(3 downto 1);
variable l : line;
begin
clk <= '0';
reset <= '1';
wait for 1 ns;
reset <= '0';
for i in 1 to 100 loop
for j in 1 to 70 loop
clk <= '1'; wait for 1 ns;
clk <= '0'; wait for 1 ns;
r := sign_dut(1) xor
sign_ref(1);
u := std_ulogic'image(r);
write(l,u(2));
end loop;
writeline(output,l);
end loop;
wait;
end process;
end BIST;
|
gpl-3.0
|
57e339d4948b0a2b0e196728d56ac549
| 0.614559 | 3.604972 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd
| 19 | 18,779 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version.
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
type StType is (
READY,
DECIDE ,
ADDR_PHASE ,
ADDR_TO_DATA_GAP ,
ADDR_TO_DATA_GAP2,
ADDR_TO_DATA_GAP3,
DATA_PHASE ,
ALMOST_READY ,
ALMOST_READY2 ,
ALMOST_READY3
);
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state,nextstate : StType;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "gray";
attribute fsm_encoding of nextstate : signal is "gray";
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
|
gpl-3.0
|
927faa2b18c6df682c1c6d968bcc0466
| 0.543213 | 3.740092 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/predict.vhd
| 1 | 9,301 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Branch prediction --
-- --
-- --
-- --
-- Author : Olivier Schneider --
-- --
-- june 2004 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity predict is
generic (
nb_record : integer := 3
);
port (
clock : in std_logic;
reset : in std_logic;
-- Datas from PF pipeline stage
PF_pc : in std_logic_vector(31 downto 0); -- PC of the current instruction extracted
-- Datas from DI pipeline stage
DI_bra : in std_logic; -- Branch detected
DI_adr : in std_logic_vector(31 downto 0); -- Address of the branch
-- Datas from EX pipeline stage
EX_bra_confirm : in std_logic; -- Confirm if the branch test is ok
EX_adr : in std_logic_vector(31 downto 0); -- Address of the branch
EX_adresse : in std_logic_vector(31 downto 0); -- Result of the branch
EX_uncleared : in std_logic; -- Define if the EX stage is cleared
-- Outputs to PF pipeline stage
PR_bra_cmd : out std_logic; -- Defined a branch
PR_bra_bad : out std_logic; -- Defined a branch to restore from a bad prediction
PR_bra_adr : out std_logic_vector(31 downto 0); -- New PC
-- Clear the three pipeline stage : EI, DI, EX
PR_clear : out std_logic
);
end entity;
architecture rtl of predict is
-- Record contained in the table of prediction
type pred_type is
record
is_affected : std_logic; -- Check if the record is affected
last_bra : std_logic; -- The last branch confirmation result
code_adr : std_logic_vector(31 downto 0); -- Branch instruction address
bra_adr : std_logic_vector(31 downto 0); -- Branch result
end record;
type pred_tab_type is array(1 to nb_record) of pred_type;
-- Table of predictions
signal pred_tab : pred_tab_type;
signal pre_pred_tab : pred_tab_type;
signal next_out : integer range 1 to nb_record := 1; -- Next record to be erased in the table
signal add_record : std_logic;
begin
-- Do the predictions
process(reset, PF_pc, DI_bra, DI_adr, EX_adr, EX_adresse, EX_bra_confirm, pred_tab)
variable index : integer range 0 to nb_record; -- Table index if a code_adr match with an instruction address
variable index2 : integer range 0 to nb_record; -- Table index if a code_adr match with an instruction address
variable index3 : integer range 0 to nb_record; -- Table index if a code_adr match with an instruction address
variable bad_pred : std_logic; -- Flag of bad prediction
begin
-- Default signal affectations
index := 0;
index2 := 0;
index3 := 0;
pre_pred_tab <= pred_tab; -- No modification in table of prediction by default
PR_bra_cmd <= '0';
PR_bra_bad <= '0';
PR_bra_adr <= (others => '0');
PR_clear <= '0';
bad_pred := '0';
add_record <= '0';
-- Check a match in the table
for i in 1 to nb_record loop
if pred_tab(i).is_affected = '1' then
if PF_pc = pred_tab(i).code_adr then
index3 := i;
end if;
if DI_adr = pred_tab(i).code_adr then
index := i;
end if;
if EX_adr = pred_tab(i).code_adr then
index2 := i;
end if;
end if;
end loop;
-- Branch prediciton
if index3 /= 0 then
PR_bra_cmd <= '1';
PR_bra_adr <= pred_tab(index3).bra_adr;
end if;
-- Check if the prediction is ok
if EX_uncleared = '1' then
if index2 /= 0 then
if pred_tab(index2).last_bra /= EX_bra_confirm then -- Bad test result prediction
if EX_bra_confirm = '1' then
pre_pred_tab(index2).last_bra <= '1';
pre_pred_tab(index2).bra_adr <= EX_adresse;
else
pre_pred_tab(index2).last_bra <= '0';
pre_pred_tab(index2).bra_adr <= std_logic_vector(unsigned(pred_tab(index2).code_adr)+4);
end if;
bad_pred := '1';
elsif pred_tab(index2).bra_adr /= EX_adresse then -- Bad adress result prediction
pre_pred_tab(index2).bra_adr <= EX_adresse;
bad_pred := '1';
end if;
end if;
end if;
-- Clear the pipeline and branch to the new instruction
if bad_pred = '1' then
PR_bra_bad <= '1';
PR_bra_adr <= pre_pred_tab(index2).bra_adr;
PR_clear <= '1';
end if;
-- Add a record in the table
if DI_bra = '1' then
if index = 0 then
add_record <= '1';
pre_pred_tab(next_out).is_affected <= '1'; -- The record is affected
pre_pred_tab(next_out).last_bra <= '0'; -- Can't predict the branch the first time
pre_pred_tab(next_out).code_adr <= DI_adr; -- Save the branch address
pre_pred_tab(next_out).bra_adr <= std_logic_vector(unsigned(DI_adr)+4); -- Branch result
end if;
end if;
end process;
-- Update the table of prediction
process(clock, reset)
begin
if reset = '1' then
next_out <= 1; -- At the beginning the first record must be chosen to be filled
for i in 1 to nb_record loop
pred_tab(i).is_affected <= '0';
end loop;
elsif rising_edge(clock) then
pred_tab <= pre_pred_tab;
if add_record = '1' then
if next_out = nb_record then
next_out <= 1;
else
next_out <= next_out+1; -- Next record to be erased
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
9f360a40280023509830e65d589fd3c1
| 0.430706 | 4.86454 | false | false | false | false |
maxx04/cam_sim
|
cam_sim.srcs/sim_1/imports/BMP/sim_bmppack.vhd
| 1 | 8,349 |
-------------------------------------------------------------------------------
-- Title : BMP Package
-- Project :
-------------------------------------------------------------------------------
-- File : sim_bmppack.vhd
-- Author : Kest
-- Company :
-- Created : 2006-12-05
-- Last update: 2007-10-29
-- Platform : ModelSIM 6.0
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006 by Kest
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006-12-05 1.0 kest Created
-------------------------------------------------------------------------------
-- http://de.wikipedia.org/wiki/Windows_Bitmap
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-------------------------------------------------------------------------------
package sim_bmppack is
-- maximale Größe des Speichers
constant cMAX_X : integer := 1300;
constant cMAX_Y : integer := 1300;
constant cBytesPerPixel : integer := 3;
constant cMaxMemSize : integer := cMAX_X * cMAX_Y * cBytesPerPixel;
subtype file_element is std_logic_vector(7 downto 0);
type mem_array is array(cMaxMemSize downto 0) of file_element;
type header_array is array(53 downto 0) of file_element;
procedure ReadFile(FileName : in string);
procedure WriteFile(FileName : in string);
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0));
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0));
function GetWidth(header : in header_array) return integer;
procedure GetWidth(signal width : out integer);
function GetHeigth(header : in header_array) return integer;
procedure GetHeigth(signal height : out integer);
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0));
procedure SetPixel (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0));
procedure DrawCross (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0));
end package sim_bmppack;
-------------------------------------------------------------------------------
-- Package body
-------------------------------------------------------------------------------
package body sim_bmppack is
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
shared variable memory_in : mem_array;
shared variable memory_out : mem_array;
shared variable header : header_array;
shared variable pImageSize : integer;
shared variable pImageWidth : integer;
shared variable pImageHeight : integer;
-----------------------------------------------------------------------------
-- This code reads a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure ReadFile(FileName : in string) is
variable next_vector : bit_vector (0 downto 0);
variable actual_len : natural;
variable index : integer := 0;
type bit_vector_file is file of bit_vector;
file read_file : bit_vector_file open read_mode is FileName;
begin
report "Read File";
report FileName;
index := 0;
---------------------------------------------------------------------------
-- Header einlesen
---------------------------------------------------------------------------
report "Read Header";
for i in 0 to 53 loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
header(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
index := index + 1;
end if;
end loop;
pImageWidth := GetWidth(header);
pImageHeight := GetHeigth(header);
pImageSize := pImageWidth * pImageHeight;
report "Read Image";
index := 0;
while not endfile(read_file) loop
read(read_file, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
memory_in(index) := conv_std_logic_vector(bit'pos(next_vector(0)), 8);
memory_out(index) := x"45";
index := index + 1;
end if;
end loop;
report "Okay";
end ReadFile;
-----------------------------------------------------------------------------
-- Read one byte from Memory
-----------------------------------------------------------------------------
procedure ReadByteFromMemory (adr : in integer; variable data : out std_logic_vector(7 downto 0)) is
begin
data := memory_in(adr);
end ReadByteFromMemory;
-----------------------------------------------------------------------------
-- Pixel Operationen
-----------------------------------------------------------------------------
procedure GetPixel (x : in integer; y : in integer; signal data : out std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
data(23 downto 16) <= memory_in(x*3 + 3*y*GetWidth(header));
data(15 downto 8) <= memory_in(x*3+1 + 3*y*GetWidth(header));
data(7 downto 0) <= memory_in(x*3+2 + 3*y*GetWidth(header));
end if;
end GetPixel;
procedure SetPixel (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0)) is
begin
if x >= 0 and x < cMAX_X and y >= 0 and y < cMAX_Y then
memory_out(x*3+y*(GetWidth(header)*3)) := data(23 downto 16);
memory_out(x*3+1+y*(GetWidth(header)*3)) := data(15 downto 8);
memory_out(x*3+2+y*(GetWidth(header)*3)) := data(7 downto 0);
end if;
end SetPixel;
procedure DrawCross (x : in integer; y : in integer; signal data : in std_logic_vector(23 downto 0)) is
constant CrossSize : integer := 5;
begin
for n in -CrossSize to CrossSize loop
SetPixel(x+n,y,data);
SetPixel(x,y+n,data);
end loop;
end DrawCross;
-----------------------------------------------------------------------------
-- Write one byte to Memory
-----------------------------------------------------------------------------
procedure WriteByteToMemory (adr : in integer; variable data : in std_logic_vector(7 downto 0)) is
begin
memory_out(adr) := data;
end WriteByteToMemory;
-- Get Width of Image
function GetWidth(header : in header_array) return integer is
begin
return conv_integer(header(21) & header(20) & header(19) & header(18));
end function GetWidth;
procedure GetWidth(signal width : out integer) is
begin
width <= pImageWidth;
end GetWidth;
-- Get Height of Image
function GetHeigth(header : in header_array) return integer is
begin
return conv_integer(header(25) & header(24) & header(23) & header(22));
end function GetHeigth;
procedure GetHeigth(signal height : out integer) is
begin
height <= pImageHeight;
end GetHeigth;
-----------------------------------------------------------------------------
-- This code write a raw binary file one byte at a time.
-----------------------------------------------------------------------------
procedure WriteFile(FileName : in string) is
variable next_vector : character;
variable index : integer := 0;
type char_file is file of character;
file write_file : char_file open write_mode is FileName;
begin
report "Write File...";
report FileName;
report "write Header";
index := 0;
for i in 0 to 53 loop
next_vector := character'val(conv_integer(header(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "write Image";
index := 0;
while index < pImageSize*3 loop
next_vector := character'val(conv_integer(memory_out(index)));
write(write_file, next_vector);
index := index + 1;
end loop;
report "Okay";
end WriteFile;
end sim_bmppack;
|
gpl-3.0
|
28bb7b7b0025f4c55b95617c33c2dce9
| 0.50509 | 4.486298 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Arithmetic/Multiplier.vhd
| 1 | 3,670 |
------------------------------------------------------
------------------------------------------------------
-- Description: --
-- Implementation of a simple multiplier --
-- --
-- Generics: --
-- X_WIDTH - Width of the input x --
-- X_FRACTION - Width of the fractional part of x --
-- Y_WIDTH - Width of the input y --
-- Y_FRACTION - Width of the fractional part of y --
-- S_WIDTH - Desired width of the output s --
-- S_FRACTION - Desired width of the fractional --
-- part of s --
-- --
-- Input/Output: --
-- x - First factor --
-- y - Second factor --
-- s - Product --
-- --
------------------------------------------------------
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Multiplier is
generic (
X_WIDTH : natural := 16;
X_FRACTION : natural := 14;
Y_WIDTH : natural := 16;
Y_FRACTION : natural := 14;
S_WIDTH : natural := 16;
S_FRACTION : natural := 13
);
port(
x : in std_logic_vector(X_WIDTH-1 downto 0);
y : in std_logic_vector(Y_WIDTH-1 downto 0);
s : out std_logic_vector(S_WIDTH-1 downto 0)
);
end Multiplier;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Multiplier is
-- Functions -----------------------------------------------------------------
function paddedLength(old_width : integer ;upper_limit : integer) return integer is
begin
if(upper_limit > old_width) then
return upper_limit;
else
return old_width;
end if;
end paddedLength;
-- Constants -----------------------------------------------------------------
constant UPPER_LIMIT : integer := X_FRACTION+Y_FRACTION-S_FRACTION+S_WIDTH-1;
constant LOWER_LIMIT : integer := X_FRACTION+Y_FRACTION-S_FRACTION;
constant X_LENGTH : integer := paddedLength(X_WIDTH, UPPER_LIMIT);
constant Y_LENGTH : integer := paddedLength(Y_WIDTH, UPPER_LIMIT);
-- Signals -------------------------------------------------------------------
signal x_padded : std_logic_vector(X_LENGTH-1 downto 0);
signal y_padded : std_logic_vector(Y_LENGTH-1 downto 0);
signal product : std_logic_vector(X_LENGTH + Y_LENGTH - 1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Fill upper bits if necessary
x_padder:
if(UPPER_LIMIT > X_WIDTH) generate
x_padded(UPPER_LIMIT-1 downto X_WIDTH) <= (others => x(X_WIDTH-1));
end generate;
y_padder:
if(UPPER_LIMIT > Y_WIDTH) generate
y_padded(UPPER_LIMIT-1 downto Y_WIDTH) <= (others => y(Y_WIDTH-1));
end generate;
-- Put the input onto the multiplier
x_padded(X_WIDTH-1 downto 0) <= x;
y_padded(Y_WIDTH-1 downto 0) <= y;
-- Multiply and cast result into appropriate size
product <= std_logic_vector(signed(x_padded) * signed(y_padded));
s <= product(UPPER_LIMIT downto LOWER_LIMIT);
end architecture;
|
mit
|
fd38b909176e42054df8fb5d2fb78bf7
| 0.419619 | 4.530864 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/debugregisters.vhd
| 1 | 3,777 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/28/2017 01:43:25 PM
-- Design Name:
-- Module Name: debugregisters - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debugregisters is
generic (
constant ADDR_WIDTH : integer := 4;
constant DATA_WIDTH : integer := 32
);
Port (
-- SYS CON
clk : in std_logic;
rst : in std_logic;
-- Wishbone Slave in
wb_adr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wb_dat_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
-- Wishbone Slave out
wb_dat_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic ;
-- input/ouput
dummyram_sel_o : out std_logic;
ddr3ram_sel_o : out std_logic;
dummyaddress_sel_o : out std_logic;
dummydeadbeef_sel_o : out std_logic;
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0)--;
--ddr_init_calib_complete_i : in std_logic
);
end debugregisters;
architecture Behavioral of debugregisters is
type ram_type is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM: ram_type;
signal ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal chipselect_s : std_logic;
constant whisbonecompselect_addr : integer := 0;
constant io_addr : integer := 1;
constant ddr_status : integer := 2;
begin
ADDR <= wb_adr_i(ADDR_WIDTH-1 downto 0);
--chipselect_s <= '1' when wb_adr_i(WSH_ADDR_WIDTH-1 downto RAM_ADDR_WIDTH) = BASE_ADDRESS (WSH_ADDR_WIDTH-1 downto RAM_ADDR_WIDTH);
bram: process (clk, rst)
begin
if (rst ='1') then
wb_ack_o <= '0';
for i in 0 to 2**ADDR_WIDTH-1 loop
RAM(i) <= conv_std_logic_vector(0,RAM(i)'length);
end loop;
elsif (clk'event and clk = '1') then
if (wb_stb_i = '1' and wb_cyc_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
RAM(conv_integer(ADDR)) <= wb_dat_i;
end if;
wb_dat_o <= RAM(conv_integer(ADDR)) ;
else
wb_ack_o <= '0';
end if;
-- input bits
RAM(io_addr)(6 downto 4) <= usr_sw_i;
--RAM(ddr_status)(0) <= ddr_init_calib_complete_i;
end if;
end process bram;
--output bits
dummyram_sel_o <= '1' when RAM(whisbonecompselect_addr)(1 downto 0) = "00" else '0';
ddr3ram_sel_o <= '1' when RAM(whisbonecompselect_addr)(1 downto 0) = "01" else '0';
dummyaddress_sel_o <= '1' when RAM(whisbonecompselect_addr)(1 downto 0) = "10" else '0';
dummydeadbeef_sel_o <= '1' when RAM(whisbonecompselect_addr)(1 downto 0) = "11" else '0';
usr_led_o <= RAM(io_addr)(3 downto 0);
end Behavioral;
|
gpl-3.0
|
8887deadc4fd9e81fa29502ebf0e4f66
| 0.545671 | 3.449315 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Top Level/AudioStage_tl.vhd
| 1 | 4,121 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AudioStage_tl is
port (
vauxn : in std_logic;
vauxp : in std_logic;
pwm_out : out std_logic;
pwm_amp : out std_logic;
leds : out std_logic_vector(15 downto 0);
muteInput : in std_logic;
bypassLP : in std_logic;
bypassEcho : in std_logic;
bypassFlanger : in std_logic;
bypassEQ : in std_logic;
clk : in std_logic;
reset : in std_logic
) ;
end entity ; -- AudioStage_tl
architecture arch of AudioStage_tl is
signal sampleInputClk : std_logic;
signal sampleOutput : std_logic_vector(11 downto 0);
signal decimatorInput : std_logic_vector(15 downto 0);
signal decimatorOutput : std_logic_vector(15 downto 0);
signal decimatorMuxedOutput : std_logic_vector(15 downto 0);
signal throughputClk : std_logic;
signal sampleClk : std_logic;
signal echoClk : std_logic;
signal effectInputEcho : std_logic_vector(15 downto 0);
signal effectOutputEcho : std_logic_vector(15 downto 0);
signal effectInputFlanger : std_logic_vector(15 downto 0);
signal effectOutputFlanger : std_logic_vector(15 downto 0);
signal effectInputFlangerb : std_logic_vector(15 downto 0);
signal temp_eq_in : std_logic_vector(15 downto 0);
signal temp_eq_out : std_logic_vector(15 downto 0);
signal toPWM : std_logic_vector(8 downto 0);
signal clkPWM : std_logic;
begin
pwm_amp <= '1';
leds <= effectInputEcho;
sampleClkGenerator : entity work.ClockDivider
generic map (
divider => 128 --2^11*44.1 k to 705.6 k
--divider => 142 --100 MHz to 705.6 kHz.
)
port map (
clk => clk,
clkOut => sampleInputClk,
reset => reset
);
-- INPUT
ADC : entity work.ADSampler
port map (
vauxn => vauxn,
vauxp => vauxp,
output => sampleOutput,
sampleClk => sampleInputClk,
clk => clk,
reset => reset
);
-- Concatenate 0's to create 16 bit input.
--decimatorInput <= sampleOutput & "0000";
--decimatorInput <= sampleOutput and (others => muteInput);
decimatorInput <= sampleOutput & x"0" when muteInput = '0' else
(others => '0');
decimator: entity work.StructuralDecimator
port map (
input => decimatorInput,
output => decimatorOutput,
clk => clk,
reset => reset
);
decimatorMuxedOutput <= decimatorOutput when bypassLP = '0' else
decimatorInput;
-- EFFECTS
effectInputEcho <= decimatorMuxedOutput;
echoClkGenerator : entity work.ClockDivider
generic map (
divider => 256 -- Clock at 8*44.1 kHz (Echo has 8 states per sample)
)
port map (
clk => clk,
clkOut => echoClk,
reset => reset
);
Echo: entity work.EffectEcho
port map (
input => effectInputEcho,
output => effectOutputEcho,
clk => echoClk,
reset => reset
);
effectInputFlanger <= effectOutputEcho when bypassEcho = '0' else
effectInputEcho;
pipeline_1: entity work.VectorRegister
generic map(wordLength => 16 -- buffer between echo and flanger
)
port map(
input =>effectInputFlanger,
output=>effectInputFlangerb,
clk => throughputClk,
reset =>reset
);
Flanger: entity work.EffectFlanger
port map (
input => effectInputFlangerb,
output => effectOutputFlanger,
clk => echoClk,
reset => reset
);
-- OUTPUT
temp_eq_in <= effectOutputFlanger when bypassFlanger = '0' else
effectInputFlanger;
EqualizerClkGenerator : entity work.ClockDivider
generic map (
divider => 2048 -- Clock at 1*44.1 kHz (Recommended Clock for Equalizer)
)
port map (
clk => clk,
clkOut => throughputClk,
reset => reset
);
temp_eq_out <= temp_eq_in;
-- EQ: entity work.Generic_Equalizer_Low_Pass
-- port map(
-- clk => throughputClk,
-- reset => reset,
-- input => temp_eq_in,
-- output => temp_eq_out
-- );
toPWM <= temp_eq_out(15 downto 7);
-- toPWM <= temp_eq_out(15 downto 7) when bypassEQ = '0' else
-- temp_eq_in(15 downto 7);
-- Output freq: 195.3 kHz
PWM: entity work.DAPwm
generic map(
wordLength => 9 -- 512 values -> 195.3 kHz @ 100MHz
)
port map(
input => toPWM,
output => pwm_out,
clk => clk,
reset => reset
);
end architecture ; -- arch
|
mit
|
85cf2b48b872539462d6554821ea5996
| 0.668284 | 3.162701 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/wshexp-core/dma_controller.vhd
| 2 | 20,396 |
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: DMA controller (dma_controller.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 0.2
--
-- description: Manages the DMA transfers.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 30-09-2010 (mcattin) Add status, error and abort
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wshexp_core_pkg.all;
entity dma_controller is
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_h_o : out std_logic_vector(31 downto 0);
dma_ctrl_host_addr_l_o : out std_logic_vector(31 downto 0);
dma_ctrl_len_o : out std_logic_vector(31 downto 0);
dma_ctrl_start_l2p_o : out std_logic; -- To the L2P DMA master
dma_ctrl_start_p2l_o : out std_logic; -- To the P2L DMA master
dma_ctrl_start_next_o : out std_logic; -- To the P2L DMA master
dma_ctrl_byte_swap_o : out std_logic_vector(1 downto 0);
dma_ctrl_abort_o : out std_logic;
dma_ctrl_done_i : in std_logic;
dma_ctrl_error_i : in std_logic;
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i : in std_logic_vector(31 downto 0);
next_item_host_addr_h_i : in std_logic_vector(31 downto 0);
next_item_host_addr_l_i : in std_logic_vector(31 downto 0);
next_item_len_i : in std_logic_vector(31 downto 0);
next_item_next_l_i : in std_logic_vector(31 downto 0);
next_item_next_h_i : in std_logic_vector(31 downto 0);
next_item_attrib_i : in std_logic_vector(31 downto 0);
next_item_valid_i : in std_logic;
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i : in std_logic; -- Bus clock
wb_adr_i : in std_logic_vector(3 downto 0); -- Adress
wb_dat_o : out std_logic_vector(31 downto 0); -- Data in
wb_dat_i : in std_logic_vector(31 downto 0); -- Data out
wb_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wb_cyc_i : in std_logic; -- Read or write cycle
wb_stb_i : in std_logic; -- Read or write strobe
wb_we_i : in std_logic; -- Write
wb_ack_o : out std_logic; -- Acknowledge
---------------------------------------------------------
-- debug outputs
dma_ctrl_current_state_do : out std_logic_vector (2 downto 0);
dma_ctrl_do : out std_logic_vector(31 downto 0);
dma_stat_do : out std_logic_vector(31 downto 0);
dma_attrib_do : out std_logic_vector(31 downto 0)
);
end dma_controller;
architecture behaviour of dma_controller is
------------------------------------------------------------------------------
-- Wishbone slave component declaration
------------------------------------------------------------------------------
component dma_controller_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
clk_i : in std_logic;
-- Port for std_logic_vector field: 'DMA engine control' in reg: 'DMACTRLR'
dma_ctrl_o : out std_logic_vector(31 downto 0);
dma_ctrl_i : in std_logic_vector(31 downto 0);
dma_ctrl_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA engine status' in reg: 'DMASTATR'
dma_stat_o : out std_logic_vector(31 downto 0);
dma_stat_i : in std_logic_vector(31 downto 0);
dma_stat_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address in the carrier' in reg: 'DMACSTARTR'
dma_cstart_o : out std_logic_vector(31 downto 0);
dma_cstart_i : in std_logic_vector(31 downto 0);
dma_cstart_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address (low) in the host' in reg: 'DMAHSTARTLR'
dma_hstartl_o : out std_logic_vector(31 downto 0);
dma_hstartl_i : in std_logic_vector(31 downto 0);
dma_hstartl_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA start address (high) in the host' in reg: 'DMAHSTARTHR'
dma_hstarth_o : out std_logic_vector(31 downto 0);
dma_hstarth_i : in std_logic_vector(31 downto 0);
dma_hstarth_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA read length in bytes' in reg: 'DMALENR'
dma_len_o : out std_logic_vector(31 downto 0);
dma_len_i : in std_logic_vector(31 downto 0);
dma_len_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pointer (low) to next item in list' in reg: 'DMANEXTLR'
dma_nextl_o : out std_logic_vector(31 downto 0);
dma_nextl_i : in std_logic_vector(31 downto 0);
dma_nextl_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pointer (high) to next item in list' in reg: 'DMANEXTHR'
dma_nexth_o : out std_logic_vector(31 downto 0);
dma_nexth_i : in std_logic_vector(31 downto 0);
dma_nexth_load_o : out std_logic;
-- Port for std_logic_vector field: 'DMA chain control' in reg: 'DMAATTRIBR'
dma_attrib_o : out std_logic_vector(31 downto 0);
dma_attrib_i : in std_logic_vector(31 downto 0);
dma_attrib_load_o : out std_logic
);
end component dma_controller_wb_slave;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_IDLE : std_logic_vector(2 downto 0) := "000";
constant c_DONE : std_logic_vector(2 downto 0) := "001";
constant c_BUSY : std_logic_vector(2 downto 0) := "010";
constant c_ERROR : std_logic_vector(2 downto 0) := "011";
constant c_ABORT : std_logic_vector(2 downto 0) := "100";
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- DMA controller registers
signal dma_ctrl : std_logic_vector(31 downto 0);
signal dma_stat : std_logic_vector(31 downto 0);
signal dma_cstart : std_logic_vector(31 downto 0);
signal dma_hstartl : std_logic_vector(31 downto 0);
signal dma_hstarth : std_logic_vector(31 downto 0);
signal dma_len : std_logic_vector(31 downto 0);
signal dma_nextl : std_logic_vector(31 downto 0);
signal dma_nexth : std_logic_vector(31 downto 0);
signal dma_attrib : std_logic_vector(31 downto 0);
signal dma_ctrl_load : std_logic;
signal dma_stat_load : std_logic;
signal dma_cstart_load : std_logic;
signal dma_hstartl_load : std_logic;
signal dma_hstarth_load : std_logic;
signal dma_len_load : std_logic;
signal dma_nextl_load : std_logic;
signal dma_nexth_load : std_logic;
signal dma_attrib_load : std_logic;
signal dma_ctrl_reg : std_logic_vector(31 downto 0);
signal dma_stat_reg : std_logic_vector(31 downto 0);
signal dma_cstart_reg : std_logic_vector(31 downto 0);
signal dma_hstartl_reg : std_logic_vector(31 downto 0);
signal dma_hstarth_reg : std_logic_vector(31 downto 0);
signal dma_len_reg : std_logic_vector(31 downto 0);
signal dma_nextl_reg : std_logic_vector(31 downto 0);
signal dma_nexth_reg : std_logic_vector(31 downto 0);
signal dma_attrib_reg : std_logic_vector(31 downto 0);
-- DMA controller FSM
type dma_ctrl_state_type is (DMA_IDLE, DMA_START_TRANSFER, DMA_TRANSFER,
DMA_START_CHAIN, DMA_CHAIN,
DMA_ERROR, DMA_ABORT);
signal dma_ctrl_current_state : dma_ctrl_state_type;
-- status signals
signal dma_status : std_logic_vector(2 downto 0);
signal dma_error_irq : std_logic;
signal dma_done_irq : std_logic;
begin
dma_ctrl_do <= dma_ctrl;
dma_stat_do <= dma_stat;
dma_attrib_do <= dma_attrib;
with dma_ctrl_current_state select dma_ctrl_current_state_do <=
"000" when DMA_IDLE,
"001" when DMA_START_TRANSFER,
"010" when DMA_TRANSFER,
"011" when DMA_START_CHAIN,
"100" when DMA_CHAIN,
"110" when DMA_ERROR,
"111" when DMA_ABORT;
------------------------------------------------------------------------------
-- Wishbone slave instanciation
------------------------------------------------------------------------------
dma_controller_wb_slave_0 : dma_controller_wb_slave port map (
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
clk_i => clk_i,
dma_ctrl_o => dma_ctrl,
dma_ctrl_i => dma_ctrl_reg,
dma_ctrl_load_o => dma_ctrl_load,
dma_stat_o => open,
dma_stat_i => dma_stat_reg,
dma_stat_load_o => open,
dma_cstart_o => dma_cstart,
dma_cstart_i => dma_cstart_reg,
dma_cstart_load_o => dma_cstart_load,
dma_hstartl_o => dma_hstartl,
dma_hstartl_i => dma_hstartl_reg,
dma_hstartl_load_o => dma_hstartl_load,
dma_hstarth_o => dma_hstarth,
dma_hstarth_i => dma_hstarth_reg,
dma_hstarth_load_o => dma_hstarth_load,
dma_len_o => dma_len,
dma_len_i => dma_len_reg,
dma_len_load_o => dma_len_load,
dma_nextl_o => dma_nextl,
dma_nextl_i => dma_nextl_reg,
dma_nextl_load_o => dma_nextl_load,
dma_nexth_o => dma_nexth,
dma_nexth_i => dma_nexth_reg,
dma_nexth_load_o => dma_nexth_load,
dma_attrib_o => dma_attrib,
dma_attrib_i => dma_attrib_reg,
dma_attrib_load_o => dma_attrib_load
);
------------------------------------------------------------------------------
-- DMA controller registers
------------------------------------------------------------------------------
p_regs : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
dma_ctrl_reg <= (others => '0');
dma_stat_reg <= (others => '0');
dma_cstart_reg <= (others => '0');
dma_hstartl_reg <= (others => '0');
dma_hstarth_reg <= (others => '0');
dma_len_reg <= (others => '0');
dma_nextl_reg <= (others => '0');
dma_nexth_reg <= (others => '0');
dma_attrib_reg <= (others => '0');
elsif rising_edge(clk_i) then
-- Control register
if (dma_ctrl_load = '1') then
dma_ctrl_reg <= dma_ctrl;
end if;
-- Status register
dma_stat_reg(2 downto 0) <= dma_status;
dma_stat_reg(31 downto 3) <= (others => '0');
-- Target start address
if (dma_cstart_load = '1') then
dma_cstart_reg <= dma_cstart;
end if;
-- Host start address lowest 32-bit
if (dma_hstartl_load = '1') then
dma_hstartl_reg <= dma_hstartl;
end if;
-- Host start address highest 32-bit
if (dma_hstarth_load = '1') then
dma_hstarth_reg <= dma_hstarth;
end if;
-- DMA transfer length in byte
if (dma_len_load = '1') then
dma_len_reg <= dma_len;
end if;
-- next item address lowest 32-bit
if (dma_nextl_load = '1') then
dma_nextl_reg <= dma_nextl;
end if;
-- next item address highest 32-bit
if (dma_nexth_load = '1') then
dma_nexth_reg <= dma_nexth;
end if;
-- Chained DMA control
if (dma_attrib_load = '1') then
dma_attrib_reg <= dma_attrib;
end if;
-- next item received => start a new transfer
if (next_item_valid_i = '1') then
dma_ctrl_reg(0) <= '1';
dma_cstart_reg <= next_item_carrier_addr_i;
dma_hstartl_reg <= next_item_host_addr_l_i;
dma_hstarth_reg <= next_item_host_addr_h_i;
dma_len_reg <= next_item_len_i;
dma_nextl_reg <= next_item_next_l_i;
dma_nexth_reg <= next_item_next_h_i;
dma_attrib_reg <= next_item_attrib_i;
end if;
-- Start DMA, 1 tick pulse
if (dma_ctrl_reg(0) = '1') then
dma_ctrl_reg(0) <= '0';
end if;
end if;
end process p_regs;
dma_ctrl_byte_swap_o <= dma_ctrl_reg(3 downto 2);
------------------------------------------------------------------------------
-- IRQ output assignement
------------------------------------------------------------------------------
dma_ctrl_irq_o <= dma_error_irq & dma_done_irq;
------------------------------------------------------------------------------
-- DMA controller FSM
------------------------------------------------------------------------------
p_fsm : process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= c_IDLE;
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
elsif rising_edge(clk_i) then
case dma_ctrl_current_state is
when DMA_IDLE =>
-- Clear done irq to make it 1 tick pulse
dma_done_irq <= '0';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_START_TRANSFER =>
-- Clear abort signal
dma_ctrl_abort_o <= '0';
if (unsigned(dma_len_reg(31 downto 2)) = 0) then
-- Requesting a DMA of 0 word length gives a error
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
else
-- Start the DMA if the length is not 0
if (dma_attrib_reg(1) = '0') then
-- L2P transfer (from target to PCIe)
dma_ctrl_start_l2p_o <= '1';
elsif (dma_attrib_reg(1) = '1') then
-- P2L transfer (from PCIe to target)
dma_ctrl_start_p2l_o <= '1';
end if;
dma_ctrl_current_state <= DMA_TRANSFER;
dma_ctrl_carrier_addr_o <= dma_cstart_reg;
dma_ctrl_host_addr_h_o <= dma_hstarth_reg;
dma_ctrl_host_addr_l_o <= dma_hstartl_reg;
dma_ctrl_len_o <= dma_len_reg;
dma_status <= c_BUSY;
end if;
when DMA_TRANSFER =>
-- Clear start signals, to make them 1 tick pulses
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
if (dma_ctrl_reg(1) = '1') then
-- Transfer aborted
dma_ctrl_current_state <= DMA_ABORT;
elsif(dma_ctrl_error_i = '1') then
-- An error occurs !
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
elsif(dma_ctrl_done_i = '1') then
-- End of DMA transfer
if(dma_attrib_reg(0) = '1') then
-- More transfer in chained DMA
dma_ctrl_current_state <= DMA_START_CHAIN;
else
-- Was the last transfer
dma_status <= c_DONE;
dma_done_irq <= '1';
dma_ctrl_current_state <= DMA_IDLE;
end if;
end if;
when DMA_START_CHAIN =>
-- Catch the next item in host memory
dma_ctrl_current_state <= DMA_CHAIN;
dma_ctrl_host_addr_h_o <= dma_nexth_reg;
dma_ctrl_host_addr_l_o <= dma_nextl_reg;
dma_ctrl_len_o <= X"0000001C";
dma_ctrl_start_next_o <= '1';
when DMA_CHAIN =>
-- Clear start next signal, to make it 1 tick pulse
dma_ctrl_start_next_o <= '0';
if (dma_ctrl_reg(1) = '1') then
-- Transfer aborted
dma_ctrl_current_state <= DMA_ABORT;
elsif(dma_ctrl_error_i = '1') then
-- An error occurs !
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
elsif (next_item_valid_i = '1') then
-- next item received
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_ERROR =>
dma_status <= c_ERROR;
-- Clear error irq to make it 1 tick pulse
dma_error_irq <= '0';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when DMA_ABORT =>
dma_status <= c_ABORT;
dma_ctrl_abort_o <= '1';
if(dma_ctrl_reg(0) = '1') then
-- Starts a new transfer
dma_ctrl_current_state <= DMA_START_TRANSFER;
end if;
when others =>
dma_ctrl_current_state <= DMA_IDLE;
dma_ctrl_carrier_addr_o <= (others => '0');
dma_ctrl_host_addr_h_o <= (others => '0');
dma_ctrl_host_addr_l_o <= (others => '0');
dma_ctrl_len_o <= (others => '0');
dma_ctrl_start_l2p_o <= '0';
dma_ctrl_start_p2l_o <= '0';
dma_ctrl_start_next_o <= '0';
dma_status <= (others => '0');
dma_error_irq <= '0';
dma_done_irq <= '0';
dma_ctrl_abort_o <= '0';
end case;
end if;
end process p_fsm;
end behaviour;
|
gpl-3.0
|
fd725b0ef91479ec4d8079e0dd9664b9
| 0.497156 | 3.599718 | false | false | false | false |
openttp/openttp
|
software/system/src/fpga/vhdl/TICounters.vhd
| 1 | 3,941 |
----------------------------------------------------------------------------------
-- TICounters - a collection of counters
--
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Michael J. Wouters
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
-- Modification history
-- 2013-10-21 MJW First version.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
use work.TRIGGERS.OneShot;
--
-- 32 bit time-interval measurement
--
entity TICounter32 is
port( startTrig : in STD_LOGIC;
stopTrig : in STD_LOGIC;
clk : in STD_LOGIC;
tint : out STD_LOGIC_VECTOR(31 downto 0); -- the time interval measurement
dataReady : out STD_LOGIC;
ledPulse : out STD_LOGIC
);
end TICounter32;
architecture RTL of TICounter32 is
signal cnt :STD_LOGIC_VECTOR(29 downto 0);
signal savereg :STD_LOGIC_VECTOR(31 downto 0);
signal triggered :STD_LOGIC;
signal delay1: STD_LOGIC;
begin
-- Free running counter with synchronous reset
-- The start trigger must only be one period of 'clk' long so it will
-- be typically be driven via a one-shot
process (clk)
begin
if (rising_edge(clk)) then
if (startTrig='1' ) then
cnt<= (others => '0');
else
cnt<= cnt + 1;
end if;
end if;
end process;
-- Register for saving the counter reading
-- Similar to the start trigger, the stop trigger must be only one period of 'clk' long
process (clk)
begin
if rising_edge(clk) then
if delay1 ='1' then
savereg <= cnt & "00"; -- bottom two bits will eventually set by a delay chain measurement
end if;
end if;
end process;
-- Delay of one clock period to synchronise clocking of output register
-- with data availablity
process (clk)
begin
if rising_edge(clk) then
delay1 <= stopTrig;
end if;
end process;
-- 'Data ready' signal - just a delayed 'B' trigger
process (clk)
begin
if rising_edge(clk) then
triggered <= delay1;
end if;
end process;
tint <= savereg;
-- Kind of a hack
-- A long pulse, suitable for driving an LED or such like
-- Since it's only a visual indication we don't care that there's a delay between the trigger
-- pulse and the output pulse
-- At 100 MHz, the output pulse is 20 ms long (and delayed by up to 20 ms) if bit 21 is used
ledDriver: OneShot port map (trigger=>triggered,clk=>cnt(21),pulse=>ledPulse);
dataReady <= triggered;
end RTL;
--
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package TICounters is
component TICounter32 is port (
startTrig : in STD_LOGIC;
stopTrig : in STD_LOGIC;
clk : in STD_LOGIC;
tint : out STD_LOGIC_VECTOR(31 downto 0);
dataReady : out STD_LOGIC;
ledPulse : out STD_LOGIC
);
end component;
end TICounters;
|
mit
|
935d8e93ceaa7da0cc7f555e4976dcda
| 0.669373 | 3.5 | false | false | false | false |
Project-Bonfire/Bonfire
|
RTL/base_line/FIFO_one_hot_credit_based.vhd
| 5 | 5,364 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
credit_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
credit_out <= '0';
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
if read_en = '1' then
credit_out <= '1';
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in) begin
if valid_in = '1' and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
gpl-3.0
|
df5028c25784b785fbc3e347782d5356
| 0.486577 | 3.465116 | false | false | false | false |
metaspace/ghdl_extra
|
lfsr4/lfsr2.vhdl
| 1 | 5,485 |
-- file : lfsr2.vhdl
-- parameterised LFSR generator with 2 factors
-- table from http://www.physics.otago.ac.nz/px/research/
-- electronics/papers/technical-reports/lfsr_table.pdf
-- by Roy Ward, Tim Molteno, "Table of Linear Feedback Shift Registers"
-- version oct. 8 01:09:20 CEST 2010
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity lfsr2 is
generic(
size : integer := 7); -- default size
port(
-- control pins
clk, reset, din : in std_logic := '0';
-- all the bits from the shift register are available
lfsr : inout std_ulogic_vector(size downto 1);
-- leave "open" or connect to a constant only :
init_val : in std_ulogic_vector(size downto 1) := (1=>'1', others=>'0');
-- dedicated output :
s : out std_logic );
end lfsr2;
architecture fibonacci of lfsr2 is
type poly_array_type is array(2 to 785) of integer;
constant poly2_array : poly_array_type := (
2=>1, 3=>2, 4=>3, 5=>3, 6=>5, 7=>6, 9=>5, 10=>7,
11=>9, 15=>14, 17=>14, 18=>11, 20=>17, 21=>19, 22=>21, 23=>18,
25=>22, 28=>25, 29=>27, 31=>28, 33=>20, 35=>33, 36=>25, 39=>35,
41=>38, 47=>42, 49=>40, 52=>49, 55=>31, 57=>50, 58=>39, 60=>59,
63=>62, 65=>47, 68=>59, 71=>65, 73=>48, 79=>70, 81=>77, 84=>71,
87=>74, 89=>51, 93=>91, 94=>73, 95=>84, 97=>91, 98=>87, 100=>63,
103=>94, 105=>89, 106=>91, 108=>77, 111=>101, 113=>104, 118=>85, 119=>111,
121=>103, 123=>121, 124=>87, 127=>126, 129=>124, 130=>127, 132=>103, 134=>77,
135=>124, 137=>116, 140=>111, 142=>121, 145=>93, 148=>121, 150=>97, 151=>148,
153=>152, 159=>128, 161=>143, 167=>161, 169=>135, 170=>147, 172=>165, 174=>161,
175=>169, 177=>169, 178=>91, 183=>127, 185=>161, 191=>182, 193=>178, 194=>107,
198=>133, 199=>165, 201=>187, 202=>147, 207=>164, 209=>203, 212=>107, 215=>192,
217=>172, 218=>207, 223=>190, 225=>193, 231=>205, 233=>159, 234=>203, 236=>231,
239=>203, 241=>171, 247=>165, 249=>163, 250=>147, 252=>185, 255=>203, 257=>245,
258=>175, 263=>170, 265=>223, 266=>219, 268=>243, 270=>217, 271=>213, 273=>250,
274=>207, 278=>273, 279=>274, 281=>188, 282=>247, 284=>165, 286=>217, 287=>216,
289=>268, 292=>195, 294=>233, 295=>247, 297=>292, 300=>293, 302=>261, 305=>203,
313=>234, 314=>299, 316=>181, 319=>283, 321=>290, 322=>255, 327=>293, 329=>279,
332=>209, 333=>331, 337=>282, 342=>217, 343=>268, 345=>323, 350=>297, 351=>317,
353=>284, 359=>291, 362=>299, 364=>297, 366=>337, 367=>346, 369=>278, 370=>231,
375=>359, 377=>336, 378=>335, 380=>333, 382=>301, 383=>293, 385=>379, 386=>303,
390=>301, 391=>363, 393=>386, 394=>259, 396=>371, 399=>313, 401=>249, 404=>215,
406=>249, 407=>336, 409=>322, 412=>265, 415=>313, 417=>310, 422=>273, 423=>398,
425=>413, 428=>323, 431=>311, 433=>400, 436=>271, 438=>373, 439=>390, 441=>410,
446=>341, 447=>374, 449=>315, 450=>371, 455=>417, 457=>441, 458=>255, 460=>399,
462=>389, 463=>370, 465=>406, 470=>321, 471=>470, 474=>283, 476=>461, 478=>357,
479=>375, 481=>343, 484=>379, 487=>393, 489=>406, 490=>271, 494=>357, 495=>419,
497=>419, 503=>500, 505=>349, 506=>411, 508=>399, 511=>501, 513=>428, 518=>485,
519=>440, 521=>489, 524=>357, 527=>480, 529=>487, 532=>531, 537=>443, 540=>361,
543=>527, 545=>423, 550=>357, 551=>416, 553=>514, 556=>403, 559=>525, 561=>490,
564=>401, 566=>413, 567=>424, 569=>492, 570=>503, 574=>561, 575=>429, 577=>552,
582=>497, 583=>453, 585=>464, 588=>437, 590=>497, 593=>507, 594=>575, 599=>569,
601=>400, 607=>502, 609=>578, 610=>483, 615=>404, 617=>417, 622=>325, 623=>555,
625=>492, 628=>405, 631=>324, 633=>532, 634=>319, 639=>623, 641=>630, 642=>523,
646=>397, 647=>642, 649=>612, 650=>647, 652=>559, 655=>567, 657=>619, 658=>603,
662=>365, 663=>406, 665=>632, 670=>517, 671=>656, 673=>645, 676=>435, 679=>613,
686=>489, 687=>674, 689=>675, 692=>393, 695=>483, 697=>430, 698=>483, 702=>665,
705=>686, 708=>421, 711=>619, 713=>672, 714=>691, 716=>533, 719=>569, 721=>712,
722=>491, 726=>721, 727=>547, 729=>671, 730=>583, 735=>691, 737=>732, 738=>391,
740=>587, 743=>653, 745=>487, 746=>395, 751=>733, 753=>595, 754=>735, 756=>407,
759=>661, 761=>758, 762=>679, 767=>599, 769=>649, 772=>765, 774=>589, 775=>408,
777=>748, 778=>403, 782=>453, 783=>715, 785=>693, others=>0);
begin
process (clk, reset)
begin
assert poly2_array(size) > 0
report "Wrong size for LFSR2" severity failure;
-- initialisation
if reset = '1' then
lfsr <= init_val;
else
if rising_edge(clk) then
-- create the new bit
lfsr(1) <= lfsr(size)
xor lfsr(poly2_array(size))
xor din;
-- shift the register
lfsr(size downto 2) <= lfsr(size-1 downto 1);
end if;
end if;
end process;
-- update the output
s <= lfsr(1);
end fibonacci;
|
gpl-3.0
|
0abc649f2d12a5218ca9137460efe2f2
| 0.603829 | 2.726143 | false | false | false | false |
freecores/minimips
|
miniMIPS/src/pps_ex.vhd
| 1 | 8,966 |
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Execution stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
use work.alu;
entity pps_ex is
port(
clock : in std_logic;
reset : in std_logic;
stop_all : in std_logic; -- Unconditionnal locking of outputs
clear : in std_logic; -- Clear the pipeline stage
-- Datas from DI stage
DI_bra : in std_logic; -- Branch instruction
DI_link : in std_logic; -- Branch with link
DI_op1 : in bus32; -- Operand 1 for alu
DI_op2 : in bus32; -- Operand 2 for alu
DI_code_ual : in alu_ctrl_type; -- Alu operation
DI_offset : in bus32; -- Offset for address calculation
DI_adr_reg_dest : in adr_reg_type; -- Destination register address for the result
DI_ecr_reg : in std_logic; -- Effective writing of the result
DI_mode : in std_logic; -- Address mode (relative to pc ou index by a register)
DI_op_mem : in std_logic; -- Memory operation
DI_r_w : in std_logic; -- Type of memory operation (read or write)
DI_adr : in bus32; -- Instruction address
DI_exc_cause : in bus32; -- Potential cause exception
DI_level : in level_type; -- Availability stage of the result for bypassing
DI_it_ok : in std_logic; -- Allow hardware interruptions
-- Synchronous outputs to MEM stage
EX_adr : out bus32; -- Instruction address
EX_bra_confirm : out std_logic; -- Branch execution confirmation
EX_data_ual : out bus32; -- Ual result
EX_adresse : out bus32; -- Address calculation result
EX_adr_reg_dest : out adr_reg_type; -- Destination register for the result
EX_ecr_reg : out std_logic; -- Effective writing of the result
EX_op_mem : out std_logic; -- Memory operation needed
EX_r_w : out std_logic; -- Type of memory operation (read or write)
EX_exc_cause : out bus32; -- Potential cause exception
EX_level : out level_type; -- Availability stage of result for bypassing
EX_it_ok : out std_logic -- Allow hardware interruptions
);
end entity;
architecture rtl of pps_ex is
component alu
port (
clock : in bus1;
reset : in bus1;
op1 : in bus32; -- Operand 1
op2 : in bus32; -- Operand 2
ctrl : in alu_ctrl_type; -- Operation
res : out bus32; -- Result
overflow : out bus1 -- Overflow
);
end component;
signal res_ual : bus32; -- Alu result output
signal base_adr : bus32; -- Output of the address mode mux selection
signal pre_ecr_reg : std_logic; -- Output of mux selection for writing command to register
signal pre_data_ual : bus32; -- Mux selection of the data to write
signal pre_bra_confirm : std_logic; -- Result of the test in alu when branch instruction
signal pre_exc_cause : bus32; -- Preparation of the exception detection signal
signal overflow_ual : std_logic; -- Dectection of the alu overflow
begin
-- Alu instantiation
U1_alu : alu port map (clock => clock, reset => reset, op1=>DI_op1, op2=>DI_op2, ctrl=>DI_code_ual,
res=>res_ual, overflow=>overflow_ual);
-- Calculation of the future outputs
base_adr <= DI_op1 when DI_mode='0' else DI_adr;
pre_ecr_reg <= DI_ecr_reg when DI_link='0' else pre_bra_confirm;
pre_data_ual <= res_ual when DI_link='0' else bus32(unsigned(DI_adr) + 4);
pre_bra_confirm <= DI_bra and res_ual(0);
pre_exc_cause <= DI_exc_cause when DI_exc_cause/=IT_NOEXC else
IT_OVERF when overflow_ual='1' else
IT_NOEXC;
-- Set the synchronous outputs
process(clock) is
begin
if clock='1' and clock'event then
if reset='1' then
EX_adr <= (others => '0');
EX_bra_confirm <= '0';
EX_data_ual <= (others => '0');
EX_adresse <= (others => '0');
EX_adr_reg_dest <= (others => '0');
EX_ecr_reg <= '0';
EX_op_mem <= '0';
EX_r_w <= '0';
EX_exc_cause <= IT_NOEXC;
EX_level <= LVL_DI;
EX_it_ok <= '0';
elsif stop_all = '0' then
if clear = '1' then -- Clear the stage
EX_adr <= DI_adr;
EX_bra_confirm <= '0';
EX_data_ual <= (others => '0');
EX_adresse <= (others => '0');
EX_adr_reg_dest <= (others => '0');
EX_ecr_reg <= '0';
EX_op_mem <= '0';
EX_r_w <= '0';
EX_exc_cause <= IT_NOEXC;
EX_level <= LVL_DI;
EX_it_ok <= '0';
else -- Normal evolution
EX_adr <= DI_adr;
EX_bra_confirm <= pre_bra_confirm;
EX_data_ual <= pre_data_ual;
EX_adr_reg_dest <= DI_adr_reg_dest;
EX_ecr_reg <= pre_ecr_reg;
EX_op_mem <= DI_op_mem;
EX_r_w <= DI_r_w;
EX_exc_cause <= pre_exc_cause;
EX_level <= DI_level;
EX_it_ok <= DI_it_ok;
EX_adresse <= bus32(unsigned(DI_offset) + unsigned(base_adr));
end if;
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
cd479136bffcb82b12e045bc65574ce9
| 0.423489 | 4.759023 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_mdio.vhd
| 1 | 2,782 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_mdio IS
END tb_mdio;
ARCHITECTURE behavior OF tb_mdio IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mdio
PORT(
clk : IN std_logic;
rst : IN std_logic;
cnt_5 : in STD_LOGIC;
cnt_23 : IN std_logic;
mdc : OUT std_logic;
mdio_i : IN std_logic;
mdio_o : OUT std_logic;
mdio_t : OUT std_logic;
data : IN std_logic_vector(7 downto 0);
digit : OUT std_logic_vector(15 downto 0);
trgr : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal cnt64 : std_logic_vector(63 downto 0) := ( others => '0' );
signal mdio_i : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal trgr : std_logic := '0';
--Outputs
signal mdc : std_logic;
signal mdio_o : std_logic;
signal mdio_t : std_logic;
signal digit : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mdio PORT MAP (
clk => clk,
rst => rst,
cnt_5 => cnt64(5),
cnt_23 => cnt64(8),
mdc => mdc,
mdio_i => mdio_i,
mdio_o => mdio_o,
mdio_t => mdio_t,
data => data,
digit => digit,
trgr => trgr
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
cnt_64_p :process
begin
cnt64 <= cnt64 + 1;
wait for clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '0';
wait for 10 us;
trgr <= '1';
wait for 1 us;
trgr <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
58b0edc8bf4bffa38a49cc51ace1a1ea
| 0.596334 | 3.486216 | false | false | false | false |
cretingame/Yarr-fw
|
ip-cores/spartan6/fifo_64x512.vhd
| 2 | 7,679 |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:fifo_generator:6.2
-- You must compile the wrapper file fifo_64x512.vhd when simulating
-- the core, fifo_64x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_64x512 IS
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(63 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
prog_full_thresh_assert: in std_logic_vector(8 downto 0);
prog_full_thresh_negate: in std_logic_vector(8 downto 0);
dout: out std_logic_vector(63 downto 0);
full: out std_logic;
empty: out std_logic;
valid: out std_logic;
prog_full: out std_logic);
END fifo_64x512;
ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
-- synthesis translate_off
component wrapped_fifo_64x512
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(63 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
prog_full_thresh_assert: in std_logic_vector(8 downto 0);
prog_full_thresh_negate: in std_logic_vector(8 downto 0);
dout: out std_logic_vector(63 downto 0);
full: out std_logic;
empty: out std_logic;
valid: out std_logic;
prog_full: out std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 64,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 64,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 508,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 509,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x72",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_64x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_64x512_a;
|
gpl-3.0
|
797791c9c94d5b50a52062ee3d0df56f
| 0.546295 | 3.691827 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/rx-core/decode_8b10b/decode_8b10b_wrapper.vhd
| 1 | 8,781 |
-------------------------------------------------------------------------------
--
-- Module : decode_8b10b_wrapper.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder
--
-- Description : Top-level core wrapper file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY decode_8b10b;
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
ENTITY decode_8b10b_wrapper IS
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
ND : OUT STD_LOGIC := '0'
);
--------------------------------------------------------------------------------
-- Port Definitions:
--------------------------------------------------------------------------------
-- Mandatory Pins
-- CLK : Clock Input
-- DIN : Encoded Symbol Input
-- DOUT : Data Output, decoded data byte
-- KOUT : Command Output
-------------------------------------------------------------------------
-- Optional Pins
-- CLK_B : Clock Input (B port)
-- DIN_B : Encoded Symbol Input (B port)
-- DOUT_B : Data Output, decoded data byte (B port)
-- KOUT_B : Command Output (B port)
-- CE : Clock Enable
-- SINIT : Synchronous Initialization. Resets core to known state.
-- DISP_IN : Disparity Input (running disparity in)
-- CODE_ERR : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set.
-- DISP_ERR : Disparity Error
-- ND : New Data
-- RUN_DISP : Running Disparity
-- SYM_DISP : Symbol Disparity
-- CE_B : Clock Enable (B port)
-- SINIT_B : Synchronous Initialization. Resets core to known state.
-- (B port)
-- DISP_IN_B : Disparity Input (running disparity in) (B port)
-- CODE_ERR_B : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set. (B port)
-- DISP_ERR_B : Disparity Error (B port)
-- ND_B : New Data (B port)
-- RUN_DISP_B : Running Disparity (B port)
-- SYM_DISP_B : Symbol Disparity (B port)
----------------------------------------------------------------------------
END decode_8b10b_wrapper;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_wrapper IS
CONSTANT LOW : STD_LOGIC := '0';
CONSTANT HIGH : STD_LOGIC := '1';
CONSTANT LOWSLV : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
-------------------------------------------------------------------------------
-- BEGIN ARCHITECTURE
-------------------------------------------------------------------------------
BEGIN
dec : ENTITY decode_8b10b.decode_8b10b_top
GENERIC MAP (
C_DECODE_TYPE => 1,
C_HAS_BPORTS => 0,
C_HAS_CE => 1,
C_HAS_CODE_ERR => 1,
C_HAS_DISP_ERR => 1,
C_HAS_DISP_IN => 0,
C_HAS_ND => 1,
C_HAS_RUN_DISP => 0,
C_HAS_SINIT => 1,
C_HAS_SYM_DISP => 0,
C_SINIT_VAL => "0000000001",
C_SINIT_VAL_B => "0000000000"
)
PORT MAP(
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
KOUT => KOUT,
CE => CE,
SINIT => SINIT,
DISP_IN => LOW,
CODE_ERR => CODE_ERR,
DISP_ERR => DISP_ERR,
ND => ND,
RUN_DISP => open,
SYM_DISP => open,
CLK_B => LOW,
DIN_B => LOWSLV,
DOUT_B => open,
KOUT_B => open,
CE_B => HIGH,
SINIT_B => LOW,
DISP_IN_B => LOW,
CODE_ERR_B => open,
DISP_ERR_B => open,
ND_B => open,
RUN_DISP_B => open,
SYM_DISP_B => open
);
--------------------------------------------------------------------------------
-- Generic Definitions:
--------------------------------------------------------------------------------
-- C_DECODE_TYPE : Implementation: 0=LUT based, 1=BRAM based
-- C_HAS_BPORTS : 1 indicates second decoder should be generated
-- C_HAS_CE : 1 indicates ce(_b) port is present
-- C_HAS_CODE_ERR : 1 indicates code_err(_b) port is present
-- C_HAS_DISP_ERR : 1 indicates disp_err(_b) port is present
-- C_HAS_DISP_IN : 1 indicates disp_in(_b) port is present
-- C_HAS_ND : 1 indicates nd(_b) port is present
-- C_HAS_RUN_DISP : 1 indicates run_disp(_b) port is present
-- C_HAS_SINIT : 1 indicates sinit(_b) port is present
-- C_HAS_SYM_DISP : 1 indicates sym_disp(_b) port is present
-- C_SINIT_VAL : 10-bit binary string, dout/kout/run_disp init value
-- C_SINIT_VAL_B : 10-bit binary string, dout_b/kout_b/run_disp_b init
-- value
--------------------------------------------------------------------------------
--------------------------------------------------------
-- C_SINIT_VAL/C_SINIT_VAL_B {DOUT,KOUT,RD}
--------------------------------------------------------
-- D.0.0 (pos) DOUT: 000_00000 KOUT: 0 RD: 1
-- D.0.0 (neg) DOUT: 000_00000 KOUT: 0 RD: 0
-- D.10.2 (pos) DOUT: 010_01010 KOUT: 0 RD: 1
-- D.10.2 (neg) DOUT: 010_01010 KOUT: 0 RD: 0
-- D.21.5 (pos) DOUT: 101_10101 KOUT: 0 RD: 1
-- D.21.5 (neg) DOUT: 101_10101 KOUT: 0 RD: 0
--------------------------------------------------------
END xilinx;
|
gpl-3.0
|
1ec38cf5683df27544d4e531142b505b
| 0.453935 | 4.289692 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_ctrl_filter.vhd
| 1 | 2,839 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_ctrl_filter IS
END tb_ctrl_filter;
ARCHITECTURE behavior OF tb_ctrl_filter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ctrl_filter
port (Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector (7 downto 0);
PktOut : out std_logic;
DataOut : out std_logic_vector (7 downto 0);
CtrlEn : out std_logic;
CtrlData : out std_logic_vector (7 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal PktIn : std_logic := '0';
signal ByteIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal PktOut : std_logic;
signal ByteOut : std_logic_vector(7 downto 0);
signal CtrlEn : std_logic;
signal CtrlData : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ctrl_filter PORT MAP (
Clk => Clk,
Rst => Rst,
PktIn => PktIn,
DataIn => ByteIn,
PktOut => PktOut,
DataOut => ByteOut,
CtrlEn => CtrlEn,
CtrlData => CtrlData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
for j in 0 to 15 loop
PktIn <= '1';
for i in 1 to 7 loop
ByteIn <= x"55";
wait for Clk_period;
end loop;
ByteIn <= x"d5";
wait for Clk_period;
ByteIn <= x"00";
wait for Clk_period * 9;
for i in 1 to 15 loop
ByteIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*10;
end loop;
wait;
end process;
END;
|
gpl-3.0
|
57d03d225aa7feb9eee8ffe245506902
| 0.616414 | 3.584596 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
phy_tx.vhd
| 1 | 3,238 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Simple ethernet TX
-- takes data from bus, puts it into a async FIFO, kicks it onto the wire
entity phy_tx is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
PhyTxd : out STD_LOGIC_VECTOR (3 downto 0);
PhyTxEn : out STD_LOGIC;
PhyTxClk : in STD_LOGIC;
PhyTxEr : out STD_LOGIC;
Led : out std_logic_vector(1 downto 0);
-- Some temporary debug stuff
value : out std_logic_vector(15 downto 0);
sw : in std_logic_vector(7 downto 0);
data : in STD_LOGIC_VECTOR (7 downto 0);
busPkt : in STD_LOGIC;
busDesc : in STD_LOGIC
);
end phy_tx;
architecture Behavioral of phy_tx is
signal fifo_full, fifo_re, fifo_empty, fifo_valid : STD_LOGIC;
signal fifo_dout : std_logic_vector(3 downto 0);
COMPONENT async_fifo_tx
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Fifo has nibbles swapped
signal pktDataX : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
PhyTxEr <= '0';
PhyTxEn <= fifo_valid;
PhyTxd <= fifo_dout;
pktDataX <= data(3 downto 0) & data(7 downto 4);
fifo_re <= not fifo_empty;
Led(1) <= not fifo_empty;
Led(0) <= fifo_full;
xclk_fifo : async_fifo_tx
PORT MAP (
rst => rst,
wr_clk => clk,
rd_clk => PhyTxClk,
din => pktDataX,
wr_en => busPkt,
rd_en => fifo_re,
dout => fifo_dout,
full => fifo_full,
empty => fifo_empty,
valid => fifo_valid
);
main: process (PhyTxClk)
variable cnt : STD_LOGIC_VECTOR(9 downto 0);
begin
if RISING_EDGE(PhyTxClk) then
if fifo_valid = '1' then
if cnt(9 downto 2) = sw then
case cnt(1 downto 0) is
when b"10" =>
value( 3 downto 0) <= fifo_dout;
when b"11" =>
value( 7 downto 4) <= fifo_dout;
when b"00" =>
value(11 downto 8) <= fifo_dout;
when b"01" =>
value(15 downto 12) <= fifo_dout;
when others =>
value <= ( others => '0' );
end case;
end if;
cnt := cnt + 1;
else
cnt := (others => '0');
end if;
if rst = '1' then
value <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
f4199fe10f6752308bcd0b5d85079a92
| 0.612106 | 3.159024 | false | false | false | false |
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/top.vhd
| 1 | 8,129 |
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Jakub Cabal <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/mig_ddr3_wrapper_virtex6
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TOP is
generic(
-- DO NOT CHANGE THESE VALUES!
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per Rank for phy.
BANK_WIDTH : integer := 3; -- # of memory Bank Address bits.
CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory.
CKE_WIDTH : integer := 1; -- # of CKE outputs to memory.
CS_WIDTH : integer := 1; -- # of unique CS outputs to memory.
DM_WIDTH : integer := 8; -- # of Data Mask bits.
DQ_WIDTH : integer := 64; -- # of Data (DQ) bits.
DQS_WIDTH : integer := 8; -- # of DQS/DQS# bits.
ROW_WIDTH : integer := 14; -- # of memory Row Address bits.
-- ONLY FOR SIMULATION
SIM_BYPASS_INIT_CAL : string := "OFF"
);
Port (
ASYNC_RST : in std_logic;
CLK_REF_P : in std_logic;
CLK_REF_N : in std_logic;
-- UART INTERFACE
UART_TX : out std_logic;
UART_RX : in std_logic;
-- DDR3
DDR3_DQ : inout std_logic_vector(DQ_WIDTH-1 downto 0);
DDR3_DM : out std_logic_vector(DM_WIDTH-1 downto 0);
DDR3_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
DDR3_BA : out std_logic_vector(BANK_WIDTH-1 downto 0);
DDR3_RAS_N : out std_logic;
DDR3_CAS_N : out std_logic;
DDR3_WE_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_CS_N : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
DDR3_ODT : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
DDR3_CKE : out std_logic_vector(CKE_WIDTH-1 downto 0);
DDR3_DQS_P : inout std_logic_vector(DQS_WIDTH-1 downto 0);
DDR3_DQS_N : inout std_logic_vector(DQS_WIDTH-1 downto 0);
DDR3_CK_P : out std_logic_vector(CK_WIDTH-1 downto 0);
DDR3_CK_N : out std_logic_vector(CK_WIDTH-1 downto 0);
PHY_INIT_DONE : out std_logic
);
end TOP;
architecture FULL of TOP is
-- USER CLOCK AND RESET
signal user_clk : std_logic;
signal user_rst : std_logic;
-- UART SIGNALS
signal uart_data_out : std_logic_vector(7 downto 0);
signal uart_data_vld : std_logic;
signal uart_error : std_logic;
signal uart_data_in : std_logic_vector(7 downto 0);
signal uart_data_en : std_logic;
signal uart_busy : std_logic;
-- MIG WRAPPER SIGNALS
signal mig_addr : std_logic_vector(24 downto 0);
signal mig_ready : std_logic;
signal mig_wr_data : std_logic_vector(511 downto 0);
signal mig_wr_en : std_logic;
signal mig_rd_en : std_logic;
signal mig_rd_data : std_logic_vector(511 downto 0);
signal mig_rd_data_vld : std_logic;
begin
-- -------------------------------------------------------------------------
-- UART MODULE
-- -------------------------------------------------------------------------
uart_i: entity work.UART
generic map (
BAUD_RATE => 115200,
DATA_BITS => 8,
PARITY_BIT => "even",
CLK_FREQ => 200e6,
INPUT_FIFO => False, -- Attention, FIFO does not yet work properly!
FIFO_DEPTH => 256
)
port map (
CLK => user_clk,
RST => user_rst,
-- UART INTERFACE
TX_UART => UART_TX,
RX_UART => UART_RX,
-- USER DATA OUTPUT INTERFACE
DATA_OUT => uart_data_out,
DATA_VLD => uart_data_vld,
FRAME_ERROR => uart_error,
-- USER DATA INPUT INTERFACE
DATA_IN => uart_data_in,
DATA_SEND => uart_data_en,
BUSY => uart_busy
);
-- -------------------------------------------------------------------------
-- DATA GENERATOR MODULE
-- -------------------------------------------------------------------------
data_generator_i: entity work.DATA_GENERATOR
port map (
-- CLOCK AND RESETS
CLK => user_clk,
RST => user_rst,
-- USER INTERFACE TO UART MODULE
UART_WR_DATA => uart_data_in,
UART_WR_EN => uart_data_en,
UART_BUSY => uart_busy,
UART_RD_DATA => uart_data_out,
UART_RD_DATA_VLD => uart_data_vld,
UART_FRAME_ERROR => uart_error,
-- MIG WRAPPER INTERFACE
MIG_ADDR => mig_addr,
MIG_READY => mig_ready,
MIG_RD_EN => mig_rd_en,
MIG_WR_EN => mig_wr_en,
MIG_WR_DATA => mig_wr_data,
MIG_RD_DATA => mig_rd_data,
MIG_RD_DATA_VLD => mig_rd_data_vld
);
-- -------------------------------------------------------------------------
-- MIG DDR3 WRAPPER MODULE
-- -------------------------------------------------------------------------
mig_wrapper_i : entity work.MIG_WRAPPER
generic map(
nCS_PER_RANK => nCS_PER_RANK,
BANK_WIDTH => BANK_WIDTH,
CK_WIDTH => CK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
CS_WIDTH => CS_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DM_WIDTH => DM_WIDTH,
DQS_WIDTH => DQS_WIDTH,
ROW_WIDTH => ROW_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL
)
port map(
-- CLOCK AND RESETS
CLK_REF_P => CLK_REF_P,
CLK_REF_N => CLK_REF_N,
ASYNC_RST => ASYNC_RST,
USER_CLK_OUT => user_clk,
USER_RST_OUT => user_rst,
-- USER INTERFACE
MIG_ADDR => mig_addr,
MIG_READY => mig_ready,
MIG_RD_EN => mig_rd_en,
MIG_WR_EN => mig_wr_en,
MIG_WR_DATA => mig_wr_data,
MIG_RD_DATA => mig_rd_data,
MIG_RD_DATA_VLD => mig_rd_data_vld,
-- DDR3 INTERFACE
DDR3_DQ => DDR3_DQ,
DDR3_DM => DDR3_DM,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CS_N => DDR3_CS_N,
DDR3_ODT => DDR3_ODT,
DDR3_CKE => DDR3_CKE,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
PHY_INIT_DONE => PHY_INIT_DONE
);
end FULL;
|
mit
|
6887bb4ad3329005e0e0d4a4353b0588
| 0.49551 | 3.710178 | false | false | false | false |
starsheriff/papilio-one250
|
uart_4/main.vhd
| 1 | 1,786 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_transmitter is
Port(
clk : in STD_LOGIC;
data_out : out STD_LOGIC;
switches : in STD_LOGIC_VECTOR(7 downto 0);
leds : out STD_LOGIC_VECTOR(7 downto 0);
JOY_PUSH : in STD_LOGIC
);
end serial_transmitter;
architecture Behavioral of serial_transmitter is
signal data_shiftreg : std_logic_vector(9 downto 0) := (others => '1');
signal busy_shiftreg : std_logic_vector(9 downto 0) := (others => '0');
signal counter : std_logic_vector(12 downto 0) := (others => '0');
signal data_byte : std_logic_vector(7 downto 0) := (others => '1');
--signal data_buf : std_logic_vector(7 downto 0) := (others => '0');
signal send : std_logic := '0';
signal sig_old : std_logic := '0';
begin
data_out <= data_shiftreg(0);
--debug_out <= shiftreg(0);
leds <= switches;
send <= not JOY_PUSH;
data_byte <= switches;
process(clk)
begin
if rising_edge(clk) then
if busy_shiftreg(0) = '0' then
sig_old <= send;
if sig_old='0' and send='1' then
-- least significant bit is 0 indicating that the line is free
-- now set the whole shiftregister to 1, indicating that the line is busy
busy_shiftreg <= (others => '1');
data_shiftreg <= '1' & data_byte & '0';
counter <= (others => '0');
end if;
else
if counter=3332 then
data_shiftreg <= '1' & data_shiftreg(9 downto 1);
busy_shiftreg <= '0' & busy_shiftreg(9 downto 1);
counter <= (others => '0');
else
counter <= counter + 1;
end if; -- counter
end if; -- rising_edge
end if;
end process;
end Behavioral;
|
gpl-2.0
|
c635d196510404dc6f50e718f081ee35
| 0.589026 | 3.508841 | false | false | false | false |
openttp/openttp
|
software/system/src/fpga/vhdl/PPSToCR.vhd
| 1 | 2,481 |
----------------------------------------------------------------------------------
--
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Michael J. Wouters
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.TRIGGERS.OneShot;
entity PPSToCR is
port( trigger : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC);
end PPSToCR;
architecture Behavioral of PPSToCR is
type fsm_type is (ST_WAIT,ST_TRIGGERED);
signal curr_state: fsm_type;
signal trig_pulse: STD_LOGIC;
constant ser_cr : STD_LOGIC_VECTOR(0 to 9) := "0101100001";
begin
process (clk)
variable clk_div_cnt: natural range 0 to 1023:=0;
variable bit_cnt: natural range 0 to 15:=0;
begin
if rising_edge(clk) then
case curr_state is
when ST_WAIT =>
curr_state <= ST_WAIT;
serial_out <= '1';
if trig_pulse='1' then
curr_state <= ST_TRIGGERED;
end if;
when ST_TRIGGERED=>
serial_out<=ser_cr(bit_cnt);
clk_div_cnt:=clk_div_cnt+1;
if clk_div_cnt = 868 then -- main clock divider
bit_cnt := bit_cnt+1;
clk_div_cnt:=0;
if bit_cnt=10 then
curr_state <= ST_WAIT;
bit_cnt:=0;
clk_div_cnt:=0;
end if;
end if;
when others =>
curr_state <= ST_WAIT;
serial_out <= '1';
end case;
end if;
end process;
trigin: OneShot port map (trigger=>trigger,clk=>clk,pulse=>trig_pulse);
end Behavioral;
|
mit
|
4b1f1642f2b3e4b5566b5de7bbcd708b
| 0.670697 | 3.460251 | false | false | false | false |
SteelRaven7/soundbox-vhdl
|
Source/Effects/EffectEcho.vhd
| 1 | 4,877 |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.fixed_pkg.all;
entity EffectEcho is
generic (
wordLength : natural := 16;
constantsWordLength : natural := 16
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
);
end entity ; -- EffectEcho
architecture arch of EffectEcho is
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
constant delayDuration : natural := 2;
constant decayGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(-0.5, constantsWordLength);
constant directGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.8, constantsWordLength);
constant echoGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.5, constantsWordLength);
-- 2 second max delay
constant addressWidth : natural := 17;
constant addressMax : natural := 44100;
signal feedback : std_logic_vector(wordLength-1 downto 0);
signal directGained : std_logic_vector(wordLength-1 downto 0);
signal delayedGained : std_logic_vector(wordLength-1 downto 0);
signal delayed : std_logic_vector(wordLength-1 downto 0);
signal feedbackDirectSum : std_logic_vector(wordLength-1 downto 0);
signal writeBus : std_logic_vector(wordLength-1 downto 0);
signal readBus : std_logic_vector(wordLength-1 downto 0);
signal writeEnable : std_logic_vector(0 downto 0);
signal memoryAddress : std_logic_vector(addressWidth-1 downto 0);
type state_type is (readStart, readWait, read, writeDone);
constant waitTime : natural := 4;
type reg_type is record
state : state_type;
waitCounter : natural range 0 to waitTime;
address : unsigned(addressWidth-1 downto 0);
writeEnable : std_logic;
delayedOutput : std_logic_vector(wordLength-1 downto 0);
end record;
signal r, rin : reg_type;
begin
-- Summation
feedbackSum : entity work.AdderSat
generic map (
wordLength => wordLength
)
port map (
a => input,
b => feedback,
s => feedbackDirectSum
);
outputSum : entity work.AdderSat
generic map (
wordLength => wordLength
)
port map (
a => directGained,
b => delayedGained,
s => output
);
-- Gains
directMult : entity work.Multiplier
generic map (
X_WIDTH => wordLength,
X_FRACTION => wordLength-1,
Y_WIDTH => constantsWordLength,
Y_FRACTION => constantsWordLength-1,
S_WIDTH => wordLength,
S_FRACTION => wordLength-1
)
port map (
x => input,
y => directGain,
s => directGained
);
feedbackMult : entity work.Multiplier
generic map (
X_WIDTH => wordLength,
X_FRACTION => wordLength-1,
Y_WIDTH => constantsWordLength,
Y_FRACTION => constantsWordLength-1,
S_WIDTH => wordLength,
S_FRACTION => wordLength-1
)
port map (
x => delayed,
y => decayGain,
s => feedback
);
echoMult : entity work.Multiplier
generic map (
X_WIDTH => wordLength,
X_FRACTION => wordLength-1,
Y_WIDTH => constantsWordLength,
Y_FRACTION => constantsWordLength-1,
S_WIDTH => wordLength,
S_FRACTION => wordLength-1
)
port map (
x => delayed,
y => echoGain,
s => delayedGained
);
-- Delay
writeBus <= feedbackDirectSum;
writeEnable <= (others => r.writeEnable);
delayed <= r.delayedOutput;
memoryAddress <= std_logic_vector(r.address);
memory: blk_mem_gen_0
port map (
dina => writeBus,
wea => writeEnable,
doutb => readBus,
clka => clk,
clkb => clk,
addra => memoryAddress,
addrb => memoryAddress
);
clk_proc : process( clk, reset )
begin
if(reset = '1') then
r.state <= readStart;
r.address <= (others => '0');
r.writeEnable <= '0';
r.delayedOutput <= (others => '0');
elsif(rising_edge(clk)) then
r <= rin;
end if;
end process ; -- clk_proc
comb_proc : process( r, rin, readBus)
variable v : reg_type;
begin
v := r;
v.writeEnable := '0';
case r.state is
when readStart =>
v.state := readWait;
v.waitCounter := 0;
when readWait =>
-- Wait some cycles before reading
if(r.waitCounter >= waitTime) then
v.state := read;
else
v.waitCounter := r.waitCounter + 1;
end if;
when read =>
v.state := writeDone;
-- Write the new value
v.writeEnable := '1';
-- Result is ready, read it.
v.delayedOutput := readBus;
when writeDone =>
v.state := readStart;
if(r.address = addressMax-1) then
v.address := (others => '0');
else
v.address := v.address + 1;
end if;
when others =>
-- Don't care
end case;
rin <= v;
end process ; -- comb_proc
end architecture ; -- arch
|
mit
|
65ef8f004eb08bd311e0b82e7628857f
| 0.661472 | 3.181344 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/kintex7/app.vhd
| 1 | 56,713 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/18/2016 01:10:56 PM
-- Design Name:
-- Module Name: app - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.app_pkg.all;
entity app is
Generic(
AXI_BUS_WIDTH : integer := 64;
axis_data_width_c : integer := 64;
axis_rx_tkeep_width_c : integer := 64/8;
axis_rx_tuser_width_c : integer := 22;
wb_address_width_c : integer := 32;
wb_data_width_c : integer := 32;
address_mask_c : STD_LOGIC_VECTOR(32-1 downto 0) := X"000FFFFF";
DMA_MEMORY_SELECTED : string := "DDR3" -- DDR3, BRAM, DEMUX
);
Port ( clk_i : in STD_LOGIC;
sys_clk_n_i : IN STD_LOGIC;
sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
user_lnk_up_i : in STD_LOGIC;
user_app_rdy_i : in STD_LOGIC;
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
-- PCIe debug
tx_err_drop_i: in STD_LOGIC;
cfg_dstatus_i : in STD_LOGIC_VECTOR(15 DOWNTO 0);
--DDR3
ddr3_dq_io : inout std_logic_vector(63 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(7 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(7 downto 0);
--init_calib_complete_o : out std_logic;
ddr3_addr_o : out std_logic_vector(14 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(0 downto 0);
ddr3_ck_n_o : out std_logic_vector(0 downto 0);
ddr3_cke_o : out std_logic_vector(0 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_dm_o : out std_logic_vector(7 downto 0);
ddr3_odt_o : out std_logic_vector(0 downto 0);
--I/O
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
front_led_o : out STD_LOGIC_VECTOR (3 downto 0)
);
end app;
architecture Behavioral of app is
constant DEBUG_C : std_logic_vector(5 downto 0) := "000000";
signal rst_n_s : std_logic;
signal count_s : STD_LOGIC_VECTOR (28 downto 0);
signal gray_count_s : STD_LOGIC_VECTOR (28 downto 0);
signal ddr_count_s : STD_LOGIC_VECTOR (28 downto 0);
signal eop_s : std_logic; -- Arbiter end of operation
signal cfg_interrupt_s : std_logic;
signal pcie_id_s : std_logic_vector (15 downto 0); -- Completer/Requester ID
---------------------------------------------------------
-- debug signals
signal wbm_states_ds : STD_LOGIC_VECTOR(3 downto 0);
signal wbm_op_ds : STD_LOGIC_VECTOR(2 downto 0);
signal wbm_header_type_ds : STD_LOGIC;
signal wbm_payload_length_ds : STD_LOGIC_VECTOR(9 downto 0);
signal wbm_address_ds : STD_LOGIC_VECTOR(31 downto 0);
signal dma_ctrl_current_state_ds : std_logic_vector (2 downto 0);
signal dma_ctrl_ds : std_logic_vector(31 downto 0);
signal dma_stat_ds : std_logic_vector(31 downto 0);
signal dma_attrib_ds : std_logic_vector(31 downto 0);
---------------------------------------------------------
-- CSR Wishbone bus
signal wb_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_cyc_s : STD_LOGIC;
signal wb_sel_s : STD_LOGIC_VECTOR (4 - 1 downto 0);
signal wb_stb_s : STD_LOGIC;
signal wb_we_s : STD_LOGIC;
signal wb_ack_s : STD_LOGIC;
signal wb_stall_s : std_logic; -- Stall
signal wb_err_s : std_logic; -- Error
signal wb_rty_s : std_logic; -- Retry
signal wb_int_s : std_logic; -- Interrupt
signal wb_dma_ctrl_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_dma_ctrl_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dma_ctrl_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dma_ctrl_cyc_s : STD_LOGIC;
--signal wb_dma_ctrl_sel_s : STD_LOGIC_VECTOR (wb_data_width_c/8 - 1 downto 0);
signal wb_dma_ctrl_stb_s : STD_LOGIC;
signal wb_dma_ctrl_we_s : STD_LOGIC;
signal wb_dma_ctrl_ack_s : STD_LOGIC;
signal wb_mem_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_mem_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_mem_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_mem_cyc_s : STD_LOGIC;
--signal wb_mem_sel_s : STD_LOGIC_VECTOR (wb_data_width_c/8 - 1 downto 0);
signal wb_mem_stb_s : STD_LOGIC;
signal wb_mem_we_s : STD_LOGIC;
signal wb_mem_ack_s : STD_LOGIC;
signal wb_dbg_adr_s : STD_LOGIC_VECTOR (32 - 1 downto 0);
signal wb_dbg_dat_m2s_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dbg_dat_s2m_s : STD_LOGIC_VECTOR (wb_data_width_c - 1 downto 0);
signal wb_dbg_cyc_s : std_logic;
signal wb_dbg_sel_s : STD_LOGIC_VECTOR (wb_data_width_c/8 - 1 downto 0);
signal wb_dbg_stb_s : STD_LOGIC;
signal wb_dbg_we_s : STD_LOGIC;
signal wb_dbg_ack_s : STD_LOGIC;
---------------------------------------------------------
-- Slave AXI-Stream from arbiter to pcie_tx
signal s_axis_rx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal s_axis_rx_tuser_s : STD_LOGIC_VECTOR (21 downto 0);
signal s_axis_rx_tlast_s : STD_LOGIC;
signal s_axis_rx_tvalid_s :STD_LOGIC;
signal s_axis_rx_tready_s : STD_LOGIC;
---------------------------------------------------------
-- Master AXI-Stream pcie_rx to wishbone master
signal m_axis_tx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal m_axis_tx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal m_axis_tx_tuser_s : STD_LOGIC_VECTOR (3 downto 0);
signal m_axis_tx_tlast_s : STD_LOGIC;
signal m_axis_tx_tvalid_s : STD_LOGIC;
signal m_axis_tx_tready_s : STD_LOGIC;
---------------------------------------------------------
-- From Wishbone master (wbm) to L2P DMA
signal pd_wbm_address_s : STD_LOGIC_VECTOR(63 downto 0);
signal pd_wbm_data_s : STD_LOGIC_VECTOR(31 downto 0);
signal p2l_wbm_rdy_s : std_logic;
signal pd_pdm_data_valid_w_s : std_logic_vector(1 downto 0);
signal pd_wbm_valid_s : std_logic;
signal pd_wbm_hdr_rid_s : std_logic_vector(15 downto 0); -- Requester ID
signal pd_wbm_hdr_tag_s : std_logic_vector(7 downto 0);
signal pd_wbm_target_mrd_s : std_logic; -- Target memory read
signal pd_wbm_target_mwr_s : std_logic;
signal wbm_pd_ready_s : std_logic;
signal pd_op_s : STD_LOGIC_VECTOR(2 downto 0);
signal pd_header_type_s : STD_LOGIC;
signal pd_payload_length_s : STD_LOGIC_VECTOR(9 downto 0);
---------------------------------------------------------
-- From Wishbone master (wbm) to L2P DMA
signal pd_pdm_data_valid_s : STD_LOGIC;
signal pd_pdm_data_last_s : STD_LOGIC;
signal pd_pdm_data_s : STD_LOGIC_VECTOR(axis_data_width_c - 1 downto 0);
signal pd_pdm_keep_s : std_logic_vector(7 downto 0);
signal p2l_dma_rdy_s : std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
signal wbm_arb_tdata_s : std_logic_vector (axis_data_width_c - 1 downto 0);
signal wbm_arb_tkeep_s : std_logic_vector (axis_data_width_c/8 - 1 downto 0);
signal wbm_arb_tlast_s : std_logic;
signal wbm_arb_tvalid_s : std_logic;
signal wbm_arb_req_s : std_logic;
signal wbm_arb_tready_s : std_logic;
signal dma_ctrl_irq_s : std_logic_vector(1 downto 0);
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
signal dma_ctrl_carrier_addr_s : std_logic_vector(31 downto 0);
signal dma_ctrl_host_addr_h_s : std_logic_vector(31 downto 0);
signal dma_ctrl_host_addr_l_s : std_logic_vector(31 downto 0);
signal dma_ctrl_len_s : std_logic_vector(31 downto 0);
signal dma_ctrl_start_l2p_s : std_logic; -- To the L2P DMA master
signal dma_ctrl_start_p2l_s : std_logic; -- To the P2L DMA master
signal dma_ctrl_start_next_s : std_logic; -- To the P2L DMA master
signal dma_ctrl_byte_swap_s : std_logic_vector(1 downto 0);
signal dma_ctrl_abort_s : std_logic;
signal dma_ctrl_done_s : std_logic;
signal dma_ctrl_error_s : std_logic;
signal dma_ctrl_l2p_done_s : std_logic;
signal dma_ctrl_l2p_error_s : std_logic;
signal dma_ctrl_p2l_done_s : std_logic;
signal dma_ctrl_p2l_error_s : std_logic;
---------------------------------------------------------
-- From P2L DMA master
signal next_item_carrier_addr_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_h_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_l_s : std_logic_vector(31 downto 0);
signal next_item_len_s : std_logic_vector(31 downto 0);
signal next_item_next_l_s : std_logic_vector(31 downto 0);
signal next_item_next_h_s : std_logic_vector(31 downto 0);
signal next_item_attrib_s : std_logic_vector(31 downto 0);
signal next_item_valid_s : std_logic;
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
signal pdm_arb_tvalid_s : std_logic; -- Read completion signals
signal pdm_arb_tlast_s : std_logic; -- Toward the arbiter
signal pdm_arb_tdata_s : std_logic_vector(63 downto 0);
signal pdm_arb_tkeep_s : std_logic_vector(7 downto 0);
signal pdm_arb_req_s : std_logic;
signal pdm_arb_tready_s : std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
signal p2l_dma_adr_s : std_logic_vector(31 downto 0); -- Adress
signal p2l_dma_dat_s2m_s : std_logic_vector(63 downto 0); -- Data in
signal p2l_dma_dat_m2s_s : std_logic_vector(63 downto 0); -- Data out
signal p2l_dma_sel_s : std_logic_vector(7 downto 0); -- Byte select
signal p2l_dma_cyc_s : std_logic; -- Read or write cycle
signal p2l_dma_stb_s : std_logic; -- Read or write strobe
signal p2l_dma_we_s : std_logic; -- Write
signal p2l_dma_ack_s : std_logic; -- Acknowledge
signal p2l_dma_stall_s : std_logic; -- for pipelined Wishbone
signal l2p_dma_adr_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_dat_s2m_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_dat_m2s_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_sel_s : std_logic_vector(3 downto 0);
signal l2p_dma_cyc_s : std_logic;
signal l2p_dma_stb_s : std_logic;
signal l2p_dma_we_s : std_logic;
signal l2p_dma_ack_s : std_logic;
signal l2p_dma_stall_s : std_logic;
signal dma_adr_s : std_logic_vector(31 downto 0); -- Adress
signal dma_dat_s2m_s : std_logic_vector(63 downto 0); -- Data in
signal dma_dat_m2s_s : std_logic_vector(63 downto 0); -- Data out
signal dma_sel_s : std_logic_vector(7 downto 0); -- Byte select
signal dma_cyc_s : std_logic; -- Read or write cycle
signal dma_stb_s : std_logic; -- Read or write strobe
signal dma_we_s : std_logic; -- Write
signal dma_ack_s : std_logic; -- Acknowledge
signal dma_stall_s : std_logic; -- for pipelined Wishbone
signal l2p_current_state_ds : std_logic_vector (2 downto 0);
signal l2p_data_cnt_ds : unsigned(12 downto 0);
signal l2p_len_cnt_ds : unsigned(12 downto 0);
signal l2p_timeout_cnt_ds : unsigned(12 downto 0);
signal wb_timeout_cnt_ds : unsigned(12 downto 0);
-- Data FIFO
signal data_fifo_rd_ds : std_logic;
signal data_fifo_wr_ds : std_logic;
signal data_fifo_empty_ds : std_logic;
signal data_fifo_full_ds : std_logic;
signal data_fifo_dout_ds : std_logic_vector(axis_data_width_c-1 downto 0);
signal data_fifo_din_ds : std_logic_vector(axis_data_width_c-1 downto 0);
-- Addr FIFO
signal addr_fifo_rd_ds : std_logic;
signal addr_fifo_wr_ds : std_logic;
signal addr_fifo_empty_ds : std_logic;
signal addr_fifo_full_ds : std_logic;
signal addr_fifo_dout_ds : std_logic_vector(64-1 downto 0);
signal addr_fifo_din_ds : std_logic_vector(axis_data_width_c-1 downto 0);
--constant cyc_nb_exp_c : integer := 2;
--constant cyc_nb_c : integer := 2**cyc_nb_exp_c;
--type ram_dma_data_bus is array (cyc_nb_c-1 downto 0) of std_logic_vector(64-1 downto 0);
signal dummyram_sel_s : std_logic;
signal ddr3ram_sel_s : std_logic;
signal dummyaddress_sel_s : std_logic;
signal dummydeadbeef_sel_s : std_logic;
---------------------------------------------------------
-- From DMA master to Dummy RAM
signal dma_bram_adr_s : std_logic_vector(32-1 downto 0); -- Adress
signal dma_bram_dat_s2m_s : std_logic_vector(64-1 downto 0); -- Data in
signal dma_bram_dat_m2s_s : std_logic_vector(64-1 downto 0); -- Data out
signal dma_bram_sel_s : std_logic_vector(8-1 downto 0); -- Byte select
signal dma_bram_cyc_s : std_logic; -- Read or write cycle
signal dma_bram_stb_s : std_logic; -- Read or write strobe
signal dma_bram_we_s : std_logic; -- Write
signal dma_bram_ack_s : std_logic; -- Acknowledge
signal dma_bram_stall_s : std_logic; -- for pipelined Wishbone
---------------------------------------------------------
-- From DMA master to DDR3 control
signal dma_ddr_addr_s : std_logic_vector(32-1 downto 0); -- Adress
signal dma_ddr_dat_s2m_s : std_logic_vector(64-1 downto 0); -- Data in
signal dma_ddr_dat_m2s_s : std_logic_vector(64-1 downto 0); -- Data out
signal dma_ddr_sel_s : std_logic_vector(8-1 downto 0); -- Byte select
signal dma_ddr_cyc_s : std_logic; -- Read or write cycle
signal dma_ddr_stb_s : std_logic; -- Read or write strobe
signal dma_ddr_we_s : std_logic; -- Write
signal dma_ddr_ack_s : std_logic; -- Acknowledge
signal dma_ddr_stall_s : std_logic; -- for pipelined Wishbone
---------------------------------------------------------
-- DDR3 control to output
signal ddr3_dq_s : std_logic_vector(63 downto 0);
signal ddr3_dqs_p_s : std_logic_vector(7 downto 0);
signal ddr3_dqs_n_s : std_logic_vector(7 downto 0);
signal init_calib_complete_s : std_logic;
signal ddr3_addr_s : std_logic_vector(14 downto 0);
signal ddr3_ba_s : std_logic_vector(2 downto 0);
signal ddr3_ras_n_s : std_logic;
signal ddr3_cas_n_s : std_logic;
signal ddr3_we_n_s : std_logic;
signal ddr3_reset_n_s : std_logic;
signal ddr3_ck_p_s : std_logic_vector(0 downto 0);
signal ddr3_ck_n_s : std_logic_vector(0 downto 0);
signal ddr3_cke_s : std_logic_vector(0 downto 0);
signal ddr3_cs_n_s : std_logic_vector(0 downto 0);
signal ddr3_dm_s : std_logic_vector(7 downto 0);
signal ddr3_odt_s : std_logic_vector(0 downto 0);
---------------------------------------------------------
-- DDR3 control to MIG
signal ddr_app_addr_s : std_logic_vector(28 downto 0);
signal ddr_app_cmd_s : std_logic_vector(2 downto 0);
signal ddr_app_cmd_en_s : std_logic;
signal ddr_app_wdf_data_s : std_logic_vector(511 downto 0);
signal ddr_app_wdf_end_s : std_logic;
signal ddr_app_wdf_mask_s : std_logic_vector(63 downto 0);
signal ddr_app_wdf_wren_s : std_logic;
signal ddr_app_rd_data_s : std_logic_vector(511 downto 0);
signal ddr_app_rd_data_end_s : std_logic;
signal ddr_app_rd_data_valid_s : std_logic;
signal ddr_app_rdy_s : std_logic;
signal ddr_app_wdf_rdy_s : std_logic;
signal ddr_app_ui_clk_s : std_logic;
signal ddr_app_ui_clk_sync_rst_s : std_logic;
----------------------------------------------------------------------------
-- DDR3 Debug signalss
signal ddr_rd_fifo_full_ds : std_logic_vector(1 downto 0);
signal ddr_rd_fifo_empty_ds : std_logic_vector(1 downto 0);
signal ddr_rd_fifo_rd_ds : std_logic_vector(1 downto 0);
signal ddr_rd_mask_rd_data_count_ds : std_logic_vector(3 downto 0);
signal ddr_rd_data_rd_data_count_ds : std_logic_vector(3 downto 0);
signal ddr_wb_rd_mask_dout_ds : std_logic_vector(7 downto 0);
signal ddr_wb_rd_mask_addr_dout_ds : std_logic_vector(29-1 downto 0);
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
signal ldm_arb_tdata_s : std_logic_vector (axis_data_width_c - 1 downto 0);
signal ldm_arb_tkeep_s : std_logic_vector (axis_data_width_c/8 - 1 downto 0);
signal ldm_arb_tlast_s : std_logic;
signal ldm_arb_tvalid_s : std_logic;
signal ldm_arb_tready_s : std_logic;
signal ldm_arb_req_s : std_logic;
--signal arb_ldm_gnt_s : std_logic;
begin
rst_n_s <= not rst_i;
s_axis_rx_tdata_s <= s_axis_rx_tdata_i;
s_axis_rx_tkeep_s <= s_axis_rx_tkeep_i;
s_axis_rx_tlast_s <= s_axis_rx_tlast_i;
s_axis_rx_tready_o <= s_axis_rx_tready_s;
s_axis_rx_tuser_s <= s_axis_rx_tuser_i;
s_axis_rx_tvalid_s <= s_axis_rx_tvalid_i;
-- Master AXI-Stream
m_axis_tx_tdata_o <= m_axis_tx_tdata_s;
m_axis_tx_tkeep_o <= m_axis_tx_tkeep_s;
m_axis_tx_tuser_o <= m_axis_tx_tuser_s;
m_axis_tx_tlast_o <= m_axis_tx_tlast_s;
m_axis_tx_tvalid_o <= m_axis_tx_tvalid_s;
m_axis_tx_tready_s <= m_axis_tx_tready_i;
cfg_interrupt_assert_o <= '0';
cfg_interrupt_di_o <= (others => '0');
cfg_interrupt_stat_o <= '0';
cfg_pciecap_interrupt_msgnum_o <= (others => '0');
cfg_interrupt_o <= cfg_interrupt_s;
pcie_id_s <= cfg_bus_number_i & cfg_device_number_i & cfg_function_number_i;
wbm_pd_ready_s <= p2l_wbm_rdy_s and p2l_dma_rdy_s;
interrupt_p : process(rst_i,clk_i)
begin
if (rst_i = '1') then
cfg_interrupt_s <= '0';
elsif(clk_i'event and clk_i = '1') then
cfg_interrupt_s <= cfg_interrupt_s;
if (cfg_interrupt_rdy_i = '1') then
cfg_interrupt_s <= '0';
end if;
if (dma_ctrl_irq_s /= "00") then
cfg_interrupt_s <= '1';
end if;
end if;
end process interrupt_p;
cnt:simple_counter
port map(
enable_i => dma_ctrl_irq_s(0),
rst_i => rst_i,
clk_i => clk_i,
count_o => count_s,
gray_count_o => gray_count_s
);
cnt_sync:m_clk_sync
Generic map(
data_width_g => 29
)
Port map(
rst0_i => rst_i,
rst1_i => ddr_app_ui_clk_sync_rst_s,
clk0_i => clk_i,
clk1_i => ddr_app_ui_clk_s,
data0_i => count_s,
data1_o => ddr_count_s
);
p2l_dec_comp:p2l_decoder
port map(
clk_i => clk_i,
rst_i => rst_i,
-- Slave AXI-Stream
s_axis_rx_tdata_i => s_axis_rx_tdata_s,
s_axis_rx_tkeep_i => s_axis_rx_tkeep_s,
s_axis_rx_tlast_i => s_axis_rx_tlast_s,
s_axis_rx_tready_o => s_axis_rx_tready_s,
s_axis_rx_tuser_i => s_axis_rx_tuser_s,
s_axis_rx_tvalid_i => s_axis_rx_tvalid_s,
-- To the wishbone master
pd_wbm_address_o => pd_wbm_address_s,
pd_wbm_data_o => pd_wbm_data_s,
pd_wbm_valid_o => pd_wbm_valid_s,
pd_wbm_hdr_rid_o => pd_wbm_hdr_rid_s,
pd_wbm_hdr_tag_o => pd_wbm_hdr_tag_s,
pd_wbm_target_mrd_o => pd_wbm_target_mrd_s,
pd_wbm_target_mwr_o => pd_wbm_target_mwr_s,
wbm_pd_ready_i => wbm_pd_ready_s,
pd_op_o => pd_op_s,
pd_header_type_o => pd_header_type_s,
pd_payload_length_o => pd_payload_length_s,
-- L2P DMA
pd_pdm_data_valid_o => pd_pdm_data_valid_s,
pd_pdm_data_valid_w_o => pd_pdm_data_valid_w_s,
pd_pdm_data_last_o => pd_pdm_data_last_s,
pd_pdm_keep_o => pd_pdm_keep_s,
pd_pdm_data_o => pd_pdm_data_s
);
wb32:wbmaster32
generic map (
g_ACK_TIMEOUT => 100 -- Wishbone ACK timeout (in wb_clk cycles)
)
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- From P2L packet decoder
--
-- Header
pd_wbm_hdr_start_i => pd_wbm_valid_s, -- Header strobe
--pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_wbm_hdr_rid_i => pd_wbm_hdr_rid_s, -- Requester ID
pd_wbm_hdr_cid_i => pcie_id_s, --X"0100", -- Completer ID
pd_wbm_hdr_tag_i => pd_wbm_hdr_tag_s,
pd_wbm_target_mrd_i => pd_wbm_target_mrd_s, -- Target memory read
pd_wbm_target_mwr_i => pd_wbm_target_mwr_s, -- Target memory write
--
-- Address
pd_wbm_addr_start_i => pd_wbm_valid_s, -- Address strobe
pd_wbm_addr_i => pd_wbm_address_s(31 downto 0),-- Target address (in byte) that will increment with data
-- increment = 4 bytes
--
-- Data
pd_wbm_data_valid_i => pd_wbm_valid_s, -- Indicates Data is valid
--pd_wbm_data_last_i : in std_logic; -- Indicates end of the packet
pd_wbm_data_i => pd_wbm_data_s, -- Data
--pd_wbm_be_i : in std_logic_vector(3 downto 0); -- Byte Enable for data
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o => open,-- Ready to accept target write
p2l_rdy_o => p2l_wbm_rdy_s,--wbm_pd_ready_s, -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i => "11",-- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
wbm_arb_tdata_o => wbm_arb_tdata_s,
wbm_arb_tkeep_o => wbm_arb_tkeep_s,
--wbm_arb_tuser_o => wbm_arb_tuser_s,
wbm_arb_tlast_o => wbm_arb_tlast_s,
wbm_arb_tvalid_o => wbm_arb_tvalid_s,
wbm_arb_tready_i => wbm_arb_tready_s,
wbm_arb_req_o => wbm_arb_req_s,
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i => clk_i, -- Wishbone bus clock
wb_adr_o => wb_adr_s(30 downto 0),-- Address
wb_dat_o => wb_dat_m2s_s,-- Data out
wb_sel_o => wb_sel_s, -- Byte select
wb_stb_o => wb_stb_s, -- Strobe
wb_we_o => wb_we_s, -- Write
wb_cyc_o => wb_cyc_s, -- Cycle
wb_dat_i => wb_dat_s2m_s,-- Data in
wb_ack_i => wb_ack_s, -- Acknowledge
wb_stall_i => wb_stall_s, -- Stall
wb_err_i => wb_err_s, -- Error
wb_rty_i => wb_rty_s, -- Retry
wb_int_i => wb_int_s -- Interrupt
);
wb_stall_s <= '0';
wb_err_s <= '0';
wb_rty_s <= '0';
wb_int_s <= '0';
wb_dma_ctrl_adr_s <= wb_adr_s(31 downto 0);
wb_dma_ctrl_dat_m2s_s <= wb_dat_m2s_s;
wb_dma_ctrl_stb_s <= wb_stb_s;
wb_dma_ctrl_we_s <= wb_we_s;
wb_dbg_adr_s <= wb_adr_s(31 downto 0);
wb_dbg_dat_m2s_s <= wb_dat_m2s_s;
wb_dbg_stb_s <= wb_stb_s;
wb_dbg_we_s <= wb_we_s;
wb_dbg_sel_s <= (others => '1');
wb_mem_adr_s <= wb_adr_s(31 downto 0);
wb_mem_dat_m2s_s <= wb_dat_m2s_s;
wb_mem_stb_s <= wb_stb_s;
wb_mem_we_s <= wb_we_s;
-- CSR Wishbone adress demux
process(wb_adr_s,wb_cyc_s,wb_mem_cyc_s,wb_cyc_s,wb_dma_ctrl_dat_s2m_s,wb_dma_ctrl_ack_s,wb_mem_dat_s2m_s,wb_mem_ack_s,wb_dbg_dat_s2m_s,wb_dbg_ack_s)
begin
if wb_adr_s(31 downto 4) = X"0000000" then
wb_dma_ctrl_cyc_s <= wb_cyc_s;
wb_dbg_cyc_s <= '0';
wb_mem_cyc_s <= '0';
wb_dat_s2m_s <= wb_dma_ctrl_dat_s2m_s;
wb_ack_s <= wb_dma_ctrl_ack_s;
elsif wb_adr_s(31 downto 4) = X"0000001" then
wb_dma_ctrl_cyc_s <= '0';
wb_dbg_cyc_s <= wb_cyc_s;
wb_mem_cyc_s <= '0';
wb_dat_s2m_s <= wb_dbg_dat_s2m_s;
wb_ack_s <= wb_dbg_ack_s;
else
wb_dma_ctrl_cyc_s <= '0';
wb_dbg_cyc_s <= '0';
wb_mem_cyc_s <= wb_cyc_s;
wb_dat_s2m_s <= wb_mem_dat_s2m_s;
wb_ack_s <= wb_mem_ack_s;
end if;
end process;
csr_ram:bram_wbs32
generic map (
ADDR_WIDTH => 5,
DATA_WIDTH => 32
)
port map (
-- SYS CON
clk => clk_i,
rst => rst_i,
-- Wishbone Slave in
wb_adr_i => wb_mem_adr_s(5 - 1 downto 0),
--wb_dat_i(63 downto 32) => X"00000000",
wb_dat_i => wb_mem_dat_m2s_s,
wb_we_i => wb_mem_we_s,
wb_stb_i => wb_mem_stb_s,
wb_cyc_i => wb_mem_cyc_s,
wb_lock_i => wb_mem_stb_s,
-- Wishbone Slave out
--wb_dat_o(63 downto 32) => wb_null,--open,
wb_dat_o => wb_mem_dat_s2m_s,
wb_ack_o => wb_mem_ack_s
);
dma_ctrl:dma_controller
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o => dma_ctrl_irq_s,
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_o => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_o => dma_ctrl_host_addr_l_s,
dma_ctrl_len_o => dma_ctrl_len_s,
dma_ctrl_start_l2p_o => dma_ctrl_start_l2p_s, -- To the L2P DMA master
dma_ctrl_start_p2l_o => dma_ctrl_start_p2l_s, -- To the P2L DMA master
dma_ctrl_start_next_o => dma_ctrl_start_next_s, -- To the P2L DMA master
dma_ctrl_byte_swap_o => dma_ctrl_byte_swap_s,
dma_ctrl_abort_o => dma_ctrl_abort_s,
dma_ctrl_done_i => dma_ctrl_done_s,
dma_ctrl_error_i => dma_ctrl_error_s,
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i => next_item_carrier_addr_s,
next_item_host_addr_h_i => next_item_host_addr_h_s,
next_item_host_addr_l_i => next_item_host_addr_l_s,
next_item_len_i => next_item_len_s,
next_item_next_l_i => next_item_next_l_s,
next_item_next_h_i => next_item_next_h_s,
next_item_attrib_i => next_item_attrib_s,
next_item_valid_i => next_item_valid_s,
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i => clk_i, -- Bus clock
wb_adr_i => wb_dma_ctrl_adr_s(3 downto 0), -- Adress
wb_dat_o => wb_dma_ctrl_dat_s2m_s, -- Data in
wb_dat_i => wb_dma_ctrl_dat_m2s_s, -- Data out
wb_sel_i => "1111", -- Byte select
wb_cyc_i => wb_dma_ctrl_cyc_s, -- Read or write cycle
wb_stb_i => wb_dma_ctrl_stb_s, -- Read or write strobe
wb_we_i => wb_dma_ctrl_we_s, -- Write
wb_ack_o => wb_dma_ctrl_ack_s, -- Acknowledge
dma_ctrl_current_state_do => dma_ctrl_current_state_ds,
dma_ctrl_do => dma_ctrl_ds,
dma_stat_do => dma_stat_ds,
dma_attrib_do => dma_attrib_ds
);
-- Status signals from DMA masters
dma_ctrl_done_s <= dma_ctrl_l2p_done_s or dma_ctrl_p2l_done_s;
dma_ctrl_error_s <= dma_ctrl_l2p_error_s or dma_ctrl_p2l_error_s;
dbg_reg_comp:debugregisters
Port map(
-- SYS CON
clk => clk_i,
rst => rst_i,
-- Wishbone Slave in
wb_adr_i => wb_dbg_adr_s(3 downto 0),
wb_dat_i => wb_dbg_dat_m2s_s,
wb_we_i => wb_dbg_we_s,
wb_stb_i => wb_dbg_stb_s,
wb_cyc_i => wb_dbg_cyc_s,
-- Wishbone Slave out
wb_dat_o => wb_dbg_dat_s2m_s,
wb_ack_o => wb_dbg_ack_s,
-- input/ouput
dummyram_sel_o => dummyram_sel_s,
ddr3ram_sel_o => ddr3ram_sel_s,
dummyaddress_sel_o => dummyaddress_sel_s,
dummydeadbeef_sel_o => dummydeadbeef_sel_s,
usr_led_o => usr_led_o,
usr_sw_i => usr_sw_i--,
--ddr_init_calib_complete_i => init_calib_complete_s
);
p2l_dma:p2l_dma_master
generic map (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP => false
)
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
l2p_rid_i => pcie_id_s,
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_s,
dma_ctrl_len_i => dma_ctrl_len_s,
dma_ctrl_start_p2l_i => dma_ctrl_start_p2l_s,
dma_ctrl_start_next_i => dma_ctrl_start_next_s,
dma_ctrl_done_o => dma_ctrl_p2l_done_s,
dma_ctrl_error_o => dma_ctrl_p2l_error_s,
dma_ctrl_byte_swap_i => "111",
dma_ctrl_abort_i => dma_ctrl_abort_s,
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
pd_pdm_master_cpld_i => '1', -- Master read completion with data
pd_pdm_master_cpln_i => '0', -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i => pd_pdm_data_valid_s, -- Indicates Data is valid
pd_pdm_data_valid_w_i => pd_pdm_data_valid_w_s,
pd_pdm_data_last_i => pd_pdm_data_last_s, -- Indicates end of the packet
pd_pdm_data_i => pd_pdm_data_s, -- Data
pd_pdm_be_i => pd_pdm_keep_s, -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o => p2l_dma_rdy_s, -- De-asserted to pause transfer already in progress
rx_error_o => open, -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o => pdm_arb_tvalid_s, -- Read completion signals
pdm_arb_tlast_o => pdm_arb_tlast_s, -- Toward the arbiter
pdm_arb_tdata_o => pdm_arb_tdata_s,
pdm_arb_tkeep_o => pdm_arb_tkeep_s,
pdm_arb_req_o => pdm_arb_req_s,
arb_pdm_gnt_i => pdm_arb_tready_s,
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i => clk_i, -- Bus clock
p2l_dma_adr_o => p2l_dma_adr_s, -- Adress
p2l_dma_dat_i => p2l_dma_dat_s2m_s, -- Data in
p2l_dma_dat_o => p2l_dma_dat_m2s_s, -- Data out
p2l_dma_sel_o => p2l_dma_sel_s, -- Byte select
p2l_dma_cyc_o => p2l_dma_cyc_s, -- Read or write cycle
p2l_dma_stb_o => p2l_dma_stb_s, -- Read or write strobe
p2l_dma_we_o => p2l_dma_we_s, -- Write
p2l_dma_ack_i => p2l_dma_ack_s, -- Acknowledge
p2l_dma_stall_i => p2l_dma_stall_s, -- for pipelined Wishbone
l2p_dma_cyc_i => l2p_dma_cyc_s, -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o => next_item_carrier_addr_s,
next_item_host_addr_h_o => next_item_host_addr_h_s,
next_item_host_addr_l_o => next_item_host_addr_l_s,
next_item_len_o => next_item_len_s,
next_item_next_l_o => next_item_next_l_s,
next_item_next_h_o => next_item_next_h_s,
next_item_attrib_o => next_item_attrib_s,
next_item_valid_o => next_item_valid_s
);
-----------------------------------------------------------------------------
-- L2P DMA master
-----------------------------------------------------------------------------
--l2p_dma_stall_s <= '0';
l2p_dma : l2p_dma_master
port map
(
clk_i => clk_i,
rst_n_i => rst_n_s,
l2p_rid_i => pcie_id_s,
dma_ctrl_target_addr_i => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_s,
dma_ctrl_len_i => dma_ctrl_len_s,
dma_ctrl_start_l2p_i => dma_ctrl_start_l2p_s,
dma_ctrl_done_o => dma_ctrl_l2p_done_s,
dma_ctrl_error_o => dma_ctrl_l2p_error_s,
dma_ctrl_byte_swap_i => "000", --TODO
dma_ctrl_abort_i => dma_ctrl_abort_s,
ldm_arb_tvalid_o => ldm_arb_tvalid_s,
ldm_arb_tlast_o => ldm_arb_tlast_s,
ldm_arb_tdata_o => ldm_arb_tdata_s,
ldm_arb_tkeep_o => ldm_arb_tkeep_s,
ldm_arb_req_o => ldm_arb_req_s,
arb_ldm_gnt_i => ldm_arb_tready_s,
l2p_edb_o => open,
ldm_arb_tready_i => ldm_arb_tready_s,
l2p_rdy_i => '1',
tx_error_i => '0',
l2p_dma_clk_i => clk_i,
l2p_dma_adr_o => l2p_dma_adr_s,
l2p_dma_dat_i => l2p_dma_dat_s2m_s,
l2p_dma_dat_o => l2p_dma_dat_m2s_s,
l2p_dma_sel_o => l2p_dma_sel_s,
l2p_dma_cyc_o => l2p_dma_cyc_s,
l2p_dma_stb_o => l2p_dma_stb_s,
l2p_dma_we_o => l2p_dma_we_s,
l2p_dma_ack_i => l2p_dma_ack_s,
l2p_dma_stall_i => l2p_dma_stall_s,
p2l_dma_cyc_i => p2l_dma_cyc_s,
--DMA Debug
l2p_current_state_do => l2p_current_state_ds,
l2p_data_cnt_do => l2p_data_cnt_ds,
l2p_len_cnt_do => l2p_len_cnt_ds,
l2p_timeout_cnt_do => l2p_timeout_cnt_ds,
wb_timeout_cnt_do => wb_timeout_cnt_ds,
-- Data FIFO
data_fifo_rd_do => data_fifo_rd_ds,
data_fifo_wr_do => data_fifo_wr_ds,
data_fifo_empty_do => data_fifo_empty_ds,
data_fifo_full_do => data_fifo_full_ds,
data_fifo_dout_do => data_fifo_dout_ds,
data_fifo_din_do => data_fifo_din_ds,
-- Addr FIFO
addr_fifo_rd_do => addr_fifo_rd_ds,
addr_fifo_wr_do => addr_fifo_wr_ds,
addr_fifo_empty_do => addr_fifo_empty_ds,
addr_fifo_full_do => addr_fifo_full_ds,
addr_fifo_dout_do => addr_fifo_dout_ds,
addr_fifo_din_do => addr_fifo_din_ds
);
arbiter:l2p_arbiter
generic map(
axis_data_width_c => axis_data_width_c
)
port map(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i => wbm_arb_tdata_s,
wbm_arb_tkeep_i => wbm_arb_tkeep_s,
wbm_arb_tlast_i => wbm_arb_tlast_s,
wbm_arb_tvalid_i => wbm_arb_tvalid_s,
wbm_arb_req_i => wbm_arb_req_s,
wbm_arb_tready_o => wbm_arb_tready_s,
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i => pdm_arb_tdata_s,
pdm_arb_tkeep_i => pdm_arb_tkeep_s,
pdm_arb_tlast_i => pdm_arb_tlast_s,
pdm_arb_tvalid_i => pdm_arb_tvalid_s,
pdm_arb_req_i => pdm_arb_req_s,
pdm_arb_tready_o => pdm_arb_tready_s,
arb_pdm_gnt_o => open,
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i => ldm_arb_tdata_s,
ldm_arb_tkeep_i => ldm_arb_tkeep_s,
ldm_arb_tlast_i => ldm_arb_tlast_s,
ldm_arb_tvalid_i => ldm_arb_tvalid_s,
ldm_arb_req_i => ldm_arb_req_s,
ldm_arb_tready_o => ldm_arb_tready_s,
arb_ldm_gnt_o => open,
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o => m_axis_tx_tdata_s,
axis_tx_tkeep_o => m_axis_tx_tkeep_s,
axis_tx_tuser_o => m_axis_tx_tuser_s,
axis_tx_tlast_o => m_axis_tx_tlast_s,
axis_tx_tvalid_o => m_axis_tx_tvalid_s,
axis_tx_tready_i => m_axis_tx_tready_s,
eop_do => eop_s
);
dma_bram_gen : if DMA_MEMORY_SELECTED = "DEMUX" or DMA_MEMORY_SELECTED = "BRAM" generate
dma_ram:k_bram
generic map (
ADDR_WIDTH => 9+4,
DATA_WIDTH => 64
)
port map (
-- SYS CON
clk => clk_i,
rst => rst_i,
-- Wishbone Slave in
wb_adr_i => dma_bram_adr_s(9+4 - 1 downto 0),
wb_dat_i => dma_bram_dat_m2s_s,
wb_we_i => dma_bram_we_s,
wb_stb_i => dma_bram_stb_s,
wb_cyc_i => dma_bram_cyc_s,
wb_lock_i => dma_bram_stb_s,
-- Wishbone Slave out
wb_dat_o => dma_bram_dat_s2m_s,
wb_ack_o => dma_bram_ack_s
);
end generate dma_bram_gen;
clk200_gen : if DMA_MEMORY_SELECTED = "BRAM" generate
--LVDS input to internal single
CLK_IBUFDS : IBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map(
I => sys_clk_p_i,
IB => sys_clk_n_i,
O => open
);
end generate clk200_gen;
dma_ddr3_gen : if DMA_MEMORY_SELECTED = "DEMUX" or DMA_MEMORY_SELECTED = "DDR3" generate
cmp_ddr3_ctrl_wb : ddr3_ctrl_wb
port map(
rst_n_i => rst_n_s,
ddr_addr_o => ddr_app_addr_s,
ddr_cmd_o => ddr_app_cmd_s,
ddr_cmd_en_o => ddr_app_cmd_en_s,
ddr_wdf_data_o => ddr_app_wdf_data_s,
ddr_wdf_end_o => ddr_app_wdf_end_s,
ddr_wdf_mask_o => ddr_app_wdf_mask_s,
ddr_wdf_wren_o => ddr_app_wdf_wren_s,
ddr_rd_data_i => ddr_app_rd_data_s,
ddr_rd_data_end_i => ddr_app_rd_data_end_s,
ddr_rd_data_valid_i => ddr_app_rd_data_valid_s,
ddr_rdy_i => ddr_app_rdy_s,
ddr_wdf_rdy_i => ddr_app_wdf_rdy_s,
ddr_ui_clk_i => ddr_app_ui_clk_s,
ddr_ui_clk_sync_rst_i => ddr_app_ui_clk_sync_rst_s,
ddr_sr_req_o => open,
ddr_ref_req_o => open,
ddr_zq_req_o => open,
ddr_sr_active_i => '1',
ddr_ref_ack_i => '1',
ddr_zq_ack_i => '1',
ddr_init_calib_complete_i => '1',
wb_clk_i => clk_i,
wb_sel_i => dma_ddr_sel_s,
wb_cyc_i => dma_ddr_cyc_s,
wb_stb_i => dma_ddr_stb_s,
wb_we_i => dma_ddr_we_s,
wb_addr_i => dma_ddr_addr_s,
wb_data_i => dma_ddr_dat_m2s_s,
wb_data_o => dma_ddr_dat_s2m_s,
wb_ack_o => dma_ddr_ack_s,
wb_stall_o => dma_ddr_stall_s,
ddr_wb_rd_mask_dout_do => ddr_wb_rd_mask_dout_ds,
ddr_wb_rd_mask_addr_dout_do => ddr_wb_rd_mask_addr_dout_ds,
ddr_rd_mask_rd_data_count_do => ddr_rd_mask_rd_data_count_ds,
ddr_rd_data_rd_data_count_do => ddr_rd_data_rd_data_count_ds,
ddr_rd_fifo_full_do => ddr_rd_fifo_full_ds,
ddr_rd_fifo_empty_do => ddr_rd_fifo_empty_ds,
ddr_rd_fifo_rd_do => ddr_rd_fifo_rd_ds
);
dma_ddr_sel_s <= (others => '1');
u_mig_7series_0 : mig_7series_0
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr_s,
ddr3_ba => ddr3_ba_s,
ddr3_cas_n => ddr3_cas_n_s,
ddr3_ck_n => ddr3_ck_n_s,
ddr3_ck_p => ddr3_ck_p_s,
ddr3_cke => ddr3_cke_s,
ddr3_ras_n => ddr3_ras_n_s,
ddr3_reset_n => ddr3_reset_n_s,
ddr3_we_n => ddr3_we_n_s,
ddr3_dq => ddr3_dq_s,
ddr3_dqs_n => ddr3_dqs_n_s,
ddr3_dqs_p => ddr3_dqs_p_s,
init_calib_complete => init_calib_complete_s,
ddr3_cs_n => ddr3_cs_n_s,
ddr3_dm => ddr3_dm_s,
ddr3_odt => ddr3_odt_s,
-- Application interface ports
app_addr => ddr_app_addr_s,
app_cmd => ddr_app_cmd_s,
app_en => ddr_app_cmd_en_s,
app_wdf_data => ddr_app_wdf_data_s,
app_wdf_end => ddr_app_wdf_end_s,
app_wdf_wren => ddr_app_wdf_wren_s,
app_rd_data => ddr_app_rd_data_s,
app_rd_data_end => ddr_app_rd_data_end_s,
app_rd_data_valid => ddr_app_rd_data_valid_s,
app_rdy => ddr_app_rdy_s,
app_wdf_rdy => ddr_app_wdf_rdy_s,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ddr_app_ui_clk_s,
ui_clk_sync_rst => ddr_app_ui_clk_sync_rst_s,
app_wdf_mask => ddr_app_wdf_mask_s,
-- System Clock Ports
sys_clk_p => sys_clk_p_i,
sys_clk_n => sys_clk_n_i,
sys_rst => rst_i
);
--DDR3
ddr3_dq_io <= ddr3_dq_s;
ddr3_dqs_p_io <= ddr3_dqs_p_s;
ddr3_dqs_n_io <= ddr3_dqs_n_s;
--init_calib_complete_o <= init_calib_complete_s;
ddr3_addr_o <= ddr3_addr_s;
ddr3_ba_o <= ddr3_ba_s;
ddr3_ras_n_o <= ddr3_ras_n_s;
ddr3_cas_n_o <= ddr3_cas_n_s;
ddr3_we_n_o <= ddr3_we_n_s;
ddr3_reset_n_o <= ddr3_reset_n_s;
ddr3_ck_p_o <= ddr3_ck_p_s;
ddr3_ck_n_o <= ddr3_ck_n_s;
ddr3_cke_o <= ddr3_cke_s;
ddr3_cs_n_o <= ddr3_cs_n_s;
ddr3_dm_o <= ddr3_dm_s;
ddr3_odt_o <= ddr3_odt_s;
end generate dma_ddr3_gen;
-- BRAM Wishbone Slave in
dma_bram_adr_s <= dma_adr_s;
dma_bram_dat_m2s_s <= dma_dat_m2s_s;
dma_bram_we_s <= dma_we_s;
dma_bram_stb_s <= dma_stb_s;
-- DDR CTRL Wishbone Slave in
dma_ddr_addr_s <= dma_adr_s;
dma_ddr_dat_m2s_s <= dma_dat_m2s_s;
dma_ddr_we_s <= dma_we_s;
dma_ddr_stb_s <= dma_stb_s;
dma_demux_gen : if DMA_MEMORY_SELECTED = "DEMUX" generate
dma_sel : process(clk_i,dummyram_sel_s, ddr3ram_sel_s, dummyaddress_sel_s, dummydeadbeef_sel_s,
dma_bram_dat_s2m_s,dma_bram_ack_s,dma_cyc_s,
dma_ddr_dat_s2m_s,dma_ddr_ack_s,
dma_ddr_dat_s2m_s,dma_ddr_ack_s)
begin
dma_dat_s2m_s <= (others => '0');
dma_ack_s <= '0';
dma_bram_cyc_s <= '0';
dma_ddr_cyc_s <= '0';
if(dummyram_sel_s = '1') then
dma_dat_s2m_s <= dma_bram_dat_s2m_s;
dma_ack_s <= dma_bram_ack_s;
dma_bram_cyc_s <= dma_cyc_s;
end if;
if (ddr3ram_sel_s = '1') then
dma_dat_s2m_s <= dma_ddr_dat_s2m_s;
dma_ack_s <= dma_ddr_ack_s;
dma_ddr_cyc_s <= dma_cyc_s;
end if;
if(dummyaddress_sel_s = '1') then
end if;
if(dummyaddress_sel_s = '1') then
end if;
end process dma_sel;
end generate dma_demux_gen;
dma_bramonly_gen : if DMA_MEMORY_SELECTED = "BRAM" generate
dma_dat_s2m_s <= dma_bram_dat_s2m_s;
dma_ack_s <= dma_bram_ack_s;
dma_bram_cyc_s <= dma_cyc_s;
end generate dma_bramonly_gen;
dma_ddr3only_gen : if DMA_MEMORY_SELECTED = "DDR3" generate
dma_dat_s2m_s <= dma_ddr_dat_s2m_s;
dma_ack_s <= dma_ddr_ack_s;
dma_ddr_cyc_s <= dma_cyc_s;
end generate dma_ddr3only_gen;
dma_mux: process(
l2p_dma_adr_s,l2p_dma_dat_m2s_s,l2p_dma_sel_s,l2p_dma_cyc_s,l2p_dma_stb_s,l2p_dma_we_s,
p2l_dma_adr_s,p2l_dma_dat_m2s_s,p2l_dma_sel_s,p2l_dma_cyc_s,p2l_dma_stb_s,p2l_dma_we_s)
begin
if l2p_dma_cyc_s = '1' then
dma_adr_s <= l2p_dma_adr_s(31 downto 0);
dma_dat_m2s_s <= l2p_dma_dat_m2s_s;
dma_sel_s <= l2p_dma_sel_s & l2p_dma_sel_s;
dma_cyc_s <= l2p_dma_cyc_s;
dma_stb_s <= l2p_dma_stb_s;
dma_we_s <= l2p_dma_we_s;
elsif p2l_dma_cyc_s = '1' then
dma_adr_s <= p2l_dma_adr_s;
dma_dat_m2s_s <= p2l_dma_dat_m2s_s;
dma_sel_s <= p2l_dma_sel_s;
dma_cyc_s <= p2l_dma_cyc_s;
dma_stb_s <= p2l_dma_stb_s;
dma_we_s <= p2l_dma_we_s;
else
dma_adr_s <= (others => '0');
dma_dat_m2s_s <= (others => '0');
dma_sel_s <= (others => '0');
dma_cyc_s <= '0';
dma_stb_s <= '0';
dma_we_s <= '0';
end if;
end process dma_mux;
l2p_dma_dat_s2m_s <= dma_dat_s2m_s;
p2l_dma_dat_s2m_s <= dma_dat_s2m_s;
l2p_dma_ack_s <= dma_ack_s;
p2l_dma_ack_s <= dma_ack_s;
l2p_dma_stall_s <= dma_stall_s;
p2l_dma_stall_s <= dma_stall_s;
dma_stall_s <= '0';
front_led_o <= count_s(28 downto 25);
--usr_led_o <= '1' & usr_sw_i;
dbg_0 : if DEBUG_C(0) = '1' generate
axis_debug : ila_axis
PORT MAP (
clk => clk_i,
probe0 => s_axis_rx_tdata_s,
probe1 => s_axis_rx_tkeep_s,
probe2(0) => s_axis_rx_tlast_s,
probe3(0) => s_axis_rx_tvalid_s,
probe4(0) => s_axis_rx_tready_s,
probe5 => m_axis_tx_tdata_s,
probe6 => m_axis_tx_tkeep_s,
probe7(0) => m_axis_tx_tlast_s,
probe8(0) => m_axis_tx_tvalid_s,
probe9(0) => m_axis_tx_tready_s,
probe10 => s_axis_rx_tuser_i,
probe11(0) => dma_ctrl_start_l2p_s,
probe12(0) => dma_ctrl_start_p2l_s,
probe13(0) => dma_ctrl_start_next_s,
probe14(0) => dma_ctrl_abort_s,
probe15(0) => dma_ctrl_done_s,
probe16(0) => dma_ctrl_error_s,
probe17(0) => user_lnk_up_i,
probe18(0) => cfg_interrupt_s,
probe19(0) => cfg_interrupt_rdy_i,
probe20(0) => dma_ctrl_done_s,
probe21 => wbm_arb_tready_s & wbm_arb_tready_s & ldm_arb_tready_s,--dma_ctrl_current_state_ds,
probe22(0) => tx_err_drop_i,--next_item_valid_s
probe23 => count_s
);
end generate dbg_0;
dbg_1 : if DEBUG_C(1) = '1' generate
dma_ctrl_debug : ila_dma_ctrl_reg
PORT MAP (
clk => clk_i,
probe0 => dma_ctrl_carrier_addr_s,
probe1 => dma_ctrl_host_addr_h_s,
probe2 => dma_ctrl_host_addr_l_s,
probe3 => dma_ctrl_len_s,
probe4(0) => dma_ctrl_start_l2p_s,
probe5(0) => dma_ctrl_start_p2l_s,
probe6(0) => dma_ctrl_start_next_s,
probe7 => dma_ctrl_byte_swap_s,
probe8(0) => dma_ctrl_abort_s,
probe9(0) => dma_ctrl_done_s,
probe10(0) => dma_ctrl_error_s,
probe11 => dma_ctrl_current_state_ds,
probe12 => next_item_carrier_addr_s,
probe13 => next_item_host_addr_h_s,
probe14 => next_item_host_addr_l_s,
probe15 => next_item_len_s,
probe16 => next_item_next_l_s,
probe17 => next_item_next_h_s,
probe18 => next_item_attrib_s,
probe19(0) => next_item_valid_s,
probe20 => dma_ctrl_irq_s
);
end generate dbg_1;
dbg_2 : if DEBUG_C(2) = '1' generate
pipelined_wishbone_debug : ila_wsh_pipe
PORT MAP (
clk => clk_i,
probe0 => dma_adr_s,
probe1 => dma_dat_s2m_s,
probe2 => dma_dat_m2s_s,
probe3 => dma_sel_s,
probe4(0) => dma_cyc_s,
probe5(0) => dma_stb_s,
probe6(0) => dma_we_s,
probe7(0) => dma_ack_s,
probe8(0) => dma_stall_s,
probe9(0) => l2p_dma_cyc_s,
probe10(0) => p2l_dma_cyc_s,
probe11(0) => dma_ctrl_start_l2p_s,
probe12(0) => dma_ctrl_start_p2l_s,
probe13(0) => dma_ctrl_start_next_s,
probe14 => ddr_rd_mask_rd_data_count_ds,
probe15 => ddr_rd_data_rd_data_count_ds,
probe16 => ddr_wb_rd_mask_addr_dout_ds & ddr_wb_rd_mask_dout_ds,
probe17 => count_s
);
end generate dbg_2;
dbg_3 : if DEBUG_C(3) = '1' generate
wbm_to_p2l_debug : ila_pd_pdm
PORT MAP (
clk => clk_i,
probe0 => pd_pdm_data_s,
probe1(0) => pd_pdm_data_last_s,
probe2(0) => pd_pdm_data_valid_s,
probe3 => s_axis_rx_tdata_s,
probe4 => s_axis_rx_tkeep_s,
probe5(0) => s_axis_rx_tlast_s,
probe6(0) => s_axis_rx_tvalid_s,
probe7(0) => ldm_arb_tready_s,
probe8 => l2p_current_state_ds,
probe9 => dma_ctrl_current_state_ds,
probe10 => pd_pdm_data_valid_w_s,
probe11(1) => next_item_valid_s
);
end generate dbg_3;
dbg_4 : if DEBUG_C(4) = '1' generate
l2p_debug : ila_l2p_dma
PORT MAP (
clk => clk_i,
probe0 => dma_ctrl_carrier_addr_s,
probe1 => dma_ctrl_host_addr_h_s,
probe2 => dma_ctrl_host_addr_l_s,
probe3 => dma_ctrl_len_s,
probe4(0) => dma_ctrl_start_l2p_s,
probe5(0) => dma_ctrl_done_s ,
probe6(0) => dma_ctrl_l2p_error_s ,
probe7(0) => dma_ctrl_abort_s,
probe8(0) => ldm_arb_tvalid_s,
probe9(0) => ldm_arb_tlast_s,
probe10 => ldm_arb_tdata_s,
probe11 => ldm_arb_tkeep_s,
probe12(0) => ldm_arb_tready_s,
probe13(0) => ldm_arb_req_s,
probe14(0) => pdm_arb_tready_s,
probe15(0) => '0',
probe16 => l2p_dma_adr_s(31 downto 0),
probe17 => l2p_dma_dat_m2s_s,
probe18 => l2p_dma_dat_s2m_s,
probe19(0) => l2p_dma_cyc_s,
probe20(0) => l2p_dma_stb_s,
probe21(0) => l2p_dma_we_s,
probe22(0) => l2p_dma_ack_s,
probe23(0) => l2p_dma_stall_s,
probe24(0) => p2l_dma_cyc_s,
probe25 => l2p_current_state_ds,
probe26 => std_logic_vector(l2p_data_cnt_ds),
probe27 => std_logic_vector(l2p_len_cnt_ds),
probe28(0) => data_fifo_rd_ds,
probe29(0) => data_fifo_wr_ds,
probe30(0) => data_fifo_empty_ds,
probe31(0) => data_fifo_full_ds,
probe32 => data_fifo_dout_ds,
probe33 => data_fifo_din_ds,
probe34(0) => addr_fifo_rd_ds,
probe35(0) => addr_fifo_wr_ds,
probe36(0) => addr_fifo_empty_ds,
probe37(0) => addr_fifo_full_ds,
probe38 => addr_fifo_dout_ds,
probe39 => addr_fifo_din_ds,
probe40 => std_logic_vector(wb_timeout_cnt_ds),
probe41 => std_logic_vector(l2p_timeout_cnt_ds),
probe42 => count_s
);
end generate dbg_4;
dbg_5 : if DEBUG_C(5) = '1' generate
ddr_debug : ila_ddr
PORT MAP (
clk => ddr_app_ui_clk_s,
probe0 => ddr_app_addr_s,
probe1 => ddr_app_cmd_s,
probe2(0) => ddr_app_cmd_en_s,
probe3 => ddr_app_wdf_data_s,
probe4(0) => ddr_app_wdf_end_s,
probe5 => ddr_app_wdf_mask_s,
probe6(0) => ddr_app_wdf_wren_s,
probe7 => ddr_app_rd_data_s,
probe8(0) => ddr_app_rd_data_end_s,
probe9(0) => ddr_app_rd_data_valid_s,
probe10(0) => ddr_app_rdy_s,
probe11(0) => ddr_app_wdf_rdy_s,
probe12(0) => ddr_app_ui_clk_sync_rst_s,
probe13(0) => init_calib_complete_s,
probe14 => ddr_count_s
);
end generate dbg_5;
end Behavioral;
|
gpl-3.0
|
2572133ff84c4b41bd2d3aeee30a35da
| 0.503959 | 2.927123 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
disp.vhd
| 1 | 3,208 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity disp is
Port ( clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
data_i : in std_logic_vector(15 downto 0);
led_an_o : out std_logic_vector(3 downto 0);
led_seg_o : out std_logic_vector(6 downto 0));
end disp;
architecture Behavioral of disp is
signal Reset : std_logic;
signal ena_o : std_logic;
signal seg_sel : std_logic_vector(3 downto 0);
begin
Reset <= rst_i when RISING_EDGE(clk_i);
led_an_o <= seg_sel;
logi: process (clk_i) is
variable clk_i_div : STD_LOGIC_VECTOR(16 downto 0);
begin
if rising_edge(clk_i) then
ena_o <= clk_i_div(16);
if clk_i_div(16) = '1' then
clk_i_div := (others => '0');
-- else
-- ena_o <= '0';
end if;
clk_i_div := clk_i_div + 1;
if Reset = '1' then
clk_i_div := (others => '0');
end if;
end if;
end process logi;
enc_proc: process (clk_i) is
variable flop : integer range 0 to 3 := 0;
variable nibble : std_logic_vector(3 downto 0);
variable value : std_logic_vector(6 downto 0);
begin
if rising_edge(clk_i) then
if ena_o = '1' then
seg_sel <= seg_sel(2 downto 0) & seg_sel(3);
if flop = 3 then
flop := 0;
else
flop := flop + 1;
end if;
nibble := data_i(3 + flop * 4 downto flop * 4);
case nibble is -- abcdefg
when B"0000" => value := B"1000000"; -- B"00000011";
when B"0001" => value := B"1111001"; -- B"10011111";
when B"0010" => value := B"0100100"; -- B"00100101";
when B"0011" => value := B"0110000"; -- B"00001101";
when B"0100" => value := B"0011001"; -- B"10011001";
when B"0101" => value := B"0010010"; -- B"01001001";
when B"0110" => value := B"0000010"; -- B"01000001";
when B"0111" => value := B"1111000"; -- B"00011111";
when B"1000" => value := B"0000000"; -- B"00000001";
when B"1001" => value := B"0010000"; -- B"00001001";
when B"1010" => value := B"0001000"; -- B"00010001";
when B"1011" => value := B"0000011"; -- B"11000001";
when B"1100" => value := B"0100111"; -- B"11100101";
when B"1101" => value := B"0100001"; -- B"10000101";
when B"1110" => value := B"0000110"; -- B"01100001";
when B"1111" => value := B"0001110"; -- B"01110001";
when others => value := B"1111111";
end case;
led_seg_o <= value;
end if;
if Reset = '1' then
seg_sel <= B"1110";
flop := 0;
end if;
end if;
end process enc_proc;
end Behavioral;
|
gpl-3.0
|
33bec687733050df9f3d6b0526ebc764
| 0.615025 | 3.009381 | false | false | false | false |
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/uart/comp/uart_fifo.vhd
| 1 | 5,156 |
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity UART_FIFO is
Generic (
DATA_WIDTH : integer := 8;
FIFO_DEPTH : integer := 256
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- FIFO WRITE INTERFACE
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
WR_EN : in std_logic;
FULL : out std_logic;
-- FIFO READ INTERFACE
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
DATA_VLD : out std_logic;
RD_EN : in std_logic;
EMPTY : out std_logic
);
end UART_FIFO;
architecture FULL of UART_FIFO is
constant addr_width : integer := integer(ceil(log2(real(FIFO_DEPTH))));
signal wr_addr : unsigned(addr_width-1 downto 0);
signal wr_ready : std_logic;
signal rd_addr : unsigned(addr_width-1 downto 0);
signal rd_ready : std_logic;
signal full_sig : std_logic;
signal empty_sig : std_logic;
type bram_type is array(FIFO_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal bram : bram_type := (others => (others => '0'));
begin
wr_ready <= WR_EN AND NOT full_sig AND NOT RST;
rd_ready <= RD_EN AND NOT empty_sig AND NOT RST;
FULL <= full_sig;
EMPTY <= empty_sig;
-- -------------------------------------------------------------------------
-- BRAM AND DATA VALID FLAG GENERATOR
-- -------------------------------------------------------------------------
bram_mem : process (CLK)
begin
if (rising_edge(CLK)) then
if (wr_ready = '1') then
bram(to_integer(wr_addr)) <= DATA_IN;
end if;
DATA_OUT <= bram(to_integer(rd_addr));
end if;
end process;
data_vld_flag_gen : process (CLK)
begin
if (rising_edge(CLK)) then
DATA_VLD <= rd_ready;
end if;
end process;
-- -------------------------------------------------------------------------
-- FIFO WRITE ADDRESS COUNTER
-- -------------------------------------------------------------------------
wr_addr_cnt : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
wr_addr <= (others => '0');
elsif (wr_ready = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- FIFO READ ADDRESS COUNTER
-- -------------------------------------------------------------------------
rd_addr_cnt : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rd_addr <= (others => '0');
elsif (rd_ready = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- FULL FLAG GENERATOR
-- -------------------------------------------------------------------------
full_flag_gen : process (rd_addr, wr_addr)
begin
if (rd_addr = (wr_addr+1)) then
full_sig <= '1';
else
full_sig <= '0';
end if;
end process;
-- -------------------------------------------------------------------------
-- EMPTY FLAG GENERATOR
-- -------------------------------------------------------------------------
empty_flag_gen : process (rd_addr, wr_addr)
begin
if (rd_addr = wr_addr) then
empty_sig <= '1';
else
empty_sig <= '0';
end if;
end process;
end FULL;
|
mit
|
dfd7308d96739ba8f393713f83566401
| 0.479829 | 4.406838 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/sim_tb_top.vhd
| 2 | 35,045 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 8;
constant C3_P0_DATA_PORT_SIZE : integer := 64;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000200", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000003ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000200", x"01000000");
constant C3_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000400", x"03000000");
constant C3_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000005ff", x"04ffffff");
constant C3_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff000", x"f8000000");
constant C3_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000400", x"03000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr3_ctrl_spec_bank3_64b_32b is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_reset_n : out std_logic; c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000200";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000003ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000200";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000400";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000005ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000400"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(191 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(191 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p1_cmd_en : std_logic;
signal c3_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p1_cmd_empty : std_logic;
signal c3_p1_cmd_full : std_logic;
signal c3_p1_wr_en : std_logic;
signal c3_p1_wr_mask : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
signal c3_p1_wr_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_wr_full : std_logic;
signal c3_p1_wr_empty : std_logic;
signal c3_p1_wr_count : std_logic_vector(6 downto 0);
signal c3_p1_wr_underrun : std_logic;
signal c3_p1_wr_error : std_logic;
signal c3_p1_rd_en : std_logic;
signal c3_p1_rd_data : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
signal c3_p1_rd_full : std_logic;
signal c3_p1_rd_empty : std_logic;
signal c3_p1_rd_count : std_logic_vector(6 downto 0);
signal c3_p1_rd_overflow : std_logic;
signal c3_p1_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr3_ctrl_spec_bank3_64b_32b generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error,
c3_p1_cmd_clk => (c3_clk0),
c3_p1_cmd_en => c3_p1_cmd_en,
c3_p1_cmd_instr => c3_p1_cmd_instr,
c3_p1_cmd_bl => c3_p1_cmd_bl,
c3_p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
c3_p1_cmd_empty => c3_p1_cmd_empty,
c3_p1_cmd_full => c3_p1_cmd_full,
c3_p1_wr_clk => (c3_clk0),
c3_p1_wr_en => c3_p1_wr_en,
c3_p1_wr_mask => c3_p1_wr_mask,
c3_p1_wr_data => c3_p1_wr_data,
c3_p1_wr_full => c3_p1_wr_full,
c3_p1_wr_empty => c3_p1_wr_empty,
c3_p1_wr_count => c3_p1_wr_count,
c3_p1_wr_underrun => c3_p1_wr_underrun,
c3_p1_wr_error => c3_p1_wr_error,
c3_p1_rd_clk => (c3_clk0),
c3_p1_rd_en => c3_p1_rd_en,
c3_p1_rd_data => c3_p1_rd_data,
c3_p1_rd_full => c3_p1_rd_full,
c3_p1_rd_empty => c3_p1_rd_empty,
c3_p1_rd_count => c3_p1_rd_count,
c3_p1_rd_overflow => c3_p1_rd_overflow,
c3_p1_rd_error => c3_p1_rd_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C3_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C3_p1_DATA_MODE,
C_p1_END_ADDRESS => C3_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C3_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C3_p1_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p1_mcb_cmd_en_o => c3_p1_cmd_en,
p1_mcb_cmd_instr_o => c3_p1_cmd_instr,
p1_mcb_cmd_bl_o => c3_p1_cmd_bl,
p1_mcb_cmd_addr_o => c3_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c3_p1_cmd_full,
p1_mcb_wr_en_o => c3_p1_wr_en,
p1_mcb_wr_mask_o => c3_p1_wr_mask,
p1_mcb_wr_data_o => c3_p1_wr_data,
p1_mcb_wr_full_i => c3_p1_wr_full,
p1_mcb_wr_fifo_counts => c3_p1_wr_count,
p1_mcb_rd_en_o => c3_p1_rd_en,
p1_mcb_rd_data_i => c3_p1_rd_data,
p1_mcb_rd_empty_i => c3_p1_rd_empty,
p1_mcb_rd_fifo_counts => c3_p1_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
gpl-3.0
|
e02e1303921a9e84e57a9dffbc3fe678
| 0.451733 | 3.312069 | false | false | false | false |
kuba-moo/VHDL-precise-packet-generator
|
tb_uart_tx.vhd
| 1 | 2,643 |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_uart_tx IS
END tb_uart_tx;
ARCHITECTURE behavior OF tb_uart_tx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_tx
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
FreqEn : IN std_logic;
Byte : IN std_logic_vector(7 downto 0);
Kick : IN std_logic;
RsTx : OUT std_logic;
Busy : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '1';
signal FreqEn : std_logic := '0';
signal Byte : std_logic_vector(7 downto 0) := X"AA";
signal Kick : std_logic := '0';
--Outputs
signal RsTx : std_logic;
signal Busy : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: uart_tx PORT MAP (
Clk => Clk,
Rst => Rst,
FreqEn => FreqEn,
Byte => Byte,
Kick => Kick,
RsTx => RsTx,
Busy => Busy
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Frequenct enable process
Freq_process :process
begin
FreqEn <= '0';
wait for Clk_period * 2;
FreqEn <= '1';
wait for Clk_period;
end process;
-- Kick process
Kick_process :process
begin
Kick <= '0';
Byte <= X"00";
wait for Clk_period * 25;
Kick <= '1';
Byte <= X"55";
wait for Clk_period;
Byte <= X"00";
wait for Clk_period;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Rst <= '0';
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
54732c4c74b37b265a6546de93891de8
| 0.611805 | 3.595918 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/i2c-master/i2c_master_byte_ctrl.vhd
| 2 | 7,866 |
-- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- ------------------------------------------------------------------
--
-- Permission:
--
-- Lattice SG Pte. Ltd. grants permission to use this code
-- pursuant to the terms of the Lattice Reference Design License Agreement.
--
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice SG Pte. Ltd.
-- 101 Thomson Road, United Square #07-02
-- Singapore 307591
--
--
-- TEL: 1-800-Lattice (USA and Canada)
-- +65-6631-2000 (Singapore)
-- +1-503-268-8001 (other locations)
--
-- web: http:--www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic; -- master clock
rst : in std_logic; -- synchronous active high reset
nReset : in std_logic; -- asynchronous active low reset
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- control inputs
start : in std_logic;
stop : in std_logic;
read : in std_logic;
write : in std_logic;
ack_in : in std_logic;
din : in std_logic_vector(7 downto 0);
-- status outputs
cmd_ack : out std_logic;
ack_out : out std_logic; -- i2c clock line input
dout : out std_logic_vector(7 downto 0);
i2c_al : in std_logic;
-- signals for bit_controller
core_cmd : out std_logic_vector(3 downto 0);
core_txd : out std_logic;
core_rxd : in std_logic;
core_ack : in std_logic
);
end;
architecture arch of i2c_master_byte_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "1000";
constant ST_IDLE : std_logic_vector(4 downto 0) := "00000";
constant ST_START : std_logic_vector(4 downto 0) := "00001";
constant ST_READ : std_logic_vector(4 downto 0) := "00010";
constant ST_WRITE : std_logic_vector(4 downto 0) := "00100";
constant ST_ACK : std_logic_vector(4 downto 0) := "01000";
constant ST_STOP : std_logic_vector(4 downto 0) := "10000";
signal c_state : std_logic_vector(4 downto 0);
signal go : std_logic;
signal dcnt : std_logic_vector(2 downto 0);
signal cnt_done : std_logic;
signal sr : std_logic_vector(7 downto 0); --8bit shift register
signal shift, ld : std_logic;
signal cmd_ack_int : std_logic;
begin
go <= '1' when (((read = '1') OR (write = '1') OR (stop = '1')) AND (cmd_ack_int = '0')) else '0';
dout <= sr;
-- generate shift register
process(clk,nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= sr(6 downto 0) & core_rxd;
end if;
end if;
end process;
-- generate counter
process(clk,nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= "111";
elsif (shift = '1') then
dcnt <= dcnt - '1';
end if;
end if;
end process;
cnt_done <= '1' when (dcnt = "000") else '0';
-- state machine
process(clk,nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
elsif rising_edge(clk) then
if ((rst = '1') OR (i2c_al = '1')) then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
else
-- initially reset all signals
core_txd <= sr(7);
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
case (c_state) is
when ST_IDLE =>
if (go = '1') then
if (start = '1') then
c_state <= ST_START;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when ST_START =>
if (core_ack = '1') then
if (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when ST_WRITE =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when ST_READ =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_READ; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
shift <= '1';
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when ST_ACK =>
if (core_ack = '1') then
if (stop = '1') then
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
else
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
-- assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when ST_STOP =>
if (core_ack = '1') then
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
when others => NULL;
end case;
end if;
end if;
end process;
cmd_ack <= cmd_ack_int;
end arch;
|
gpl-3.0
|
e4c055fdcd462259bf9da665bb0172f5
| 0.481058 | 3.234375 | false | false | false | false |
makestuff/umdkv2
|
vhdl/mem-arbiter/mem_arbiter.vhdl
| 1 | 20,162 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_ctrl_pkg.all;
entity mem_arbiter is
generic (
NO_MONITOR : boolean
);
port (
clk_in : in std_logic;
reset_in : in std_logic;
-- Connetion to mem_pipe
ppReady_out : out std_logic;
ppCmd_in : in MCCmdType;
ppAddr_in : in std_logic_vector(22 downto 0);
ppData_in : in std_logic_vector(15 downto 0);
ppData_out : out std_logic_vector(15 downto 0);
ppRDV_out : out std_logic;
-- Connection to mem_ctrl
mcAutoMode_out : out std_logic;
mcReady_in : in std_logic;
mcCmd_out : out MCCmdType;
mcAddr_out : out std_logic_vector(22 downto 0);
mcData_out : out std_logic_vector(15 downto 0);
mcData_in : in std_logic_vector(15 downto 0);
mcRDV_in : in std_logic;
-- Connection to MegaDrive
mdDriveBus_out : out std_logic;
mdReset_in : in std_logic;
mdDTACK_out : out std_logic;
mdAddr_in : in std_logic_vector(22 downto 0);
mdData_io : inout std_logic_vector(15 downto 0);
mdOE_in : in std_logic;
mdAS_in : in std_logic;
mdLDSW_in : in std_logic;
mdUDSW_in : in std_logic;
-- Trace pipe
traceReset_in : in std_logic;
traceEnable_in : in std_logic;
traceData_out : out std_logic_vector(55 downto 0);
traceValid_out : out std_logic;
-- MegaDrive registers
regAddr_out : out std_logic_vector(2 downto 0);
regWrData_out : out std_logic_vector(15 downto 0);
regWrValid_out : out std_logic;
regRdData_in : in std_logic_vector(15 downto 0);
regRdStrobe_out : out std_logic;
regMapRam_in : in std_logic
);
end entity;
architecture rtl of mem_arbiter is
type StateType is (
S_RESET, -- MD in reset, host has access to SDRAM
S_IDLE, -- wait for mdOE_sync to go low when A22='0', indicating a MD cart read
-- Forced refresh loop on startup
S_FORCE_REFRESH_EXEC,
S_FORCE_REFRESH_NOP1,
S_FORCE_REFRESH_NOP2,
S_FORCE_REFRESH_NOP3,
-- Owned read
S_READ_OWNED_WAIT,
S_READ_OWNED_NOP1,
S_READ_OWNED_NOP2,
S_READ_OWNED_NOP3,
S_READ_OWNED_NOP4,
S_READ_OWNED_REFRESH,
S_READ_OWNED_FINISH,
-- Foreign read
S_READ_OTHER,
-- Owned write
S_WRITE_OWNED_NOP1,
S_WRITE_OWNED_NOP2,
S_WRITE_OWNED_NOP3,
S_WRITE_OWNED_NOP4,
S_WRITE_OWNED_EXEC,
S_WRITE_OWNED_FINISH,
-- Foreign write
S_WRITE_OTHER_NOP1,
S_WRITE_OTHER_NOP2,
S_WRITE_OTHER_NOP3,
S_WRITE_OTHER_NOP4,
S_WRITE_OTHER_EXEC,
S_WRITE_OTHER_FINISH,
-- Register write
S_WRITE_REG_NOP1,
S_WRITE_REG_NOP2,
S_WRITE_REG_NOP3,
S_WRITE_REG_NOP4,
S_WRITE_REG_EXEC,
S_WRITE_REG_FINISH
);
type BankType is array (0 to 15) of std_logic_vector(4 downto 0);
-- Registers
signal state : StateType := S_RESET;
signal state_next : StateType;
signal dataReg : std_logic_vector(15 downto 0) := (others => '0');
signal dataReg_next : std_logic_vector(15 downto 0);
signal addrReg : std_logic_vector(22 downto 0) := (others => '0');
signal addrReg_next : std_logic_vector(22 downto 0);
signal mdAS : std_logic;
signal mdAS_next : std_logic;
constant HB_MAX : unsigned(11 downto 0) := (others => '1');
signal hbCount : unsigned(11 downto 0) := (others => '0');
signal hbCount_next : unsigned(11 downto 0);
signal tsCount : unsigned(12 downto 0) := (others => '0');
signal tsCount_next : unsigned(12 downto 0);
function BANK_INIT return BankType is
begin
if ( NO_MONITOR ) then return (
"00000", "00001", "00010", "00011", "00100", "00101", "00110", "00111",
"01000", "01001", "01010", "01011", "01100", "01101", "01110", "01111");
else return (
"00000", "00001", "00010", "00011", "00100", "00101", "00110", "00111",
"11111", "01001", "01010", "01011", "01100", "01101", "01110", "01111");
end if;
end function;
signal memBank : BankType := BANK_INIT;
signal memBank_next : BankType;
signal bootInsn : std_logic_vector(15 downto 0);
-- Synchronise MegaDrive signals to sysClk
signal mdAS_sync : std_logic := '1';
signal mdOE_sync : std_logic := '1';
signal mdDSW_sync : std_logic_vector(1 downto 0) := "11";
signal mdAddr_sync : std_logic_vector(22 downto 0) := (others => '0');
signal mdData_sync : std_logic_vector(15 downto 0) := (others => '0');
constant TR_RD : std_logic_vector(2 downto 0) := "011";
constant TR_HB : std_logic_vector(2 downto 0) := "100";
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_RESET;
dataReg <= (others => '0');
addrReg <= (others => '0');
mdAddr_sync <= (others => '0');
mdAS_sync <= '1';
mdOE_sync <= '1';
mdDSW_sync <= "11";
mdData_sync <= (others => '0');
mdAS <= '1';
hbCount <= (others => '0');
tsCount <= (others => '0');
memBank <= BANK_INIT;
else
state <= state_next;
dataReg <= dataReg_next;
addrReg <= addrReg_next;
mdAddr_sync <= mdAddr_in;
mdAS_sync <= mdAS_in;
mdOE_sync <= mdOE_in;
mdDSW_sync <= mdUDSW_in & mdLDSW_in;
mdData_sync <= mdData_io;
mdAS <= mdAS_next;
hbCount <= hbCount_next;
tsCount <= tsCount_next;
memBank <= memBank_next;
end if;
end if;
end process;
-- #############################################################################################
-- ## State machine to control the SDRAM ##
-- #############################################################################################
process(
state, dataReg, addrReg,
mdOE_sync, mdDSW_sync, mdAddr_sync, mdData_sync, mdAS_sync, mdAS, mdReset_in,
mcReady_in, mcData_in, mcRDV_in,
ppCmd_in, ppAddr_in, ppData_in,
regMapRam_in, bootInsn, memBank, regRdData_in,
hbCount, tsCount, traceEnable_in, traceReset_in
)
-- Function to generate SDRAM physical address using MD address and memBank (SSF2) regs
impure function transAddr(addr : std_logic_vector(22 downto 0)) return std_logic_vector is
begin
return memBank(to_integer(unsigned(addr(21 downto 18)))) & addr(17 downto 0);
end function;
begin
-- Local register defaults
state_next <= state;
dataReg_next <= dataReg;
addrReg_next <= addrReg;
mdAS_next <= mdAS;
memBank_next <= memBank;
-- Memory controller defaults
mcAutoMode_out <= '0'; -- don't auto-refresh by default.
mcCmd_out <= MC_NOP;
mcAddr_out <= (others => 'X');
mcData_out <= (others => 'X');
-- Pipe defaults
ppData_out <= (others => 'X');
ppReady_out <= '0';
ppRDV_out <= '0';
-- Trace defaults
traceData_out <= (others => 'X');
traceValid_out <= '0';
-- MegaDrive registers
regAddr_out <= (others => 'X');
regWrData_out <= (others => 'X');
regWrValid_out <= '0';
regRdStrobe_out <= '0';
-- MegaDrive data bus
mdData_io <= (others => 'Z');
mdDriveBus_out <= '0';
-- Maybe send heartbeat message
if ( traceReset_in = '1' ) then
tsCount_next <= (others => '0');
hbCount_next <= (others => '0');
else
tsCount_next <= tsCount + 1;
hbCount_next <= hbCount + 1;
end if;
if ( hbCount = HB_MAX ) then
traceData_out <= TR_HB & std_logic_vector(tsCount) & x"000000" & x"0000";
traceValid_out <= traceEnable_in;
end if;
case state is
-- -------------------------------------------------------------------------------------
-- Whilst the MD is in reset, the SDRAM does auto-refresh, and the host has complete
-- control over it.
--
when S_RESET =>
-- Enable auto-refresh
mcAutoMode_out <= '1';
-- Drive mem-ctrl inputs with mem-pipe outputs
mcCmd_out <= ppCmd_in;
mcAddr_out <= ppAddr_in;
mcData_out <= ppData_in;
-- Drive mem-pipe inputs with mem-ctrl outputs
ppData_out <= mcData_in;
ppReady_out <= mcReady_in;
ppRDV_out <= mcRDV_in;
-- Proceed when host or the soft-reset sequence releases MD from reset
if ( mdReset_in = '0' and mcReady_in = '1' ) then
state_next <= S_FORCE_REFRESH_EXEC;
end if;
-- -------------------------------------------------------------------------------------
-- There's a delay of ~100ms between deasserting reset and the first instruction-fetch,
-- which can be used profitably by forcing a series of SDRAM refresh cycles.
--
when S_FORCE_REFRESH_EXEC =>
mcCmd_out <= MC_REF; -- issue refresh cycle
state_next <= S_FORCE_REFRESH_NOP1;
when S_FORCE_REFRESH_NOP1 =>
state_next <= S_FORCE_REFRESH_NOP2;
when S_FORCE_REFRESH_NOP2 =>
state_next <= S_FORCE_REFRESH_NOP3;
when S_FORCE_REFRESH_NOP3 =>
if ( mdOE_sync = '1' ) then
state_next <= S_FORCE_REFRESH_EXEC; -- loop back for another refresh
else
state_next <= S_IDLE; -- 68000 has started fetching
end if;
-- -------------------------------------------------------------------------------------
-- Wait until the in-progress owned read completes, then register the result, send to
-- the trace FIFO and proceed.
--
when S_READ_OWNED_WAIT =>
mdData_io <= mcData_in;
mdDriveBus_out <= '1';
if ( mcRDV_in = '1' ) then
state_next <= S_READ_OWNED_NOP1;
if ( regMapRam_in = '1' ) then
dataReg_next <= mcData_in;
traceData_out <= TR_RD & std_logic_vector(tsCount) & addrReg & mdAS & mcData_in;
else
dataReg_next <= bootInsn;
traceData_out <= TR_RD & std_logic_vector(tsCount) & addrReg & mdAS & bootInsn;
end if;
traceValid_out <= traceEnable_in;
hbCount_next <= (others => '0'); -- reset heartbeat
end if;
-- Give the host enough time for one I/O cycle, if it wants it.
--
when S_READ_OWNED_NOP1 =>
mdData_io <= dataReg;
mdDriveBus_out <= '1';
ppReady_out <= mcReady_in;
mcCmd_out <= ppCmd_in;
mcAddr_out <= ppAddr_in;
mcData_out <= ppData_in;
state_next <= S_READ_OWNED_NOP2;
when S_READ_OWNED_NOP2 =>
mdData_io <= dataReg;
mdDriveBus_out <= '1';
state_next <= S_READ_OWNED_NOP3;
when S_READ_OWNED_NOP3 =>
mdData_io <= dataReg;
mdDriveBus_out <= '1';
state_next <= S_READ_OWNED_NOP4;
when S_READ_OWNED_NOP4 =>
mdData_io <= dataReg;
mdDriveBus_out <= '1';
ppData_out <= mcData_in;
ppRDV_out <= mcRDV_in;
state_next <= S_READ_OWNED_REFRESH;
-- Start a refresh cycle, then wait for it to complete.
--
when S_READ_OWNED_REFRESH =>
mdData_io <= dataReg;
mdDriveBus_out <= '1';
state_next <= S_READ_OWNED_FINISH;
mcCmd_out <= MC_REF;
when S_READ_OWNED_FINISH =>
mdData_io <= dataReg;
mdDriveBus_out <= '1';
if ( mcReady_in = '1' and mdOE_sync = '1' ) then
state_next <= S_IDLE;
end if;
-- -------------------------------------------------------------------------------------
-- Wait for the in-progress foreign read to complete, then send to the trace FIFO and go
-- back to S_IDLE.
--
when S_READ_OTHER =>
if ( mdOE_sync = '1' ) then
state_next <= S_IDLE;
traceData_out <= TR_RD & std_logic_vector(tsCount) & addrReg & mdAS & mdData_sync;
traceValid_out <= traceEnable_in;
hbCount_next <= (others => '0'); -- reset heartbeat
end if;
-- -------------------------------------------------------------------------------------
-- An owned write has been requested, but things are not yet stable so give the host
-- enough time for one I/O cycle, if it wants it - this will provide enough of a delay
-- for the write masks and data to stabilise.
--
when S_WRITE_OWNED_NOP1 =>
ppReady_out <= mcReady_in;
mcCmd_out <= ppCmd_in;
mcAddr_out <= ppAddr_in;
mcData_out <= ppData_in;
state_next <= S_WRITE_OWNED_NOP2;
when S_WRITE_OWNED_NOP2 =>
state_next <= S_WRITE_OWNED_NOP3;
when S_WRITE_OWNED_NOP3 =>
state_next <= S_WRITE_OWNED_NOP4;
when S_WRITE_OWNED_NOP4 =>
ppData_out <= mcData_in;
ppRDV_out <= mcRDV_in;
state_next <= S_WRITE_OWNED_EXEC;
-- Now execute the owned write.
--
when S_WRITE_OWNED_EXEC =>
state_next <= S_WRITE_OWNED_FINISH;
traceData_out <= '0' & mdDSW_sync & std_logic_vector(tsCount) & addrReg & mdAS & mdData_sync;
traceValid_out <= traceEnable_in;
hbCount_next <= (others => '0'); -- reset heartbeat
if ( addrReg(21) = '1' ) then
-- Only actually write to the 0x400000-0x7FFFFF range
mcCmd_out <= MC_WR;
mcAddr_out <= transAddr(addrReg);
mcData_out <= mdData_sync;
end if;
when S_WRITE_OWNED_FINISH =>
if ( mdDSW_sync = "11" and mcReady_in = '1' ) then
state_next <= S_IDLE;
end if;
-- -------------------------------------------------------------------------------------
-- A foreign write has been requested, but things are not yet stable so give the host
-- enough time for one I/O cycle, if it wants it - this will provide enough of a delay
-- for the write masks and data to stabilise.
--
when S_WRITE_OTHER_NOP1 =>
ppReady_out <= mcReady_in;
mcCmd_out <= ppCmd_in;
mcAddr_out <= ppAddr_in;
mcData_out <= ppData_in;
state_next <= S_WRITE_OTHER_NOP2;
when S_WRITE_OTHER_NOP2 =>
state_next <= S_WRITE_OTHER_NOP3;
when S_WRITE_OTHER_NOP3 =>
state_next <= S_WRITE_OTHER_NOP4;
when S_WRITE_OTHER_NOP4 =>
ppData_out <= mcData_in;
ppRDV_out <= mcRDV_in;
state_next <= S_WRITE_OTHER_EXEC;
-- Now execute the foreign write - it'll be handled by someone else so just copy it over
-- to the trace FIFO.
--
when S_WRITE_OTHER_EXEC =>
state_next <= S_WRITE_OTHER_FINISH;
traceData_out <= '0' & mdDSW_sync & std_logic_vector(tsCount) & addrReg & mdAS & mdData_sync;
traceValid_out <= traceEnable_in;
hbCount_next <= (others => '0'); -- reset heartbeat
when S_WRITE_OTHER_FINISH =>
if ( mdDSW_sync = "11" ) then
state_next <= S_IDLE;
end if;
-- -------------------------------------------------------------------------------------
-- A register write has been requested, but things are not yet stable so give the host
-- enough time for one I/O cycle, if it wants it - this will provide enough of a delay
-- for the write masks and data to stabilise.
--
when S_WRITE_REG_NOP1 =>
ppReady_out <= mcReady_in;
mcCmd_out <= ppCmd_in;
mcAddr_out <= ppAddr_in;
mcData_out <= ppData_in;
state_next <= S_WRITE_REG_NOP2;
when S_WRITE_REG_NOP2 =>
state_next <= S_WRITE_REG_NOP3;
when S_WRITE_REG_NOP3 =>
state_next <= S_WRITE_REG_NOP4;
when S_WRITE_REG_NOP4 =>
ppData_out <= mcData_in;
ppRDV_out <= mcRDV_in;
state_next <= S_WRITE_REG_EXEC;
-- Now execute the register write.
--
when S_WRITE_REG_EXEC =>
state_next <= S_WRITE_REG_FINISH;
traceData_out <= '0' & mdDSW_sync & std_logic_vector(tsCount) & addrReg & mdAS & mdData_sync;
traceValid_out <= traceEnable_in;
hbCount_next <= (others => '0'); -- reset heartbeat
if ( addrReg(6 downto 3) = "1111" ) then
memBank_next(to_integer(unsigned(mdData_sync(6) & addrReg(2 downto 0)))) <= mdData_sync(4 downto 0);
elsif ( addrReg(6 downto 3) = "0000" ) then
regAddr_out <= addrReg(2 downto 0);
regWrData_out <= mdData_sync;
regWrValid_out <= '1';
end if;
when S_WRITE_REG_FINISH =>
if ( mdDSW_sync = "11" and mcReady_in = '1' ) then
state_next <= S_IDLE;
end if;
-- -------------------------------------------------------------------------------------
-- S_IDLE & others.
--
when others =>
-- See if the host wants MD back in reset
if ( mdReset_in = '1' ) then
-- MD back in reset, so give host full control again
state_next <= S_RESET;
end if;
if ( mdOE_sync = '0' ) then
-- MD is reading
addrReg_next <= mdAddr_sync;
mdAS_next <= mdAS_sync;
if ( mdAddr_sync(22 downto 7) = x"A130" ) then
-- MD is reading the 0xA130xx range
state_next <= S_READ_OWNED_NOP1;
regAddr_out <= mdAddr_sync(2 downto 0);
dataReg_next <= regRdData_in;
regRdStrobe_out <= '1';
traceData_out <= TR_RD & std_logic_vector(tsCount) & mdAddr_sync & mdAS_sync & regRdData_in;
traceValid_out <= traceEnable_in;
hbCount_next <= (others => '0'); -- reset heartbeat
elsif ( mdAddr_sync(22) = '0' ) then
-- MD is doing an owned read (i.e in our address ranges)
state_next <= S_READ_OWNED_WAIT;
mcCmd_out <= MC_RD;
mcAddr_out <= transAddr(mdAddr_sync);
else
-- MD is doing a foreign read (i.e not in our address ranges)
state_next <= S_READ_OTHER;
end if;
elsif ( mdDSW_sync /= "11" ) then
-- MD is writing
addrReg_next <= mdAddr_sync;
mdAS_next <= mdAS_sync;
if ( mdAddr_sync(22 downto 7) = x"A130" ) then
-- MD is writing 0xA130xx range
if ( mdAddr_sync(6 downto 0) = "1111000" ) then
-- The 0xA130F0 register is not mapped
state_next <= S_WRITE_OTHER_NOP1;
else
-- All others are mapped
state_next <= S_WRITE_REG_NOP1;
end if;
elsif ( mdAddr_sync(22) = '0' ) then
-- MD is doing an owned write (i.e in our address ranges)
state_next <= S_WRITE_OWNED_NOP1;
else
-- MD is doing a foreign write (i.e not in our address ranges)
state_next <= S_WRITE_OTHER_NOP1;
end if;
end if;
end case;
end process;
-- Boot ROM - just load the bootblock from flash into onboard RAM and start it running
with addrReg(4 downto 0) select bootInsn <=
x"0000" when "00000", -- initial SSP
x"0000" when "00001",
x"0000" when "00010", -- initial PC
x"0008" when "00011",
x"41F9" when "00100", -- lea 0xA13000, a0
x"00A1" when "00101",
x"3000" when "00110",
x"43F9" when "00111", -- lea 0xFF0000, a1
x"00FF" when "01000",
x"0000" when "01001",
x"317C" when "01010", -- move.w #(TURBO|FLASH), 4(a0)
x"0005" when "01011",
x"0004" when "01100",
x"30BC" when "01101", -- move.w #0x0306, (a0)
x"0306" when "01110",
x"30BC" when "01111", -- move.w #0x0000, (a0)
x"0000" when "10000",
x"30BC" when "10001", -- move.w #0xFFFF, (a0)
x"FFFF" when "10010",
x"707F" when "10011", -- moveq #127, d0 ; copy 128 words = 256 bytes
x"32D0" when "10100", -- move.w (a0), (a1)+
x"51C8" when "10101", -- dbra d0, *-4
x"FFFC" when "10110",
x"4EF9" when "10111", -- jmp 0xFF0000
x"00FF" when "11000",
x"0000" when "11001",
(others => 'X') when others;
-- A verifiable test bootblock can be installed like this:
--
-- $ printf '\x31\x7C\x00\x00\x00\x04\x33\xFC\x60\xFE\x00\x40\x00\x00\x4E\xF9\x00\x40\x00\x00' > bra.bin
-- $ $HOME/makestuff/apps/flcli/lin.x64/rel/flcli -v 1d50:602b:0002 -p J:A7A0A3A1:spi-talk.xsvf
-- $ $HOME/makestuff/apps/gordon/lin.x64/rel/gordon -v 1d50:602b:0002 -t indirect:1 -w bra.bin:0x60000
-- $ $HOME/makestuff/apps/gordon/lin.x64/rel/gordon -v 1d50:602b:0002 -t indirect:1 -r foo.bin:0x60000:256
-- $ dis68 foo.bin 0 3
-- 0x000000 move.w #0, 4(a0)
-- 0x000006 move.w #0x60FE, 0x400000 ; opcode for bra.s -2
-- 0x00000E jmp 0x400000
--
-- It consists of the opcodes to deselect the flash (and thereby map in the SDRAM), then write
-- the opcode for bra.s -2 to 0x400000 and jump to it. Reads from onboard RAM don't show on the
-- trace, but you can see the infinite bra.s -2 loop executing OK.
mdDTACK_out <= '0'; -- for now, just rely on MD's auto-DTACK
end architecture;
|
gpl-3.0
|
49338bd98ffad672da2f2456b4093069
| 0.592005 | 3.061342 | false | false | false | false |
cretingame/Yarr-fw
|
ip-cores/spartan6/rx_bridge_ctrl_fifo.vhd
| 2 | 10,274 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rx_bridge_ctrl_fifo.vhd when simulating
-- the core, rx_bridge_ctrl_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rx_bridge_ctrl_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END rx_bridge_ctrl_fifo;
ARCHITECTURE rx_bridge_ctrl_fifo_a OF rx_bridge_ctrl_fifo IS
-- synthesis translate_off
COMPONENT wrapped_rx_bridge_ctrl_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rx_bridge_ctrl_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 8,
c_default_value => "BlankString",
c_din_width => 64,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 64,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 255,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 254,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 8,
c_rd_depth => 256,
c_rd_freq => 1,
c_rd_pntr_width => 8,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 8,
c_wr_depth => 256,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 8,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rx_bridge_ctrl_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END rx_bridge_ctrl_fifo_a;
|
gpl-3.0
|
7ed9453c4f134f192cb215b12a48a286
| 0.538252 | 3.322768 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/receiver.vhd
| 3 | 6,075 |
----------------------------------------------------------------------------------
-- receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the serial port. The first byte is the commands
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received it will be kept available for 10 cycles
-- on the op and data outputs. A valid command can be detected by checking if the
-- execute output is set. After 10 cycles the registers will be cleared
-- automatically and the receiver waits for new data from the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity receiver is
generic (
FREQ : integer;
RATE : integer
);
Port ( rx : in STD_LOGIC;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out STD_LOGIC_VECTOR (7 downto 0);
data : out STD_LOGIC_VECTOR (31 downto 0);
execute : out STD_LOGIC
);
end receiver;
architecture Behavioral of receiver is
type UART_STATES is (INIT, WAITSTOP, WAITSTART, WAITBEGIN, READBYTE, ANALYZE, READY);
constant BITLENGTH : integer := FREQ / RATE;
signal counter, ncounter : integer range 0 to BITLENGTH; -- clock prescaling counter
signal bitcount, nbitcount : integer range 0 to 8; -- count rxed bits of current byte
signal bytecount, nbytecount : integer range 0 to 5; -- count rxed bytes of current command
signal state, nstate : UART_STATES; -- receiver state
signal opcode, nopcode : std_logic_vector (7 downto 0); -- opcode byte
signal dataBuf, ndataBuf : std_logic_vector (31 downto 0); -- data dword
begin
op <= opcode;
data <= dataBuf;
process(clock, reset)
begin
if reset = '1' then
state <= INIT;
elsif rising_edge(clock) then
counter <= ncounter;
bitcount <= nbitcount;
bytecount <= nbytecount;
dataBuf <= ndataBuf;
opcode <= nopcode;
state <= nstate;
end if;
end process;
process(trxClock, state, counter, bitcount, bytecount, dataBuf, opcode, rx)
begin
case state is
-- reset uart
when INIT =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= (others => '0');
ndataBuf <= (others => '0');
nstate <= WAITSTOP;
-- wait for stop bit
when WAITSTOP =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '1' then
nstate <= WAITSTART;
else
nstate <= state;
end if;
-- wait for start bit
when WAITSTART =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if rx = '0' then
nstate <= WAITBEGIN;
else
nstate <= state;
end if;
-- wait for first half of start bit
when WAITBEGIN =>
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = BITLENGTH / 2 then
ncounter <= 0;
nstate <= READBYTE;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nstate <= state;
end if;
-- receive byte
when READBYTE =>
if counter = BITLENGTH then
ncounter <= 0;
nbitcount <= bitcount + 1;
if bitcount = 8 then
nbytecount <= bytecount + 1;
nstate <= ANALYZE;
nopcode <= opcode;
ndataBuf <= dataBuf;
else
nbytecount <= bytecount;
if bytecount = 0 then
nopcode <= rx & opcode(7 downto 1);
ndataBuf <= dataBuf;
else
nopcode <= opcode;
ndataBuf <= rx & dataBuf(31 downto 1);
end if;
nstate <= state;
end if;
else
if trxClock = '1' then
ncounter <= counter + 1;
else
ncounter <= counter;
end if;
nbitcount <= bitcount;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
nstate <= state;
end if;
-- check if long or short command has been fully received
when ANALYZE =>
ncounter <= 0;
nbitcount <= 0;
nbytecount <= bytecount;
nopcode <= opcode;
ndataBuf <= dataBuf;
-- long command when 5 bytes have been received
if bytecount = 5 then
nstate <= READY;
-- short command when set flag not set
elsif opcode(7) = '0' then
nstate <= READY;
-- otherwise continue receiving
else
nstate <= WAITSTOP;
end if;
-- done, give 10 cycles for processing
when READY =>
ncounter <= counter + 1;
nbitcount <= 0;
nbytecount <= 0;
nopcode <= opcode;
ndataBuf <= dataBuf;
if counter = 10 then
nstate <= INIT;
else
nstate <= state;
end if;
end case;
end process;
-- set execute flag properly
process(state)
begin
if state = READY then
execute <= '1';
else
execute <= '0';
end if;
end process;
end Behavioral;
|
gpl-2.0
|
5b504cde2244f97082a5691f96c52fab
| 0.609383 | 3.842505 | false | false | false | false |
techwoes/sump
|
logic_analyzer2/eia232.vhd
| 3 | 4,310 |
----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_prescaler: prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
|
gpl-2.0
|
a92b2c1c12c69423f06833f129cab8fd
| 0.614153 | 3.260212 | false | false | false | false |
makestuff/umdkv2
|
vhdl/umdkv2_rtl.vhdl
| 1 | 15,934 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_ctrl_pkg.all;
entity umdkv2 is
generic (
RESET_INIT : std_logic;
MAPRAM_INIT : std_logic;
MAPRAM_FORCE : boolean;
NO_MONITOR : boolean
);
port (
clk_in : in std_logic;
reset_in : in std_logic;
-- DVR interface ---------------------------------------------------------------------------
chanAddr_in : in std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_in : in std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_in : in std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
h2fReady_out : out std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_out : out std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_out : out std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_in : in std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- SDRAM interface -------------------------------------------------------------------------
ramCmd_out : out std_logic_vector(2 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic;
-- MegaDrive interface ---------------------------------------------------------------------
mdReset_out : out std_logic;
mdDriveBus_out : out std_logic;
mdDTACK_out : out std_logic;
mdAddr_in : in std_logic_vector(22 downto 0);
mdData_io : inout std_logic_vector(15 downto 0);
mdOE_in : in std_logic;
mdAS_in : in std_logic;
mdLDSW_in : in std_logic;
mdUDSW_in : in std_logic;
-- SPI bus ---------------------------------------------------------------------------------
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic;
spiCS_out : out std_logic_vector(1 downto 0)
);
end entity;
architecture structural of umdkv2 is
-- Command Pipe input
signal cmdData : std_logic_vector(7 downto 0);
signal cmdValid : std_logic;
signal cmdReady : std_logic;
-- 8-bit Command Pipe (FIFO -> 8to16)
signal cmd8Data : std_logic_vector(7 downto 0);
signal cmd8Valid : std_logic;
signal cmd8Ready : std_logic;
-- 16-bit Command Pipe (8to16 -> MemPipe)
signal cmd16Data : std_logic_vector(15 downto 0);
signal cmd16Valid : std_logic;
signal cmd16Ready : std_logic;
-- 16-bit Response Pipe (MemPipe -> 16to8)
signal rsp16Data : std_logic_vector(15 downto 0);
signal rsp16Valid : std_logic;
signal rsp16Ready : std_logic;
-- 8-bit Response Pipe (16to8 -> FIFO)
signal rsp8Data : std_logic_vector(7 downto 0);
signal rsp8Valid : std_logic;
signal rsp8Ready : std_logic;
-- Response Pipe output
signal rspData : std_logic_vector(7 downto 0);
signal rspValid : std_logic;
signal rspReady : std_logic;
-- Pipe interface
signal ppReady : std_logic;
signal ppCmd : MCCmdType;
signal ppAddr : std_logic_vector(22 downto 0);
signal ppDataWr : std_logic_vector(15 downto 0);
signal ppDataRd : std_logic_vector(15 downto 0);
signal ppRDV : std_logic;
-- Memory controller interface
signal mcAutoMode : std_logic;
signal mcReady : std_logic;
signal mcCmd : MCCmdType;
signal mcAddr : std_logic_vector(22 downto 0);
signal mcDataWr : std_logic_vector(15 downto 0);
signal mcDataRd : std_logic_vector(15 downto 0);
signal mcRDV : std_logic;
-- Registers implementing the channels
signal reg1 : std_logic_vector(1 downto 0) := '0' & RESET_INIT;
signal reg1_next : std_logic_vector(1 downto 0);
signal mdCfg : std_logic_vector(3 downto 0) := (others => '0');
signal mdCfg_next : std_logic_vector(3 downto 0);
signal mapRam : std_logic := MAPRAM_INIT;
signal mapRam_next : std_logic;
-- Trace data
signal tfiData : std_logic_vector(55 downto 0);
signal tfiValid : std_logic;
signal tfiReady : std_logic;
signal tfoData : std_logic_vector(55 downto 0);
signal tfoValid : std_logic;
signal tfoReady : std_logic;
signal trcData : std_logic_vector(7 downto 0);
signal trcValid : std_logic;
signal trcReady : std_logic;
signal tfDepth : std_logic_vector(12 downto 0);
-- MD register writes
signal regAddr : std_logic_vector(2 downto 0);
signal regWrData : std_logic_vector(15 downto 0);
signal regWrValid : std_logic;
signal regRdData : std_logic_vector(15 downto 0);
signal regRdStrobe : std_logic;
signal spiRdData : std_logic_vector(15 downto 0);
signal spiRdStrobe : std_logic;
signal spiWrValid : std_logic;
-- SPI send & receive pipes
signal sendData : std_logic_vector(7 downto 0);
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0);
signal recvValid : std_logic;
signal recvReady : std_logic;
-- Reset stuff
signal mdReset : std_logic;
signal softReset : std_logic;
-- Bits in the host config register reg1
constant RESET : integer := 0;
constant TRACE : integer := 1;
-- Bits in the MD config register mdCfg
constant TURBO : integer := 0;
constant SUPPRESS : integer := 1;
constant CHIPSEL : integer := 2;
-- Chip-select constants
constant FLASH : std_logic_vector(1 downto 0) := "01";
constant SDCARD : std_logic_vector(1 downto 0) := "10";
constant FLASHCS : integer := 0;
constant SDCARDCS : integer := 1;
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
reg1 <= '0' & RESET_INIT;
mdCfg <= (others => '0');
mapRam <= MAPRAM_INIT;
else
reg1 <= reg1_next;
mdCfg <= mdCfg_next;
if ( MAPRAM_FORCE ) then
mapRam <= MAPRAM_INIT;
else
mapRam <= mapRam_next;
end if;
end if;
end if;
end process;
-- Select values to return for each channel when the host is reading
with chanAddr_in select f2hData_out <=
rspData when "0000000",
"000000" & reg1 when "0000001",
trcData when "0000010",
trcValid & "00" & tfDepth(12 downto 8) when "0000011",
tfDepth(7 downto 0) when "0000100",
x"00" when others;
-- Generate valid signal for responding to host reads
with chanAddr_in select f2hValid_out <=
rspValid when "0000000",
'1' when "0000001",
trcValid when "0000010",
'1' when "0000011",
'1' when "0000100",
'0' when others;
trcReady <=
f2hReady_in when chanAddr_in = "0000010"
else '0';
-- Trace FIFO
trace_fifo: entity work.trace_fifo_wrapper
port map (
clk_in => clk_in,
depth_out => tfDepth,
-- Production end
inputData_in => tfiData,
inputValid_in => tfiValid,
inputReady_out => tfiReady,
-- Consumption end
outputData_out => tfoData,
outputValid_out => tfoValid,
outputReady_in => tfoReady
);
-- Trace Pipe 56->8 converter
trace_conv: entity work.conv_56to8
port map (
clk_in => clk_in,
reset_in => reset_in,
data56_in => tfoData,
valid56_in => tfoValid,
ready56_out => tfoReady,
data8_out => trcData,
valid8_out => trcValid,
ready8_in => trcReady
);
-- Instantiate the memory arbiter for testing
spi_funnel: entity work.spi_funnel
port map (
clk_in => clk_in,
reset_in => '0',
-- CPU I/O
cpuByteWide_in => regAddr(0),
cpuWrData_in => regWrData,
cpuWrValid_in => spiWrValid,
cpuRdData_out => spiRdData,
cpuRdStrobe_in => spiRdStrobe,
-- Sending SPI data
sendData_out => sendData,
sendValid_out => sendValid,
sendReady_in => sendReady,
-- Receiving SPI data
recvData_in => recvData,
recvValid_in => recvValid,
recvReady_out => recvReady
);
-- SPI master
spi_master : entity work.spi_master
generic map (
SLOW_COUNT => "111011", -- spiClk = sysClk/120 (400kHz @48MHz)
FAST_COUNT => "000000", -- spiClk = sysClk/2 (24MHz @48MHz)
BIT_ORDER => '1' -- MSB first
)
port map (
reset_in => '0',
clk_in => clk_in,
-- Send pipe
turbo_in => mdCfg(TURBO),
suppress_in => mdCfg(SUPPRESS),
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
-- Receive pipe
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
-- SPI interface
spiClk_out => spiClk_out,
spiData_out => spiData_out,
spiData_in => spiData_in
);
-- Command Pipe FIFO
cmd_fifo: entity work.fifo
generic map (
WIDTH => 8,
DEPTH => 2
)
port map (
clk_in => clk_in,
reset_in => '0',
depth_out => open,
-- Input pipe
inputData_in => cmdData,
inputValid_in => cmdValid,
inputReady_out => cmdReady,
-- Output pipe
outputData_out => cmd8Data,
outputValid_out => cmd8Valid,
outputReady_in => cmd8Ready
);
-- Command Pipe 8->16 converter
cmd_conv: entity work.conv_8to16
port map (
clk_in => clk_in,
reset_in => '0',
data8_in => cmd8Data,
valid8_in => cmd8Valid,
ready8_out => cmd8Ready,
data16_out => cmd16Data,
valid16_out => cmd16Valid,
ready16_in => cmd16Ready
);
-- Response Pipe 16->8 converter
rsp_conv: entity work.conv_16to8
port map (
clk_in => clk_in,
reset_in => '0',
data16_in => rsp16Data,
valid16_in => rsp16Valid,
ready16_out => rsp16Ready,
data8_out => rsp8Data,
valid8_out => rsp8Valid,
ready8_in => rsp8Ready
);
-- Response Pipe FIFO
rsp_fifo: entity work.fifo
generic map (
WIDTH => 8,
DEPTH => 2
)
port map (
clk_in => clk_in,
reset_in => '0',
depth_out => open,
-- Input pipe
inputData_in => rsp8Data,
inputValid_in => rsp8Valid,
inputReady_out => rsp8Ready,
-- Output pipe
outputData_out => rspData,
outputValid_out => rspValid,
outputReady_in => rspReady
);
-- Memory Pipe Unit (connects command & response pipes to the memory controller)
mem_pipe: entity work.mem_pipe
port map (
clk_in => clk_in,
reset_in => reset_in,
-- Command pipe
cmdData_in => cmd16Data,
cmdValid_in => cmd16Valid,
cmdReady_out => cmd16Ready,
-- Response pipe
rspData_out => rsp16Data,
rspValid_out => rsp16Valid,
rspReady_in => rsp16Ready,
-- Memory controller interface
mcReady_in => ppReady,
mcCmd_out => ppCmd,
mcAddr_out => ppAddr,
mcData_out => ppDataWr,
mcData_in => ppDataRd,
mcRDV_in => ppRDV
);
-- Instantiate the memory arbiter unit
mem_arbiter: entity work.mem_arbiter
generic map (
NO_MONITOR => NO_MONITOR
)
port map (
clk_in => clk_in,
reset_in => reset_in,
-- Connetion to mem_pipe
ppReady_out => ppReady,
ppCmd_in => ppCmd,
ppAddr_in => ppAddr,
ppData_in => ppDataWr,
ppData_out => ppDataRd,
ppRDV_out => ppRDV,
-- Connection to mem_ctrl
mcAutoMode_out => mcAutoMode,
mcReady_in => mcReady,
mcCmd_out => mcCmd,
mcAddr_out => mcAddr,
mcData_out => mcDataWr,
mcData_in => mcDataRd,
mcRDV_in => mcRDV,
-- Connection to MegaDrive
mdDriveBus_out => mdDriveBus_out,
mdReset_in => mdReset,
mdDTACK_out => mdDTACK_out,
mdAddr_in => mdAddr_in,
mdData_io => mdData_io,
mdOE_in => mdOE_in,
mdAS_in => mdAS_in,
mdLDSW_in => mdLDSW_in,
mdUDSW_in => mdUDSW_in,
-- Trace pipe
traceReset_in => reg1(RESET),
traceEnable_in => reg1(TRACE),
traceData_out => tfiData,
traceValid_out => tfiValid,
-- MegaDrive register writes & reads
regAddr_out => regAddr,
regWrData_out => regWrData,
regWrValid_out => regWrValid,
regRdData_in => regRdData,
regRdStrobe_out => regRdStrobe,
regMapRam_in => mapRam
);
-- Memory controller (connects SDRAM to Memory Pipe Unit)
mem_ctrl: entity work.mem_ctrl
generic map (
INIT_COUNT => "1" & x"2C0", --\
REFRESH_DELAY => "0" & x"300", -- Much longer in real hardware!
REFRESH_LENGTH => "0" & x"002" --/
)
port map (
clk_in => clk_in,
reset_in => reset_in,
-- Client interface
mcAutoMode_in => mcAutoMode,
mcReady_out => mcReady,
mcCmd_in => mcCmd,
mcAddr_in => mcAddr,
mcData_in => mcDataWr,
mcData_out => mcDataRd,
mcRDV_out => mcRDV,
-- SDRAM interface
ramCmd_out => ramCmd_out,
ramBank_out => ramBank_out,
ramAddr_out => ramAddr_out,
ramData_io => ramData_io,
ramLDQM_out => ramLDQM_out,
ramUDQM_out => ramUDQM_out
);
-- Reset controller
reset_ctrl: entity work.reset_ctrl
port map (
clk_in => clk_in,
hardReset_in => reg1(RESET),
softReset_in => softReset,
mdReset_out => mdReset
);
reg1_next <=
h2fData_in(1 downto 0) when chanAddr_in = "0000001" and h2fValid_in = '1'
else reg1;
mdCfg_next <=
regWrData(3 downto 0) when regAddr = "010" and regWrValid = '1'
else mdCfg;
-- Connect channel 0 writes to the SDRAM command pipe and response pipe ready to ch0 read ready
cmdData <=
h2fData_in when chanAddr_in = "0000000" and h2fValid_in = '1'
else (others => 'X');
cmdValid <=
h2fValid_in when chanAddr_in = "0000000"
else '0';
rspReady <=
f2hReady_in when chanAddr_in = "0000000"
else '0';
-- Generate ready signal for throttling host writes
with chanAddr_in select h2fReady_out <=
cmdReady when "0000000",
'1' when "0000001",
'0' when others;
-- Drive SPI chip-select lines
spiCS_out(FLASHCS) <=
'0' when mdCfg(CHIPSEL+1 downto CHIPSEL) = FLASH
else '1';
spiCS_out(SDCARDCS) <=
'0' when mdCfg(CHIPSEL+1 downto CHIPSEL) = SDCARD
else '1';
spiWrValid <=
'1' when regAddr(2 downto 1) = "00" and regWrValid = '1'
else '0';
spiRdStrobe <=
'1' when regAddr(2 downto 1) = "00" and regRdStrobe = '1'
else '0';
mapRam_next <=
'1' when regAddr = "010" and regWrValid = '1' and regWrData = x"0000"
else mapRam;
softReset <=
'1' when regAddr = "011" and regWrValid = '1' and regWrData = x"DEAD"
else '0';
mdReset_out <= mdReset;
-- Dummy register reads
with regAddr select regRdData <=
spiRdData when "000",
spiRdData when "001",
x"DEAD" when "010",
x"F00D" when "011",
x"1234" when "100",
x"5678" when "101",
x"ABCD" when "110",
x"B00B" when others;
end architecture;
|
gpl-3.0
|
d4bf74b6c3edfc5ec92a6ef0e8924c76
| 0.602297 | 3.145282 | false | false | false | false |
eda-ricercatore/eda-ricercatore.github.io
|
vecchi-progetti/vlsi-design-projects/mult32_tb.vhd
| 1 | 2,194 |
----------------------------------------------------------------------------------
-- This is written by Zhiyang Ong to verify his
-- behavioral design of an unsigned 32-bit
-- multiplier.
-- Import IEEE VHDL libraries
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- use arith.all;
use work.arith.all;
-- Declare an instance of the testbench
ENTITY mult32_tb IS
END mult32_tb;
ARCHITECTURE behavior OF mult32_tb IS
-- Component Declaration
COMPONENT <mult32>
PORT( ip_a, ip_b : IN std_logic_vector(31 downto 0);
opt : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
-- Declaring input signals for the instance of
-- the multiplier
SIGNAL <ip1> : std_logic_vector(31 downto 0);
SIGNAL <ip2> : std_logic_vector(31 downto 0);
SIGNAL <res> : std_logic_vector(63 downto 0);
BEGIN
-- Component Instantiation
uut: <mult32> PORT MAP(
<ip_a> => <ip1>,
<ip_b> => <ip2>,
<opt> => <res>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
ip1 <= to_unsigned(200, 32);
ip2 <= to_unsigned(15, 32);
wait for 20 ns;
-- assert(res=3000) report "Error detected!"
-- severity warning;
ip1 <= to_unsigned(40, 32);
ip2 <= to_unsigned(1301, 32);
wait for 20 ns;
ip1 <= to_unsigned(0, 32);
ip2 <= to_unsigned(12, 32);
wait for 20 ns;
ip1 <= to_unsigned(17, 32);
ip2 <= to_unsigned(0, 32);
wait for 20 ns;
ip1 <= to_unsigned(0, 32);
ip2 <= to_unsigned(0, 32);
wait for 20 ns;
ip1 <= to_unsigned(397, 32);
ip2 <= to_unsigned(1, 32);
wait for 20 ns;
ip1 <= to_unsigned(1, 32);
ip2 <= to_unsigned(74, 32);
wait for 20 ns;
ip1 <= to_unsigned(752, 32);
ip2 <= to_unsigned(752, 32);
wait for 20 ns;
ip1 <= to_unsigned(67108864, 32);
ip2 <= to_unsigned(16, 32);
wait for 20 ns;
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
mit
|
449903d047a59fdaecebb1d7b6b07b3a
| 0.567457 | 3.034578 | false | false | false | false |
cretingame/Yarr-fw
|
rtl/common/synchronizer.vhd
| 2 | 1,061 |
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Deglitches async inputs
-- # Data: 09/2016
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Async input
async_in : in std_logic;
sync_out : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
signal deglitch_t1 : std_logic;
signal deglitch_t2 : std_logic;
begin
deglitch_proc : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sync_out <= '0';
deglitch_t1 <= '0';
deglitch_t2 <= '0';
elsif rising_edge(clk_i) then
deglitch_t1 <= async_in;
deglitch_t2 <= deglitch_t1;
sync_out <= deglitch_t2;
end if;
end process deglitch_proc;
end rtl;
|
gpl-3.0
|
3ba39d70d07ee912c5ceebefc19c0e5a
| 0.526861 | 3.560403 | false | false | false | false |
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/testbench.vhd
| 1 | 8,541 |
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Jakub Cabal <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/mig_ddr3_wrapper_virtex6
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TESTBENCH is
end TESTBENCH;
--------------------------------------------------------------------------------
-- THIS TESTBENCH REQUIRES DDR3 MODEL FROM XILINX MIG IP CORE!!!
--------------------------------------------------------------------------------
architecture FULL of TESTBENCH is
-- DO NOT CHANGE THESE VALUES!
constant nCS_PER_RANK : integer := 1; -- # of unique CS outputs per Rank for phy.
constant BANK_WIDTH : integer := 3; -- # of memory Bank Address bits.
constant CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory.
constant CKE_WIDTH : integer := 1; -- # of CKE outputs to memory.
constant CS_WIDTH : integer := 1; -- # of unique CS outputs to memory.
constant DM_WIDTH : integer := 8; -- # of Data Mask bits.
constant DQ_WIDTH : integer := 64; -- # of Data (DQ) bits.
constant DQS_WIDTH : integer := 8; -- # of DQS/DQS# bits.
constant ROW_WIDTH : integer := 14; -- # of memory Row Address bits.
constant MEMORY_WIDTH : integer := 16;
constant NUM_DDR3 : integer := DQ_WIDTH/MEMORY_WIDTH;
constant TPROP_DQS : time := 0 ps; -- Delay for DQS signal during Write Operation
constant TPROP_DQS_RD : time := 0 ps; -- Delay for DQS signal during Read Operation
constant TPROP_PCB_CTRL : time := 0 ps; -- Delay for Address and Ctrl signals
constant TPROP_PCB_DATA : time := 0 ps; -- Delay for data signal during Write operation
constant TPROP_PCB_DATA_RD : time := 0 ps; -- Delay for data signal during Read operation
component ddr3_model
port(
rst_n : in std_logic;
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
ba : in std_logic_vector(BANK_WIDTH-1 downto 0);
addr : in std_logic_vector(ROW_WIDTH-1 downto 0);
dq : inout std_logic_vector(MEMORY_WIDTH-1 downto 0);
dqs : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
dqs_n : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
tdqs_n : out std_logic_vector((MEMORY_WIDTH/16) downto 0);
odt : in std_logic
);
end component ddr3_model;
signal CLK_REF_P : std_logic := '0';
signal CLK_REF_N : std_logic := '1';
signal RST : std_logic := '0';
signal sys_rst_n : std_logic;
signal rx_uart : std_logic := '1';
signal tx_uart : std_logic;
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
signal phy_init_done : std_logic;
constant clk_period : time := 5 ns;
constant uart_period : time := 8681 ns;
constant data_value : std_logic_vector(7 downto 0) := X"13";
constant data_value2 : std_logic_vector(7 downto 0) := X"10";
begin
utt: entity work.TOP
generic map(
nCS_PER_RANK => nCS_PER_RANK,
BANK_WIDTH => BANK_WIDTH,
CK_WIDTH => CK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
CS_WIDTH => CS_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DM_WIDTH => DM_WIDTH,
DQS_WIDTH => DQS_WIDTH,
ROW_WIDTH => ROW_WIDTH,
SIM_BYPASS_INIT_CAL => "FAST"
)
port map (
ASYNC_RST => RST,
CLK_REF_P => CLK_REF_P,
CLK_REF_N => CLK_REF_N,
-- UART INTERFACE
UART_TX => tx_uart,
UART_RX => rx_uart,
-- DDR3 INTERFACE
DDR3_DQ => ddr3_dq,
DDR3_DM => ddr3_dm,
DDR3_ADDR => ddr3_addr,
DDR3_BA => ddr3_ba,
DDR3_RAS_N => ddr3_ras_n,
DDR3_CAS_N => ddr3_cas_n,
DDR3_WE_N => ddr3_we_n,
DDR3_RESET_N => ddr3_reset_n,
DDR3_CS_N => ddr3_cs_n,
DDR3_ODT => ddr3_odt,
DDR3_CKE => ddr3_cke,
DDR3_DQS_P => ddr3_dqs_p,
DDR3_DQS_N => ddr3_dqs_n,
DDR3_CK_P => ddr3_ck_p,
DDR3_CK_N => ddr3_ck_n,
PHY_INIT_DONE => phy_init_done
);
-- DDR3 MODEL FROM XILINX MIG IP CORE
gen_ddr3_mem : for i in 0 to NUM_DDR3-1 generate
ddr3_model_i : ddr3_model
port map(
rst_n => ddr3_reset_n,
ck => ddr3_ck_p((i*MEMORY_WIDTH)/72),
ck_n => ddr3_ck_n((i*MEMORY_WIDTH)/72),
cke => ddr3_cke((i*MEMORY_WIDTH)/72),
cs_n => ddr3_cs_n((i*MEMORY_WIDTH)/72),
ras_n => ddr3_ras_n,
cas_n => ddr3_cas_n,
we_n => ddr3_we_n,
dm_tdqs => ddr3_dm((2*(i+1)-1) downto (2*i)),
ba => ddr3_ba,
addr => ddr3_addr,
dq => ddr3_dq(16*(i+1)-1 downto 16*(i)),
dqs => ddr3_dqs_p((2*(i+1)-1) downto (2*i)),
dqs_n => ddr3_dqs_n((2*(i+1)-1) downto (2*i)),
tdqs_n => open,
odt => ddr3_odt((i*MEMORY_WIDTH)/72)
);
end generate;
clk_process : process
begin
CLK_REF_P <= '0';
CLK_REF_N <= '1';
wait for clk_period/2;
CLK_REF_P <= '1';
CLK_REF_N <= '0';
wait for clk_period/2;
end process;
test_rx_uart : process
begin
rx_uart <= '1';
RST <= '1';
wait for 50 ns;
RST <= '0';
wait for uart_period;
rx_uart <= '0'; -- start bit
wait for uart_period;
for i in 0 to 7 loop
rx_uart <= data_value(i); -- data bits
wait for uart_period;
end loop;
rx_uart <= '1'; -- parity bit
wait for uart_period;
rx_uart <= '1'; -- stop bit
wait for uart_period;
wait for 750 ns;
rx_uart <= '0'; -- start bit
wait for uart_period;
for i in 0 to 7 loop
rx_uart <= data_value2(i); -- data bits
wait for uart_period;
end loop;
rx_uart <= '1'; -- parity bit
wait for uart_period;
rx_uart <= '1'; -- stop bit
wait for uart_period;
wait;
end process;
end FULL;
|
mit
|
aa66283d1c56fdf610d31b880236e73e
| 0.542794 | 3.424619 | false | false | false | false |
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