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AEW2015/PYNQ_PR_Overlay
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Pynq-Z1/vivado/Partial_Designs/Source/pass_through_full.vhd
| 1 | 349,830 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name: Pass-through filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter passes the video signals from input to output.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Pass-through architecture
architecture Behavioral of Video_Box is
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
---- Number of Slave Registers 512
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg32 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg33 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg34 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg35 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg36 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg37 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg38 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg39 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg40 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg41 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg42 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg43 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg44 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg45 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg46 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg47 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg48 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg49 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg50 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg51 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg52 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg53 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg54 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg55 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg56 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg57 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg58 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg59 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg60 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg61 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg62 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg63 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg64 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg65 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg66 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg67 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg68 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg69 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg70 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg71 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg72 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg73 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg74 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg75 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg76 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg77 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg78 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg79 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg80 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg81 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg82 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg83 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg84 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg85 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg86 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg87 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg88 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg89 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg90 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg91 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg92 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg93 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg94 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg95 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg96 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg97 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg98 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg99 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg100 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg101 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg102 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg103 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg104 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg105 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg106 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg107 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg108 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg109 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg110 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg111 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg112 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg113 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg114 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg115 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg116 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg117 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg118 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg119 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg120 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg121 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg122 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg123 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg124 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg125 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg126 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg127 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg128 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg129 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg130 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg131 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg132 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg133 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg134 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg135 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg136 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg137 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg138 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg139 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg140 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg141 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg142 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg143 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg144 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg145 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg146 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg147 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg148 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg149 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg150 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg151 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg152 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg153 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg154 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg155 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg156 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg157 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg158 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg159 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg160 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg161 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg162 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg163 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg164 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg165 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg166 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg167 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg168 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg169 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg170 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg171 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg172 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg173 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg174 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg175 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg176 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg177 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg178 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg179 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg180 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg181 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg182 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg183 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg184 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg185 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg186 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg187 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg188 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg189 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg190 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg191 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg192 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg193 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg194 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg195 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg196 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg197 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg198 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg199 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg200 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg201 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg202 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg203 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg204 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg205 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg206 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg207 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg208 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg209 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg210 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg211 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg212 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg213 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg214 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg215 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg216 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg217 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg218 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg219 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg220 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg221 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg222 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg223 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg224 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg225 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg226 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg227 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg228 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg229 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg230 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg231 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg232 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg233 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg234 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg235 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg236 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg237 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg238 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg239 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg240 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg241 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg242 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg243 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg244 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg245 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg246 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg247 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg248 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg249 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg250 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg251 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg252 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg253 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg254 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg255 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg256 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg257 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg258 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg259 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg260 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg261 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg262 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg263 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg264 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg265 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg266 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg267 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg268 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg269 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg270 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg271 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg272 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg273 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg274 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg275 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg276 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg277 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg278 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg279 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg280 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg281 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg282 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg283 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg284 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg285 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg286 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg287 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg288 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg289 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg290 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg291 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg292 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg293 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg294 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg295 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg296 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg297 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg298 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg299 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg300 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg301 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg302 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg303 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg304 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg305 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg306 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg307 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg308 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg309 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg310 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg311 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg312 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg313 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg314 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg315 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg316 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg317 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg318 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg319 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg320 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg321 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg322 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg323 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg324 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg325 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg326 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg327 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg328 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg329 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg330 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg331 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg332 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg333 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg334 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg335 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg336 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg337 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg338 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg339 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg340 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg341 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg342 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg343 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg344 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg345 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg346 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg347 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg348 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg349 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg350 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg351 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg352 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg353 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg354 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg355 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg356 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg357 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg358 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg359 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg360 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg361 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg362 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg363 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg364 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg365 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg366 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg367 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg368 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg369 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg370 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg371 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg372 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg373 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg374 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg375 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg376 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg377 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg378 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg379 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg380 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg381 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg382 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg383 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg384 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg385 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg386 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg387 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg388 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg389 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg390 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg391 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg392 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg393 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg394 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg395 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg396 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg397 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg398 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg399 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg400 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg401 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg402 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg403 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg404 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg405 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg406 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg407 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg408 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg409 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg410 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg411 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg412 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg413 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg414 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg415 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg416 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg417 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg418 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg419 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg420 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg421 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg422 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg423 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg424 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg425 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg426 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg427 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg428 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg429 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg430 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg431 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg432 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg433 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg434 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg435 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg436 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg437 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg438 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg439 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg440 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg441 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg442 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg443 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg444 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg445 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg446 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg447 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg448 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg449 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg450 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg451 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg452 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg453 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg454 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg455 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg456 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg457 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg458 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg459 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg460 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg461 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg462 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg463 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg464 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg465 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg466 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg467 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg468 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg469 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg470 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg471 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg472 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg473 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg474 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg475 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg476 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg477 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg478 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg479 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg480 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg481 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg482 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg483 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg484 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg485 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg486 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg487 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg488 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg489 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg490 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg491 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg492 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg493 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg494 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg495 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg496 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg497 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg498 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg499 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg500 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg501 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg502 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg503 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg504 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg505 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg506 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg507 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg508 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg509 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg510 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg511 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--the user can edit the rgb values here
USER_LOGIC <= RGB_IN_reg;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
slv_reg32 <= (others => '0');
slv_reg33 <= (others => '0');
slv_reg34 <= (others => '0');
slv_reg35 <= (others => '0');
slv_reg36 <= (others => '0');
slv_reg37 <= (others => '0');
slv_reg38 <= (others => '0');
slv_reg39 <= (others => '0');
slv_reg40 <= (others => '0');
slv_reg41 <= (others => '0');
slv_reg42 <= (others => '0');
slv_reg43 <= (others => '0');
slv_reg44 <= (others => '0');
slv_reg45 <= (others => '0');
slv_reg46 <= (others => '0');
slv_reg47 <= (others => '0');
slv_reg48 <= (others => '0');
slv_reg49 <= (others => '0');
slv_reg50 <= (others => '0');
slv_reg51 <= (others => '0');
slv_reg52 <= (others => '0');
slv_reg53 <= (others => '0');
slv_reg54 <= (others => '0');
slv_reg55 <= (others => '0');
slv_reg56 <= (others => '0');
slv_reg57 <= (others => '0');
slv_reg58 <= (others => '0');
slv_reg59 <= (others => '0');
slv_reg60 <= (others => '0');
slv_reg61 <= (others => '0');
slv_reg62 <= (others => '0');
slv_reg63 <= (others => '0');
slv_reg64 <= (others => '0');
slv_reg65 <= (others => '0');
slv_reg66 <= (others => '0');
slv_reg67 <= (others => '0');
slv_reg68 <= (others => '0');
slv_reg69 <= (others => '0');
slv_reg70 <= (others => '0');
slv_reg71 <= (others => '0');
slv_reg72 <= (others => '0');
slv_reg73 <= (others => '0');
slv_reg74 <= (others => '0');
slv_reg75 <= (others => '0');
slv_reg76 <= (others => '0');
slv_reg77 <= (others => '0');
slv_reg78 <= (others => '0');
slv_reg79 <= (others => '0');
slv_reg80 <= (others => '0');
slv_reg81 <= (others => '0');
slv_reg82 <= (others => '0');
slv_reg83 <= (others => '0');
slv_reg84 <= (others => '0');
slv_reg85 <= (others => '0');
slv_reg86 <= (others => '0');
slv_reg87 <= (others => '0');
slv_reg88 <= (others => '0');
slv_reg89 <= (others => '0');
slv_reg90 <= (others => '0');
slv_reg91 <= (others => '0');
slv_reg92 <= (others => '0');
slv_reg93 <= (others => '0');
slv_reg94 <= (others => '0');
slv_reg95 <= (others => '0');
slv_reg96 <= (others => '0');
slv_reg97 <= (others => '0');
slv_reg98 <= (others => '0');
slv_reg99 <= (others => '0');
slv_reg100 <= (others => '0');
slv_reg101 <= (others => '0');
slv_reg102 <= (others => '0');
slv_reg103 <= (others => '0');
slv_reg104 <= (others => '0');
slv_reg105 <= (others => '0');
slv_reg106 <= (others => '0');
slv_reg107 <= (others => '0');
slv_reg108 <= (others => '0');
slv_reg109 <= (others => '0');
slv_reg110 <= (others => '0');
slv_reg111 <= (others => '0');
slv_reg112 <= (others => '0');
slv_reg113 <= (others => '0');
slv_reg114 <= (others => '0');
slv_reg115 <= (others => '0');
slv_reg116 <= (others => '0');
slv_reg117 <= (others => '0');
slv_reg118 <= (others => '0');
slv_reg119 <= (others => '0');
slv_reg120 <= (others => '0');
slv_reg121 <= (others => '0');
slv_reg122 <= (others => '0');
slv_reg123 <= (others => '0');
slv_reg124 <= (others => '0');
slv_reg125 <= (others => '0');
slv_reg126 <= (others => '0');
slv_reg127 <= (others => '0');
slv_reg128 <= (others => '0');
slv_reg129 <= (others => '0');
slv_reg130 <= (others => '0');
slv_reg131 <= (others => '0');
slv_reg132 <= (others => '0');
slv_reg133 <= (others => '0');
slv_reg134 <= (others => '0');
slv_reg135 <= (others => '0');
slv_reg136 <= (others => '0');
slv_reg137 <= (others => '0');
slv_reg138 <= (others => '0');
slv_reg139 <= (others => '0');
slv_reg140 <= (others => '0');
slv_reg141 <= (others => '0');
slv_reg142 <= (others => '0');
slv_reg143 <= (others => '0');
slv_reg144 <= (others => '0');
slv_reg145 <= (others => '0');
slv_reg146 <= (others => '0');
slv_reg147 <= (others => '0');
slv_reg148 <= (others => '0');
slv_reg149 <= (others => '0');
slv_reg150 <= (others => '0');
slv_reg151 <= (others => '0');
slv_reg152 <= (others => '0');
slv_reg153 <= (others => '0');
slv_reg154 <= (others => '0');
slv_reg155 <= (others => '0');
slv_reg156 <= (others => '0');
slv_reg157 <= (others => '0');
slv_reg158 <= (others => '0');
slv_reg159 <= (others => '0');
slv_reg160 <= (others => '0');
slv_reg161 <= (others => '0');
slv_reg162 <= (others => '0');
slv_reg163 <= (others => '0');
slv_reg164 <= (others => '0');
slv_reg165 <= (others => '0');
slv_reg166 <= (others => '0');
slv_reg167 <= (others => '0');
slv_reg168 <= (others => '0');
slv_reg169 <= (others => '0');
slv_reg170 <= (others => '0');
slv_reg171 <= (others => '0');
slv_reg172 <= (others => '0');
slv_reg173 <= (others => '0');
slv_reg174 <= (others => '0');
slv_reg175 <= (others => '0');
slv_reg176 <= (others => '0');
slv_reg177 <= (others => '0');
slv_reg178 <= (others => '0');
slv_reg179 <= (others => '0');
slv_reg180 <= (others => '0');
slv_reg181 <= (others => '0');
slv_reg182 <= (others => '0');
slv_reg183 <= (others => '0');
slv_reg184 <= (others => '0');
slv_reg185 <= (others => '0');
slv_reg186 <= (others => '0');
slv_reg187 <= (others => '0');
slv_reg188 <= (others => '0');
slv_reg189 <= (others => '0');
slv_reg190 <= (others => '0');
slv_reg191 <= (others => '0');
slv_reg192 <= (others => '0');
slv_reg193 <= (others => '0');
slv_reg194 <= (others => '0');
slv_reg195 <= (others => '0');
slv_reg196 <= (others => '0');
slv_reg197 <= (others => '0');
slv_reg198 <= (others => '0');
slv_reg199 <= (others => '0');
slv_reg200 <= (others => '0');
slv_reg201 <= (others => '0');
slv_reg202 <= (others => '0');
slv_reg203 <= (others => '0');
slv_reg204 <= (others => '0');
slv_reg205 <= (others => '0');
slv_reg206 <= (others => '0');
slv_reg207 <= (others => '0');
slv_reg208 <= (others => '0');
slv_reg209 <= (others => '0');
slv_reg210 <= (others => '0');
slv_reg211 <= (others => '0');
slv_reg212 <= (others => '0');
slv_reg213 <= (others => '0');
slv_reg214 <= (others => '0');
slv_reg215 <= (others => '0');
slv_reg216 <= (others => '0');
slv_reg217 <= (others => '0');
slv_reg218 <= (others => '0');
slv_reg219 <= (others => '0');
slv_reg220 <= (others => '0');
slv_reg221 <= (others => '0');
slv_reg222 <= (others => '0');
slv_reg223 <= (others => '0');
slv_reg224 <= (others => '0');
slv_reg225 <= (others => '0');
slv_reg226 <= (others => '0');
slv_reg227 <= (others => '0');
slv_reg228 <= (others => '0');
slv_reg229 <= (others => '0');
slv_reg230 <= (others => '0');
slv_reg231 <= (others => '0');
slv_reg232 <= (others => '0');
slv_reg233 <= (others => '0');
slv_reg234 <= (others => '0');
slv_reg235 <= (others => '0');
slv_reg236 <= (others => '0');
slv_reg237 <= (others => '0');
slv_reg238 <= (others => '0');
slv_reg239 <= (others => '0');
slv_reg240 <= (others => '0');
slv_reg241 <= (others => '0');
slv_reg242 <= (others => '0');
slv_reg243 <= (others => '0');
slv_reg244 <= (others => '0');
slv_reg245 <= (others => '0');
slv_reg246 <= (others => '0');
slv_reg247 <= (others => '0');
slv_reg248 <= (others => '0');
slv_reg249 <= (others => '0');
slv_reg250 <= (others => '0');
slv_reg251 <= (others => '0');
slv_reg252 <= (others => '0');
slv_reg253 <= (others => '0');
slv_reg254 <= (others => '0');
slv_reg255 <= (others => '0');
slv_reg256 <= (others => '0');
slv_reg257 <= (others => '0');
slv_reg258 <= (others => '0');
slv_reg259 <= (others => '0');
slv_reg260 <= (others => '0');
slv_reg261 <= (others => '0');
slv_reg262 <= (others => '0');
slv_reg263 <= (others => '0');
slv_reg264 <= (others => '0');
slv_reg265 <= (others => '0');
slv_reg266 <= (others => '0');
slv_reg267 <= (others => '0');
slv_reg268 <= (others => '0');
slv_reg269 <= (others => '0');
slv_reg270 <= (others => '0');
slv_reg271 <= (others => '0');
slv_reg272 <= (others => '0');
slv_reg273 <= (others => '0');
slv_reg274 <= (others => '0');
slv_reg275 <= (others => '0');
slv_reg276 <= (others => '0');
slv_reg277 <= (others => '0');
slv_reg278 <= (others => '0');
slv_reg279 <= (others => '0');
slv_reg280 <= (others => '0');
slv_reg281 <= (others => '0');
slv_reg282 <= (others => '0');
slv_reg283 <= (others => '0');
slv_reg284 <= (others => '0');
slv_reg285 <= (others => '0');
slv_reg286 <= (others => '0');
slv_reg287 <= (others => '0');
slv_reg288 <= (others => '0');
slv_reg289 <= (others => '0');
slv_reg290 <= (others => '0');
slv_reg291 <= (others => '0');
slv_reg292 <= (others => '0');
slv_reg293 <= (others => '0');
slv_reg294 <= (others => '0');
slv_reg295 <= (others => '0');
slv_reg296 <= (others => '0');
slv_reg297 <= (others => '0');
slv_reg298 <= (others => '0');
slv_reg299 <= (others => '0');
slv_reg300 <= (others => '0');
slv_reg301 <= (others => '0');
slv_reg302 <= (others => '0');
slv_reg303 <= (others => '0');
slv_reg304 <= (others => '0');
slv_reg305 <= (others => '0');
slv_reg306 <= (others => '0');
slv_reg307 <= (others => '0');
slv_reg308 <= (others => '0');
slv_reg309 <= (others => '0');
slv_reg310 <= (others => '0');
slv_reg311 <= (others => '0');
slv_reg312 <= (others => '0');
slv_reg313 <= (others => '0');
slv_reg314 <= (others => '0');
slv_reg315 <= (others => '0');
slv_reg316 <= (others => '0');
slv_reg317 <= (others => '0');
slv_reg318 <= (others => '0');
slv_reg319 <= (others => '0');
slv_reg320 <= (others => '0');
slv_reg321 <= (others => '0');
slv_reg322 <= (others => '0');
slv_reg323 <= (others => '0');
slv_reg324 <= (others => '0');
slv_reg325 <= (others => '0');
slv_reg326 <= (others => '0');
slv_reg327 <= (others => '0');
slv_reg328 <= (others => '0');
slv_reg329 <= (others => '0');
slv_reg330 <= (others => '0');
slv_reg331 <= (others => '0');
slv_reg332 <= (others => '0');
slv_reg333 <= (others => '0');
slv_reg334 <= (others => '0');
slv_reg335 <= (others => '0');
slv_reg336 <= (others => '0');
slv_reg337 <= (others => '0');
slv_reg338 <= (others => '0');
slv_reg339 <= (others => '0');
slv_reg340 <= (others => '0');
slv_reg341 <= (others => '0');
slv_reg342 <= (others => '0');
slv_reg343 <= (others => '0');
slv_reg344 <= (others => '0');
slv_reg345 <= (others => '0');
slv_reg346 <= (others => '0');
slv_reg347 <= (others => '0');
slv_reg348 <= (others => '0');
slv_reg349 <= (others => '0');
slv_reg350 <= (others => '0');
slv_reg351 <= (others => '0');
slv_reg352 <= (others => '0');
slv_reg353 <= (others => '0');
slv_reg354 <= (others => '0');
slv_reg355 <= (others => '0');
slv_reg356 <= (others => '0');
slv_reg357 <= (others => '0');
slv_reg358 <= (others => '0');
slv_reg359 <= (others => '0');
slv_reg360 <= (others => '0');
slv_reg361 <= (others => '0');
slv_reg362 <= (others => '0');
slv_reg363 <= (others => '0');
slv_reg364 <= (others => '0');
slv_reg365 <= (others => '0');
slv_reg366 <= (others => '0');
slv_reg367 <= (others => '0');
slv_reg368 <= (others => '0');
slv_reg369 <= (others => '0');
slv_reg370 <= (others => '0');
slv_reg371 <= (others => '0');
slv_reg372 <= (others => '0');
slv_reg373 <= (others => '0');
slv_reg374 <= (others => '0');
slv_reg375 <= (others => '0');
slv_reg376 <= (others => '0');
slv_reg377 <= (others => '0');
slv_reg378 <= (others => '0');
slv_reg379 <= (others => '0');
slv_reg380 <= (others => '0');
slv_reg381 <= (others => '0');
slv_reg382 <= (others => '0');
slv_reg383 <= (others => '0');
slv_reg384 <= (others => '0');
slv_reg385 <= (others => '0');
slv_reg386 <= (others => '0');
slv_reg387 <= (others => '0');
slv_reg388 <= (others => '0');
slv_reg389 <= (others => '0');
slv_reg390 <= (others => '0');
slv_reg391 <= (others => '0');
slv_reg392 <= (others => '0');
slv_reg393 <= (others => '0');
slv_reg394 <= (others => '0');
slv_reg395 <= (others => '0');
slv_reg396 <= (others => '0');
slv_reg397 <= (others => '0');
slv_reg398 <= (others => '0');
slv_reg399 <= (others => '0');
slv_reg400 <= (others => '0');
slv_reg401 <= (others => '0');
slv_reg402 <= (others => '0');
slv_reg403 <= (others => '0');
slv_reg404 <= (others => '0');
slv_reg405 <= (others => '0');
slv_reg406 <= (others => '0');
slv_reg407 <= (others => '0');
slv_reg408 <= (others => '0');
slv_reg409 <= (others => '0');
slv_reg410 <= (others => '0');
slv_reg411 <= (others => '0');
slv_reg412 <= (others => '0');
slv_reg413 <= (others => '0');
slv_reg414 <= (others => '0');
slv_reg415 <= (others => '0');
slv_reg416 <= (others => '0');
slv_reg417 <= (others => '0');
slv_reg418 <= (others => '0');
slv_reg419 <= (others => '0');
slv_reg420 <= (others => '0');
slv_reg421 <= (others => '0');
slv_reg422 <= (others => '0');
slv_reg423 <= (others => '0');
slv_reg424 <= (others => '0');
slv_reg425 <= (others => '0');
slv_reg426 <= (others => '0');
slv_reg427 <= (others => '0');
slv_reg428 <= (others => '0');
slv_reg429 <= (others => '0');
slv_reg430 <= (others => '0');
slv_reg431 <= (others => '0');
slv_reg432 <= (others => '0');
slv_reg433 <= (others => '0');
slv_reg434 <= (others => '0');
slv_reg435 <= (others => '0');
slv_reg436 <= (others => '0');
slv_reg437 <= (others => '0');
slv_reg438 <= (others => '0');
slv_reg439 <= (others => '0');
slv_reg440 <= (others => '0');
slv_reg441 <= (others => '0');
slv_reg442 <= (others => '0');
slv_reg443 <= (others => '0');
slv_reg444 <= (others => '0');
slv_reg445 <= (others => '0');
slv_reg446 <= (others => '0');
slv_reg447 <= (others => '0');
slv_reg448 <= (others => '0');
slv_reg449 <= (others => '0');
slv_reg450 <= (others => '0');
slv_reg451 <= (others => '0');
slv_reg452 <= (others => '0');
slv_reg453 <= (others => '0');
slv_reg454 <= (others => '0');
slv_reg455 <= (others => '0');
slv_reg456 <= (others => '0');
slv_reg457 <= (others => '0');
slv_reg458 <= (others => '0');
slv_reg459 <= (others => '0');
slv_reg460 <= (others => '0');
slv_reg461 <= (others => '0');
slv_reg462 <= (others => '0');
slv_reg463 <= (others => '0');
slv_reg464 <= (others => '0');
slv_reg465 <= (others => '0');
slv_reg466 <= (others => '0');
slv_reg467 <= (others => '0');
slv_reg468 <= (others => '0');
slv_reg469 <= (others => '0');
slv_reg470 <= (others => '0');
slv_reg471 <= (others => '0');
slv_reg472 <= (others => '0');
slv_reg473 <= (others => '0');
slv_reg474 <= (others => '0');
slv_reg475 <= (others => '0');
slv_reg476 <= (others => '0');
slv_reg477 <= (others => '0');
slv_reg478 <= (others => '0');
slv_reg479 <= (others => '0');
slv_reg480 <= (others => '0');
slv_reg481 <= (others => '0');
slv_reg482 <= (others => '0');
slv_reg483 <= (others => '0');
slv_reg484 <= (others => '0');
slv_reg485 <= (others => '0');
slv_reg486 <= (others => '0');
slv_reg487 <= (others => '0');
slv_reg488 <= (others => '0');
slv_reg489 <= (others => '0');
slv_reg490 <= (others => '0');
slv_reg491 <= (others => '0');
slv_reg492 <= (others => '0');
slv_reg493 <= (others => '0');
slv_reg494 <= (others => '0');
slv_reg495 <= (others => '0');
slv_reg496 <= (others => '0');
slv_reg497 <= (others => '0');
slv_reg498 <= (others => '0');
slv_reg499 <= (others => '0');
slv_reg500 <= (others => '0');
slv_reg501 <= (others => '0');
slv_reg502 <= (others => '0');
slv_reg503 <= (others => '0');
slv_reg504 <= (others => '0');
slv_reg505 <= (others => '0');
slv_reg506 <= (others => '0');
slv_reg507 <= (others => '0');
slv_reg508 <= (others => '0');
slv_reg509 <= (others => '0');
slv_reg510 <= (others => '0');
slv_reg511 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 24
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 25
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 26
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 27
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 28
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 29
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 30
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 31
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 32
slv_reg32(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 33
slv_reg33(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 34
slv_reg34(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 35
slv_reg35(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 36
slv_reg36(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 37
slv_reg37(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 38
slv_reg38(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 39
slv_reg39(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 40
slv_reg40(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 41
slv_reg41(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 42
slv_reg42(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 43
slv_reg43(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 44
slv_reg44(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 45
slv_reg45(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 46
slv_reg46(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 47
slv_reg47(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 48
slv_reg48(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 49
slv_reg49(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 50
slv_reg50(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 51
slv_reg51(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 52
slv_reg52(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 53
slv_reg53(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 54
slv_reg54(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 55
slv_reg55(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 56
slv_reg56(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 57
slv_reg57(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 58
slv_reg58(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 59
slv_reg59(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 60
slv_reg60(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 61
slv_reg61(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 62
slv_reg62(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 63
slv_reg63(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 64
slv_reg64(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 65
slv_reg65(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 66
slv_reg66(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 67
slv_reg67(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 68
slv_reg68(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 69
slv_reg69(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 70
slv_reg70(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 71
slv_reg71(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 72
slv_reg72(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 73
slv_reg73(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 74
slv_reg74(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 75
slv_reg75(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 76
slv_reg76(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 77
slv_reg77(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 78
slv_reg78(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 79
slv_reg79(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 80
slv_reg80(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 81
slv_reg81(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 82
slv_reg82(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 83
slv_reg83(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 84
slv_reg84(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 85
slv_reg85(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 86
slv_reg86(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 87
slv_reg87(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 88
slv_reg88(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 89
slv_reg89(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 90
slv_reg90(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 91
slv_reg91(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 92
slv_reg92(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 93
slv_reg93(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 94
slv_reg94(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 95
slv_reg95(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 96
slv_reg96(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 97
slv_reg97(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 98
slv_reg98(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 99
slv_reg99(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 100
slv_reg100(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 101
slv_reg101(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 102
slv_reg102(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 103
slv_reg103(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 104
slv_reg104(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 105
slv_reg105(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 106
slv_reg106(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 107
slv_reg107(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 108
slv_reg108(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 109
slv_reg109(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 110
slv_reg110(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 111
slv_reg111(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 112
slv_reg112(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 113
slv_reg113(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 114
slv_reg114(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 115
slv_reg115(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 116
slv_reg116(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 117
slv_reg117(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 118
slv_reg118(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 119
slv_reg119(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 120
slv_reg120(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 121
slv_reg121(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 122
slv_reg122(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 123
slv_reg123(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 124
slv_reg124(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 125
slv_reg125(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 126
slv_reg126(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 127
slv_reg127(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 128
slv_reg128(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 129
slv_reg129(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 130
slv_reg130(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 131
slv_reg131(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 132
slv_reg132(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 133
slv_reg133(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 134
slv_reg134(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 135
slv_reg135(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 136
slv_reg136(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 137
slv_reg137(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 138
slv_reg138(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 139
slv_reg139(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 140
slv_reg140(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 141
slv_reg141(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 142
slv_reg142(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 143
slv_reg143(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 144
slv_reg144(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 145
slv_reg145(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 146
slv_reg146(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 147
slv_reg147(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 148
slv_reg148(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 149
slv_reg149(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 150
slv_reg150(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 151
slv_reg151(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 152
slv_reg152(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 153
slv_reg153(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 154
slv_reg154(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 155
slv_reg155(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 156
slv_reg156(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 157
slv_reg157(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 158
slv_reg158(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 159
slv_reg159(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 160
slv_reg160(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 161
slv_reg161(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 162
slv_reg162(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 163
slv_reg163(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 164
slv_reg164(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 165
slv_reg165(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 166
slv_reg166(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 167
slv_reg167(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 168
slv_reg168(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 169
slv_reg169(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 170
slv_reg170(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 171
slv_reg171(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 172
slv_reg172(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 173
slv_reg173(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 174
slv_reg174(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 175
slv_reg175(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 176
slv_reg176(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 177
slv_reg177(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 178
slv_reg178(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 179
slv_reg179(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 180
slv_reg180(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 181
slv_reg181(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 182
slv_reg182(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 183
slv_reg183(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 184
slv_reg184(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 185
slv_reg185(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 186
slv_reg186(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 187
slv_reg187(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 188
slv_reg188(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 189
slv_reg189(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 190
slv_reg190(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 191
slv_reg191(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 192
slv_reg192(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 193
slv_reg193(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 194
slv_reg194(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 195
slv_reg195(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 196
slv_reg196(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 197
slv_reg197(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 198
slv_reg198(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 199
slv_reg199(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 200
slv_reg200(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 201
slv_reg201(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 202
slv_reg202(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 203
slv_reg203(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 204
slv_reg204(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 205
slv_reg205(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 206
slv_reg206(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 207
slv_reg207(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 208
slv_reg208(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 209
slv_reg209(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 210
slv_reg210(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 211
slv_reg211(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 212
slv_reg212(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 213
slv_reg213(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 214
slv_reg214(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 215
slv_reg215(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 216
slv_reg216(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 217
slv_reg217(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 218
slv_reg218(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 219
slv_reg219(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 220
slv_reg220(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 221
slv_reg221(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 222
slv_reg222(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 223
slv_reg223(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 224
slv_reg224(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 225
slv_reg225(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 226
slv_reg226(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 227
slv_reg227(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 228
slv_reg228(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 229
slv_reg229(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 230
slv_reg230(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 231
slv_reg231(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 232
slv_reg232(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 233
slv_reg233(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 234
slv_reg234(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 235
slv_reg235(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 236
slv_reg236(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 237
slv_reg237(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 238
slv_reg238(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 239
slv_reg239(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 240
slv_reg240(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 241
slv_reg241(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 242
slv_reg242(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 243
slv_reg243(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 244
slv_reg244(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 245
slv_reg245(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 246
slv_reg246(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 247
slv_reg247(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 248
slv_reg248(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 249
slv_reg249(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 250
slv_reg250(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 251
slv_reg251(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 252
slv_reg252(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 253
slv_reg253(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 254
slv_reg254(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 255
slv_reg255(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 256
slv_reg256(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 257
slv_reg257(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 258
slv_reg258(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 259
slv_reg259(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 260
slv_reg260(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 261
slv_reg261(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 262
slv_reg262(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 263
slv_reg263(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 264
slv_reg264(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 265
slv_reg265(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 266
slv_reg266(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 267
slv_reg267(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 268
slv_reg268(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 269
slv_reg269(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 270
slv_reg270(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 271
slv_reg271(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 272
slv_reg272(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 273
slv_reg273(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 274
slv_reg274(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 275
slv_reg275(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 276
slv_reg276(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 277
slv_reg277(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 278
slv_reg278(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 279
slv_reg279(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 280
slv_reg280(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 281
slv_reg281(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 282
slv_reg282(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 283
slv_reg283(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 284
slv_reg284(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 285
slv_reg285(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 286
slv_reg286(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 287
slv_reg287(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 288
slv_reg288(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 289
slv_reg289(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 290
slv_reg290(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 291
slv_reg291(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 292
slv_reg292(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 293
slv_reg293(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 294
slv_reg294(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 295
slv_reg295(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 296
slv_reg296(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 297
slv_reg297(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 298
slv_reg298(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 299
slv_reg299(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 300
slv_reg300(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 301
slv_reg301(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 302
slv_reg302(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 303
slv_reg303(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 304
slv_reg304(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 305
slv_reg305(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 306
slv_reg306(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 307
slv_reg307(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 308
slv_reg308(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 309
slv_reg309(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 310
slv_reg310(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 311
slv_reg311(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 312
slv_reg312(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 313
slv_reg313(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 314
slv_reg314(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 315
slv_reg315(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 316
slv_reg316(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 317
slv_reg317(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 318
slv_reg318(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 319
slv_reg319(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 320
slv_reg320(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 321
slv_reg321(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 322
slv_reg322(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 323
slv_reg323(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 324
slv_reg324(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 325
slv_reg325(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 326
slv_reg326(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 327
slv_reg327(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 328
slv_reg328(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 329
slv_reg329(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 330
slv_reg330(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 331
slv_reg331(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 332
slv_reg332(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 333
slv_reg333(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 334
slv_reg334(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 335
slv_reg335(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 336
slv_reg336(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 337
slv_reg337(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 338
slv_reg338(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 339
slv_reg339(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 340
slv_reg340(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 341
slv_reg341(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 342
slv_reg342(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 343
slv_reg343(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 344
slv_reg344(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 345
slv_reg345(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 346
slv_reg346(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 347
slv_reg347(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 348
slv_reg348(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 349
slv_reg349(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 350
slv_reg350(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 351
slv_reg351(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 352
slv_reg352(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 353
slv_reg353(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 354
slv_reg354(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 355
slv_reg355(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 356
slv_reg356(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 357
slv_reg357(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 358
slv_reg358(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 359
slv_reg359(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 360
slv_reg360(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 361
slv_reg361(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 362
slv_reg362(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 363
slv_reg363(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 364
slv_reg364(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 365
slv_reg365(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 366
slv_reg366(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 367
slv_reg367(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 368
slv_reg368(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 369
slv_reg369(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 370
slv_reg370(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 371
slv_reg371(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 372
slv_reg372(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 373
slv_reg373(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 374
slv_reg374(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 375
slv_reg375(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 376
slv_reg376(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 377
slv_reg377(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 378
slv_reg378(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 379
slv_reg379(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 380
slv_reg380(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 381
slv_reg381(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 382
slv_reg382(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 383
slv_reg383(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 384
slv_reg384(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 385
slv_reg385(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 386
slv_reg386(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 387
slv_reg387(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 388
slv_reg388(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 389
slv_reg389(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 390
slv_reg390(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 391
slv_reg391(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 392
slv_reg392(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 393
slv_reg393(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 394
slv_reg394(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 395
slv_reg395(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 396
slv_reg396(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 397
slv_reg397(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 398
slv_reg398(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 399
slv_reg399(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 400
slv_reg400(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 401
slv_reg401(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 402
slv_reg402(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 403
slv_reg403(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 404
slv_reg404(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 405
slv_reg405(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 406
slv_reg406(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 407
slv_reg407(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 408
slv_reg408(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 409
slv_reg409(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 410
slv_reg410(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 411
slv_reg411(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 412
slv_reg412(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 413
slv_reg413(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 414
slv_reg414(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 415
slv_reg415(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 416
slv_reg416(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 417
slv_reg417(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 418
slv_reg418(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 419
slv_reg419(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 420
slv_reg420(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 421
slv_reg421(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 422
slv_reg422(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 423
slv_reg423(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 424
slv_reg424(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 425
slv_reg425(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 426
slv_reg426(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 427
slv_reg427(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 428
slv_reg428(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 429
slv_reg429(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 430
slv_reg430(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 431
slv_reg431(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 432
slv_reg432(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 433
slv_reg433(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 434
slv_reg434(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 435
slv_reg435(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 436
slv_reg436(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 437
slv_reg437(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 438
slv_reg438(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 439
slv_reg439(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 440
slv_reg440(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 441
slv_reg441(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 442
slv_reg442(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 443
slv_reg443(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 444
slv_reg444(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 445
slv_reg445(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 446
slv_reg446(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 447
slv_reg447(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 448
slv_reg448(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 449
slv_reg449(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 450
slv_reg450(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 451
slv_reg451(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 452
slv_reg452(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 453
slv_reg453(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 454
slv_reg454(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 455
slv_reg455(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 456
slv_reg456(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 457
slv_reg457(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 458
slv_reg458(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 459
slv_reg459(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 460
slv_reg460(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 461
slv_reg461(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 462
slv_reg462(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 463
slv_reg463(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 464
slv_reg464(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 465
slv_reg465(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 466
slv_reg466(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 467
slv_reg467(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 468
slv_reg468(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 469
slv_reg469(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 470
slv_reg470(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 471
slv_reg471(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 472
slv_reg472(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 473
slv_reg473(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 474
slv_reg474(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 475
slv_reg475(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 476
slv_reg476(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 477
slv_reg477(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 478
slv_reg478(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 479
slv_reg479(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 480
slv_reg480(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 481
slv_reg481(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 482
slv_reg482(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 483
slv_reg483(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 484
slv_reg484(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 485
slv_reg485(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 486
slv_reg486(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 487
slv_reg487(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 488
slv_reg488(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 489
slv_reg489(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 490
slv_reg490(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 491
slv_reg491(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 492
slv_reg492(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 493
slv_reg493(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 494
slv_reg494(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 495
slv_reg495(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 496
slv_reg496(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 497
slv_reg497(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 498
slv_reg498(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 499
slv_reg499(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 500
slv_reg500(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 501
slv_reg501(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 502
slv_reg502(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 503
slv_reg503(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 504
slv_reg504(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 505
slv_reg505(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 506
slv_reg506(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 507
slv_reg507(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 508
slv_reg508(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 509
slv_reg509(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 510
slv_reg510(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 511
slv_reg511(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
slv_reg32 <= slv_reg32;
slv_reg33 <= slv_reg33;
slv_reg34 <= slv_reg34;
slv_reg35 <= slv_reg35;
slv_reg36 <= slv_reg36;
slv_reg37 <= slv_reg37;
slv_reg38 <= slv_reg38;
slv_reg39 <= slv_reg39;
slv_reg40 <= slv_reg40;
slv_reg41 <= slv_reg41;
slv_reg42 <= slv_reg42;
slv_reg43 <= slv_reg43;
slv_reg44 <= slv_reg44;
slv_reg45 <= slv_reg45;
slv_reg46 <= slv_reg46;
slv_reg47 <= slv_reg47;
slv_reg48 <= slv_reg48;
slv_reg49 <= slv_reg49;
slv_reg50 <= slv_reg50;
slv_reg51 <= slv_reg51;
slv_reg52 <= slv_reg52;
slv_reg53 <= slv_reg53;
slv_reg54 <= slv_reg54;
slv_reg55 <= slv_reg55;
slv_reg56 <= slv_reg56;
slv_reg57 <= slv_reg57;
slv_reg58 <= slv_reg58;
slv_reg59 <= slv_reg59;
slv_reg60 <= slv_reg60;
slv_reg61 <= slv_reg61;
slv_reg62 <= slv_reg62;
slv_reg63 <= slv_reg63;
slv_reg64 <= slv_reg64;
slv_reg65 <= slv_reg65;
slv_reg66 <= slv_reg66;
slv_reg67 <= slv_reg67;
slv_reg68 <= slv_reg68;
slv_reg69 <= slv_reg69;
slv_reg70 <= slv_reg70;
slv_reg71 <= slv_reg71;
slv_reg72 <= slv_reg72;
slv_reg73 <= slv_reg73;
slv_reg74 <= slv_reg74;
slv_reg75 <= slv_reg75;
slv_reg76 <= slv_reg76;
slv_reg77 <= slv_reg77;
slv_reg78 <= slv_reg78;
slv_reg79 <= slv_reg79;
slv_reg80 <= slv_reg80;
slv_reg81 <= slv_reg81;
slv_reg82 <= slv_reg82;
slv_reg83 <= slv_reg83;
slv_reg84 <= slv_reg84;
slv_reg85 <= slv_reg85;
slv_reg86 <= slv_reg86;
slv_reg87 <= slv_reg87;
slv_reg88 <= slv_reg88;
slv_reg89 <= slv_reg89;
slv_reg90 <= slv_reg90;
slv_reg91 <= slv_reg91;
slv_reg92 <= slv_reg92;
slv_reg93 <= slv_reg93;
slv_reg94 <= slv_reg94;
slv_reg95 <= slv_reg95;
slv_reg96 <= slv_reg96;
slv_reg97 <= slv_reg97;
slv_reg98 <= slv_reg98;
slv_reg99 <= slv_reg99;
slv_reg100 <= slv_reg100;
slv_reg101 <= slv_reg101;
slv_reg102 <= slv_reg102;
slv_reg103 <= slv_reg103;
slv_reg104 <= slv_reg104;
slv_reg105 <= slv_reg105;
slv_reg106 <= slv_reg106;
slv_reg107 <= slv_reg107;
slv_reg108 <= slv_reg108;
slv_reg109 <= slv_reg109;
slv_reg110 <= slv_reg110;
slv_reg111 <= slv_reg111;
slv_reg112 <= slv_reg112;
slv_reg113 <= slv_reg113;
slv_reg114 <= slv_reg114;
slv_reg115 <= slv_reg115;
slv_reg116 <= slv_reg116;
slv_reg117 <= slv_reg117;
slv_reg118 <= slv_reg118;
slv_reg119 <= slv_reg119;
slv_reg120 <= slv_reg120;
slv_reg121 <= slv_reg121;
slv_reg122 <= slv_reg122;
slv_reg123 <= slv_reg123;
slv_reg124 <= slv_reg124;
slv_reg125 <= slv_reg125;
slv_reg126 <= slv_reg126;
slv_reg127 <= slv_reg127;
slv_reg128 <= slv_reg128;
slv_reg129 <= slv_reg129;
slv_reg130 <= slv_reg130;
slv_reg131 <= slv_reg131;
slv_reg132 <= slv_reg132;
slv_reg133 <= slv_reg133;
slv_reg134 <= slv_reg134;
slv_reg135 <= slv_reg135;
slv_reg136 <= slv_reg136;
slv_reg137 <= slv_reg137;
slv_reg138 <= slv_reg138;
slv_reg139 <= slv_reg139;
slv_reg140 <= slv_reg140;
slv_reg141 <= slv_reg141;
slv_reg142 <= slv_reg142;
slv_reg143 <= slv_reg143;
slv_reg144 <= slv_reg144;
slv_reg145 <= slv_reg145;
slv_reg146 <= slv_reg146;
slv_reg147 <= slv_reg147;
slv_reg148 <= slv_reg148;
slv_reg149 <= slv_reg149;
slv_reg150 <= slv_reg150;
slv_reg151 <= slv_reg151;
slv_reg152 <= slv_reg152;
slv_reg153 <= slv_reg153;
slv_reg154 <= slv_reg154;
slv_reg155 <= slv_reg155;
slv_reg156 <= slv_reg156;
slv_reg157 <= slv_reg157;
slv_reg158 <= slv_reg158;
slv_reg159 <= slv_reg159;
slv_reg160 <= slv_reg160;
slv_reg161 <= slv_reg161;
slv_reg162 <= slv_reg162;
slv_reg163 <= slv_reg163;
slv_reg164 <= slv_reg164;
slv_reg165 <= slv_reg165;
slv_reg166 <= slv_reg166;
slv_reg167 <= slv_reg167;
slv_reg168 <= slv_reg168;
slv_reg169 <= slv_reg169;
slv_reg170 <= slv_reg170;
slv_reg171 <= slv_reg171;
slv_reg172 <= slv_reg172;
slv_reg173 <= slv_reg173;
slv_reg174 <= slv_reg174;
slv_reg175 <= slv_reg175;
slv_reg176 <= slv_reg176;
slv_reg177 <= slv_reg177;
slv_reg178 <= slv_reg178;
slv_reg179 <= slv_reg179;
slv_reg180 <= slv_reg180;
slv_reg181 <= slv_reg181;
slv_reg182 <= slv_reg182;
slv_reg183 <= slv_reg183;
slv_reg184 <= slv_reg184;
slv_reg185 <= slv_reg185;
slv_reg186 <= slv_reg186;
slv_reg187 <= slv_reg187;
slv_reg188 <= slv_reg188;
slv_reg189 <= slv_reg189;
slv_reg190 <= slv_reg190;
slv_reg191 <= slv_reg191;
slv_reg192 <= slv_reg192;
slv_reg193 <= slv_reg193;
slv_reg194 <= slv_reg194;
slv_reg195 <= slv_reg195;
slv_reg196 <= slv_reg196;
slv_reg197 <= slv_reg197;
slv_reg198 <= slv_reg198;
slv_reg199 <= slv_reg199;
slv_reg200 <= slv_reg200;
slv_reg201 <= slv_reg201;
slv_reg202 <= slv_reg202;
slv_reg203 <= slv_reg203;
slv_reg204 <= slv_reg204;
slv_reg205 <= slv_reg205;
slv_reg206 <= slv_reg206;
slv_reg207 <= slv_reg207;
slv_reg208 <= slv_reg208;
slv_reg209 <= slv_reg209;
slv_reg210 <= slv_reg210;
slv_reg211 <= slv_reg211;
slv_reg212 <= slv_reg212;
slv_reg213 <= slv_reg213;
slv_reg214 <= slv_reg214;
slv_reg215 <= slv_reg215;
slv_reg216 <= slv_reg216;
slv_reg217 <= slv_reg217;
slv_reg218 <= slv_reg218;
slv_reg219 <= slv_reg219;
slv_reg220 <= slv_reg220;
slv_reg221 <= slv_reg221;
slv_reg222 <= slv_reg222;
slv_reg223 <= slv_reg223;
slv_reg224 <= slv_reg224;
slv_reg225 <= slv_reg225;
slv_reg226 <= slv_reg226;
slv_reg227 <= slv_reg227;
slv_reg228 <= slv_reg228;
slv_reg229 <= slv_reg229;
slv_reg230 <= slv_reg230;
slv_reg231 <= slv_reg231;
slv_reg232 <= slv_reg232;
slv_reg233 <= slv_reg233;
slv_reg234 <= slv_reg234;
slv_reg235 <= slv_reg235;
slv_reg236 <= slv_reg236;
slv_reg237 <= slv_reg237;
slv_reg238 <= slv_reg238;
slv_reg239 <= slv_reg239;
slv_reg240 <= slv_reg240;
slv_reg241 <= slv_reg241;
slv_reg242 <= slv_reg242;
slv_reg243 <= slv_reg243;
slv_reg244 <= slv_reg244;
slv_reg245 <= slv_reg245;
slv_reg246 <= slv_reg246;
slv_reg247 <= slv_reg247;
slv_reg248 <= slv_reg248;
slv_reg249 <= slv_reg249;
slv_reg250 <= slv_reg250;
slv_reg251 <= slv_reg251;
slv_reg252 <= slv_reg252;
slv_reg253 <= slv_reg253;
slv_reg254 <= slv_reg254;
slv_reg255 <= slv_reg255;
slv_reg256 <= slv_reg256;
slv_reg257 <= slv_reg257;
slv_reg258 <= slv_reg258;
slv_reg259 <= slv_reg259;
slv_reg260 <= slv_reg260;
slv_reg261 <= slv_reg261;
slv_reg262 <= slv_reg262;
slv_reg263 <= slv_reg263;
slv_reg264 <= slv_reg264;
slv_reg265 <= slv_reg265;
slv_reg266 <= slv_reg266;
slv_reg267 <= slv_reg267;
slv_reg268 <= slv_reg268;
slv_reg269 <= slv_reg269;
slv_reg270 <= slv_reg270;
slv_reg271 <= slv_reg271;
slv_reg272 <= slv_reg272;
slv_reg273 <= slv_reg273;
slv_reg274 <= slv_reg274;
slv_reg275 <= slv_reg275;
slv_reg276 <= slv_reg276;
slv_reg277 <= slv_reg277;
slv_reg278 <= slv_reg278;
slv_reg279 <= slv_reg279;
slv_reg280 <= slv_reg280;
slv_reg281 <= slv_reg281;
slv_reg282 <= slv_reg282;
slv_reg283 <= slv_reg283;
slv_reg284 <= slv_reg284;
slv_reg285 <= slv_reg285;
slv_reg286 <= slv_reg286;
slv_reg287 <= slv_reg287;
slv_reg288 <= slv_reg288;
slv_reg289 <= slv_reg289;
slv_reg290 <= slv_reg290;
slv_reg291 <= slv_reg291;
slv_reg292 <= slv_reg292;
slv_reg293 <= slv_reg293;
slv_reg294 <= slv_reg294;
slv_reg295 <= slv_reg295;
slv_reg296 <= slv_reg296;
slv_reg297 <= slv_reg297;
slv_reg298 <= slv_reg298;
slv_reg299 <= slv_reg299;
slv_reg300 <= slv_reg300;
slv_reg301 <= slv_reg301;
slv_reg302 <= slv_reg302;
slv_reg303 <= slv_reg303;
slv_reg304 <= slv_reg304;
slv_reg305 <= slv_reg305;
slv_reg306 <= slv_reg306;
slv_reg307 <= slv_reg307;
slv_reg308 <= slv_reg308;
slv_reg309 <= slv_reg309;
slv_reg310 <= slv_reg310;
slv_reg311 <= slv_reg311;
slv_reg312 <= slv_reg312;
slv_reg313 <= slv_reg313;
slv_reg314 <= slv_reg314;
slv_reg315 <= slv_reg315;
slv_reg316 <= slv_reg316;
slv_reg317 <= slv_reg317;
slv_reg318 <= slv_reg318;
slv_reg319 <= slv_reg319;
slv_reg320 <= slv_reg320;
slv_reg321 <= slv_reg321;
slv_reg322 <= slv_reg322;
slv_reg323 <= slv_reg323;
slv_reg324 <= slv_reg324;
slv_reg325 <= slv_reg325;
slv_reg326 <= slv_reg326;
slv_reg327 <= slv_reg327;
slv_reg328 <= slv_reg328;
slv_reg329 <= slv_reg329;
slv_reg330 <= slv_reg330;
slv_reg331 <= slv_reg331;
slv_reg332 <= slv_reg332;
slv_reg333 <= slv_reg333;
slv_reg334 <= slv_reg334;
slv_reg335 <= slv_reg335;
slv_reg336 <= slv_reg336;
slv_reg337 <= slv_reg337;
slv_reg338 <= slv_reg338;
slv_reg339 <= slv_reg339;
slv_reg340 <= slv_reg340;
slv_reg341 <= slv_reg341;
slv_reg342 <= slv_reg342;
slv_reg343 <= slv_reg343;
slv_reg344 <= slv_reg344;
slv_reg345 <= slv_reg345;
slv_reg346 <= slv_reg346;
slv_reg347 <= slv_reg347;
slv_reg348 <= slv_reg348;
slv_reg349 <= slv_reg349;
slv_reg350 <= slv_reg350;
slv_reg351 <= slv_reg351;
slv_reg352 <= slv_reg352;
slv_reg353 <= slv_reg353;
slv_reg354 <= slv_reg354;
slv_reg355 <= slv_reg355;
slv_reg356 <= slv_reg356;
slv_reg357 <= slv_reg357;
slv_reg358 <= slv_reg358;
slv_reg359 <= slv_reg359;
slv_reg360 <= slv_reg360;
slv_reg361 <= slv_reg361;
slv_reg362 <= slv_reg362;
slv_reg363 <= slv_reg363;
slv_reg364 <= slv_reg364;
slv_reg365 <= slv_reg365;
slv_reg366 <= slv_reg366;
slv_reg367 <= slv_reg367;
slv_reg368 <= slv_reg368;
slv_reg369 <= slv_reg369;
slv_reg370 <= slv_reg370;
slv_reg371 <= slv_reg371;
slv_reg372 <= slv_reg372;
slv_reg373 <= slv_reg373;
slv_reg374 <= slv_reg374;
slv_reg375 <= slv_reg375;
slv_reg376 <= slv_reg376;
slv_reg377 <= slv_reg377;
slv_reg378 <= slv_reg378;
slv_reg379 <= slv_reg379;
slv_reg380 <= slv_reg380;
slv_reg381 <= slv_reg381;
slv_reg382 <= slv_reg382;
slv_reg383 <= slv_reg383;
slv_reg384 <= slv_reg384;
slv_reg385 <= slv_reg385;
slv_reg386 <= slv_reg386;
slv_reg387 <= slv_reg387;
slv_reg388 <= slv_reg388;
slv_reg389 <= slv_reg389;
slv_reg390 <= slv_reg390;
slv_reg391 <= slv_reg391;
slv_reg392 <= slv_reg392;
slv_reg393 <= slv_reg393;
slv_reg394 <= slv_reg394;
slv_reg395 <= slv_reg395;
slv_reg396 <= slv_reg396;
slv_reg397 <= slv_reg397;
slv_reg398 <= slv_reg398;
slv_reg399 <= slv_reg399;
slv_reg400 <= slv_reg400;
slv_reg401 <= slv_reg401;
slv_reg402 <= slv_reg402;
slv_reg403 <= slv_reg403;
slv_reg404 <= slv_reg404;
slv_reg405 <= slv_reg405;
slv_reg406 <= slv_reg406;
slv_reg407 <= slv_reg407;
slv_reg408 <= slv_reg408;
slv_reg409 <= slv_reg409;
slv_reg410 <= slv_reg410;
slv_reg411 <= slv_reg411;
slv_reg412 <= slv_reg412;
slv_reg413 <= slv_reg413;
slv_reg414 <= slv_reg414;
slv_reg415 <= slv_reg415;
slv_reg416 <= slv_reg416;
slv_reg417 <= slv_reg417;
slv_reg418 <= slv_reg418;
slv_reg419 <= slv_reg419;
slv_reg420 <= slv_reg420;
slv_reg421 <= slv_reg421;
slv_reg422 <= slv_reg422;
slv_reg423 <= slv_reg423;
slv_reg424 <= slv_reg424;
slv_reg425 <= slv_reg425;
slv_reg426 <= slv_reg426;
slv_reg427 <= slv_reg427;
slv_reg428 <= slv_reg428;
slv_reg429 <= slv_reg429;
slv_reg430 <= slv_reg430;
slv_reg431 <= slv_reg431;
slv_reg432 <= slv_reg432;
slv_reg433 <= slv_reg433;
slv_reg434 <= slv_reg434;
slv_reg435 <= slv_reg435;
slv_reg436 <= slv_reg436;
slv_reg437 <= slv_reg437;
slv_reg438 <= slv_reg438;
slv_reg439 <= slv_reg439;
slv_reg440 <= slv_reg440;
slv_reg441 <= slv_reg441;
slv_reg442 <= slv_reg442;
slv_reg443 <= slv_reg443;
slv_reg444 <= slv_reg444;
slv_reg445 <= slv_reg445;
slv_reg446 <= slv_reg446;
slv_reg447 <= slv_reg447;
slv_reg448 <= slv_reg448;
slv_reg449 <= slv_reg449;
slv_reg450 <= slv_reg450;
slv_reg451 <= slv_reg451;
slv_reg452 <= slv_reg452;
slv_reg453 <= slv_reg453;
slv_reg454 <= slv_reg454;
slv_reg455 <= slv_reg455;
slv_reg456 <= slv_reg456;
slv_reg457 <= slv_reg457;
slv_reg458 <= slv_reg458;
slv_reg459 <= slv_reg459;
slv_reg460 <= slv_reg460;
slv_reg461 <= slv_reg461;
slv_reg462 <= slv_reg462;
slv_reg463 <= slv_reg463;
slv_reg464 <= slv_reg464;
slv_reg465 <= slv_reg465;
slv_reg466 <= slv_reg466;
slv_reg467 <= slv_reg467;
slv_reg468 <= slv_reg468;
slv_reg469 <= slv_reg469;
slv_reg470 <= slv_reg470;
slv_reg471 <= slv_reg471;
slv_reg472 <= slv_reg472;
slv_reg473 <= slv_reg473;
slv_reg474 <= slv_reg474;
slv_reg475 <= slv_reg475;
slv_reg476 <= slv_reg476;
slv_reg477 <= slv_reg477;
slv_reg478 <= slv_reg478;
slv_reg479 <= slv_reg479;
slv_reg480 <= slv_reg480;
slv_reg481 <= slv_reg481;
slv_reg482 <= slv_reg482;
slv_reg483 <= slv_reg483;
slv_reg484 <= slv_reg484;
slv_reg485 <= slv_reg485;
slv_reg486 <= slv_reg486;
slv_reg487 <= slv_reg487;
slv_reg488 <= slv_reg488;
slv_reg489 <= slv_reg489;
slv_reg490 <= slv_reg490;
slv_reg491 <= slv_reg491;
slv_reg492 <= slv_reg492;
slv_reg493 <= slv_reg493;
slv_reg494 <= slv_reg494;
slv_reg495 <= slv_reg495;
slv_reg496 <= slv_reg496;
slv_reg497 <= slv_reg497;
slv_reg498 <= slv_reg498;
slv_reg499 <= slv_reg499;
slv_reg500 <= slv_reg500;
slv_reg501 <= slv_reg501;
slv_reg502 <= slv_reg502;
slv_reg503 <= slv_reg503;
slv_reg504 <= slv_reg504;
slv_reg505 <= slv_reg505;
slv_reg506 <= slv_reg506;
slv_reg507 <= slv_reg507;
slv_reg508 <= slv_reg508;
slv_reg509 <= slv_reg509;
slv_reg510 <= slv_reg510;
slv_reg511 <= slv_reg511;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39, slv_reg40, slv_reg41, slv_reg42, slv_reg43, slv_reg44, slv_reg45, slv_reg46, slv_reg47, slv_reg48, slv_reg49, slv_reg50, slv_reg51, slv_reg52, slv_reg53, slv_reg54, slv_reg55, slv_reg56, slv_reg57, slv_reg58, slv_reg59, slv_reg60, slv_reg61, slv_reg62, slv_reg63, slv_reg64, slv_reg65, slv_reg66, slv_reg67, slv_reg68, slv_reg69, slv_reg70, slv_reg71, slv_reg72, slv_reg73, slv_reg74, slv_reg75, slv_reg76, slv_reg77, slv_reg78, slv_reg79, slv_reg80, slv_reg81, slv_reg82, slv_reg83, slv_reg84, slv_reg85, slv_reg86, slv_reg87, slv_reg88, slv_reg89, slv_reg90, slv_reg91, slv_reg92, slv_reg93, slv_reg94, slv_reg95, slv_reg96, slv_reg97, slv_reg98, slv_reg99, slv_reg100, slv_reg101, slv_reg102, slv_reg103, slv_reg104, slv_reg105, slv_reg106, slv_reg107, slv_reg108, slv_reg109, slv_reg110, slv_reg111, slv_reg112, slv_reg113, slv_reg114, slv_reg115, slv_reg116, slv_reg117, slv_reg118, slv_reg119, slv_reg120, slv_reg121, slv_reg122, slv_reg123, slv_reg124, slv_reg125, slv_reg126, slv_reg127, slv_reg128, slv_reg129, slv_reg130, slv_reg131, slv_reg132, slv_reg133, slv_reg134, slv_reg135, slv_reg136, slv_reg137, slv_reg138, slv_reg139, slv_reg140, slv_reg141, slv_reg142, slv_reg143, slv_reg144, slv_reg145, slv_reg146, slv_reg147, slv_reg148, slv_reg149, slv_reg150, slv_reg151, slv_reg152, slv_reg153, slv_reg154, slv_reg155, slv_reg156, slv_reg157, slv_reg158, slv_reg159, slv_reg160, slv_reg161, slv_reg162, slv_reg163, slv_reg164, slv_reg165, slv_reg166, slv_reg167, slv_reg168, slv_reg169, slv_reg170, slv_reg171, slv_reg172, slv_reg173, slv_reg174, slv_reg175, slv_reg176, slv_reg177, slv_reg178, slv_reg179, slv_reg180, slv_reg181, slv_reg182, slv_reg183, slv_reg184, slv_reg185, slv_reg186, slv_reg187, slv_reg188, slv_reg189, slv_reg190, slv_reg191, slv_reg192, slv_reg193, slv_reg194, slv_reg195, slv_reg196, slv_reg197, slv_reg198, slv_reg199, slv_reg200, slv_reg201, slv_reg202, slv_reg203, slv_reg204, slv_reg205, slv_reg206, slv_reg207, slv_reg208, slv_reg209, slv_reg210, slv_reg211, slv_reg212, slv_reg213, slv_reg214, slv_reg215, slv_reg216, slv_reg217, slv_reg218, slv_reg219, slv_reg220, slv_reg221, slv_reg222, slv_reg223, slv_reg224, slv_reg225, slv_reg226, slv_reg227, slv_reg228, slv_reg229, slv_reg230, slv_reg231, slv_reg232, slv_reg233, slv_reg234, slv_reg235, slv_reg236, slv_reg237, slv_reg238, slv_reg239, slv_reg240, slv_reg241, slv_reg242, slv_reg243, slv_reg244, slv_reg245, slv_reg246, slv_reg247, slv_reg248, slv_reg249, slv_reg250, slv_reg251, slv_reg252, slv_reg253, slv_reg254, slv_reg255, slv_reg256, slv_reg257, slv_reg258, slv_reg259, slv_reg260, slv_reg261, slv_reg262, slv_reg263, slv_reg264, slv_reg265, slv_reg266, slv_reg267, slv_reg268, slv_reg269, slv_reg270, slv_reg271, slv_reg272, slv_reg273, slv_reg274, slv_reg275, slv_reg276, slv_reg277, slv_reg278, slv_reg279, slv_reg280, slv_reg281, slv_reg282, slv_reg283, slv_reg284, slv_reg285, slv_reg286, slv_reg287, slv_reg288, slv_reg289, slv_reg290, slv_reg291, slv_reg292, slv_reg293, slv_reg294, slv_reg295, slv_reg296, slv_reg297, slv_reg298, slv_reg299, slv_reg300, slv_reg301, slv_reg302, slv_reg303, slv_reg304, slv_reg305, slv_reg306, slv_reg307, slv_reg308, slv_reg309, slv_reg310, slv_reg311, slv_reg312, slv_reg313, slv_reg314, slv_reg315, slv_reg316, slv_reg317, slv_reg318, slv_reg319, slv_reg320, slv_reg321, slv_reg322, slv_reg323, slv_reg324, slv_reg325, slv_reg326, slv_reg327, slv_reg328, slv_reg329, slv_reg330, slv_reg331, slv_reg332, slv_reg333, slv_reg334, slv_reg335, slv_reg336, slv_reg337, slv_reg338, slv_reg339, slv_reg340, slv_reg341, slv_reg342, slv_reg343, slv_reg344, slv_reg345, slv_reg346, slv_reg347, slv_reg348, slv_reg349, slv_reg350, slv_reg351, slv_reg352, slv_reg353, slv_reg354, slv_reg355, slv_reg356, slv_reg357, slv_reg358, slv_reg359, slv_reg360, slv_reg361, slv_reg362, slv_reg363, slv_reg364, slv_reg365, slv_reg366, slv_reg367, slv_reg368, slv_reg369, slv_reg370, slv_reg371, slv_reg372, slv_reg373, slv_reg374, slv_reg375, slv_reg376, slv_reg377, slv_reg378, slv_reg379, slv_reg380, slv_reg381, slv_reg382, slv_reg383, slv_reg384, slv_reg385, slv_reg386, slv_reg387, slv_reg388, slv_reg389, slv_reg390, slv_reg391, slv_reg392, slv_reg393, slv_reg394, slv_reg395, slv_reg396, slv_reg397, slv_reg398, slv_reg399, slv_reg400, slv_reg401, slv_reg402, slv_reg403, slv_reg404, slv_reg405, slv_reg406, slv_reg407, slv_reg408, slv_reg409, slv_reg410, slv_reg411, slv_reg412, slv_reg413, slv_reg414, slv_reg415, slv_reg416, slv_reg417, slv_reg418, slv_reg419, slv_reg420, slv_reg421, slv_reg422, slv_reg423, slv_reg424, slv_reg425, slv_reg426, slv_reg427, slv_reg428, slv_reg429, slv_reg430, slv_reg431, slv_reg432, slv_reg433, slv_reg434, slv_reg435, slv_reg436, slv_reg437, slv_reg438, slv_reg439, slv_reg440, slv_reg441, slv_reg442, slv_reg443, slv_reg444, slv_reg445, slv_reg446, slv_reg447, slv_reg448, slv_reg449, slv_reg450, slv_reg451, slv_reg452, slv_reg453, slv_reg454, slv_reg455, slv_reg456, slv_reg457, slv_reg458, slv_reg459, slv_reg460, slv_reg461, slv_reg462, slv_reg463, slv_reg464, slv_reg465, slv_reg466, slv_reg467, slv_reg468, slv_reg469, slv_reg470, slv_reg471, slv_reg472, slv_reg473, slv_reg474, slv_reg475, slv_reg476, slv_reg477, slv_reg478, slv_reg479, slv_reg480, slv_reg481, slv_reg482, slv_reg483, slv_reg484, slv_reg485, slv_reg486, slv_reg487, slv_reg488, slv_reg489, slv_reg490, slv_reg491, slv_reg492, slv_reg493, slv_reg494, slv_reg495, slv_reg496, slv_reg497, slv_reg498, slv_reg499, slv_reg500, slv_reg501, slv_reg502, slv_reg503, slv_reg504, slv_reg505, slv_reg506, slv_reg507, slv_reg508, slv_reg509, slv_reg510, slv_reg511, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when b"000000101" =>
reg_data_out <= slv_reg5;
when b"000000110" =>
reg_data_out <= slv_reg6;
when b"000000111" =>
reg_data_out <= slv_reg7;
when b"000001000" =>
reg_data_out <= slv_reg8;
when b"000001001" =>
reg_data_out <= slv_reg9;
when b"000001010" =>
reg_data_out <= slv_reg10;
when b"000001011" =>
reg_data_out <= slv_reg11;
when b"000001100" =>
reg_data_out <= slv_reg12;
when b"000001101" =>
reg_data_out <= slv_reg13;
when b"000001110" =>
reg_data_out <= slv_reg14;
when b"000001111" =>
reg_data_out <= slv_reg15;
when b"000010000" =>
reg_data_out <= slv_reg16;
when b"000010001" =>
reg_data_out <= slv_reg17;
when b"000010010" =>
reg_data_out <= slv_reg18;
when b"000010011" =>
reg_data_out <= slv_reg19;
when b"000010100" =>
reg_data_out <= slv_reg20;
when b"000010101" =>
reg_data_out <= slv_reg21;
when b"000010110" =>
reg_data_out <= slv_reg22;
when b"000010111" =>
reg_data_out <= slv_reg23;
when b"000011000" =>
reg_data_out <= slv_reg24;
when b"000011001" =>
reg_data_out <= slv_reg25;
when b"000011010" =>
reg_data_out <= slv_reg26;
when b"000011011" =>
reg_data_out <= slv_reg27;
when b"000011100" =>
reg_data_out <= slv_reg28;
when b"000011101" =>
reg_data_out <= slv_reg29;
when b"000011110" =>
reg_data_out <= slv_reg30;
when b"000011111" =>
reg_data_out <= slv_reg31;
when b"000100000" =>
reg_data_out <= slv_reg32;
when b"000100001" =>
reg_data_out <= slv_reg33;
when b"000100010" =>
reg_data_out <= slv_reg34;
when b"000100011" =>
reg_data_out <= slv_reg35;
when b"000100100" =>
reg_data_out <= slv_reg36;
when b"000100101" =>
reg_data_out <= slv_reg37;
when b"000100110" =>
reg_data_out <= slv_reg38;
when b"000100111" =>
reg_data_out <= slv_reg39;
when b"000101000" =>
reg_data_out <= slv_reg40;
when b"000101001" =>
reg_data_out <= slv_reg41;
when b"000101010" =>
reg_data_out <= slv_reg42;
when b"000101011" =>
reg_data_out <= slv_reg43;
when b"000101100" =>
reg_data_out <= slv_reg44;
when b"000101101" =>
reg_data_out <= slv_reg45;
when b"000101110" =>
reg_data_out <= slv_reg46;
when b"000101111" =>
reg_data_out <= slv_reg47;
when b"000110000" =>
reg_data_out <= slv_reg48;
when b"000110001" =>
reg_data_out <= slv_reg49;
when b"000110010" =>
reg_data_out <= slv_reg50;
when b"000110011" =>
reg_data_out <= slv_reg51;
when b"000110100" =>
reg_data_out <= slv_reg52;
when b"000110101" =>
reg_data_out <= slv_reg53;
when b"000110110" =>
reg_data_out <= slv_reg54;
when b"000110111" =>
reg_data_out <= slv_reg55;
when b"000111000" =>
reg_data_out <= slv_reg56;
when b"000111001" =>
reg_data_out <= slv_reg57;
when b"000111010" =>
reg_data_out <= slv_reg58;
when b"000111011" =>
reg_data_out <= slv_reg59;
when b"000111100" =>
reg_data_out <= slv_reg60;
when b"000111101" =>
reg_data_out <= slv_reg61;
when b"000111110" =>
reg_data_out <= slv_reg62;
when b"000111111" =>
reg_data_out <= slv_reg63;
when b"001000000" =>
reg_data_out <= slv_reg64;
when b"001000001" =>
reg_data_out <= slv_reg65;
when b"001000010" =>
reg_data_out <= slv_reg66;
when b"001000011" =>
reg_data_out <= slv_reg67;
when b"001000100" =>
reg_data_out <= slv_reg68;
when b"001000101" =>
reg_data_out <= slv_reg69;
when b"001000110" =>
reg_data_out <= slv_reg70;
when b"001000111" =>
reg_data_out <= slv_reg71;
when b"001001000" =>
reg_data_out <= slv_reg72;
when b"001001001" =>
reg_data_out <= slv_reg73;
when b"001001010" =>
reg_data_out <= slv_reg74;
when b"001001011" =>
reg_data_out <= slv_reg75;
when b"001001100" =>
reg_data_out <= slv_reg76;
when b"001001101" =>
reg_data_out <= slv_reg77;
when b"001001110" =>
reg_data_out <= slv_reg78;
when b"001001111" =>
reg_data_out <= slv_reg79;
when b"001010000" =>
reg_data_out <= slv_reg80;
when b"001010001" =>
reg_data_out <= slv_reg81;
when b"001010010" =>
reg_data_out <= slv_reg82;
when b"001010011" =>
reg_data_out <= slv_reg83;
when b"001010100" =>
reg_data_out <= slv_reg84;
when b"001010101" =>
reg_data_out <= slv_reg85;
when b"001010110" =>
reg_data_out <= slv_reg86;
when b"001010111" =>
reg_data_out <= slv_reg87;
when b"001011000" =>
reg_data_out <= slv_reg88;
when b"001011001" =>
reg_data_out <= slv_reg89;
when b"001011010" =>
reg_data_out <= slv_reg90;
when b"001011011" =>
reg_data_out <= slv_reg91;
when b"001011100" =>
reg_data_out <= slv_reg92;
when b"001011101" =>
reg_data_out <= slv_reg93;
when b"001011110" =>
reg_data_out <= slv_reg94;
when b"001011111" =>
reg_data_out <= slv_reg95;
when b"001100000" =>
reg_data_out <= slv_reg96;
when b"001100001" =>
reg_data_out <= slv_reg97;
when b"001100010" =>
reg_data_out <= slv_reg98;
when b"001100011" =>
reg_data_out <= slv_reg99;
when b"001100100" =>
reg_data_out <= slv_reg100;
when b"001100101" =>
reg_data_out <= slv_reg101;
when b"001100110" =>
reg_data_out <= slv_reg102;
when b"001100111" =>
reg_data_out <= slv_reg103;
when b"001101000" =>
reg_data_out <= slv_reg104;
when b"001101001" =>
reg_data_out <= slv_reg105;
when b"001101010" =>
reg_data_out <= slv_reg106;
when b"001101011" =>
reg_data_out <= slv_reg107;
when b"001101100" =>
reg_data_out <= slv_reg108;
when b"001101101" =>
reg_data_out <= slv_reg109;
when b"001101110" =>
reg_data_out <= slv_reg110;
when b"001101111" =>
reg_data_out <= slv_reg111;
when b"001110000" =>
reg_data_out <= slv_reg112;
when b"001110001" =>
reg_data_out <= slv_reg113;
when b"001110010" =>
reg_data_out <= slv_reg114;
when b"001110011" =>
reg_data_out <= slv_reg115;
when b"001110100" =>
reg_data_out <= slv_reg116;
when b"001110101" =>
reg_data_out <= slv_reg117;
when b"001110110" =>
reg_data_out <= slv_reg118;
when b"001110111" =>
reg_data_out <= slv_reg119;
when b"001111000" =>
reg_data_out <= slv_reg120;
when b"001111001" =>
reg_data_out <= slv_reg121;
when b"001111010" =>
reg_data_out <= slv_reg122;
when b"001111011" =>
reg_data_out <= slv_reg123;
when b"001111100" =>
reg_data_out <= slv_reg124;
when b"001111101" =>
reg_data_out <= slv_reg125;
when b"001111110" =>
reg_data_out <= slv_reg126;
when b"001111111" =>
reg_data_out <= slv_reg127;
when b"010000000" =>
reg_data_out <= slv_reg128;
when b"010000001" =>
reg_data_out <= slv_reg129;
when b"010000010" =>
reg_data_out <= slv_reg130;
when b"010000011" =>
reg_data_out <= slv_reg131;
when b"010000100" =>
reg_data_out <= slv_reg132;
when b"010000101" =>
reg_data_out <= slv_reg133;
when b"010000110" =>
reg_data_out <= slv_reg134;
when b"010000111" =>
reg_data_out <= slv_reg135;
when b"010001000" =>
reg_data_out <= slv_reg136;
when b"010001001" =>
reg_data_out <= slv_reg137;
when b"010001010" =>
reg_data_out <= slv_reg138;
when b"010001011" =>
reg_data_out <= slv_reg139;
when b"010001100" =>
reg_data_out <= slv_reg140;
when b"010001101" =>
reg_data_out <= slv_reg141;
when b"010001110" =>
reg_data_out <= slv_reg142;
when b"010001111" =>
reg_data_out <= slv_reg143;
when b"010010000" =>
reg_data_out <= slv_reg144;
when b"010010001" =>
reg_data_out <= slv_reg145;
when b"010010010" =>
reg_data_out <= slv_reg146;
when b"010010011" =>
reg_data_out <= slv_reg147;
when b"010010100" =>
reg_data_out <= slv_reg148;
when b"010010101" =>
reg_data_out <= slv_reg149;
when b"010010110" =>
reg_data_out <= slv_reg150;
when b"010010111" =>
reg_data_out <= slv_reg151;
when b"010011000" =>
reg_data_out <= slv_reg152;
when b"010011001" =>
reg_data_out <= slv_reg153;
when b"010011010" =>
reg_data_out <= slv_reg154;
when b"010011011" =>
reg_data_out <= slv_reg155;
when b"010011100" =>
reg_data_out <= slv_reg156;
when b"010011101" =>
reg_data_out <= slv_reg157;
when b"010011110" =>
reg_data_out <= slv_reg158;
when b"010011111" =>
reg_data_out <= slv_reg159;
when b"010100000" =>
reg_data_out <= slv_reg160;
when b"010100001" =>
reg_data_out <= slv_reg161;
when b"010100010" =>
reg_data_out <= slv_reg162;
when b"010100011" =>
reg_data_out <= slv_reg163;
when b"010100100" =>
reg_data_out <= slv_reg164;
when b"010100101" =>
reg_data_out <= slv_reg165;
when b"010100110" =>
reg_data_out <= slv_reg166;
when b"010100111" =>
reg_data_out <= slv_reg167;
when b"010101000" =>
reg_data_out <= slv_reg168;
when b"010101001" =>
reg_data_out <= slv_reg169;
when b"010101010" =>
reg_data_out <= slv_reg170;
when b"010101011" =>
reg_data_out <= slv_reg171;
when b"010101100" =>
reg_data_out <= slv_reg172;
when b"010101101" =>
reg_data_out <= slv_reg173;
when b"010101110" =>
reg_data_out <= slv_reg174;
when b"010101111" =>
reg_data_out <= slv_reg175;
when b"010110000" =>
reg_data_out <= slv_reg176;
when b"010110001" =>
reg_data_out <= slv_reg177;
when b"010110010" =>
reg_data_out <= slv_reg178;
when b"010110011" =>
reg_data_out <= slv_reg179;
when b"010110100" =>
reg_data_out <= slv_reg180;
when b"010110101" =>
reg_data_out <= slv_reg181;
when b"010110110" =>
reg_data_out <= slv_reg182;
when b"010110111" =>
reg_data_out <= slv_reg183;
when b"010111000" =>
reg_data_out <= slv_reg184;
when b"010111001" =>
reg_data_out <= slv_reg185;
when b"010111010" =>
reg_data_out <= slv_reg186;
when b"010111011" =>
reg_data_out <= slv_reg187;
when b"010111100" =>
reg_data_out <= slv_reg188;
when b"010111101" =>
reg_data_out <= slv_reg189;
when b"010111110" =>
reg_data_out <= slv_reg190;
when b"010111111" =>
reg_data_out <= slv_reg191;
when b"011000000" =>
reg_data_out <= slv_reg192;
when b"011000001" =>
reg_data_out <= slv_reg193;
when b"011000010" =>
reg_data_out <= slv_reg194;
when b"011000011" =>
reg_data_out <= slv_reg195;
when b"011000100" =>
reg_data_out <= slv_reg196;
when b"011000101" =>
reg_data_out <= slv_reg197;
when b"011000110" =>
reg_data_out <= slv_reg198;
when b"011000111" =>
reg_data_out <= slv_reg199;
when b"011001000" =>
reg_data_out <= slv_reg200;
when b"011001001" =>
reg_data_out <= slv_reg201;
when b"011001010" =>
reg_data_out <= slv_reg202;
when b"011001011" =>
reg_data_out <= slv_reg203;
when b"011001100" =>
reg_data_out <= slv_reg204;
when b"011001101" =>
reg_data_out <= slv_reg205;
when b"011001110" =>
reg_data_out <= slv_reg206;
when b"011001111" =>
reg_data_out <= slv_reg207;
when b"011010000" =>
reg_data_out <= slv_reg208;
when b"011010001" =>
reg_data_out <= slv_reg209;
when b"011010010" =>
reg_data_out <= slv_reg210;
when b"011010011" =>
reg_data_out <= slv_reg211;
when b"011010100" =>
reg_data_out <= slv_reg212;
when b"011010101" =>
reg_data_out <= slv_reg213;
when b"011010110" =>
reg_data_out <= slv_reg214;
when b"011010111" =>
reg_data_out <= slv_reg215;
when b"011011000" =>
reg_data_out <= slv_reg216;
when b"011011001" =>
reg_data_out <= slv_reg217;
when b"011011010" =>
reg_data_out <= slv_reg218;
when b"011011011" =>
reg_data_out <= slv_reg219;
when b"011011100" =>
reg_data_out <= slv_reg220;
when b"011011101" =>
reg_data_out <= slv_reg221;
when b"011011110" =>
reg_data_out <= slv_reg222;
when b"011011111" =>
reg_data_out <= slv_reg223;
when b"011100000" =>
reg_data_out <= slv_reg224;
when b"011100001" =>
reg_data_out <= slv_reg225;
when b"011100010" =>
reg_data_out <= slv_reg226;
when b"011100011" =>
reg_data_out <= slv_reg227;
when b"011100100" =>
reg_data_out <= slv_reg228;
when b"011100101" =>
reg_data_out <= slv_reg229;
when b"011100110" =>
reg_data_out <= slv_reg230;
when b"011100111" =>
reg_data_out <= slv_reg231;
when b"011101000" =>
reg_data_out <= slv_reg232;
when b"011101001" =>
reg_data_out <= slv_reg233;
when b"011101010" =>
reg_data_out <= slv_reg234;
when b"011101011" =>
reg_data_out <= slv_reg235;
when b"011101100" =>
reg_data_out <= slv_reg236;
when b"011101101" =>
reg_data_out <= slv_reg237;
when b"011101110" =>
reg_data_out <= slv_reg238;
when b"011101111" =>
reg_data_out <= slv_reg239;
when b"011110000" =>
reg_data_out <= slv_reg240;
when b"011110001" =>
reg_data_out <= slv_reg241;
when b"011110010" =>
reg_data_out <= slv_reg242;
when b"011110011" =>
reg_data_out <= slv_reg243;
when b"011110100" =>
reg_data_out <= slv_reg244;
when b"011110101" =>
reg_data_out <= slv_reg245;
when b"011110110" =>
reg_data_out <= slv_reg246;
when b"011110111" =>
reg_data_out <= slv_reg247;
when b"011111000" =>
reg_data_out <= slv_reg248;
when b"011111001" =>
reg_data_out <= slv_reg249;
when b"011111010" =>
reg_data_out <= slv_reg250;
when b"011111011" =>
reg_data_out <= slv_reg251;
when b"011111100" =>
reg_data_out <= slv_reg252;
when b"011111101" =>
reg_data_out <= slv_reg253;
when b"011111110" =>
reg_data_out <= slv_reg254;
when b"011111111" =>
reg_data_out <= slv_reg255;
when b"100000000" =>
reg_data_out <= slv_reg256;
when b"100000001" =>
reg_data_out <= slv_reg257;
when b"100000010" =>
reg_data_out <= slv_reg258;
when b"100000011" =>
reg_data_out <= slv_reg259;
when b"100000100" =>
reg_data_out <= slv_reg260;
when b"100000101" =>
reg_data_out <= slv_reg261;
when b"100000110" =>
reg_data_out <= slv_reg262;
when b"100000111" =>
reg_data_out <= slv_reg263;
when b"100001000" =>
reg_data_out <= slv_reg264;
when b"100001001" =>
reg_data_out <= slv_reg265;
when b"100001010" =>
reg_data_out <= slv_reg266;
when b"100001011" =>
reg_data_out <= slv_reg267;
when b"100001100" =>
reg_data_out <= slv_reg268;
when b"100001101" =>
reg_data_out <= slv_reg269;
when b"100001110" =>
reg_data_out <= slv_reg270;
when b"100001111" =>
reg_data_out <= slv_reg271;
when b"100010000" =>
reg_data_out <= slv_reg272;
when b"100010001" =>
reg_data_out <= slv_reg273;
when b"100010010" =>
reg_data_out <= slv_reg274;
when b"100010011" =>
reg_data_out <= slv_reg275;
when b"100010100" =>
reg_data_out <= slv_reg276;
when b"100010101" =>
reg_data_out <= slv_reg277;
when b"100010110" =>
reg_data_out <= slv_reg278;
when b"100010111" =>
reg_data_out <= slv_reg279;
when b"100011000" =>
reg_data_out <= slv_reg280;
when b"100011001" =>
reg_data_out <= slv_reg281;
when b"100011010" =>
reg_data_out <= slv_reg282;
when b"100011011" =>
reg_data_out <= slv_reg283;
when b"100011100" =>
reg_data_out <= slv_reg284;
when b"100011101" =>
reg_data_out <= slv_reg285;
when b"100011110" =>
reg_data_out <= slv_reg286;
when b"100011111" =>
reg_data_out <= slv_reg287;
when b"100100000" =>
reg_data_out <= slv_reg288;
when b"100100001" =>
reg_data_out <= slv_reg289;
when b"100100010" =>
reg_data_out <= slv_reg290;
when b"100100011" =>
reg_data_out <= slv_reg291;
when b"100100100" =>
reg_data_out <= slv_reg292;
when b"100100101" =>
reg_data_out <= slv_reg293;
when b"100100110" =>
reg_data_out <= slv_reg294;
when b"100100111" =>
reg_data_out <= slv_reg295;
when b"100101000" =>
reg_data_out <= slv_reg296;
when b"100101001" =>
reg_data_out <= slv_reg297;
when b"100101010" =>
reg_data_out <= slv_reg298;
when b"100101011" =>
reg_data_out <= slv_reg299;
when b"100101100" =>
reg_data_out <= slv_reg300;
when b"100101101" =>
reg_data_out <= slv_reg301;
when b"100101110" =>
reg_data_out <= slv_reg302;
when b"100101111" =>
reg_data_out <= slv_reg303;
when b"100110000" =>
reg_data_out <= slv_reg304;
when b"100110001" =>
reg_data_out <= slv_reg305;
when b"100110010" =>
reg_data_out <= slv_reg306;
when b"100110011" =>
reg_data_out <= slv_reg307;
when b"100110100" =>
reg_data_out <= slv_reg308;
when b"100110101" =>
reg_data_out <= slv_reg309;
when b"100110110" =>
reg_data_out <= slv_reg310;
when b"100110111" =>
reg_data_out <= slv_reg311;
when b"100111000" =>
reg_data_out <= slv_reg312;
when b"100111001" =>
reg_data_out <= slv_reg313;
when b"100111010" =>
reg_data_out <= slv_reg314;
when b"100111011" =>
reg_data_out <= slv_reg315;
when b"100111100" =>
reg_data_out <= slv_reg316;
when b"100111101" =>
reg_data_out <= slv_reg317;
when b"100111110" =>
reg_data_out <= slv_reg318;
when b"100111111" =>
reg_data_out <= slv_reg319;
when b"101000000" =>
reg_data_out <= slv_reg320;
when b"101000001" =>
reg_data_out <= slv_reg321;
when b"101000010" =>
reg_data_out <= slv_reg322;
when b"101000011" =>
reg_data_out <= slv_reg323;
when b"101000100" =>
reg_data_out <= slv_reg324;
when b"101000101" =>
reg_data_out <= slv_reg325;
when b"101000110" =>
reg_data_out <= slv_reg326;
when b"101000111" =>
reg_data_out <= slv_reg327;
when b"101001000" =>
reg_data_out <= slv_reg328;
when b"101001001" =>
reg_data_out <= slv_reg329;
when b"101001010" =>
reg_data_out <= slv_reg330;
when b"101001011" =>
reg_data_out <= slv_reg331;
when b"101001100" =>
reg_data_out <= slv_reg332;
when b"101001101" =>
reg_data_out <= slv_reg333;
when b"101001110" =>
reg_data_out <= slv_reg334;
when b"101001111" =>
reg_data_out <= slv_reg335;
when b"101010000" =>
reg_data_out <= slv_reg336;
when b"101010001" =>
reg_data_out <= slv_reg337;
when b"101010010" =>
reg_data_out <= slv_reg338;
when b"101010011" =>
reg_data_out <= slv_reg339;
when b"101010100" =>
reg_data_out <= slv_reg340;
when b"101010101" =>
reg_data_out <= slv_reg341;
when b"101010110" =>
reg_data_out <= slv_reg342;
when b"101010111" =>
reg_data_out <= slv_reg343;
when b"101011000" =>
reg_data_out <= slv_reg344;
when b"101011001" =>
reg_data_out <= slv_reg345;
when b"101011010" =>
reg_data_out <= slv_reg346;
when b"101011011" =>
reg_data_out <= slv_reg347;
when b"101011100" =>
reg_data_out <= slv_reg348;
when b"101011101" =>
reg_data_out <= slv_reg349;
when b"101011110" =>
reg_data_out <= slv_reg350;
when b"101011111" =>
reg_data_out <= slv_reg351;
when b"101100000" =>
reg_data_out <= slv_reg352;
when b"101100001" =>
reg_data_out <= slv_reg353;
when b"101100010" =>
reg_data_out <= slv_reg354;
when b"101100011" =>
reg_data_out <= slv_reg355;
when b"101100100" =>
reg_data_out <= slv_reg356;
when b"101100101" =>
reg_data_out <= slv_reg357;
when b"101100110" =>
reg_data_out <= slv_reg358;
when b"101100111" =>
reg_data_out <= slv_reg359;
when b"101101000" =>
reg_data_out <= slv_reg360;
when b"101101001" =>
reg_data_out <= slv_reg361;
when b"101101010" =>
reg_data_out <= slv_reg362;
when b"101101011" =>
reg_data_out <= slv_reg363;
when b"101101100" =>
reg_data_out <= slv_reg364;
when b"101101101" =>
reg_data_out <= slv_reg365;
when b"101101110" =>
reg_data_out <= slv_reg366;
when b"101101111" =>
reg_data_out <= slv_reg367;
when b"101110000" =>
reg_data_out <= slv_reg368;
when b"101110001" =>
reg_data_out <= slv_reg369;
when b"101110010" =>
reg_data_out <= slv_reg370;
when b"101110011" =>
reg_data_out <= slv_reg371;
when b"101110100" =>
reg_data_out <= slv_reg372;
when b"101110101" =>
reg_data_out <= slv_reg373;
when b"101110110" =>
reg_data_out <= slv_reg374;
when b"101110111" =>
reg_data_out <= slv_reg375;
when b"101111000" =>
reg_data_out <= slv_reg376;
when b"101111001" =>
reg_data_out <= slv_reg377;
when b"101111010" =>
reg_data_out <= slv_reg378;
when b"101111011" =>
reg_data_out <= slv_reg379;
when b"101111100" =>
reg_data_out <= slv_reg380;
when b"101111101" =>
reg_data_out <= slv_reg381;
when b"101111110" =>
reg_data_out <= slv_reg382;
when b"101111111" =>
reg_data_out <= slv_reg383;
when b"110000000" =>
reg_data_out <= slv_reg384;
when b"110000001" =>
reg_data_out <= slv_reg385;
when b"110000010" =>
reg_data_out <= slv_reg386;
when b"110000011" =>
reg_data_out <= slv_reg387;
when b"110000100" =>
reg_data_out <= slv_reg388;
when b"110000101" =>
reg_data_out <= slv_reg389;
when b"110000110" =>
reg_data_out <= slv_reg390;
when b"110000111" =>
reg_data_out <= slv_reg391;
when b"110001000" =>
reg_data_out <= slv_reg392;
when b"110001001" =>
reg_data_out <= slv_reg393;
when b"110001010" =>
reg_data_out <= slv_reg394;
when b"110001011" =>
reg_data_out <= slv_reg395;
when b"110001100" =>
reg_data_out <= slv_reg396;
when b"110001101" =>
reg_data_out <= slv_reg397;
when b"110001110" =>
reg_data_out <= slv_reg398;
when b"110001111" =>
reg_data_out <= slv_reg399;
when b"110010000" =>
reg_data_out <= slv_reg400;
when b"110010001" =>
reg_data_out <= slv_reg401;
when b"110010010" =>
reg_data_out <= slv_reg402;
when b"110010011" =>
reg_data_out <= slv_reg403;
when b"110010100" =>
reg_data_out <= slv_reg404;
when b"110010101" =>
reg_data_out <= slv_reg405;
when b"110010110" =>
reg_data_out <= slv_reg406;
when b"110010111" =>
reg_data_out <= slv_reg407;
when b"110011000" =>
reg_data_out <= slv_reg408;
when b"110011001" =>
reg_data_out <= slv_reg409;
when b"110011010" =>
reg_data_out <= slv_reg410;
when b"110011011" =>
reg_data_out <= slv_reg411;
when b"110011100" =>
reg_data_out <= slv_reg412;
when b"110011101" =>
reg_data_out <= slv_reg413;
when b"110011110" =>
reg_data_out <= slv_reg414;
when b"110011111" =>
reg_data_out <= slv_reg415;
when b"110100000" =>
reg_data_out <= slv_reg416;
when b"110100001" =>
reg_data_out <= slv_reg417;
when b"110100010" =>
reg_data_out <= slv_reg418;
when b"110100011" =>
reg_data_out <= slv_reg419;
when b"110100100" =>
reg_data_out <= slv_reg420;
when b"110100101" =>
reg_data_out <= slv_reg421;
when b"110100110" =>
reg_data_out <= slv_reg422;
when b"110100111" =>
reg_data_out <= slv_reg423;
when b"110101000" =>
reg_data_out <= slv_reg424;
when b"110101001" =>
reg_data_out <= slv_reg425;
when b"110101010" =>
reg_data_out <= slv_reg426;
when b"110101011" =>
reg_data_out <= slv_reg427;
when b"110101100" =>
reg_data_out <= slv_reg428;
when b"110101101" =>
reg_data_out <= slv_reg429;
when b"110101110" =>
reg_data_out <= slv_reg430;
when b"110101111" =>
reg_data_out <= slv_reg431;
when b"110110000" =>
reg_data_out <= slv_reg432;
when b"110110001" =>
reg_data_out <= slv_reg433;
when b"110110010" =>
reg_data_out <= slv_reg434;
when b"110110011" =>
reg_data_out <= slv_reg435;
when b"110110100" =>
reg_data_out <= slv_reg436;
when b"110110101" =>
reg_data_out <= slv_reg437;
when b"110110110" =>
reg_data_out <= slv_reg438;
when b"110110111" =>
reg_data_out <= slv_reg439;
when b"110111000" =>
reg_data_out <= slv_reg440;
when b"110111001" =>
reg_data_out <= slv_reg441;
when b"110111010" =>
reg_data_out <= slv_reg442;
when b"110111011" =>
reg_data_out <= slv_reg443;
when b"110111100" =>
reg_data_out <= slv_reg444;
when b"110111101" =>
reg_data_out <= slv_reg445;
when b"110111110" =>
reg_data_out <= slv_reg446;
when b"110111111" =>
reg_data_out <= slv_reg447;
when b"111000000" =>
reg_data_out <= slv_reg448;
when b"111000001" =>
reg_data_out <= slv_reg449;
when b"111000010" =>
reg_data_out <= slv_reg450;
when b"111000011" =>
reg_data_out <= slv_reg451;
when b"111000100" =>
reg_data_out <= slv_reg452;
when b"111000101" =>
reg_data_out <= slv_reg453;
when b"111000110" =>
reg_data_out <= slv_reg454;
when b"111000111" =>
reg_data_out <= slv_reg455;
when b"111001000" =>
reg_data_out <= slv_reg456;
when b"111001001" =>
reg_data_out <= slv_reg457;
when b"111001010" =>
reg_data_out <= slv_reg458;
when b"111001011" =>
reg_data_out <= slv_reg459;
when b"111001100" =>
reg_data_out <= slv_reg460;
when b"111001101" =>
reg_data_out <= slv_reg461;
when b"111001110" =>
reg_data_out <= slv_reg462;
when b"111001111" =>
reg_data_out <= slv_reg463;
when b"111010000" =>
reg_data_out <= slv_reg464;
when b"111010001" =>
reg_data_out <= slv_reg465;
when b"111010010" =>
reg_data_out <= slv_reg466;
when b"111010011" =>
reg_data_out <= slv_reg467;
when b"111010100" =>
reg_data_out <= slv_reg468;
when b"111010101" =>
reg_data_out <= slv_reg469;
when b"111010110" =>
reg_data_out <= slv_reg470;
when b"111010111" =>
reg_data_out <= slv_reg471;
when b"111011000" =>
reg_data_out <= slv_reg472;
when b"111011001" =>
reg_data_out <= slv_reg473;
when b"111011010" =>
reg_data_out <= slv_reg474;
when b"111011011" =>
reg_data_out <= slv_reg475;
when b"111011100" =>
reg_data_out <= slv_reg476;
when b"111011101" =>
reg_data_out <= slv_reg477;
when b"111011110" =>
reg_data_out <= slv_reg478;
when b"111011111" =>
reg_data_out <= slv_reg479;
when b"111100000" =>
reg_data_out <= slv_reg480;
when b"111100001" =>
reg_data_out <= slv_reg481;
when b"111100010" =>
reg_data_out <= slv_reg482;
when b"111100011" =>
reg_data_out <= slv_reg483;
when b"111100100" =>
reg_data_out <= slv_reg484;
when b"111100101" =>
reg_data_out <= slv_reg485;
when b"111100110" =>
reg_data_out <= slv_reg486;
when b"111100111" =>
reg_data_out <= slv_reg487;
when b"111101000" =>
reg_data_out <= slv_reg488;
when b"111101001" =>
reg_data_out <= slv_reg489;
when b"111101010" =>
reg_data_out <= slv_reg490;
when b"111101011" =>
reg_data_out <= slv_reg491;
when b"111101100" =>
reg_data_out <= slv_reg492;
when b"111101101" =>
reg_data_out <= slv_reg493;
when b"111101110" =>
reg_data_out <= slv_reg494;
when b"111101111" =>
reg_data_out <= slv_reg495;
when b"111110000" =>
reg_data_out <= slv_reg496;
when b"111110001" =>
reg_data_out <= slv_reg497;
when b"111110010" =>
reg_data_out <= slv_reg498;
when b"111110011" =>
reg_data_out <= slv_reg499;
when b"111110100" =>
reg_data_out <= slv_reg500;
when b"111110101" =>
reg_data_out <= slv_reg501;
when b"111110110" =>
reg_data_out <= slv_reg502;
when b"111110111" =>
reg_data_out <= slv_reg503;
when b"111111000" =>
reg_data_out <= slv_reg504;
when b"111111001" =>
reg_data_out <= slv_reg505;
when b"111111010" =>
reg_data_out <= slv_reg506;
when b"111111011" =>
reg_data_out <= slv_reg507;
when b"111111100" =>
reg_data_out <= slv_reg508;
when b"111111101" =>
reg_data_out <= slv_reg509;
when b"111111110" =>
reg_data_out <= slv_reg510;
when b"111111111" =>
reg_data_out <= slv_reg511;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End Pass-through architecture
|
bsd-3-clause
|
9eb715ccbf1c6f1979db70e93cbda4cf
| 0.520593 | 3.52701 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_auto_cc_0/mig_wrap_auto_cc_0_sim_netlist.vhdl
| 1 | 745,907 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
-- Date : Sun Mar 26 22:18:09 2017
-- Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top mig_wrap_auto_cc_0 -prefix
-- mig_wrap_auto_cc_0_ mig_wrap_auto_cc_0_sim_netlist.vhdl
-- Design : mig_wrap_auto_cc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_dmem is
port (
dout_i : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
end mig_wrap_auto_cc_0_dmem;
architecture STRUCTURE of mig_wrap_auto_cc_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(1 downto 0),
DIB(1 downto 0) => DI(3 downto 2),
DIC(1 downto 0) => DI(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(13 downto 12),
DIB(1 downto 0) => DI(15 downto 14),
DIC(1 downto 0) => DI(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(19 downto 18),
DIB(1 downto 0) => DI(21 downto 20),
DIC(1 downto 0) => DI(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(25 downto 24),
DIB(1 downto 0) => DI(27 downto 26),
DIC(1 downto 0) => DI(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(31 downto 30),
DIB(1 downto 0) => DI(33 downto 32),
DIC(1 downto 0) => DI(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(37 downto 36),
DIB(1 downto 0) => DI(39 downto 38),
DIC(1 downto 0) => DI(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(43 downto 42),
DIB(1 downto 0) => DI(45 downto 44),
DIC(1 downto 0) => DI(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(49 downto 48),
DIB(1 downto 0) => DI(51 downto 50),
DIC(1 downto 0) => DI(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(55 downto 54),
DIB(1 downto 0) => DI(57 downto 56),
DIC(1 downto 0) => DI(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(61 downto 60),
DIB(1 downto 0) => DI(63 downto 62),
DIC(1) => '0',
DIC(0) => DI(64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_64_n_0,
DOA(0) => RAM_reg_0_15_60_64_n_1,
DOB(1) => RAM_reg_0_15_60_64_n_2,
DOB(0) => RAM_reg_0_15_60_64_n_3,
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => RAM_reg_0_15_60_64_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(7 downto 6),
DIB(1 downto 0) => DI(9 downto 8),
DIC(1 downto 0) => DI(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => dout_i(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => dout_i(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => dout_i(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => dout_i(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => dout_i(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => dout_i(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => dout_i(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => dout_i(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => dout_i(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => dout_i(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => dout_i(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => dout_i(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => dout_i(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => dout_i(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => dout_i(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => dout_i(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => dout_i(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => dout_i(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => dout_i(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => dout_i(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => dout_i(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => dout_i(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => dout_i(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => dout_i(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => dout_i(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => dout_i(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => dout_i(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => dout_i(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => dout_i(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => dout_i(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => dout_i(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => dout_i(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => dout_i(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => dout_i(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => dout_i(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => dout_i(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => dout_i(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => dout_i(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => dout_i(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => dout_i(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => dout_i(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => dout_i(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => dout_i(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => dout_i(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => dout_i(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => dout_i(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => dout_i(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => dout_i(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => dout_i(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => dout_i(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => dout_i(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => dout_i(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_1,
Q => dout_i(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_0,
Q => dout_i(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_3,
Q => dout_i(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_2,
Q => dout_i(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_5,
Q => dout_i(64),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => dout_i(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => dout_i(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => dout_i(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => dout_i(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_dmem_81 is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_dmem_81 : entity is "dmem";
end mig_wrap_auto_cc_0_dmem_81;
architecture STRUCTURE of mig_wrap_auto_cc_0_dmem_81 is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(1 downto 0),
DIB(1 downto 0) => I123(3 downto 2),
DIC(1 downto 0) => I123(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(13 downto 12),
DIB(1 downto 0) => I123(15 downto 14),
DIC(1 downto 0) => I123(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(19 downto 18),
DIB(1 downto 0) => I123(21 downto 20),
DIC(1 downto 0) => I123(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(25 downto 24),
DIB(1 downto 0) => I123(27 downto 26),
DIC(1 downto 0) => I123(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(31 downto 30),
DIB(1 downto 0) => I123(33 downto 32),
DIC(1 downto 0) => I123(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(37 downto 36),
DIB(1 downto 0) => I123(39 downto 38),
DIC(1 downto 0) => I123(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(43 downto 42),
DIB(1 downto 0) => I123(45 downto 44),
DIC(1 downto 0) => I123(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(49 downto 48),
DIB(1 downto 0) => I123(51 downto 50),
DIC(1 downto 0) => I123(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(55 downto 54),
DIB(1 downto 0) => I123(57 downto 56),
DIC(1 downto 0) => I123(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(61 downto 60),
DIB(1 downto 0) => I123(63 downto 62),
DIC(1) => '0',
DIC(0) => I123(64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_64_n_0,
DOA(0) => RAM_reg_0_15_60_64_n_1,
DOB(1) => RAM_reg_0_15_60_64_n_2,
DOB(0) => RAM_reg_0_15_60_64_n_3,
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => RAM_reg_0_15_60_64_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(7 downto 6),
DIB(1 downto 0) => I123(9 downto 8),
DIC(1 downto 0) => I123(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => Q(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => Q(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_1,
Q => Q(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_0,
Q => Q(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_3,
Q => Q(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_2,
Q => Q(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_5,
Q => Q(64),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_dmem__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 36 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_dmem__parameterized0\ : entity is "dmem";
end \mig_wrap_auto_cc_0_dmem__parameterized0\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_dmem__parameterized0\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_36_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_36 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(1 downto 0),
DIB(1 downto 0) => I115(3 downto 2),
DIC(1 downto 0) => I115(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(13 downto 12),
DIB(1 downto 0) => I115(15 downto 14),
DIC(1 downto 0) => I115(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(19 downto 18),
DIB(1 downto 0) => I115(21 downto 20),
DIC(1 downto 0) => I115(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(25 downto 24),
DIB(1 downto 0) => I115(27 downto 26),
DIC(1 downto 0) => I115(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(31 downto 30),
DIB(1 downto 0) => I115(33 downto 32),
DIC(1 downto 0) => I115(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_36: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1) => '0',
DIA(0) => I115(36),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED(1),
DOA(0) => RAM_reg_0_15_36_36_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(7 downto 6),
DIB(1 downto 0) => I115(9 downto 8),
DIC(1 downto 0) => I115(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_36_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_dmem__parameterized1\ is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_dmem__parameterized1\ : entity is "dmem";
end \mig_wrap_auto_cc_0_dmem__parameterized1\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_dmem__parameterized1\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => m_axi_bresp(1 downto 0),
DIB(1 downto 0) => m_axi_bid(1 downto 0),
DIC(1 downto 0) => m_axi_bid(3 downto 2),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_dmem__parameterized2\ is
port (
Q : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_dmem__parameterized2\ : entity is "dmem";
end \mig_wrap_auto_cc_0_dmem__parameterized2\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_dmem__parameterized2\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_38 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(1 downto 0),
DIB(1 downto 0) => I127(3 downto 2),
DIC(1 downto 0) => I127(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(13 downto 12),
DIB(1 downto 0) => I127(15 downto 14),
DIC(1 downto 0) => I127(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(19 downto 18),
DIB(1 downto 0) => I127(21 downto 20),
DIC(1 downto 0) => I127(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(25 downto 24),
DIB(1 downto 0) => I127(27 downto 26),
DIC(1 downto 0) => I127(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(31 downto 30),
DIB(1 downto 0) => I127(33 downto 32),
DIC(1 downto 0) => I127(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_36_38: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(37 downto 36),
DIB(1) => '0',
DIB(0) => I127(38),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_38_n_0,
DOA(0) => RAM_reg_0_15_36_38_n_1,
DOB(1) => NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED(1),
DOB(0) => RAM_reg_0_15_36_38_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(7 downto 6),
DIB(1 downto 0) => I127(9 downto 8),
DIC(1 downto 0) => I127(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_rd_bin_cntr;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__2\ : label is "soft_lutpair22";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__6\(0)
);
\gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__6\(1)
);
\gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__6\(2)
);
\gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__6\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__6\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__2_n_0\,
I1 => \ram_empty_i_i_3__2_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__2_n_0\
);
\ram_empty_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_bin_cntr_20 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_bin_cntr_20 : entity is "rd_bin_cntr";
end mig_wrap_auto_cc_0_rd_bin_cntr_20;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_bin_cntr_20 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__0\ : label is "soft_lutpair17";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => \ram_empty_i_i_3__0_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_bin_cntr_41 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_bin_cntr_41 : entity is "rd_bin_cntr";
end mig_wrap_auto_cc_0_rd_bin_cntr_41;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_bin_cntr_41 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of ram_empty_i_i_2 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of ram_empty_i_i_3 : label is "soft_lutpair12";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => plusOp(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => ram_empty_i_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_bin_cntr_62 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_bin_cntr_62 : entity is "rd_bin_cntr";
end mig_wrap_auto_cc_0_rd_bin_cntr_62;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_bin_cntr_62 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__3\ : label is "soft_lutpair7";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__8\(0)
);
\gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__8\(1)
);
\gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__8\(2)
);
\gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__8\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__8\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__3_n_0\,
I1 => \ram_empty_i_i_3__3_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__3_n_0\
);
\ram_empty_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_bin_cntr_86 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_bin_cntr_86 : entity is "rd_bin_cntr";
end mig_wrap_auto_cc_0_rd_bin_cntr_86;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_bin_cntr_86 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__1\ : label is "soft_lutpair2";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__2\(0)
);
\gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__2\(1)
);
\gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__2\(2)
);
\gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__2\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__2\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__1_n_0\,
I1 => \ram_empty_i_i_3__1_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__1_n_0\
);
\ram_empty_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_fwft is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_rd_fwft;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => \goreg_dm.dout_i_reg[5]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_bready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_bvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_fwft_18 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[36]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_fwft_18 : entity is "rd_fwft";
end mig_wrap_auto_cc_0_rd_fwft_18;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_fwft_18 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[36]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => \goreg_dm.dout_i_reg[36]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_wready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_wvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_wvalid
);
\ram_empty_i_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_fwft_39 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_fwft_39 : entity is "rd_fwft";
end mig_wrap_auto_cc_0_rd_fwft_39;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_fwft_39 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[64]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_awready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_awvalid
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_fwft_60 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_fwft_60 : entity is "rd_fwft";
end mig_wrap_auto_cc_0_rd_fwft_60;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_fwft_60 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[38]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => \goreg_dm.dout_i_reg[38]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_rready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_fwft_84 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_fwft_84 : entity is "rd_fwft";
end mig_wrap_auto_cc_0_rd_fwft_84;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_fwft_84 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[64]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_arready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_arvalid
);
\ram_empty_i_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_rd_status_flags_as;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_status_flags_as_19 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_status_flags_as_19 : entity is "rd_status_flags_as";
end mig_wrap_auto_cc_0_rd_status_flags_as_19;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_status_flags_as_19 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_status_flags_as_40 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_status_flags_as_40 : entity is "rd_status_flags_as";
end mig_wrap_auto_cc_0_rd_status_flags_as_40;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_status_flags_as_40 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_status_flags_as_61 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_status_flags_as_61 : entity is "rd_status_flags_as";
end mig_wrap_auto_cc_0_rd_status_flags_as_61;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_status_flags_as_61 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_status_flags_as_85 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_status_flags_as_85 : entity is "rd_status_flags_as";
end mig_wrap_auto_cc_0_rd_status_flags_as_85;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_status_flags_as_85 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
end mig_wrap_auto_cc_0_synchronizer_ff;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_1 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_1;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_10 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_10 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_10;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_11 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_11 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_11;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_11 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_12 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_12 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_12;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_12 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_13 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_13 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_13;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_13 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_14 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_14 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_14;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_14 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_15 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_15 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_15;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_15 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_2 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_2 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_2;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_3 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_3 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_3;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_31 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_31 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_31;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_31 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_32 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_32 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_32;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_32 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_33 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_33 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_33;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_33 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_34 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_34 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_34;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_34 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_35 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_35 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_35;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_35 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_36 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_36 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_36;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_36 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_4 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_4 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_4;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_5 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_5 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_5;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_52 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_52 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_52;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_52 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_53 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_53 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_53;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_53 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_54 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_54 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_54;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_54 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_55 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_55 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_55;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_55 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_56 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_56 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_56;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_56 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_57 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_57 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_57;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_57 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_75 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_75 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_75;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_75 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_76 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_76 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_76;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_76 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_77 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_77 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_77;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_77 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_78 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_78 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_78;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_78 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_79 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_79 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_79;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_79 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_synchronizer_ff_80 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_synchronizer_ff_80 : entity is "synchronizer_ff";
end mig_wrap_auto_cc_0_synchronizer_ff_80;
architecture STRUCTURE of mig_wrap_auto_cc_0_synchronizer_ff_80 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_21\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_21\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_21\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_21\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_42\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_42\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_42\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_42\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_63\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_63\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_63\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_63\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_87\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_87\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_87\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_87\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_22\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_22\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_22\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_22\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_43\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_43\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_43\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_43\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_64\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_64\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_64\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_64\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_88\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_88\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_88\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_88\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_23\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_23\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_23\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_23\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_44\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_44\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_44\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_44\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_65\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_65\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_65\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_65\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_89\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_89\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_89\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_89\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_24\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_24\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_24\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_24\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_45\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_45\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_45\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_45\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_66\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_66\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_66\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_66\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_90\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_90\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_90\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_90\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_25\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_25\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_25\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_25\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_46\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_46\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_46\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_46\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_67\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_67\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_67\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_67\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_91\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_91\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_91\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_91\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_26\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_26\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_26\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_26\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_47\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_47\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_47\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_47\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_68\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_68\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_68\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_68\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_92\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_92\ : entity is "synchronizer_ff";
end \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_92\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_92\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_wr_bin_cntr;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair24";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_bin_cntr_17 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_bin_cntr_17 : entity is "wr_bin_cntr";
end mig_wrap_auto_cc_0_wr_bin_cntr_17;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_bin_cntr_17 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__2\ : label is "soft_lutpair19";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__5\(0)
);
\gic0.gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__5\(1)
);
\gic0.gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__5\(2)
);
\gic0.gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__5\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__5\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_bin_cntr_38 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_bin_cntr_38 : entity is "wr_bin_cntr";
end mig_wrap_auto_cc_0_wr_bin_cntr_38;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_bin_cntr_38 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__1\ : label is "soft_lutpair14";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__4\(0)
);
\gic0.gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__4\(1)
);
\gic0.gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__4\(2)
);
\gic0.gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__4\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__4\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_bin_cntr_59 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_bin_cntr_59 : entity is "wr_bin_cntr";
end mig_wrap_auto_cc_0_wr_bin_cntr_59;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_bin_cntr_59 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__0\ : label is "soft_lutpair9";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__3\(0)
);
\gic0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__3\(1)
);
\gic0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__3\(2)
);
\gic0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__3\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__3\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_bin_cntr_83 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_bin_cntr_83 : entity is "wr_bin_cntr";
end mig_wrap_auto_cc_0_wr_bin_cntr_83;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_bin_cntr_83 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__3\ : label is "soft_lutpair4";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__7\(0)
);
\gic0.gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__7\(1)
);
\gic0.gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__7\(2)
);
\gic0.gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__7\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__7\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_status_flags_as is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_wr_status_flags_as;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_bvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_bready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_bready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_bvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_status_flags_as_16 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_status_flags_as_16 : entity is "wr_status_flags_as";
end mig_wrap_auto_cc_0_wr_status_flags_as_16;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_status_flags_as_16 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_wvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_wready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_wready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_status_flags_as_37 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_status_flags_as_37 : entity is "wr_status_flags_as";
end mig_wrap_auto_cc_0_wr_status_flags_as_37;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_status_flags_as_37 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_awvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_awready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_awready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_status_flags_as_58 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_status_flags_as_58 : entity is "wr_status_flags_as";
end mig_wrap_auto_cc_0_wr_status_flags_as_58;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_status_flags_as_58 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_rready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_rready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_rvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_status_flags_as_82 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_status_flags_as_82 : entity is "wr_status_flags_as";
end mig_wrap_auto_cc_0_wr_status_flags_as_82;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_status_flags_as_82 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_arvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_arready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_clk_x_pntrs;
architecture STRUCTURE of mig_wrap_auto_cc_0_clk_x_pntrs is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair20";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized2\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized4\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized5\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => ram_full_i_i_4_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => ram_full_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_clk_x_pntrs_27 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_clk_x_pntrs_27 : entity is "clk_x_pntrs";
end mig_wrap_auto_cc_0_clk_x_pntrs_27;
architecture STRUCTURE of mig_wrap_auto_cc_0_clk_x_pntrs_27 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__1_n_0\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair10";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_42\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_43\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_44\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_45\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_46\
port map (
D(0) => p_0_out,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_47\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out_1(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out_1(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out_1(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__1_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__1_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_2__1_n_0\
);
\ram_full_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_4__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_clk_x_pntrs_48 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_clk_x_pntrs_48 : entity is "clk_x_pntrs";
end mig_wrap_auto_cc_0_clk_x_pntrs_48;
architecture STRUCTURE of mig_wrap_auto_cc_0_clk_x_pntrs_48 is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair5";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_63\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_64\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_65\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_66\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_67\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_68\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__0_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__0_n_0\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_clk_x_pntrs_6 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_clk_x_pntrs_6 : entity is "clk_x_pntrs";
end mig_wrap_auto_cc_0_clk_x_pntrs_6;
architecture STRUCTURE of mig_wrap_auto_cc_0_clk_x_pntrs_6 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair15";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_21\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_22\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_23\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_24\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_25\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_26\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__2_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__2_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__2_n_0\
);
\ram_full_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_clk_x_pntrs_70 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_clk_x_pntrs_70 : entity is "clk_x_pntrs";
end mig_wrap_auto_cc_0_clk_x_pntrs_70;
architecture STRUCTURE of mig_wrap_auto_cc_0_clk_x_pntrs_70 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair0";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized0_87\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized1_88\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized2_89\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized3_90\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized4_91\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\mig_wrap_auto_cc_0_synchronizer_ff__parameterized5_92\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__3_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__3_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__3_n_0\
);
\ram_full_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_memory is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_memory;
architecture STRUCTURE of mig_wrap_auto_cc_0_memory is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.mig_wrap_auto_cc_0_dmem
port map (
DI(64 downto 0) => DI(64 downto 0),
dout_i(64) => \gdm.dm_gen.dm_n_0\,
dout_i(63) => \gdm.dm_gen.dm_n_1\,
dout_i(62) => \gdm.dm_gen.dm_n_2\,
dout_i(61) => \gdm.dm_gen.dm_n_3\,
dout_i(60) => \gdm.dm_gen.dm_n_4\,
dout_i(59) => \gdm.dm_gen.dm_n_5\,
dout_i(58) => \gdm.dm_gen.dm_n_6\,
dout_i(57) => \gdm.dm_gen.dm_n_7\,
dout_i(56) => \gdm.dm_gen.dm_n_8\,
dout_i(55) => \gdm.dm_gen.dm_n_9\,
dout_i(54) => \gdm.dm_gen.dm_n_10\,
dout_i(53) => \gdm.dm_gen.dm_n_11\,
dout_i(52) => \gdm.dm_gen.dm_n_12\,
dout_i(51) => \gdm.dm_gen.dm_n_13\,
dout_i(50) => \gdm.dm_gen.dm_n_14\,
dout_i(49) => \gdm.dm_gen.dm_n_15\,
dout_i(48) => \gdm.dm_gen.dm_n_16\,
dout_i(47) => \gdm.dm_gen.dm_n_17\,
dout_i(46) => \gdm.dm_gen.dm_n_18\,
dout_i(45) => \gdm.dm_gen.dm_n_19\,
dout_i(44) => \gdm.dm_gen.dm_n_20\,
dout_i(43) => \gdm.dm_gen.dm_n_21\,
dout_i(42) => \gdm.dm_gen.dm_n_22\,
dout_i(41) => \gdm.dm_gen.dm_n_23\,
dout_i(40) => \gdm.dm_gen.dm_n_24\,
dout_i(39) => \gdm.dm_gen.dm_n_25\,
dout_i(38) => \gdm.dm_gen.dm_n_26\,
dout_i(37) => \gdm.dm_gen.dm_n_27\,
dout_i(36) => \gdm.dm_gen.dm_n_28\,
dout_i(35) => \gdm.dm_gen.dm_n_29\,
dout_i(34) => \gdm.dm_gen.dm_n_30\,
dout_i(33) => \gdm.dm_gen.dm_n_31\,
dout_i(32) => \gdm.dm_gen.dm_n_32\,
dout_i(31) => \gdm.dm_gen.dm_n_33\,
dout_i(30) => \gdm.dm_gen.dm_n_34\,
dout_i(29) => \gdm.dm_gen.dm_n_35\,
dout_i(28) => \gdm.dm_gen.dm_n_36\,
dout_i(27) => \gdm.dm_gen.dm_n_37\,
dout_i(26) => \gdm.dm_gen.dm_n_38\,
dout_i(25) => \gdm.dm_gen.dm_n_39\,
dout_i(24) => \gdm.dm_gen.dm_n_40\,
dout_i(23) => \gdm.dm_gen.dm_n_41\,
dout_i(22) => \gdm.dm_gen.dm_n_42\,
dout_i(21) => \gdm.dm_gen.dm_n_43\,
dout_i(20) => \gdm.dm_gen.dm_n_44\,
dout_i(19) => \gdm.dm_gen.dm_n_45\,
dout_i(18) => \gdm.dm_gen.dm_n_46\,
dout_i(17) => \gdm.dm_gen.dm_n_47\,
dout_i(16) => \gdm.dm_gen.dm_n_48\,
dout_i(15) => \gdm.dm_gen.dm_n_49\,
dout_i(14) => \gdm.dm_gen.dm_n_50\,
dout_i(13) => \gdm.dm_gen.dm_n_51\,
dout_i(12) => \gdm.dm_gen.dm_n_52\,
dout_i(11) => \gdm.dm_gen.dm_n_53\,
dout_i(10) => \gdm.dm_gen.dm_n_54\,
dout_i(9) => \gdm.dm_gen.dm_n_55\,
dout_i(8) => \gdm.dm_gen.dm_n_56\,
dout_i(7) => \gdm.dm_gen.dm_n_57\,
dout_i(6) => \gdm.dm_gen.dm_n_58\,
dout_i(5) => \gdm.dm_gen.dm_n_59\,
dout_i(4) => \gdm.dm_gen.dm_n_60\,
dout_i(3) => \gdm.dm_gen.dm_n_61\,
dout_i(2) => \gdm.dm_gen.dm_n_62\,
dout_i(1) => \gdm.dm_gen.dm_n_63\,
dout_i(0) => \gdm.dm_gen.dm_n_64\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_64\,
Q => Q(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_54\,
Q => Q(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_53\,
Q => Q(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_52\,
Q => Q(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_51\,
Q => Q(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_50\,
Q => Q(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_49\,
Q => Q(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_48\,
Q => Q(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_47\,
Q => Q(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_46\,
Q => Q(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_45\,
Q => Q(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_63\,
Q => Q(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_44\,
Q => Q(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_43\,
Q => Q(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_42\,
Q => Q(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_41\,
Q => Q(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_40\,
Q => Q(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_39\,
Q => Q(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_38\,
Q => Q(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_37\,
Q => Q(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_36\,
Q => Q(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_35\,
Q => Q(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_62\,
Q => Q(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_34\,
Q => Q(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_33\,
Q => Q(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_32\,
Q => Q(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_31\,
Q => Q(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_30\,
Q => Q(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_29\,
Q => Q(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_28\,
Q => Q(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_27\,
Q => Q(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_26\,
Q => Q(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_25\,
Q => Q(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_61\,
Q => Q(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_24\,
Q => Q(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_23\,
Q => Q(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_22\,
Q => Q(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_21\,
Q => Q(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_20\,
Q => Q(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_19\,
Q => Q(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_18\,
Q => Q(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_17\,
Q => Q(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_16\,
Q => Q(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_15\,
Q => Q(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_60\,
Q => Q(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_14\,
Q => Q(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_13\,
Q => Q(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_12\,
Q => Q(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_11\,
Q => Q(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_10\,
Q => Q(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_9\,
Q => Q(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_8\,
Q => Q(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_7\,
Q => Q(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_6\,
Q => Q(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_5\,
Q => Q(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_59\,
Q => Q(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_4\,
Q => Q(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_3\,
Q => Q(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_2\,
Q => Q(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_1\,
Q => Q(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_0\,
Q => Q(64),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_58\,
Q => Q(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_57\,
Q => Q(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_56\,
Q => Q(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_55\,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_memory_73 is
port (
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_memory_73 : entity is "memory";
end mig_wrap_auto_cc_0_memory_73;
architecture STRUCTURE of mig_wrap_auto_cc_0_memory_73 is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.mig_wrap_auto_cc_0_dmem_81
port map (
E(0) => E(0),
I123(64 downto 0) => I123(64 downto 0),
Q(64) => \gdm.dm_gen.dm_n_0\,
Q(63) => \gdm.dm_gen.dm_n_1\,
Q(62) => \gdm.dm_gen.dm_n_2\,
Q(61) => \gdm.dm_gen.dm_n_3\,
Q(60) => \gdm.dm_gen.dm_n_4\,
Q(59) => \gdm.dm_gen.dm_n_5\,
Q(58) => \gdm.dm_gen.dm_n_6\,
Q(57) => \gdm.dm_gen.dm_n_7\,
Q(56) => \gdm.dm_gen.dm_n_8\,
Q(55) => \gdm.dm_gen.dm_n_9\,
Q(54) => \gdm.dm_gen.dm_n_10\,
Q(53) => \gdm.dm_gen.dm_n_11\,
Q(52) => \gdm.dm_gen.dm_n_12\,
Q(51) => \gdm.dm_gen.dm_n_13\,
Q(50) => \gdm.dm_gen.dm_n_14\,
Q(49) => \gdm.dm_gen.dm_n_15\,
Q(48) => \gdm.dm_gen.dm_n_16\,
Q(47) => \gdm.dm_gen.dm_n_17\,
Q(46) => \gdm.dm_gen.dm_n_18\,
Q(45) => \gdm.dm_gen.dm_n_19\,
Q(44) => \gdm.dm_gen.dm_n_20\,
Q(43) => \gdm.dm_gen.dm_n_21\,
Q(42) => \gdm.dm_gen.dm_n_22\,
Q(41) => \gdm.dm_gen.dm_n_23\,
Q(40) => \gdm.dm_gen.dm_n_24\,
Q(39) => \gdm.dm_gen.dm_n_25\,
Q(38) => \gdm.dm_gen.dm_n_26\,
Q(37) => \gdm.dm_gen.dm_n_27\,
Q(36) => \gdm.dm_gen.dm_n_28\,
Q(35) => \gdm.dm_gen.dm_n_29\,
Q(34) => \gdm.dm_gen.dm_n_30\,
Q(33) => \gdm.dm_gen.dm_n_31\,
Q(32) => \gdm.dm_gen.dm_n_32\,
Q(31) => \gdm.dm_gen.dm_n_33\,
Q(30) => \gdm.dm_gen.dm_n_34\,
Q(29) => \gdm.dm_gen.dm_n_35\,
Q(28) => \gdm.dm_gen.dm_n_36\,
Q(27) => \gdm.dm_gen.dm_n_37\,
Q(26) => \gdm.dm_gen.dm_n_38\,
Q(25) => \gdm.dm_gen.dm_n_39\,
Q(24) => \gdm.dm_gen.dm_n_40\,
Q(23) => \gdm.dm_gen.dm_n_41\,
Q(22) => \gdm.dm_gen.dm_n_42\,
Q(21) => \gdm.dm_gen.dm_n_43\,
Q(20) => \gdm.dm_gen.dm_n_44\,
Q(19) => \gdm.dm_gen.dm_n_45\,
Q(18) => \gdm.dm_gen.dm_n_46\,
Q(17) => \gdm.dm_gen.dm_n_47\,
Q(16) => \gdm.dm_gen.dm_n_48\,
Q(15) => \gdm.dm_gen.dm_n_49\,
Q(14) => \gdm.dm_gen.dm_n_50\,
Q(13) => \gdm.dm_gen.dm_n_51\,
Q(12) => \gdm.dm_gen.dm_n_52\,
Q(11) => \gdm.dm_gen.dm_n_53\,
Q(10) => \gdm.dm_gen.dm_n_54\,
Q(9) => \gdm.dm_gen.dm_n_55\,
Q(8) => \gdm.dm_gen.dm_n_56\,
Q(7) => \gdm.dm_gen.dm_n_57\,
Q(6) => \gdm.dm_gen.dm_n_58\,
Q(5) => \gdm.dm_gen.dm_n_59\,
Q(4) => \gdm.dm_gen.dm_n_60\,
Q(3) => \gdm.dm_gen.dm_n_61\,
Q(2) => \gdm.dm_gen.dm_n_62\,
Q(1) => \gdm.dm_gen.dm_n_63\,
Q(0) => \gdm.dm_gen.dm_n_64\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_64\,
Q => \m_axi_arid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \m_axi_arid[3]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \m_axi_arid[3]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \m_axi_arid[3]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \m_axi_arid[3]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \m_axi_arid[3]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \m_axi_arid[3]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \m_axi_arid[3]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \m_axi_arid[3]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \m_axi_arid[3]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \m_axi_arid[3]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_63\,
Q => \m_axi_arid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \m_axi_arid[3]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \m_axi_arid[3]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \m_axi_arid[3]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \m_axi_arid[3]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \m_axi_arid[3]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \m_axi_arid[3]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \m_axi_arid[3]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \m_axi_arid[3]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_arid[3]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_arid[3]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_62\,
Q => \m_axi_arid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_arid[3]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_arid[3]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_arid[3]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_arid[3]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_arid[3]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_arid[3]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_arid[3]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_arid[3]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_arid[3]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_arid[3]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_61\,
Q => \m_axi_arid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_arid[3]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_arid[3]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_arid[3]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_arid[3]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_arid[3]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_arid[3]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_arid[3]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_arid[3]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_arid[3]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_arid[3]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_60\,
Q => \m_axi_arid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_arid[3]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_arid[3]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_arid[3]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_arid[3]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_arid[3]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_arid[3]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_arid[3]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_arid[3]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_arid[3]\(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_arid[3]\(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_59\,
Q => \m_axi_arid[3]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_arid[3]\(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_arid[3]\(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_arid[3]\(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_arid[3]\(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_arid[3]\(64),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_58\,
Q => \m_axi_arid[3]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \m_axi_arid[3]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \m_axi_arid[3]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \m_axi_arid[3]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_memory__parameterized0\ is
port (
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_memory__parameterized0\ : entity is "memory";
end \mig_wrap_auto_cc_0_memory__parameterized0\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_memory__parameterized0\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\mig_wrap_auto_cc_0_dmem__parameterized0\
port map (
E(0) => E(0),
I115(36 downto 0) => I115(36 downto 0),
Q(36) => \gdm.dm_gen.dm_n_0\,
Q(35) => \gdm.dm_gen.dm_n_1\,
Q(34) => \gdm.dm_gen.dm_n_2\,
Q(33) => \gdm.dm_gen.dm_n_3\,
Q(32) => \gdm.dm_gen.dm_n_4\,
Q(31) => \gdm.dm_gen.dm_n_5\,
Q(30) => \gdm.dm_gen.dm_n_6\,
Q(29) => \gdm.dm_gen.dm_n_7\,
Q(28) => \gdm.dm_gen.dm_n_8\,
Q(27) => \gdm.dm_gen.dm_n_9\,
Q(26) => \gdm.dm_gen.dm_n_10\,
Q(25) => \gdm.dm_gen.dm_n_11\,
Q(24) => \gdm.dm_gen.dm_n_12\,
Q(23) => \gdm.dm_gen.dm_n_13\,
Q(22) => \gdm.dm_gen.dm_n_14\,
Q(21) => \gdm.dm_gen.dm_n_15\,
Q(20) => \gdm.dm_gen.dm_n_16\,
Q(19) => \gdm.dm_gen.dm_n_17\,
Q(18) => \gdm.dm_gen.dm_n_18\,
Q(17) => \gdm.dm_gen.dm_n_19\,
Q(16) => \gdm.dm_gen.dm_n_20\,
Q(15) => \gdm.dm_gen.dm_n_21\,
Q(14) => \gdm.dm_gen.dm_n_22\,
Q(13) => \gdm.dm_gen.dm_n_23\,
Q(12) => \gdm.dm_gen.dm_n_24\,
Q(11) => \gdm.dm_gen.dm_n_25\,
Q(10) => \gdm.dm_gen.dm_n_26\,
Q(9) => \gdm.dm_gen.dm_n_27\,
Q(8) => \gdm.dm_gen.dm_n_28\,
Q(7) => \gdm.dm_gen.dm_n_29\,
Q(6) => \gdm.dm_gen.dm_n_30\,
Q(5) => \gdm.dm_gen.dm_n_31\,
Q(4) => \gdm.dm_gen.dm_n_32\,
Q(3) => \gdm.dm_gen.dm_n_33\,
Q(2) => \gdm.dm_gen.dm_n_34\,
Q(1) => \gdm.dm_gen.dm_n_35\,
Q(0) => \gdm.dm_gen.dm_n_36\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_wdata[31]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_wdata[31]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_wdata[31]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_wdata[31]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_wdata[31]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_wdata[31]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_wdata[31]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_wdata[31]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_wdata[31]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_wdata[31]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_wdata[31]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_wdata[31]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_wdata[31]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_wdata[31]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_wdata[31]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_wdata[31]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_wdata[31]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_wdata[31]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_wdata[31]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_wdata[31]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_wdata[31]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_wdata[31]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_wdata[31]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_wdata[31]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_wdata[31]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_wdata[31]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_wdata[31]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_wdata[31]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_wdata[31]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_wdata[31]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_wdata[31]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_wdata[31]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_wdata[31]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_wdata[31]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_wdata[31]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_wdata[31]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_wdata[31]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_memory__parameterized1\ is
port (
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_memory__parameterized1\ : entity is "memory";
end \mig_wrap_auto_cc_0_memory__parameterized1\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_memory__parameterized1\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\mig_wrap_auto_cc_0_dmem__parameterized1\
port map (
E(0) => E(0),
Q(5) => \gdm.dm_gen.dm_n_0\,
Q(4) => \gdm.dm_gen.dm_n_1\,
Q(3) => \gdm.dm_gen.dm_n_2\,
Q(2) => \gdm.dm_gen.dm_n_3\,
Q(1) => \gdm.dm_gen.dm_n_4\,
Q(0) => \gdm.dm_gen.dm_n_5\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_bid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_bid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_bid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_bid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_bid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_bid[3]\(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_memory__parameterized2\ is
port (
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_memory__parameterized2\ : entity is "memory";
end \mig_wrap_auto_cc_0_memory__parameterized2\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_memory__parameterized2\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\mig_wrap_auto_cc_0_dmem__parameterized2\
port map (
E(0) => E(0),
I127(38 downto 0) => I127(38 downto 0),
Q(38) => \gdm.dm_gen.dm_n_0\,
Q(37) => \gdm.dm_gen.dm_n_1\,
Q(36) => \gdm.dm_gen.dm_n_2\,
Q(35) => \gdm.dm_gen.dm_n_3\,
Q(34) => \gdm.dm_gen.dm_n_4\,
Q(33) => \gdm.dm_gen.dm_n_5\,
Q(32) => \gdm.dm_gen.dm_n_6\,
Q(31) => \gdm.dm_gen.dm_n_7\,
Q(30) => \gdm.dm_gen.dm_n_8\,
Q(29) => \gdm.dm_gen.dm_n_9\,
Q(28) => \gdm.dm_gen.dm_n_10\,
Q(27) => \gdm.dm_gen.dm_n_11\,
Q(26) => \gdm.dm_gen.dm_n_12\,
Q(25) => \gdm.dm_gen.dm_n_13\,
Q(24) => \gdm.dm_gen.dm_n_14\,
Q(23) => \gdm.dm_gen.dm_n_15\,
Q(22) => \gdm.dm_gen.dm_n_16\,
Q(21) => \gdm.dm_gen.dm_n_17\,
Q(20) => \gdm.dm_gen.dm_n_18\,
Q(19) => \gdm.dm_gen.dm_n_19\,
Q(18) => \gdm.dm_gen.dm_n_20\,
Q(17) => \gdm.dm_gen.dm_n_21\,
Q(16) => \gdm.dm_gen.dm_n_22\,
Q(15) => \gdm.dm_gen.dm_n_23\,
Q(14) => \gdm.dm_gen.dm_n_24\,
Q(13) => \gdm.dm_gen.dm_n_25\,
Q(12) => \gdm.dm_gen.dm_n_26\,
Q(11) => \gdm.dm_gen.dm_n_27\,
Q(10) => \gdm.dm_gen.dm_n_28\,
Q(9) => \gdm.dm_gen.dm_n_29\,
Q(8) => \gdm.dm_gen.dm_n_30\,
Q(7) => \gdm.dm_gen.dm_n_31\,
Q(6) => \gdm.dm_gen.dm_n_32\,
Q(5) => \gdm.dm_gen.dm_n_33\,
Q(4) => \gdm.dm_gen.dm_n_34\,
Q(3) => \gdm.dm_gen.dm_n_35\,
Q(2) => \gdm.dm_gen.dm_n_36\,
Q(1) => \gdm.dm_gen.dm_n_37\,
Q(0) => \gdm.dm_gen.dm_n_38\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \s_axi_rid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \s_axi_rid[3]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \s_axi_rid[3]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \s_axi_rid[3]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \s_axi_rid[3]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \s_axi_rid[3]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \s_axi_rid[3]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \s_axi_rid[3]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \s_axi_rid[3]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \s_axi_rid[3]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \s_axi_rid[3]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \s_axi_rid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \s_axi_rid[3]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \s_axi_rid[3]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \s_axi_rid[3]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \s_axi_rid[3]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \s_axi_rid[3]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \s_axi_rid[3]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \s_axi_rid[3]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \s_axi_rid[3]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \s_axi_rid[3]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \s_axi_rid[3]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \s_axi_rid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \s_axi_rid[3]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \s_axi_rid[3]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \s_axi_rid[3]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_rid[3]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_rid[3]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_rid[3]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_rid[3]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_rid[3]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_rid[3]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \s_axi_rid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \s_axi_rid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \s_axi_rid[3]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \s_axi_rid[3]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \s_axi_rid[3]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \s_axi_rid[3]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \s_axi_rid[3]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end mig_wrap_auto_cc_0_rd_logic;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.mig_wrap_auto_cc_0_rd_fwft
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[5]\(0) => \goreg_dm.dout_i_reg[5]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gras.rsts\: entity work.mig_wrap_auto_cc_0_rd_status_flags_as
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.mig_wrap_auto_cc_0_rd_bin_cntr
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_logic_28 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_logic_28 : entity is "rd_logic";
end mig_wrap_auto_cc_0_rd_logic_28;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_logic_28 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.mig_wrap_auto_cc_0_rd_fwft_39
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.mig_wrap_auto_cc_0_rd_status_flags_as_40
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.mig_wrap_auto_cc_0_rd_bin_cntr_41
port map (
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_logic_49 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_logic_49 : entity is "rd_logic";
end mig_wrap_auto_cc_0_rd_logic_49;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_logic_49 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.mig_wrap_auto_cc_0_rd_fwft_60
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[38]\(0) => \goreg_dm.dout_i_reg[38]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gras.rsts\: entity work.mig_wrap_auto_cc_0_rd_status_flags_as_61
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.mig_wrap_auto_cc_0_rd_bin_cntr_62
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_logic_7 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[36]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_logic_7 : entity is "rd_logic";
end mig_wrap_auto_cc_0_rd_logic_7;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_logic_7 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.mig_wrap_auto_cc_0_rd_fwft_18
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[36]\(0) => \goreg_dm.dout_i_reg[36]\(0),
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.mig_wrap_auto_cc_0_rd_status_flags_as_19
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.mig_wrap_auto_cc_0_rd_bin_cntr_20
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_rd_logic_71 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_rd_logic_71 : entity is "rd_logic";
end mig_wrap_auto_cc_0_rd_logic_71;
architecture STRUCTURE of mig_wrap_auto_cc_0_rd_logic_71 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.mig_wrap_auto_cc_0_rd_fwft_84
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.mig_wrap_auto_cc_0_rd_status_flags_as_85
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.mig_wrap_auto_cc_0_rd_bin_cntr_86
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
end mig_wrap_auto_cc_0_reset_blk_ramfifo;
architecture STRUCTURE of mig_wrap_auto_cc_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_1
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_3
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_4
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_5
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_reset_blk_ramfifo_30 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_reset_blk_ramfifo_30 : entity is "reset_blk_ramfifo";
end mig_wrap_auto_cc_0_reset_blk_ramfifo_30;
architecture STRUCTURE of mig_wrap_auto_cc_0_reset_blk_ramfifo_30 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_31
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_32
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_33
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_34
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_35
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_36
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_reset_blk_ramfifo_51 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_reset_blk_ramfifo_51 : entity is "reset_blk_ramfifo";
end mig_wrap_auto_cc_0_reset_blk_ramfifo_51;
architecture STRUCTURE of mig_wrap_auto_cc_0_reset_blk_ramfifo_51 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ <= \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_52
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_53
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_54
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_55
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_56
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_57
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_reset_blk_ramfifo_74 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_reset_blk_ramfifo_74 : entity is "reset_blk_ramfifo";
end mig_wrap_auto_cc_0_reset_blk_ramfifo_74;
architecture STRUCTURE of mig_wrap_auto_cc_0_reset_blk_ramfifo_74 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_75
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_76
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_77
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_78
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_79
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_80
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_reset_blk_ramfifo_9 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_reset_blk_ramfifo_9 : entity is "reset_blk_ramfifo";
end mig_wrap_auto_cc_0_reset_blk_ramfifo_9;
architecture STRUCTURE of mig_wrap_auto_cc_0_reset_blk_ramfifo_9 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_10
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_11
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_12
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_13
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_14
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.mig_wrap_auto_cc_0_synchronizer_ff_15
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_auto_cc_0_wr_logic;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.mig_wrap_auto_cc_0_wr_status_flags_as
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.mig_wrap_auto_cc_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_logic_29 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_logic_29 : entity is "wr_logic";
end mig_wrap_auto_cc_0_wr_logic_29;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_logic_29 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.mig_wrap_auto_cc_0_wr_status_flags_as_37
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
wpntr: entity work.mig_wrap_auto_cc_0_wr_bin_cntr_38
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_logic_50 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_logic_50 : entity is "wr_logic";
end mig_wrap_auto_cc_0_wr_logic_50;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_logic_50 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.mig_wrap_auto_cc_0_wr_status_flags_as_58
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.mig_wrap_auto_cc_0_wr_bin_cntr_59
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_logic_72 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_logic_72 : entity is "wr_logic";
end mig_wrap_auto_cc_0_wr_logic_72;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_logic_72 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.mig_wrap_auto_cc_0_wr_status_flags_as_82
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
wpntr: entity work.mig_wrap_auto_cc_0_wr_bin_cntr_83
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_wr_logic_8 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_wr_logic_8 : entity is "wr_logic";
end mig_wrap_auto_cc_0_wr_logic_8;
architecture STRUCTURE of mig_wrap_auto_cc_0_wr_logic_8 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.mig_wrap_auto_cc_0_wr_status_flags_as_16
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
wpntr: entity work.mig_wrap_auto_cc_0_wr_bin_cntr_17
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_fifo_generator_ramfifo is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end mig_wrap_auto_cc_0_fifo_generator_ramfifo;
architecture STRUCTURE of mig_wrap_auto_cc_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.mig_wrap_auto_cc_0_clk_x_pntrs_27
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
Q(3 downto 0) => p_22_out(3 downto 0),
\gc0.count_d1_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gc0.count_d1_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gc0.count_d1_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gc0.count_d1_reg[3]\(0) => p_0_out_0(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_23_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out_1(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.mig_wrap_auto_cc_0_rd_logic_28
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[64]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.mig_wrap_auto_cc_0_wr_logic_29
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out_1(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gntv_or_sync_fifo.mem\: entity work.mig_wrap_auto_cc_0_memory
port map (
DI(64 downto 0) => DI(64 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
Q(64 downto 0) => Q(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => p_18_out,
s_aclk => s_aclk
);
rstblk: entity work.mig_wrap_auto_cc_0_reset_blk_ramfifo_30
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_23_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_fifo_generator_ramfifo_69 is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_fifo_generator_ramfifo_69 : entity is "fifo_generator_ramfifo";
end mig_wrap_auto_cc_0_fifo_generator_ramfifo_69;
architecture STRUCTURE of mig_wrap_auto_cc_0_fifo_generator_ramfifo_69 is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rach : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.mig_wrap_auto_cc_0_clk_x_pntrs_70
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rach,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.mig_wrap_auto_cc_0_rd_logic_71
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[64]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.mig_wrap_auto_cc_0_wr_logic_72
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gntv_or_sync_fifo.mem\: entity work.mig_wrap_auto_cc_0_memory_73
port map (
E(0) => p_18_out,
I123(64 downto 0) => I123(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.mig_wrap_auto_cc_0_reset_blk_ramfifo_74
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rach,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo";
end \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized0\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.mig_wrap_auto_cc_0_clk_x_pntrs_6
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_15_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.mig_wrap_auto_cc_0_rd_logic_7
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[36]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.mig_wrap_auto_cc_0_wr_logic_8
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gntv_or_sync_fifo.mem\: entity work.\mig_wrap_auto_cc_0_memory__parameterized0\
port map (
E(0) => p_18_out,
I115(36 downto 0) => I115(36 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.mig_wrap_auto_cc_0_reset_blk_ramfifo_9
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_15_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo";
end \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized1\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_wrch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.mig_wrap_auto_cc_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_wrch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.mig_wrap_auto_cc_0_rd_logic
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[5]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.mig_wrap_auto_cc_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\mig_wrap_auto_cc_0_memory__parameterized1\
port map (
E(0) => p_18_out,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0)
);
rstblk: entity work.mig_wrap_auto_cc_0_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_wrch,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
port (
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized2\ : entity is "fifo_generator_ramfifo";
end \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized2\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rdch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.mig_wrap_auto_cc_0_clk_x_pntrs_48
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rdch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.mig_wrap_auto_cc_0_rd_logic_49
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[38]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.mig_wrap_auto_cc_0_wr_logic_50
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\mig_wrap_auto_cc_0_memory__parameterized2\
port map (
E(0) => p_18_out,
I127(38 downto 0) => I127(38 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0)
);
rstblk: entity work.mig_wrap_auto_cc_0_reset_blk_ramfifo_51
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ => \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rdch,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_fifo_generator_top is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end mig_wrap_auto_cc_0_fifo_generator_top;
architecture STRUCTURE of mig_wrap_auto_cc_0_fifo_generator_top is
begin
\grf.rf\: entity work.mig_wrap_auto_cc_0_fifo_generator_ramfifo_69
port map (
I123(64 downto 0) => I123(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_fifo_generator_top_0 is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_auto_cc_0_fifo_generator_top_0 : entity is "fifo_generator_top";
end mig_wrap_auto_cc_0_fifo_generator_top_0;
architecture STRUCTURE of mig_wrap_auto_cc_0_fifo_generator_top_0 is
begin
\grf.rf\: entity work.mig_wrap_auto_cc_0_fifo_generator_ramfifo
port map (
DI(64 downto 0) => DI(64 downto 0),
Q(64 downto 0) => Q(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_fifo_generator_top__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top";
end \mig_wrap_auto_cc_0_fifo_generator_top__parameterized0\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_fifo_generator_top__parameterized0\ is
begin
\grf.rf\: entity work.\mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized0\
port map (
I115(36 downto 0) => I115(36 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_fifo_generator_top__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top";
end \mig_wrap_auto_cc_0_fifo_generator_top__parameterized1\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_fifo_generator_top__parameterized1\ is
begin
\grf.rf\: entity work.\mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mig_wrap_auto_cc_0_fifo_generator_top__parameterized2\ is
port (
inverted_reset : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \mig_wrap_auto_cc_0_fifo_generator_top__parameterized2\ : entity is "fifo_generator_top";
end \mig_wrap_auto_cc_0_fifo_generator_top__parameterized2\;
architecture STRUCTURE of \mig_wrap_auto_cc_0_fifo_generator_top__parameterized2\ is
begin
\grf.rf\: entity work.\mig_wrap_auto_cc_0_fifo_generator_ramfifo__parameterized2\
port map (
I127(38 downto 0) => I127(38 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ => inverted_reset,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_fifo_generator_v13_1_3_synth is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
end mig_wrap_auto_cc_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3_synth is
signal inverted_reset : STD_LOGIC;
begin
\gaxi_full_lite.gread_ch.grach2.axi_rach\: entity work.mig_wrap_auto_cc_0_fifo_generator_top
port map (
I123(64 downto 0) => I123(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gaxi_full_lite.gread_ch.grdch2.axi_rdch\: entity work.\mig_wrap_auto_cc_0_fifo_generator_top__parameterized2\
port map (
I127(38 downto 0) => I127(38 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gaxi_full_lite.gwrite_ch.gwach2.axi_wach\: entity work.mig_wrap_auto_cc_0_fifo_generator_top_0
port map (
DI(64 downto 0) => DI(64 downto 0),
Q(64 downto 0) => Q(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch\: entity work.\mig_wrap_auto_cc_0_fifo_generator_top__parameterized0\
port map (
I115(36 downto 0) => I115(36 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch\: entity work.\mig_wrap_auto_cc_0_fifo_generator_top__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 17 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 65;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 39;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 65;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 37;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 6;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
end mig_wrap_auto_cc_0_fifo_generator_v13_1_3;
architecture STRUCTURE of mig_wrap_auto_cc_0_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
dout(17) <= \<const0>\;
dout(16) <= \<const0>\;
dout(15) <= \<const0>\;
dout(14) <= \<const0>\;
dout(13) <= \<const0>\;
dout(12) <= \<const0>\;
dout(11) <= \<const0>\;
dout(10) <= \<const0>\;
dout(9) <= \<const0>\;
dout(8) <= \<const0>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const0>\;
dout(3) <= \<const0>\;
dout(2) <= \<const0>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
empty <= \<const0>\;
full <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.mig_wrap_auto_cc_0_fifo_generator_v13_1_3_synth
port map (
DI(64 downto 61) => s_axi_awid(3 downto 0),
DI(60 downto 29) => s_axi_awaddr(31 downto 0),
DI(28 downto 21) => s_axi_awlen(7 downto 0),
DI(20 downto 18) => s_axi_awsize(2 downto 0),
DI(17 downto 16) => s_axi_awburst(1 downto 0),
DI(15) => s_axi_awlock(0),
DI(14 downto 11) => s_axi_awcache(3 downto 0),
DI(10 downto 8) => s_axi_awprot(2 downto 0),
DI(7 downto 4) => s_axi_awqos(3 downto 0),
DI(3 downto 0) => s_axi_awregion(3 downto 0),
I115(36 downto 5) => s_axi_wdata(31 downto 0),
I115(4 downto 1) => s_axi_wstrb(3 downto 0),
I115(0) => s_axi_wlast,
I123(64 downto 61) => s_axi_arid(3 downto 0),
I123(60 downto 29) => s_axi_araddr(31 downto 0),
I123(28 downto 21) => s_axi_arlen(7 downto 0),
I123(20 downto 18) => s_axi_arsize(2 downto 0),
I123(17 downto 16) => s_axi_arburst(1 downto 0),
I123(15) => s_axi_arlock(0),
I123(14 downto 11) => s_axi_arcache(3 downto 0),
I123(10 downto 8) => s_axi_arprot(2 downto 0),
I123(7 downto 4) => s_axi_arqos(3 downto 0),
I123(3 downto 0) => s_axi_arregion(3 downto 0),
I127(38 downto 35) => m_axi_rid(3 downto 0),
I127(34 downto 3) => m_axi_rdata(31 downto 0),
I127(2 downto 1) => m_axi_rresp(1 downto 0),
I127(0) => m_axi_rlast,
Q(64 downto 61) => m_axi_awid(3 downto 0),
Q(60 downto 29) => m_axi_awaddr(31 downto 0),
Q(28 downto 21) => m_axi_awlen(7 downto 0),
Q(20 downto 18) => m_axi_awsize(2 downto 0),
Q(17 downto 16) => m_axi_awburst(1 downto 0),
Q(15) => m_axi_awlock(0),
Q(14 downto 11) => m_axi_awcache(3 downto 0),
Q(10 downto 8) => m_axi_awprot(2 downto 0),
Q(7 downto 4) => m_axi_awqos(3 downto 0),
Q(3 downto 0) => m_axi_awregion(3 downto 0),
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 61) => m_axi_arid(3 downto 0),
\m_axi_arid[3]\(60 downto 29) => m_axi_araddr(31 downto 0),
\m_axi_arid[3]\(28 downto 21) => m_axi_arlen(7 downto 0),
\m_axi_arid[3]\(20 downto 18) => m_axi_arsize(2 downto 0),
\m_axi_arid[3]\(17 downto 16) => m_axi_arburst(1 downto 0),
\m_axi_arid[3]\(15) => m_axi_arlock(0),
\m_axi_arid[3]\(14 downto 11) => m_axi_arcache(3 downto 0),
\m_axi_arid[3]\(10 downto 8) => m_axi_arprot(2 downto 0),
\m_axi_arid[3]\(7 downto 4) => m_axi_arqos(3 downto 0),
\m_axi_arid[3]\(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\m_axi_wdata[31]\(36 downto 5) => m_axi_wdata(31 downto 0),
\m_axi_wdata[31]\(4 downto 1) => m_axi_wstrb(3 downto 0),
\m_axi_wdata[31]\(0) => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[3]\(5 downto 2) => s_axi_bid(3 downto 0),
\s_axi_bid[3]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[3]\(38 downto 35) => s_axi_rid(3 downto 0),
\s_axi_rid[3]\(34 downto 3) => s_axi_rdata(31 downto 0),
\s_axi_rid[3]\(2 downto 1) => s_axi_rresp(1 downto 0),
\s_axi_rid[3]\(0) => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 61;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 61;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 6;
attribute C_FAMILY : string;
attribute C_FAMILY of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 6;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 39;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 35;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 39;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 5;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "yes";
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "1'b1";
end mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter;
architecture STRUCTURE of mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
signal \<const0>\ : STD_LOGIC;
signal async_conv_reset_n : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXI_ADDR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 32;
attribute C_AXI_ARUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_AWUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_BUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_DATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 32;
attribute C_AXI_ID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_RUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_WUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 65;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 39;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 65;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 37;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 6;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_FAMILY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SYNCHRONIZER_STAGE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
begin
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi\: entity work.mig_wrap_auto_cc_0_fifo_generator_v13_1_3
port map (
almost_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\,
almost_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\,
axi_ar_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\(4 downto 0),
axi_ar_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\,
axi_ar_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\(4 downto 0),
axi_ar_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\,
axi_ar_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\,
axi_ar_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\(4 downto 0),
axi_aw_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\(4 downto 0),
axi_aw_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\,
axi_aw_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\(4 downto 0),
axi_aw_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\,
axi_aw_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\,
axi_aw_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\(4 downto 0),
axi_b_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\(4 downto 0),
axi_b_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\,
axi_b_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\(4 downto 0),
axi_b_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\,
axi_b_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\,
axi_b_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\(4 downto 0),
axi_r_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\(4 downto 0),
axi_r_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\,
axi_r_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\,
axi_r_prog_empty_thresh(3 downto 0) => B"0000",
axi_r_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\,
axi_r_prog_full_thresh(3 downto 0) => B"0000",
axi_r_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\(4 downto 0),
axi_r_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\,
axi_r_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\,
axi_r_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\(4 downto 0),
axi_w_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\(4 downto 0),
axi_w_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\,
axi_w_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\,
axi_w_prog_empty_thresh(3 downto 0) => B"0000",
axi_w_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\,
axi_w_prog_full_thresh(3 downto 0) => B"0000",
axi_w_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\(4 downto 0),
axi_w_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\,
axi_w_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\,
axi_w_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\(4 downto 0),
axis_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\(10 downto 0),
axis_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\,
axis_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\(10 downto 0),
axis_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\,
axis_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\,
axis_wr_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\(9 downto 0),
dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\,
din(17 downto 0) => B"000000000000000000",
dout(17 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\(17 downto 0),
empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\,
full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => m_axi_aclk,
m_aclk_en => '1',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(3 downto 0) => m_axi_arid(3 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(3 downto 0) => m_axi_awid(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\(3 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\(0),
m_axi_wvalid => m_axi_wvalid,
m_axis_tdata(7 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\(7 downto 0),
m_axis_tdest(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\(0),
m_axis_tid(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\(0),
m_axis_tkeep(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\(0),
m_axis_tlast => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\,
m_axis_tready => '0',
m_axis_tstrb(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\(0),
m_axis_tuser(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\(3 downto 0),
m_axis_tvalid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\,
overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\,
prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\(9 downto 0),
rd_en => '0',
rd_rst => '0',
rd_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\,
rst => '0',
s_aclk => s_axi_aclk,
s_aclk_en => '1',
s_aresetn => async_conv_reset_n,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(3 downto 0) => s_axi_arid(3 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(3 downto 0) => s_axi_awid(3 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(3 downto 0) => s_axi_bid(3 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(3 downto 0) => s_axi_rid(3 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid,
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\,
sleep => '0',
srst => '0',
underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\,
valid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\,
wr_ack => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\,
wr_clk => '0',
wr_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\(9 downto 0),
wr_en => '0',
wr_rst => '0',
wr_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_aresetn,
I1 => m_axi_aresetn,
O => async_conv_reset_n
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mig_wrap_auto_cc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mig_wrap_auto_cc_0 : entity is "mig_wrap_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of mig_wrap_auto_cc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of mig_wrap_auto_cc_0 : entity is "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4";
end mig_wrap_auto_cc_0;
architecture STRUCTURE of mig_wrap_auto_cc_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of inst : label is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of inst : label is 32;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of inst : label is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of inst : label is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of inst : label is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of inst : label is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of inst : label is 61;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of inst : label is 4;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of inst : label is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of inst : label is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of inst : label is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of inst : label is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of inst : label is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of inst : label is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of inst : label is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of inst : label is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of inst : label is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of inst : label is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of inst : label is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of inst : label is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of inst : label is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of inst : label is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of inst : label is 65;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of inst : label is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of inst : label is 32;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of inst : label is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of inst : label is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of inst : label is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of inst : label is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of inst : label is 61;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of inst : label is 4;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of inst : label is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of inst : label is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of inst : label is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of inst : label is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of inst : label is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of inst : label is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of inst : label is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of inst : label is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of inst : label is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of inst : label is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of inst : label is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of inst : label is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of inst : label is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of inst : label is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of inst : label is 65;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 4;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of inst : label is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of inst : label is 4;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of inst : label is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of inst : label is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of inst : label is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of inst : label is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of inst : label is 6;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of inst : label is 65;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of inst : label is 65;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of inst : label is 6;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of inst : label is 39;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of inst : label is 37;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of inst : label is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of inst : label is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of inst : label is 35;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of inst : label is 4;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of inst : label is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of inst : label is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of inst : label is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of inst : label is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of inst : label is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of inst : label is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of inst : label is 39;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of inst : label is 5;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of inst : label is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of inst : label is 37;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of inst : label is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of inst : label is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of inst : label is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of inst : label is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of inst : label is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of inst : label is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of inst : label is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of inst : label is 37;
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of inst : label is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of inst : label is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of inst : label is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of inst : label is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of inst : label is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of inst : label is "1'b1";
attribute downgradeipidentifiedwarnings of inst : label is "yes";
begin
inst: entity work.mig_wrap_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
port map (
m_axi_aclk => m_axi_aclk,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => m_axi_aresetn,
m_axi_arid(3 downto 0) => m_axi_arid(3 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(3 downto 0) => m_axi_awid(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(3 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(3 downto 0) => s_axi_arid(3 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(3 downto 0) => s_axi_awid(3 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(3 downto 0) => s_axi_bid(3 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(3 downto 0) => s_axi_rid(3 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
mit
|
107600f8682458671c86bedd408e27ea
| 0.579686 | 2.716746 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_int_axi4_read_cntrl.vhd
| 1 | 5,353 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 28, 2017
--! @brief Contains the entity and architecture of the
--! Interrupt Controller's Slave AXI4-Lite Read
--! Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_int_pack.all;
--! The Read Controller implements a Slave AXI4-Lite Read
--! interface in order to allow a Master interface to read from
--! the registers of the core.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_int_axi4_read_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Interrupt Controller parameters.
int_id_address : std_logic_vector := X"0004"; --! Defines the offset for the Interrupt Identifier register.
int_enables_address : std_logic_vector := X"0000"; --! Defines the offset for the Interrupt Enables register.
int_active_address : std_logic_vector := X"0008" --! Defines the offset for the Interrupt Active register.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- Interrupt Controller Interface.
int_id : in std_logic_vector(axi_data_width-1 downto 0); --! Interrupt Identifier register.
int_enables : in std_logic_vector(axi_data_width-1 downto 0); --! Interrupt Enables register.
int_active : in std_logic_vector(axi_data_width-1 downto 0) --! Interrupt Active register.
);
end plasoc_int_axi4_read_cntrl;
architecture Behavioral of plasoc_int_axi4_read_cntrl is
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal axi_araddr_buff : std_logic_vector(axi_address_width-1 downto 0);
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
-- Drive the axi read interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Wait for handshake,
if axi_arvalid='1' and axi_arready_buff='1' then
-- Prevent the master from sending any more control information.
axi_arready_buff <= '0';
-- Sample the address sent from the master.
axi_araddr_buff <= axi_araddr;
state <= state_read;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_arready_buff <= '1';
end if;
-- READ mode.
when state_read=>
-- Wait for handshake,
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
-- Set the data and let the master know it's available.
else
axi_rvalid_buff <= '1';
-- Send data according to the bufferred address.
if axi_araddr_buff=int_id_address then
axi_rdata <= int_id;
elsif axi_araddr_buff=int_enables_address then
axi_rdata <= int_enables;
elsif axi_araddr_buff=int_active_address then
axi_rdata <= int_active;
else
axi_rdata <= (others=>'0');
end if;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
e92b4b2ba6dd0cc82ab4979900b1fe9a
| 0.533719 | 4.413026 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vsigrefofkofall.vhd
| 1 | 1,328 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vsigrefofkofall is
port (
clock : in std_logic;
Vrefofkplusone : in std_logic_vector(31 downto 0);
refsigma : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : out std_logic_vector(31 downto 0);
Vsigrefofkofone : out std_logic_vector(31 downto 0);
Vsigrefofkoftwo : out std_logic_vector(31 downto 0)
);
end k_ukf_Vsigrefofkofall;
architecture struct of k_ukf_Vsigrefofkofall is
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
begin
Vsigrefofkofzero <= Vrefofkplusone;
M1 : k_ukf_add port map
( clock => clock,
dataa => Vrefofkplusone,
datab => refsigma,
result => Vsigrefofkofone);
M2 : k_ukf_sub port map
( clock => clock,
dataa => Vrefofkplusone,
datab => refsigma,
result => Vsigrefofkoftwo);
end struct;
|
gpl-2.0
|
10d6950caae70fa849043db4086cb72a
| 0.636295 | 3.246944 | false | false | false | false |
Ttl/pic16f84
|
stack.vhd
| 1 | 867 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity stack is
Port ( clk, reset : in STD_LOGIC;
push, pop : in STD_LOGIC;
pcin : in STD_LOGIC_VECTOR (12 downto 0);
pcout : out STD_LOGIC_VECTOR (12 downto 0));
end stack;
architecture Behavioral of stack is
signal stack : stack_type13;
begin
process(clk, reset, stack, push, pop, pcin)
variable pointer : unsigned(2 downto 0);
begin
if rising_edge(clk) then
if push = '1' then
--Write
pointer := pointer + 1;
stack(to_integer(pointer)) <= pcin;
elsif pop = '1' then
pointer := pointer - 1;
end if;
end if;
-- Set output, only readable after pop
pcout <= stack(to_integer(pointer));
if reset = '1' then
pointer := to_unsigned(0,3);
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
a1ab03fd3acddd3c3360c1e46ee4195f
| 0.623991 | 3.321839 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/blk_mem_gen_1/synth/blk_mem_gen_1.vhd
| 1 | 14,823 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_1_arch : ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_XDEVICEFAMILY=kintex7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.53475 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "kintex7",
C_XDEVICEFAMILY => "kintex7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.53475 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
|
bsd-3-clause
|
6b4c03bbcf75ac6ace6a256f4cbbb7c0
| 0.62855 | 3.006694 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_reg_module.vhd
| 4 | 87,143 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_8.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_8.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_8.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
|
bsd-3-clause
|
78f20e6899bedc4cac6e2a44f7a4cb77
| 0.438807 | 3.702698 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/buttons.vhdl
| 1 | 1,072 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_buttons is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- push buttons
buttons : in std_logic_vector(3 downto 0)
);
end mmio_buttons;
architecture mmio of mmio_buttons is
constant reading : std_logic := '0';
signal data_out : word_t;
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
process(clk)
begin
if rising_edge(clk) and en = '1' and size /= "00" then
case wr is
when reading => zeroextend(data_out, buttons);
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end;
|
gpl-3.0
|
683a1f606e73671ff27fe17d50f032b5
| 0.522388 | 3.646259 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_cpu_axi4_read_cntrl.vhd
| 1 | 12,314 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 17, 2017
--! @brief Contains the entity and architecture of the
--! CPU's Master AXI4-Full Read Memory Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_cpu_pack.all;
--! The Read Memory Controller implements a Master AXI4-Full Read
--! interface in order to allow the CPU to perform reads from
--! main memory and other devices external to the CPU. Much optimization
--! of the Write and Read Memory Controllers is needed for future revisions,
--! considering the current revision is implemented in a sequential, blocking
--! manner. Specifically, for the sake simplicity, the AXI4-Full Read Address,
--! and Read Data are implemented as a state machine, rather than as separate
--! processes that can permit concurrent execution.
--!
--! Information specific to the AXI4-Full
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_cpu_axi4_read_cntrl is
generic (
-- CPU parameters.
cpu_address_width : integer := 16; --! Defines the address width of the CPU. This should normally be equal to the CPU's width.
cpu_data_width : integer := 32; --! Defines the data width of the CPU. This should normally be equal to the CPU's width.
-- Cache parameters.
cache_offset_width : integer := 5; --! Indicates whether the requested address of the CPU is cacheable or noncacheable.
-- axi read constants
axi_aruser_width : integer := 0; --! Width of user-define AXI4-Full Address Read signal.
axi_ruser_width : integer := 0 --! Width of user-define AXI4-Full Read Data signal.
);
port(
-- Global interfaces.
clock : in std_logic; --! Clock. Tested with 50 MHz.
nreset : in std_logic; --! Reset on low.
-- Memory interface.
mem_read_address : in std_logic_vector(cpu_address_width-1 downto 0); --! The requested address sent to the read memory controller.
mem_read_data : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! The word read from the read memory controller.
mem_read_enable : in std_logic; --! Enables the operation of the read memory controller.
mem_read_valid : out std_logic; --! Indicates the read memory controller has a valid word on mem_read_data.
mem_read_ready : in std_logic; --! Indicates the cache is ready to sample a word from mem_read_data.
-- Cache interface.
cache_cacheable : in std_logic; --! Indicates whether the requested address of the CPU is cacheable or noncacheable.
-- Master AXI4-Full Read interface.
axi_arid : out std_logic_vector(-1 downto 0); --! AXI4-Full Address Read signal.
axi_araddr : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0'); --! AXI4-Full Address Read signal.
axi_arlen : out std_logic_vector(7 downto 0); --! AXI4-Full Address Read signal.
axi_arsize : out std_logic_vector(2 downto 0); --! AXI4-Full Address Read signal.
axi_arburst : out std_logic_vector(1 downto 0); --! AXI4-Full Address Read signal.
axi_arlock : out std_logic; --! AXI4-Full Address Read signal.
axi_arcache : out std_logic_vector(3 downto 0); --! AXI4-Full Address Read signal.
axi_arprot : out std_logic_vector(2 downto 0); --! AXI4-Full Address Read signal.
axi_arqos : out std_logic_vector(3 downto 0); --! AXI4-Full Address Read signal.
axi_arregion : out std_logic_vector(3 downto 0); --! AXI4-Full Address Read signal.
axi_aruser : out std_logic_vector(axi_aruser_width-1 downto 0); --! AXI4-Full Address Read signal.
axi_arvalid : out std_logic; --! AXI4-Full Address Read signal.
axi_arready : in std_logic; --! AXI4-Full Address Read signal.
axi_rid : in std_logic_vector(-1 downto 0); --! AXI4-Full Read Data signal.
axi_rdata : in std_logic_vector(cpu_data_width-1 downto 0); --! AXI4-Full Read Data signal.
axi_rresp : in std_logic_vector(1 downto 0); --! AXI4-Full Read Data signal.
axi_rlast : in std_logic; --! AXI4-Full Read Data signal.
axi_ruser : in std_logic_vector(axi_ruser_width-1 downto 0); --! AXI4-Full Read Data signal.
axi_rvalid : in std_logic; --! AXI4-Full Read Data signal.
axi_rready : out std_logic; --! AXI4-Full Read Data signal.
-- Error interface.
error_data : out std_logic_vector(3 downto 0) := (others=>'0') --! Returns value signifying error in the transaction.
);
end plasoc_cpu_axi4_read_cntrl;
architecture Behavioral of plasoc_cpu_axi4_read_cntrl is
subtype error_data_type is std_logic_vector(error_data'high downto error_data'low);
constant cpu_bytes_per_word : integer := cpu_data_width/8;
constant cache_words_per_line : integer := 2**cache_offset_width/cpu_bytes_per_word;
constant axi_burst_len_noncacheable : integer := 0;
constant axi_burst_len_cacheable : integer := cache_words_per_line-1;
type state_type is (state_wait,state_read,state_error);
signal state : state_type := state_wait;
signal counter : integer range 0 to cache_words_per_line;
signal axi_finished : boolean := False;
signal axi_arlen_buff : std_logic_vector(7 downto 0) := (others=>'0');
signal axi_arvalid_buff : std_logic := '0';
signal axi_rready_buff : std_logic := '0';
signal mem_read_valid_buff : std_logic := '0';
constant fifo_index_width : integer := cache_offset_width-clogb2(cpu_data_width/8);
type fifo_type is array(0 to 2**fifo_index_width-1) of std_logic_vector(cpu_data_width-1 downto 0);
signal fifo : fifo_type := (others=>(others=>'0'));
signal m_ptr : integer range 0 to 2**fifo_index_width-1 := 0;
signal s_ptr : integer range 0 to 2**fifo_index_width-1 := 0;
begin
axi_arid <= (others=>'0');
axi_arlen <= axi_arlen_buff;
axi_arsize <= std_logic_vector(to_unsigned(clogb2(cpu_bytes_per_word),axi_arsize'length));
axi_arburst <= axi_burst_incr;
axi_arlock <= axi_lock_normal_access;
axi_arcache <= axi_cache_device_nonbufferable;
axi_arprot <= axi_prot_instr & not axi_prot_sec & not axi_prot_priv;
axi_arqos <= (others=>'0');
axi_arregion <= (others=>'0');
axi_aruser <= (others=>'0');
axi_arvalid <= axi_arvalid_buff;
axi_rready <= axi_rready_buff;
mem_read_valid <= mem_read_valid_buff;
mem_read_data <= fifo(s_ptr);
process (clock)
variable burst_len : integer range 0 to 2**axi_arlen'length-1;
variable error_data_buff : error_data_type := (others=>'0');
begin
if rising_edge(clock) then
if nreset='0' then
error_data <= (others=>'0');
error_data_buff := (others=>'0');
axi_arvalid_buff <= '0';
axi_rready_buff <= '0';
mem_read_valid_buff <= '0';
state <= state_wait;
else
case state is
-- WAIT mode.
when state_wait =>
-- Wait until the memory read interface requests data.
if mem_read_enable='1' then
-- Set control information.
axi_araddr <= mem_read_address;
-- The burst length will change according to whether the memory access is cacheable or not.
if cache_cacheable='1' then
burst_len := axi_burst_len_cacheable;
else
burst_len := axi_burst_len_noncacheable;
end if;
axi_arlen_buff <= std_logic_vector(to_unsigned(burst_len,axi_arlen'length));
-- Set counter to keep track the number of words read from the burst.
counter <= 0;
s_ptr <= 0;
m_ptr <= 0;
-- Reset finish indicator.
axi_finished <= False;
-- Wait until handshake before reading data.
if axi_arvalid_buff='1' and axi_arready='1' then
axi_arvalid_buff <= '0';
axi_rready_buff <= '1';
state <= state_read;
else
axi_arvalid_buff <= '1';
end if;
end if;
-- READ mode.
when state_read=>
if axi_rvalid='1' and axi_rready_buff='1' then
fifo(m_ptr) <= axi_rdata;
end if;
if m_ptr/=s_ptr and mem_read_valid_buff='1' and mem_read_ready='1' then
if s_ptr=2**fifo_index_width-1 then
s_ptr <= 0;
else
s_ptr <= s_ptr+1;
end if;
end if;
if axi_rvalid='1' and axi_rready_buff='1' and ((m_ptr+1) mod 2**fifo_index_width)/=s_ptr then
if m_ptr=2**fifo_index_width-1 then
m_ptr <= 0;
else
m_ptr <= m_ptr+1;
end if;
end if;
if mem_read_valid_buff='1' and mem_read_ready='1' and counter/=axi_arlen_buff then
counter <= counter+1;
end if;
if axi_rvalid='1' and axi_rready_buff='1' and axi_rlast='1' then
axi_finished <= True;
end if;
if (axi_rvalid='1' and axi_rready_buff='1' and axi_rlast='1') or axi_finished then
axi_rready_buff <= '0';
elsif ((m_ptr+1) mod 2**fifo_index_width)/=s_ptr then
axi_rready_buff <= '1';
else
axi_rready_buff <= '0';
end if;
if mem_read_valid_buff='1' and mem_read_ready='1' and counter=axi_arlen_buff then
mem_read_valid_buff <= '0';
elsif m_ptr/=s_ptr then
mem_read_valid_buff <= '1';
else
mem_read_valid_buff <= '0';
end if;
if mem_read_valid_buff='1' and mem_read_ready='1' and counter=axi_arlen_buff then
state <= state_wait;
end if;
-- block in ERROR mode.
when state_error=>
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
0213022638735987ca06b872b7844852
| 0.498376 | 4.495801 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_gpio_axi4_read_cntrl.vhd
| 1 | 5,111 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! UART Core's Read Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
entity plasoc_gpio_axi4_read_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Register interface.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_data_in_offset : std_logic_vector := X"0004";
reg_data_out_offset : std_logic_vector := X"0008"
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- Register interface.
reg_control : in std_logic_vector(axi_data_width-1 downto 0);
reg_data_in : in std_logic_vector(axi_data_width-1 downto 0);
reg_data_out : in std_logic_vector(axi_data_width-1 downto 0)
);
end plasoc_gpio_axi4_read_cntrl;
architecture Behavioral of plasoc_gpio_axi4_read_cntrl is
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal axi_araddr_buff : std_logic_vector(axi_address_width-1 downto 0);
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
-- Drive the axi read interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Wait for handshake,
if axi_arvalid='1' and axi_arready_buff='1' then
-- Prevent the master from sending any more control information.
axi_arready_buff <= '0';
-- Sample the address sent from the master.
axi_araddr_buff <= axi_araddr;
state <= state_read;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_arready_buff <= '1';
end if;
-- READ mode.
when state_read=>
-- Wait for handshake,
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
-- Set the data and let the master know it's available.
else
axi_rvalid_buff <= '1';
-- Send data according to the bufferred address.
if axi_araddr_buff=reg_control_offset then
axi_rdata <= reg_control;
elsif axi_araddr_buff=reg_data_in_offset then
axi_rdata <= reg_data_in;
elsif axi_araddr_buff=reg_data_out_offset then
axi_rdata <= reg_data_out;
else
axi_rdata <= (others=>'0');
end if;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
212b9425046ce0fa2479783a84353a91
| 0.473489 | 4.646364 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/uart/uart_tx.vhdl
| 1 | 3,753 |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity uart_tx is
port (
clk : in std_logic;
reset : in std_logic;
tx_start : in std_logic;
baud_tick : in std_logic;
tx_data : in std_logic_vector( 7 downto 0 );
tx_done_tick : out std_logic;
tx : out std_logic
);
end entity;
architecture behav of uart_tx is
type STATE is (IDLE, START, DATA, STOP);
signal state_reg : STATE;
signal state_next : STATE;
signal baud_reg : std_logic_vector( 4 downto 0 );
signal baud_next : std_logic_vector( 4 downto 0 );
signal n_reg : std_logic_vector( 4 downto 0 );
signal n_next : std_logic_vector( 4 downto 0 );
signal d_reg : std_logic_vector( 7 downto 0 );
signal d_next : std_logic_vector( 7 downto 0 );
signal tx_reg : std_logic;
signal tx_next : std_logic;
begin
a: process (clk, reset) is
begin
if (reset = '1' ) then
state_reg <= IDLE;
baud_reg <= (others => '0');
n_reg <= (others => '0');
d_reg <= (others => '0');
tx_reg <= '1';
elsif (clk'EVENT and (clk = '1')) then
state_reg <= STATE_NEXT;
baud_reg <= baud_next;
n_reg <= n_next;
d_reg <= d_next;
tx_reg <= tx_next;
end if;
end process;
process
begin
wait ;
state_next <= state_reg;
tx_done_tick <= '0';
baud_next <= baud_reg;
n_next <= n_reg;
d_next <= d_reg;
tx_next <= tx_reg;
case ( state_reg ) is
when
IDLE =>
tx_next <= '1';
if ( tx_start = '1' ) then
state_next <= START;
baud_next <= "00000";
d_next <= tx_data;
end if;
when
START =>
tx_next <= '0';
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"10" ) ) then
state_next <= DATA;
baud_next <= "00000";
n_next <= "00000";
end if;
end if;
when
DATA =>
tx_next <= d_reg(0 );
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"10" ) ) then
d_next <= std_logic_vector(unsigned(d_reg) srl 1);
baud_next <= "00000";
n_next <= vec_increment(n_reg) ;
else
if ( ( n_reg = X"8" ) ) then
state_next <= STOP;
end if;
end if;
end if;
when
STOP =>
tx_next <= '1';
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"10" ) ) then
state_next <= IDLE;
tx_done_tick <= '1';
end if;
end if;
end case;
end process;
tx <= tx_reg;
end;
|
gpl-3.0
|
9ab541bd862ee4d34b0a98bc677e94bf
| 0.375433 | 4.128713 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/src/PmodNAV_axi_quad_spi_0_0/sim/PmodNAV_axi_quad_spi_0_0.vhd
| 1 | 15,071 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_8;
USE axi_quad_spi_v3_2_8.axi_quad_spi;
ENTITY PmodNAV_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END PmodNAV_axi_quad_spi_0_0;
ARCHITECTURE PmodNAV_axi_quad_spi_0_0_arch OF PmodNAV_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '0',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END PmodNAV_axi_quad_spi_0_0_arch;
|
bsd-3-clause
|
56e9926b8008af732c1ea148ae9ca4cc
| 0.642094 | 3.04096 | false | false | false | false |
makestuff/dvr-connectors
|
conv-16to8/vhdl/tb_unit/conv_16to8_tb.vhdl
| 1 | 3,196 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_16to8_tb is
end entity;
architecture behavioural of conv_16to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 16-bit interface signals
signal data16 : std_logic_vector(15 downto 0);
signal valid16 : std_logic;
signal ready16 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_16to8
port map(
clk_in => sysClk,
reset_in => '0',
data16_in => data16,
valid16_in => valid16,
ready16_out => ready16,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data16 <= (others => 'Z');
valid16 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data16 <= to_4(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3)) & to_4(inLine.all(4));
valid16 <= to_1(inLine.all(6));
ready8 <= to_1(inLine.all(8));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready16);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data16 <= (others => 'Z');
valid16 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
f4026603acf1642c4f9d4e816f406719
| 0.673655 | 3.164356 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/rgb2dvi_v1_2/src/rgb2dvi.vhd
| 1 | 7,781 |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 source interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure (optional), encoding and serialization logic.
-- On the input side it has 24-bit RGB video data bus, pixel clock and synchronization
-- signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2dvi is
Generic (
kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "MMCM"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kRstActiveHigh : boolean := true); --true, if active-high; false, if active-low
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
-- Auxiliary signals
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video in
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic; --pixel-clock recovered from the DVI interface
SerialClk : in std_logic); -- 5x PixelClk
end rgb2dvi;
architecture Behavioral of rgb2dvi is
type dataOut_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type dataOutRaw_t is array (2 downto 0) of std_logic_vector(9 downto 0);
signal pDataOut : dataOut_t;
signal pDataOutRaw : dataOutRaw_t;
signal pVde, pC0, pC1 : std_logic_vector(2 downto 0);
signal aRst_int, aPixelClkLckd : std_logic;
signal PixelClkIO, SerialClkIO, aRstLck, pRstLck : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
-- Generate SerialClk internally?
ClockGenInternal: if kGenerateSerialClk generate
ClockGenX: entity work.ClockGen
Generic map (
kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive => kClkPrimitive) -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port map (
PixelClkIn => PixelClk,
PixelClkOut => PixelClkIO,
SerialClk => SerialClkIO,
aRst => aRst_int,
aLocked => aPixelClkLckd);
--TODO revise this
aRstLck <= not aPixelClkLckd;
end generate ClockGenInternal;
ClockGenExternal: if not kGenerateSerialClk generate
PixelClkIO <= PixelClk;
SerialClkIO <= SerialClk;
aRstLck <= aRst_int;
end generate ClockGenExternal;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRstLck,
OutClk => PixelClk,
oRst => pRstLck);
-- Clock needs no encoding, send a pulse
ClockSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Clk_p,
sDataOut_n => TMDS_Clk_n,
--Encoded parallel data (raw)
pDataOut => "1111100000",
aRst => pRstLck);
DataEncoders: for i in 0 to 2 generate
DataEncoder: entity work.TMDS_Encoder
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
pDataOutRaw => pDataOutRaw(i),
aRst => pRstLck,
pDataOut => pDataOut(i),
pC0 => pC0(i),
pC1 => pC1(i),
pVde => pVde(i)
);
DataSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Data_p(i),
sDataOut_n => TMDS_Data_n(i),
--Encoded parallel data (raw)
pDataOut => pDataOutRaw(i),
aRst => pRstLck);
end generate DataEncoders;
-- DVI Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason vid_data is packed in RBG order
pDataOut(2) <= vid_pData(23 downto 16); -- red is channel 2
pDataOut(0) <= vid_pData(7 downto 0); -- blue is channel 0
pDataOut(1) <= vid_pData(15 downto 8); -- green is channel 1
pC0(2 downto 1) <= (others => '0'); -- default is low for control signals
pC1(2 downto 1) <= (others => '0'); -- default is low for control signals
pC0(0) <= vid_pHSync; -- channel 0 carries control signals too
pC1(0) <= vid_pVSync; -- channel 0 carries control signals too
pVde <= vid_pVDE & vid_pVDE & vid_pVDE; -- all of them are either active or blanking at once
end Behavioral;
|
bsd-3-clause
|
9511a097a9b6d9755383147110f39169
| 0.662126 | 4.373806 | false | false | false | false |
tmeissner/cryptocores
|
cbcaes/sim/vhdl/tb_cbcaes.vhd
| 1 | 5,429 |
-- ======================================================================
-- AES Counter mode testbench
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use std.env.all;
entity tb_cbcaes is
end entity tb_cbcaes;
architecture sim of tb_cbcaes is
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_start : std_logic := '0';
signal s_mode : std_logic := '0';
signal s_iv : std_logic_vector(0 to 127) := (others => '0');
signal s_key : std_logic_vector(0 to 127) := (others => '0');
signal s_datain : std_logic_vector(0 to 127) := (others => '0');
signal s_validin : std_logic := '0';
signal s_acceptin : std_logic;
signal s_dataout : std_logic_vector(0 to 127);
signal s_validout : std_logic := '0';
signal s_acceptout : std_logic := '0';
procedure cryptData(datain : in std_logic_vector(0 to 127);
key : in std_logic_vector(0 to 127);
iv : in std_logic_vector(0 to 127);
mode : in boolean;
start : in boolean;
final : in boolean;
dataout : out std_logic_vector(0 to 127);
bytelen : in integer) is
begin
report "VHPIDIRECT cryptData" severity failure;
end procedure;
attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
variable v_data : std_logic_vector(0 to 127);
begin
for i in 0 to 15 loop
for y in 0 to 7 loop
v_data((i*8)+y) := datain((i*8)+7-y);
end loop;
end loop;
return v_data;
end function;
begin
i_cbcaes : entity work.cbcaes
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
mode_i => s_mode,
key_i => s_key,
iv_i => s_iv,
data_i => s_datain,
valid_i => s_validin,
accept_o => s_acceptin,
data_o => s_dataout,
valid_o => s_validout,
accept_i => s_acceptout
);
s_clk <= not(s_clk) after 10 ns;
s_reset <= '1' after 100 ns;
process is
variable v_key : std_logic_vector(0 to 127);
variable v_iv : std_logic_vector(0 to 127);
variable v_datain : std_logic_vector(0 to 127);
variable v_dataout : std_logic_vector(0 to 127);
variable v_random : RandomPType;
begin
v_random.InitSeed(v_random'instance_name);
wait until s_reset = '1' and rising_edge(s_clk);
-- ENCRYPTION TESTs
report "Test CBC-AES encryption";
s_start <= '1';
s_mode <= '0';
v_iv := v_random.RandSlv(128);
v_key := v_random.RandSlv(128);
for i in 0 to 31 loop
v_datain := v_random.RandSlv(128);
s_validin <= '1';
s_key <= v_key;
s_iv <= v_iv;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), swap(v_iv), false, i = 0, i = 31, v_dataout, v_datain'length/8);
wait until s_acceptin = '1' and rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
wait until s_validout = '1' and rising_edge(s_clk);
s_acceptout <= '1';
assert s_dataout = swap(v_dataout)
report "Encryption error: Expected 0x" & to_hstring(swap(v_dataout)) & ", got 0x" & to_hstring(s_dataout)
severity failure;
wait until rising_edge(s_clk);
s_acceptout <= '0';
end loop;
-- DECRYPTION TESTs
report "Test CBC-AES decryption";
s_start <= '1';
s_mode <= '1';
v_iv := v_random.RandSlv(128);
v_key := v_random.RandSlv(128);
for i in 0 to 31 loop
v_datain := v_random.RandSlv(128);
s_validin <= '1';
s_key <= v_key;
s_iv <= v_iv;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), swap(v_iv), true, i = 0, i = 31, v_dataout, v_datain'length/8);
wait until s_acceptin = '1' and rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
wait until s_validout = '1' and rising_edge(s_clk);
s_acceptout <= '1';
assert s_dataout = swap(v_dataout)
report "Decryption error: Expected 0x" & to_hstring(swap(v_dataout)) & ", got 0x" & to_hstring(s_dataout)
severity failure;
wait until rising_edge(s_clk);
s_acceptout <= '0';
end loop;
wait for 100 ns;
report "Simulation finished without errors";
finish(0);
end process;
end architecture sim;
|
gpl-2.0
|
cea79a2b4983484a61534cec19fb2f84
| 0.566403 | 3.418766 | false | false | false | false |
tmeissner/cryptocores
|
aes/rtl/vhdl/aes_pkg.vhd
| 1 | 17,229 |
-- ======================================================================
-- AES encryption/decryption
-- Copyright (C) 2019 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
-- aes implementation
-- key length: 128 bit -> Nk = 4
-- data width: 128 bit -> Nb = 4
-- round number Nr = 10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package aes_pkg is
-- components
component aes_enc is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic;
clk_i : in std_logic;
key_i : in std_logic_vector(0 to 127);
data_i : in std_logic_vector(0 to 127);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127);
valid_o : out std_logic;
accept_i : in std_logic
);
end component aes_enc;
component aes_dec is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic;
clk_i : in std_logic;
key_i : in std_logic_vector(0 to 127);
data_i : in std_logic_vector(0 to 127);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127);
valid_o : out std_logic;
accept_i : in std_logic
);
end component aes_dec;
-- constants for AES128
constant c_nk : natural := 4; -- key size
constant c_nb : natural := 4; -- number of bytes
constant c_nr : natural := 10; -- number of rounds
subtype t_rounds is natural range 0 to c_nr + 1;
subtype t_key_rounds is natural range 0 to 9;
subtype t_enc_rounds is natural range t_rounds'low to t_rounds'high+1;
subtype t_dec_rounds is natural range t_rounds'low to t_rounds'high+1;
type t_datatable1d is array (0 to 3) of std_logic_vector(7 downto 0);
type t_datatable2d is array (0 to 3) of t_datatable1d;
type t_stable1d is array (0 to 15) of std_logic_vector(7 downto 0);
type t_stable2d is array (0 to 15) of t_stable1d;
type t_key is array (0 to 3) of std_logic_vector(31 downto 0);
type t_rcon is array (0 to 9) of std_logic_vector(7 downto 0);
constant c_sbox : t_stable2d := (
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F
(x"63", x"7c", x"77", x"7b", x"f2", x"6b", x"6f", x"c5", x"30", x"01", x"67", x"2b", x"fe", x"d7", x"ab", x"76"), -- 0
(x"ca", x"82", x"c9", x"7d", x"fa", x"59", x"47", x"f0", x"ad", x"d4", x"a2", x"af", x"9c", x"a4", x"72", x"c0"), -- 1
(x"b7", x"fd", x"93", x"26", x"36", x"3f", x"f7", x"cc", x"34", x"a5", x"e5", x"f1", x"71", x"d8", x"31", x"15"), -- 2
(x"04", x"c7", x"23", x"c3", x"18", x"96", x"05", x"9a", x"07", x"12", x"80", x"e2", x"eb", x"27", x"b2", x"75"), -- 3
(x"09", x"83", x"2c", x"1a", x"1b", x"6e", x"5a", x"a0", x"52", x"3b", x"d6", x"b3", x"29", x"e3", x"2f", x"84"), -- 4
(x"53", x"d1", x"00", x"ed", x"20", x"fc", x"b1", x"5b", x"6a", x"cb", x"be", x"39", x"4a", x"4c", x"58", x"cf"), -- 5
(x"d0", x"ef", x"aa", x"fb", x"43", x"4d", x"33", x"85", x"45", x"f9", x"02", x"7f", x"50", x"3c", x"9f", x"a8"), -- 6
(x"51", x"a3", x"40", x"8f", x"92", x"9d", x"38", x"f5", x"bc", x"b6", x"da", x"21", x"10", x"ff", x"f3", x"d2"), -- 7
(x"cd", x"0c", x"13", x"ec", x"5f", x"97", x"44", x"17", x"c4", x"a7", x"7e", x"3d", x"64", x"5d", x"19", x"73"), -- 8
(x"60", x"81", x"4f", x"dc", x"22", x"2a", x"90", x"88", x"46", x"ee", x"b8", x"14", x"de", x"5e", x"0b", x"db"), -- 9
(x"e0", x"32", x"3a", x"0a", x"49", x"06", x"24", x"5c", x"c2", x"d3", x"ac", x"62", x"91", x"95", x"e4", x"79"), -- A
(x"e7", x"c8", x"37", x"6d", x"8d", x"d5", x"4e", x"a9", x"6c", x"56", x"f4", x"ea", x"65", x"7a", x"ae", x"08"), -- B
(x"ba", x"78", x"25", x"2e", x"1c", x"a6", x"b4", x"c6", x"e8", x"dd", x"74", x"1f", x"4b", x"bd", x"8b", x"8a"), -- C
(x"70", x"3e", x"b5", x"66", x"48", x"03", x"f6", x"0e", x"61", x"35", x"57", x"b9", x"86", x"c1", x"1d", x"9e"), -- D
(x"e1", x"f8", x"98", x"11", x"69", x"d9", x"8e", x"94", x"9b", x"1e", x"87", x"e9", x"ce", x"55", x"28", x"df"), -- E
(x"8c", x"a1", x"89", x"0d", x"bf", x"e6", x"42", x"68", x"41", x"99", x"2d", x"0f", x"b0", x"54", x"bb", x"16")); -- F
constant c_sbox_invers : t_stable2d := (
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F
(x"52", x"09", x"6a", x"d5", x"30", x"36", x"a5", x"38", x"bf", x"40", x"a3", x"9e", x"81", x"f3", x"d7", x"fb"), -- 0
(x"7c", x"e3", x"39", x"82", x"9b", x"2f", x"ff", x"87", x"34", x"8e", x"43", x"44", x"c4", x"de", x"e9", x"cb"), -- 1
(x"54", x"7b", x"94", x"32", x"a6", x"c2", x"23", x"3d", x"ee", x"4c", x"95", x"0b", x"42", x"fa", x"c3", x"4e"), -- 2
(x"08", x"2e", x"a1", x"66", x"28", x"d9", x"24", x"b2", x"76", x"5b", x"a2", x"49", x"6d", x"8b", x"d1", x"25"), -- 3
(x"72", x"f8", x"f6", x"64", x"86", x"68", x"98", x"16", x"d4", x"a4", x"5c", x"cc", x"5d", x"65", x"b6", x"92"), -- 4
(x"6c", x"70", x"48", x"50", x"fd", x"ed", x"b9", x"da", x"5e", x"15", x"46", x"57", x"a7", x"8d", x"9d", x"84"), -- 5
(x"90", x"d8", x"ab", x"00", x"8c", x"bc", x"d3", x"0a", x"f7", x"e4", x"58", x"05", x"b8", x"b3", x"45", x"06"), -- 6
(x"d0", x"2c", x"1e", x"8f", x"ca", x"3f", x"0f", x"02", x"c1", x"af", x"bd", x"03", x"01", x"13", x"8a", x"6b"), -- 7
(x"3a", x"91", x"11", x"41", x"4f", x"67", x"dc", x"ea", x"97", x"f2", x"cf", x"ce", x"f0", x"b4", x"e6", x"73"), -- 8
(x"96", x"ac", x"74", x"22", x"e7", x"ad", x"35", x"85", x"e2", x"f9", x"37", x"e8", x"1c", x"75", x"df", x"6e"), -- 9
(x"47", x"f1", x"1a", x"71", x"1d", x"29", x"c5", x"89", x"6f", x"b7", x"62", x"0e", x"aa", x"18", x"be", x"1b"), -- A
(x"fc", x"56", x"3e", x"4b", x"c6", x"d2", x"79", x"20", x"9a", x"db", x"c0", x"fe", x"78", x"cd", x"5a", x"f4"), -- B
(x"1f", x"dd", x"a8", x"33", x"88", x"07", x"c7", x"31", x"b1", x"12", x"10", x"59", x"27", x"80", x"ec", x"5f"), -- C
(x"60", x"51", x"7f", x"a9", x"19", x"b5", x"4a", x"0d", x"2d", x"e5", x"7a", x"9f", x"93", x"c9", x"9c", x"ef"), -- D
(x"a0", x"e0", x"3b", x"4d", x"ae", x"2a", x"f5", x"b0", x"c8", x"eb", x"bb", x"3c", x"83", x"53", x"99", x"61"), -- E
(x"17", x"2b", x"04", x"7e", x"ba", x"77", x"d6", x"26", x"e1", x"69", x"14", x"63", x"55", x"21", x"0c", x"7d"));-- F
constant c_rcon : t_rcon := (x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36");
function bytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector;
function invbytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector;
function subbytes (input : in t_datatable2d) return t_datatable2d;
function invsubbytes (input : in t_datatable2d) return t_datatable2d;
function shiftrow (input : t_datatable2d) return t_datatable2d;
function invshiftrow (input : t_datatable2d) return t_datatable2d;
function mixcolumns (input : t_datatable2d) return t_datatable2d;
function invmixcolumns (input : t_datatable2d) return t_datatable2d;
function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector;
function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d;
function subword (input : in std_logic_vector(31 downto 0)) return std_logic_vector;
function rotword (input : in std_logic_vector(31 downto 0)) return std_logic_vector;
function key_round (key : t_key; round : t_key_rounds) return t_key;
function set_state (input : in std_logic_vector(0 to 127)) return t_datatable2d;
function get_state (input : in t_datatable2d) return std_logic_vector;
function set_key (input : in std_logic_vector(0 to 127)) return t_key;
function to_string(input : t_datatable2d) return string;
end package aes_pkg;
package body aes_pkg is
function bytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return c_sbox(to_integer(unsigned(input(7 downto 4))))(to_integer(unsigned(input(3 downto 0))));
end function bytesub;
function invbytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return c_sbox_invers(to_integer(unsigned(input(7 downto 4))))(to_integer(unsigned(input(3 downto 0))));
end function invbytesub;
function subbytes (input : in t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
for row in 0 to 3 loop
v_data(row)(column) := c_sbox(to_integer(unsigned(input(row)(column)(7 downto 4))))(to_integer(unsigned(input(row)(column)(3 downto 0))));
end loop;
end loop;
return v_data;
end function subbytes;
function invsubbytes (input : in t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
for row in 0 to 3 loop
v_data(row)(column) := c_sbox_invers(to_integer(unsigned(input(row)(column)(7 downto 4))))(to_integer(unsigned(input(row)(column)(3 downto 0))));
end loop;
end loop;
return v_data;
end function invsubbytes;
function shiftrow (input : t_datatable2d) return t_datatable2d is
variable v_datamatrix : t_datatable2d;
begin
-- copy input in internal matrix
v_datamatrix := input;
-- 2nd row
v_datamatrix(1)(0) := input(1)(1);
v_datamatrix(1)(1) := input(1)(2);
v_datamatrix(1)(2) := input(1)(3);
v_datamatrix(1)(3) := input(1)(0);
-- 3rd row
v_datamatrix(2)(0) := input(2)(2);
v_datamatrix(2)(1) := input(2)(3);
v_datamatrix(2)(2) := input(2)(0);
v_datamatrix(2)(3) := input(2)(1);
-- 4rd row
v_datamatrix(3)(0) := input(3)(3);
v_datamatrix(3)(1) := input(3)(0);
v_datamatrix(3)(2) := input(3)(1);
v_datamatrix(3)(3) := input(3)(2);
-- return manipulated internal matrix
return v_datamatrix;
end function shiftrow;
function invshiftrow (input : t_datatable2d) return t_datatable2d is
variable v_datamatrix : t_datatable2d;
begin
-- copy input in internal matrix
v_datamatrix := input;
-- 2nd row
v_datamatrix(1)(0) := input(1)(3);
v_datamatrix(1)(1) := input(1)(0);
v_datamatrix(1)(2) := input(1)(1);
v_datamatrix(1)(3) := input(1)(2);
-- 3rd row
v_datamatrix(2)(0) := input(2)(2);
v_datamatrix(2)(1) := input(2)(3);
v_datamatrix(2)(2) := input(2)(0);
v_datamatrix(2)(3) := input(2)(1);
-- 4rd row
v_datamatrix(3)(0) := input(3)(1);
v_datamatrix(3)(1) := input(3)(2);
v_datamatrix(3)(2) := input(3)(3);
v_datamatrix(3)(3) := input(3)(0);
-- return manipulated internal matrix
return v_datamatrix;
end function invshiftrow;
-- trivial algorithmus to multiply two bytes in the GF(2^8) finite field defined
-- by the polynomial x^8 + x^4 + x^3 + x + 1
-- taken from http://www.codeplanet.eu/tutorials/cpp/51-advanced-encryption-standard.html
-- and ported to vhdl
function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector is
variable v_a, v_b : std_logic_vector(7 downto 0);
variable v_data : std_logic_vector(7 downto 0) := (others => '0');
variable v_hi_bit_set : boolean;
begin
v_a := a;
v_b := b;
for index in 0 to 7 loop
if(v_b(0) = '1') then
v_data := v_data xor v_a;
end if;
v_hi_bit_set := v_a(7) = '1';
v_a := v_a(6 downto 0) & '0';
if (v_hi_bit_set) then
v_a := v_a xor x"1B";
end if;
v_b := '0' & v_b(7 downto 1);
end loop;
return v_data;
end function gmul;
-- matrix columns manipulation
function mixcolumns (input : t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
v_data(0)(column) := gmul(x"02", input(0)(column)) xor gmul(x"03", input(1)(column)) xor input(2)(column) xor input(3)(column);
v_data(1)(column) := input(0)(column) xor gmul(x"02", input(1)(column)) xor gmul(x"03",input(2)(column)) xor input(3)(column);
v_data(2)(column) := input(0)(column) xor input(1)(column) xor gmul(x"02",input(2)(column)) xor gmul(x"03",input(3)(column));
v_data(3)(column) := gmul(x"03", input(0)(column)) xor input(1)(column) xor input(2)(column) xor gmul(x"02",input(3)(column));
end loop;
return v_data;
end function mixcolumns;
-- matrix columns manipulation
function invmixcolumns (input : t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
v_data(0)(column) := gmul(x"0E", input(0)(column)) xor gmul(x"0B", input(1)(column)) xor gmul(x"0D", input(2)(column)) xor gmul(x"09", input(3)(column));
v_data(1)(column) := gmul(x"09", input(0)(column)) xor gmul(x"0E", input(1)(column)) xor gmul(x"0B", input(2)(column)) xor gmul(x"0D", input(3)(column));
v_data(2)(column) := gmul(x"0D", input(0)(column)) xor gmul(x"09", input(1)(column)) xor gmul(x"0E", input(2)(column)) xor gmul(x"0B", input(3)(column));
v_data(3)(column) := gmul(x"0B", input(0)(column)) xor gmul(x"0D", input(1)(column)) xor gmul(x"09", input(2)(column)) xor gmul(x"0E", input(3)(column));
end loop;
return v_data;
end function invmixcolumns;
function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d is
variable v_data : t_datatable2d;
variable v_key : t_datatable1d;
begin
for column in 0 to 3 loop
v_key := (key(column)(31 downto 24), key(column)(23 downto 16), key(column)(15 downto 8), key(column)(7 downto 0));
for row in 0 to 3 loop
v_data(row)(column) := input(row)(column) xor v_key(row);
end loop;
end loop;
return v_data;
end function addroundkey;
function subword (input : in std_logic_vector(31 downto 0)) return std_logic_vector is
variable v_data : std_logic_vector(31 downto 0);
begin
v_data := bytesub(input(31 downto 24)) & bytesub(input(23 downto 16)) & bytesub(input(15 downto 8)) & bytesub(input(7 downto 0));
return v_data;
end function subword;
function rotword (input : in std_logic_vector(31 downto 0)) return std_logic_vector is
begin
return (input(23 downto 16), input(15 downto 8), input(7 downto 0), input(31 downto 24));
end function rotword;
function key_round (key : t_key; round : t_key_rounds) return t_key is
variable v_key : t_key;
begin
v_key(3) := subword(rotword(key(3))) xor (c_rcon(round) & x"000000");
v_key(0) := key(0) xor v_key(3);
v_key(1) := v_key(0) xor key(1);
v_key(2) := v_key(1) xor key(2);
v_key(3) := v_key(2) xor key(3);
return v_key;
end function key_round;
function set_state (input : in std_logic_vector(0 to 127)) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
for row in 0 to 3 loop
v_data(row)(column) := input(row*8+column*32 to row*8+column*32+7);
end loop;
end loop;
return v_data;
end function set_state;
function get_state (input : in t_datatable2d) return std_logic_vector is
begin
return input(0)(0) & input(1)(0) & input(2)(0) & input(3)(0) &
input(0)(1) & input(1)(1) & input(2)(1) & input(3)(1) &
input(0)(2) & input(1)(2) & input(2)(2) & input(3)(2) &
input(0)(3) & input(1)(3) & input(2)(3) & input(3)(3);
end function get_state;
function set_key (input : in std_logic_vector(0 to 127)) return t_key is
begin
return (input(0 to 31), input(32 to 63), input(64 to 95), input(96 to 127));
end function set_key;
function to_string(input : t_datatable2d) return string is
begin
return '(' & to_hstring(input(0)(0)) & ',' & to_hstring(input(0)(1)) & ',' & to_hstring(input(0)(2)) & ',' & to_hstring(input(0)(3)) & ')' & LF &
'(' & to_hstring(input(1)(0)) & ',' & to_hstring(input(1)(1)) & ',' & to_hstring(input(1)(2)) & ',' & to_hstring(input(1)(3)) & ')' & LF &
'(' & to_hstring(input(2)(0)) & ',' & to_hstring(input(2)(1)) & ',' & to_hstring(input(2)(2)) & ',' & to_hstring(input(2)(3)) & ')' & LF &
'(' & to_hstring(input(3)(0)) & ',' & to_hstring(input(3)(1)) & ',' & to_hstring(input(3)(2)) & ',' & to_hstring(input(3)(3)) & ')';
end function to_string;
end package body aes_pkg;
|
gpl-2.0
|
e06e9cd891a7aeb469eec4eccf096a87
| 0.560799 | 2.584608 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_crossbar.vhd
| 1 | 44,293 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Crossbar Core. This core should not be
--! utilized directly.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.all;
--! The Crossbar Core is an interconnect developed so that
--! one or more Slave AXI4-Full interfaces can perform
--! transactions with one or more Master AXI4-Full interfaces.
--!
--! It is critical to have an understanding of the AXI4-Full protocol
--! when it comes to utilizing this Crossbar. Additionally, the Crossbar Core
--! should not be instantiated directly. Instead, a Crossbar Wrapper should
--! be generated with the crossgen python2.7 application. Not only does the
--! Wrapper provide more intuitive interfaces to each of the Slave and Master
--! interfaces, but necessary multiplexers are added to ensure all outputs
--! do not return infinite impedance.
--!
--! The Crossbar is built such that split transactions are supported. Requesting
--! interfaces, such as Slave Address interfaces and Master Response interfaces, can
--! perform a request by presenting either an Address or an ID with an asserted valid
--! signal. Static priorities are used; referring to the Crossbar Wrapper, requesting
--! interfaces closest to the top of the component declaration are given priority over
--! lower interfaces.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from here since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_crossbar is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Full address width.
axi_data_width : integer := 32; --! Defines the AXI4-Full data width.
axi_master_amount : integer := 2; --! Defines the number of Master AXI4-Full interfaces.
axi_slave_id_width : integer := 2; --! Defines the ID width of each Slave AXI4-Full interface.
axi_slave_amount : integer := 4; --! Defines the number of Slave AXI4-Full interfaces.
axi_master_base_address : std_logic_vector := X"4000000000000000"; --! Defines the base addresses that refer to the address space of each Master AXI4-Full interface. The position of the address in the address vector corresponds to the position of the Master interface in the signals vector.
axi_master_high_address : std_logic_vector := X"ffffffff3fffffff" --! Defines the high addresses that refer to the address space of each Master AXI4-Full interface. The position of the address in the address vector corresponds to the position of the Master interface in the signals vector.
);
port (
aclk : in std_logic;
aresetn : in std_logic;
s_address_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Address Write interfaces are connected to a Master interface.
s_data_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Data Write interfaces are connected to a Master interface.
s_response_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Response Write interfaces are connected to a Master interface.
s_address_read_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Address Read interfaces are connected to a Master interface.
s_data_read_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Data Read interfaces are connected to a Master interface.
m_address_write_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Address Write interfaces are connected to a Slave interface.
m_data_write_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Data Write interfaces are connected to a Slave interface.
m_response_write_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Response Write interfaces are connected to a Slave interface.
m_address_read_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Address Read interfaces are connected to a Slave interface.
m_data_read_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Data Read interfaces are connected to a Slave interface.
s_axi_awid : in std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
s_axi_awlen : in std_logic_vector(axi_slave_amount*8-1 downto 0);
s_axi_awsize : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_awburst : in std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_awlock : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_awcache : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awprot : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_awqos : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awregion : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_awready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wdata : in std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
s_axi_wlast : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bid : out std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_bresp : out std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_bvalid : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arid : in std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
s_axi_arlen : in std_logic_vector(axi_slave_amount*8-1 downto 0);
s_axi_arsize : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_arburst : in std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_arlock : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arcache : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arprot : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_arqos : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arregion : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rid : out std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_rdata : out std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_rlast : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rvalid : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_awid : out std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_awaddr : out std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
m_axi_awlen : out std_logic_vector(axi_master_amount*8-1 downto 0);
m_axi_awsize : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_awburst : out std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_awlock : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_awcache : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awprot : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_awqos : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awregion : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_awready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wdata : out std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
m_axi_wstrb : out std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
m_axi_wlast : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bid : in std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_bresp : in std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_bvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bready : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arid : out std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_araddr : out std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
m_axi_arlen : out std_logic_vector(axi_master_amount*8-1 downto 0);
m_axi_arsize : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_arburst : out std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_arlock : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arcache : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arprot : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_arqos : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arregion : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rid : in std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_rdata : in std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
m_axi_rresp : in std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_rlast : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rready : out std_logic_vector(axi_master_amount*1-1 downto 0)
);
end plasoc_crossbar;
architecture Behavioral of plasoc_crossbar is
constant axi_slave_iden_width : integer := clogb2(axi_slave_amount);
constant axi_master_iden_width : integer := clogb2(axi_master_amount);
constant axi_master_id_width : integer := axi_slave_iden_width+axi_slave_id_width;
component plasoc_crossbar_base is
generic (
width : integer := 16;
input_amount : integer := 2;
output_amount : integer := 2);
port (
inputs : in std_logic_vector(width*input_amount-1 downto 0);
enables : in std_logic_vector(input_amount*output_amount-1 downto 0);
outputs : out std_logic_vector(width*output_amount-1 downto 0));
end component;
component plasoc_crossbar_axi4_write_cntrl is
generic (
axi_slave_amount : integer := 2;
axi_master_amount : integer := 4);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_write_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0);
axi_write_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0);
axi_address_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_data_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_response_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
s_axi_awvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wlast : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_awready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bvalid : in std_logic_vector(axi_master_amount*1-1 downto 0));
end component;
component plasoc_crossbar_axi4_read_cntrl is
generic (
axi_slave_amount : integer := 2;
axi_master_amount : integer := 4);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_read_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0);
axi_read_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0);
axi_address_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_data_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
s_axi_arvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_arready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rlast : in std_logic_vector(axi_master_amount*1-1 downto 0));
end component;
function set_crossbar_enables( enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable s2m_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
variable m2s_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
for each_master in 0 to axi_master_amount-1 loop
if enables(each_slave+each_master*axi_slave_amount)='1' then
s2m_enables(each_slave+each_master*axi_slave_amount) := '1';
m2s_enables(each_master+each_slave*axi_master_amount) := '1';
else
s2m_enables(each_slave+each_master*axi_slave_amount) := '0';
m2s_enables(each_master+each_slave*axi_master_amount) := '0';
end if;
end loop;
end loop;
cross_enables(cross_enables_width-1 downto 0) := s2m_enables;
cross_enables(2*cross_enables_width-1 downto cross_enables_width) := m2s_enables;
return cross_enables;
end;
function set_connected( enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable slave_connected : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
variable master_connected : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
variable or_reduced : Boolean;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := False;
for each_master in 0 to axi_master_amount-1 loop
or_reduced := or_reduced or (enables(each_slave+each_master*axi_slave_amount)='1');
end loop;
if or_reduced then
slave_connected(each_slave) := '1';
end if;
end loop;
for each_master in 0 to axi_master_amount-1 loop
or_reduced := False;
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := or_reduced or (enables(each_slave+each_master*axi_slave_amount)='1');
end loop;
if or_reduced then
master_connected(each_master) := '1';
end if;
end loop;
connected(axi_slave_amount-1 downto 0) := slave_connected;
connected(connected_width-1 downto axi_slave_amount) := master_connected;
return connected;
end;
function decode_master_iden (
address : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
base_addresses : in std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
high_addresses : in std_logic_vector(axi_master_amount*axi_address_width-1 downto 0))
return std_logic_vector is
variable master_iden_buff : std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0) := (others=>'0');
variable slave_address : std_logic_vector(axi_address_width-1 downto 0);
variable master_base_address : std_logic_vector(axi_address_width-1 downto 0);
variable master_high_address : std_logic_vector(axi_address_width-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
slave_address := address((1+each_slave)*axi_address_width-1 downto each_slave*axi_address_width);
for each_master in 0 to axi_master_amount-1 loop
master_base_address := base_addresses((1+each_master)*axi_address_width-1 downto each_master*axi_address_width);
master_high_address := high_addresses((1+each_master)*axi_address_width-1 downto each_master*axi_address_width);
if slave_address>=master_base_address and slave_address<=master_high_address then
master_iden_buff((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width) :=
std_logic_vector(to_unsigned(each_master,axi_master_iden_width));
end if;
end loop;
end loop;
return master_iden_buff;
end;
signal axi_read_slave_iden : std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
signal axi_write_slave_iden : std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
signal axi_read_master_iden : std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
signal axi_write_master_iden : std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
signal s_axi_awid_full : std_logic_vector(axi_slave_amount*axi_master_id_width-1 downto 0);
signal s_axi_arid_full : std_logic_vector(axi_slave_amount*axi_master_id_width-1 downto 0);
signal m_axi_rid_from_slave : std_logic_vector(axi_master_amount*axi_slave_id_width-1 downto 0);
signal m_axi_bid_from_slave : std_logic_vector(axi_master_amount*axi_slave_id_width-1 downto 0);
signal axi_address_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_s2m_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_m2s_write_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_data_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_s2m_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_m2s_write_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_response_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_response_s2m_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_response_m2s_write_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_address_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_s2m_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_m2s_read_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_data_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_s2m_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_m2s_read_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal s_address_write_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_address_write_connected <= s_address_write_connected_buff;
s_data_write_connected <= s_data_write_connected_buff;
s_response_write_connected <= s_response_write_connected_buff;
s_address_read_connected <= s_address_read_connected_buff;
s_data_read_connected <= s_data_read_connected_buff;
m_address_write_connected <= m_address_write_connected_buff;
m_data_write_connected <= m_data_write_connected_buff;
m_response_write_connected <= m_response_write_connected_buff;
m_address_read_connected <= m_address_read_connected_buff;
m_data_read_connected <= m_data_read_connected_buff;
plasoc_crossbar_axi4_write_cntrl_inst : plasoc_crossbar_axi4_write_cntrl
generic map (
axi_slave_amount => axi_slave_amount,
axi_master_amount => axi_master_amount)
port map (
aclk => aclk,
aresetn => aresetn,
axi_write_master_iden => axi_write_master_iden,
axi_write_slave_iden => axi_write_slave_iden,
axi_address_write_enables => axi_address_write_enables,
axi_data_write_enables => axi_data_write_enables,
axi_response_write_enables => axi_response_write_enables,
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
s_axi_wlast => s_axi_wlast,
s_axi_bready => s_axi_bready,
m_axi_awready => m_axi_awready,
m_axi_wready => m_axi_wready,
m_axi_bvalid => m_axi_bvalid);
plasoc_crossbar_axi4_read_cntrl_inst : plasoc_crossbar_axi4_read_cntrl
generic map (
axi_slave_amount => axi_slave_amount,
axi_master_amount => axi_master_amount)
port map (
aclk => aclk,
aresetn => aresetn,
axi_read_master_iden => axi_read_master_iden,
axi_read_slave_iden => axi_read_slave_iden,
axi_address_read_enables => axi_address_read_enables,
axi_data_read_enables => axi_data_read_enables,
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
m_axi_arready => m_axi_arready,
m_axi_rvalid => m_axi_rvalid,
m_axi_rlast => m_axi_rlast);
generate_slave_idassigns:
for each_slave in 0 to axi_slave_amount-1 generate
s_axi_awid_full((1+each_slave)*axi_master_id_width-1 downto (1+each_slave)*axi_master_id_width-axi_slave_iden_width) <=
std_logic_vector(to_unsigned(each_slave,axi_slave_iden_width));
s_axi_awid_full(axi_slave_id_width-1+each_slave*axi_master_id_width downto 0+each_slave*axi_master_id_width) <=
s_axi_awid((1+each_slave)*axi_slave_id_width-1 downto 0+each_slave*axi_slave_id_width);
s_axi_arid_full((1+each_slave)*axi_master_id_width-1 downto (1+each_slave)*axi_master_id_width-axi_slave_iden_width) <=
std_logic_vector(to_unsigned(each_slave,axi_slave_iden_width));
s_axi_arid_full(axi_slave_id_width-1+each_slave*axi_master_id_width downto 0+each_slave*axi_master_id_width) <=
s_axi_arid((1+each_slave)*axi_slave_id_width-1 downto 0+each_slave*axi_slave_id_width);
end generate generate_slave_idassigns;
generate_master_idassigns:
for each_master in 0 to axi_master_amount-1 generate
axi_read_slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width) <=
m_axi_rid((1+each_master)*axi_master_id_width-1 downto (1+each_master)*axi_master_id_width-axi_slave_iden_width);
m_axi_rid_from_slave((1+each_master)*axi_slave_id_width-1 downto each_master*axi_slave_id_width) <=
m_axi_rid(axi_slave_id_width-1+each_master*axi_master_id_width downto 0+each_master*axi_master_id_width);
axi_write_slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width) <=
m_axi_bid((1+each_master)*axi_master_id_width-1 downto (1+each_master)*axi_master_id_width-axi_slave_iden_width);
m_axi_bid_from_slave((1+each_master)*axi_slave_id_width-1 downto each_master*axi_slave_id_width) <=
m_axi_bid(axi_slave_id_width-1+each_master*axi_master_id_width downto 0+each_master*axi_master_id_width);
end generate generate_master_idassigns;
process (s_axi_awaddr)
begin
axi_write_master_iden <= decode_master_iden(s_axi_awaddr,axi_master_base_address,axi_master_high_address);
end process;
process (s_axi_araddr)
begin
axi_read_master_iden <= decode_master_iden(s_axi_araddr,axi_master_base_address,axi_master_high_address);
end process;
process (axi_address_write_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_address_write_enables);
s_address_write_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_address_write_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_data_write_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_data_write_enables);
s_data_write_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_data_write_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_response_write_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_response_write_enables);
s_response_write_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_response_write_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_address_read_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_address_read_enables);
s_address_read_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_address_read_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_data_read_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_data_read_enables);
s_data_read_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_data_read_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_address_write_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_address_write_enables);
axi_address_s2m_write_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_address_m2s_write_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_data_write_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_data_write_enables);
axi_data_s2m_write_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_data_m2s_write_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_response_write_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_response_write_enables);
axi_response_s2m_write_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_response_m2s_write_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_address_read_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_address_read_enables);
axi_address_s2m_read_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_address_m2s_read_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_data_read_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_data_read_enables);
axi_data_s2m_read_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_data_m2s_read_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
awid_cross_inst : plasoc_crossbar_base
generic map (width => axi_master_id_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awid_full,enables => axi_address_s2m_write_enables,outputs => m_axi_awid);
awaddr_cross_inst : plasoc_crossbar_base
generic map (width => axi_address_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awaddr,enables => axi_address_s2m_write_enables,outputs => m_axi_awaddr);
awlen_cross_inst : plasoc_crossbar_base
generic map (width => 8,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awlen,enables => axi_address_s2m_write_enables,outputs => m_axi_awlen);
awsize_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awsize,enables => axi_address_s2m_write_enables,outputs => m_axi_awsize);
awburst_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awburst,enables => axi_address_s2m_write_enables,outputs => m_axi_awburst);
awlock_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awlock,enables => axi_address_s2m_write_enables,outputs => m_axi_awlock);
awcache_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awcache,enables => axi_address_s2m_write_enables,outputs => m_axi_awcache);
awprot_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awprot,enables => axi_address_s2m_write_enables,outputs => m_axi_awprot);
awqos_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awqos,enables => axi_address_s2m_write_enables,outputs => m_axi_awqos);
awregion_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awregion,enables => axi_address_s2m_write_enables,outputs => m_axi_awregion);
awvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awvalid,enables => axi_address_s2m_write_enables,outputs => m_axi_awvalid);
awready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_awready,enables => axi_address_m2s_write_enables,outputs => s_axi_awready);
wdata_cross_inst : plasoc_crossbar_base
generic map (width => axi_data_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wdata,enables => axi_data_s2m_write_enables,outputs => m_axi_wdata);
wstrb_cross_inst : plasoc_crossbar_base
generic map (width => axi_data_width/8,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wstrb,enables => axi_data_s2m_write_enables,outputs => m_axi_wstrb);
wlast_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wlast,enables => axi_data_s2m_write_enables,outputs => m_axi_wlast);
wvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wvalid,enables => axi_data_s2m_write_enables,outputs => m_axi_wvalid);
wready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_wready,enables => axi_data_m2s_write_enables,outputs => s_axi_wready);
bid_cross_inst : plasoc_crossbar_base
generic map (width => axi_slave_id_width,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_bid_from_slave,enables => axi_response_m2s_write_enables,outputs => s_axi_bid);
bresp_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_bresp,enables => axi_response_m2s_write_enables,outputs => s_axi_bresp);
bvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_bvalid,enables => axi_response_m2s_write_enables,outputs => s_axi_bvalid);
bready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_bready,enables => axi_response_s2m_write_enables,outputs => m_axi_bready);
arid_cross_inst : plasoc_crossbar_base
generic map (width => axi_master_id_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arid_full,enables => axi_address_s2m_read_enables,outputs => m_axi_arid);
araddr_cross_inst : plasoc_crossbar_base
generic map (width => axi_address_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_araddr,enables => axi_address_s2m_read_enables,outputs => m_axi_araddr);
arlen_cross_inst : plasoc_crossbar_base
generic map (width => 8,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arlen,enables => axi_address_s2m_read_enables,outputs => m_axi_arlen);
arsize_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arsize,enables => axi_address_s2m_read_enables,outputs => m_axi_arsize);
arburst_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arburst,enables => axi_address_s2m_read_enables,outputs => m_axi_arburst);
arlock_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arlock,enables => axi_address_s2m_read_enables,outputs => m_axi_arlock);
arcache_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arcache,enables => axi_address_s2m_read_enables,outputs => m_axi_arcache);
arprot_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arprot,enables => axi_address_s2m_read_enables,outputs => m_axi_arprot);
arqos_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arqos,enables => axi_address_s2m_read_enables,outputs => m_axi_arqos);
arregion_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arregion,enables => axi_address_s2m_read_enables,outputs => m_axi_arregion);
arvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arvalid,enables => axi_address_s2m_read_enables,outputs => m_axi_arvalid);
arready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_arready,enables => axi_address_m2s_read_enables,outputs => s_axi_arready);
rid_cross_inst : plasoc_crossbar_base
generic map (width => axi_slave_id_width,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rid_from_slave,enables => axi_data_m2s_read_enables,outputs => s_axi_rid);
rdata_cross_inst : plasoc_crossbar_base
generic map (width => axi_data_width,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rdata,enables => axi_data_m2s_read_enables,outputs => s_axi_rdata);
rresp_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rresp,enables => axi_data_m2s_read_enables,outputs => s_axi_rresp);
rlast_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rlast,enables => axi_data_m2s_read_enables,outputs => s_axi_rlast);
rvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rvalid,enables => axi_data_m2s_read_enables,outputs => s_axi_rvalid);
rready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_rready,enables => axi_data_s2m_read_enables,outputs => m_axi_rready);
end Behavioral;
|
mit
|
89296bf5b510e17cbb87d3f126995122
| 0.634841 | 3.639224 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_fifo.vhd
| 4 | 24,997 |
-------------------------------------------------------------------------------
-- axi_datamover_fifo.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_afifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 )))
or
(C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 0 )
generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_datamover_v5_1_9.axi_datamover_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Ainit_Rd_clk => fifo_async_rd_reset ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
bsd-3-clause
|
5c88fe320f77b5eb76eb2f7f365c5f7f
| 0.41733 | 4.482159 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd
| 4 | 51,651 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_8.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_8.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_8.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_8.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
bsd-3-clause
|
5618e772d241cae0b383a3676ffbbf43
| 0.406226 | 4.221577 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/uart16550.vhdl
| 1 | 2,721 |
-- Memory mapped 16550 UART
-- Acutally, it's won't even be a proper 8250, it should at least support
-- 9600 baud 8N1 with Tx, Rx, data_available, tx_ready memory-mapped
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
entity uart16550 is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- pins
tx : out std_logic;
rx : in std_logic
);
end uart16550;
architecture behav of uart16550 is
constant reading : std_logic := '0';
constant writing : std_logic := '1';
begin
dout <= HI_Z;
process(clk)
begin
if rising_edge(clk) and size /= "00" then
-- A 16550 UART spans 7 registers
dout <= NEG_ONE;
case addr(2 downto 0) is
when "000" => -- union { Tx, Rx, baud_lo }
null;
when "001" => -- union { baud_hi, int_enable }
null;
when "010" => -- union { int_status, fifo_ctrl }
null;
when "011" => -- struct LINE_CTRL { set baud, config }
null;
when "100" => -- struct MODEM_CTRL
null;
when "101" => -- struct LINE_STATUS { tx_empty, data_available }
null;
when "110" => -- struct MODEM_STATUS
null;
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end;
--
--struct uart16550 {
-- union {
-- writeonly uint8_t tx;
-- readonly uint8_t rx;
-- uint8_t baud_div_lo;
-- UART_PAD
-- };
-- union {
-- uint8_t int_enable;
-- uint8_t baud_div_hi;
-- UART_PAD
-- };
--
-- union {
-- uint8_t int_status;
-- uint8_t fifo_ctrl;
-- UART_PAD
-- };
--
-- writeonly struct {
-- union {
-- uint8_t set_baud : 1;
-- uint8_t : 2;
-- uint8_t config : 5;
-- UART_PAD
-- };
-- } line_ctrl;
--
-- writeonly union {uint8_t modem_ctrl; UART_PAD};
--
-- readonly union {struct {
-- uint8_t : 2;
-- uint8_t tx_empty : 1;
-- uint8_t : 4;
-- uint8_t data_available : 1;
-- }; UART_PAD } line_status;
--
-- readonly union{uint8_t modem_status; UART_PAD};
--};
|
gpl-3.0
|
86cda8782bfc6f5c5ab74bee88001d62
| 0.455715 | 3.520052 | false | false | false | false |
Apollinaire/GameOfLife_FPGA
|
sources/Cell.vhd
| 1 | 2,167 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.01.2017 10:06:34
-- Design Name:
-- Module Name: Cell - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Cell is
Generic (CELL_INIT : STD_LOGIC := '0');
Port ( CLK : in STD_LOGIC;
CLK_E : in STD_LOGIC;
PROX : in STD_LOGIC_VECTOR(7 downto 0);
RST : in STD_LOGIC;
RST_VALUE : in STD_LOGIC;
STATE : out STD_LOGIC);
end Cell;
architecture Behavioral of Cell is
-- The state of the cell needs to be read and written so an internal signal is used
signal internalState : STD_LOGIC := CELL_INIT;
signal count : integer range 0 to 8 := 0;
signal count0 : integer range 0 to 1 := 0;
signal count1 : integer range 0 to 1 := 0;
signal count2 : integer range 0 to 1 := 0;
signal count3 : integer range 0 to 1 := 0;
signal count4 : integer range 0 to 1 := 0;
signal count5 : integer range 0 to 1 := 0;
signal count6 : integer range 0 to 1 := 0;
signal count7 : integer range 0 to 1 := 0;
begin
STATE <= internalState;
count0 <= 1 when PROX(0)='1' else 0;
count1 <= 1 when PROX(1)='1' else 0;
count2 <= 1 when PROX(2)='1' else 0;
count3 <= 1 when PROX(3)='1' else 0;
count4 <= 1 when PROX(4)='1' else 0;
count5 <= 1 when PROX(5)='1' else 0;
count6 <= 1 when PROX(6)='1' else 0;
count7 <= 1 when PROX(7)='1' else 0;
count <= count0+count1+count2+count3+count4+count5+count6+count7;
process(CLK, CLK_E, RST, RST_VALUE, PROX) --the rules for every cell of the GoL
begin
if (RST = '1') then
internalState <= RST_VALUE;
elsif (CLK_E'event and CLK_E='1') then
if (count=3) then
internalState <= '1';
elsif (count=2 and internalState = '1') then
internalState <= '1';
else
internalState <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
f908a3b457362c85981b267b75f27a1d
| 0.583756 | 3.354489 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/vga_controller.vhdl
| 1 | 5,049 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_vga is
port(
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
memclk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- I/O
vgaclk, rst : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic
);
end mmio_vga;
architecture mmio of mmio_vga is
component sync
port (
clk : in std_logic;
en : in std_logic;
hsync, vsync : out std_logic;
retracing : out std_logic;
col : out std_logic_vector (9 downto 0); -- 640 = 10_1000_0000b
row : out std_logic_vector (8 downto 0) -- 480 = 1_1110_0000b
);
end component;
component vram
port (
x : in std_logic_vector (9 downto 0); -- 640 = 10_1000_0000b
y : in std_logic_vector (8 downto 0); -- 480 = 1_1110_0000b
retracing : in std_logic;
-- I/O
r, g, b : out std_logic_vector (3 downto 0);
-- Bus access to VRAM
bus_addr : in addr_t;
bus_din : in word_t;
bus_dout : out word_t;
bus_wr : in std_logic;
bus_clk : in std_logic
);
end component;
constant reading : std_logic := '0';
constant writing : std_logic := '1';
signal retracing : std_logic;
signal row : std_logic_vector (8 downto 0);
signal col : std_logic_vector (9 downto 0);
-- XXX The original idea was having multiple VGA modes
-- Each VGA mode consists of a tuple of a Sync mode
-- which defines the control signals and thereby the resolution
-- and a shader, which accesses the VRAM in a specific way
-- e.g. you can pair a 1024x768 sync with a shader that use a color palette
-- While this would be cleaner, I think there's no way around having the
-- shader work at double the VGA frequency, so it may access the VRAM.
-- As I got no time for that, the mode code is commented out.
--subtype vga_sync_t is std_logic_vector(1 downto 0);
--subtype vga_shader_t is std_logic_vector(1 downto 0);
--constant VGA_SYNC_NONE : vga_sync_t := (others => '0');
--constant VGA_VRAM_NONE : vga_shader_t := (others => '0');
--constant VGA_SYNC_640_480 : vga_sync_t := "01";
--constant VGA_SHADER_640_480 : vga_shader_t := "01";
--type vga_mode_t is record sync : vga_sync_t; shader : vga_shader_t; end record;
--type vga_mode_table_t is array (natural range <>) of vga_mode_t;
--constant modes : vga_mode_table_t := (
--(VGA_SYNC_NONE, VGA_SHADER_NONE),
--(VGA_SYNC_640_480, VGA_SHADER_640_480),
--(VGA_SYNC_NONE, VGA_SHADER_NONE)
--);
signal mode_idx : std_logic_vector(1 downto 0) := "01";
signal bus_access_vram : std_logic := '0';
signal bus_vram_din, bus_vram_dout, data_out : word_t;
signal bus_vram_addr : word_t;
signal bus_writing_vram : ctrl_t := '0';
begin
-- FIXME: make shader selectable
inst_sync_640_480: sync port map (clk => vgaclk, en => '1', hsync => hsync, vsync => vsync, retracing => retracing, col => col, row => row);
--inst_vram: dualport_bram generic map(WORD_WIDTH => 8, ADDR_WIDTH => 8)
bus_writing_vram <= wr and bus_access_vram and en;
bus_vram_din <= din when bus_access_vram = '1';
bus_vram_addr <= addr when bus_access_vram = '1';
inst_vram: vram
port map (x => col, y => row, retracing => retracing,
r => r, g => g, b => b,
bus_addr => bus_vram_addr,
bus_din => bus_vram_din,
bus_dout => bus_vram_dout,
bus_wr => bus_writing_vram,
bus_clk => memclk
);
dout <= data_out when en = '1' and wr = '0' and bus_access_vram = '0' else
bus_vram_dout when en = '1' and wr = '0' and bus_access_vram = '1' else HI_Z;
process(memclk)
begin
if rising_edge(memclk) and en = '1' and size /= "00" then
case addr(31 downto 24) is
-- 0x14xx_xxxx is IO configuration space
-- TODO use work.memory_map.mmap instead of hardcoded address base
when X"14"=>
bus_access_vram <= '0';
case addr(3 downto 0) is
when X"0" => -- vga_mode
if wr = writing then
mode_idx <= din(mode_idx'High downto mode_idx'Low);
else
zeroextend(data_out, mode_idx);
end if;
when others => null;
end case;
-- 0x10xx_xxxx is IO memory space
when X"10" => -- forward to BRAM
bus_access_vram <= '1';
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end mmio;
|
gpl-3.0
|
c26d1c98c56d901603d1a2c0759512e8
| 0.553971 | 3.420732 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/dvi2rgb_v1_7/src/dvi2rgb.vhd
| 1 | 11,119 |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "900p_edid.data"; -- Select EDID file to use
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(15 downto 8) <= pDataIn(1); -- green is channel 1
pData(7 downto 0) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
bsd-3-clause
|
64e907a6e9199856822a3c7498caac1d
| 0.606619 | 4.553235 | false | false | false | false |
Ttl/pic16f84
|
decoder.vhd
| 1 | 6,050 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
use IEEE.NUMERIC_STD.ALL;
-- Decocing unit. Outputs control signals for datapath control.
entity decoder is
Port ( instr : in STD_LOGIC_VECTOR(13 downto 0);
bmux, rwmux, branch, writew, skip, retrn : out STD_LOGIC;
pc_push : out STD_LOGIC;
amux : out std_logic_vector(1 downto 0);
aluop : out alu_ctrl;
status_write : out std_logic_vector(4 downto 0);
retfie : out std_logic);
end decoder;
architecture Behavioral of decoder is
signal z_write, dc_write, c_write, to_write, pd_write : std_logic;
begin
process(instr)
-- ALU A mux: 00 : instr, 01 : ram ,10 : 0, 11 : 1
-- ALU B mux: 0 : W, 1 : 1
alias wf_bit is instr(7);
begin
amux <= "00";
retfie <= '0';
bmux <= '0';
rwmux <= '0';
branch <= '0';
writew <= '0';
aluop <= A_PASSA;
skip <= '0';
retrn <= '0';
pc_push <= '0';
-- Status register update flags
z_write <= '0';
c_write <= '0';
dc_write <= '0';
to_write <= '0';
pd_write <= '0';
case instr(13 downto 8) is
--addwf f,d
when "000111" =>
amux <= "01"; -- ram
writew <= not wf_bit;
rwmux <= wf_bit;
aluop <= A_ADD;
c_write <= '1';
dc_write <= '1';
z_write <= '1';
-- andwf f,d
when "000101" =>
amux <= "01"; -- ram
writew <= not wf_bit;
rwmux <= wf_bit;
aluop <= A_AND;
z_write <= '1';
-- clrf f/clrw -
when "000001" =>
amux <= "10"; -- 0
writew <= not wf_bit;
rwmux <= wf_bit;
aluop <= A_PASSA; -- pass A
z_write <= '1';
-- comf f,d
when "001001" =>
amux <= "01";
aluop <= A_NOTA; -- NOT A
writew <= not wf_bit;
rwmux <= wf_bit;
z_write <= '1';
-- decf f,d
when "000011" =>
amux <= "01";
writew <= not wf_bit;
rwmux <= wf_bit;
z_write <= '1';
bmux <= '1';
aluop <= A_SUBAB;
-- decfsz f,d
when "001011" =>
amux <= "01";
writew <= not wf_bit;
rwmux <= wf_bit;
bmux <= '1';
aluop <= A_SUBAB;
skip <= '1';
-- incf f,d
when "001010" =>
amux <= "01";
writew <= not wf_bit;
rwmux <= wf_bit;
z_write <= '1';
bmux <= '1';
aluop <= A_ADD;
-- incfsz f,d
when "001111" =>
amux <= "01";
writew <= not wf_bit;
rwmux <= wf_bit;
bmux <= '1';
aluop <= A_ADD;
skip <= '1';
-- iorwf f,d
when "000100" =>
amux <= "01"; -- ram
writew <= not wf_bit;
rwmux <= wf_bit;
aluop <= A_OR;
z_write <= '1';
-- movf
when "001000" =>
amux <= "01"; -- ram
writew <= not wf_bit;
z_write <= '1';
-- nop is in others
-- rlf f,d
when "001101" =>
amux <= "01";
aluop <= A_RLFA;
writew <= not wf_bit;
rwmux <= wf_bit;
c_write <= '1';
-- rrf f,d
when "001100" =>
amux <= "01";
aluop <= A_RRFA;
writew <= not wf_bit;
rwmux <= wf_bit;
c_write <= '1';
--subwf f,d
when "000010" =>
amux <= "01"; -- ram
writew <= not wf_bit;
rwmux <= wf_bit;
aluop <= A_SUBAB;
c_write <= '1';
dc_write <= '1';
z_write <= '1';
--swapf f,d
when "001110" =>
amux <= "01"; -- ram
writew <= not wf_bit;
rwmux <= wf_bit;
aluop <= A_SWAPA;
-- xorwf f,d
when "000110" =>
amux <= "01"; -- ram
writew <= not wf_bit;
rwmux <= wf_bit;
aluop <= A_XOR;
z_write <= '1';
-- Literal operations
-- addlw, k
when "111111"|"111110" =>
writew <= '1';
aluop <= A_ADD;
c_write <= '1';
dc_write <= '1';
z_write <= '1';
-- andlw, k
when "111001" =>
aluop <= A_AND;
z_write <= '1';
writew <= '1';
-- iorlw, k
when "111000" =>
aluop <= A_OR;
z_write <= '1';
writew <= '1';
-- xorlw, k
when "111010" =>
aluop <= A_XOR;
z_write <= '1';
writew <= '1';
-- sublw, k
when "111100"|"111101" =>
writew <= '1';
aluop <= A_SUBAB;
c_write <= '1';
dc_write <= '1';
z_write <= '1';
-- movlw
when "110000"|"110001"|"110010"|"110011" =>
writew <= '1';
-- retlw
when "110100"|"110101"|"110110"|"110111" =>
retrn <= '1';
writew <= '1';
-- Misc operations
when others =>
-- goto
if instr(13 downto 11) = "101" then
branch <= '1';
end if;
-- nop
if instr(13 downto 7) = "0000000"
and instr(4 downto 0) = "00000" then
-- Nothing
end if;
-- bcf f,b / bsf f,b
if instr(13 downto 11) = "010" then
aluop <= A_BITSET;
amux <= "01"; --ram
rwmux <= '1';
end if;
-- bcfsc f,d / bsfss f,d
if instr(13 downto 11) = "011" then
aluop <= A_BITTST;
amux <= "01"; --ram
skip <= '1';
end if;
-- call
if instr(13 downto 11) = "100" then
branch <= '1';
pc_push <= '1';
end if;
-- movwf
if instr(13 downto 7) = "0000001" then
amux <= "10"; -- 0
rwmux <= '1';
aluop <= A_ADD; -- add
end if;
-- return
if instr = "00000000001000" then
retrn <= '1';
end if;
-- retfie
if instr = "00000000001001" then
retrn <= '1';
retfie <= '1';
end if;
end case;
end process;
status_write <= to_write&pd_write&z_write&dc_write&c_write;
end Behavioral;
|
lgpl-3.0
|
a2a5b290dcd6085fe9311cf14ffea7f6
| 0.421818 | 3.408451 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/axi_quad_spi.vhd
| 2 | 82,124 |
-------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
use UNISIM.vcomponents.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
-------------------------------------------------------------------------------
entity axi_quad_spi is
generic(
-- Async_Clk parameter is added only for Vivado, it is not used in the design, this is
-- NON HDL parameter
Async_Clk : integer := 0;
-- General Parameters
C_FAMILY : string := "virtex7";
C_SELECT_XPM : integer := 1;
C_SUB_FAMILY : string := "virtex7";
C_INSTANCE : string := "axi_quad_spi_inst";
-------------------------
C_SPI_MEM_ADDR_BITS : integer := 24; -- allowed values are 24 or 32 only and used in XIP mode
C_TYPE_OF_AXI4_INTERFACE : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
C_XIP_MODE : integer range 0 to 1 := 0;--default NON XIP Mode
C_UC_FAMILY : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- 3 - spansion
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters *as max address is 7c, only 7 address bits are used
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters *as max 24 bits of address are supported on SPI interface, only 24 address bits are used
C_S_AXI4_ADDR_WIDTH : integer ;--range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4 ;
C_SHARED_STARTUP : integer range 0 to 1 := 0;
-------------------------
-- To FIX CR# 685366, below lines are added again in RTL (Vivado Requirement), but these parameters are not used in the core RTL
C_S_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_LSB_STUP : integer range 0 to 1 := 0
);
port(
-- external async clock for SPI interface logic
ext_spi_clk : in std_logic;
-- axi4 lite interface clk and reset signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi4 full interface clk and reset signals
s_axi4_aclk : in std_logic;
s_axi4_aresetn : in std_logic;
-------------------------------
-------------------------------
--*axi4 lite port interface* --
-------------------------------
-------------------------------
-- axi write address channel signals
---------------
s_axi_awaddr : in std_logic_vector (6 downto 0);--((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
---------------
-- axi write data channel signals
---------------
s_axi_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
---------------
-- axi write response channel signals
---------------
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_araddr : in std_logic_vector(6 downto 0); -- ((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_rdata : out std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-------------------------------
-------------------------------
--*axi4 full port interface* --
-------------------------------
------------------------------------
-- axi write address Channel Signals
------------------------------------
s_axi4_awid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_awaddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0); --((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_awlen : in std_logic_vector(7 downto 0);
s_axi4_awsize : in std_logic_vector(2 downto 0);
s_axi4_awburst : in std_logic_vector(1 downto 0);
s_axi4_awlock : in std_logic; -- not supported in design
s_axi4_awcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_awprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_awvalid : in std_logic;
s_axi4_awready : out std_logic;
---------------------------------------
-- axi4 full write Data Channel Signals
---------------------------------------
s_axi4_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI4_DATA_WIDTH-1)downto 0);
s_axi4_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
s_axi4_wlast : in std_logic;
s_axi4_wvalid : in std_logic;
s_axi4_wready : out std_logic;
-------------------------------------------
-- axi4 full write Response Channel Signals
-------------------------------------------
s_axi4_bid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_bresp : out std_logic_vector(1 downto 0);
s_axi4_bvalid : out std_logic;
s_axi4_bready : in std_logic;
-----------------------------------
-- axi read address Channel Signals
-----------------------------------
s_axi4_arid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_araddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_arlen : in std_logic_vector(7 downto 0);
s_axi4_arsize : in std_logic_vector(2 downto 0);
s_axi4_arburst : in std_logic_vector(1 downto 0);
s_axi4_arlock : in std_logic; -- not supported in design
s_axi4_arcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_arprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_arvalid : in std_logic;
s_axi4_arready : out std_logic;
--------------------------------
-- axi read data Channel Signals
--------------------------------
s_axi4_rid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_rdata : out std_logic_vector(31 downto 0);--((C_S_AXI4_DATA_WIDTH-1) downto 0);
s_axi4_rresp : out std_logic_vector(1 downto 0);
s_axi4_rlast : out std_logic;
s_axi4_rvalid : out std_logic;
s_axi4_rready : in std_logic;
--------------------------------
-------------------------------
--*SPI port interface * --
-------------------------------
io0_i : in std_logic; -- MOSI signal in standard SPI
io0_o : out std_logic;
io0_t : out std_logic;
-------------------------------
io1_i : in std_logic; -- MISO signal in standard SPI
io1_o : out std_logic;
io1_t : out std_logic;
-----------------
-- quad mode pins
-----------------
io2_i : in std_logic;
io2_o : out std_logic;
io2_t : out std_logic;
---------------
io3_i : in std_logic;
io3_o : out std_logic;
io3_t : out std_logic;
---------------------------------
-- common pins
----------------
spisel : in std_logic;
-----
sck_i : in std_logic;
sck_o : out std_logic;
sck_t : out std_logic;
-----
ss_i : in std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
ss_o : out std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
ss_t : out std_logic;
------------------------
-- STARTUP INTERFACE
------------------------
cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output
clk : in std_logic; -- input
gsr : in std_logic; -- input
gts : in std_logic; -- input
keyclearb : in std_logic; -- input
usrcclkts : in std_logic; -- input
usrdoneo : in std_logic; -- input
usrdonets : in std_logic; -- input
pack : in std_logic; -- input
----------------------
-- INTERRUPT INTERFACE
----------------------
ip2intc_irpt : out std_logic
---------------------------------
);
-------------------------------
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ACLK : signal is "10000";
attribute MAX_FANOUT of EXT_SPI_CLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ARESETN : signal is "10000";
attribute INITIALVAL : string;
attribute INITIALVAL of SPISEL : signal is "VCC";
-------------------------------
end entity axi_quad_spi;
--------------------------------------------------------------------------------
architecture imp of axi_quad_spi is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- constant added for webtalk information
---------------------------------------------------------------------------------
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_quad_spi,{"
-- & "C_FAMILY = " & C_FAMILY
-- & ",C_SUB_FAMILY = " & C_SUB_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",C_S_AXI_ADDR_WIDTH = " & integer'image(C_S_AXI_ADDR_WIDTH)
-- & ",C_S_AXI_DATA_WIDTH = " & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",C_S_AXI4_ADDR_WIDTH = " & integer'image(C_S_AXI4_ADDR_WIDTH)
-- & ",C_S_AXI4_DATA_WIDTH = " & integer'image(C_S_AXI4_DATA_WIDTH)
-- & ",C_S_AXI4_ID_WIDTH = " & integer'image(C_S_AXI4_ID_WIDTH)
-- & ",C_FIFO_DEPTH = " & integer'image(C_FIFO_DEPTH)
-- & ",C_SCK_RATIO = " & integer'image(C_SCK_RATIO)
-- & ",C_NUM_SS_BITS = " & integer'image(C_NUM_SS_BITS)
-- & ",C_NUM_TRANSFER_BITS = " & integer'image(C_NUM_TRANSFER_BITS)
-- & ",C_USE_STARTUP = " & integer'image(C_USE_STARTUP)
-- & ",C_SPI_MODE = " & integer'image(C_SPI_MODE)
-- & ",C_SPI_MEMORY = " & integer'image(C_SPI_MEMORY)
-- & ",C_TYPE_OF_AXI4_INTERFACE = " & integer'image(C_TYPE_OF_AXI4_INTERFACE)
-- & ",C_XIP_MODE = " & integer'image(C_XIP_MODE)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------
-------------------------------------------------------------
-- Function Declaration
-------------------------------------------------------------
-- get_fifo_presence - This function returns the 0 or 1 based upon the FIFO Depth.
--
function get_fifo_presence(C_FIFO_DEPTH: integer) return integer is
-----
begin
-----
if(C_FIFO_DEPTH = 0)then
return 0;
else
return 1;
end if;
end function get_fifo_presence;
function get_fifo_depth(C_FIFO_EXIST: integer; C_FIFO_DEPTH : integer) return integer is
-----
begin
-----
if(C_FIFO_EXIST = 1)then
return C_FIFO_DEPTH;
else
return 64; -- to ensure that log2 functions does not become invalid
end if;
end function get_fifo_depth;
------------------------------
function get_fifo_occupancy_count(C_FIFO_DEPTH: integer) return integer is
-----
variable j : integer := 0;
variable k : integer := 0;
-----
begin
-----
if (C_FIFO_DEPTH = 0) then
return 4;
else
for i in 0 to 11 loop
if(2**i >= C_FIFO_DEPTH) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
end if;
-------
end function get_fifo_occupancy_count;
------------------------------
-- Constant declarations
------------------------------
--------------------- ******************* ------------------------------------
-- Core Parameters
--------------------- ******************* ------------------------------------
--
constant C_FIFO_EXIST : integer := get_fifo_presence(C_FIFO_DEPTH);
constant C_FIFO_DEPTH_UPDATED : integer := get_fifo_depth(C_FIFO_EXIST, C_FIFO_DEPTH);
-- width of control register
constant C_SPICR_REG_WIDTH : integer := 10;-- refer DS
-- width of status register
constant C_SPISR_REG_WIDTH : integer := 11;-- refer DS
-- count the counter width for calculating FIFO occupancy
constant C_OCCUPANCY_NUM_BITS : integer := get_fifo_occupancy_count(C_FIFO_DEPTH_UPDATED);
-- width of spi shift register
constant C_SPI_NUM_BITS_REG : integer := 8;-- this is fixed
constant C_NUM_SPI_REGS : integer := 8;-- this is fixed
constant C_IPISR_IPIER_BITS : integer := 14;-- total 14 interrupts - 0 to 13
--------------------- ******************* ------------------------------------
-- AXI lite parameters
--------------------- ******************* ------------------------------------
constant C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 20;
-- interupt mode
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to (C_IPISR_IPIER_BITS-1)):=
(
others => INTR_REG_EVENT
-- when C_SPI_MODE = 0
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 0
-- OR
-- Eight interrupts if C_FIFO_DEPTH_UPDATED = 0 and slave mode
----------------------- OR ---------------------------
-- Nine interrupts if C_FIFO_DEPTH_UPDATED = 16 and slave mode
-- OR
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
-- when C_SPI_MODE = 1 or 2
-- Thirteen interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
);
constant ZEROES : std_logic_vector(31 downto 0):= X"00000000";
-- this constant is defined as the start of SPI register addresses.
constant C_IP_REG_ADDR_OFFSET : std_logic_vector := X"00000060";
-- Address range array
constant C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--ZEROES & C_BASEADDR,
--ZEROES & (C_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--interrupt address higher range
-- soft reset register base & high addr
--ZEROES & (C_BASEADDR or X"00000040"),
--ZEROES & (C_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000018")
ZEROES & C_IP_REG_ADDR_OFFSET,
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- AXI4 Address range array
constant C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--*ZEROES & C_S_AXI4_BASEADDR,
--*ZEROES & (C_S_AXI4_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--soft reset register high addr
-- soft reset register base & high addr
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000040"),
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- No. of CE's required per address range
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 16 , -- 16 CEs required for interrupt
--1 => 1, -- 1 CE required for soft reset
1 => 8, -- 8 CE required for Addressing Holes in soft reset
2 => C_NUM_SPI_REGS
);
-- no. of Chip Enable Signals
constant C_NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- no. of Chip Select Signals
constant C_NUM_CS_SIGNALS : integer := (C_ARD_ADDR_RANGE_ARRAY'LENGTH/2);
-----------------------------
----------------------- ******************* ------------------------------------
---- XIP Mode parameters
----------------------- ******************* ------------------------------------
-- No. of XIP SPI registers
constant C_NUM_XIP_SPI_REGS : integer := 2;-- this is fixed
-- width of XIP control register
constant C_XIP_SPICR_REG_WIDTH: integer := 2;-- refer DS
-- width of XIP status register
constant C_XIP_SPISR_REG_WIDTH: integer := 5;-- refer DS
-- Address range array
constant C_XIP_LITE_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000004")
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000004")
);
-- No. of CE's required per address range
constant C_XIP_LITE_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 2 CEs required for XIP lite interface
);
-- no. of Chip Enable Signals
constant C_NUM_XIP_CE_SIGNALS : integer :=
calc_num_ce(C_XIP_LITE_ARD_NUM_CE_ARRAY);
function assign_addr_bits (addr_bits_info : integer) return string is
variable addr_width_24 : integer:= 24;
variable addr_width_32 : integer:= 32;
begin
if addr_bits_info = 24 then -- old logic for 24 bit addressing
return X"00FFFFFF";--addr_width_24;
else
return X"FFFFFFFF";--addr_width_32;
end if;
end function assign_addr_bits;
constant C_XIP_ADDR_OFFSET : std_logic_vector := X"FFFFFFFF";--assign_addr_bits(C_SPI_MEM_ADDR_BITS); -- X"00FFFFFF";
-- XIP Full Interface Address range array
constant C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_S_AXI4_BASEADDR),
--*ZEROES & (C_S_AXI4_BASEADDR or C_24_BIT_ADDR_OFFSET)
ZEROES & X"00000000",
ZEROES & C_XIP_ADDR_OFFSET
);
-- No. of CE's required per address range
constant C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 0 CEs required for XIP Full interface
);
---------------------------------------------------------------------------------
constant C_XIP_FIFO_DEPTH : integer := 264;
-------------------------------------------------------------------------------
----Startup Signals
signal di_int : std_logic_vector(3 downto 0); -- output
signal di_int_sync : std_logic_vector(3 downto 0); -- output
signal dts_int : std_logic_vector(3 downto 0); -- input
signal do_int : std_logic_vector(3 downto 0); -- input
-- signal declaration
signal bus2ip_clk : std_logic;
signal bus2ip_be_int : std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0);
signal ip2bus_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0 )
:= (others => '0');
signal ip2bus_wrack_int : std_logic := '0';
signal ip2bus_rdack_int : std_logic := '0';
signal ip2bus_error_int : std_logic := '0';
signal bus2ip_reset_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
-- XIP signals
signal bus2ip_xip_rdce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal bus2ip_xip_wrce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal io0_i_sync : std_logic;
signal io1_i_sync : std_logic;
signal io2_i_sync : std_logic;
signal io3_i_sync : std_logic;
signal io0_i_sync_int : std_logic;
signal io1_i_sync_int : std_logic;
signal io2_i_sync_int : std_logic;
signal io3_i_sync_int : std_logic;
signal io0_i_int : std_logic;
signal io1_i_int : std_logic;
signal io2_i_int : std_logic;
signal io3_i_int : std_logic;
signal io0_o_int : std_logic;
signal io1_o_int : std_logic;
signal io2_o_int : std_logic;
signal io3_o_int : std_logic;
signal io0_t_int : std_logic;
signal io1_t_int : std_logic;
signal io2_t_int : std_logic;
signal io3_t_int : std_logic;
signal burst_tr_int : std_logic;
signal rready_int : std_logic;
signal bus2ip_reset_ipif4_inverted : std_logic;
signal fcsbo_int : std_logic;
signal ss_o_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal ss_t_int : std_logic;
signal ss_i_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal fcsbts_int : std_logic;
signal startup_di : std_logic_vector(1 downto 0); -- output
signal startup_do : std_logic_vector(1 downto 0) := (others => '1'); -- output
signal startup_dts : std_logic_vector(1 downto 0) := (others => '0'); -- output
-----
begin
-----
--------STUP and XIP mode
STARTUP_USED_1: if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1) generate
begin
DI_INT_IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(3),
C => EXT_SPI_CLK,
D => di_int(3) --MOSI_I
);
DI_INT_IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(2),
C => EXT_SPI_CLK,
D => di_int(2) -- MISO_I
);
DI_INT_IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(1),
C => EXT_SPI_CLK,
D => di_int(1)
);
-----------------------
DI_INT_IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(0),
C => EXT_SPI_CLK,
D => di_int(0)
);
io0_i_sync_int <= di_int_sync(0);
io1_i_sync_int <= di_int_sync(1);
io2_i_sync_int <= di_int_sync(2);
io3_i_sync_int <= di_int_sync(3);
end generate STARTUP_USED_1;
DATA_STARTUP_EN : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1 and C_XIP_MODE = 1)
generate
-----
begin
-----
do_int(0) <= io0_o_int;
dts_int(0) <= io0_t_int ;
do_int(1) <= io1_o_int;
dts_int(1) <= io1_t_int ;
fcsbo_int <= ss_o_int(0);
fcsbts_int <= ss_t_int;
NUM_SS : if (C_NUM_SS_BITS = 1) generate
begin
ss_o <= (others => '0');
ss_t <= '0';
end generate NUM_SS;
NUM_SS_G1 : if (C_NUM_SS_BITS > 1) generate
begin
ss_i_int <= ss_i((C_NUM_SS_BITS-1) downto 1) & '1';
ss_o <= ss_o_int((C_NUM_SS_BITS-1) downto 1);-- & '0';
ss_t <= ss_t_int;
end generate NUM_SS_G1;
DATA_OUT_NQUAD: if C_SPI_MODE = 0 or C_SPI_MODE = 1 generate
begin
startup_di <= di_int_sync(3) & di_int_sync(2);
do_int(2) <= startup_do(0);
do_int(3) <= startup_do(1);
dts_int(2) <= startup_dts(0);
dts_int(3) <= startup_dts(1);
--do <= do_int(3) & do_int(1);
--dts <= dts_int(3) & dts_int(1);
end generate DATA_OUT_NQUAD;
DATA_OUT_QUAD: if C_SPI_MODE = 2 generate
begin
--di <= "00";--di_int(3) & di_int(2);
do_int(2) <= io2_o_int;--do(2);
do_int(3) <= io3_o_int;--do(1);
--do <= do_int(3) & do_int(1);
dts_int(2) <= io2_t_int;--dts_int(3) & dts_int(1);
dts_int(3) <= io3_t_int;--dts_int(3) & dts_int(1);
end generate DATA_OUT_QUAD;
end generate DATA_STARTUP_EN;
DATA_STARTUP_DIS : if ((C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0)) and C_XIP_MODE = 1)
generate
-----
begin
-----
io0_o <= io0_o_int;
io0_t <= io0_t_int;
io1_t <= io1_t_int;
io1_o <= io1_o_int;
io2_o <= io2_o_int;
io2_t <= io2_t_int;
io3_t <= io3_t_int;
io3_o <= io3_o_int;
ss_i_int <= ss_i;
ss_o <= ss_o_int;-- & '0';
ss_t <= ss_t_int;
end generate DATA_STARTUP_DIS;
--------STUP and XIP mode off
STARTUP_USED: if (C_USE_STARTUP = 0 or C_UC_FAMILY = 0) generate
begin
io0_i_sync_int <= io0_i_sync;
io1_i_sync_int <= io1_i_sync;
io2_i_sync_int <= io2_i_sync;
io3_i_sync_int <= io3_i_sync;
end generate STARTUP_USED;
IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io0_i_sync,
C => ext_spi_clk,
D => io0_i --MOSI_I
);
IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io1_i_sync,
C => ext_spi_clk,
D => io1_i -- MISO_I
);
IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io2_i_sync,
C => ext_spi_clk,
D => io2_i
);
-----------------------
IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io3_i_sync,
C => ext_spi_clk,
D => io3_i
);
-----------------------
-------------------------------------------------------------------------------
---------------
-- AXI_QUAD_SPI_LEGACY_MODE: This logic is legacy AXI4 Lite interface based design
---------------
QSPI_LEGACY_MD_GEN : if C_TYPE_OF_AXI4_INTERFACE = 0 generate
---------------
begin
-----
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
(
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(bus2ip_reset_int);
end if;
end process REG_RST_FRM_IPIF;
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_LSB_STUP => C_LSB_STUP,
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SUB_FAMILY => C_FAMILY ,
C_UC_FAMILY => C_UC_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SELECT_XPM => C_SELECT_XPM ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
C_SHARED_STARTUP => C_SHARED_STARTUP,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => ext_spi_clk, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => '0',
WVALID => '0',
---------------------------------------------------
--SPI Ports
IO0_I => io0_i_sync,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i_sync,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i_sync,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i_sync,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => startup_di, -- output
DO => startup_do, -- 4-bit input
DTS => startup_dts, -- 4-bit input
GSR => gsr, -- 1-bit input, SetReset
CLK => clk, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets, -- SRDONETS -- 1-bit input
PACK => pack
-----
);
burst_tr_int <= '0';
end generate QSPI_LEGACY_MD_GEN;
------------------------------------------------------------------------------
QSPI_ENHANCED_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 0 generate
---------------
begin
-----
-- AXI_QUAD_SPI_I: core instance
QSPI_ENHANCED_MD_IPIF_I : entity axi_quad_spi_v3_2_8.axi_qspi_enhanced_mode
generic map(
-- General Parameters
C_FAMILY => C_FAMILY , -- : string := "virtex7";
C_SUB_FAMILY => C_FAMILY , -- : string := "virtex7";
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, -- : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
--C_XIP_MODE => C_XIP_MODE , -- : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS => C_AXI4_CLK_PS , -- : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , -- : integer := 10000;--ext clock period
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , -- : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO => C_SCK_RATIO , -- : integer := 16;--default in legacy mode
C_NUM_SS_BITS => C_NUM_SS_BITS , -- : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , -- : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE => C_SPI_MODE , -- : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP => C_USE_STARTUP , -- : integer range 0 to 1 := 1; --
C_SPI_MEMORY => C_SPI_MEMORY , -- : integer range 0 to 2 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , -- : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , -- : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , -- : std_logic_vector := x"00000000"
-------------------------
C_S_AXI_SPI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
-------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL ,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS -- newly added
)
port map(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
-----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESETN => s_axi4_aresetn , -- : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address channel signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid, -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready, -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid, -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready, -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Reset => bus2ip_reset_ipif_inverted , -- out
----------------------------------------------------------
-- Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int, -- in
----------------------------------------------------------
burst_tr => burst_tr_int, -- in
rready => rready_int
);
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_LSB_STUP => C_LSB_STUP,
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SELECT_XPM => C_SELECT_XPM ,
C_SUB_FAMILY => C_FAMILY ,
C_UC_FAMILY => C_UC_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
C_SHARED_STARTUP => C_SHARED_STARTUP,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => rready_int,
WVALID => S_AXI4_WVALID,
--SPI Ports
IO0_I => io0_i_sync,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i_sync,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i_sync,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i_sync,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => startup_di, -- output
DO => startup_do, -- 4-bit input
DTS => startup_dts, -- 4-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets, -- SRDONETS -- 1-bit input
PACK => pack
-----
);
end generate QSPI_ENHANCED_MD_GEN;
--------------------------------------------------------------------------------
-----------------
-- XIP_MODE: This logic is used in XIP mode where AXI4 Lite & AXI4 Full interface
-- used in the design
---------------
XIP_MODE_GEN : if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 1 generate
---------------
constant XIPCR : natural := 0; -- at address C_BASEADDR + 60 h
constant XIPSR : natural := 1;
--
signal bus2ip_reset_int : std_logic;
signal bus2ip_clk_int : std_logic;
signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_error_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
signal IP2Bus_XIPCR_WrAck : std_logic;
signal IP2Bus_XIPCR_RdAck : std_logic;
signal XIPCR_1_CPOL_int : std_logic;
signal XIPCR_0_CPHA_int : std_logic;
signal IP2Bus_XIPCR_Data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
signal IP2Bus_XIPSR_Data_int : std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
signal TO_XIPSR_AXI_TR_ERR_int : std_logic;
signal TO_XIPSR_mst_modf_err_int : std_logic;
signal TO_XIPSR_axi_rx_full_int : std_logic;
signal TO_XIPSR_axi_rx_empty_int : std_logic;
signal xipsr_cpha_cpol_err_int :std_logic;
signal xipsr_cmd_err_int :std_logic;
signal ip2bus_xipsr_wrack :std_logic;
signal ip2bus_xipsr_rdack :std_logic;
signal xipsr_axi_tr_err_int :std_logic;
signal xipsr_axi_tr_done_int :std_logic;
signal ip2bus_xipsr_rdack_int :std_logic;
signal ip2bus_xipsr_wrack_int :std_logic;
signal MISO_I_int :std_logic;
signal SCK_O_int :std_logic;
signal TO_XIPSR_trans_error_int :std_logic;
signal TO_XIPSR_CPHA_CPOL_ERR_int :std_logic;
signal ip2bus_wrack_core_reg_d1 :std_logic;
signal ip2bus_wrack_core_reg :std_logic;
signal ip2bus_rdack_core_reg_d1 :std_logic;
signal ip2bus_rdack_core_reg_d2 :std_logic;
signal ip2Bus_RdAck_core_reg_d3 :std_logic;
signal Rst_to_spi_int :std_logic;
begin
-----
---- AXI4 Lite interface instance and interface with the port list
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_XIP_LITE_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_LITE_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
( -- AXI4 Lite interface
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk_int , -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => open, -- bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_xip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_xip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
--------------------------------------------------------------------------
ip2bus_error_int <= '0'; -- there is no error in this mode
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(S_AXI_ARESETN);
end if;
end process REG_RST_FRM_IPIF;
--------------------------------------------------------------------------
XIP_CR_I : entity axi_quad_spi_v3_2_8.xip_cntrl_reg
generic map
(
C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SPI_MODE => C_SPI_MODE
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
Bus2IP_XIPCR_WrCE => bus2ip_xip_wrce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_RdCE => bus2ip_xip_rdce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_data => bus2ip_data_int , -- : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------
ip2Bus_RdAck_core => ip2Bus_RdAck_core_reg_d2, -- IP2Bus_XIPCR_WrAck,
ip2Bus_WrAck_core => ip2Bus_WrAck_core_reg, -- IP2Bus_XIPCR_RdAck,
------------------------
--XIPCR_7_0_CMD => XIPCR_7_0_CMD, -- out std_logic_vector;
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
------------------------
IP2Bus_XIPCR_Data => IP2Bus_XIPCR_Data_int, -- out std_logic;
------------------------
TO_XIPSR_CPHA_CPOL_ERR=> TO_XIPSR_CPHA_CPOL_ERR_int -- out std_logic
);
--------------------------------------------------------------------------
REG_WR_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR);
ip2Bus_WrAck_core_reg <= (bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR)) and
(not ip2Bus_WrAck_core_reg_d1);
end if;
end if;
end process REG_WR_ACK_P;
-------------------------
ip2bus_wrack_int <= ip2Bus_WrAck_core_reg;
-------------------------
REG_RD_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg_d2 <= '0';
ip2Bus_RdAck_core_reg_d3 <= '0';
else
ip2Bus_RdAck_core_reg_d1 <= bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR);
ip2Bus_RdAck_core_reg_d2 <= (bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR)) and
(not ip2Bus_RdAck_core_reg_d1);
ip2Bus_RdAck_core_reg_d3 <= ip2Bus_RdAck_core_reg_d2;
end if;
end if;
end process REG_RD_ACK_P;
-------------------------
ip2bus_rdack_int <= ip2Bus_RdAck_core_reg_d3;
-------------------------
REG_IP2BUS_DATA_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2bus_data_int <= (others => '0');
elsif(ip2Bus_RdAck_core_reg_d2 = '1') then
ip2bus_data_int <= ("000000000000000000000000000000" & IP2Bus_XIPCR_Data_int) or
("000000000000000000000000000" & IP2Bus_XIPSR_Data_int);
end if;
end if;
end process REG_IP2BUS_DATA_P;
-------------------------
--------------------------------------------------------------------------
XIP_SR_I : entity axi_quad_spi_v3_2_8.xip_status_reg
generic map
(
C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
XIPSR_AXI_TR_ERR => TO_XIPSR_AXI_TR_ERR_int, -- : in std_logic;
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int, -- : in std_logic;
XIPSR_MST_MODF_ERR => TO_XIPSR_mst_modf_err_int, -- : in std_logic;
XIPSR_AXI_RX_FULL => TO_XIPSR_axi_rx_full_int, -- : in std_logic;
XIPSR_AXI_RX_EMPTY => TO_XIPSR_axi_rx_empty_int, -- : in std_logic;
------------------------
Bus2IP_XIPSR_WrCE => bus2ip_xip_wrce_int(XIPSR),
Bus2IP_XIPSR_RdCE => bus2ip_xip_rdce_int(XIPSR),
-------------------
IP2Bus_XIPSR_Data => IP2Bus_XIPSR_Data_int ,
ip2Bus_RdAck => ip2Bus_RdAck_core_reg_d3
);
---------------------------------------------------------------------------
--REG_RST4_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST4_FRM_IPIF: process (S_AXI4_ACLK) is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
bus2ip_reset_ipif4_inverted <= not(S_AXI4_ARESETN);
end if;
end process REG_RST4_FRM_IPIF;
-------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2_8.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
Soft_Reset_frm_axi => bus2ip_reset_ipif4_inverted ,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------------------------------------------
AXI_QSPI_XIP_I : entity axi_quad_spi_v3_2_8.axi_qspi_xip_if
generic map
(
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SUB_FAMILY => C_FAMILY ,
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
--C_XIP_MODE => C_XIP_MODE ,
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
--C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
-------------------------
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH ,
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH ,
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR ,
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR ,
-------------------------
--C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH ,
--C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH ,
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY => C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_XIP_FULL_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY
)
port map
(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int,
----------------------------------
S_AXI_ACLK => s_axi_aclk , -- : in std_logic;
S_AXI_ARESETN => bus2ip_reset_ipif_inverted, -- : in std_logic;
----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESET => bus2ip_reset_ipif4_inverted, -- : in std_logic;
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel Signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid , -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready , -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid , -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready , -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int , -- in std_logic
-------------------------------
TO_XIPSR_trans_error => TO_XIPSR_AXI_TR_ERR_int , -- out std_logic
TO_XIPSR_mst_modf_err => TO_XIPSR_mst_modf_err_int,
TO_XIPSR_axi_rx_full => TO_XIPSR_axi_rx_full_int ,
TO_XIPSR_axi_rx_empty => TO_XIPSR_axi_rx_empty_int,
-------------------------------
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
--*SPI port interface * --
-------------------------------
IO0_I => io0_i_sync_int, -- : in std_logic; -- MOSI signal in standard SPI
IO0_O => io0_o_int, -- : out std_logic;
IO0_T => io0_t_int, -- : out std_logic;
-------------------------------
IO1_I => io1_i_sync_int, -- : in std_logic; -- MISO signal in standard SPI
IO1_O => io1_o_int, -- : out std_logic;
IO1_T => io1_t_int, -- : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I => io2_i_sync_int, -- : in std_logic;
IO2_O => io2_o_int, -- : out std_logic;
IO2_T => io2_t_int, -- : out std_logic;
---------------
IO3_I => io3_i_sync_int, -- : in std_logic;
IO3_O => io3_o_int, -- : out std_logic;
IO3_T => io3_t_int, -- : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL => spisel, -- : in std_logic;
-----
SCK_I => sck_i , -- : in std_logic;
SCK_O_reg => SCK_O_int , -- : out std_logic;
SCK_T => sck_t , -- : out std_logic;
-----
SS_I => ss_i_int , -- : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O => ss_o_int , -- : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T => ss_t_int -- : out std_logic;
----------------------
);
-- no interrupt from this mode of core
IP2INTC_Irpt <= '0';
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= io1_i_sync; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => io1_i_sync, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => bus2ip_reset_ipif4_inverted,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets, -- SRDONETS -- 1-bit input
PACK => pack
);
--------------------
end generate SCK_MISO_STARTUP_USED;
end generate XIP_MODE_GEN;
------------------------------------------------------------------------------
end architecture imp;
------------------------------------------------------------------------------
|
bsd-3-clause
|
d2683b9d509779780f10379d04df3d11
| 0.438495 | 3.78993 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/alu.vhdl
| 1 | 3,897 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
use work.overloads.all;
use work.txt_utils.all;
entity alu is
port(Src1 : in word_t;
Src2 : in word_t;
AluOp : in alu_op_t;
Immediate : in ctrl_t;
AluResult : out word_t;
isZero : out ctrl_t;
trap : out traps_t -- only TRAP_OVERFLOW is relevant
);
end alu;
-- http://www-inst.eecs.berkeley.edu/~cs61c/resources/MIPS_Green_Sheet.pdf
architecture behav of alu is
signal HI, LO : word_t;
function immediately_correct(Src2 : word_t; immediate : ctrl_t) return word_t is
begin
if immediate = '0' then
return Src2;
else
return X"0000" & half(Src2);
end if;
end function;
begin
trap <= TRAP_NONE; -- rethink
process (Src1, Src2, AluOp, immediate)
variable result : word_t := X"8BAD_F00D";
alias shamt is Src2(5 downto 0); -- 0 <= shamt <= 31
begin
case AluOp is
-- Trapping not implemented
when ALU_ADD => result := Src1 + Src2;
when ALU_ADDU => result := Src1 + Src2;
when ALU_SUB | ALU_SUBU =>
result := Src1 - Src2;
when ALU_AND => result := Src1 and immediately_correct(Src2, immediate);
when ALU_OR => result := Src1 or immediately_correct(Src2, immediate);
when ALU_NOR => result := Src1 nor immediately_correct(Src2, immediate);
when ALU_XOR => result := Src1 xor immediately_correct(Src2, immediate);
when ALU_LU => result := half(Src2) & X"0000";
when ALU_SLL => result := Src1 sll vtou(shamt);
when ALU_SRL => result := Src1 srl vtou(shamt);
when ALU_SRA => result := Src1 sra vtou(shamt);
when ALU_MULT | ALU_MULTU | ALU_DIV | ALU_DIVU =>
-- Interesting read: http://yarchive.net/comp/mips_exceptions.html
-- TL;DR: No arithmetic division errors on a MIPS R3000
--trap <= TRAP_UNIMPLEMENTED; -- FIXME!
null;
when ALU_MFHI => result := HI;
when ALU_MFLO => result := LO;
-- These weren't part of the MIPS R3000 AFAIK, implemented here anyway.
when ALU_MTHI => HI <= Src1;
when ALU_MTLO => LO <= Src2;
when ALU_SLT =>
result := (31 downto 1 => '0')
& high_if(vtoi(Src1) < vtoi(Src2));
when ALU_SLTU => result := (31 downto 1 => '0') & high_if(Src1 < Src2);
-- Some (all?) of these could be optimized away (e.g. EQ can be done with SUB)
when ALU_EQ => result := (31 downto 1 => '0') & low_if(Src1 = Src2);
when ALU_NE => result := (31 downto 1 => '0') & low_if(Src1 /= Src2);
when ALU_LEZ => result := (31 downto 1 => '0')
& low_if(vtoi(Src1) <= 0);
when ALU_LTZ => result := (31 downto 1 => '0')
& low_if(vtoi(Src1) < 0);
when ALU_GTZ => result := (31 downto 1 => '0')
& low_if(vtoi(Src1) > 0);
when ALU_GEZ => result := (31 downto 1 => '0')
& low_if(vtoi(Src1) >= 0);
when others => null; -- trap <= TRAP_UNIMPLEMENTED; -- FIXME!
end case;
if result = ZERO then
isZero <= '1';
else
isZero <= '0';
end if;
AluResult <= result;
end process;
end behav;
|
gpl-3.0
|
1b5a5e125a39935ec4feed13edf23dd9
| 0.472928 | 3.908726 | false | false | false | false |
makestuff/dvr-connectors
|
conv-16to8/vhdl/conv_16to8.vhdl
| 1 | 2,547 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_16to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 16-bit data coming in
data16_in : in std_logic_vector(15 downto 0);
valid16_in : in std_logic;
ready16_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_16to8 is
type StateType is (
S_WRITE_MSB,
S_WRITE_LSB
);
signal state : StateType := S_WRITE_MSB;
signal state_next : StateType;
signal lsb : std_logic_vector(7 downto 0) := (others => '0');
signal lsb_next : std_logic_vector(7 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE_MSB;
lsb <= (others => '0');
else
state <= state_next;
lsb <= lsb_next;
end if;
end if;
end process;
-- Next state logic
process(state, lsb, data16_in, valid16_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
lsb_next <= lsb;
case state is
-- Write the LSB and return:
when S_WRITE_LSB =>
ready16_out <= '0'; -- not ready for data from 16-bit side
data8_out <= lsb;
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE_MSB;
end if;
-- When a word arrives, write the MSB:
when others =>
ready16_out <= ready8_in; -- ready for data from 16-bit side
data8_out <= data16_in(15 downto 8);
valid8_out <= valid16_in;
if ( valid16_in = '1' and ready8_in = '1' ) then
lsb_next <= data16_in(7 downto 0);
state_next <= S_WRITE_LSB;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
08f49d78c414317bceba7010e5abd39d
| 0.641932 | 3.017773 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/mlite_pack.vhd
| 1 | 23,394 |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
mit
|
5aab0ad6b85a1dff6963fb660bee1ee5
| 0.544114 | 3.629227 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/sobel_filter/pixel_buffer.vhd
| 1 | 4,592 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/14/2017 03:01:40 PM
-- Design Name:
-- Module Name: pixel_buffer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library work;
use work.filter_lib.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pixel_buffer is
generic (
WIDTH : natural := 3;
HEIGHT : natural := 3;
LINE_LENGTH : natural := 2048
);
port (
-- Clock
CLK : in std_logic;
-- Inputs
data_in : in pixel_t;
vde_in : in std_logic; -- Active video Flag (optional)
hs_in : in std_logic; -- Horizontal sync signal (optional)
vs_in : in std_logic; -- Veritcal sync signal (optional)
-- Outputs
data_out : out pixel2d_t(WIDTH - 1 downto 0, HEIGHT - 1 downto 0);
vde_out : out std_logic; -- Active video Flag (optional)
hs_out : out std_logic; -- Horizontal sync signal (optional)
vs_out : out std_logic -- Veritcal sync signal (optional)
);
end pixel_buffer;
architecture Behavioral of pixel_buffer is
signal to_window : pixel_t;
-- Indeces for the line buffers
signal line_buffer_index, line_buffer_index_next : unsigned(log2ceil(LINE_LENGTH) - 1 downto 0);
-- Window of pixels to be sent out
signal window_reg, window_next : pixel2d_t(WIDTH - 1 downto 0, HEIGHT - 1 downto 0);
-- Used to control shifting in the linebuffer
signal new_line, vde_prev, shift : std_logic;
begin
-- To guarantee zero padding
to_window <= data_in when vde_in = '1' else
(others=>'0');
-- Control logic for shifting stuff
shift <= vde_in;
-- Falling-edge detector for the vde signal
process(CLK)
begin
if (rising_edge(CLK)) then
vde_prev <= vde_in;
end if;
end process;
new_line <= '1' when (vde_prev = '1') and (vde_in = '0') else '0';
-- Counter for line_buffer_index
process(CLK)
begin
if (rising_edge(CLK)) then
line_buffer_index <= line_buffer_index_next;
window_reg <= window_next;
end if;
end process;
-- Increment when shift is asserted, zero otherwise
line_buffer_index_next <= (others=>'0') when (new_line = '1') else
(line_buffer_index + 1) when (shift = '1') else
line_buffer_index;
-- LINEBUFFERS and WINDOW
-- Generate linebuffers, and do reads/writes to the window
if_linebuffers:
if (HEIGHT > 1) generate -- Verify if this is necessary or not
for_linebuffers:
for row in 1 to HEIGHT - 1 generate
line_x : entity work.line_buffer(inferred)
generic map (
LENGTH => 2048
)
port map (
CLK => CLK,
en => shift,
index => std_logic_vector(line_buffer_index),
d_in => window_next(0, row - 1),
d_out => window_next(0, row)
);
end generate;
end generate;
-- Shift pixels around in the window
window_next(0,0) <= to_window when (shift = '1') else
window_reg(0, 0);
rows:
for row in 0 to (HEIGHT - 1) generate
columns:
for column in 0 to (WIDTH - 1) generate
-- If not last column
not_last_col:
if column < (WIDTH - 1) generate
-- Feed each pixel to the next reg in the row
window_next(column + 1, row) <= window_reg(column, row) when (shift = '1') else
window_reg(column + 1, row);
end generate; -- if not last col
end generate; -- for cols
end generate; -- for rows
-- Outputs
data_out <= window_reg;
-- TODO: Delay these by an appropriate amount
vde_out <= vde_in;
hs_out <= hs_in;
vs_out <= vs_in;
end Behavioral;
|
bsd-3-clause
|
b59fe7b43f01801e7189eb049bdde71c
| 0.539852 | 4.060124 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_s2mm_sts_strm.vhd
| 4 | 38,431 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_strm.vhd.vhd
-- Description: This entity is the AXI Status Stream Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_strm is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_SKID : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
s2mm_rxlength_valid : out std_logic ; --
s2mm_rxlength_clr : in std_logic ; --
s2mm_rxlength : out std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
stsstrm_fifo_rden : in std_logic ; --
stsstrm_fifo_empty : out std_logic ; --
stsstrm_fifo_dout : out std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_sts_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status Stream FIFO Depth
constant STSSTRM_FIFO_DEPTH : integer := 16;
-- Status Stream FIFO Data Count Width (Unsused)
constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_full : std_logic := '0';
signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_sinit : std_logic := '0';
signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_cdc_from : std_logic := '0';
signal rxlength_valid_trdy : std_logic := '0';
--signal sts_tvalid_re : std_logic := '0';-- CR565502
--signal sts_tvalid_d1 : std_logic := '0';-- CR565502
signal sts_tvalid : std_logic := '0';
signal sts_tready : std_logic := '0';
signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sts_tlast : std_logic := '0';
signal m_tvalid : std_logic := '0';
signal m_tready : std_logic := '0';
signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_tlast : std_logic := '0';
signal tag_stripped : std_logic := '0';
signal mask_tag_write : std_logic := '0';
--signal mask_tag_hold : std_logic := '0';-- CR565502
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal s2mm_stop_d1 : std_logic := '0';
signal s2mm_stop_re : std_logic := '0';
signal sts_rden : std_logic := '0';
signal follower_empty : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
begin
-- Generate Synchronous FIFO
-- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0_2.sync_fifo_fg
-- generic map (
-- C_FAMILY => C_FAMILY ,
-- C_MEMORY_TYPE => USE_LOGIC_FIFOS,
-- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
-- C_READ_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_PORTS_DIFFER => 0,
-- C_HAS_DCOUNT => 1, --req for proper fifo operation
-- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_RD_ACK => 0,
-- C_HAS_RD_ERR => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_ERR => 0,
-- C_RD_ACK_LOW => 0,
-- C_RD_ERR_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_ERR_LOW => 0,
-- C_PRELOAD_REGS => 1,-- 1 = first word fall through
-- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- -- C_USE_EMBEDDED_REG => 1 -- 0 ;
-- )
-- port map (
--
-- Clk => m_axi_sg_aclk ,
-- Sinit => fifo_sinit ,
-- Din => fifo_din ,
-- Wr_en => fifo_wren ,
-- Rd_en => stsstrm_fifo_rden ,
-- Dout => stsstrm_fifo_dout ,
-- Full => fifo_full ,
-- Empty => stsstrm_fifo_empty ,
-- Almost_full => open ,
-- Data_count => open ,
-- Rd_ack => open ,
-- Rd_err => open ,
-- Wr_ack => open ,
-- Wr_err => open
--
-- );
I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => fifo_sinit ,
FIFO_Write => fifo_wren ,
Data_In => fifo_din ,
FIFO_Read => sts_rden, --sts_queue_rden ,
Data_Out => fifo_out, --sts_queue_dout ,
FIFO_Empty => fifo_empty, --sts_queue_empty ,
FIFO_Full => fifo_full ,
Addr => open
);
sts_rden <= (not fifo_empty) and follower_empty;
stsstrm_fifo_empty <= follower_empty;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then
follower_empty <= '1';
elsif (sts_rden = '1') then
follower_empty <= '0';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (fifo_sinit = '1') then
stsstrm_fifo_dout <= (others => '0');
elsif (sts_rden = '1') then
stsstrm_fifo_dout <= fifo_out;
end if;
end if;
end process;
fifo_sinit <= not m_axi_sg_aresetn;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write;
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
--
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif((sts_tvalid_re = '1' and tag_stripped = '0')
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
end if;
end if;
end process REG_RXLENGTH;
s2mm_rxlength_valid <= rxlength_valid_cdc_from;
s2mm_rxlength <= rxlength_cdc_from;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- register stop to create re pulse
REG_STOP : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
s2mm_stop_d1 <= '0';
else
s2mm_stop_d1 <= s2mm_stop;
end if;
end if;
end process REG_STOP;
s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1;
skid_rst <= not m_axi_sg_aresetn;
ENABLE_SKID : if C_ENABLE_SKID = 1 generate
begin
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate ENABLE_SKID;
DISABLE_SKID : if C_ENABLE_SKID = 0 generate
begin
sts_tvalid <= s_axis_s2mm_sts_tvalid;
s_axis_s2mm_sts_tready <= sts_tready;
sts_tdata <= s_axis_s2mm_sts_tdata;
sts_tkeep <= s_axis_s2mm_sts_tkeep;
sts_tlast <= s_axis_s2mm_sts_tlast;
end generate DISABLE_SKID;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal s2mm_stop_reg : std_logic := '0'; -- CR605883
signal p_s2mm_stop_d1_cdc_tig : std_logic := '0';
signal p_s2mm_stop_d2 : std_logic := '0';
signal p_s2mm_stop_d3 : std_logic := '0';
signal p_s2mm_stop_re : std_logic := '0';
--ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true";
begin
-- Generate Asynchronous FIFO
I_STSSTRM_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 ,
-- C_DEPTH => STSSTRM_FIFO_DEPTH ,
-- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH ,
C_DEPTH => 15 ,
C_CNT_WIDTH => 4 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_sinit ,
AFIFO_Wr_clk => axi_prmry_aclk ,
AFIFO_Wr_en => fifo_wren ,
AFIFO_Din => fifo_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => stsstrm_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => stsstrm_fifo_dout ,
AFIFO_Full => fifo_full ,
AFIFO_Empty => stsstrm_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
fifo_sinit <= not p_reset_n;
fifo_din <= sts_tlast & sts_tdata;
fifo_wren <= sts_tvalid -- valid data
and not fifo_full -- fifo has room
and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length
and not mask_tag_write; -- not masking off tag word
sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- -- Create register delay of status tvalid in order to create a
-- -- rising edge pulse. note xx_re signal will hold at 1 if
-- -- fifo full on rising edge of tvalid.
-- REG_TVALID : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- sts_tvalid_d1 <= '0';
-- elsif(fifo_full = '0')then
-- sts_tvalid_d1 <= sts_tvalid;
-- end if;
-- end if;
-- end process REG_TVALID;
-- -- rising edge on tvalid used to gate off status tag from being
-- -- writen into fifo.
-- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1;
REG_TAG_STRIPPED : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
tag_stripped <= '0';
-- Reset on write of last word
elsif(fifo_wren = '1' and sts_tlast = '1')then
tag_stripped <= '0';
-- Set on beginning of new status stream
elsif(sts_tready = '1' and sts_tvalid = '1')then
tag_stripped <= '1';
end if;
end if;
end process REG_TAG_STRIPPED;
-- CR565502 - particular throttle condition caused masking of tag write to not occur
-- simplified logic will provide more robust handling of tag write mask
-- REG_MASK_TAG : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- mask_tag_hold <= '0';
-- elsif(tag_stripped = '1')then
-- mask_tag_hold <= '0';
--
-- elsif(sts_tvalid_re = '1'
-- or (fifo_wren = '1' and sts_tlast = '1'))then
-- mask_tag_hold <= '1';
-- end if;
-- end if;
-- end process;
--
-- -- Mask TAG if not already masked and rising edge of tvalid
-- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold);
mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid;
-- Generate logic to capture receive length when Use Receive Length is
-- enabled
GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
signal rxlength_clr_d1_cdc_tig : std_logic := '0';
signal rxlength_clr_d2 : std_logic := '0';
signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal rxlength_valid_d1_cdc_to : std_logic := '0';
signal rxlength_valid_d2_cdc_from : std_logic := '0';
signal rxlength_valid_d3 : std_logic := '0';
signal rxlength_valid_d4 : std_logic := '0';
signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0';
ATTRIBUTE async_reg : STRING;
--ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true";
begin
-- Double register from secondary clock domain to primary
S2P_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_rxlength_clr,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_clr_d2,
scndry_vect_out => open
);
-- S2P_CLK_CROSS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0')then
-- rxlength_clr_d1_cdc_tig <= '0';
-- rxlength_clr_d2 <= '0';
-- else
-- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr;
-- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig;
-- end if;
-- end if;
-- end process S2P_CLK_CROSS;
-- Register receive length on assertion of last and valid
-- Mark rxlength as valid for higher processes
TRDY_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or rxlength_clr_d2 = '1')then
rxlength_valid_trdy <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_valid_trdy <= '1';
end if;
end if;
end process TRDY_RXLENGTH;
REG_RXLENGTH : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
rxlength_cdc_from <= (others => '0');
rxlength_valid_cdc_from <= '0';
elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then
rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0);
rxlength_valid_cdc_from <= '1';
elsif (rxlength_valid_d2_back = '1') then
rxlength_valid_cdc_from <= '0';
end if;
end if;
end process REG_RXLENGTH;
SYNC_RXLENGTH : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_d2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_back,
scndry_vect_out => open
);
-- SYNC_RXLENGTH : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then
--
-- rxlength_valid_d1_back_cdc_to <= '0';
-- rxlength_valid_d2_back <= '0';
-- else
-- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from;
-- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to;
--
-- end if;
-- end if;
-- end process SYNC_RXLENGTH;
-- Double register from primary clock domain to secondary
P2S_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => rxlength_valid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => rxlength_valid_d2_cdc_from,
scndry_vect_out => open
);
P2S_CLK_CROSS2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => rxlength_cdc_from,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => rxlength_d2
);
P2S_CLK_CROSS1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then
-- rxlength_d1_cdc_to <= (others => '0');
-- rxlength_d2 <= (others => '0');
-- rxlength_valid_d1_cdc_to <= '0';
-- rxlength_valid_d2_cdc_from <= '0';
rxlength_valid_d3 <= '0';
else
-- rxlength_d1_cdc_to <= rxlength_cdc_from;
-- rxlength_d2 <= rxlength_d1_cdc_to;
-- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from;
-- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to;
rxlength_valid_d3 <= rxlength_valid_d2_cdc_from;
end if;
end if;
end process P2S_CLK_CROSS1;
process (m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then
rxlength_valid_d4 <= '0';
elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then
rxlength_valid_d4 <= '1';
end if;
end if;
end process;
s2mm_rxlength <= rxlength_d2;
-- s2mm_rxlength_valid <= rxlength_valid_d2;
s2mm_rxlength_valid <= rxlength_valid_d4;
end generate GEN_STS_APP_LENGTH;
-- Do NOT generate logic to capture receive length when option disabled
GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
end generate GEN_NO_STS_APP_LENGTH;
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop_reg <= '0';
else
s2mm_stop_reg <= s2mm_stop;
end if;
end if;
end process REG_STOP;
-- double register s2mm error into primary clock domain
REG_ERR2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_s2mm_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_s2mm_stop_d1_cdc_tig <= '0';
-- p_s2mm_stop_d2 <= '0';
p_s2mm_stop_d3 <= '0';
else
--p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883
-- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg;
-- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig;
p_s2mm_stop_d3 <= p_s2mm_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY1;
p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
STS_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_s2mm_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_sts_tvalid ,
S_READY => s_axis_s2mm_sts_tready ,
S_Data => s_axis_s2mm_sts_tdata ,
S_STRB => s_axis_s2mm_sts_tkeep ,
S_Last => s_axis_s2mm_sts_tlast ,
-- Master Side (Stream Data Output
M_VALID => sts_tvalid ,
M_READY => sts_tready ,
M_Data => sts_tdata ,
M_STRB => sts_tkeep ,
M_Last => sts_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
bsd-3-clause
|
bbe0adf814a04a6ad846831f18367166
| 0.446931 | 3.997815 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd
| 4 | 21,799 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_4;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
bsd-3-clause
|
ef1cf2bf35671bf824ae86222685ce0a
| 0.438919 | 4.351098 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vsigactofkofone.vhd
| 1 | 1,381 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vsigactofkofone is
port (
clock : in std_logic;
Vactcapofkofone : in std_logic_vector(31 downto 0);
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Vsigactofkofone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vsigactofkofone;
architecture struct of k_ukf_Vsigactofkofone is
component k_ukf_Vsigactofkofzero is
port (
clock : in std_logic;
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Vsigactofkofzero : out std_logic_vector(31 downto 0)
);
end component;
begin
M1 : k_ukf_Vsigactofkofzero port map
( clock => clock,
I => I,
Isc => Isc,
Vactcapofk => Vactcapofkofone,
M => M,
D => D,
B => B,
Vsigactofkofzero => Vsigactofkofone);
end struct;
|
gpl-2.0
|
2411660845cbb2cfe059e6ed15844aa9
| 0.559015 | 3.605744 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/WB.vhdl
| 1 | 1,907 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end;
architecture struct of WriteBack is
component BranchMux is
port (
BranchANDZero: in ctrl_t;
AddrALUresult, addr: in addr_t;
output: out addr_t);
end component;
component JumpDirMux is
port (
JumpDir: in ctrl_t;
jumpAddr, BranchMux: in addr_t;
output: out addr_t);
end component;
component JumpRegMux is
port (
JumpReg: in ctrl_t;
reg1data, JumpDirMux: in addr_t;
output: out addr_t);
end component;
component linkMux is
port (
Link : in ctrl_t;
pc: in word_t;
memToRegMux: in word_t;
output: out word_t);
end component;
component memToRegMux is
port (
MemtoReg: in ctrl_t;
aluResult : in word_t;
memReadData : in word_t;
output : out word_t);
end component;
signal BranchMuxOut, JumpDirMuxOut : addr_t;
signal MemToRegMuxOut : word_t;
begin
branchMux1: BranchMux
port map (BranchANDZero => TakeBranch, AddrALUresult => branch_addr, addr => pc_plus_4, output => BranchMuxOut);
jumpDirMux1: JumpDirMux
port map (JumpDir => JumpDir, jumpAddr => jump_addr, BranchMux => BranchMuxOut, output => JumpDirMuxOut);
jumpRegMux1:JumpRegMux
port map (JumpReg => JumpReg, reg1Data => regReadData1, JumpDirMux => JumpDirMuxOut, output => new_pc);
linkMux1: linkMux
port map(Link => Link, pc => pc_plus_4, memToRegMux => memToRegMuxOut, output => regWriteData);
memToRegMux1: memToRegMux
port map(MemtoReg => memToReg, aluresult => ALUResult, memReadData => memReadData, output => memToRegMuxOut);
end struct;
|
gpl-3.0
|
8aba752d3d84650781b99185d77eed6f
| 0.666492 | 3.653257 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_sigma.vhd
| 1 | 1,049 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_sigma is
port (
clock : in std_logic;
Pdashofk : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
sigma : out std_logic_vector(31 downto 0)
);
end k_ukf_sigma;
architecture struct of k_ukf_sigma is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sqrt IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_sqrt port map
( clock => clock,
data => Pdashofk,
result => Z);
M2 : k_ukf_mult port map
( clock => clock,
dataa => T,
datab => Z,
result => sigma);
end struct;
|
gpl-2.0
|
eac6b8c199c689a7a0e3e45eaac55d0c
| 0.589133 | 2.89779 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/mips_tb.vhdl
| 1 | 5,933 |
-- This is the top level MIPS architecture
-- FIXME Looping doesn't work.
-- Check if this was the case with previous versions too (Travis)
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity mips_tb is
end;
architecture struct of mips_tb is
component clkdivider is
port (
ticks : in natural;
bigclk : in std_logic;
rst : in std_logic;
smallclk : out std_logic
);
end component;
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
component mem is
generic (ROM : string := "");
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic;
-- VGA I/O
vgaclk, rst : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic;
-- LEDs
leds : out std_logic_vector(7 downto 0);
-- Push buttons
buttons : in std_logic_vector(3 downto 0);
-- DIP Switch IO
switch : in std_logic_vector(7 downto 0)
);
end component;
component cpu is
generic(PC_ADD : natural := 4;
SINGLE_ADDRESS_SPACE : boolean := false);
port(
clk : in std_logic;
rst : in std_logic;
-- Register File
readreg1, readreg2 : out reg_t;
writereg: out reg_t;
regWriteData: out word_t;
regReadData1, regReadData2 : in word_t;
regWrite : out std_logic;
-- Memory
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t;
-- Debug info
instruction : out instruction_t
);
end component;
signal readreg1, readreg2 : reg_t;
signal writereg: reg_t;
signal regWriteData: word_t;
signal regReadData1, regReadData2 : word_t;
signal regWrite : std_logic;
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
signal sysclk : std_logic := '0';
signal regrst : std_logic := '0';
signal rst : std_logic := '0';
signal online : boolean := true;
signal cpu_regWrite : std_logic;
signal cpu_readreg1 : reg_t;
signal cpu_readreg2 : reg_t;
signal test_readreg1 : reg_t;
signal test_readreg2 : reg_t;
signal clk : std_logic := '0';
--alias clk is sysclk;
-- VGA
-- nothing yet
begin
clkdivider1: clkdivider port map (
ticks => 8, bigclk => sysclk, rst => rst, smallclk => clk
);
regfile_inst: regFile port map (
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg,
writeData => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => clk,
rst => regrst,
regWrite => regWrite
);
mem_bus: mem
generic map (ROM => "")
port map (
addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
clk => clk,
vgaclk => '0', rst => '1',
r => open, g => open, b => open,
hsync => open, vsync => open,
leds => open,
-- Push buttons
buttons => B"0000",
-- DIP Switch IO
switch => B"1010_1010"
);
cpu_inst: cpu
generic map(SINGLE_ADDRESS_SPACE => true)
port map (
clk => clk,
rst => rst,
-- Register File
readreg1 => cpu_readreg1, readreg2 => cpu_readreg2,
writereg => writereg,
regWriteData => regWriteData,
regReadData1 => regReadData1, regReadData2 => regReadData2,
regWrite => cpu_RegWrite,
-- Memory
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr,
-- Debug info
instruction => open
);
regwrite <= cpu_RegWrite when online else '0';
readreg1 <= cpu_readreg1 when online else test_readreg1;
readreg2 <= cpu_readreg2 when online else test_readreg2;
test: process begin
wait for 4 ns;
rst <= '1';
wait for 4 ns;
rst <= '0';
wait for 4 ns;
wait for 5200 ns;
rst <= '0';
online <= false;
wait for 20 ns;
test_readreg1 <= R1;
wait for 8 ns;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "[r1] Failed to ori. 0xF000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
test_readreg1 <= R2;
test_readreg2 <= R1;
wait for 16 ns;
assert regReadData2 = X"0000_F000" report
ANSI_RED & "[r1] Failed to ori. 0xF000 /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
assert regReadData1 = X"0000_FBAD" report
ANSI_RED & "[r2] Failed to ori. 0xFBAD /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
test_readreg1 <= R3;
test_readreg2 <= R4;
wait for 16 ns;
assert regReadData1 = X"A000_0000" report
ANSI_RED & "[r3] 0xA000_0000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
assert regReadData2 = X"FFFF_FFAD" report
ANSI_RED & "[r4] 0xFFFF_FFAD /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
wait;
end process;
clkproc: process begin
sysclk <= not sysclk; wait for 1 ns; if not online then sysclk <= '0'; wait; end if;
end process;
end struct;
|
gpl-3.0
|
e36dfa12fa84270eaba0d0f36a5372bd
| 0.539356 | 3.860117 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_s2mm_sm.vhd
| 4 | 50,952 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sm.vhd
-- Description: This entity contains the S2MM DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sm is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1
-- Depth of DataMover command FIFO
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
-- S2MM Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_desc_flush : in std_logic ; --
s2mm_cmnd_idle : out std_logic ; --
s2mm_sts_idle : out std_logic ; --
s2mm_eof_set : out std_logic ; --
s2mm_eof_micro : in std_logic ; --
s2mm_sof_micro : in std_logic ; --
--
-- S2MM Descriptor Fetch Request --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
desc_available : in std_logic ; --
--
-- S2MM Status Stream RX Length --
s2mm_rxlength_valid : in std_logic ; --
s2mm_rxlength_clr : out std_logic ; --
s2mm_rxlength : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
-- DataMover Command --
s2mm_cmnd_wr : out std_logic ; --
s2mm_cmnd_data : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
s2mm_desc_info : in std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant S2MM_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-- Zero buffer length error - compare value
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal s2mm_rxlength_clr_cmb : std_logic := '0';
signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_rxlength_set : std_logic := '0';
signal blength_grtr_rxlength : std_logic := '0';
signal rxlength_fetched : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal desc_fetch_done_d1 : std_logic := '0';
signal zero_length_error : std_logic := '0';
signal s2mm_eof_set_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
signal eof_micro : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
EN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
eof_micro <= s2mm_eof_micro;
end generate EN_MICRO_DMA;
NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
eof_micro <= '0';
end generate NO_MICRO_DMA;
s2mm_eof_set <= s2mm_eof_set_i;
burst_type <= '1' and (not s2mm_keyhole);
-- A 0 s2mm_keyhole means incremental burst
-- a 1 s2mm_keyhole means fixed burst
-------------------------------------------------------------------------------
-- Not using rx length from status stream - (indeterminate length mode)
-------------------------------------------------------------------------------
GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-- For no status stream or not using length in status app field then eof set is
-- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd)
s2mm_eof_set_i <= '0';
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_fetch_done,
desc_update_done,
s2mm_cmnd_pending,
s2mm_stop,
s2mm_desc_flush,
updt_pending
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
-- fetch descriptor if desc available, not stopped and running
-- if (updt_pending = '1') then
-- s2mm_ns <= WAIT_STATUS;
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 1) then
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
else
s2mm_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- wait until fetch complete then execute
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- s2mm_ns <= EXECUTE_XFER;
elsif (s2mm_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
write_cmnd_cmb <= '1';
else
-- coverage off
s2mm_ns <= WAIT_STATUS;
-- coverage on
end if;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- if error exit
-- if(s2mm_stop = '1')then
-- s2mm_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(s2mm_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- s2mm_ns <= IDLE;
-- else
-- s2mm_ns <= WAIT_STATUS;
-- end if;
-- else
-- s2mm_ns <= EXECUTE_XFER;
-- end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- for no Q wait until desc updated
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register State Machine Statues
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register State Machine Signalse
-------------------------------------------------------------------------------
-- SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1';
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For Indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & PAD_VALUE
-- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro --'0' -- For Indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & s2mm_desc_blength;
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro -- For indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-- Drive unused output to zero
s2mm_rxlength_clr <= '0';
end generate GEN_SM_FOR_NO_LENGTH;
-------------------------------------------------------------------------------
-- Generate state machine and support logic for Using RX Length from Status
-- Stream
-------------------------------------------------------------------------------
-- this would not hold good for MCDMA
GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
GET_RXLENGTH,
CMPR_LENGTH,
EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_update_done,
-- desc_fetch_done,
updt_pending,
s2mm_rxlength_valid,
rxlength_fetched,
s2mm_cmnd_pending,
zero_length_error,
s2mm_stop,
s2mm_desc_flush
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
s2mm_rxlength_clr_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_rxlength_set <= '0';
--rxlength_fetched_clr <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE; --FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
desc_fetch_req_cmb <= '0';
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1')then
s2mm_ns <= IDLE;
-- Descriptor fetch complete
else --if(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
-- else
-- desc_fetch_req_cmb <= '1';
end if;
-------------------------------------------------------------------
WHEN GET_RXLENGTH =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- Buffer length zero, do not compare lengths, execute
-- command to force datamover to issue interror
elsif(zero_length_error = '1')then
s2mm_ns <= EXECUTE_XFER;
elsif(s2mm_rxlength_valid = '1')then
s2mm_rxlength_set <= '1';
s2mm_rxlength_clr_cmb <= '1';
s2mm_ns <= CMPR_LENGTH;
else
s2mm_ns <= GET_RXLENGTH;
end if;
-------------------------------------------------------------------
WHEN CMPR_LENGTH =>
s2mm_ns <= EXECUTE_XFER;
-------------------------------------------------------------------
when EXECUTE_XFER =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- write new command if one is not already pending
elsif(s2mm_cmnd_pending = '0')then
write_cmnd_cmb <= '1';
-- If descriptor queuing enabled then
-- do NOT need to wait for status
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
-- No queuing therefore must wait for
-- status before issuing next command
else
s2mm_ns <= WAIT_STATUS;
end if;
else
s2mm_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register state machine signals
-------------------------------------------------------------------------------
SM_SIG_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_req <= '0' ;
s2mm_rxlength_clr <= '0' ;
else
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
desc_fetch_req <= '1';
else
desc_fetch_req <= desc_fetch_req_cmb ;
end if;
s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb;
end if;
end if;
end process SM_SIG_REGISTER;
-------------------------------------------------------------------------------
-- Check for a ZERO value in descriptor buffer length. If there is
-- then flag an error and skip waiting for valid rxlength. cmnd will
-- get written to datamover with BTT=0 and datamover will flag dmaint error
-- which will be logged in desc, reset required to clear error
-------------------------------------------------------------------------------
REG_ALIGN_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_done_d1 <= '0';
else
desc_fetch_done_d1 <= desc_fetch_done;
end if;
end if;
end process REG_ALIGN_DONE;
-------------------------------------------------------------------------------
-- Zero length error detection - for determinate mode, detect early to prevent
-- rxlength calcuation from first taking place. This will force a 0 BTT
-- command to be issued to the datamover causing an internal error.
-------------------------------------------------------------------------------
REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
zero_length_error <= '0';
elsif(desc_fetch_done_d1 = '1'
and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then
zero_length_error <= '1';
end if;
end if;
end process REG_ZERO_LNGTH_ERR;
-------------------------------------------------------------------------------
-- Capture/Hold receive length from status stream. Also decrement length
-- based on if received length is greater than descriptor buffer size. (i.e. is
-- the case where multiple descriptors/buffers are used to describe one packet)
-------------------------------------------------------------------------------
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
rxlength <= (others => '0');
-- If command register rxlength from status stream fifo
elsif(s2mm_rxlength_set = '1')then
rxlength <= s2mm_rxlength;
-- On command write if current desc buffer size not greater
-- than current rxlength then decrement rxlength in preperations
-- for subsequent commands
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0))
- unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0)));
end if;
end if;
end process REG_RXLENGTH;
-------------------------------------------------------------------------------
-- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To'
-- Received Length value
-------------------------------------------------------------------------------
REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
blength_grtr_rxlength <= '0';
elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then
blength_grtr_rxlength <= '1';
else
blength_grtr_rxlength <= '0';
end if;
end if;
end process REG_BLENGTH_GRTR_RXLNGTH;
-------------------------------------------------------------------------------
-- On command assert rxlength fetched flag indicating length grabbed from
-- status stream fifo
-------------------------------------------------------------------------------
RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then
rxlength_fetched <= '0';
elsif(s2mm_rxlength_set = '1')then
rxlength_fetched <= '1';
end if;
end if;
end process RXLENGTH_FTCHED_PROCESS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF=0 to CMD Tag
& '0' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF=1 to CMD Tag
& '1' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- Set EOF=1
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF='0' to CMD Tag
& '0' -- Cat. IOC='0' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF='1' to CMD Tag
& '1' -- Cat. IOC='1' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
end generate GEN_SM_FOR_LENGTH;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for s2mm is Idle.
-------------------------------------------------------------------------------
-- Increment queue count for each command written if not occuring at
-- same time a status from DM being updated to SG engine
count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0'
else '0';
-- Decrement queue count for each status update to SG engine if not occuring
-- at same time as command being written to DM
count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1'
else '0';
-- keep track of number queue commands
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift (0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- indicate idle when no more queued commands
--s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
s2mm_sts_idle <= not cmnds_queued_shift(0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0';
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
bsd-3-clause
|
d0d23e2d71665bcca95684b7d90018af
| 0.375903 | 4.903946 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/plasoc_0_crossbar_wrap.vhd
| 2 | 66,403 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.plasoc_crossbar;
use work.plasoc_0_crossbar_wrap_pack.all;
entity plasoc_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 8;
axi_slave_amount : integer := 2;
axi_master_base_address : std_logic_vector := X"44a5000044a4000044a3000044a2000044a1000044a000000100000000000000";
axi_master_high_address : std_logic_vector := X"44a5ffff44a4ffff44a3ffff44a2ffff44a1ffff44a0ffff0103ffff0000ffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
cdma_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_awlen : in std_logic_vector(7 downto 0);
cdma_s_axi_awsize : in std_logic_vector(2 downto 0);
cdma_s_axi_awburst : in std_logic_vector(1 downto 0);
cdma_s_axi_awlock : in std_logic;
cdma_s_axi_awcache : in std_logic_vector(3 downto 0);
cdma_s_axi_awprot : in std_logic_vector(2 downto 0);
cdma_s_axi_awqos : in std_logic_vector(3 downto 0);
cdma_s_axi_awregion : in std_logic_vector(3 downto 0);
cdma_s_axi_awvalid : in std_logic;
cdma_s_axi_awready : out std_logic;
cdma_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cdma_s_axi_wlast : in std_logic;
cdma_s_axi_wvalid : in std_logic;
cdma_s_axi_wready : out std_logic;
cdma_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_bresp : out std_logic_vector(1 downto 0);
cdma_s_axi_bvalid : out std_logic;
cdma_s_axi_bready : in std_logic;
cdma_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_arlen : in std_logic_vector(7 downto 0);
cdma_s_axi_arsize : in std_logic_vector(2 downto 0);
cdma_s_axi_arburst : in std_logic_vector(1 downto 0);
cdma_s_axi_arlock : in std_logic;
cdma_s_axi_arcache : in std_logic_vector(3 downto 0);
cdma_s_axi_arprot : in std_logic_vector(2 downto 0);
cdma_s_axi_arqos : in std_logic_vector(3 downto 0);
cdma_s_axi_arregion : in std_logic_vector(3 downto 0);
cdma_s_axi_arvalid : in std_logic;
cdma_s_axi_arready : out std_logic;
cdma_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_rresp : out std_logic_vector(1 downto 0);
cdma_s_axi_rlast : out std_logic;
cdma_s_axi_rvalid : out std_logic;
cdma_s_axi_rready : in std_logic;
bram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_awlen : out std_logic_vector(7 downto 0);
bram_m_axi_awsize : out std_logic_vector(2 downto 0);
bram_m_axi_awburst : out std_logic_vector(1 downto 0);
bram_m_axi_awlock : out std_logic;
bram_m_axi_awcache : out std_logic_vector(3 downto 0);
bram_m_axi_awprot : out std_logic_vector(2 downto 0);
bram_m_axi_awqos : out std_logic_vector(3 downto 0);
bram_m_axi_awregion : out std_logic_vector(3 downto 0);
bram_m_axi_awvalid : out std_logic;
bram_m_axi_awready : in std_logic;
bram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
bram_m_axi_wlast : out std_logic;
bram_m_axi_wvalid : out std_logic;
bram_m_axi_wready : in std_logic;
bram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_bresp : in std_logic_vector(1 downto 0);
bram_m_axi_bvalid : in std_logic;
bram_m_axi_bready : out std_logic;
bram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_arlen : out std_logic_vector(7 downto 0);
bram_m_axi_arsize : out std_logic_vector(2 downto 0);
bram_m_axi_arburst : out std_logic_vector(1 downto 0);
bram_m_axi_arlock : out std_logic;
bram_m_axi_arcache : out std_logic_vector(3 downto 0);
bram_m_axi_arprot : out std_logic_vector(2 downto 0);
bram_m_axi_arqos : out std_logic_vector(3 downto 0);
bram_m_axi_arregion : out std_logic_vector(3 downto 0);
bram_m_axi_arvalid : out std_logic;
bram_m_axi_arready : in std_logic;
bram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_rresp : in std_logic_vector(1 downto 0);
bram_m_axi_rlast : in std_logic;
bram_m_axi_rvalid : in std_logic;
bram_m_axi_rready : out std_logic;
ram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_awlen : out std_logic_vector(7 downto 0);
ram_m_axi_awsize : out std_logic_vector(2 downto 0);
ram_m_axi_awburst : out std_logic_vector(1 downto 0);
ram_m_axi_awlock : out std_logic;
ram_m_axi_awcache : out std_logic_vector(3 downto 0);
ram_m_axi_awprot : out std_logic_vector(2 downto 0);
ram_m_axi_awqos : out std_logic_vector(3 downto 0);
ram_m_axi_awregion : out std_logic_vector(3 downto 0);
ram_m_axi_awvalid : out std_logic;
ram_m_axi_awready : in std_logic;
ram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ram_m_axi_wlast : out std_logic;
ram_m_axi_wvalid : out std_logic;
ram_m_axi_wready : in std_logic;
ram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_bresp : in std_logic_vector(1 downto 0);
ram_m_axi_bvalid : in std_logic;
ram_m_axi_bready : out std_logic;
ram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_arlen : out std_logic_vector(7 downto 0);
ram_m_axi_arsize : out std_logic_vector(2 downto 0);
ram_m_axi_arburst : out std_logic_vector(1 downto 0);
ram_m_axi_arlock : out std_logic;
ram_m_axi_arcache : out std_logic_vector(3 downto 0);
ram_m_axi_arprot : out std_logic_vector(2 downto 0);
ram_m_axi_arqos : out std_logic_vector(3 downto 0);
ram_m_axi_arregion : out std_logic_vector(3 downto 0);
ram_m_axi_arvalid : out std_logic;
ram_m_axi_arready : in std_logic;
ram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_rresp : in std_logic_vector(1 downto 0);
ram_m_axi_rlast : in std_logic;
ram_m_axi_rvalid : in std_logic;
ram_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
gpio_m_axi_awlock : out std_logic;
gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
gpio_m_axi_awvalid : out std_logic;
gpio_m_axi_awready : in std_logic;
gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
gpio_m_axi_wlast : out std_logic;
gpio_m_axi_wvalid : out std_logic;
gpio_m_axi_wready : in std_logic;
gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
gpio_m_axi_bvalid : in std_logic;
gpio_m_axi_bready : out std_logic;
gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
gpio_m_axi_arlock : out std_logic;
gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
gpio_m_axi_arvalid : out std_logic;
gpio_m_axi_arready : in std_logic;
gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
gpio_m_axi_rlast : in std_logic;
gpio_m_axi_rvalid : in std_logic;
gpio_m_axi_rready : out std_logic;
cdma_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_awlen : out std_logic_vector(7 downto 0);
cdma_m_axi_awsize : out std_logic_vector(2 downto 0);
cdma_m_axi_awburst : out std_logic_vector(1 downto 0);
cdma_m_axi_awlock : out std_logic;
cdma_m_axi_awcache : out std_logic_vector(3 downto 0);
cdma_m_axi_awprot : out std_logic_vector(2 downto 0);
cdma_m_axi_awqos : out std_logic_vector(3 downto 0);
cdma_m_axi_awregion : out std_logic_vector(3 downto 0);
cdma_m_axi_awvalid : out std_logic;
cdma_m_axi_awready : in std_logic;
cdma_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cdma_m_axi_wlast : out std_logic;
cdma_m_axi_wvalid : out std_logic;
cdma_m_axi_wready : in std_logic;
cdma_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_bresp : in std_logic_vector(1 downto 0);
cdma_m_axi_bvalid : in std_logic;
cdma_m_axi_bready : out std_logic;
cdma_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_arlen : out std_logic_vector(7 downto 0);
cdma_m_axi_arsize : out std_logic_vector(2 downto 0);
cdma_m_axi_arburst : out std_logic_vector(1 downto 0);
cdma_m_axi_arlock : out std_logic;
cdma_m_axi_arcache : out std_logic_vector(3 downto 0);
cdma_m_axi_arprot : out std_logic_vector(2 downto 0);
cdma_m_axi_arqos : out std_logic_vector(3 downto 0);
cdma_m_axi_arregion : out std_logic_vector(3 downto 0);
cdma_m_axi_arvalid : out std_logic;
cdma_m_axi_arready : in std_logic;
cdma_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_rresp : in std_logic_vector(1 downto 0);
cdma_m_axi_rlast : in std_logic;
cdma_m_axi_rvalid : in std_logic;
cdma_m_axi_rready : out std_logic;
uart_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_awlen : out std_logic_vector(7 downto 0);
uart_m_axi_awsize : out std_logic_vector(2 downto 0);
uart_m_axi_awburst : out std_logic_vector(1 downto 0);
uart_m_axi_awlock : out std_logic;
uart_m_axi_awcache : out std_logic_vector(3 downto 0);
uart_m_axi_awprot : out std_logic_vector(2 downto 0);
uart_m_axi_awqos : out std_logic_vector(3 downto 0);
uart_m_axi_awregion : out std_logic_vector(3 downto 0);
uart_m_axi_awvalid : out std_logic;
uart_m_axi_awready : in std_logic;
uart_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
uart_m_axi_wlast : out std_logic;
uart_m_axi_wvalid : out std_logic;
uart_m_axi_wready : in std_logic;
uart_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_bresp : in std_logic_vector(1 downto 0);
uart_m_axi_bvalid : in std_logic;
uart_m_axi_bready : out std_logic;
uart_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_arlen : out std_logic_vector(7 downto 0);
uart_m_axi_arsize : out std_logic_vector(2 downto 0);
uart_m_axi_arburst : out std_logic_vector(1 downto 0);
uart_m_axi_arlock : out std_logic;
uart_m_axi_arcache : out std_logic_vector(3 downto 0);
uart_m_axi_arprot : out std_logic_vector(2 downto 0);
uart_m_axi_arqos : out std_logic_vector(3 downto 0);
uart_m_axi_arregion : out std_logic_vector(3 downto 0);
uart_m_axi_arvalid : out std_logic;
uart_m_axi_arready : in std_logic;
uart_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_rresp : in std_logic_vector(1 downto 0);
uart_m_axi_rlast : in std_logic;
uart_m_axi_rvalid : in std_logic;
uart_m_axi_rready : out std_logic;
timer_extra_0_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_awlock : out std_logic;
timer_extra_0_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awvalid : out std_logic;
timer_extra_0_m_axi_awready : in std_logic;
timer_extra_0_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_extra_0_m_axi_wlast : out std_logic;
timer_extra_0_m_axi_wvalid : out std_logic;
timer_extra_0_m_axi_wready : in std_logic;
timer_extra_0_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_bvalid : in std_logic;
timer_extra_0_m_axi_bready : out std_logic;
timer_extra_0_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_arlock : out std_logic;
timer_extra_0_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arvalid : out std_logic;
timer_extra_0_m_axi_arready : in std_logic;
timer_extra_0_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_rlast : in std_logic;
timer_extra_0_m_axi_rvalid : in std_logic;
timer_extra_0_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end plasoc_0_crossbar_wrap;
architecture Behavioral of plasoc_0_crossbar_wrap is
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
signal s_axi_awid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_awaddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_awlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_awsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_awlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_wstrb : std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
signal s_axi_wlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_bresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_bvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_araddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_arlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_arsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_arlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_rdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_rresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_rlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal m_axi_awid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_awaddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_awlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_awsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_awlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_wstrb : std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
signal m_axi_wlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_bresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_bvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_araddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_arlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_arsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_arlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_rdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_rresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_rlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal s_address_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_axi_awid <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awid & cpu_s_axi_awid;
s_axi_awaddr <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awaddr & cpu_s_axi_awaddr;
s_axi_awlen <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awlen & cpu_s_axi_awlen;
s_axi_awsize <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awsize & cpu_s_axi_awsize;
s_axi_awburst <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awburst & cpu_s_axi_awburst;
s_axi_awlock <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awlock & cpu_s_axi_awlock;
s_axi_awcache <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awcache & cpu_s_axi_awcache;
s_axi_awprot <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awprot & cpu_s_axi_awprot;
s_axi_awqos <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awqos & cpu_s_axi_awqos;
s_axi_awregion <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awregion & cpu_s_axi_awregion;
s_axi_awvalid <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_awvalid & cpu_s_axi_awvalid;
s_axi_wdata <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_wdata & cpu_s_axi_wdata;
s_axi_wstrb <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_wstrb & cpu_s_axi_wstrb;
s_axi_wlast <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_wlast & cpu_s_axi_wlast;
s_axi_wvalid <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_wvalid & cpu_s_axi_wvalid;
s_axi_bready <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_bready & cpu_s_axi_bready;
s_axi_arid <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arid & cpu_s_axi_arid;
s_axi_araddr <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_araddr & cpu_s_axi_araddr;
s_axi_arlen <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arlen & cpu_s_axi_arlen;
s_axi_arsize <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arsize & cpu_s_axi_arsize;
s_axi_arburst <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arburst & cpu_s_axi_arburst;
s_axi_arlock <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arlock & cpu_s_axi_arlock;
s_axi_arcache <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arcache & cpu_s_axi_arcache;
s_axi_arprot <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arprot & cpu_s_axi_arprot;
s_axi_arqos <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arqos & cpu_s_axi_arqos;
s_axi_arregion <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arregion & cpu_s_axi_arregion;
s_axi_arvalid <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_arvalid & cpu_s_axi_arvalid;
s_axi_rready <= std_logic_vector(to_unsigned(0,0)) & cdma_s_axi_rready & cpu_s_axi_rready;
m_axi_awready <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_awready & uart_m_axi_awready & cdma_m_axi_awready & gpio_m_axi_awready & timer_m_axi_awready & int_m_axi_awready & ram_m_axi_awready & bram_m_axi_awready;
m_axi_wready <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_wready & uart_m_axi_wready & cdma_m_axi_wready & gpio_m_axi_wready & timer_m_axi_wready & int_m_axi_wready & ram_m_axi_wready & bram_m_axi_wready;
m_axi_bid <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_bid & uart_m_axi_bid & cdma_m_axi_bid & gpio_m_axi_bid & timer_m_axi_bid & int_m_axi_bid & ram_m_axi_bid & bram_m_axi_bid;
m_axi_bresp <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_bresp & uart_m_axi_bresp & cdma_m_axi_bresp & gpio_m_axi_bresp & timer_m_axi_bresp & int_m_axi_bresp & ram_m_axi_bresp & bram_m_axi_bresp;
m_axi_bvalid <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_bvalid & uart_m_axi_bvalid & cdma_m_axi_bvalid & gpio_m_axi_bvalid & timer_m_axi_bvalid & int_m_axi_bvalid & ram_m_axi_bvalid & bram_m_axi_bvalid;
m_axi_arready <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_arready & uart_m_axi_arready & cdma_m_axi_arready & gpio_m_axi_arready & timer_m_axi_arready & int_m_axi_arready & ram_m_axi_arready & bram_m_axi_arready;
m_axi_rid <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_rid & uart_m_axi_rid & cdma_m_axi_rid & gpio_m_axi_rid & timer_m_axi_rid & int_m_axi_rid & ram_m_axi_rid & bram_m_axi_rid;
m_axi_rdata <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_rdata & uart_m_axi_rdata & cdma_m_axi_rdata & gpio_m_axi_rdata & timer_m_axi_rdata & int_m_axi_rdata & ram_m_axi_rdata & bram_m_axi_rdata;
m_axi_rresp <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_rresp & uart_m_axi_rresp & cdma_m_axi_rresp & gpio_m_axi_rresp & timer_m_axi_rresp & int_m_axi_rresp & ram_m_axi_rresp & bram_m_axi_rresp;
m_axi_rlast <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_rlast & uart_m_axi_rlast & cdma_m_axi_rlast & gpio_m_axi_rlast & timer_m_axi_rlast & int_m_axi_rlast & ram_m_axi_rlast & bram_m_axi_rlast;
m_axi_rvalid <= std_logic_vector(to_unsigned(0,0)) & timer_extra_0_m_axi_rvalid & uart_m_axi_rvalid & cdma_m_axi_rvalid & gpio_m_axi_rvalid & timer_m_axi_rvalid & int_m_axi_rvalid & ram_m_axi_rvalid & bram_m_axi_rvalid;
cpu_s_axi_awready <= '0' when s_address_write_connected(0)='0' else s_axi_awready(0);
cdma_s_axi_awready <= '0' when s_address_write_connected(1)='0' else s_axi_awready(1);
cpu_s_axi_wready <= '0' when s_data_write_connected(0)='0' else s_axi_wready(0);
cdma_s_axi_wready <= '0' when s_data_write_connected(1)='0' else s_axi_wready(1);
cpu_s_axi_bid <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cdma_s_axi_bid <= (others=>'0') when s_response_write_connected(1)='0' else s_axi_bid((1+1)*axi_slave_id_width-1 downto 1*axi_slave_id_width);
cpu_s_axi_bresp <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bresp((1+0)*2-1 downto 0*2);
cdma_s_axi_bresp <= (others=>'0') when s_response_write_connected(1)='0' else s_axi_bresp((1+1)*2-1 downto 1*2);
cpu_s_axi_bvalid <= '0' when s_response_write_connected(0)='0' else s_axi_bvalid(0);
cdma_s_axi_bvalid <= '0' when s_response_write_connected(1)='0' else s_axi_bvalid(1);
cpu_s_axi_arready <= '0' when s_address_read_connected(0)='0' else s_axi_arready(0);
cdma_s_axi_arready <= '0' when s_address_read_connected(1)='0' else s_axi_arready(1);
cpu_s_axi_rid <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cdma_s_axi_rid <= (others=>'0') when s_data_read_connected(1)='0' else s_axi_rid((1+1)*axi_slave_id_width-1 downto 1*axi_slave_id_width);
cpu_s_axi_rdata <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cdma_s_axi_rdata <= (others=>'0') when s_data_read_connected(1)='0' else s_axi_rdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
cpu_s_axi_rresp <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rresp((1+0)*2-1 downto 0*2);
cdma_s_axi_rresp <= (others=>'0') when s_data_read_connected(1)='0' else s_axi_rresp((1+1)*2-1 downto 1*2);
cpu_s_axi_rlast <= '0' when s_data_read_connected(0)='0' else s_axi_rlast(0);
cdma_s_axi_rlast <= '0' when s_data_read_connected(1)='0' else s_axi_rlast(1);
cpu_s_axi_rvalid <= '0' when s_data_read_connected(0)='0' else s_axi_rvalid(0);
cdma_s_axi_rvalid <= '0' when s_data_read_connected(1)='0' else s_axi_rvalid(1);
bram_m_axi_awid <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
ram_m_axi_awid <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_awid <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
timer_m_axi_awid <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
gpio_m_axi_awid <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
cdma_m_axi_awid <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awid((1+5)*axi_master_id_width-1 downto 5*axi_master_id_width);
uart_m_axi_awid <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awid((1+6)*axi_master_id_width-1 downto 6*axi_master_id_width);
timer_extra_0_m_axi_awid <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awid((1+7)*axi_master_id_width-1 downto 7*axi_master_id_width);
bram_m_axi_awaddr <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awaddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
ram_m_axi_awaddr <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awaddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_awaddr <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awaddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
timer_m_axi_awaddr <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awaddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
gpio_m_axi_awaddr <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awaddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
cdma_m_axi_awaddr <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awaddr((1+5)*axi_address_width-1 downto 5*axi_address_width);
uart_m_axi_awaddr <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awaddr((1+6)*axi_address_width-1 downto 6*axi_address_width);
timer_extra_0_m_axi_awaddr <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awaddr((1+7)*axi_address_width-1 downto 7*axi_address_width);
bram_m_axi_awlen <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awlen((1+0)*8-1 downto 0*8);
ram_m_axi_awlen <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awlen((1+1)*8-1 downto 1*8);
int_m_axi_awlen <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awlen((1+2)*8-1 downto 2*8);
timer_m_axi_awlen <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awlen((1+3)*8-1 downto 3*8);
gpio_m_axi_awlen <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awlen((1+4)*8-1 downto 4*8);
cdma_m_axi_awlen <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awlen((1+5)*8-1 downto 5*8);
uart_m_axi_awlen <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awlen((1+6)*8-1 downto 6*8);
timer_extra_0_m_axi_awlen <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awlen((1+7)*8-1 downto 7*8);
bram_m_axi_awsize <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awsize((1+0)*3-1 downto 0*3);
ram_m_axi_awsize <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awsize((1+1)*3-1 downto 1*3);
int_m_axi_awsize <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awsize((1+2)*3-1 downto 2*3);
timer_m_axi_awsize <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awsize((1+3)*3-1 downto 3*3);
gpio_m_axi_awsize <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awsize((1+4)*3-1 downto 4*3);
cdma_m_axi_awsize <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awsize((1+5)*3-1 downto 5*3);
uart_m_axi_awsize <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awsize((1+6)*3-1 downto 6*3);
timer_extra_0_m_axi_awsize <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awsize((1+7)*3-1 downto 7*3);
bram_m_axi_awburst <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awburst((1+0)*2-1 downto 0*2);
ram_m_axi_awburst <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awburst((1+1)*2-1 downto 1*2);
int_m_axi_awburst <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awburst((1+2)*2-1 downto 2*2);
timer_m_axi_awburst <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awburst((1+3)*2-1 downto 3*2);
gpio_m_axi_awburst <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awburst((1+4)*2-1 downto 4*2);
cdma_m_axi_awburst <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awburst((1+5)*2-1 downto 5*2);
uart_m_axi_awburst <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awburst((1+6)*2-1 downto 6*2);
timer_extra_0_m_axi_awburst <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awburst((1+7)*2-1 downto 7*2);
bram_m_axi_awlock <= '0' when m_address_write_connected(0)='0' else m_axi_awlock(0);
ram_m_axi_awlock <= '0' when m_address_write_connected(1)='0' else m_axi_awlock(1);
int_m_axi_awlock <= '0' when m_address_write_connected(2)='0' else m_axi_awlock(2);
timer_m_axi_awlock <= '0' when m_address_write_connected(3)='0' else m_axi_awlock(3);
gpio_m_axi_awlock <= '0' when m_address_write_connected(4)='0' else m_axi_awlock(4);
cdma_m_axi_awlock <= '0' when m_address_write_connected(5)='0' else m_axi_awlock(5);
uart_m_axi_awlock <= '0' when m_address_write_connected(6)='0' else m_axi_awlock(6);
timer_extra_0_m_axi_awlock <= '0' when m_address_write_connected(7)='0' else m_axi_awlock(7);
bram_m_axi_awcache <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awcache((1+0)*4-1 downto 0*4);
ram_m_axi_awcache <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awcache((1+1)*4-1 downto 1*4);
int_m_axi_awcache <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awcache((1+2)*4-1 downto 2*4);
timer_m_axi_awcache <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awcache((1+3)*4-1 downto 3*4);
gpio_m_axi_awcache <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awcache((1+4)*4-1 downto 4*4);
cdma_m_axi_awcache <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awcache((1+5)*4-1 downto 5*4);
uart_m_axi_awcache <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awcache((1+6)*4-1 downto 6*4);
timer_extra_0_m_axi_awcache <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awcache((1+7)*4-1 downto 7*4);
bram_m_axi_awprot <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awprot((1+0)*3-1 downto 0*3);
ram_m_axi_awprot <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awprot((1+1)*3-1 downto 1*3);
int_m_axi_awprot <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awprot((1+2)*3-1 downto 2*3);
timer_m_axi_awprot <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awprot((1+3)*3-1 downto 3*3);
gpio_m_axi_awprot <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awprot((1+4)*3-1 downto 4*3);
cdma_m_axi_awprot <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awprot((1+5)*3-1 downto 5*3);
uart_m_axi_awprot <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awprot((1+6)*3-1 downto 6*3);
timer_extra_0_m_axi_awprot <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awprot((1+7)*3-1 downto 7*3);
bram_m_axi_awqos <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awqos((1+0)*4-1 downto 0*4);
ram_m_axi_awqos <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awqos((1+1)*4-1 downto 1*4);
int_m_axi_awqos <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awqos((1+2)*4-1 downto 2*4);
timer_m_axi_awqos <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awqos((1+3)*4-1 downto 3*4);
gpio_m_axi_awqos <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awqos((1+4)*4-1 downto 4*4);
cdma_m_axi_awqos <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awqos((1+5)*4-1 downto 5*4);
uart_m_axi_awqos <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awqos((1+6)*4-1 downto 6*4);
timer_extra_0_m_axi_awqos <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awqos((1+7)*4-1 downto 7*4);
bram_m_axi_awregion <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awregion((1+0)*4-1 downto 0*4);
ram_m_axi_awregion <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awregion((1+1)*4-1 downto 1*4);
int_m_axi_awregion <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awregion((1+2)*4-1 downto 2*4);
timer_m_axi_awregion <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awregion((1+3)*4-1 downto 3*4);
gpio_m_axi_awregion <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awregion((1+4)*4-1 downto 4*4);
cdma_m_axi_awregion <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awregion((1+5)*4-1 downto 5*4);
uart_m_axi_awregion <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awregion((1+6)*4-1 downto 6*4);
timer_extra_0_m_axi_awregion <= (others=>'0') when m_address_write_connected(7)='0' else m_axi_awregion((1+7)*4-1 downto 7*4);
bram_m_axi_awvalid <= '0' when m_address_write_connected(0)='0' else m_axi_awvalid(0);
ram_m_axi_awvalid <= '0' when m_address_write_connected(1)='0' else m_axi_awvalid(1);
int_m_axi_awvalid <= '0' when m_address_write_connected(2)='0' else m_axi_awvalid(2);
timer_m_axi_awvalid <= '0' when m_address_write_connected(3)='0' else m_axi_awvalid(3);
gpio_m_axi_awvalid <= '0' when m_address_write_connected(4)='0' else m_axi_awvalid(4);
cdma_m_axi_awvalid <= '0' when m_address_write_connected(5)='0' else m_axi_awvalid(5);
uart_m_axi_awvalid <= '0' when m_address_write_connected(6)='0' else m_axi_awvalid(6);
timer_extra_0_m_axi_awvalid <= '0' when m_address_write_connected(7)='0' else m_axi_awvalid(7);
bram_m_axi_wdata <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
ram_m_axi_wdata <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
int_m_axi_wdata <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wdata((1+2)*axi_data_width-1 downto 2*axi_data_width);
timer_m_axi_wdata <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wdata((1+3)*axi_data_width-1 downto 3*axi_data_width);
gpio_m_axi_wdata <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wdata((1+4)*axi_data_width-1 downto 4*axi_data_width);
cdma_m_axi_wdata <= (others=>'0') when m_data_write_connected(5)='0' else m_axi_wdata((1+5)*axi_data_width-1 downto 5*axi_data_width);
uart_m_axi_wdata <= (others=>'0') when m_data_write_connected(6)='0' else m_axi_wdata((1+6)*axi_data_width-1 downto 6*axi_data_width);
timer_extra_0_m_axi_wdata <= (others=>'0') when m_data_write_connected(7)='0' else m_axi_wdata((1+7)*axi_data_width-1 downto 7*axi_data_width);
bram_m_axi_wstrb <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wstrb((1+0)*axi_data_width/8-1 downto 0*axi_data_width/8);
ram_m_axi_wstrb <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wstrb((1+1)*axi_data_width/8-1 downto 1*axi_data_width/8);
int_m_axi_wstrb <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wstrb((1+2)*axi_data_width/8-1 downto 2*axi_data_width/8);
timer_m_axi_wstrb <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wstrb((1+3)*axi_data_width/8-1 downto 3*axi_data_width/8);
gpio_m_axi_wstrb <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wstrb((1+4)*axi_data_width/8-1 downto 4*axi_data_width/8);
cdma_m_axi_wstrb <= (others=>'0') when m_data_write_connected(5)='0' else m_axi_wstrb((1+5)*axi_data_width/8-1 downto 5*axi_data_width/8);
uart_m_axi_wstrb <= (others=>'0') when m_data_write_connected(6)='0' else m_axi_wstrb((1+6)*axi_data_width/8-1 downto 6*axi_data_width/8);
timer_extra_0_m_axi_wstrb <= (others=>'0') when m_data_write_connected(7)='0' else m_axi_wstrb((1+7)*axi_data_width/8-1 downto 7*axi_data_width/8);
bram_m_axi_wlast <= '0' when m_data_write_connected(0)='0' else m_axi_wlast(0);
ram_m_axi_wlast <= '0' when m_data_write_connected(1)='0' else m_axi_wlast(1);
int_m_axi_wlast <= '0' when m_data_write_connected(2)='0' else m_axi_wlast(2);
timer_m_axi_wlast <= '0' when m_data_write_connected(3)='0' else m_axi_wlast(3);
gpio_m_axi_wlast <= '0' when m_data_write_connected(4)='0' else m_axi_wlast(4);
cdma_m_axi_wlast <= '0' when m_data_write_connected(5)='0' else m_axi_wlast(5);
uart_m_axi_wlast <= '0' when m_data_write_connected(6)='0' else m_axi_wlast(6);
timer_extra_0_m_axi_wlast <= '0' when m_data_write_connected(7)='0' else m_axi_wlast(7);
bram_m_axi_wvalid <= '0' when m_data_write_connected(0)='0' else m_axi_wvalid(0);
ram_m_axi_wvalid <= '0' when m_data_write_connected(1)='0' else m_axi_wvalid(1);
int_m_axi_wvalid <= '0' when m_data_write_connected(2)='0' else m_axi_wvalid(2);
timer_m_axi_wvalid <= '0' when m_data_write_connected(3)='0' else m_axi_wvalid(3);
gpio_m_axi_wvalid <= '0' when m_data_write_connected(4)='0' else m_axi_wvalid(4);
cdma_m_axi_wvalid <= '0' when m_data_write_connected(5)='0' else m_axi_wvalid(5);
uart_m_axi_wvalid <= '0' when m_data_write_connected(6)='0' else m_axi_wvalid(6);
timer_extra_0_m_axi_wvalid <= '0' when m_data_write_connected(7)='0' else m_axi_wvalid(7);
bram_m_axi_bready <= '0' when m_response_write_connected(0)='0' else m_axi_bready(0);
ram_m_axi_bready <= '0' when m_response_write_connected(1)='0' else m_axi_bready(1);
int_m_axi_bready <= '0' when m_response_write_connected(2)='0' else m_axi_bready(2);
timer_m_axi_bready <= '0' when m_response_write_connected(3)='0' else m_axi_bready(3);
gpio_m_axi_bready <= '0' when m_response_write_connected(4)='0' else m_axi_bready(4);
cdma_m_axi_bready <= '0' when m_response_write_connected(5)='0' else m_axi_bready(5);
uart_m_axi_bready <= '0' when m_response_write_connected(6)='0' else m_axi_bready(6);
timer_extra_0_m_axi_bready <= '0' when m_response_write_connected(7)='0' else m_axi_bready(7);
bram_m_axi_arid <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
ram_m_axi_arid <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_arid <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
timer_m_axi_arid <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
gpio_m_axi_arid <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
cdma_m_axi_arid <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arid((1+5)*axi_master_id_width-1 downto 5*axi_master_id_width);
uart_m_axi_arid <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arid((1+6)*axi_master_id_width-1 downto 6*axi_master_id_width);
timer_extra_0_m_axi_arid <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arid((1+7)*axi_master_id_width-1 downto 7*axi_master_id_width);
bram_m_axi_araddr <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_araddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
ram_m_axi_araddr <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_araddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_araddr <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_araddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
timer_m_axi_araddr <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_araddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
gpio_m_axi_araddr <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_araddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
cdma_m_axi_araddr <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_araddr((1+5)*axi_address_width-1 downto 5*axi_address_width);
uart_m_axi_araddr <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_araddr((1+6)*axi_address_width-1 downto 6*axi_address_width);
timer_extra_0_m_axi_araddr <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_araddr((1+7)*axi_address_width-1 downto 7*axi_address_width);
bram_m_axi_arlen <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arlen((1+0)*8-1 downto 0*8);
ram_m_axi_arlen <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arlen((1+1)*8-1 downto 1*8);
int_m_axi_arlen <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arlen((1+2)*8-1 downto 2*8);
timer_m_axi_arlen <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arlen((1+3)*8-1 downto 3*8);
gpio_m_axi_arlen <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arlen((1+4)*8-1 downto 4*8);
cdma_m_axi_arlen <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arlen((1+5)*8-1 downto 5*8);
uart_m_axi_arlen <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arlen((1+6)*8-1 downto 6*8);
timer_extra_0_m_axi_arlen <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arlen((1+7)*8-1 downto 7*8);
bram_m_axi_arsize <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arsize((1+0)*3-1 downto 0*3);
ram_m_axi_arsize <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arsize((1+1)*3-1 downto 1*3);
int_m_axi_arsize <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arsize((1+2)*3-1 downto 2*3);
timer_m_axi_arsize <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arsize((1+3)*3-1 downto 3*3);
gpio_m_axi_arsize <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arsize((1+4)*3-1 downto 4*3);
cdma_m_axi_arsize <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arsize((1+5)*3-1 downto 5*3);
uart_m_axi_arsize <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arsize((1+6)*3-1 downto 6*3);
timer_extra_0_m_axi_arsize <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arsize((1+7)*3-1 downto 7*3);
bram_m_axi_arburst <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arburst((1+0)*2-1 downto 0*2);
ram_m_axi_arburst <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arburst((1+1)*2-1 downto 1*2);
int_m_axi_arburst <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arburst((1+2)*2-1 downto 2*2);
timer_m_axi_arburst <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arburst((1+3)*2-1 downto 3*2);
gpio_m_axi_arburst <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arburst((1+4)*2-1 downto 4*2);
cdma_m_axi_arburst <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arburst((1+5)*2-1 downto 5*2);
uart_m_axi_arburst <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arburst((1+6)*2-1 downto 6*2);
timer_extra_0_m_axi_arburst <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arburst((1+7)*2-1 downto 7*2);
bram_m_axi_arlock <= '0' when m_address_read_connected(0)='0' else m_axi_arlock(0);
ram_m_axi_arlock <= '0' when m_address_read_connected(1)='0' else m_axi_arlock(1);
int_m_axi_arlock <= '0' when m_address_read_connected(2)='0' else m_axi_arlock(2);
timer_m_axi_arlock <= '0' when m_address_read_connected(3)='0' else m_axi_arlock(3);
gpio_m_axi_arlock <= '0' when m_address_read_connected(4)='0' else m_axi_arlock(4);
cdma_m_axi_arlock <= '0' when m_address_read_connected(5)='0' else m_axi_arlock(5);
uart_m_axi_arlock <= '0' when m_address_read_connected(6)='0' else m_axi_arlock(6);
timer_extra_0_m_axi_arlock <= '0' when m_address_read_connected(7)='0' else m_axi_arlock(7);
bram_m_axi_arcache <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arcache((1+0)*4-1 downto 0*4);
ram_m_axi_arcache <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arcache((1+1)*4-1 downto 1*4);
int_m_axi_arcache <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arcache((1+2)*4-1 downto 2*4);
timer_m_axi_arcache <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arcache((1+3)*4-1 downto 3*4);
gpio_m_axi_arcache <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arcache((1+4)*4-1 downto 4*4);
cdma_m_axi_arcache <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arcache((1+5)*4-1 downto 5*4);
uart_m_axi_arcache <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arcache((1+6)*4-1 downto 6*4);
timer_extra_0_m_axi_arcache <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arcache((1+7)*4-1 downto 7*4);
bram_m_axi_arprot <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arprot((1+0)*3-1 downto 0*3);
ram_m_axi_arprot <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arprot((1+1)*3-1 downto 1*3);
int_m_axi_arprot <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arprot((1+2)*3-1 downto 2*3);
timer_m_axi_arprot <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arprot((1+3)*3-1 downto 3*3);
gpio_m_axi_arprot <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arprot((1+4)*3-1 downto 4*3);
cdma_m_axi_arprot <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arprot((1+5)*3-1 downto 5*3);
uart_m_axi_arprot <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arprot((1+6)*3-1 downto 6*3);
timer_extra_0_m_axi_arprot <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arprot((1+7)*3-1 downto 7*3);
bram_m_axi_arqos <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arqos((1+0)*4-1 downto 0*4);
ram_m_axi_arqos <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arqos((1+1)*4-1 downto 1*4);
int_m_axi_arqos <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arqos((1+2)*4-1 downto 2*4);
timer_m_axi_arqos <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arqos((1+3)*4-1 downto 3*4);
gpio_m_axi_arqos <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arqos((1+4)*4-1 downto 4*4);
cdma_m_axi_arqos <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arqos((1+5)*4-1 downto 5*4);
uart_m_axi_arqos <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arqos((1+6)*4-1 downto 6*4);
timer_extra_0_m_axi_arqos <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arqos((1+7)*4-1 downto 7*4);
bram_m_axi_arregion <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arregion((1+0)*4-1 downto 0*4);
ram_m_axi_arregion <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arregion((1+1)*4-1 downto 1*4);
int_m_axi_arregion <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arregion((1+2)*4-1 downto 2*4);
timer_m_axi_arregion <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arregion((1+3)*4-1 downto 3*4);
gpio_m_axi_arregion <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arregion((1+4)*4-1 downto 4*4);
cdma_m_axi_arregion <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arregion((1+5)*4-1 downto 5*4);
uart_m_axi_arregion <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arregion((1+6)*4-1 downto 6*4);
timer_extra_0_m_axi_arregion <= (others=>'0') when m_address_read_connected(7)='0' else m_axi_arregion((1+7)*4-1 downto 7*4);
bram_m_axi_arvalid <= '0' when m_address_read_connected(0)='0' else m_axi_arvalid(0);
ram_m_axi_arvalid <= '0' when m_address_read_connected(1)='0' else m_axi_arvalid(1);
int_m_axi_arvalid <= '0' when m_address_read_connected(2)='0' else m_axi_arvalid(2);
timer_m_axi_arvalid <= '0' when m_address_read_connected(3)='0' else m_axi_arvalid(3);
gpio_m_axi_arvalid <= '0' when m_address_read_connected(4)='0' else m_axi_arvalid(4);
cdma_m_axi_arvalid <= '0' when m_address_read_connected(5)='0' else m_axi_arvalid(5);
uart_m_axi_arvalid <= '0' when m_address_read_connected(6)='0' else m_axi_arvalid(6);
timer_extra_0_m_axi_arvalid <= '0' when m_address_read_connected(7)='0' else m_axi_arvalid(7);
bram_m_axi_rready <= '0' when m_data_read_connected(0)='0' else m_axi_rready(0);
ram_m_axi_rready <= '0' when m_data_read_connected(1)='0' else m_axi_rready(1);
int_m_axi_rready <= '0' when m_data_read_connected(2)='0' else m_axi_rready(2);
timer_m_axi_rready <= '0' when m_data_read_connected(3)='0' else m_axi_rready(3);
gpio_m_axi_rready <= '0' when m_data_read_connected(4)='0' else m_axi_rready(4);
cdma_m_axi_rready <= '0' when m_data_read_connected(5)='0' else m_axi_rready(5);
uart_m_axi_rready <= '0' when m_data_read_connected(6)='0' else m_axi_rready(6);
timer_extra_0_m_axi_rready <= '0' when m_data_read_connected(7)='0' else m_axi_rready(7);
plasoc_crossbar_inst : plasoc_crossbar
generic map
(
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
axi_master_amount => axi_master_amount,
axi_slave_id_width => axi_slave_id_width,
axi_slave_amount => axi_slave_amount,
axi_master_base_address => axi_master_base_address,
axi_master_high_address => axi_master_high_address
)
port map
(
aclk => aclk,
aresetn => aresetn,
s_address_write_connected => s_address_write_connected,
s_data_write_connected => s_data_write_connected,
s_response_write_connected => s_response_write_connected,
s_address_read_connected => s_address_read_connected,
s_data_read_connected => s_data_read_connected,
m_address_write_connected => m_address_write_connected,
m_data_write_connected => m_data_write_connected,
m_response_write_connected => m_response_write_connected,
m_address_read_connected => m_address_read_connected,
m_data_read_connected => m_data_read_connected,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awqos => s_axi_awqos,
s_axi_awregion => s_axi_awregion,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arqos => s_axi_arqos,
s_axi_arregion => s_axi_arregion,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
end Behavioral;
|
mit
|
003718e18e6bd1293260385556283c07
| 0.677469 | 2.472189 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/tsc.vhdl
| 1 | 1,188 |
-- Counts clock cycles elapsed since system startup
-- FIXME Maybe use a separate clock? VGA for example?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_tsc is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE
);
end mmio_tsc;
architecture mmio of mmio_tsc is
constant reading : std_logic := '0';
signal tstamp : word_t := ZERO;
signal data_out : word_t;
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
process(clk) begin
if rising_edge(clk) then
if size /= "00" and en = '1' then
case wr is
when reading => data_out <= tstamp;
when others => null;
end case;
end if;
tstamp <= vec_increment(tstamp);
end if;
end process;
end;
|
gpl-3.0
|
10f6a97035945beda1edb5d94e3c0c4a
| 0.520202 | 3.735849 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_int_axi4_write_cntrl.vhd
| 1 | 6,106 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 28, 2017
--! @brief Contains the entity and architecture of the
--! Interrupt Controller's Slave AXI4-Lite Write
--! Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_int_pack.all;
--! The Write Controller implements a Slave AXI4-Lite Write
--! interface in order to allow a Master interface to write to
--! the registers of the core.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_int_axi4_write_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Interrupt Controller parameters.
int_enables_address : std_logic_vector := X"0000" --! Defines the offset for the Interrupt Enables register.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Interrupt Controller interface.
int_enables : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0') --! Interrupt Enables register.
);
end plasoc_int_axi4_write_cntrl;
architecture Behavioral of plasoc_int_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
-- Drive the axi write interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
int_enables <= (others=>'0');
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Sample address interface on handshake and go start
-- performing the write operation.
if axi_awvalid='1' and axi_awready_buff='1' then
-- Prevent the master from sending any more control information.
axi_awready_buff <= '0';
-- Sample the address sent from the master.
axi_awaddr_buff <= axi_awaddr;
-- Begin to read data to write.
axi_wready_buff <= '1';
state <= state_write;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_awready_buff <= '1';
end if;
-- WRITE mode.
when state_write=>
-- Wait for handshake.
if axi_wvalid='1' and axi_wready_buff='1' then
-- Prevent the master from sending any more data.
axi_wready_buff <= '0';
-- Only sample written data if the address is valid.
if axi_awaddr_buff=int_enables_address then
-- Only sample the specified bytes.
for each_byte in 0 to axi_data_width/8-1 loop
if axi_wstrb(each_byte)='1' then
int_enables(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end loop;
end if;
-- Begin to transmit the response.
state <= state_response;
axi_bvalid_buff <= '1';
end if;
-- RESPONSE mode.
when state_response=>
-- Wait for handshake.
if axi_bvalid_buff='1' and axi_bready='1' then
-- Starting waiting for more address information on
-- successful handshake.
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
4cd3cc3f0dbf2c2a083a5aa9a953a327
| 0.51605 | 4.533036 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/axiplasma_wrapper.vhd
| 1 | 114,895 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Wrapper Plasma-SoC Top Module.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_cpu_pack.plasoc_cpu;
use work.plasoc_int_pack.plasoc_int;
use work.plasoc_int_pack.default_interrupt_total;
use work.plasoc_timer_pack.plasoc_timer;
use work.plasoc_gpio_pack.plasoc_gpio;
use work.plasoc_uart_pack.plasoc_uart;
use work.plasoc_0_crossbar_wrap_pack.plasoc_0_crossbar_wrap;
use work.plasoc_0_crossbar_wrap_pack.clogb2;
use work.plasoc_axi4_full2lite_pack.plasoc_axi4_full2lite;
use work.vc707_pack.vc707_default_gpio_width;
entity axiplasma_wrapper is
generic (
lower_app : string := "boot";
upper_app : string := "none";
upper_ext : boolean := true); -- Setting upper_ext to false for hardware deployment isn't supported!
port(
sys_clk_p : in std_logic; -- 200 MHz on the VC707.
sys_clk_n : in std_logic; -- 200 MHz on the VC707.
sys_rst : in std_logic;
gpio_output : out std_logic_vector(vc707_default_gpio_width-1 downto 0);
gpio_input : in std_logic_vector(vc707_default_gpio_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR3_addr : out std_logic_vector(13 downto 0);
DDR3_ba : out std_logic_vector(2 downto 0);
DDR3_cas_n : out std_logic;
DDR3_ck_n : out std_logic_vector(0 downto 0);
DDR3_ck_p : out std_logic_vector(0 downto 0);
DDR3_cke : out std_logic_vector(0 downto 0);
DDR3_cs_n : out std_logic_vector(0 downto 0);
DDR3_dm : out std_logic_vector(7 downto 0);
DDR3_dq : inout std_logic_vector(63 downto 0);
DDR3_dqs_n : inout std_logic_vector(7 downto 0);
DDR3_dqs_p : inout std_logic_vector(7 downto 0);
DDR3_odt : out std_logic_vector(0 downto 0);
DDR3_ras_n : out std_logic;
DDR3_reset_n : out std_logic;
DDR3_we_n : out std_logic);
end axiplasma_wrapper;
architecture Behavioral of axiplasma_wrapper is
component clk_wiz_0 is
port (
aclk : out std_logic;
sys_rst : in std_logic;
locked : out std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic);
end component;
component proc_sys_reset_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0));
end component;
component mig_wrap_wrapper is
port (
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_cas_n : out STD_LOGIC;
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
SYS_CLK_clk_n : in STD_LOGIC;
SYS_CLK_clk_p : in STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_rst : in STD_LOGIC;
ui_addn_clk_0 : out STD_LOGIC;
ui_clk_sync_rst : out STD_LOGIC);
end component;
-- Component declarations.
component bram is
generic (
select_app : string := "none"; -- jump, boot, main
address_width : integer := 18;
data_width : integer := 32;
bram_depth : integer := 65536);
port(
bram_rst_a : in std_logic;
bram_clk_a : in std_logic;
bram_en_a : in std_logic;
bram_we_a : in std_logic_vector(data_width/8-1 downto 0);
bram_addr_a : in std_logic_vector(address_width-1 downto 0);
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0);
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0'));
end component;
component axi_cdma_0 is
port (
m_axi_aclk : in std_logic;
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
cdma_introut : out std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(5 downto 0);
s_axi_lite_wready : out std_logic;
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bready : in std_logic;
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_arready : out std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_araddr : in std_logic_vector(5 downto 0);
s_axi_lite_rready : in std_logic;
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_arready : in std_logic;
m_axi_arvalid : out std_logic;
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_rready : out std_logic;
m_axi_rvalid : in std_logic;
m_axi_rdata : in std_logic_vector(31 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rlast : in std_logic;
m_axi_awready : in std_logic;
m_axi_awvalid : out std_logic;
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_wready : in std_logic;
m_axi_wvalid : out std_logic;
m_axi_wdata : out std_logic_vector(31 downto 0);
m_axi_wstrb : out std_logic_vector(3 downto 0);
m_axi_wlast : out std_logic;
m_axi_bready : out std_logic;
m_axi_bvalid : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
cdma_tvect_out : out std_logic_vector(31 downto 0));
end component;
component axi_bram_ctrl_0 is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awid : in std_logic_vector(0 downto 0);
s_axi_awaddr : in std_logic_vector(15 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(0 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(0 downto 0);
s_axi_araddr : in std_logic_vector(15 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(0 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector(3 downto 0);
bram_addr_a : out std_logic_vector(15 downto 0);
bram_wrdata_a : out std_logic_vector(31 downto 0);
bram_rddata_a : in std_logic_vector(31 downto 0));
end component;
component axi_bram_ctrl_1 is
port (
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awid : in std_logic_vector(0 downto 0);
s_axi_awaddr : in std_logic_vector(17 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(0 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(0 downto 0);
s_axi_araddr : in std_logic_vector(17 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(0 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector(3 downto 0);
bram_addr_a : out std_logic_vector(17 downto 0);
bram_wrdata_a : out std_logic_vector(31 downto 0);
bram_rddata_a : in std_logic_vector(31 downto 0));
end component;
constant axi_address_width : integer := 32;
constant axi_data_width : integer := 32;
constant axi_master_amount : integer := 5;
constant axi_slave_amount : integer := 2;
constant axi_slave_id_width : integer := 0;
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
constant axi_lite_address_width : integer := 16; -- a misnomer.
constant axi_ram_address_width : integer := 18;
constant axi_ram_depth : integer := 65536;
signal aclk : std_logic;
signal ddr_reset : std_logic;
signal ddr_clock : std_logic;
signal aresetn : std_logic_vector(0 downto 0);
signal cross_aresetn : std_logic_vector(0 downto 0);
signal dcm_locked : std_logic;
signal cpu_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_axi_full_awlen : std_logic_vector(7 downto 0);
signal cpu_axi_full_awsize : std_logic_vector(2 downto 0);
signal cpu_axi_full_awburst : std_logic_vector(1 downto 0);
signal cpu_axi_full_awlock : std_logic;
signal cpu_axi_full_awcache : std_logic_vector(3 downto 0);
signal cpu_axi_full_awprot : std_logic_vector(2 downto 0);
signal cpu_axi_full_awqos : std_logic_vector(3 downto 0);
signal cpu_axi_full_awregion : std_logic_vector(3 downto 0);
signal cpu_axi_full_awvalid : std_logic;
signal cpu_axi_full_awready : std_logic;
signal cpu_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cpu_axi_full_wlast : std_logic;
signal cpu_axi_full_wvalid : std_logic;
signal cpu_axi_full_wready : std_logic;
signal cpu_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_bresp : std_logic_vector(1 downto 0);
signal cpu_axi_full_bvalid : std_logic;
signal cpu_axi_full_bready : std_logic;
signal cpu_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cpu_axi_full_arlen : std_logic_vector(7 downto 0);
signal cpu_axi_full_arsize : std_logic_vector(2 downto 0);
signal cpu_axi_full_arburst : std_logic_vector(1 downto 0);
signal cpu_axi_full_arlock : std_logic;
signal cpu_axi_full_arcache : std_logic_vector(3 downto 0);
signal cpu_axi_full_arprot : std_logic_vector(2 downto 0);
signal cpu_axi_full_arqos : std_logic_vector(3 downto 0);
signal cpu_axi_full_arregion : std_logic_vector(3 downto 0);
signal cpu_axi_full_arvalid : std_logic;
signal cpu_axi_full_arready : std_logic;
signal cpu_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cpu_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cpu_axi_full_rresp : std_logic_vector(1 downto 0);
signal cpu_axi_full_rlast : std_logic;
signal cpu_axi_full_rvalid : std_logic;
signal cpu_axi_full_rready : std_logic;
signal cdma_axi_full_awid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdma_axi_full_awlen : std_logic_vector(7 downto 0);
signal cdma_axi_full_awsize : std_logic_vector(2 downto 0);
signal cdma_axi_full_awburst : std_logic_vector(1 downto 0);
signal cdma_axi_full_awlock : std_logic;
signal cdma_axi_full_awcache : std_logic_vector(3 downto 0);
signal cdma_axi_full_awprot : std_logic_vector(2 downto 0);
signal cdma_axi_full_awqos : std_logic_vector(3 downto 0);
signal cdma_axi_full_awregion : std_logic_vector(3 downto 0);
signal cdma_axi_full_awvalid : std_logic;
signal cdma_axi_full_awready : std_logic;
signal cdma_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdma_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cdma_axi_full_wlast : std_logic;
signal cdma_axi_full_wvalid : std_logic;
signal cdma_axi_full_wready : std_logic;
signal cdma_axi_full_bid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_bresp : std_logic_vector(1 downto 0);
signal cdma_axi_full_bvalid : std_logic;
signal cdma_axi_full_bready : std_logic;
signal cdma_axi_full_arid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdma_axi_full_arlen : std_logic_vector(7 downto 0);
signal cdma_axi_full_arsize : std_logic_vector(2 downto 0);
signal cdma_axi_full_arburst : std_logic_vector(1 downto 0);
signal cdma_axi_full_arlock : std_logic;
signal cdma_axi_full_arcache : std_logic_vector(3 downto 0);
signal cdma_axi_full_arprot : std_logic_vector(2 downto 0);
signal cdma_axi_full_arqos : std_logic_vector(3 downto 0);
signal cdma_axi_full_arregion : std_logic_vector(3 downto 0);
signal cdma_axi_full_arvalid : std_logic;
signal cdma_axi_full_arready : std_logic;
signal cdma_axi_full_rid : std_logic_vector(axi_slave_id_width-1 downto 0);
signal cdma_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdma_axi_full_rresp : std_logic_vector(1 downto 0);
signal cdma_axi_full_rlast : std_logic;
signal cdma_axi_full_rvalid : std_logic;
signal cdma_axi_full_rready : std_logic;
signal bram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal bram_axi_full_awlen : std_logic_vector(7 downto 0);
signal bram_axi_full_awsize : std_logic_vector(2 downto 0);
signal bram_axi_full_awburst : std_logic_vector(1 downto 0);
signal bram_axi_full_awlock : std_logic;
signal bram_axi_full_awcache : std_logic_vector(3 downto 0);
signal bram_axi_full_awprot : std_logic_vector(2 downto 0);
signal bram_axi_full_awqos : std_logic_vector(3 downto 0);
signal bram_axi_full_awregion : std_logic_vector(3 downto 0);
signal bram_axi_full_awvalid : std_logic;
signal bram_axi_full_awready : std_logic;
signal bram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal bram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal bram_axi_full_wlast : std_logic;
signal bram_axi_full_wvalid : std_logic;
signal bram_axi_full_wready : std_logic;
signal bram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_bresp : std_logic_vector(1 downto 0);
signal bram_axi_full_bvalid : std_logic;
signal bram_axi_full_bready : std_logic;
signal bram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal bram_axi_full_arlen : std_logic_vector(7 downto 0);
signal bram_axi_full_arsize : std_logic_vector(2 downto 0);
signal bram_axi_full_arburst : std_logic_vector(1 downto 0);
signal bram_axi_full_arlock : std_logic;
signal bram_axi_full_arcache : std_logic_vector(3 downto 0);
signal bram_axi_full_arprot : std_logic_vector(2 downto 0);
signal bram_axi_full_arqos : std_logic_vector(3 downto 0);
signal bram_axi_full_arregion : std_logic_vector(3 downto 0);
signal bram_axi_full_arvalid : std_logic;
signal bram_axi_full_arready : std_logic;
signal bram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal bram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal bram_axi_full_rresp : std_logic_vector(1 downto 0);
signal bram_axi_full_rlast : std_logic;
signal bram_axi_full_rvalid : std_logic;
signal bram_axi_full_rready : std_logic;
signal bram_bram_rst_a : STD_LOGIC;
signal bram_bram_clk_a : STD_LOGIC;
signal bram_bram_en_a : STD_LOGIC;
signal bram_bram_we_a : STD_LOGIC_VECTOR(axi_data_width/8-1 DOWNTO 0);
signal bram_bram_addr_a : STD_LOGIC_VECTOR(axi_lite_address_width-1 DOWNTO 0);
signal bram_bram_wrdata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0);
signal bram_bram_rddata_a : STD_LOGIC_VECTOR(axi_data_width-1 DOWNTO 0);
signal ram_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal ram_axi_full_awlen : std_logic_vector(7 downto 0);
signal ram_axi_full_awsize : std_logic_vector(2 downto 0);
signal ram_axi_full_awburst : std_logic_vector(1 downto 0);
signal ram_axi_full_awlock : std_logic;
signal ram_axi_full_awcache : std_logic_vector(3 downto 0);
signal ram_axi_full_awprot : std_logic_vector(2 downto 0);
signal ram_axi_full_awqos : std_logic_vector(3 downto 0);
signal ram_axi_full_awregion : std_logic_vector(3 downto 0);
signal ram_axi_full_awvalid : std_logic;
signal ram_axi_full_awready : std_logic;
signal ram_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal ram_axi_full_wlast : std_logic;
signal ram_axi_full_wvalid : std_logic;
signal ram_axi_full_wready : std_logic;
signal ram_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_bresp : std_logic_vector(1 downto 0);
signal ram_axi_full_bvalid : std_logic;
signal ram_axi_full_bready : std_logic;
signal ram_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal ram_axi_full_arlen : std_logic_vector(7 downto 0);
signal ram_axi_full_arsize : std_logic_vector(2 downto 0);
signal ram_axi_full_arburst : std_logic_vector(1 downto 0);
signal ram_axi_full_arlock : std_logic;
signal ram_axi_full_arcache : std_logic_vector(3 downto 0);
signal ram_axi_full_arprot : std_logic_vector(2 downto 0);
signal ram_axi_full_arqos : std_logic_vector(3 downto 0);
signal ram_axi_full_arregion : std_logic_vector(3 downto 0);
signal ram_axi_full_arvalid : std_logic;
signal ram_axi_full_arready : std_logic;
signal ram_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal ram_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal ram_axi_full_rresp : std_logic_vector(1 downto 0);
signal ram_axi_full_rlast : std_logic;
signal ram_axi_full_rvalid : std_logic;
signal ram_axi_full_rready : std_logic;
signal ram_axi_full_arlock_slv : std_logic_vector (0 downto 0);
signal ram_axi_full_awlock_slv : std_logic_vector (0 downto 0);
signal ram_axi_full_arid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_awid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_bid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_axi_full_rid_slv : std_logic_vector(3 downto 0) := (others=>'0');
signal ram_bram_rst_a : std_logic;
signal ram_bram_clk_a : std_logic;
signal ram_bram_en_a : std_logic;
signal ram_bram_we_a : std_logic_vector(axi_data_width/8-1 downto 0);
signal ram_bram_addr_a : std_logic_vector(axi_ram_address_width-1 downto 0);
signal ram_bram_wrdata_a : std_logic_vector(axi_data_width-1 downto 0);
signal ram_bram_rddata_a : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_awlen : std_logic_vector(7 downto 0);
signal int_axi_full_awsize : std_logic_vector(2 downto 0);
signal int_axi_full_awburst : std_logic_vector(1 downto 0);
signal int_axi_full_awlock : std_logic;
signal int_axi_full_awcache : std_logic_vector(3 downto 0);
signal int_axi_full_awprot : std_logic_vector(2 downto 0);
signal int_axi_full_awqos : std_logic_vector(3 downto 0);
signal int_axi_full_awregion : std_logic_vector(3 downto 0);
signal int_axi_full_awvalid : std_logic;
signal int_axi_full_awready : std_logic;
signal int_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_full_wlast : std_logic;
signal int_axi_full_wvalid : std_logic;
signal int_axi_full_wready : std_logic;
signal int_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_bresp : std_logic_vector(1 downto 0);
signal int_axi_full_bvalid : std_logic;
signal int_axi_full_bready : std_logic;
signal int_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal int_axi_full_arlen : std_logic_vector(7 downto 0);
signal int_axi_full_arsize : std_logic_vector(2 downto 0);
signal int_axi_full_arburst : std_logic_vector(1 downto 0);
signal int_axi_full_arlock : std_logic;
signal int_axi_full_arcache : std_logic_vector(3 downto 0);
signal int_axi_full_arprot : std_logic_vector(2 downto 0);
signal int_axi_full_arqos : std_logic_vector(3 downto 0);
signal int_axi_full_arregion : std_logic_vector(3 downto 0);
signal int_axi_full_arvalid : std_logic;
signal int_axi_full_arready : std_logic;
signal int_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal int_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_full_rresp : std_logic_vector(1 downto 0);
signal int_axi_full_rlast : std_logic;
signal int_axi_full_rvalid : std_logic;
signal int_axi_full_rready : std_logic;
signal timer_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_awlen : std_logic_vector(7 downto 0);
signal timer_axi_full_awsize : std_logic_vector(2 downto 0);
signal timer_axi_full_awburst : std_logic_vector(1 downto 0);
signal timer_axi_full_awlock : std_logic;
signal timer_axi_full_awcache : std_logic_vector(3 downto 0);
signal timer_axi_full_awprot : std_logic_vector(2 downto 0);
signal timer_axi_full_awqos : std_logic_vector(3 downto 0);
signal timer_axi_full_awregion : std_logic_vector(3 downto 0);
signal timer_axi_full_awvalid : std_logic;
signal timer_axi_full_awready : std_logic;
signal timer_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_full_wlast : std_logic;
signal timer_axi_full_wvalid : std_logic;
signal timer_axi_full_wready : std_logic;
signal timer_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_bresp : std_logic_vector(1 downto 0);
signal timer_axi_full_bvalid : std_logic;
signal timer_axi_full_bready : std_logic;
signal timer_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_axi_full_arlen : std_logic_vector(7 downto 0);
signal timer_axi_full_arsize : std_logic_vector(2 downto 0);
signal timer_axi_full_arburst : std_logic_vector(1 downto 0);
signal timer_axi_full_arlock : std_logic;
signal timer_axi_full_arcache : std_logic_vector(3 downto 0);
signal timer_axi_full_arprot : std_logic_vector(2 downto 0);
signal timer_axi_full_arqos : std_logic_vector(3 downto 0);
signal timer_axi_full_arregion : std_logic_vector(3 downto 0);
signal timer_axi_full_arvalid : std_logic;
signal timer_axi_full_arready : std_logic;
signal timer_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_full_rresp : std_logic_vector(1 downto 0);
signal timer_axi_full_rlast : std_logic;
signal timer_axi_full_rvalid : std_logic;
signal timer_axi_full_rready : std_logic;
signal gpio_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_awlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_awsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_awburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_awlock : std_logic;
signal gpio_axi_full_awcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_awqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_awregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_awvalid : std_logic;
signal gpio_axi_full_awready : std_logic;
signal gpio_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_full_wlast : std_logic;
signal gpio_axi_full_wvalid : std_logic;
signal gpio_axi_full_wready : std_logic;
signal gpio_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_bvalid : std_logic;
signal gpio_axi_full_bready : std_logic;
signal gpio_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal gpio_axi_full_arlen : std_logic_vector(7 downto 0);
signal gpio_axi_full_arsize : std_logic_vector(2 downto 0);
signal gpio_axi_full_arburst : std_logic_vector(1 downto 0);
signal gpio_axi_full_arlock : std_logic;
signal gpio_axi_full_arcache : std_logic_vector(3 downto 0);
signal gpio_axi_full_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_full_arqos : std_logic_vector(3 downto 0);
signal gpio_axi_full_arregion : std_logic_vector(3 downto 0);
signal gpio_axi_full_arvalid : std_logic;
signal gpio_axi_full_arready : std_logic;
signal gpio_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal gpio_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_full_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_full_rlast : std_logic;
signal gpio_axi_full_rvalid : std_logic;
signal gpio_axi_full_rready : std_logic;
signal cdmareg_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdmareg_axi_full_awlen : std_logic_vector(7 downto 0);
signal cdmareg_axi_full_awsize : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_awburst : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_awlock : std_logic;
signal cdmareg_axi_full_awcache : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_awprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_awqos : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_awregion : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_awvalid : std_logic;
signal cdmareg_axi_full_awready : std_logic;
signal cdmareg_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdmareg_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cdmareg_axi_full_wlast : std_logic;
signal cdmareg_axi_full_wvalid : std_logic;
signal cdmareg_axi_full_wready : std_logic;
signal cdmareg_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_bresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_bvalid : std_logic;
signal cdmareg_axi_full_bready : std_logic;
signal cdmareg_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal cdmareg_axi_full_arlen : std_logic_vector(7 downto 0);
signal cdmareg_axi_full_arsize : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_arburst : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_arlock : std_logic;
signal cdmareg_axi_full_arcache : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_arprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_full_arqos : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_arregion : std_logic_vector(3 downto 0);
signal cdmareg_axi_full_arvalid : std_logic;
signal cdmareg_axi_full_arready : std_logic;
signal cdmareg_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal cdmareg_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdmareg_axi_full_rresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_full_rlast : std_logic;
signal cdmareg_axi_full_rvalid : std_logic;
signal cdmareg_axi_full_rready : std_logic;
signal timer_extra_0_axi_full_awid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_extra_0_axi_full_awlen : std_logic_vector(7 downto 0);
signal timer_extra_0_axi_full_awsize : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_awburst : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_awlock : std_logic;
signal timer_extra_0_axi_full_awcache : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_awprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_awqos : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_awregion : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_awvalid : std_logic;
signal timer_extra_0_axi_full_awready : std_logic;
signal timer_extra_0_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_extra_0_axi_full_wlast : std_logic;
signal timer_extra_0_axi_full_wvalid : std_logic;
signal timer_extra_0_axi_full_wready : std_logic;
signal timer_extra_0_axi_full_bid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_bresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_bvalid : std_logic;
signal timer_extra_0_axi_full_bready : std_logic;
signal timer_extra_0_axi_full_arid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal timer_extra_0_axi_full_arlen : std_logic_vector(7 downto 0);
signal timer_extra_0_axi_full_arsize : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_arburst : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_arlock : std_logic;
signal timer_extra_0_axi_full_arcache : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_arprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_full_arqos : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_arregion : std_logic_vector(3 downto 0);
signal timer_extra_0_axi_full_arvalid : std_logic;
signal timer_extra_0_axi_full_arready : std_logic;
signal timer_extra_0_axi_full_rid : std_logic_vector(axi_master_id_width-1 downto 0);
signal timer_extra_0_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_full_rresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_full_rlast : std_logic;
signal timer_extra_0_axi_full_rvalid : std_logic;
signal timer_extra_0_axi_full_rready : std_logic;
signal uart_axi_full_awid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_awaddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_awlen : std_logic_vector(7 downto 0);
signal uart_axi_full_awsize : std_logic_vector(2 downto 0);
signal uart_axi_full_awburst : std_logic_vector(1 downto 0);
signal uart_axi_full_awlock : std_logic;
signal uart_axi_full_awcache : std_logic_vector(3 downto 0);
signal uart_axi_full_awprot : std_logic_vector(2 downto 0);
signal uart_axi_full_awqos : std_logic_vector(3 downto 0);
signal uart_axi_full_awregion : std_logic_vector(3 downto 0);
signal uart_axi_full_awvalid : std_logic;
signal uart_axi_full_awready : std_logic;
signal uart_axi_full_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_full_wlast : std_logic;
signal uart_axi_full_wvalid : std_logic;
signal uart_axi_full_wready : std_logic;
signal uart_axi_full_bid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_bresp : std_logic_vector(1 downto 0);
signal uart_axi_full_bvalid : std_logic;
signal uart_axi_full_bready : std_logic;
signal uart_axi_full_arid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_araddr : std_logic_vector(axi_address_width-1 downto 0);
signal uart_axi_full_arlen : std_logic_vector(7 downto 0);
signal uart_axi_full_arsize : std_logic_vector(2 downto 0);
signal uart_axi_full_arburst : std_logic_vector(1 downto 0);
signal uart_axi_full_arlock : std_logic;
signal uart_axi_full_arcache : std_logic_vector(3 downto 0);
signal uart_axi_full_arprot : std_logic_vector(2 downto 0);
signal uart_axi_full_arqos : std_logic_vector(3 downto 0);
signal uart_axi_full_arregion : std_logic_vector(3 downto 0);
signal uart_axi_full_arvalid : std_logic;
signal uart_axi_full_arready : std_logic;
signal uart_axi_full_rid : std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal uart_axi_full_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_full_rresp : std_logic_vector(1 downto 0);
signal uart_axi_full_rlast : std_logic;
signal uart_axi_full_rvalid : std_logic;
signal uart_axi_full_rready : std_logic;
signal int_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal int_axi_lite_awprot : std_logic_vector(2 downto 0);
signal int_axi_lite_awvalid : std_logic;
signal int_axi_lite_awready : std_logic;
signal int_axi_lite_wvalid : std_logic;
signal int_axi_lite_wready : std_logic;
signal int_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal int_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal int_axi_lite_bvalid : std_logic;
signal int_axi_lite_bready : std_logic;
signal int_axi_lite_bresp : std_logic_vector(1 downto 0);
signal int_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal int_axi_lite_arprot : std_logic_vector(2 downto 0);
signal int_axi_lite_arvalid : std_logic;
signal int_axi_lite_arready : std_logic;
signal int_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal int_axi_lite_rvalid : std_logic;
signal int_axi_lite_rready : std_logic;
signal int_axi_lite_rresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_axi_lite_awprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_awvalid : std_logic;
signal timer_axi_lite_awready : std_logic;
signal timer_axi_lite_wvalid : std_logic;
signal timer_axi_lite_wready : std_logic;
signal timer_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_axi_lite_bvalid : std_logic;
signal timer_axi_lite_bready : std_logic;
signal timer_axi_lite_bresp : std_logic_vector(1 downto 0);
signal timer_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_axi_lite_arprot : std_logic_vector(2 downto 0);
signal timer_axi_lite_arvalid : std_logic;
signal timer_axi_lite_arready : std_logic;
signal timer_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal timer_axi_lite_rvalid : std_logic;
signal timer_axi_lite_rready : std_logic;
signal timer_axi_lite_rresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal gpio_axi_lite_awprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_awvalid : std_logic;
signal gpio_axi_lite_awready : std_logic;
signal gpio_axi_lite_wvalid : std_logic;
signal gpio_axi_lite_wready : std_logic;
signal gpio_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal gpio_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal gpio_axi_lite_bvalid : std_logic;
signal gpio_axi_lite_bready : std_logic;
signal gpio_axi_lite_bresp : std_logic_vector(1 downto 0);
signal gpio_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal gpio_axi_lite_arprot : std_logic_vector(2 downto 0);
signal gpio_axi_lite_arvalid : std_logic;
signal gpio_axi_lite_arready : std_logic;
signal gpio_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal gpio_axi_lite_rvalid : std_logic;
signal gpio_axi_lite_rready : std_logic;
signal gpio_axi_lite_rresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal cdmareg_axi_lite_awprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_lite_awvalid : std_logic;
signal cdmareg_axi_lite_awready : std_logic;
signal cdmareg_axi_lite_wvalid : std_logic;
signal cdmareg_axi_lite_wready : std_logic;
signal cdmareg_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal cdmareg_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal cdmareg_axi_lite_bvalid : std_logic;
signal cdmareg_axi_lite_bready : std_logic;
signal cdmareg_axi_lite_bresp : std_logic_vector(1 downto 0);
signal cdmareg_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal cdmareg_axi_lite_arprot : std_logic_vector(2 downto 0);
signal cdmareg_axi_lite_arvalid : std_logic;
signal cdmareg_axi_lite_arready : std_logic;
signal cdmareg_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal cdmareg_axi_lite_rvalid : std_logic;
signal cdmareg_axi_lite_rready : std_logic;
signal cdmareg_axi_lite_rresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal uart_axi_lite_awprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_awvalid : std_logic;
signal uart_axi_lite_awready : std_logic;
signal uart_axi_lite_wvalid : std_logic;
signal uart_axi_lite_wready : std_logic;
signal uart_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal uart_axi_lite_bvalid : std_logic;
signal uart_axi_lite_bready : std_logic;
signal uart_axi_lite_bresp : std_logic_vector(1 downto 0);
signal uart_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal uart_axi_lite_arprot : std_logic_vector(2 downto 0);
signal uart_axi_lite_arvalid : std_logic;
signal uart_axi_lite_arready : std_logic;
signal uart_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal uart_axi_lite_rvalid : std_logic;
signal uart_axi_lite_rready : std_logic;
signal uart_axi_lite_rresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_lite_awaddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_extra_0_axi_lite_awprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_lite_awvalid : std_logic;
signal timer_extra_0_axi_lite_awready : std_logic;
signal timer_extra_0_axi_lite_wvalid : std_logic;
signal timer_extra_0_axi_lite_wready : std_logic;
signal timer_extra_0_axi_lite_wdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_lite_wstrb : std_logic_vector(axi_data_width/8-1 downto 0);
signal timer_extra_0_axi_lite_bvalid : std_logic;
signal timer_extra_0_axi_lite_bready : std_logic;
signal timer_extra_0_axi_lite_bresp : std_logic_vector(1 downto 0);
signal timer_extra_0_axi_lite_araddr : std_logic_vector(axi_lite_address_width-1 downto 0);
signal timer_extra_0_axi_lite_arprot : std_logic_vector(2 downto 0);
signal timer_extra_0_axi_lite_arvalid : std_logic;
signal timer_extra_0_axi_lite_arready : std_logic;
signal timer_extra_0_axi_lite_rdata : std_logic_vector(axi_data_width-1 downto 0);
signal timer_extra_0_axi_lite_rvalid : std_logic;
signal timer_extra_0_axi_lite_rready : std_logic;
signal timer_extra_0_axi_lite_rresp : std_logic_vector(1 downto 0);
signal cpu_int : std_logic;
signal int_dev_ints : std_logic_vector(default_interrupt_total-1 downto 0) := (others=>'0');
signal timer_int : std_logic;
signal gpio_int : std_logic;
signal cdma_int : std_logic;
signal uart_int : std_logic;
signal timer_extra_0_int : std_logic;
-- attribute mark_debug : boolean;
-- attribute mark_debug of cpu_axi_full_awaddr : signal is true;
-- attribute mark_debug of cpu_axi_full_awvalid : signal is true;
-- attribute mark_debug of cpu_axi_full_awready : signal is true;
-- attribute mark_debug of cpu_axi_full_wdata : signal is true;
-- attribute mark_debug of cpu_axi_full_wstrb : signal is true;
-- attribute mark_debug of cpu_axi_full_wlast : signal is true;
-- attribute mark_debug of cpu_axi_full_wvalid : signal is true;
-- attribute mark_debug of cpu_axi_full_wready : signal is true;
-- attribute mark_debug of cpu_axi_full_bresp : signal is true;
-- attribute mark_debug of cpu_axi_full_bvalid : signal is true;
-- attribute mark_debug of cpu_axi_full_bready : signal is true;
-- attribute mark_debug of cpu_axi_full_araddr : signal is true;
-- attribute mark_debug of cpu_axi_full_arvalid : signal is true;
-- attribute mark_debug of cpu_axi_full_arready : signal is true;
-- attribute mark_debug of cpu_axi_full_rdata : signal is true;
-- attribute mark_debug of cpu_axi_full_rlast : signal is true;
-- attribute mark_debug of cpu_axi_full_rvalid : signal is true;
-- attribute mark_debug of cpu_axi_full_rready : signal is true;
begin
int_dev_ints(0) <= timer_int;
int_dev_ints(1) <= gpio_int;
int_dev_ints(2) <= cdma_int;
int_dev_ints(3) <= uart_int;
int_dev_ints(4) <= timer_extra_0_int;
cdma_axi_full_awlock <= '0';
cdma_axi_full_arlock <= '0';
ram_axi_full_arlock_slv(0) <= ram_axi_full_arlock;
ram_axi_full_awlock_slv(0) <= ram_axi_full_awlock;
ram_axi_full_arid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_arid;
ram_axi_full_awid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_awid;
ram_axi_full_bid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_bid;
ram_axi_full_rid_slv(axi_master_id_width-1 downto 0) <= ram_axi_full_rid;
-- Crossbar instantiation.
plasoc_0_crossbar_wrap_inst : plasoc_0_crossbar_wrap
port map (
cpu_s_axi_awid => cpu_axi_full_awid,
cpu_s_axi_awaddr => cpu_axi_full_awaddr,
cpu_s_axi_awlen => cpu_axi_full_awlen,
cpu_s_axi_awsize => cpu_axi_full_awsize,
cpu_s_axi_awburst => cpu_axi_full_awburst,
cpu_s_axi_awlock => cpu_axi_full_awlock,
cpu_s_axi_awcache => cpu_axi_full_awcache,
cpu_s_axi_awprot => cpu_axi_full_awprot,
cpu_s_axi_awqos => cpu_axi_full_awqos,
cpu_s_axi_awregion => cpu_axi_full_awregion,
cpu_s_axi_awvalid => cpu_axi_full_awvalid,
cpu_s_axi_awready => cpu_axi_full_awready,
cpu_s_axi_wdata => cpu_axi_full_wdata,
cpu_s_axi_wstrb => cpu_axi_full_wstrb,
cpu_s_axi_wlast => cpu_axi_full_wlast,
cpu_s_axi_wvalid => cpu_axi_full_wvalid,
cpu_s_axi_wready => cpu_axi_full_wready,
cpu_s_axi_bid => cpu_axi_full_bid,
cpu_s_axi_bresp => cpu_axi_full_bresp,
cpu_s_axi_bvalid => cpu_axi_full_bvalid,
cpu_s_axi_bready => cpu_axi_full_bready,
cpu_s_axi_arid => cpu_axi_full_arid,
cpu_s_axi_araddr => cpu_axi_full_araddr,
cpu_s_axi_arlen => cpu_axi_full_arlen,
cpu_s_axi_arsize => cpu_axi_full_arsize,
cpu_s_axi_arburst => cpu_axi_full_arburst,
cpu_s_axi_arlock => cpu_axi_full_arlock,
cpu_s_axi_arcache => cpu_axi_full_arcache,
cpu_s_axi_arprot => cpu_axi_full_arprot,
cpu_s_axi_arqos => cpu_axi_full_arqos,
cpu_s_axi_arregion => cpu_axi_full_arregion,
cpu_s_axi_arvalid => cpu_axi_full_arvalid,
cpu_s_axi_arready => cpu_axi_full_arready,
cpu_s_axi_rid => cpu_axi_full_rid,
cpu_s_axi_rdata => cpu_axi_full_rdata,
cpu_s_axi_rresp => cpu_axi_full_rresp,
cpu_s_axi_rlast => cpu_axi_full_rlast,
cpu_s_axi_rvalid => cpu_axi_full_rvalid,
cpu_s_axi_rready => cpu_axi_full_rready,
cdma_s_axi_awid => cdma_axi_full_awid,
cdma_s_axi_awaddr => cdma_axi_full_awaddr,
cdma_s_axi_awlen => cdma_axi_full_awlen,
cdma_s_axi_awsize => cdma_axi_full_awsize,
cdma_s_axi_awburst => cdma_axi_full_awburst,
cdma_s_axi_awlock => cdma_axi_full_awlock,
cdma_s_axi_awcache => cdma_axi_full_awcache,
cdma_s_axi_awprot => cdma_axi_full_awprot,
cdma_s_axi_awqos => cdma_axi_full_awqos,
cdma_s_axi_awregion => cdma_axi_full_awregion,
cdma_s_axi_awvalid => cdma_axi_full_awvalid,
cdma_s_axi_awready => cdma_axi_full_awready,
cdma_s_axi_wdata => cdma_axi_full_wdata,
cdma_s_axi_wstrb => cdma_axi_full_wstrb,
cdma_s_axi_wlast => cdma_axi_full_wlast,
cdma_s_axi_wvalid => cdma_axi_full_wvalid,
cdma_s_axi_wready => cdma_axi_full_wready,
cdma_s_axi_bid => cdma_axi_full_bid,
cdma_s_axi_bresp => cdma_axi_full_bresp,
cdma_s_axi_bvalid => cdma_axi_full_bvalid,
cdma_s_axi_bready => cdma_axi_full_bready,
cdma_s_axi_arid => cdma_axi_full_arid,
cdma_s_axi_araddr => cdma_axi_full_araddr,
cdma_s_axi_arlen => cdma_axi_full_arlen,
cdma_s_axi_arsize => cdma_axi_full_arsize,
cdma_s_axi_arburst => cdma_axi_full_arburst,
cdma_s_axi_arlock => cdma_axi_full_arlock,
cdma_s_axi_arcache => cdma_axi_full_arcache,
cdma_s_axi_arprot => cdma_axi_full_arprot,
cdma_s_axi_arqos => cdma_axi_full_arqos,
cdma_s_axi_arregion => cdma_axi_full_arregion,
cdma_s_axi_arvalid => cdma_axi_full_arvalid,
cdma_s_axi_arready => cdma_axi_full_arready,
cdma_s_axi_rid => cdma_axi_full_rid,
cdma_s_axi_rdata => cdma_axi_full_rdata,
cdma_s_axi_rresp => cdma_axi_full_rresp,
cdma_s_axi_rlast => cdma_axi_full_rlast,
cdma_s_axi_rvalid => cdma_axi_full_rvalid,
cdma_s_axi_rready => cdma_axi_full_rready,
bram_m_axi_awid => bram_axi_full_awid,
bram_m_axi_awaddr => bram_axi_full_awaddr,
bram_m_axi_awlen => bram_axi_full_awlen,
bram_m_axi_awsize => bram_axi_full_awsize,
bram_m_axi_awburst => bram_axi_full_awburst,
bram_m_axi_awlock => bram_axi_full_awlock,
bram_m_axi_awcache => bram_axi_full_awcache,
bram_m_axi_awprot => bram_axi_full_awprot,
bram_m_axi_awqos => bram_axi_full_awqos,
bram_m_axi_awregion => bram_axi_full_awregion,
bram_m_axi_awvalid => bram_axi_full_awvalid,
bram_m_axi_awready => bram_axi_full_awready,
bram_m_axi_wdata => bram_axi_full_wdata,
bram_m_axi_wstrb => bram_axi_full_wstrb,
bram_m_axi_wlast => bram_axi_full_wlast,
bram_m_axi_wvalid => bram_axi_full_wvalid,
bram_m_axi_wready => bram_axi_full_wready,
bram_m_axi_bid => bram_axi_full_bid,
bram_m_axi_bresp => bram_axi_full_bresp,
bram_m_axi_bvalid => bram_axi_full_bvalid,
bram_m_axi_bready => bram_axi_full_bready,
bram_m_axi_arid => bram_axi_full_arid,
bram_m_axi_araddr => bram_axi_full_araddr,
bram_m_axi_arlen => bram_axi_full_arlen,
bram_m_axi_arsize => bram_axi_full_arsize,
bram_m_axi_arburst => bram_axi_full_arburst,
bram_m_axi_arlock => bram_axi_full_arlock,
bram_m_axi_arcache => bram_axi_full_arcache,
bram_m_axi_arprot => bram_axi_full_arprot,
bram_m_axi_arqos => bram_axi_full_arqos,
bram_m_axi_arregion => bram_axi_full_arregion,
bram_m_axi_arvalid => bram_axi_full_arvalid,
bram_m_axi_arready => bram_axi_full_arready,
bram_m_axi_rid => bram_axi_full_rid,
bram_m_axi_rdata => bram_axi_full_rdata,
bram_m_axi_rresp => bram_axi_full_rresp,
bram_m_axi_rlast => bram_axi_full_rlast,
bram_m_axi_rvalid => bram_axi_full_rvalid,
bram_m_axi_rready => bram_axi_full_rready,
ram_m_axi_awid => ram_axi_full_awid,
ram_m_axi_awaddr => ram_axi_full_awaddr,
ram_m_axi_awlen => ram_axi_full_awlen,
ram_m_axi_awsize => ram_axi_full_awsize,
ram_m_axi_awburst => ram_axi_full_awburst,
ram_m_axi_awlock => ram_axi_full_awlock,
ram_m_axi_awcache => ram_axi_full_awcache,
ram_m_axi_awprot => ram_axi_full_awprot,
ram_m_axi_awqos => ram_axi_full_awqos,
ram_m_axi_awregion => ram_axi_full_awregion,
ram_m_axi_awvalid => ram_axi_full_awvalid,
ram_m_axi_awready => ram_axi_full_awready,
ram_m_axi_wdata => ram_axi_full_wdata,
ram_m_axi_wstrb => ram_axi_full_wstrb,
ram_m_axi_wlast => ram_axi_full_wlast,
ram_m_axi_wvalid => ram_axi_full_wvalid,
ram_m_axi_wready => ram_axi_full_wready,
ram_m_axi_bid => ram_axi_full_bid,
ram_m_axi_bresp => ram_axi_full_bresp,
ram_m_axi_bvalid => ram_axi_full_bvalid,
ram_m_axi_bready => ram_axi_full_bready,
ram_m_axi_arid => ram_axi_full_arid,
ram_m_axi_araddr => ram_axi_full_araddr,
ram_m_axi_arlen => ram_axi_full_arlen,
ram_m_axi_arsize => ram_axi_full_arsize,
ram_m_axi_arburst => ram_axi_full_arburst,
ram_m_axi_arlock => ram_axi_full_arlock,
ram_m_axi_arcache => ram_axi_full_arcache,
ram_m_axi_arprot => ram_axi_full_arprot,
ram_m_axi_arqos => ram_axi_full_arqos,
ram_m_axi_arregion => ram_axi_full_arregion,
ram_m_axi_arvalid => ram_axi_full_arvalid,
ram_m_axi_arready => ram_axi_full_arready,
ram_m_axi_rid => ram_axi_full_rid,
ram_m_axi_rdata => ram_axi_full_rdata,
ram_m_axi_rresp => ram_axi_full_rresp,
ram_m_axi_rlast => ram_axi_full_rlast,
ram_m_axi_rvalid => ram_axi_full_rvalid,
ram_m_axi_rready => ram_axi_full_rready,
int_m_axi_awid => int_axi_full_awid,
int_m_axi_awaddr => int_axi_full_awaddr,
int_m_axi_awlen => int_axi_full_awlen,
int_m_axi_awsize => int_axi_full_awsize,
int_m_axi_awburst => int_axi_full_awburst,
int_m_axi_awlock => int_axi_full_awlock,
int_m_axi_awcache => int_axi_full_awcache,
int_m_axi_awprot => int_axi_full_awprot,
int_m_axi_awqos => int_axi_full_awqos,
int_m_axi_awregion => int_axi_full_awregion,
int_m_axi_awvalid => int_axi_full_awvalid,
int_m_axi_awready => int_axi_full_awready,
int_m_axi_wdata => int_axi_full_wdata,
int_m_axi_wstrb => int_axi_full_wstrb,
int_m_axi_wlast => int_axi_full_wlast,
int_m_axi_wvalid => int_axi_full_wvalid,
int_m_axi_wready => int_axi_full_wready,
int_m_axi_bid => int_axi_full_bid,
int_m_axi_bresp => int_axi_full_bresp,
int_m_axi_bvalid => int_axi_full_bvalid,
int_m_axi_bready => int_axi_full_bready,
int_m_axi_arid => int_axi_full_arid,
int_m_axi_araddr => int_axi_full_araddr,
int_m_axi_arlen => int_axi_full_arlen,
int_m_axi_arsize => int_axi_full_arsize,
int_m_axi_arburst => int_axi_full_arburst,
int_m_axi_arlock => int_axi_full_arlock,
int_m_axi_arcache => int_axi_full_arcache,
int_m_axi_arprot => int_axi_full_arprot,
int_m_axi_arqos => int_axi_full_arqos,
int_m_axi_arregion => int_axi_full_arregion,
int_m_axi_arvalid => int_axi_full_arvalid,
int_m_axi_arready => int_axi_full_arready,
int_m_axi_rid => int_axi_full_rid,
int_m_axi_rdata => int_axi_full_rdata,
int_m_axi_rresp => int_axi_full_rresp,
int_m_axi_rlast => int_axi_full_rlast,
int_m_axi_rvalid => int_axi_full_rvalid,
int_m_axi_rready => int_axi_full_rready,
timer_m_axi_awid => timer_axi_full_awid,
timer_m_axi_awaddr => timer_axi_full_awaddr,
timer_m_axi_awlen => timer_axi_full_awlen,
timer_m_axi_awsize => timer_axi_full_awsize,
timer_m_axi_awburst => timer_axi_full_awburst,
timer_m_axi_awlock => timer_axi_full_awlock,
timer_m_axi_awcache => timer_axi_full_awcache,
timer_m_axi_awprot => timer_axi_full_awprot,
timer_m_axi_awqos => timer_axi_full_awqos,
timer_m_axi_awregion => timer_axi_full_awregion,
timer_m_axi_awvalid => timer_axi_full_awvalid,
timer_m_axi_awready => timer_axi_full_awready,
timer_m_axi_wdata => timer_axi_full_wdata,
timer_m_axi_wstrb => timer_axi_full_wstrb,
timer_m_axi_wlast => timer_axi_full_wlast,
timer_m_axi_wvalid => timer_axi_full_wvalid,
timer_m_axi_wready => timer_axi_full_wready,
timer_m_axi_bid => timer_axi_full_bid,
timer_m_axi_bresp => timer_axi_full_bresp,
timer_m_axi_bvalid => timer_axi_full_bvalid,
timer_m_axi_bready => timer_axi_full_bready,
timer_m_axi_arid => timer_axi_full_arid,
timer_m_axi_araddr => timer_axi_full_araddr,
timer_m_axi_arlen => timer_axi_full_arlen,
timer_m_axi_arsize => timer_axi_full_arsize,
timer_m_axi_arburst => timer_axi_full_arburst,
timer_m_axi_arlock => timer_axi_full_arlock,
timer_m_axi_arcache => timer_axi_full_arcache,
timer_m_axi_arprot => timer_axi_full_arprot,
timer_m_axi_arqos => timer_axi_full_arqos,
timer_m_axi_arregion => timer_axi_full_arregion,
timer_m_axi_arvalid => timer_axi_full_arvalid,
timer_m_axi_arready => timer_axi_full_arready,
timer_m_axi_rid => timer_axi_full_rid,
timer_m_axi_rdata => timer_axi_full_rdata,
timer_m_axi_rresp => timer_axi_full_rresp,
timer_m_axi_rlast => timer_axi_full_rlast,
timer_m_axi_rvalid => timer_axi_full_rvalid,
timer_m_axi_rready => timer_axi_full_rready,
gpio_m_axi_awid => gpio_axi_full_awid,
gpio_m_axi_awaddr => gpio_axi_full_awaddr,
gpio_m_axi_awlen => gpio_axi_full_awlen,
gpio_m_axi_awsize => gpio_axi_full_awsize,
gpio_m_axi_awburst => gpio_axi_full_awburst,
gpio_m_axi_awlock => gpio_axi_full_awlock,
gpio_m_axi_awcache => gpio_axi_full_awcache,
gpio_m_axi_awprot => gpio_axi_full_awprot,
gpio_m_axi_awqos => gpio_axi_full_awqos,
gpio_m_axi_awregion => gpio_axi_full_awregion,
gpio_m_axi_awvalid => gpio_axi_full_awvalid,
gpio_m_axi_awready => gpio_axi_full_awready,
gpio_m_axi_wdata => gpio_axi_full_wdata,
gpio_m_axi_wstrb => gpio_axi_full_wstrb,
gpio_m_axi_wlast => gpio_axi_full_wlast,
gpio_m_axi_wvalid => gpio_axi_full_wvalid,
gpio_m_axi_wready => gpio_axi_full_wready,
gpio_m_axi_bid => gpio_axi_full_bid,
gpio_m_axi_bresp => gpio_axi_full_bresp,
gpio_m_axi_bvalid => gpio_axi_full_bvalid,
gpio_m_axi_bready => gpio_axi_full_bready,
gpio_m_axi_arid => gpio_axi_full_arid,
gpio_m_axi_araddr => gpio_axi_full_araddr,
gpio_m_axi_arlen => gpio_axi_full_arlen,
gpio_m_axi_arsize => gpio_axi_full_arsize,
gpio_m_axi_arburst => gpio_axi_full_arburst,
gpio_m_axi_arlock => gpio_axi_full_arlock,
gpio_m_axi_arcache => gpio_axi_full_arcache,
gpio_m_axi_arprot => gpio_axi_full_arprot,
gpio_m_axi_arqos => gpio_axi_full_arqos,
gpio_m_axi_arregion => gpio_axi_full_arregion,
gpio_m_axi_arvalid => gpio_axi_full_arvalid,
gpio_m_axi_arready => gpio_axi_full_arready,
gpio_m_axi_rid => gpio_axi_full_rid,
gpio_m_axi_rdata => gpio_axi_full_rdata,
gpio_m_axi_rresp => gpio_axi_full_rresp,
gpio_m_axi_rlast => gpio_axi_full_rlast,
gpio_m_axi_rvalid => gpio_axi_full_rvalid,
gpio_m_axi_rready => gpio_axi_full_rready,
cdma_m_axi_awid => cdmareg_axi_full_awid,
cdma_m_axi_awaddr => cdmareg_axi_full_awaddr,
cdma_m_axi_awlen => cdmareg_axi_full_awlen,
cdma_m_axi_awsize => cdmareg_axi_full_awsize,
cdma_m_axi_awburst => cdmareg_axi_full_awburst,
cdma_m_axi_awlock => cdmareg_axi_full_awlock,
cdma_m_axi_awcache => cdmareg_axi_full_awcache,
cdma_m_axi_awprot => cdmareg_axi_full_awprot,
cdma_m_axi_awqos => cdmareg_axi_full_awqos,
cdma_m_axi_awregion => cdmareg_axi_full_awregion,
cdma_m_axi_awvalid => cdmareg_axi_full_awvalid,
cdma_m_axi_awready => cdmareg_axi_full_awready,
cdma_m_axi_wdata => cdmareg_axi_full_wdata,
cdma_m_axi_wstrb => cdmareg_axi_full_wstrb,
cdma_m_axi_wlast => cdmareg_axi_full_wlast,
cdma_m_axi_wvalid => cdmareg_axi_full_wvalid,
cdma_m_axi_wready => cdmareg_axi_full_wready,
cdma_m_axi_bid => cdmareg_axi_full_bid,
cdma_m_axi_bresp => cdmareg_axi_full_bresp,
cdma_m_axi_bvalid => cdmareg_axi_full_bvalid,
cdma_m_axi_bready => cdmareg_axi_full_bready,
cdma_m_axi_arid => cdmareg_axi_full_arid,
cdma_m_axi_araddr => cdmareg_axi_full_araddr,
cdma_m_axi_arlen => cdmareg_axi_full_arlen,
cdma_m_axi_arsize => cdmareg_axi_full_arsize,
cdma_m_axi_arburst => cdmareg_axi_full_arburst,
cdma_m_axi_arlock => cdmareg_axi_full_arlock,
cdma_m_axi_arcache => cdmareg_axi_full_arcache,
cdma_m_axi_arprot => cdmareg_axi_full_arprot,
cdma_m_axi_arqos => cdmareg_axi_full_arqos,
cdma_m_axi_arregion => cdmareg_axi_full_arregion,
cdma_m_axi_arvalid => cdmareg_axi_full_arvalid,
cdma_m_axi_arready => cdmareg_axi_full_arready,
cdma_m_axi_rid => cdmareg_axi_full_rid,
cdma_m_axi_rdata => cdmareg_axi_full_rdata,
cdma_m_axi_rresp => cdmareg_axi_full_rresp,
cdma_m_axi_rlast => cdmareg_axi_full_rlast,
cdma_m_axi_rvalid => cdmareg_axi_full_rvalid,
cdma_m_axi_rready => cdmareg_axi_full_rready,
uart_m_axi_awid => uart_axi_full_awid,
uart_m_axi_awaddr => uart_axi_full_awaddr,
uart_m_axi_awlen => uart_axi_full_awlen,
uart_m_axi_awsize => uart_axi_full_awsize,
uart_m_axi_awburst => uart_axi_full_awburst,
uart_m_axi_awlock => uart_axi_full_awlock,
uart_m_axi_awcache => uart_axi_full_awcache,
uart_m_axi_awprot => uart_axi_full_awprot,
uart_m_axi_awqos => uart_axi_full_awqos,
uart_m_axi_awregion => uart_axi_full_awregion,
uart_m_axi_awvalid => uart_axi_full_awvalid,
uart_m_axi_awready => uart_axi_full_awready,
uart_m_axi_wdata => uart_axi_full_wdata,
uart_m_axi_wstrb => uart_axi_full_wstrb,
uart_m_axi_wlast => uart_axi_full_wlast,
uart_m_axi_wvalid => uart_axi_full_wvalid,
uart_m_axi_wready => uart_axi_full_wready,
uart_m_axi_bid => uart_axi_full_bid,
uart_m_axi_bresp => uart_axi_full_bresp,
uart_m_axi_bvalid => uart_axi_full_bvalid,
uart_m_axi_bready => uart_axi_full_bready,
uart_m_axi_arid => uart_axi_full_arid,
uart_m_axi_araddr => uart_axi_full_araddr,
uart_m_axi_arlen => uart_axi_full_arlen,
uart_m_axi_arsize => uart_axi_full_arsize,
uart_m_axi_arburst => uart_axi_full_arburst,
uart_m_axi_arlock => uart_axi_full_arlock,
uart_m_axi_arcache => uart_axi_full_arcache,
uart_m_axi_arprot => uart_axi_full_arprot,
uart_m_axi_arqos => uart_axi_full_arqos,
uart_m_axi_arregion => uart_axi_full_arregion,
uart_m_axi_arvalid => uart_axi_full_arvalid,
uart_m_axi_arready => uart_axi_full_arready,
uart_m_axi_rid => uart_axi_full_rid,
uart_m_axi_rdata => uart_axi_full_rdata,
uart_m_axi_rresp => uart_axi_full_rresp,
uart_m_axi_rlast => uart_axi_full_rlast,
uart_m_axi_rvalid => uart_axi_full_rvalid,
uart_m_axi_rready => uart_axi_full_rready,
timer_extra_0_m_axi_awid => timer_extra_0_axi_full_awid,
timer_extra_0_m_axi_awaddr => timer_extra_0_axi_full_awaddr,
timer_extra_0_m_axi_awlen => timer_extra_0_axi_full_awlen,
timer_extra_0_m_axi_awsize => timer_extra_0_axi_full_awsize,
timer_extra_0_m_axi_awburst => timer_extra_0_axi_full_awburst,
timer_extra_0_m_axi_awlock => timer_extra_0_axi_full_awlock,
timer_extra_0_m_axi_awcache => timer_extra_0_axi_full_awcache,
timer_extra_0_m_axi_awprot => timer_extra_0_axi_full_awprot,
timer_extra_0_m_axi_awqos => timer_extra_0_axi_full_awqos,
timer_extra_0_m_axi_awregion => timer_extra_0_axi_full_awregion,
timer_extra_0_m_axi_awvalid => timer_extra_0_axi_full_awvalid,
timer_extra_0_m_axi_awready => timer_extra_0_axi_full_awready,
timer_extra_0_m_axi_wdata => timer_extra_0_axi_full_wdata,
timer_extra_0_m_axi_wstrb => timer_extra_0_axi_full_wstrb,
timer_extra_0_m_axi_wlast => timer_extra_0_axi_full_wlast,
timer_extra_0_m_axi_wvalid => timer_extra_0_axi_full_wvalid,
timer_extra_0_m_axi_wready => timer_extra_0_axi_full_wready,
timer_extra_0_m_axi_bid => timer_extra_0_axi_full_bid,
timer_extra_0_m_axi_bresp => timer_extra_0_axi_full_bresp,
timer_extra_0_m_axi_bvalid => timer_extra_0_axi_full_bvalid,
timer_extra_0_m_axi_bready => timer_extra_0_axi_full_bready,
timer_extra_0_m_axi_arid => timer_extra_0_axi_full_arid,
timer_extra_0_m_axi_araddr => timer_extra_0_axi_full_araddr,
timer_extra_0_m_axi_arlen => timer_extra_0_axi_full_arlen,
timer_extra_0_m_axi_arsize => timer_extra_0_axi_full_arsize,
timer_extra_0_m_axi_arburst => timer_extra_0_axi_full_arburst,
timer_extra_0_m_axi_arlock => timer_extra_0_axi_full_arlock,
timer_extra_0_m_axi_arcache => timer_extra_0_axi_full_arcache,
timer_extra_0_m_axi_arprot => timer_extra_0_axi_full_arprot,
timer_extra_0_m_axi_arqos => timer_extra_0_axi_full_arqos,
timer_extra_0_m_axi_arregion => timer_extra_0_axi_full_arregion,
timer_extra_0_m_axi_arvalid => timer_extra_0_axi_full_arvalid,
timer_extra_0_m_axi_arready => timer_extra_0_axi_full_arready,
timer_extra_0_m_axi_rid => timer_extra_0_axi_full_rid,
timer_extra_0_m_axi_rdata => timer_extra_0_axi_full_rdata,
timer_extra_0_m_axi_rresp => timer_extra_0_axi_full_rresp,
timer_extra_0_m_axi_rlast => timer_extra_0_axi_full_rlast,
timer_extra_0_m_axi_rvalid => timer_extra_0_axi_full_rvalid,
timer_extra_0_m_axi_rready => timer_extra_0_axi_full_rready,
aclk => aclk,
aresetn => cross_aresetn(0));
plasoc_cpu_inst : plasoc_cpu
port map (
aclk => aclk,
aresetn => aresetn(0),
intr_in => cpu_int,
axi_awid => cpu_axi_full_awid,
axi_awaddr => cpu_axi_full_awaddr,
axi_awlen => cpu_axi_full_awlen,
axi_awsize => cpu_axi_full_awsize,
axi_awburst => cpu_axi_full_awburst,
axi_awlock => cpu_axi_full_awlock,
axi_awcache => cpu_axi_full_awcache,
axi_awprot => cpu_axi_full_awprot,
axi_awqos => cpu_axi_full_awqos,
axi_awregion => cpu_axi_full_awregion,
axi_awvalid => cpu_axi_full_awvalid,
axi_awready => cpu_axi_full_awready,
axi_wdata => cpu_axi_full_wdata,
axi_wstrb => cpu_axi_full_wstrb,
axi_wlast => cpu_axi_full_wlast,
axi_wvalid => cpu_axi_full_wvalid,
axi_wready => cpu_axi_full_wready,
axi_bid => cpu_axi_full_bid,
axi_bresp => cpu_axi_full_bresp,
axi_bvalid => cpu_axi_full_bvalid,
axi_bready => cpu_axi_full_bready,
axi_arid => cpu_axi_full_arid,
axi_araddr => cpu_axi_full_araddr,
axi_arlen => cpu_axi_full_arlen,
axi_arsize => cpu_axi_full_arsize,
axi_arburst => cpu_axi_full_arburst,
axi_arlock => cpu_axi_full_arlock,
axi_arcache => cpu_axi_full_arcache,
axi_arprot => cpu_axi_full_arprot,
axi_arqos => cpu_axi_full_arqos,
axi_arregion => cpu_axi_full_arregion,
axi_arvalid => cpu_axi_full_arvalid,
axi_arready => cpu_axi_full_arready,
axi_rid => cpu_axi_full_rid,
axi_rdata => cpu_axi_full_rdata,
axi_rresp => cpu_axi_full_rresp,
axi_rlast => cpu_axi_full_rlast,
axi_rvalid => cpu_axi_full_rvalid,
axi_rready => cpu_axi_full_rready);
int_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => int_axi_full_awid,
s_axi_awaddr => int_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => int_axi_full_awlen,
s_axi_awsize => int_axi_full_awsize,
s_axi_awburst => int_axi_full_awburst,
s_axi_awlock => int_axi_full_awlock,
s_axi_awcache => int_axi_full_awcache,
s_axi_awprot => int_axi_full_awprot,
s_axi_awqos => int_axi_full_awqos,
s_axi_awregion => int_axi_full_awregion,
s_axi_awvalid => int_axi_full_awvalid,
s_axi_awready => int_axi_full_awready,
s_axi_wdata => int_axi_full_wdata,
s_axi_wstrb => int_axi_full_wstrb,
s_axi_wlast => int_axi_full_wlast,
s_axi_wvalid => int_axi_full_wvalid,
s_axi_wready => int_axi_full_wready,
s_axi_bid => int_axi_full_bid,
s_axi_bresp => int_axi_full_bresp,
s_axi_bvalid => int_axi_full_bvalid,
s_axi_bready => int_axi_full_bready,
s_axi_arid => int_axi_full_arid,
s_axi_araddr => int_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => int_axi_full_arlen,
s_axi_arsize => int_axi_full_arsize,
s_axi_arburst => int_axi_full_arburst,
s_axi_arlock => int_axi_full_arlock,
s_axi_arcache => int_axi_full_arcache,
s_axi_arprot => int_axi_full_arprot,
s_axi_arqos => int_axi_full_arqos,
s_axi_arregion => int_axi_full_arregion,
s_axi_arvalid => int_axi_full_arvalid,
s_axi_arready => int_axi_full_arready,
s_axi_rid => int_axi_full_rid,
s_axi_rdata => int_axi_full_rdata,
s_axi_rresp => int_axi_full_rresp,
s_axi_rlast => int_axi_full_rlast,
s_axi_rvalid => int_axi_full_rvalid,
s_axi_rready => int_axi_full_rready,
m_axi_awaddr => int_axi_lite_awaddr,
m_axi_awprot => int_axi_lite_awprot,
m_axi_awvalid => int_axi_lite_awvalid,
m_axi_awready => int_axi_lite_awready,
m_axi_wvalid => int_axi_lite_wvalid,
m_axi_wready => int_axi_lite_wready,
m_axi_wdata => int_axi_lite_wdata,
m_axi_wstrb => int_axi_lite_wstrb,
m_axi_bvalid => int_axi_lite_bvalid,
m_axi_bready => int_axi_lite_bready,
m_axi_bresp => int_axi_lite_bresp,
m_axi_araddr => int_axi_lite_araddr,
m_axi_arprot => int_axi_lite_arprot,
m_axi_arvalid => int_axi_lite_arvalid,
m_axi_arready => int_axi_lite_arready,
m_axi_rdata => int_axi_lite_rdata,
m_axi_rvalid => int_axi_lite_rvalid,
m_axi_rready => int_axi_lite_rready,
m_axi_rresp => int_axi_lite_rresp);
timer_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => timer_axi_full_awid,
s_axi_awaddr => timer_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => timer_axi_full_awlen,
s_axi_awsize => timer_axi_full_awsize,
s_axi_awburst => timer_axi_full_awburst,
s_axi_awlock => timer_axi_full_awlock,
s_axi_awcache => timer_axi_full_awcache,
s_axi_awprot => timer_axi_full_awprot,
s_axi_awqos => timer_axi_full_awqos,
s_axi_awregion => timer_axi_full_awregion,
s_axi_awvalid => timer_axi_full_awvalid,
s_axi_awready => timer_axi_full_awready,
s_axi_wdata => timer_axi_full_wdata,
s_axi_wstrb => timer_axi_full_wstrb,
s_axi_wlast => timer_axi_full_wlast,
s_axi_wvalid => timer_axi_full_wvalid,
s_axi_wready => timer_axi_full_wready,
s_axi_bid => timer_axi_full_bid,
s_axi_bresp => timer_axi_full_bresp,
s_axi_bvalid => timer_axi_full_bvalid,
s_axi_bready => timer_axi_full_bready,
s_axi_arid => timer_axi_full_arid,
s_axi_araddr => timer_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => timer_axi_full_arlen,
s_axi_arsize => timer_axi_full_arsize,
s_axi_arburst => timer_axi_full_arburst,
s_axi_arlock => timer_axi_full_arlock,
s_axi_arcache => timer_axi_full_arcache,
s_axi_arprot => timer_axi_full_arprot,
s_axi_arqos => timer_axi_full_arqos,
s_axi_arregion => timer_axi_full_arregion,
s_axi_arvalid => timer_axi_full_arvalid,
s_axi_arready => timer_axi_full_arready,
s_axi_rid => timer_axi_full_rid,
s_axi_rdata => timer_axi_full_rdata,
s_axi_rresp => timer_axi_full_rresp,
s_axi_rlast => timer_axi_full_rlast,
s_axi_rvalid => timer_axi_full_rvalid,
s_axi_rready => timer_axi_full_rready,
m_axi_awaddr => timer_axi_lite_awaddr,
m_axi_awprot => timer_axi_lite_awprot,
m_axi_awvalid => timer_axi_lite_awvalid,
m_axi_awready => timer_axi_lite_awready,
m_axi_wvalid => timer_axi_lite_wvalid,
m_axi_wready => timer_axi_lite_wready,
m_axi_wdata => timer_axi_lite_wdata,
m_axi_wstrb => timer_axi_lite_wstrb,
m_axi_bvalid => timer_axi_lite_bvalid,
m_axi_bready => timer_axi_lite_bready,
m_axi_bresp => timer_axi_lite_bresp,
m_axi_araddr => timer_axi_lite_araddr,
m_axi_arprot => timer_axi_lite_arprot,
m_axi_arvalid => timer_axi_lite_arvalid,
m_axi_arready => timer_axi_lite_arready,
m_axi_rdata => timer_axi_lite_rdata,
m_axi_rvalid => timer_axi_lite_rvalid,
m_axi_rready => timer_axi_lite_rready,
m_axi_rresp => timer_axi_lite_rresp);
gpio_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => gpio_axi_full_awid,
s_axi_awaddr => gpio_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => gpio_axi_full_awlen,
s_axi_awsize => gpio_axi_full_awsize,
s_axi_awburst => gpio_axi_full_awburst,
s_axi_awlock => gpio_axi_full_awlock,
s_axi_awcache => gpio_axi_full_awcache,
s_axi_awprot => gpio_axi_full_awprot,
s_axi_awqos => gpio_axi_full_awqos,
s_axi_awregion => gpio_axi_full_awregion,
s_axi_awvalid => gpio_axi_full_awvalid,
s_axi_awready => gpio_axi_full_awready,
s_axi_wdata => gpio_axi_full_wdata,
s_axi_wstrb => gpio_axi_full_wstrb,
s_axi_wlast => gpio_axi_full_wlast,
s_axi_wvalid => gpio_axi_full_wvalid,
s_axi_wready => gpio_axi_full_wready,
s_axi_bid => gpio_axi_full_bid,
s_axi_bresp => gpio_axi_full_bresp,
s_axi_bvalid => gpio_axi_full_bvalid,
s_axi_bready => gpio_axi_full_bready,
s_axi_arid => gpio_axi_full_arid,
s_axi_araddr => gpio_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => gpio_axi_full_arlen,
s_axi_arsize => gpio_axi_full_arsize,
s_axi_arburst => gpio_axi_full_arburst,
s_axi_arlock => gpio_axi_full_arlock,
s_axi_arcache => gpio_axi_full_arcache,
s_axi_arprot => gpio_axi_full_arprot,
s_axi_arqos => gpio_axi_full_arqos,
s_axi_arregion => gpio_axi_full_arregion,
s_axi_arvalid => gpio_axi_full_arvalid,
s_axi_arready => gpio_axi_full_arready,
s_axi_rid => gpio_axi_full_rid,
s_axi_rdata => gpio_axi_full_rdata,
s_axi_rresp => gpio_axi_full_rresp,
s_axi_rlast => gpio_axi_full_rlast,
s_axi_rvalid => gpio_axi_full_rvalid,
s_axi_rready => gpio_axi_full_rready,
m_axi_awaddr => gpio_axi_lite_awaddr,
m_axi_awprot => gpio_axi_lite_awprot,
m_axi_awvalid => gpio_axi_lite_awvalid,
m_axi_awready => gpio_axi_lite_awready,
m_axi_wvalid => gpio_axi_lite_wvalid,
m_axi_wready => gpio_axi_lite_wready,
m_axi_wdata => gpio_axi_lite_wdata,
m_axi_wstrb => gpio_axi_lite_wstrb,
m_axi_bvalid => gpio_axi_lite_bvalid,
m_axi_bready => gpio_axi_lite_bready,
m_axi_bresp => gpio_axi_lite_bresp,
m_axi_araddr => gpio_axi_lite_araddr,
m_axi_arprot => gpio_axi_lite_arprot,
m_axi_arvalid => gpio_axi_lite_arvalid,
m_axi_arready => gpio_axi_lite_arready,
m_axi_rdata => gpio_axi_lite_rdata,
m_axi_rvalid => gpio_axi_lite_rvalid,
m_axi_rready => gpio_axi_lite_rready,
m_axi_rresp => gpio_axi_lite_rresp);
cdmareg_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => cdmareg_axi_full_awid,
s_axi_awaddr => cdmareg_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => cdmareg_axi_full_awlen,
s_axi_awsize => cdmareg_axi_full_awsize,
s_axi_awburst => cdmareg_axi_full_awburst,
s_axi_awlock => cdmareg_axi_full_awlock,
s_axi_awcache => cdmareg_axi_full_awcache,
s_axi_awprot => cdmareg_axi_full_awprot,
s_axi_awqos => cdmareg_axi_full_awqos,
s_axi_awregion => cdmareg_axi_full_awregion,
s_axi_awvalid => cdmareg_axi_full_awvalid,
s_axi_awready => cdmareg_axi_full_awready,
s_axi_wdata => cdmareg_axi_full_wdata,
s_axi_wstrb => cdmareg_axi_full_wstrb,
s_axi_wlast => cdmareg_axi_full_wlast,
s_axi_wvalid => cdmareg_axi_full_wvalid,
s_axi_wready => cdmareg_axi_full_wready,
s_axi_bid => cdmareg_axi_full_bid,
s_axi_bresp => cdmareg_axi_full_bresp,
s_axi_bvalid => cdmareg_axi_full_bvalid,
s_axi_bready => cdmareg_axi_full_bready,
s_axi_arid => cdmareg_axi_full_arid,
s_axi_araddr => cdmareg_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => cdmareg_axi_full_arlen,
s_axi_arsize => cdmareg_axi_full_arsize,
s_axi_arburst => cdmareg_axi_full_arburst,
s_axi_arlock => cdmareg_axi_full_arlock,
s_axi_arcache => cdmareg_axi_full_arcache,
s_axi_arprot => cdmareg_axi_full_arprot,
s_axi_arqos => cdmareg_axi_full_arqos,
s_axi_arregion => cdmareg_axi_full_arregion,
s_axi_arvalid => cdmareg_axi_full_arvalid,
s_axi_arready => cdmareg_axi_full_arready,
s_axi_rid => cdmareg_axi_full_rid,
s_axi_rdata => cdmareg_axi_full_rdata,
s_axi_rresp => cdmareg_axi_full_rresp,
s_axi_rlast => cdmareg_axi_full_rlast,
s_axi_rvalid => cdmareg_axi_full_rvalid,
s_axi_rready => cdmareg_axi_full_rready,
m_axi_awaddr => cdmareg_axi_lite_awaddr,
m_axi_awprot => cdmareg_axi_lite_awprot,
m_axi_awvalid => cdmareg_axi_lite_awvalid,
m_axi_awready => cdmareg_axi_lite_awready,
m_axi_wvalid => cdmareg_axi_lite_wvalid,
m_axi_wready => cdmareg_axi_lite_wready,
m_axi_wdata => cdmareg_axi_lite_wdata,
m_axi_wstrb => cdmareg_axi_lite_wstrb,
m_axi_bvalid => cdmareg_axi_lite_bvalid,
m_axi_bready => cdmareg_axi_lite_bready,
m_axi_bresp => cdmareg_axi_lite_bresp,
m_axi_araddr => cdmareg_axi_lite_araddr,
m_axi_arprot => cdmareg_axi_lite_arprot,
m_axi_arvalid => cdmareg_axi_lite_arvalid,
m_axi_arready => cdmareg_axi_lite_arready,
m_axi_rdata => cdmareg_axi_lite_rdata,
m_axi_rvalid => cdmareg_axi_lite_rvalid,
m_axi_rready => cdmareg_axi_lite_rready,
m_axi_rresp => cdmareg_axi_lite_rresp);
uart_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => uart_axi_full_awid,
s_axi_awaddr => uart_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => uart_axi_full_awlen,
s_axi_awsize => uart_axi_full_awsize,
s_axi_awburst => uart_axi_full_awburst,
s_axi_awlock => uart_axi_full_awlock,
s_axi_awcache => uart_axi_full_awcache,
s_axi_awprot => uart_axi_full_awprot,
s_axi_awqos => uart_axi_full_awqos,
s_axi_awregion => uart_axi_full_awregion,
s_axi_awvalid => uart_axi_full_awvalid,
s_axi_awready => uart_axi_full_awready,
s_axi_wdata => uart_axi_full_wdata,
s_axi_wstrb => uart_axi_full_wstrb,
s_axi_wlast => uart_axi_full_wlast,
s_axi_wvalid => uart_axi_full_wvalid,
s_axi_wready => uart_axi_full_wready,
s_axi_bid => uart_axi_full_bid,
s_axi_bresp => uart_axi_full_bresp,
s_axi_bvalid => uart_axi_full_bvalid,
s_axi_bready => uart_axi_full_bready,
s_axi_arid => uart_axi_full_arid,
s_axi_araddr => uart_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => uart_axi_full_arlen,
s_axi_arsize => uart_axi_full_arsize,
s_axi_arburst => uart_axi_full_arburst,
s_axi_arlock => uart_axi_full_arlock,
s_axi_arcache => uart_axi_full_arcache,
s_axi_arprot => uart_axi_full_arprot,
s_axi_arqos => uart_axi_full_arqos,
s_axi_arregion => uart_axi_full_arregion,
s_axi_arvalid => uart_axi_full_arvalid,
s_axi_arready => uart_axi_full_arready,
s_axi_rid => uart_axi_full_rid,
s_axi_rdata => uart_axi_full_rdata,
s_axi_rresp => uart_axi_full_rresp,
s_axi_rlast => uart_axi_full_rlast,
s_axi_rvalid => uart_axi_full_rvalid,
s_axi_rready => uart_axi_full_rready,
m_axi_awaddr => uart_axi_lite_awaddr,
m_axi_awprot => uart_axi_lite_awprot,
m_axi_awvalid => uart_axi_lite_awvalid,
m_axi_awready => uart_axi_lite_awready,
m_axi_wvalid => uart_axi_lite_wvalid,
m_axi_wready => uart_axi_lite_wready,
m_axi_wdata => uart_axi_lite_wdata,
m_axi_wstrb => uart_axi_lite_wstrb,
m_axi_bvalid => uart_axi_lite_bvalid,
m_axi_bready => uart_axi_lite_bready,
m_axi_bresp => uart_axi_lite_bresp,
m_axi_araddr => uart_axi_lite_araddr,
m_axi_arprot => uart_axi_lite_arprot,
m_axi_arvalid => uart_axi_lite_arvalid,
m_axi_arready => uart_axi_lite_arready,
m_axi_rdata => uart_axi_lite_rdata,
m_axi_rvalid => uart_axi_lite_rvalid,
m_axi_rready => uart_axi_lite_rready,
m_axi_rresp => uart_axi_lite_rresp);
timer_extra_0_full2lite_inst : plasoc_axi4_full2lite
generic map (
axi_slave_id_width => axi_master_id_width,
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
s_axi_awid => timer_extra_0_axi_full_awid,
s_axi_awaddr => timer_extra_0_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => timer_extra_0_axi_full_awlen,
s_axi_awsize => timer_extra_0_axi_full_awsize,
s_axi_awburst => timer_extra_0_axi_full_awburst,
s_axi_awlock => timer_extra_0_axi_full_awlock,
s_axi_awcache => timer_extra_0_axi_full_awcache,
s_axi_awprot => timer_extra_0_axi_full_awprot,
s_axi_awqos => timer_extra_0_axi_full_awqos,
s_axi_awregion => timer_extra_0_axi_full_awregion,
s_axi_awvalid => timer_extra_0_axi_full_awvalid,
s_axi_awready => timer_extra_0_axi_full_awready,
s_axi_wdata => timer_extra_0_axi_full_wdata,
s_axi_wstrb => timer_extra_0_axi_full_wstrb,
s_axi_wlast => timer_extra_0_axi_full_wlast,
s_axi_wvalid => timer_extra_0_axi_full_wvalid,
s_axi_wready => timer_extra_0_axi_full_wready,
s_axi_bid => timer_extra_0_axi_full_bid,
s_axi_bresp => timer_extra_0_axi_full_bresp,
s_axi_bvalid => timer_extra_0_axi_full_bvalid,
s_axi_bready => timer_extra_0_axi_full_bready,
s_axi_arid => timer_extra_0_axi_full_arid,
s_axi_araddr => timer_extra_0_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => timer_extra_0_axi_full_arlen,
s_axi_arsize => timer_extra_0_axi_full_arsize,
s_axi_arburst => timer_extra_0_axi_full_arburst,
s_axi_arlock => timer_extra_0_axi_full_arlock,
s_axi_arcache => timer_extra_0_axi_full_arcache,
s_axi_arprot => timer_extra_0_axi_full_arprot,
s_axi_arqos => timer_extra_0_axi_full_arqos,
s_axi_arregion => timer_extra_0_axi_full_arregion,
s_axi_arvalid => timer_extra_0_axi_full_arvalid,
s_axi_arready => timer_extra_0_axi_full_arready,
s_axi_rid => timer_extra_0_axi_full_rid,
s_axi_rdata => timer_extra_0_axi_full_rdata,
s_axi_rresp => timer_extra_0_axi_full_rresp,
s_axi_rlast => timer_extra_0_axi_full_rlast,
s_axi_rvalid => timer_extra_0_axi_full_rvalid,
s_axi_rready => timer_extra_0_axi_full_rready,
m_axi_awaddr => timer_extra_0_axi_lite_awaddr,
m_axi_awprot => timer_extra_0_axi_lite_awprot,
m_axi_awvalid => timer_extra_0_axi_lite_awvalid,
m_axi_awready => timer_extra_0_axi_lite_awready,
m_axi_wvalid => timer_extra_0_axi_lite_wvalid,
m_axi_wready => timer_extra_0_axi_lite_wready,
m_axi_wdata => timer_extra_0_axi_lite_wdata,
m_axi_wstrb => timer_extra_0_axi_lite_wstrb,
m_axi_bvalid => timer_extra_0_axi_lite_bvalid,
m_axi_bready => timer_extra_0_axi_lite_bready,
m_axi_bresp => timer_extra_0_axi_lite_bresp,
m_axi_araddr => timer_extra_0_axi_lite_araddr,
m_axi_arprot => timer_extra_0_axi_lite_arprot,
m_axi_arvalid => timer_extra_0_axi_lite_arvalid,
m_axi_arready => timer_extra_0_axi_lite_arready,
m_axi_rdata => timer_extra_0_axi_lite_rdata,
m_axi_rvalid => timer_extra_0_axi_lite_rvalid,
m_axi_rready => timer_extra_0_axi_lite_rready,
m_axi_rresp => timer_extra_0_axi_lite_rresp);
bram_cntrl_inst : axi_bram_ctrl_0
port map (
s_axi_aclk => aclk,
s_axi_aresetn => aresetn(0),
s_axi_awid => bram_axi_full_awid,
s_axi_awaddr => bram_axi_full_awaddr(axi_lite_address_width-1 downto 0),
s_axi_awlen => bram_axi_full_awlen,
s_axi_awsize => bram_axi_full_awsize,
s_axi_awburst => bram_axi_full_awburst,
s_axi_awlock => bram_axi_full_awlock,
s_axi_awcache => bram_axi_full_awcache,
s_axi_awprot => bram_axi_full_awprot,
s_axi_awvalid => bram_axi_full_awvalid,
s_axi_awready => bram_axi_full_awready,
s_axi_wdata => bram_axi_full_wdata,
s_axi_wstrb => bram_axi_full_wstrb,
s_axi_wlast => bram_axi_full_wlast,
s_axi_wvalid => bram_axi_full_wvalid,
s_axi_wready => bram_axi_full_wready,
s_axi_bid => bram_axi_full_bid,
s_axi_bresp => bram_axi_full_bresp,
s_axi_bvalid => bram_axi_full_bvalid,
s_axi_bready => bram_axi_full_bready,
s_axi_arid => bram_axi_full_arid,
s_axi_araddr => bram_axi_full_araddr(axi_lite_address_width-1 downto 0),
s_axi_arlen => bram_axi_full_arlen,
s_axi_arsize => bram_axi_full_arsize,
s_axi_arburst => bram_axi_full_arburst,
s_axi_arlock => bram_axi_full_arlock,
s_axi_arcache => bram_axi_full_arcache,
s_axi_arprot => bram_axi_full_arprot,
s_axi_arvalid => bram_axi_full_arvalid,
s_axi_arready => bram_axi_full_arready,
s_axi_rid => bram_axi_full_rid,
s_axi_rdata => bram_axi_full_rdata,
s_axi_rresp => bram_axi_full_rresp,
s_axi_rlast => bram_axi_full_rlast,
s_axi_rvalid => bram_axi_full_rvalid,
s_axi_rready => bram_axi_full_rready,
bram_rst_a => bram_bram_rst_a,
bram_clk_a => bram_bram_clk_a,
bram_en_a => bram_bram_en_a,
bram_we_a => bram_bram_we_a,
bram_addr_a => bram_bram_addr_a,
bram_wrdata_a => bram_bram_wrdata_a,
bram_rddata_a => bram_bram_rddata_a);
bram_inst : bram
generic map (
select_app => lower_app,
address_width => axi_lite_address_width,
data_width => axi_data_width,
bram_depth => 1024 )
port map (
bram_rst_a => bram_bram_rst_a,
bram_clk_a => bram_bram_clk_a,
bram_en_a => bram_bram_en_a,
bram_we_a => bram_bram_we_a,
bram_addr_a => bram_bram_addr_a,
bram_wrdata_a => bram_bram_wrdata_a,
bram_rddata_a => bram_bram_rddata_a);
gen_int_mm :
if upper_ext=false generate
ram_cntrl_inst : axi_bram_ctrl_1
port map (
s_axi_aclk => aclk,
s_axi_aresetn => aresetn(0),
s_axi_awid => ram_axi_full_awid,
s_axi_awaddr => ram_axi_full_awaddr(axi_ram_address_width-1 downto 0),
s_axi_awlen => ram_axi_full_awlen,
s_axi_awsize => ram_axi_full_awsize,
s_axi_awburst => ram_axi_full_awburst,
s_axi_awlock => ram_axi_full_awlock,
s_axi_awcache => ram_axi_full_awcache,
s_axi_awprot => ram_axi_full_awprot,
s_axi_awvalid => ram_axi_full_awvalid,
s_axi_awready => ram_axi_full_awready,
s_axi_wdata => ram_axi_full_wdata,
s_axi_wstrb => ram_axi_full_wstrb,
s_axi_wlast => ram_axi_full_wlast,
s_axi_wvalid => ram_axi_full_wvalid,
s_axi_wready => ram_axi_full_wready,
s_axi_bid => ram_axi_full_bid,
s_axi_bresp => ram_axi_full_bresp,
s_axi_bvalid => ram_axi_full_bvalid,
s_axi_bready => ram_axi_full_bready,
s_axi_arid => ram_axi_full_arid,
s_axi_araddr => ram_axi_full_araddr(axi_ram_address_width-1 downto 0),
s_axi_arlen => ram_axi_full_arlen,
s_axi_arsize => ram_axi_full_arsize,
s_axi_arburst => ram_axi_full_arburst,
s_axi_arlock => ram_axi_full_arlock,
s_axi_arcache => ram_axi_full_arcache,
s_axi_arprot => ram_axi_full_arprot,
s_axi_arvalid => ram_axi_full_arvalid,
s_axi_arready => ram_axi_full_arready,
s_axi_rid => ram_axi_full_rid,
s_axi_rdata => ram_axi_full_rdata,
s_axi_rresp => ram_axi_full_rresp,
s_axi_rlast => ram_axi_full_rlast,
s_axi_rvalid => ram_axi_full_rvalid,
s_axi_rready => ram_axi_full_rready,
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
ram_inst : bram
generic map (
select_app => upper_app,
address_width => axi_ram_address_width,
data_width => axi_data_width,
bram_depth => axi_ram_depth)
port map (
bram_rst_a => ram_bram_rst_a,
bram_clk_a => ram_bram_clk_a,
bram_en_a => ram_bram_en_a,
bram_we_a => ram_bram_we_a,
bram_addr_a => ram_bram_addr_a,
bram_wrdata_a => ram_bram_wrdata_a,
bram_rddata_a => ram_bram_rddata_a);
clk_wiz_0_inst : clk_wiz_0
port map (
aclk => aclk,
sys_rst => sys_rst,
locked => dcm_locked,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n);
proc_sys_reset_0_inst : proc_sys_reset_0
port map (
slowest_sync_clk => aclk,
ext_reset_in => sys_rst,
aux_reset_in => '0',
mb_debug_sys_rst => '0',
dcm_locked => dcm_locked,
mb_reset => open,
bus_struct_reset => open,
peripheral_reset => open,
interconnect_aresetn => cross_aresetn,
peripheral_aresetn => aresetn);
end generate;
gen_ext_mm :
if upper_ext=true generate
mig_wrap_wrapper_inst :
mig_wrap_wrapper
port map (
DDR3_addr => DDR3_addr,
DDR3_ba => DDR3_ba,
DDR3_cas_n => DDR3_cas_n,
DDR3_ck_n => DDR3_ck_n,
DDR3_ck_p => DDR3_ck_p,
DDR3_cke => DDR3_cke,
DDR3_cs_n => DDR3_cs_n,
DDR3_dm => DDR3_dm,
DDR3_dq => DDR3_dq,
DDR3_dqs_n => DDR3_dqs_n,
DDR3_dqs_p => DDR3_dqs_p,
DDR3_odt => DDR3_odt,
DDR3_ras_n => DDR3_ras_n,
DDR3_reset_n => DDR3_reset_n,
DDR3_we_n => DDR3_we_n,
S00_AXI_araddr => ram_axi_full_araddr,
S00_AXI_arburst => ram_axi_full_arburst,
S00_AXI_arcache => ram_axi_full_arcache,
S00_AXI_arid => ram_axi_full_arid_slv,
S00_AXI_arlen => ram_axi_full_arlen,
S00_AXI_arlock => ram_axi_full_arlock_slv,
S00_AXI_arprot => ram_axi_full_arprot,
S00_AXI_arqos => ram_axi_full_arqos,
S00_AXI_arready => ram_axi_full_arready,
S00_AXI_arregion => ram_axi_full_arregion,
S00_AXI_arsize => ram_axi_full_arsize,
S00_AXI_arvalid => ram_axi_full_arvalid,
S00_AXI_awaddr => ram_axi_full_awaddr,
S00_AXI_awburst => ram_axi_full_awburst,
S00_AXI_awcache => ram_axi_full_awcache,
S00_AXI_awid => ram_axi_full_awid_slv,
S00_AXI_awlen => ram_axi_full_awlen,
S00_AXI_awlock => ram_axi_full_awlock_slv,
S00_AXI_awprot => ram_axi_full_awprot,
S00_AXI_awqos => ram_axi_full_awqos,
S00_AXI_awready => ram_axi_full_awready,
S00_AXI_awregion => ram_axi_full_awregion,
S00_AXI_awsize => ram_axi_full_awsize,
S00_AXI_awvalid => ram_axi_full_awvalid,
S00_AXI_bid => ram_axi_full_bid_slv,
S00_AXI_bready => ram_axi_full_bready,
S00_AXI_bresp => ram_axi_full_bresp,
S00_AXI_bvalid => ram_axi_full_bvalid,
S00_AXI_rdata => ram_axi_full_rdata,
S00_AXI_rid => ram_axi_full_rid_slv,
S00_AXI_rlast => ram_axi_full_rlast,
S00_AXI_rready => ram_axi_full_rready,
S00_AXI_rresp => ram_axi_full_rresp,
S00_AXI_rvalid => ram_axi_full_rvalid,
S00_AXI_wdata => ram_axi_full_wdata,
S00_AXI_wlast => ram_axi_full_wlast,
S00_AXI_wready => ram_axi_full_wready,
S00_AXI_wstrb => ram_axi_full_wstrb,
S00_AXI_wvalid => ram_axi_full_wvalid,
SYS_CLK_clk_n => sys_clk_n,
SYS_CLK_clk_p => sys_clk_p,
interconnect_aresetn => cross_aresetn,
peripheral_aresetn => aresetn,
sys_rst => sys_rst,
ui_addn_clk_0 => aclk,
ui_clk_sync_rst => open);
end generate;
plasoc_int_inst : plasoc_int
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
cpu_int => cpu_int,
dev_ints => int_dev_ints,
axi_awaddr => int_axi_lite_awaddr,
axi_awprot => int_axi_lite_awprot,
axi_awvalid => int_axi_lite_awvalid,
axi_awready => int_axi_lite_awready,
axi_wvalid => int_axi_lite_wvalid,
axi_wready => int_axi_lite_wready,
axi_wdata => int_axi_lite_wdata,
axi_wstrb => int_axi_lite_wstrb,
axi_bvalid => int_axi_lite_bvalid,
axi_bready => int_axi_lite_bready,
axi_bresp => int_axi_lite_bresp,
axi_araddr => int_axi_lite_araddr,
axi_arprot => int_axi_lite_arprot,
axi_arvalid => int_axi_lite_arvalid,
axi_arready => int_axi_lite_arready,
axi_rdata => int_axi_lite_rdata,
axi_rvalid => int_axi_lite_rvalid,
axi_rready => int_axi_lite_rready,
axi_rresp => int_axi_lite_rresp);
plasoc_timer_inst : plasoc_timer
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
axi_awaddr => timer_axi_lite_awaddr,
axi_awprot => timer_axi_lite_awprot,
axi_awvalid => timer_axi_lite_awvalid,
axi_awready => timer_axi_lite_awready,
axi_wvalid => timer_axi_lite_wvalid,
axi_wready => timer_axi_lite_wready,
axi_wdata => timer_axi_lite_wdata,
axi_wstrb => timer_axi_lite_wstrb,
axi_bvalid => timer_axi_lite_bvalid,
axi_bready => timer_axi_lite_bready,
axi_bresp => timer_axi_lite_bresp,
axi_araddr => timer_axi_lite_araddr,
axi_arprot => timer_axi_lite_arprot,
axi_arvalid => timer_axi_lite_arvalid,
axi_arready => timer_axi_lite_arready,
axi_rdata => timer_axi_lite_rdata,
axi_rvalid => timer_axi_lite_rvalid,
axi_rready => timer_axi_lite_rready,
axi_rresp => timer_axi_lite_rresp,
done => timer_int);
plasoc_gpio_inst : plasoc_gpio
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width,
data_in_width => vc707_default_gpio_width,
data_out_width => vc707_default_gpio_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
data_in => gpio_input,
data_out => gpio_output,
int => gpio_int,
axi_awaddr => gpio_axi_lite_awaddr,
axi_awprot => gpio_axi_lite_awprot,
axi_awvalid => gpio_axi_lite_awvalid,
axi_awready => gpio_axi_lite_awready,
axi_wvalid => gpio_axi_lite_wvalid,
axi_wready => gpio_axi_lite_wready,
axi_wdata => gpio_axi_lite_wdata,
axi_wstrb => gpio_axi_lite_wstrb,
axi_bvalid => gpio_axi_lite_bvalid,
axi_bready => gpio_axi_lite_bready,
axi_bresp => gpio_axi_lite_bresp,
axi_araddr => gpio_axi_lite_araddr,
axi_arprot => gpio_axi_lite_arprot,
axi_arvalid => gpio_axi_lite_arvalid,
axi_arready => gpio_axi_lite_arready,
axi_rdata => gpio_axi_lite_rdata,
axi_rvalid => gpio_axi_lite_rvalid,
axi_rready => gpio_axi_lite_rready,
axi_rresp => gpio_axi_lite_rresp);
axi_cdma_inst : axi_cdma_0
PORT map (
m_axi_aclk => aclk,
s_axi_lite_aclk => aclk,
s_axi_lite_aresetn => aresetn(0),
cdma_introut => cdma_int,
s_axi_lite_awaddr => cdmareg_axi_lite_awaddr(5 downto 0),
s_axi_lite_awvalid => cdmareg_axi_lite_awvalid,
s_axi_lite_awready => cdmareg_axi_lite_awready,
s_axi_lite_wvalid => cdmareg_axi_lite_wvalid,
s_axi_lite_wready => cdmareg_axi_lite_wready,
s_axi_lite_wdata => cdmareg_axi_lite_wdata,
s_axi_lite_bvalid => cdmareg_axi_lite_bvalid,
s_axi_lite_bready => cdmareg_axi_lite_bready,
s_axi_lite_bresp => cdmareg_axi_lite_bresp,
s_axi_lite_araddr => cdmareg_axi_lite_araddr(5 downto 0),
s_axi_lite_arvalid => cdmareg_axi_lite_arvalid,
s_axi_lite_arready => cdmareg_axi_lite_arready,
s_axi_lite_rdata => cdmareg_axi_lite_rdata,
s_axi_lite_rvalid => cdmareg_axi_lite_rvalid,
s_axi_lite_rready => cdmareg_axi_lite_rready,
s_axi_lite_rresp => cdmareg_axi_lite_rresp,
m_axi_arready => cdma_axi_full_arready,
m_axi_arvalid => cdma_axi_full_arvalid,
m_axi_araddr => cdma_axi_full_araddr,
m_axi_arlen => cdma_axi_full_arlen,
m_axi_arsize => cdma_axi_full_arsize,
m_axi_arburst => cdma_axi_full_arburst,
m_axi_arprot => cdma_axi_full_arprot,
m_axi_arcache => cdma_axi_full_arcache,
m_axi_rready => cdma_axi_full_rready,
m_axi_rvalid => cdma_axi_full_rvalid,
m_axi_rdata => cdma_axi_full_rdata,
m_axi_rresp => cdma_axi_full_rresp,
m_axi_rlast => cdma_axi_full_rlast,
m_axi_awready => cdma_axi_full_awready,
m_axi_awvalid => cdma_axi_full_awvalid,
m_axi_awaddr => cdma_axi_full_awaddr,
m_axi_awlen => cdma_axi_full_awlen,
m_axi_awsize => cdma_axi_full_awsize,
m_axi_awburst => cdma_axi_full_awburst,
m_axi_awprot => cdma_axi_full_awprot,
m_axi_awcache => cdma_axi_full_awcache,
m_axi_wready => cdma_axi_full_wready,
m_axi_wvalid => cdma_axi_full_wvalid,
m_axi_wdata => cdma_axi_full_wdata,
m_axi_wstrb => cdma_axi_full_wstrb,
m_axi_wlast => cdma_axi_full_wlast,
m_axi_bready => cdma_axi_full_bready,
m_axi_bvalid => cdma_axi_full_bvalid,
m_axi_bresp => cdma_axi_full_bresp,
cdma_tvect_out => open);
plasoc_uart_inst : plasoc_uart
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
axi_awaddr => uart_axi_lite_awaddr,
axi_awprot => uart_axi_lite_awprot,
axi_awvalid => uart_axi_lite_awvalid,
axi_awready => uart_axi_lite_awready,
axi_wvalid => uart_axi_lite_wvalid,
axi_wready => uart_axi_lite_wready,
axi_wdata => uart_axi_lite_wdata,
axi_wstrb => uart_axi_lite_wstrb,
axi_bvalid => uart_axi_lite_bvalid,
axi_bready => uart_axi_lite_bready,
axi_bresp => uart_axi_lite_bresp,
axi_araddr => uart_axi_lite_araddr,
axi_arprot => uart_axi_lite_arprot,
axi_arvalid => uart_axi_lite_arvalid,
axi_arready => uart_axi_lite_arready,
axi_rdata => uart_axi_lite_rdata,
axi_rvalid => uart_axi_lite_rvalid,
axi_rready => uart_axi_lite_rready,
axi_rresp => uart_axi_lite_rresp,
tx => uart_tx,
rx => uart_rx,
status_in_avail => uart_int);
plasoc_timer_extra_0_inst : plasoc_timer
generic map (
axi_address_width => axi_lite_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn(0),
axi_awaddr => timer_extra_0_axi_lite_awaddr,
axi_awprot => timer_extra_0_axi_lite_awprot,
axi_awvalid => timer_extra_0_axi_lite_awvalid,
axi_awready => timer_extra_0_axi_lite_awready,
axi_wvalid => timer_extra_0_axi_lite_wvalid,
axi_wready => timer_extra_0_axi_lite_wready,
axi_wdata => timer_extra_0_axi_lite_wdata,
axi_wstrb => timer_extra_0_axi_lite_wstrb,
axi_bvalid => timer_extra_0_axi_lite_bvalid,
axi_bready => timer_extra_0_axi_lite_bready,
axi_bresp => timer_extra_0_axi_lite_bresp,
axi_araddr => timer_extra_0_axi_lite_araddr,
axi_arprot => timer_extra_0_axi_lite_arprot,
axi_arvalid => timer_extra_0_axi_lite_arvalid,
axi_arready => timer_extra_0_axi_lite_arready,
axi_rdata => timer_extra_0_axi_lite_rdata,
axi_rvalid => timer_extra_0_axi_lite_rvalid,
axi_rready => timer_extra_0_axi_lite_rready,
axi_rresp => timer_extra_0_axi_lite_rresp,
done => timer_extra_0_int);
end Behavioral;
|
mit
|
70588c10f74bffebef6a5ad40bb0d6d8
| 0.58718 | 3.30995 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_timer_axi4_write_cntrl.vhd
| 1 | 6,980 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 31, 2017
--! @brief Contains the entity and architecture of the
--! Timer Core's Slave AXI4-Lite Write Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_timer_pack.all;
--! The Write Controller implements a Slave AXI4-Lite Write
--! interface in order to allow a Master interface to write to
--! the registers of the core.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_timer_axi4_write_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Register interface.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_trig_value_offset : std_logic_vector := X"0004" --! Defines the offset for the Trigger Value register.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Register interface.
reg_control : out std_logic_vector(axi_data_width-1 downto 0); --! Control register.
reg_trig_value : out std_logic_vector(axi_data_width-1 downto 0); --! Trigger Value register.
reg_valid : out std_logic := '0' --! When high, enables writing of the Control register.
);
end plasoc_timer_axi4_write_cntrl;
architecture Behavioral of plasoc_timer_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
-- Drive the axi write interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
reg_control <= (others=>'0');
reg_trig_value <= (others=>'0');
reg_valid <= '0';
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Sample address interface on handshake and go start
-- performing the write operation.
if axi_awvalid='1' and axi_awready_buff='1' then
-- Prevent the master from sending any more control information.
axi_awready_buff <= '0';
-- Sample the address sent from the master.
axi_awaddr_buff <= axi_awaddr;
-- Begin to read data to write.
axi_wready_buff <= '1';
state <= state_write;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_awready_buff <= '1';
end if;
-- WRITE mode.
when state_write=>
-- Wait for handshake.
if axi_wvalid='1' and axi_wready_buff='1' then
-- Send valid signal indicating new data may be
-- available.
reg_valid <= '1';
-- Prevent the master from sending any more data.
axi_wready_buff <= '0';
-- Only sample the specified bytes.
for each_byte in 0 to axi_data_width/8-1 loop
if axi_wstrb(each_byte)='1' then
-- Only sample written data if the address is valid.
if axi_awaddr_buff=reg_control_offset then
reg_control(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
elsif axi_awaddr_buff=reg_trig_value_offset then
reg_trig_value(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end if;
end loop;
-- Begin to transmit the response.
state <= state_response;
axi_bvalid_buff <= '1';
end if;
-- RESPONSE mode.
when state_response=>
-- Since no new information is available, lower the valid signal.
reg_valid <= '0';
-- Wait for handshake.
if axi_bvalid_buff='1' and axi_bready='1' then
-- Starting waiting for more address information on
-- successful handshake.
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
f189005844318b8e7e7d5fd0059df98c
| 0.510315 | 4.517799 | false | false | false | false |
tmeissner/cryptocores
|
cbctdes/rtl/vhdl/cbctdes.vhd
| 1 | 6,141 |
-- ======================================================================
-- CBC-DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity cbctdes is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 TO 63); -- key input
key2_i : in std_logic_vector(0 TO 63); -- key input
key3_i : in std_logic_vector(0 TO 63); -- key input
iv_i : in std_logic_vector(0 to 63); -- iv input
data_i : in std_logic_vector(0 TO 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
ready_o : out std_logic; -- ready to encrypt/decrypt
data_o : out std_logic_vector(0 TO 63); -- data output
valid_o : out std_logic -- output data valid flag
);
end entity cbctdes;
architecture rtl of cbctdes is
component tdes is
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 TO 63); -- key input
key2_i : in std_logic_vector(0 TO 63); -- key input
key3_i : in std_logic_vector(0 TO 63); -- key input
data_i : in std_logic_vector(0 TO 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
data_o : out std_logic_vector(0 TO 63); -- data output
valid_o : out std_logic; -- output data valid flag
ready_o : out std_logic
);
end component tdes;
signal s_mode : std_logic;
signal s_des_mode : std_logic;
signal s_start : std_logic;
signal s_key1 : std_logic_vector(0 to 63);
signal s_key2 : std_logic_vector(0 to 63);
signal s_key3 : std_logic_vector(0 to 63);
signal s_tdes_key1 : std_logic_vector(0 to 63);
signal s_tdes_key2 : std_logic_vector(0 to 63);
signal s_tdes_key3 : std_logic_vector(0 to 63);
signal s_iv : std_logic_vector(0 to 63);
signal s_datain : std_logic_vector(0 to 63);
signal s_datain_d : std_logic_vector(0 to 63);
signal s_des_datain : std_logic_vector(0 to 63);
signal s_validin : std_logic;
signal s_des_dataout : std_logic_vector(0 to 63);
signal s_dataout : std_logic_vector(0 to 63);
signal s_validout : std_logic;
signal s_ready : std_logic;
signal s_readyout : std_logic;
begin
s_des_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
s_dataout xor data_i when s_mode = '0' and start_i = '0' else
data_i;
data_o <= s_iv xor s_des_dataout when s_mode = '1' and s_start = '1' else
s_datain_d xor s_des_dataout when s_mode = '1' and s_start = '0' else
s_des_dataout;
s_tdes_key1 <= key1_i when start_i = '1' else s_key1;
s_tdes_key2 <= key2_i when start_i = '1' else s_key2;
s_tdes_key3 <= key3_i when start_i = '1' else s_key3;
s_des_mode <= mode_i when start_i = '1' else s_mode;
ready_o <= s_ready;
s_validin <= valid_i and s_ready;
valid_o <= s_validout;
inputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_mode <= '0';
s_start <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_iv <= (others => '0');
s_datain <= (others => '0');
s_datain_d <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1') then
s_start <= start_i;
s_datain <= data_i;
s_datain_d <= s_datain;
end if;
if(valid_i = '1' and s_ready = '1' and start_i = '1') then
s_mode <= mode_i;
s_key1 <= key1_i;
s_key2 <= key2_i;
s_key3 <= key3_i;
s_iv <= iv_i;
end if;
end if;
end process inputregister;
outputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_ready <= '1';
s_dataout <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1' and s_readyout = '1') then
s_ready <= '0';
end if;
if(s_validout = '1') then
s_ready <= '1';
s_dataout <= s_des_dataout;
end if;
end if;
end process outputregister;
i_tdes : tdes
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_des_mode,
key1_i => s_tdes_key1,
key2_i => s_tdes_key2,
key3_i => s_tdes_key3,
data_i => s_des_datain,
valid_i => s_validin,
data_o => s_des_dataout,
valid_o => s_validout,
ready_o => s_readyout
);
end architecture rtl;
|
gpl-2.0
|
ddb8e7d4dcce6d81ed09423f12234900
| 0.528578 | 3.242344 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd
| 4 | 70,851 |
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset;
use axi_datamover_v5_1_9.axi_datamover_cmd_status;
use axi_datamover_v5_1_9.axi_datamover_pcc;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl;
use axi_datamover_v5_1_9.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_9.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_9.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1_9.axi_datamover_rd_sf;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32)); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_9.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1_9.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1_9.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1_9.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
bsd-3-clause
|
656aba55ac8cb97e8089b3ec20837bc1
| 0.43902 | 4.200818 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/overloads.vhdl
| 1 | 7,903 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package overloads is
function "+" (a : std_logic_vector; b : integer ) return std_logic_vector;
function "+" (a : std_logic_vector; b : std_logic_vector) return std_logic_vector;
function "-" (a : std_logic_vector; b : integer ) return std_logic_vector;
function "-" (a : std_logic_vector; b : std_logic_vector) return std_logic_vector;
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "sra" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sra" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
end overloads;
package body overloads is
function "+" (a : std_logic_vector; b : integer) return std_logic_vector is
variable result : unsigned(a'range);
begin
result := unsigned(a) + b;
return std_logic_vector(result);
end function;
function "+" (a : std_logic_vector; b : std_logic_vector) return std_logic_vector is
variable result : unsigned(a'range);
begin
result := unsigned(a) + unsigned(b);
return std_logic_vector(result);
end function;
function "-" (a : std_logic_vector; b : integer) return std_logic_vector is
variable result : unsigned(a'range);
begin
result := unsigned(a) - b;
return std_logic_vector(result);
end function;
function "-" (a : std_logic_vector; b : std_logic_vector) return std_logic_vector is
variable result : unsigned(a'range);
begin
result := unsigned(a) - unsigned(b);
return std_logic_vector(result);
end function;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- sra
-------------------------------------------------------------------
function "sra" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => l(l'high));
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "sra";
-------------------------------------------------------------------
function "sra" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => l(l'high));
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "sra";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
end overloads;
|
gpl-3.0
|
ee06859188e31e7d9efe72e9c37930c1
| 0.507908 | 3.843872 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_wr_status_cntl.vhd
| 4 | 57,648 |
-------------------------------------------------------------------------------
-- axi_datamover_wr_status_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_datamover_wr_status_cntl;
architecture implementation of axi_datamover_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
bsd-3-clause
|
8845515148ad71f86f947062f5216c79
| 0.411463 | 5.111545 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/JumpDirMux.vhdl
| 1 | 687 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity JumpDirMux is
port (
JumpDir: in ctrl_t;
jumpAddr : in addr_t;
BranchMux : in addr_t;
output : out addr_t
);
end entity;
architecture behav of JumpDirMux is
begin
output <= jumpAddr when JumpDir = '1' else BranchMux;
printer: process(JumpDir, JumpAddr, BranchMux)
variable output : addr_t;
begin
if JumpDir = '1' then
output := jumpAddr;
else
output := BranchMux;
end if;
printf("pc_new = %s\n", output);
end process;
end architecture behav;
|
gpl-3.0
|
0fd7e5ae9284fb8e7d9c1dcc348ebce7
| 0.577875 | 3.903409 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_axi4_full2lite_write_cntrl.vhd
| 1 | 7,301 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Full2Lite Core's Write Controller. Please refer to the documentation
--! in plasoc_axi4_full2lite.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.plasoc_axi4_full2lite_pack.all;
entity plasoc_axi4_full2lite_write_cntrl is
generic (
axi_slave_id_width : integer := 1;
axi_address_width : integer := 32;
axi_data_width : integer := 32);
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
s_axi_awlen : in std_logic_vector(8-1 downto 0);
s_axi_awsize : in std_logic_vector(3-1 downto 0);
s_axi_awburst : in std_logic_vector(2-1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(4-1 downto 0);
s_axi_awprot : in std_logic_vector(3-1 downto 0);
s_axi_awqos : in std_logic_vector(4-1 downto 0);
s_axi_awregion : in std_logic_vector(4-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0) := (others=>'0');
s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others=>'0');
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0) := (others=>'0');
m_axi_awprot : out std_logic_vector(2 downto 0) := (others=>'0');
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0) := (others=>'0');
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0));
end plasoc_axi4_full2lite_write_cntrl;
architecture Behavioral of plasoc_axi4_full2lite_write_cntrl is
signal id_buff_0 : std_logic_vector(axi_slave_id_width-1 downto 0) := (others=>'0');
signal id_buff_1 : std_logic_vector(axi_slave_id_width-1 downto 0) := (others=>'0');
signal s_axi_awready_buff : std_logic := '0';
signal m_axi_awvalid_buff : std_logic := '0';
signal s_axi_wready_buff : std_logic := '0';
signal m_axi_wvalid_buff : std_logic := '0';
signal s_axi_bvalid_buff : std_logic := '0';
signal m_axi_bready_buff : std_logic := '0';
begin
s_axi_awready <= s_axi_awready_buff;
m_axi_awvalid <= m_axi_awvalid_buff;
s_axi_wready <= s_axi_wready_buff;
m_axi_wvalid <= m_axi_wvalid_buff;
s_axi_bvalid <= s_axi_bvalid_buff;
m_axi_bready <= m_axi_bready_buff;
process (aclk)
begin
if rising_edge (aclk) then
if aresetn='0' then
s_axi_awready_buff <= '1';
m_axi_awvalid_buff <= '0';
else
if s_axi_awvalid='1' and s_axi_awready_buff='1' then
id_buff_0 <= s_axi_awid;
m_axi_awaddr <= s_axi_awaddr;
m_axi_awprot <= s_axi_awprot;
end if;
if s_axi_awvalid='1' and s_axi_awready_buff='1' then
m_axi_awvalid_buff <= '1';
elsif m_axi_awvalid_buff='1' and m_axi_awready='1' then
m_axi_awvalid_buff <= '0';
end if;
if m_axi_awready='1' then
s_axi_awready_buff <= '1';
elsif s_axi_awvalid='1' and s_axi_awready_buff='1' then
s_axi_awready_buff <= '0';
end if;
end if;
end if;
end process;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
s_axi_wready_buff <= '1';
m_axi_wvalid_buff <= '0';
else
if s_axi_wvalid='1' and s_axi_wready_buff='1' then
id_buff_1 <= id_buff_0;
m_axi_wdata <= s_axi_wdata;
m_axi_wstrb <= s_axi_wstrb;
end if;
if s_axi_wvalid='1' and s_axi_wready_buff='1' then
m_axi_wvalid_buff <= '1';
elsif m_axi_wvalid_buff='1' and m_axi_wready='1' then
m_axi_wvalid_buff <= '0';
end if;
if m_axi_wready='1' then
s_axi_wready_buff <= '1';
elsif s_axi_wvalid='1' and s_axi_wready_buff='1' then
s_axi_wready_buff <= '0';
end if;
end if;
end if;
end process;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
s_axi_bvalid_buff <= '0';
m_axi_bready_buff <= '1';
else
if m_axi_bvalid='1' and m_axi_bready_buff='1' then
s_axi_bid <= id_buff_1;
s_axi_bresp <= m_axi_bresp;
end if;
if m_axi_bvalid='1' and m_axi_bready_buff='1' then
s_axi_bvalid_buff <= '1';
elsif s_axi_bvalid_buff='1' and s_axi_bready='1' then
s_axi_bvalid_buff <= '0';
end if;
if s_axi_bready='1' then
m_axi_bready_buff <= '1';
elsif m_axi_bvalid='1' and m_axi_bready_buff='1' then
m_axi_bready_buff <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
a4051d9da1147bcde9614857a1054157
| 0.437748 | 3.950758 | false | false | false | false |
sgstair/logicanalyzer
|
fpga/toplevel.vhd
| 1 | 1,224 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:44:56 06/01/2014
-- Design Name:
-- Module Name: toplevel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity toplevel is
Port ( clk : in STD_LOGIC;
ledred : out STD_LOGIC;
ledgreen : out STD_LOGIC);
end toplevel;
architecture Behavioral of toplevel is
signal counter : unsigned(25 downto 0) := (others => '0');
begin
ledred <= counter(25);
ledgreen <= counter(24);
process(clk)
begin
if clk'event and clk='1' then
counter <= counter + 1;
end if;
end process;
end Behavioral;
|
mit
|
45fce7f7c25c8cf8a7c1863f4d6ab720
| 0.583333 | 3.910543 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/control_vec_tb.vhdl
| 1 | 2,408 |
-- See tools/assemble.pl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.txt_utils.all;
-- A testbench has no ports.
entity control_vec_tb is
end control_vec_tb;
architecture behav of control_vec_tb is
component maindec is
port ( instr : in std_logic_vector(31 downto 0); -- instruction_t
regwrite, regdst, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
memwrite : out ctrl_memwidth_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t);
end component;
signal instr : std_logic_vector(31 downto 0); -- instruction_t
signal regwrite, regdst, link, jumpreg, jumpdirect, branch : ctrl_t;
signal memread : ctrl_memwidth_t;
signal memtoreg, memsex : ctrl_t;
signal memwrite : ctrl_memwidth_t;
signal shift, alusrc : ctrl_t;
signal aluop : alu_op_t;
alias op is instr(31 downto 26);
alias rs is instr(25 downto 21);
alias rt is instr(20 downto 16);
alias rd is instr(15 downto 11);
alias shamt is instr(10 downto 6);
alias func is instr(5 downto 0);
alias address is instr(25 downto 0);
alias imm is instr(15 downto 0);
alias b is TO_BSTRING [STD_LOGIC_VECTOR return STRING];
alias b is TO_STRING [STD_ULOGIC return STRING];
begin
control : maindec port map(
instr,
regwrite, regdst, link, jumpreg, jumpdirect, branch,
memread,
memtoreg,
memsex,
memwrite,
shift, alusrc,
aluop);
printer: process
begin
instr <= X"0000_0000"; -- nop
wait for 1 ns;
assert RegWrite = '1'
and RegDst = '1'
and Link = '0'
and JumpReg = '0'
and JumpDirect = '0'
and Branch = '0'
and MemRead = "00"
and MemtoReg = '0'
and MemSex = '0'
and MemWrite = "00"
and Shift = '1'
and AluSrc = '0'
and AluOp = alu_sll
report
"Fail"
severity note;
wait;
end process;
end behav;
|
gpl-3.0
|
fffdfe0c6f01ed94d5977c76ebc86a88
| 0.527409 | 4.13036 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_PofVactofVref.vhd
| 1 | 3,496 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_PofVactofVref is
port (
clock : in std_logic;
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
PofVactofVref : out std_logic_vector(31 downto 0)
);
end k_ukf_PofVactofVref;
architecture struct of k_ukf_PofVactofVref is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11,Z12,Z13 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkofzero,
datab => Vactcapdashofkplusone,
result => Z1);
M2 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkofone,
datab => Vactcapdashofkplusone,
result => Z3);
M3 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkoftwo,
datab => Vactcapdashofkplusone,
result => Z5);
M4 : k_ukf_sub port map
( clock => clock,
dataa => Vsigrefofkofzero,
datab => Vrefcapofkplusone,
result => Z2);
M5 : k_ukf_sub port map
( clock => clock,
dataa => Vsigrefofkofone,
datab => Vrefcapofkplusone,
result => Z4);
M6 : k_ukf_sub port map
( clock => clock,
dataa => Vsigrefofkoftwo,
datab => Vrefcapofkplusone,
result => Z6);
M7 : k_ukf_mult port map
( clock => clock,
dataa => Z1,
datab => Z2,
result => Z7);
M8 : k_ukf_mult port map
( clock => clock,
dataa => Z3,
datab => Z4,
result => Z8);
M9 : k_ukf_mult port map
( clock => clock,
dataa => Z5,
datab => Z6,
result => Z9);
M10 : k_ukf_mult port map
( clock => clock,
dataa => Wofcofzero,
datab => Z7,
result => Z10);
M11 : k_ukf_mult port map
( clock => clock,
dataa => Wofcofone,
datab => Z8,
result => Z11);
M12 : k_ukf_mult port map
( clock => clock,
dataa => Wofcoftwo,
datab => Z9,
result => Z12);
M13 : k_ukf_add port map
( clock => clock,
dataa => Z10,
datab => Z11,
result => Z13);
M14 : k_ukf_add port map
( clock => clock,
dataa => Z12,
datab => Z13,
result => PofVactofVref);
end struct;
|
gpl-2.0
|
bee077b1cfd412f17e3af2bb5f720319
| 0.581808 | 3.255121 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_uart_axi4_write_cntrl.vhd
| 1 | 5,790 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! UART Core's Write Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_uart_pack.all;
entity plasoc_uart_axi4_write_cntrl is
generic (
fifo_depth : integer := 8;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_status_in_avail_bit_loc : integer := 0;
reg_control_status_out_avail_bit_loc : integer := 1;
reg_in_fifo_offset : std_logic_vector := X"0004";
reg_out_fifo_offset : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
reg_out_fifo : out std_logic_vector(7 downto 0);
reg_out_fifo_valid : out std_logic;
reg_out_fifo_ready : in std_logic;
reg_in_avail : out std_logic);
end plasoc_uart_axi4_write_cntrl;
architecture Behavioral of plasoc_uart_axi4_write_cntrl is
component generic_fifo is
generic (
FIFO_WIDTH : positive := 32;
FIFO_DEPTH : positive := 1024
);
port (
clock : in std_logic;
nreset : in std_logic;
write_data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
read_data : out std_logic_vector(FIFO_WIDTH-1 downto 0);
write_en : in std_logic;
read_en : in std_logic;
full : out std_logic;
empty : out std_logic;
level : out std_logic_vector(clogb2(FIFO_DEPTH)-1 downto 0
)
);
end component;
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
signal reg_in_fifo : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal in_fifo : std_logic_vector(7 downto 0);
signal in_valid : std_logic := '0';
signal in_not_ready : std_logic;
signal out_fifo : std_logic_vector(7 downto 0);
signal out_ready : std_logic;
signal out_not_valid : std_logic;
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
reg_in_avail <= not in_not_ready;
reg_out_fifo <= out_fifo;
reg_out_fifo_valid <= not out_not_valid;
out_ready <= reg_out_fifo_ready;
in_fifo <= reg_in_fifo(7 downto 0);
soc_uart_fifo_inst : generic_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => fifo_depth)
port map (
clock => aclk,
nreset => aresetn,
write_data => in_fifo,
read_data => out_fifo,
write_en => in_valid,
read_en => out_ready,
full => in_not_ready,
empty => out_not_valid,
level => open);
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
reg_in_fifo <= (others=>'0');
in_valid <= '0';
state <= state_wait;
else
case state is
when state_wait=>
if axi_awvalid='1' and axi_awready_buff='1' then
axi_awready_buff <= '0';
axi_awaddr_buff <= axi_awaddr;
axi_wready_buff <= '1';
state <= state_write;
else
axi_awready_buff <= '1';
end if;
when state_write=>
if axi_wvalid='1' and axi_wready_buff='1' then
axi_wready_buff <= '0';
for each_byte in 0 to axi_data_width/8-1 loop
if axi_wstrb(each_byte)='1' then
if axi_awaddr_buff=reg_out_fifo_offset and in_not_ready='0' then
reg_in_fifo(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
in_valid <= '1';
end if;
end if;
end loop;
state <= state_response;
axi_bvalid_buff <= '1';
end if;
when state_response=>
in_valid <= '0';
if axi_bvalid_buff='1' and axi_bready='1' then
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
862fd9410b929ff55d2bd2c81f461d4e
| 0.488601 | 3.928087 | false | false | false | false |
tmeissner/cryptocores
|
aes/rtl/vhdl/aes_enc.vhd
| 1 | 5,265 |
-- ======================================================================
-- AES encryption/decryption
-- Copyright (C) 2019 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity aes_enc is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity aes_enc;
architecture rtl of aes_enc is
begin
IterG : if design_type = "ITER" generate
signal s_round : t_enc_rounds;
begin
CryptP : process (reset_i, clk_i) is
variable v_state : t_datatable2d;
variable v_key : t_key;
begin
if (reset_i = '0') then
v_state := (others => (others => (others => '0')));
v_key := (others => (others => '0'));
s_round <= 0;
accept_o <= '0';
data_o <= (others => '0');
valid_o <= '0';
elsif (rising_edge(clk_i)) then
case s_round is
when 0 =>
accept_o <= '1';
if (accept_o = '1' and valid_i = '1') then
accept_o <= '0';
v_state := set_state(data_i);
v_key := set_key(key_i);
s_round <= s_round + 1;
end if;
when 1 =>
v_state := addroundkey(v_state, v_key);
v_key := key_round(v_key, s_round-1);
s_round <= s_round + 1;
when t_enc_rounds'high-1 =>
v_state := subbytes(v_state);
v_state := shiftrow(v_state);
v_state := addroundkey(v_state, v_key);
s_round <= s_round + 1;
-- set data & valid to save one cycle
valid_o <= '1';
data_o <= get_state(v_state);
when t_enc_rounds'high =>
if (valid_o = '1' and accept_i = '1') then
valid_o <= '0';
data_o <= (others => '0');
s_round <= 0;
-- Set accept to save one cycle
accept_o <= '1';
end if;
when others =>
v_state := subbytes(v_state);
v_state := shiftrow(v_state);
v_state := mixcolumns(v_state);
v_state := addroundkey(v_state, v_key);
v_key := key_round(v_key, s_round-1);
s_round <= s_round + 1;
end case;
end if;
end process CryptP;
psl : block is
signal s_key , s_din, s_dout : std_logic_vector(0 to 127) := (others => '0');
begin
process (clk_i) is
begin
if (rising_edge(clk_i)) then
s_key <= key_i;
s_din <= data_i;
s_dout <= data_o;
end if;
end process;
default clock is rising_edge(clk_i);
-- initial reset
restrict {not reset_i; reset_i[+]}[*1];
-- constraints
assume always (valid_i and not accept_o -> next valid_i);
assume always (valid_i and not accept_o -> next key_i = s_key);
assume always (valid_i and not accept_o -> next data_i = s_din);
ACCEPTO_c : cover {accept_o};
ACCEPT_IN_ROUND_0_ONLY_a : assert always (accept_o -> s_round = 0);
VALIDI_AND_ACCEPTO_c : cover {valid_i and accept_o};
ACCEPT_OFF_WHEN_VALID_a : assert always (valid_i and accept_o -> next not accept_o);
VALIDO_c : cover {valid_o};
VALID_IN_LAST_ROUND_ONLY_a : assert always (valid_o -> s_round = t_enc_rounds'high);
VALIDO_AND_ACCEPTI_c : cover {valid_o and accept_i};
VALID_OFF_WHEN_ACCEPTED_a : assert always (valid_o and accept_i -> next not valid_o);
VALIDO_AND_NOT_ACCEPTI_c : cover {valid_o and not accept_i};
VALID_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next valid_o);
DATA_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next data_o = s_dout);
end block psl;
end generate IterG;
end architecture rtl;
|
gpl-2.0
|
093643117e51767392b0ac36e4611bf5
| 0.523837 | 3.564658 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/blk_mem_gen_1/sim/blk_mem_gen_1.vhd
| 1 | 12,790 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "kintex7",
C_XDEVICEFAMILY => "kintex7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.53475 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
|
bsd-3-clause
|
727be5b15197cd696956678583677581
| 0.610321 | 3.201502 | false | false | false | false |
Ttl/pic16f84
|
datapath.vhd
| 1 | 2,040 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity datapath is
Port ( clk,reset : in STD_LOGIC;
instr10 : in STD_LOGIC_VECTOR(10 downto 0);
writedata : out std_logic_vector(7 downto 0);
readdata : in std_logic_vector(7 downto 0);
alu_op : in alu_ctrl;
write_en : out std_logic;
bmux,rwmux,writew : in std_logic;
amux : in std_logic_vector(1 downto 0);
status_flags : out std_logic_Vector(4 downto 0);
status_c_in : in std_logic;
skip_ex : in std_logic);
end datapath;
architecture Behavioral of datapath is
signal wnext, w : std_logic_vector(7 downto 0);
signal alu_z, alu_c, alu_dc : std_logic;
signal amux_out, bmux_out : std_logic_vector(7 downto 0);
signal alu_result : std_logic_vector(7 downto 0);
begin
-- If skip_ex is '1' skipped instruction is computed, but not stored
-- Write ALU result to RAM
write_en <= rwmux and not skip_ex;
-- Source of next W value
wnext <= alu_result when writew = '1' and skip_ex = '0' else w;
-- RAM input data is always ALU result
writedata <= alu_result;
-- Status flags from ALU to IO
status_flags <= "00"&alu_z&alu_dc&alu_c;
w_reg : entity work.flopr
generic map( WIDTH => 8)
port map(clk => clk,
reset => reset,
d => wnext,
q => w
);
-- ALU A mux
amux_out <= instr10(7 downto 0) when amux = "00" else
readdata when amux = "01" else
"00000000" when amux = "10" else
"--------";
-- ALU B mux
bmux_out <= w when bmux = '0' else "00000001";
alu1 : entity work.alu
Port map( a => amux_out,
b => bmux_out,
ctrl => alu_op,
bit_clr_set => instr10(10),
bit_sel => instr10(9 downto 7),
status_c => status_c_in,
r => alu_result,
z => alu_z,
c => alu_c,
dc => alu_dc
);
end Behavioral;
|
lgpl-3.0
|
a0c36f5ae9747911b7583219382ba7a5
| 0.554412 | 3.411371 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/ID.vhdl
| 1 | 4,083 |
-- Instruction Decode
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity InstructionDecode is
port (
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
memwrite : out ctrl_memwidth_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic
);
end;
architecture struct of InstructionDecode is
-- multi used componets
component maindec is
port(
instr : in std_logic_vector(31 downto 0);
Link, JumpReg, JumpDirect, Branch, MemToReg, MemSex, Shift, ALUSrc, RegWrite, RegDst: out ctrl_t;
memRead, memWrite: out ctrl_memwidth_t;
ALUOp: out alu_op_t);
end component;
component returnAddrMux is
port (
returnAddrControl: in ctrl_t;
returnAddrReg : in reg_t;
regDstMux : in reg_t;
output : out reg_t);
end component;
component regDstMux is
port (
RegDst: in ctrl_t;
rt : in reg_t; --Instruction 20-16
rd : in reg_t; --Instruction 15-11
output : out reg_t);
end component;
-- control signals consumed internally
signal iRegWrite, iRegDst, iLink, iJumpReg, iJumpDirect, iBranch, iMemToReg, iMemSex, iShift, iALUSrc, ireturnAddrControl, iBranchORJumpDirOut: ctrl_t;
signal iMemRead, iMemWrite : ctrl_memwidth_t;
signal iAluOp : alu_op_t;
signal iReadReg1, iReadReg2, iWriteReg : reg_t;
signal returnAddrControl : ctrl_t;
-- instruction signals
alias op is instr(31 downto 26);
alias rs is instr(25 downto 21);
alias rt is instr(20 downto 16);
alias rd is instr(15 downto 11);
alias shamt is instr(10 downto 6);
alias func is instr(5 downto 0);
alias imm is instr(15 downto 0);
alias jump_immediate is instr(25 downto 0);
-- regFile Signals
signal regDstMuxOut, returnAddrMuxOut : reg_t;
constant zeroes : half_t := (others => '0');
constant ones : half_t := (others => '1');
begin
-- immediates
jump_addr <= pc_plus_4(31 downto 28) & jump_immediate & "00";
returnAddrControl <= (iBranch or iJumpDirect) and iLink;
zeroxed <= (31 downto 5 => '0') & shamt;
sexed <= zeroes & imm when imm(15) = '0' else ones & imm;
maindec1: maindec
port map (instr => instr,
Link => iLink,
JumpReg => iJumpReg,
JumpDirect => iJumpDirect,
Branch => iBranch,
MemToReg => iMemToReg,
MemSex => iMemSex,
Shift => iShift,
ALUSrc => iALUSrc,
RegWrite => iRegWrite,
RegDst => iRegDst,
memRead => imemRead,
memWrite => imemWrite,
ALUOp => iALUOp);
--regFile
regDstMux1: regDstMux
port map (RegDst => iRegDst, rt => rt, rd => rd, output => RegDstMuxOut);
returnAddrMux1: returnAddrMux
port map (returnAddrControl => returnAddrControl, returnAddrReg => R31, regDstMux => regDstMuxOut, output => iWritereg);
RegWrite <= iRegWrite;
Link <= iLink;
JumpReg <= iJumpReg;
JumpDirect <= iJumpDirect;
Branch <= iBranch;
MemRead <= iMemRead;
MemToReg <= iMemToReg;
MemSex <= iMemSex;
memWrite <= iMemWrite;
Shift <= iShift;
ALUSrc <= iALUSrc;
AluOp <= iAluOp;
process(instr) begin printf(ANSI_RED & "Decoding instruction %s\n", instr); end process;
process(instr) begin printf(ANSI_RED & "readreg1=%s, readreg2=%s, writereg %s\n", iReadreg1, iReadreg2, iWritereg); end process;
ReadReg1 <= rs;
ReadReg2 <= rt;
iReadReg1 <= rs;
iReadReg2 <= rt;
WriteReg <= iWriteReg;
end struct;
|
gpl-3.0
|
8fff495b7cf694d3dcac56824eae29ed
| 0.591232 | 3.848256 | false | false | false | false |
Ttl/pic16f84
|
memory.vhd
| 1 | 8,534 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.picpkg.all;
entity memory is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
a1 : in STD_LOGIC_VECTOR (6 downto 0);
d1 : out STD_LOGIC_VECTOR (7 downto 0);
wd : in STD_LOGIC_VECTOR (7 downto 0);
we : in STD_LOGIC;
status_flags : in std_logic_vector(4 downto 0);
status_write : in std_logic_vector(4 downto 0);
status_c : out std_logic;
pc_mem_out : out std_logic_vector(12 downto 0);
pcl_in : in std_logic_vector(7 downto 0);
porta_inout : inout std_logic_vector(4 downto 0);
portb_inout : inout std_logic_vector(7 downto 0);
fsr_to_pcl : out std_logic;
intcon_out : out std_logic_vector(7 downto 0);
option_reg_out : out std_logic_vector(7 downto 0);
interrupt : in interrupt_type;
retfie : in STD_LOGIC;
portb_interrupt : out STD_LOGIC;
portb0_interrupt : out STD_LOGIC);
end memory;
architecture Behavioral of memory is
type fsr_type is array(0 to 13) of std_logic_vector(7 downto 0);
-- Two different banks
-- Access is decided by status(5) bit
signal mem_b0, mem_b1 : mem_type8 := (others => (others => '0'));
-- Special function register
signal sfr : fsr_type;
-- SFR fields
alias TMR0 is sfr(0);
alias OPTION_REG is sfr(1);
-- PCL
alias STATUS is sfr(2);
alias FSR is sfr(3);
alias PORTA is sfr(4);
alias TRISA is sfr(5);
alias PORTB is sfr(6);
alias TRISB is sfr(7);
alias EEDATA is sfr(8);
alias EECON1 is sfr(9);
alias EEADR is sfr(10);
alias EECON2 is sfr(11);
alias PCLATH is sfr(12);
alias INTCON is sfr(13);
alias bank is sfr(2)(5);
signal portb0_delayed : std_logic;
signal portb0_rising, portb0_falling : std_logic;
begin
-- Memory
process(clk, reset, we, a1, mem_b0, mem_b1, sfr, bank, pcl_in, porta_inout, portb_inout, trisa, trisb)
variable addr : std_logic_vector(6 downto 0);
variable portb_prev : std_logic_vector(7 downto 4);
begin
-- Indirect addressing
if a1 = "0000000" then
addr := fsr(6 downto 0);
else
addr := a1;
end if;
if rising_edge(clk) then
for I in 0 to 4 loop
if status_write(I) = '1' then
status(I) <= status_flags(I);
end if;
end loop;
portb_interrupt <= '0';
-- INTCON(0), RBIF bit. PORTB[4:7] has changed state, must be cleared in software
-- and with TRISB to compare only input pins
if (portb_prev(7 downto 4) and trisb(7 downto 4)) /= (portb_inout(7 downto 4) and trisb(7 downto 4)) then
portb_interrupt <= '1';
end if;
portb_prev := portb_inout(7 downto 4);
portb0_interrupt <= '0';
-- OPTION(6) is interrupt edge direction, 1 = rising edge
if option_reg(6) = '1' and portb0_rising = '1' then
portb0_interrupt <= '1';
end if;
if option_reg(6) = '0' and portb0_falling = '1' then
portb0_interrupt <= '1';
end if;
-- Set RB interrupt bit (RBIF)
if interrupt = I_RB then
intcon(0) <= '1';
end if;
-- Set PORTB(0)/INT interrupt bit (INTF)
if interrupt = I_INT then
intcon(1) <= '1';
end if;
-- Set TMR0 overflow bit (T0IF)
if interrupt = I_TMR0 then
intcon(2) <= '1';
end if;
-- On interrupt INTCON(7) GIE is cleared
if interrupt /= I_NONE then
intcon(7) <= '0';
end if;
-- On return from interrupt (retfie) GIE is set
if retfie = '1' then
intcon(7) <= '1';
end if;
if we = '1' then
--Write
case to_integer(unsigned(addr)) is
-- Indirect addressing
when 0 =>
-- Pointer pointing to itself ?
-- TMR0/OPTION_REG
when 1 =>
if bank = '0' then
tmr0 <= wd;
else
option_reg <= wd;
end if;
-- PCL
when 2 =>
--Handled by pc_control
-- STATUS
when 3 =>
status <= "00"&wd(5 downto 0);
-- FSR
when 4 =>
fsr <= wd;
-- PORTA/TRISA
when 5 =>
if bank = '0' then
-- PORTA
porta <= wd;
else
-- TRISA
trisa <= "111"&wd(4 downto 0);
end if;
-- PORTB/TRISB
when 6 =>
if bank = '0' then
-- PORTB
portb <= wd;
else
-- TRISB
trisb <= wd;
end if;
-- Not implemented
when 7 =>
-- EEDATA/EECON1
when 8 =>
if bank = '0' then
eedata <= wd;
else
eecon1 <= wd;
end if;
-- EADR/EECON2
when 9 =>
if bank = '0' then
eeadr <= wd;
else
eecon2 <= wd;
end if;
-- PCLATH
when 10 =>
pclath <= "000"&wd(4 downto 0);
-- INTCON
when 11 =>
intcon <= wd;
when others =>
if bank = '0' then
mem_b0(to_integer(unsigned(addr))) <= wd;
else
mem_b1(to_integer(unsigned(addr))) <= wd;
end if;
end case;
end if;
end if;
-- Set output
case to_integer(unsigned(addr)) is
-- Read from pointer that points to itself
when 0 =>
d1 <= "XXXXXXXX";
-- TMR0/OPTION_REG
when 1 =>
if bank = '0' then
d1 <= tmr0;
else
d1 <= option_reg;
end if;
-- PCL
when 2 =>
-- Read low bits of PC
d1 <= pcl_in;
-- STATUS
when 3 =>
d1 <= "00"&status(5 downto 0);
-- FSR
when 4 =>
d1 <= fsr;
-- PORTA/TRISA
when 5 =>
if bank = '0' then
d1 <= "000"&porta_inout;
else
d1 <= "000"&trisa(4 downto 0);
end if;
-- PORTB/TRISB
when 6 =>
if bank = '0' then
d1 <= portb_inout;
else
d1 <= trisb;
end if;
-- Not implemented, read as 0
when 7 =>
d1 <= "00000000";
-- EEDATA/EECON1
when 8 =>
if bank = '0' then
d1 <= eedata;
else
d1 <= eecon1;
end if;
-- EEADR/EECON2
when 9 =>
if bank = '0' then
d1 <= eeadr;
else
d1 <= eecon2;
end if;
-- PCLATH
when 10 =>
-- Not updated automatically from PC
d1 <= pclath;
-- INTCON
when 11 =>
d1 <= intcon;
when others =>
if bank = '0' then
d1 <= mem_b0(to_integer(unsigned(addr)));
else
d1 <= mem_b1(to_integer(unsigned(addr)));
end if;
end case;
-- Set outputs if needed
for I in 0 to 4 loop
-- If output
if trisa(I) = '0' then
porta_inout(I) <= porta(I);
else
porta_inout(I) <= 'Z';
end if;
end loop;
for I in 0 to 7 loop
-- If output
if trisb(I) = '0' then
portb_inout(I) <= portb(I);
else
portb_inout(I) <= 'Z';
end if;
end loop;
if reset = '1' then
option_reg <= "11111111";
intcon <= "0000000-";
pclath <= "00000000";
porta_inout <= "ZZZZZ";
portb_inout <= "ZZZZZZZZ";
trisa <= "---11111";
trisb <= "11111111";
status <="00011000";
end if;
end process;
portb0_delay: process(clk, portb_inout)
begin
if rising_edge(clk) then
portb0_delayed <= portb_inout(0);
end if;
end process;
portb0_rising <= not portb0_delayed and portb_inout(0);
portb0_falling <= portb0_delayed and not portb_inout(0);
-- Output C flag to ALU for RLF/RRF instructions
status_c <= status(0);
-- PCL is written to when updated
pc_mem_out <= pclath(4 downto 0)&wd;
intcon_out <= intcon;
option_reg_out <= option_reg;
fsr_to_pcl <= '1' when fsr = "00000010" else '0';
end Behavioral;
|
lgpl-3.0
|
f9bdd08adfbf32d9b166dd27e0a1a13e
| 0.478322 | 3.710435 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/sim/mig_wrap_proc_sys_reset_0_0.vhd
| 1 | 5,865 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY mig_wrap_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_0_0;
ARCHITECTURE mig_wrap_proc_sys_reset_0_0_arch OF mig_wrap_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_0_0_arch;
|
mit
|
78a1491eecc24b7d1ffbd286dc872f40
| 0.706394 | 3.57404 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_mm2s_sm.vhd
| 4 | 28,280 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
bsd-3-clause
|
c91bb753a8cf19034d8082809d2ced80
| 0.399611 | 4.602865 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/vga/vram.vhdl
| 1 | 3,654 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.color_util.all;
use work.utils.all;
use work.txt_utils.all;
use work.memory_map.all;
entity vram is
generic ( MEM_SIZE : natural := 300; PIXEL_SIZE : natural := 32 );
port (
x : in std_logic_vector (9 downto 0); -- 640 = 10_1000_0000b
y : in std_logic_vector (8 downto 0); -- 480 = 1_1110_0000b
retracing : in std_logic;
-- I/O
r, g, b : out std_logic_vector (3 downto 0);
-- Bus access to VRAM
bus_addr : in addr_t;
bus_din : in word_t;
bus_dout : out word_t;
bus_wr : in std_logic;
bus_clk : in std_logic
);
end entity vram;
architecture behavioral of vram is
constant h_display : integer := 640;
constant v_display : integer := 480;
constant x_pixels : natural := h_display / PIXEL_SIZE; -- 20
constant y_pixels : natural := v_display / PIXEL_SIZE; -- 15
type vram_t is array (0 to MEM_SIZE-1) of byte_t;
signal mem : vram_t;
signal byte00 : byte_t;
signal byte01 : byte_t;
signal byte02 : byte_t;
signal byte03 : byte_t;
signal byte04 : byte_t;
signal byte05 : byte_t;
signal byte06 : byte_t;
signal byte07 : byte_t;
signal byte08 : byte_t;
signal byte09 : byte_t;
signal byte10 : byte_t;
signal byte11 : byte_t;
signal byte12 : byte_t;
signal byte13 : byte_t;
signal byte14 : byte_t;
signal byte15 : byte_t;
signal byte16 : byte_t;
signal byte17 : byte_t;
signal byte18 : byte_t;
signal byte19 : byte_t;
signal byte150 : byte_t;
signal byte280 : byte_t;
signal byte299 : byte_t;
begin
process(x, y, retracing)
variable color : rgb_t := BLACK;
variable x_int, y_int : natural;
variable row, col : natural;
variable offset : natural;
begin
if retracing = '1' then
color := BLACK;
else
x_int := to_integer(unsigned(x(9 downto 5)));
y_int := to_integer(unsigned(y(8 downto 5)));
--color.r := x(9 downto 6);
--color.g := y(8 downto 5);
--color.b := "0000";
offset := x_int + y_int * x_pixels;
color.r := mem(offset)(7 downto 5) & B"0";
color.g := mem(offset)(4 downto 2) & B"0";
color.b := mem(offset)(1 downto 0) & B"00";
if x = "0000000000" or y = "000000000" or x = "1001111111" or y = "111011111" then
color := WHITE;
end if;
end if;
(r, g, b) <= color;
end process;
byte00 <= mem(0);
byte01 <= mem(1);
byte02 <= mem(2);
byte03 <= mem(3);
byte04 <= mem(4);
byte05 <= mem(5);
byte06 <= mem(6);
byte07 <= mem(7);
byte08 <= mem(8);
byte09 <= mem(9);
byte10 <= mem(10);
byte11 <= mem(11);
byte12 <= mem(12);
byte13 <= mem(13);
byte14 <= mem(14);
byte15 <= mem(15);
byte16 <= mem(16);
byte17 <= mem(17);
byte18 <= mem(18);
byte19 <= mem(19);
byte150 <= mem(150);
byte280 <= mem(280);
byte299 <= mem(299);
process(bus_clk)
begin
if(rising_edge(bus_clk)) then
if(bus_wr = '1') then
printf(ANSI_GREEN & "writing %s to %s\n", bus_din, bus_addr);
mem(to_integer(unsigned(bus_addr and not mmap(mmap_vram).base))) <= bus_din(7 downto 0);
end if;
bus_dout(7 downto 0) <= mem(to_integer(unsigned(bus_addr and not mmap(mmap_vram).base)));
end if;
end process;
end architecture;
|
gpl-3.0
|
b6b917c8dfcd0b18fa23b5ab3a44f4f5
| 0.539135 | 3.245115 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_gpio.vhd
| 1 | 14,745 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's GPIO Core.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
--! The Plasma-SoC's General Purpose Input and Output (GPIO) Core is built
--! so that the CPU has a simple, albiet inefficient, way to access
--! signals outside of the CPU. Because the overhead incurred in a transaction,
--! the GPIO Core should not be relied upon if large amounts of data require transfer.
--!
--! The operation of the GPIO Core can be described in terms of its registers, including
--! Control, Data In, and Data Out. The bits of the Control register include the Enable and
--! Ack. Setting the Enable bit puts the GPIO Core in interruption mode, during which Data In can
--! only accept new data from the GPIO Core's data_in if an acknowledgement is received by
--! writing high to the ACK bit. With interruption mode disabled, Data In will always accept
--! new data from data_in. Writing to the Data Out register sets the GPIO Core's data_out.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_gpio is
generic (
-- Device parameters.
data_in_width : integer := 16; --! Defines the width of data_in. This value should be less than or equal to axi_data_width.
data_out_width : integer := 16; --! Defines the width of data_out. This value should be less than or equal to axi_data_width.
-- Slave AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
axi_control_offset : integer := 0; --! Defines the offset for the Control register.
axi_control_enable_bit_loc : integer := 0; --! Defines the bit location of the Enable bit in the Control register.
axi_control_ack_bit_loc : integer := 1; --! Defines the bit location of the Ack bit in the Control register.
axi_data_in_offset : integer := 4; --! Defines the offset for the Data In register.
axi_data_out_offset : integer := 8 --! Defines the offset for the Data Out register.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low. Technically supposed to be asynchronous, however asynchronous resets aren't used.
-- Device interface.
data_in : in std_logic_vector(data_in_width-1 downto 0); --! Data read into the GPIO Core. This input can be registered into the Data In register, depending on the right conditions.
data_out : out std_logic_vector(data_out_width-1 downto 0); --! Data written out of the GPIO Core. This output is registered by the Data Out register.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- Interrupt interface.
int : out std_logic --! If the GPIO Core is configured in interruption mode, a change in Data In causes intr to go high until the GPIO Core is acknowledged.
);
end plasoc_gpio;
architecture Behavioral of plasoc_gpio is
component plasoc_gpio_cntrl is
generic (
constant data_in_width : integer := 16 );
port (
clock : in std_logic;
nreset : in std_logic;
enable : in std_logic;
ack : in std_logic;
int : out std_logic;
data_in_axi : out std_logic_vector(data_in_width-1 downto 0);
data_in_periph : in std_logic_vector(data_in_width-1 downto 0) );
end component;
component plasoc_gpio_axi4_write_cntrl is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_control_enable_bit_loc : integer := 0;
reg_control_ack_bit_loc : integer := 1;
reg_data_out_offset : std_logic_vector := X"0008"
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Register interface.
reg_control_enable : out std_logic; --! Control register.
reg_control_ack : out std_logic;
reg_data_out : out std_logic_vector(axi_data_width-1 downto 0)
);
end component;
component plasoc_gpio_axi4_read_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Register interface.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_data_in_offset : std_logic_vector := X"0004";
reg_data_out_offset : std_logic_vector := X"0008"
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- Register interface.
reg_control : in std_logic_vector(axi_data_width-1 downto 0);
reg_data_in : in std_logic_vector(axi_data_width-1 downto 0);
reg_data_out : in std_logic_vector(axi_data_width-1 downto 0)
);
end component;
-- Constant declarations.
constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width));
constant axi_data_in_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_data_in_offset,axi_address_width));
constant axi_data_out_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_data_out_offset,axi_address_width));
signal reg_control : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal reg_control_enable : std_logic; --! Control register.
signal reg_control_ack : std_logic;
signal reg_control_enable_buff : std_logic_vector(axi_data_width-1 downto 0);
signal reg_control_ack_buff : std_logic_vector(axi_data_width-1 downto 0);
signal reg_data_in : std_logic_vector(axi_data_width-1 downto 0);
signal reg_data_out : std_logic_vector(axi_data_width-1 downto 0);
begin
reg_data_in(axi_data_width-1 downto data_in_width) <= (others=>'0');
data_out <= reg_data_out(data_out_width-1 downto 0);
reg_control(axi_control_enable_bit_loc) <= reg_control_enable;
reg_control(axi_control_ack_bit_loc) <= reg_control_ack;
plasoc_gpio_cntrl_inst : plasoc_gpio_cntrl
generic map (
data_in_width => data_in_width )
port map (
clock => aclk,
nreset => aresetn,
enable => reg_control_enable,
ack => reg_control_ack,
int => int,
data_in_axi => reg_data_in(data_in_width-1 downto 0),
data_in_periph => data_in );
plasoc_gpio_axi4_write_cntrl_inst :
plasoc_gpio_axi4_write_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_enable_bit_loc => axi_control_enable_bit_loc,
reg_control_ack_bit_loc => axi_control_ack_bit_loc,
reg_data_out_offset => axi_data_out_offset_slv )
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
reg_control_enable => reg_control_enable,
reg_control_ack => reg_control_ack,
reg_data_out => reg_data_out );
plasoc_gpio_axi4_read_cntrl_inst :
plasoc_gpio_axi4_read_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_data_in_offset => axi_data_in_offset_slv,
reg_data_out_offset => axi_data_out_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
reg_control => reg_control,
reg_data_in => reg_data_in,
reg_data_out => reg_data_out);
end Behavioral;
|
mit
|
151e9f6b7a1337382db2bee9d1636630
| 0.530281 | 4.340595 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/InstructionMem.vhdl
| 1 | 2,411 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
use work.txt_utils.all;
entity InstructionMem is
generic (SINGLE_ADDRESS_SPACE : boolean := true);
port (
read_addr : in addr_t;
clk : in std_logic;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end InstructionMem;
architecture behav of InstructionMem is
type code_t is array (natural range <>) of instruction_t;
constant example_code : code_t := (
-- <_start>:
X"00000000", -- nop
X"3c1c1000", -- lui gp,0x1000
X"2402001f", -- li v0,31
X"a3820000", -- sb v0,0(gp)
X"24020003", -- li v0,3
X"a3820013", -- sb v0,19(gp)
X"240200ff", -- li v0,255
X"a3820096", -- sb v0,150(gp)
X"2402001c", -- li v0,28
X"a3820118", -- sb v0,280(gp)
X"240200e0", -- li v0,224
X"a382012b", -- sb v0,299(gp)
X"00000000", -- nop
X"3c011400", -- lui at,0x1400
X"3c1a1400", -- lui k0,0x1400
X"375a0002", -- ori k0,k0,0x2
X"83420000", -- lb v0,0(k0)
X"a0220000", -- sb v0,0(at)
X"08000000", -- j 0 <_start>
X"00000000" -- nop
);
begin
use_bus_rom: if SINGLE_ADDRESS_SPACE generate
process(read_addr, top_dout, clk)
begin
if rising_edge(clk) then
instr <= top_dout;
printf("[IMEM] *%s: %s\n", read_addr, top_dout);
top_addr <= read_addr;
top_size <= WIDTH_WORD;
top_wr <= '0';
end if;
end process;
end generate;
use_hardwired_rom: if not SINGLE_ADDRESS_SPACE generate
process(read_addr, clk)
variable instrnum : addr_t;
begin
instrnum := "00" & read_addr(31 downto 2);
if rising_edge(clk) then
instr <= example_code(vtou(instrnum));
printf("[IMEM] %s: %s\n", read_addr, example_code(vtou(instrnum)));
top_wr <= '0';
end if;
end process;
end generate;
end behav;
|
gpl-3.0
|
14f9928322d4fe847a28ce96dbd3ba3e
| 0.501037 | 3.298222 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/vga/sync.vhdl
| 1 | 2,446 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils.all;
entity sync is
port (
clk : in std_logic;
en : in std_logic;
hsync : out std_logic := '1';
vsync : out std_logic := '1';
retracing : out std_logic := '1'; -- maybe we don't need this?
-- Dunno why, but if I zero-initialize these, the very first pixel is black in the bitmap_tb
col : out std_logic_vector (9 downto 0) := (others => '1'); -- 640 = 10_1000_0000b
row : out std_logic_vector (8 downto 0) := (others => '1') -- 480 = 1_1110_0000b
);
end entity sync;
architecture behavioral of sync is
constant h_display : natural := 640;
constant h_front : natural := 20;
constant h_sync : natural := 96;
constant h_back : natural := 44;
constant h_retrace : natural := h_front + h_sync + h_back;
constant h_max : natural := h_retrace + h_display - 1;
constant v_display : natural := 480;
constant v_front : natural := 14;
constant v_sync : natural := 1;
constant v_back : natural := 30;
constant v_retrace : natural := v_front + v_sync + v_back;
constant v_max : natural := v_retrace + v_display - 1;
begin
process(en, clk)
variable h_idx: integer range 0 to h_max := 0;
variable v_idx: integer range 0 to v_max := 0;
variable in_retrace : boolean := true;
begin
if rising_edge(clk) and en = '1' then
if h_idx >= h_max - h_sync then hsync <= '0'; end if;
if v_idx >= v_max - v_sync then vsync <= '0'; end if;
in_retrace := h_idx < h_back - 1 or h_idx > h_display + h_back - 2
or v_idx < v_back or v_idx > v_display + v_back - 1;
retracing <= high_if (in_retrace);
if not in_retrace then
row <= std_logic_vector(to_unsigned(v_idx - v_back, row'length));
col <= std_logic_vector(to_unsigned(h_idx - h_back + 1, col'length));
end if;
if h_idx = h_max then
h_idx := 0;
hsync <= '1';
if v_idx = v_max then
v_idx := 0;
vsync <= '1';
else
v_idx := v_idx + 1;
end if;
else
h_idx := h_idx + 1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
38bbdc5929a49a06711da3eb453b27fc
| 0.511447 | 3.499285 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_mm2s_dre.vhd
| 4 | 87,948 |
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the alignment port widths. The value should be
-- log2(C_DWIDTH)
);
port (
-- Clock and Reset inputs ---------------
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------
-- Alignment Controls ------------------------------------------------
dre_new_align : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Input Stream Interface --------------------------------------------
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Output Stream Interface -------------------------------------------
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_dre;
architecture implementation of axi_datamover_mm2s_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
signal sig_enable_input_rdy : std_logic := '0';
signal sig_input_ready : std_logic := '0';
begin --(architecture implementation)
-- Misc assignments
--dre_in_tready <= sig_input_accept ;
dre_in_tready <= sig_input_ready ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
sig_pipeline_halt <= sig_dre_tvalid_i and not(dre_out_tready);
sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt) and
sig_enable_input_rdy;
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
sig_input_ready;
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
sig_input_ready <= sig_enable_input_rdy and
not(sig_pipeline_halt) and
not(sig_input_flush_stall) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_FLOP
--
-- Process Description:
-- Just a flop for generating an input disable while reset
-- is in progress.
--
-------------------------------------------------------------
IMP_RESET_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_enable_input_rdy <= '0';
else
sig_enable_input_rdy <= '1';
end if;
end if;
end process IMP_RESET_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Register for the flush signal
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal s_case_i_64 : Integer range 0 to 7 := 0;
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
-- signal sig_cntl_state_64 : std_logic_vector(5 downto 0);
-- Signal s_case_i_64 : Integer range 0 to 7;
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0) ,
I0 => sig_input_data_reg(1) ,
I1 => sig_input_data_reg(0) ,
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
signal sig_cntl_state_32 : std_logic_vector(3 downto 0);
Signal s_case_i_32 : Integer range 0 to 3;
Signal sig_shift_case_i : std_logic_vector(1 downto 0);
Signal sig_shift_case_reg : std_logic_vector(1 downto 0);
Signal sig_final_mux_sel : std_logic_vector(3 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
signal sig_cntl_state_16 : std_logic_vector(1 downto 0);
Signal s_case_i_16 : Integer range 0 to 1;
Signal sig_shift_case_i : std_logic;
Signal sig_shift_case_reg : std_logic;
Signal sig_final_mux_sel : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
|
bsd-3-clause
|
307de64f264a615053e1a352995484d5
| 0.368263 | 4.597146 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/mips_harvard_tb.vhdl
| 1 | 5,635 |
-- SKIP because its out of sync with the current code in InstructionMem.vhdl
-- This is the top level MIPS architecture
-- With the instruction memory not mapped on the Data/IO memory bus
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity mips_harvard_tb is
end;
architecture struct of mips_harvard_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
component mem is
generic (ROM : string := "");
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic;
-- VGA I/O
vgaclk, rst : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic;
-- LEDs
leds : out std_logic_vector(7 downto 0);
-- Push buttons
buttons : in std_logic_vector(3 downto 0);
-- DIP Switch IO
switch : in std_logic_vector(7 downto 0)
);
end component;
component cpu is
generic(PC_ADD : natural := 4;
SINGLE_ADDRESS_SPACE : boolean := true);
port(
clk : in std_logic;
rst : in std_logic;
-- Register File
readreg1, readreg2 : out reg_t;
writereg: out reg_t;
regWriteData: out word_t;
regReadData1, regReadData2 : in word_t;
regWrite : out std_logic;
-- Memory
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t;
-- Debug info
instruction : out instruction_t
);
end component;
signal readreg1, readreg2 : reg_t;
signal writereg: reg_t;
signal regWriteData: word_t;
signal regReadData1, regReadData2 : word_t;
signal regWrite : std_logic;
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
signal sysclk : std_logic := '0';
signal regrst : std_logic := '0';
signal rst : std_logic := '0';
signal online : boolean := true;
signal cpu_regWrite : std_logic;
signal cpu_readreg1 : reg_t;
signal cpu_readreg2 : reg_t;
signal test_readreg1 : reg_t;
signal test_readreg2 : reg_t;
alias clk is sysclk;
-- VGA
-- nothing yet
begin
regfile_inst: regFile port map (
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg,
writeData => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => clk,
rst => regrst,
regWrite => regWrite
);
mem_bus: mem
generic map (ROM => "")
port map (
addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
clk => clk,
vgaclk => '0', rst => '1',
r => open, g => open, b => open,
hsync => open, vsync => open,
leds => open,
-- Push buttons
buttons => B"0000",
-- DIP Switch IO
switch => B"1010_1010"
);
cpu_inst: cpu
generic map(SINGLE_ADDRESS_SPACE => false)
port map (
clk => clk,
rst => rst,
-- Register File
readreg1 => cpu_readreg1, readreg2 => cpu_readreg2,
writereg => writereg,
regWriteData => regWriteData,
regReadData1 => regReadData1, regReadData2 => regReadData2,
regWrite => cpu_RegWrite,
-- Memory
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr,
-- Debug info
instruction => open
);
regwrite <= cpu_RegWrite when online else '0';
readreg1 <= cpu_readreg1 when online else test_readreg1;
readreg2 <= cpu_readreg2 when online else test_readreg2;
test: process begin
wait for 4 ns;
rst <= '1';
wait for 4 ns;
rst <= '0';
wait for 4 ns;
wait for 260 ns;
rst <= '0';
online <= false;
wait for 20 ns;
test_readreg1 <= R1;
wait for 8 ns;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "[r1] Failed to ori. 0xF000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
test_readreg1 <= R2;
test_readreg2 <= R1;
wait for 16 ns;
assert regReadData2 = X"0000_F000" report
ANSI_RED & "[r1] Failed to ori. 0xF000 /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
assert regReadData1 = X"0000_FBAD" report
ANSI_RED & "[r2] Failed to ori. 0xFBAD /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
test_readreg1 <= R3;
test_readreg2 <= R4;
wait for 16 ns;
assert regReadData1 = X"A000_0000" report
ANSI_RED & "[r3] 0xA000_0000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
assert regReadData2 = X"FFFF_FFAD" report
ANSI_RED & "[r4] 0xFFFF_FFAD /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
wait;
end process;
clkproc: process begin
sysclk <= not sysclk; wait for 1 ns; if not online then sysclk <= '0'; wait; end if;
end process;
end struct;
|
gpl-3.0
|
4431f76e80f58d43ffe17ccc8d3f71df
| 0.545697 | 3.846416 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/sobel_filter/Video_Box.vhd
| 1 | 10,790 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Alexander West
--
-- Create Date: 03/23/2017
-- Design Name: Sobel filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
--
-- This filter applies the Sobel operator.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library work;
use work.filter_lib.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
C_S_AXI_DATA_WIDTH : integer := 32; -- Width of S_AXI data bus
C_S_AXI_ADDR_WIDTH : integer := 11 -- Width of S_AXI address bus
);
port (
-- AXI interface ports
S_AXI_ARESETN : in std_logic; -- Reset the registers
slv_reg_wren : in std_logic; -- Write enable
slv_reg_rden : in std_logic; -- Read enable
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); -- Selector for writing individual bytes
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- Write Address
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Write Data
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- Read Address
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Read Data
-- Bus Clock
S_AXI_ACLK : in std_logic;
-- Pixel Clock
PIXEL_CLK : in std_logic;
-- Video Input
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0);
-- Video Output
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic -- Veritcal sync signal (optional)
);
end Video_Box;
architecture Behavioral of Video_Box is
-- Bus Constants
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32) + 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH - ADDR_LSB - 1;
-- Video Interface
signal vid_in_reg, vid_mod, vid_out_reg : rgb_interface_t;
signal X_Coord_reg, Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
-- Control/Output Registers
signal slv_reg0, slv_reg1, slv_reg2, slv_reg3 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4, slv_reg5, slv_reg6, slv_reg7 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Buffering
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
vid_in_reg.rgb <= RGB_IN;
vid_in_reg.vde <= VDE_IN;
vid_in_reg.hs <= HS_IN;
vid_in_reg.vs <= VS_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
-- Video Output Signals
vid_out_reg <= vid_mod;
end if;
end process;
-- Module Output
RGB_OUT <= vid_out_reg.rgb;
VDE_OUT <= vid_out_reg.vde;
HS_OUT <= vid_out_reg.hs;
VS_OUT <= vid_out_reg.vs;
-- Filter Module
filter_a : entity work.sobel_filter(Behavioral)
port map (
-- Video Interface
vid_i => vid_in_reg,
vid_o => vid_mod,
-- Pixel Coordinates
x_position => X_Coord_reg,
-- y_in => Y_Coord_reg,
-- Register Inputs
threshold => slv_reg0(7 downto 0),
sensitivity => slv_reg1(3 downto 0),
invert => slv_reg2(0),
split_line => slv_reg3(15 downto 0),
rotoscope => slv_reg4(0),
-- Reference Clock
PIXEL_CLK => PIXEL_CLK
);
-- Register Input Logic
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Register Output Logic
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when b"000000101" =>
reg_data_out <= slv_reg5;
when b"000000110" =>
reg_data_out <= slv_reg6;
when b"000000111" =>
reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End Sobel filter architecture
|
bsd-3-clause
|
f074755dccf549e781b3a5fc6ff7efb2
| 0.507229 | 3.791286 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_indet_btt.vhd
| 4 | 60,724 |
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
Use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
Use axi_datamover_v5_1_9.axi_datamover_stbs_set;
Use axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
bsd-3-clause
|
a011bac210d9cebd31570d2f1c8f90e7
| 0.440979 | 4.658177 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/mlite_cpu.vhd
| 1 | 12,967 |
---------------------------------------------------------------------
-- TITLE: Plasma CPU core
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_cpu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
-- Technologies. MIPS Technologies does not endorse and is not
-- associated with this project.
-- DESCRIPTION:
-- Top level VHDL document that ties the nine other entities together.
--
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
-- memory accesses. Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
--
-- The CPU is implemented as a two or three stage pipeline.
-- An add instruction would take the following steps (see cpu.gif):
-- Stage #0:
-- 1. The "pc_next" entity passes the program counter (PC) to the
-- "mem_ctrl" entity which fetches the opcode from memory.
-- Stage #1:
-- 2. The memory returns the opcode.
-- Stage #2:
-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
-- and sends control signals to the other entities.
-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
-- sends the 32-bit reg_source and reg_target to "bus_mux".
-- 6. Based on the a_source and b_source control signals, "bus_mux"
-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
-- Stage #3 (part of stage #2 if using two stage pipeline):
-- 7. Based on the alu_func control signals, "alu" adds the values
-- from a_bus and b_bus and places the result on c_bus.
-- 8. Based on the c_source control signals, "bus_bux" multiplexes
-- c_bus onto reg_dest.
-- 9. Based on the rd_index control signal, "reg_bank" saves
-- reg_dest into the correct register.
-- Stage #3b:
-- 10. Read or write memory if needed.
--
-- All signals are active high.
-- Here are the signals for writing a character to address 0xffff
-- when using a two stage pipeline:
--
-- Program:
-- addr value opcode
-- =============================
-- 3c: 00000000 nop
-- 40: 34040041 li $a0,0x41
-- 44: 3405ffff li $a1,0xffff
-- 48: a0a40000 sb $a0,0($a1)
-- 4c: 00000000 nop
-- 50: 00000000 nop
--
-- intr_in mem_pause
-- reset_in byte_we Stages
-- ns address data_w data_r 40 44 48 4c 50
-- 3600 0 0 00000040 00000000 34040041 0 0 1
-- 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
-- 3800 0 0 00000048 00000000 A0A40000 0 0 2 1
-- 3900 0 0 0000004C 41414141 00000000 0 0 2 1
-- 4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2
-- 4100 0 0 00000050 00000000 00000000 0 0 1
---------------------------------------------------------------------
library ieee;
use work.mlite_pack.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mlite_cpu is
generic(memory_type : string := "DUAL_PORT_"; --ALTERA_LPM, XILINX_16X, or DUAL_PORT_
mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
architecture logic of mlite_cpu is
--When using a two stage pipeline "sigD <= sig".
--When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
-- so sigD is delayed by one clock cycle.
signal opcode : std_logic_vector(31 downto 0);
signal rs_index : std_logic_vector(5 downto 0);
signal rt_index : std_logic_vector(5 downto 0);
signal rd_index : std_logic_vector(5 downto 0);
signal rd_indexD : std_logic_vector(5 downto 0);
signal reg_source : std_logic_vector(31 downto 0);
signal reg_target : std_logic_vector(31 downto 0);
signal reg_dest : std_logic_vector(31 downto 0);
signal reg_destD : std_logic_vector(31 downto 0);
signal a_bus : std_logic_vector(31 downto 0);
signal a_busD : std_logic_vector(31 downto 0);
signal b_bus : std_logic_vector(31 downto 0);
signal b_busD : std_logic_vector(31 downto 0);
signal c_bus : std_logic_vector(31 downto 0);
signal c_alu : std_logic_vector(31 downto 0);
signal c_shift : std_logic_vector(31 downto 0);
signal c_mult : std_logic_vector(31 downto 0);
signal c_memory : std_logic_vector(31 downto 0);
signal imm : std_logic_vector(15 downto 0);
signal pc_future : std_logic_vector(31 downto 2);
signal pc_current : std_logic_vector(31 downto 2);
signal pc_plus4 : std_logic_vector(31 downto 2);
signal alu_func : alu_function_type;
signal alu_funcD : alu_function_type;
signal shift_func : shift_function_type;
signal shift_funcD : shift_function_type;
signal mult_func : mult_function_type;
signal mult_funcD : mult_function_type;
signal branch_func : branch_function_type;
signal take_branch : std_logic;
signal a_source : a_source_type;
signal b_source : b_source_type;
signal c_source : c_source_type;
signal pc_source : pc_source_type;
signal mem_source : mem_source_type;
signal pause_mult : std_logic;
signal pause_ctrl : std_logic;
signal pause_pipeline : std_logic;
signal pause_any : std_logic;
signal pause_non_ctrl : std_logic;
signal pause_bank : std_logic;
signal nullify_op : std_logic;
signal intr_enable : std_logic;
signal intr_signal : std_logic;
signal exception_sig : std_logic;
signal reset_reg : std_logic_vector(3 downto 0);
signal reset : std_logic;
begin --architecture
pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
or intr_signal = '1' or exception_sig = '1'
else '0';
c_bus <= c_alu or c_shift or c_mult;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
pc_source, pc_current, pause_any)
begin
if reset_in = '1' then
reset_reg <= "0000";
intr_signal <= '0';
elsif rising_edge(clk) then
if reset_reg /= "1111" then
reset_reg <= reset_reg + 1;
end if;
--don't try to interrupt a multi-cycle instruction
if pause_any = '0' then
if intr_in = '1' and intr_enable = '1' and
pc_source = FROM_INC4 then
--the epc will contain pc+4
intr_signal <= '1';
else
intr_signal <= '0';
end if;
end if;
end if;
end process;
u1_pc_next: pc_next PORT MAP (
clk => clk,
reset_in => reset,
take_branch => take_branch,
pause_in => pause_any,
pc_new => c_bus(31 downto 2),
opcode25_0 => opcode(25 downto 0),
pc_source => pc_source,
pc_future => pc_future,
pc_current => pc_current,
pc_plus4 => pc_plus4);
u2_mem_ctrl: mem_ctrl
PORT MAP (
clk => clk,
reset_in => reset,
pause_in => pause_non_ctrl,
nullify_op => nullify_op,
address_pc => pc_future,
opcode_out => opcode,
address_in => c_bus,
mem_source => mem_source,
data_write => reg_target,
data_read => c_memory,
pause_out => pause_ctrl,
address_next => address_next,
byte_we_next => byte_we_next,
address => address,
byte_we => byte_we,
data_w => data_w,
data_r => data_r);
u3_control: control PORT MAP (
opcode => opcode,
intr_signal => intr_signal,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
imm_out => imm,
alu_func => alu_func,
shift_func => shift_func,
mult_func => mult_func,
branch_func => branch_func,
a_source_out => a_source,
b_source_out => b_source,
c_source_out => c_source,
pc_source_out=> pc_source,
mem_source_out=> mem_source,
exception_out=> exception_sig);
u4_reg_bank: reg_bank
generic map(memory_type => memory_type)
port map (
clk => clk,
reset_in => reset,
pause => pause_bank,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_indexD,
reg_source_out => reg_source,
reg_target_out => reg_target,
reg_dest_new => reg_destD,
intr_enable => intr_enable);
u5_bus_mux: bus_mux port map (
imm_in => imm,
reg_source => reg_source,
a_mux => a_source,
a_out => a_bus,
reg_target => reg_target,
b_mux => b_source,
b_out => b_bus,
c_bus => c_bus,
c_memory => c_memory,
c_pc => pc_current,
c_pc_plus4 => pc_plus4,
c_mux => c_source,
reg_dest_out => reg_dest,
branch_func => branch_func,
take_branch => take_branch);
u6_alu: alu
generic map (alu_type => alu_type)
port map (
a_in => a_busD,
b_in => b_busD,
alu_function => alu_funcD,
c_alu => c_alu);
u7_shifter: shifter
generic map (shifter_type => shifter_type)
port map (
value => b_busD,
shift_amount => a_busD(4 downto 0),
shift_func => shift_funcD,
c_shift => c_shift);
u8_mult: mult
generic map (mult_type => mult_type)
port map (
clk => clk,
reset_in => reset,
a => a_busD,
b => b_busD,
mult_func => mult_funcD,
c_mult => c_mult,
pause_out => pause_mult);
pipeline2: if pipeline_stages <= 2 generate
a_busD <= a_bus;
b_busD <= b_bus;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
rd_indexD <= rd_index;
reg_destD <= reg_dest;
pause_pipeline <= '0';
end generate; --pipeline2
pipeline3: if pipeline_stages > 2 generate
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
u9_pipeline: pipeline port map (
clk => clk,
reset => reset,
a_bus => a_bus,
a_busD => a_busD,
b_bus => b_bus,
b_busD => b_busD,
alu_func => alu_func,
alu_funcD => alu_funcD,
shift_func => shift_func,
shift_funcD => shift_funcD,
mult_func => mult_func,
mult_funcD => mult_funcD,
reg_dest => reg_dest,
reg_destD => reg_destD,
rd_index => rd_index,
rd_indexD => rd_indexD,
rs_index => rs_index,
rt_index => rt_index,
pc_source => pc_source,
mem_source => mem_source,
a_source => a_source,
b_source => b_source,
c_source => c_source,
c_bus => c_bus,
pause_any => pause_any,
pause_pipeline => pause_pipeline);
end generate; --pipeline3
end; --architecture logic
|
mit
|
81107365ea34c9151769d40842017a34
| 0.540063 | 3.522684 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_input_buffer/synth/fifo_generator_input_buffer.vhd
| 1 | 39,024 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_input_buffer IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_input_buffer;
ARCHITECTURE fifo_generator_input_buffer_arch OF fifo_generator_input_buffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "fifo_generator_v13_0_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_input_buffer_arch : ARCHITECTURE IS "fifo_generator_input_buffer,fifo_generator_v13_0_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "fifo_generator_input_buffer,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4093,C_PROG_FULL_THRESH_NEGATE_VAL=4092,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4093,
C_PROG_FULL_THRESH_NEGATE_VAL => 4092,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_input_buffer_arch;
|
bsd-3-clause
|
70917f3e8a93e514c0fad02bd5270c68
| 0.629587 | 2.921833 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_timer.vhd
| 1 | 13,756 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 31, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Timer Core.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_timer_pack.all;
--! The Timer Core is developed so that the Plasma-SoC can
--! perform operations reactively to deterministic periods of time. This
--! operation is especially critical in order to run an operating
--! system preemptively. The only goals behind the development of the
--! Timer Core are simplicity and having a Slave AXI4-Lite interface.
--!
--! The operation of the Timer Core is as follows. The address space of the
--! Timer Core defines the registers Control, Trigger Value, and Tick Value.
--! Before starting the Timer Core's operation, the value written to the
--! Trigger Value sets the value to which the Tick Value must reach. Setting the
--! Start bit in the Control register starts the operation of the Timer Core,
--! during which the Tick Value increments every clock cycle until it reaches the Trigger Value.
--! Once the Tick Value equals the Trigger Value, the Done bit and signal is set
--! high until either the Acknowledge bit is set high or the Start bit is set low.
--! The Acknowledge bit is found in the Control register.
--!
--! If the Reload bit is set high, the Tick Value will reset itself back to zero
--! on the clock cycle after reaching the Trigger Value. The Reload bit is found in
--! the Control register. Both the Done bit and the Tick Value register will remain
--! zero if the Start bit is low.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_timer is
generic (
-- Timer Core's parameters.
timer_width : integer := 32; --! Defines the width of the Trigger and Tick Value registers.
-- Slave AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
axi_control_offset : integer := 0; --! For the Control register, defines the offset from axi_base_address.
axi_control_start_bit_loc : integer := 0; --! For the Start bit, defines the bit location in the Control register.
axi_control_reload_bit_loc : integer := 1; --! For the Reload bit, defines the bit location in the Control register.
axi_control_ack_bit_loc : integer := 2; --! For the Acknowledge bit, defines the bit location in the Control register.
axi_control_done_bit_loc : integer := 3; --! For the Done bit, defines the bit location in the Control register.
axi_trig_value_offset : integer := 4; --! For the Trigger Value register, defines the offset from axi_base_address.
axi_tick_value_offset : integer := 8 --! For the Tick Value register, defines the offset from axi_base_address.
);
port (
-- Global interface.
aclk : in std_logic; --! Defines the AXI4-Lite Address Width.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- Timer Core interface.
done : out std_logic --! Done signal.
);
end plasoc_timer;
architecture Behavioral of plasoc_timer is
-- Component declaration.
component plasoc_timer_cntrl is
generic (
timer_width : integer := 16 );
port (
clock : in std_logic;
start : in std_logic;
reload : in std_logic;
ack : in std_logic;
done : out std_logic := '0';
trig_value : in std_logic_vector(timer_width-1 downto 0);
tick_value : out std_logic_vector(timer_width-1 downto 0));
end component;
component plasoc_timer_control_bridge is
generic (
axi_data_width : integer := 32;
timer_width : integer := 16;
start_bit_loc : integer := 0;
reload_bit_loc : integer := 1;
ack_bit_loc : integer := 2;
done_bit_loc : integer := 3);
port (
clock : in std_logic;
nreset : in std_logic;
start : out std_logic := '0';
reload : out std_logic := '0';
ack : out std_logic := '0';
done : in std_logic;
reg_in_valid : in std_logic;
reg_in_control : in std_logic_vector(axi_data_width-1 downto 0);
reg_out_control : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'));
end component;
component plasoc_timer_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_trig_value_offset : std_logic_vector := X"0004");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
reg_control : out std_logic_vector(axi_data_width-1 downto 0);
reg_trig_value : out std_logic_vector(axi_data_width-1 downto 0);
reg_valid : out std_logic := '0');
end component;
component plasoc_timer_axi4_read_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_trig_value_offset : std_logic_vector := X"0004";
reg_tick_value_offset : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
reg_control : in std_logic_vector(axi_data_width-1 downto 0);
reg_trig_value : in std_logic_vector(axi_data_width-1 downto 0);
reg_tick_value : in std_logic_vector(axi_data_width-1 downto 0));
end component;
-- constant declarations.
constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width));
constant axi_trig_value_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_trig_value_offset,axi_address_width));
constant axi_tick_value_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_tick_value_offset,axi_address_width));
-- signal declarations.
signal start : std_logic;
signal reload : std_logic;
signal ack : std_logic;
signal done_buff : std_logic;
signal reg_valid : std_logic;
signal reg_write_control : std_logic_vector(axi_data_width-1 downto 0);
signal reg_read_control : std_logic_vector(axi_data_width-1 downto 0);
signal reg_trig_value : std_logic_vector(axi_data_width-1 downto 0);
signal reg_tick_value : std_logic_vector(axi_data_width-1 downto 0);
begin
done <= done_buff;
-- Timer controller instantiation.
plasoc_timer_cntrl_inst :
plasoc_timer_cntrl
generic map (
timer_width => timer_width )
port map (
clock => aclk,
start => start,
reload => reload,
ack => ack,
done => done_buff,
trig_value => reg_trig_value(timer_width-1 downto 0),
tick_value => reg_tick_value(timer_width-1 downto 0));
-- Timer control Bridge instantiation.
plasoc_timer_control_bridge_inst :
plasoc_timer_control_bridge
generic map (
axi_data_width => axi_data_width,
timer_width => timer_width,
start_bit_loc => axi_control_start_bit_loc,
reload_bit_loc => axi_control_reload_bit_loc,
ack_bit_loc => axi_control_ack_bit_loc,
done_bit_loc => axi_control_done_bit_loc)
port map (
clock => aclk,
nreset => aresetn,
start => start,
reload => reload,
ack => ack,
done => done_buff,
reg_in_valid => reg_valid,
reg_in_control => reg_write_control,
reg_out_control => reg_read_control);
-- Axi write controller.
plasoc_timer_axi4_write_cntrl_inst :
plasoc_timer_axi4_write_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_trig_value_offset => axi_trig_value_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
reg_control => reg_write_control,
reg_trig_value => reg_trig_value,
reg_valid => reg_valid);
-- Axi read controller.
plasoc_timer_axi4_read_cntrl_int :
plasoc_timer_axi4_read_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_trig_value_offset => axi_trig_value_offset_slv,
reg_tick_value_offset => axi_tick_value_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
reg_control => reg_read_control,
reg_trig_value => reg_trig_value,
reg_tick_value => reg_tick_value);
end Behavioral;
|
mit
|
776bd00fe35bb4fecf9a4b0c6f52fab0
| 0.554885 | 4.178615 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_int_pack.vhd
| 1 | 3,856 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Interrupt Controller. Please refer to the documentation
--! in plasoc_int.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_int_pack is
-- Default Interrupt Controller parameters. These values are modifiable. If these parameters are
-- modified, though, modifications will also be necessary for the corresponding header file.
constant default_interrupt_total : integer := 8; --! Defines the default number of available device interrupts.
constant default_int_id_offset : integer := 4; --! For the Interrupt Identifier register, defines the default offset from the Interrupt Controller's axi_base_address.
constant default_int_enables_offset : integer := 0; --! For the Interrupt Enables register, defines the default offset from the instantiations's base address.
constant default_int_active_address : integer := 8; --! For the Interrupt Active register, defines the default offset from the instantiations's base address.
constant axi_resp_okay : std_logic_vector := "00";
-- Function declarations.
function clogb2(bit_depth : in integer ) return integer;
-- Component declaration.
component plasoc_int is
generic(
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_int_id_offset : integer := default_int_id_offset;
axi_int_enables_offset : integer := default_int_enables_offset;
axi_int_active_offset : integer := default_int_active_address;
interrupt_total : integer := default_interrupt_total);
port(
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
cpu_int : out std_logic;
dev_ints : in std_logic_vector(interrupt_total-1 downto 0));
end component;
end;
package body plasoc_int_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
187b23c3bdc906b969b809bfb1ac6153
| 0.607884 | 4.115261 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP_Bonus_feu_rouge/L3TP5/fsm_travaux.vhd
| 1 | 2,448 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:38:51 10/03/2014
-- Design Name:
-- Module Name: fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm is
Port ( clk : in STD_LOGIC;
cpt : in STD_LOGIC_VECTOR (3 downto 0);
travaux : in STD_LOGIC;
reset_cpt : out STD_LOGIC;
Led : out STD_LOGIC_VECTOR (7 downto 0));
end fsm;
architecture Behavioral of fsm is
signal Led_i : STD_LOGIC_VECTOR (7 downto 0);
signal cpt : STD_LOGIC_VECTOR (3 downto 0);
signal reset_cpt_i : STD_LOGIC;
type state_type is (RV, RO, VR, ORE,ORANGE_ON, ORANGE_OFF);
signal state, next_state: state_type;
begin
Next_ouptut : process (state)
begin
-- init des tous les signaux inter..
Led_i <="11111111";
reset_cpt <='0';
case state is
when RV =>
Led_i<="10000001";
when RO =>
reset_cpt <='1';
Led_i<="10000010";
when VR =>
Led_i<="00100100";
when ORE =>
Led_i <="01000001";
when ORANGE_ON =>
Led_i<="01000010";
when ORANGE_OFF =>
Led_i<="00000000";
when others =>
Led_i<="10100101";
end case;
end process;
synchro : process (clk)
begin
if clk'event and clk='1' then
-- changement d etat
state <=next_state;
-- mise a jour des ports de sortie
Led <=Led_i;
reset_cpt<=reset_cpt_i;
end if;
end process;
next_node : process (state)
begin
next_state<=state;
case state is
when RV =>
if travaux ='1' then
next_state<= ORANGE_ON;
else
next_state<=RO;
end if;
when RO =>
next_state<=VR;
when VR =>
if cpt='0110' then
next_state<=ORE;
else
next_state<=VR;
end if;
when ORE =>
next_state<=RV;
when ORANGE_ON =>
if travaux = '0' then
next_state<=RO;
else
next_state<=ORANGE_OFF;
end if;
when ORANGE_OFF =>
next_state<=ORANGE_ON;
when others =>
next_state<=RV;
end case;
end process;
end Behavioral;
|
gpl-2.0
|
26c0899272dd4dcb8c7ee625303cfaeb
| 0.607026 | 3.14653 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_crossbar_pack.vhd
| 1 | 12,087 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Crossbar Core. Please refer to the documentation
--! in plasoc_crossbar.vhd for more information. Also, keep
--! in mind that this core should not be utilized directly.
--! Instead, a wrapper should be generated from gencross.py.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package plasoc_crossbar_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_crossbar is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_master_amount : integer := 2;
axi_slave_id_width : integer := 2;
axi_slave_amount : integer := 4;
axi_master_base_address : std_logic_vector := X"4000000000000000";
axi_master_high_address : std_logic_vector := X"ffffffff3fffffff"
);
port (
aclk : in std_logic;
aresetn : in std_logic;
s_address_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0);
s_data_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0);
s_response_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0);
s_address_read_connected : out std_logic_vector(axi_slave_amount-1 downto 0);
s_data_read_connected : out std_logic_vector(axi_slave_amount-1 downto 0);
m_address_write_connected : out std_logic_vector(axi_master_amount-1 downto 0);
m_data_write_connected : out std_logic_vector(axi_master_amount-1 downto 0);
m_response_write_connected : out std_logic_vector(axi_master_amount-1 downto 0);
m_address_read_connected : out std_logic_vector(axi_master_amount-1 downto 0);
m_data_read_connected : out std_logic_vector(axi_master_amount-1 downto 0);
s_axi_awid : in std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
s_axi_awlen : in std_logic_vector(axi_slave_amount*8-1 downto 0);
s_axi_awsize : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_awburst : in std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_awlock : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_awcache : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awprot : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_awqos : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awregion : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_awready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wdata : in std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
s_axi_wlast : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bid : out std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_bresp : out std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_bvalid : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arid : in std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
s_axi_arlen : in std_logic_vector(axi_slave_amount*8-1 downto 0);
s_axi_arsize : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_arburst : in std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_arlock : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arcache : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arprot : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_arqos : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arregion : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rid : out std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_rdata : out std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_rlast : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rvalid : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_awid : out std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_awaddr : out std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
m_axi_awlen : out std_logic_vector(axi_master_amount*8-1 downto 0);
m_axi_awsize : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_awburst : out std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_awlock : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_awcache : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awprot : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_awqos : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awregion : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_awready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wdata : out std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
m_axi_wstrb : out std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
m_axi_wlast : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bid : in std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_bresp : in std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_bvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bready : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arid : out std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_araddr : out std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
m_axi_arlen : out std_logic_vector(axi_master_amount*8-1 downto 0);
m_axi_arsize : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_arburst : out std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_arlock : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arcache : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arprot : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_arqos : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arregion : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rid : in std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_rdata : in std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
m_axi_rresp : in std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_rlast : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rready : out std_logic_vector(axi_master_amount*1-1 downto 0));
end component;
end package;
package body plasoc_crossbar_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
d4d631c644196373158089f5d1438902
| 0.486556 | 4.186699 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_crossbar_axi4_write_cntrl.vhd
| 1 | 13,814 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Crossbar's Write Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.all;
entity plasoc_crossbar_axi4_write_cntrl is
generic (
axi_slave_amount : integer := 2;
axi_master_amount : integer := 4);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_write_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0);
axi_write_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0);
axi_address_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_data_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_response_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
s_axi_awvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wlast : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_awready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bvalid : in std_logic_vector(axi_master_amount*1-1 downto 0));
end plasoc_crossbar_axi4_write_cntrl;
architecture Behavioral of plasoc_crossbar_axi4_write_cntrl is
constant axi_slave_iden_width : integer := clogb2(axi_slave_amount);
constant axi_master_iden_width : integer := clogb2(axi_master_amount);
function reduce_enables_master(
enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable or_reduced : std_logic;
variable reduce_enables : std_logic_vector(axi_master_amount-1 downto 0);
begin
for each_master in 0 to axi_master_amount-1 loop
or_reduced := '0';
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount);
end loop;
reduce_enables(each_master) := or_reduced;
end loop;
return reduce_enables;
end;
function get_slave_handshakes (
valid : in std_logic_vector(axi_slave_amount-1 downto 0);
ready : in std_logic_vector(axi_master_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0) )
return std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
begin
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if valid(each_slave)='1' and ready(master_iden_buff)='1' then
slave_handshakes(each_slave) := '1';
end if;
end loop;
return slave_handshakes;
end;
function get_slave_permissions (
slave_valid : in std_logic_vector(axi_slave_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
reduced_data_enables : in std_logic_vector(axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
begin
for each_master in 0 to axi_master_amount-1 loop
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if each_master=master_iden_buff and slave_valid(each_slave)='1' and reduced_data_enables(master_iden_buff)='0' then
slave_permissions(each_slave) := '1';
exit;
end if;
end loop;
end loop;
return slave_permissions;
end;
function set_slave_enables_ff(
slave_permissions : in std_logic_vector(axi_slave_amount-1 downto 0);
slave_handshakes : in std_logic_vector(axi_slave_amount-1 downto 0);
slave_last : in std_logic_vector(axi_slave_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
slave_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
begin
slave_enables_buff := slave_enables;
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if slave_permissions(each_slave)='1' then
slave_enables_buff(each_slave+master_iden_buff*axi_slave_amount) := '1';
elsif slave_handshakes(each_slave)='1' and slave_last(each_slave)='1' then
for each_master in 0 to axi_master_amount-1 loop
slave_enables_buff(each_slave+each_master*axi_slave_amount) := '0';
end loop;
--slave_enables_buff(each_slave+master_iden_buff*axi_slave_amount) := '0';
end if;
end loop;
return slave_enables_buff;
end;
function reduce_enables_slave(
enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable or_reduced : std_logic;
variable reduce_enables : std_logic_vector(axi_slave_amount-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := '0';
for each_master in 0 to axi_master_amount-1 loop
or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount);
end loop;
reduce_enables(each_slave) := or_reduced;
end loop;
return reduce_enables;
end;
function get_master_handshakes (
valid : in std_logic_vector(axi_master_amount-1 downto 0);
ready : in std_logic_vector(axi_slave_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0) )
return std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if valid(each_master)='1' and ready(slave_iden_buff)='1' then
master_handshakes(each_master) := '1';
end if;
end loop;
return master_handshakes;
end;
function get_master_permissions (
master_valid : in std_logic_vector(axi_master_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
reduced_response_enables : in std_logic_vector(axi_slave_amount-1 downto 0) ) return
std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
for each_slave in 0 to axi_slave_amount-1 loop
if each_slave=slave_iden_buff and master_valid(each_master)='1' and reduced_response_enables(slave_iden_buff)='0' then
master_permissions(each_master) := '1';
exit;
end if;
end loop;
end loop;
return master_permissions;
end;
function set_master_enables_ff (
master_permissions : in std_logic_vector(axi_master_amount-1 downto 0);
master_handshakes : in std_logic_vector(axi_master_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
master_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
begin
master_enables_buff := master_enables;
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if master_permissions(each_master)='1' then
master_enables_buff(slave_iden_buff+each_master*axi_slave_amount) := '1';
elsif master_handshakes(each_master)='1' then
for each_slave in 0 to axi_slave_amount-1 loop
master_enables_buff(each_slave+each_master*axi_slave_amount) := '0';
end loop;
end if;
end loop;
return master_enables_buff;
end;
signal address_slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal data_slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal axi_address_write_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0');
signal axi_data_write_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0');
signal reduced_data_write_enables : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
signal slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal response_master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
signal axi_response_write_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0');
signal reduced_response_write_enables : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
axi_address_write_enables <= axi_address_write_enables_buff;
axi_data_write_enables <= axi_data_write_enables_buff;
axi_response_write_enables <= axi_response_write_enables_buff;
process (s_axi_awvalid,m_axi_awready,axi_write_master_iden)
begin
address_slave_handshakes <= get_slave_handshakes(s_axi_awvalid,m_axi_awready,axi_write_master_iden);
end process;
process (s_axi_wvalid,m_axi_wready,axi_write_master_iden)
begin
data_slave_handshakes <= get_slave_handshakes(s_axi_wvalid,m_axi_wready,axi_write_master_iden);
end process;
process (axi_data_write_enables_buff)
begin
reduced_data_write_enables <= reduce_enables_master(axi_data_write_enables_buff);
end process;
process (s_axi_awvalid,axi_write_master_iden,reduced_data_write_enables)
begin
slave_permissions <= get_slave_permissions(s_axi_awvalid,axi_write_master_iden,reduced_data_write_enables);
end process;
process (m_axi_bvalid,s_axi_bready,axi_write_slave_iden)
begin
response_master_handshakes <= get_master_handshakes(m_axi_bvalid,s_axi_bready,axi_write_slave_iden);
end process;
process (axi_response_write_enables_buff)
begin
reduced_response_write_enables <= reduce_enables_slave(axi_response_write_enables_buff);
end process;
process (m_axi_bvalid,axi_write_slave_iden,reduced_response_write_enables)
begin
master_permissions <= get_master_permissions(m_axi_bvalid,axi_write_slave_iden,reduced_response_write_enables);
end process;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_address_write_enables_buff <= (others=>'0');
axi_data_write_enables_buff <= (others=>'0');
axi_response_write_enables_buff <= (others=>'0');
else
axi_address_write_enables_buff <= set_slave_enables_ff(slave_permissions,address_slave_handshakes,(others=>'1'),axi_write_master_iden,axi_address_write_enables_buff);
axi_data_write_enables_buff <= set_slave_enables_ff(slave_permissions,data_slave_handshakes,s_axi_wlast,axi_write_master_iden,axi_data_write_enables_buff);
axi_response_write_enables_buff <= set_master_enables_ff(master_permissions,response_master_handshakes,axi_write_slave_iden,axi_response_write_enables_buff);
end if;
end if;
end process;
end Behavioral;
|
mit
|
ff32d1bb5b7d7097939e212e9a9108c4
| 0.641668 | 3.606789 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_sim_netlist.vhdl
| 1 | 32,481 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_sim_netlist.vhdl
-- Design : mig_wrap_proc_sys_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_cdc_sync : entity is "cdc_sync";
end mig_wrap_proc_sys_reset_0_0_cdc_sync;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_cdc_sync_0 : entity is "cdc_sync";
end mig_wrap_proc_sys_reset_0_0_cdc_sync_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_upcnt_n : entity is "upcnt_n";
end mig_wrap_proc_sys_reset_0_0_upcnt_n;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_lpf : entity is "lpf";
end mig_wrap_proc_sys_reset_0_0_lpf;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.mig_wrap_proc_sys_reset_0_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.mig_wrap_proc_sys_reset_0_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => Q,
I2 => lpf_exr,
I3 => lpf_asr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_sequence_psr : entity is "sequence_psr";
end mig_wrap_proc_sys_reset_0_0_sequence_psr;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.mig_wrap_proc_sys_reset_0_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "virtex7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mig_wrap_proc_sys_reset_0_0_proc_sys_reset : entity is "proc_sys_reset";
end mig_wrap_proc_sys_reset_0_0_proc_sys_reset;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.mig_wrap_proc_sys_reset_0_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.mig_wrap_proc_sys_reset_0_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mig_wrap_proc_sys_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mig_wrap_proc_sys_reset_0_0 : entity is "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mig_wrap_proc_sys_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mig_wrap_proc_sys_reset_0_0 : entity is "proc_sys_reset,Vivado 2016.4";
end mig_wrap_proc_sys_reset_0_0;
architecture STRUCTURE of mig_wrap_proc_sys_reset_0_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.mig_wrap_proc_sys_reset_0_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
mit
|
3bd6a7474622641ee61afb9be1b82e9f
| 0.573289 | 2.857482 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/bus_mux.vhd
| 16 | 4,157 |
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
mit
|
cd55dd8fcd8e988cf6df7af4870dc20a
| 0.562665 | 3.215004 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_s2mm_scatter.vhd
| 4 | 69,142 |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
use axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr_dup <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
--HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
--begin
SLICE_INSERTION : entity axi_datamover_v5_1_9.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
--end generate HIGHER_DATAWIDTH;
--LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
--begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
-- I_TSTRB_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
-- generic map (
--
-- C_DWIDTH => TSTRB_FIFO_DWIDTH ,
-- C_DEPTH => TSTRB_FIFO_DEPTH ,
-- C_IS_ASYNC => USE_SYNC_FIFO ,
-- C_PRIM_TYPE => FIFO_PRIM ,
-- C_FAMILY => C_FAMILY
--
-- )
-- port map (
--
-- -- Write Clock and reset
-- fifo_wr_reset => sig_clr_tstrb_fifo ,
-- fifo_wr_clk => primary_aclk ,
--
-- -- Write Side
-- fifo_wr_tvalid => sig_tstrb_fifo_valid ,
-- fifo_wr_tready => sig_tstrb_fifo_rdy ,
-- fifo_wr_tdata => sig_tstrb_fifo_data_in,
-- fifo_wr_full => open ,
--
--
-- -- Read Clock and reset
-- fifo_async_rd_reset => mmap_reset ,
-- fifo_async_rd_clk => primary_aclk ,
--
-- -- Read Side
-- fifo_rd_tvalid => sig_tstrb_valid ,
-- fifo_rd_tready => sig_get_tstrb ,
-- fifo_rd_tdata => sig_tstrb_fifo_data_out ,
-- fifo_rd_empty => sig_tstrb_fifo_empty
--
-- );
--
--
--end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
bsd-3-clause
|
fae83ce93a605551d27883a2326e2b0a
| 0.436941 | 4.719268 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/plasoc_0_crossbar_wrap_pack.vhd
| 2 | 23,799 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_0_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 8;
axi_slave_amount : integer := 2;
axi_master_base_address : std_logic_vector := X"44a5000044a4000044a3000044a2000044a1000044a000000100000000000000";
axi_master_high_address : std_logic_vector := X"44a5ffff44a4ffff44a3ffff44a2ffff44a1ffff44a0ffff0103ffff0000ffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
cdma_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_awlen : in std_logic_vector(7 downto 0);
cdma_s_axi_awsize : in std_logic_vector(2 downto 0);
cdma_s_axi_awburst : in std_logic_vector(1 downto 0);
cdma_s_axi_awlock : in std_logic;
cdma_s_axi_awcache : in std_logic_vector(3 downto 0);
cdma_s_axi_awprot : in std_logic_vector(2 downto 0);
cdma_s_axi_awqos : in std_logic_vector(3 downto 0);
cdma_s_axi_awregion : in std_logic_vector(3 downto 0);
cdma_s_axi_awvalid : in std_logic;
cdma_s_axi_awready : out std_logic;
cdma_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cdma_s_axi_wlast : in std_logic;
cdma_s_axi_wvalid : in std_logic;
cdma_s_axi_wready : out std_logic;
cdma_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_bresp : out std_logic_vector(1 downto 0);
cdma_s_axi_bvalid : out std_logic;
cdma_s_axi_bready : in std_logic;
cdma_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cdma_s_axi_arlen : in std_logic_vector(7 downto 0);
cdma_s_axi_arsize : in std_logic_vector(2 downto 0);
cdma_s_axi_arburst : in std_logic_vector(1 downto 0);
cdma_s_axi_arlock : in std_logic;
cdma_s_axi_arcache : in std_logic_vector(3 downto 0);
cdma_s_axi_arprot : in std_logic_vector(2 downto 0);
cdma_s_axi_arqos : in std_logic_vector(3 downto 0);
cdma_s_axi_arregion : in std_logic_vector(3 downto 0);
cdma_s_axi_arvalid : in std_logic;
cdma_s_axi_arready : out std_logic;
cdma_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cdma_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_s_axi_rresp : out std_logic_vector(1 downto 0);
cdma_s_axi_rlast : out std_logic;
cdma_s_axi_rvalid : out std_logic;
cdma_s_axi_rready : in std_logic;
bram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_awlen : out std_logic_vector(7 downto 0);
bram_m_axi_awsize : out std_logic_vector(2 downto 0);
bram_m_axi_awburst : out std_logic_vector(1 downto 0);
bram_m_axi_awlock : out std_logic;
bram_m_axi_awcache : out std_logic_vector(3 downto 0);
bram_m_axi_awprot : out std_logic_vector(2 downto 0);
bram_m_axi_awqos : out std_logic_vector(3 downto 0);
bram_m_axi_awregion : out std_logic_vector(3 downto 0);
bram_m_axi_awvalid : out std_logic;
bram_m_axi_awready : in std_logic;
bram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
bram_m_axi_wlast : out std_logic;
bram_m_axi_wvalid : out std_logic;
bram_m_axi_wready : in std_logic;
bram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_bresp : in std_logic_vector(1 downto 0);
bram_m_axi_bvalid : in std_logic;
bram_m_axi_bready : out std_logic;
bram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
bram_m_axi_arlen : out std_logic_vector(7 downto 0);
bram_m_axi_arsize : out std_logic_vector(2 downto 0);
bram_m_axi_arburst : out std_logic_vector(1 downto 0);
bram_m_axi_arlock : out std_logic;
bram_m_axi_arcache : out std_logic_vector(3 downto 0);
bram_m_axi_arprot : out std_logic_vector(2 downto 0);
bram_m_axi_arqos : out std_logic_vector(3 downto 0);
bram_m_axi_arregion : out std_logic_vector(3 downto 0);
bram_m_axi_arvalid : out std_logic;
bram_m_axi_arready : in std_logic;
bram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
bram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
bram_m_axi_rresp : in std_logic_vector(1 downto 0);
bram_m_axi_rlast : in std_logic;
bram_m_axi_rvalid : in std_logic;
bram_m_axi_rready : out std_logic;
ram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_awlen : out std_logic_vector(7 downto 0);
ram_m_axi_awsize : out std_logic_vector(2 downto 0);
ram_m_axi_awburst : out std_logic_vector(1 downto 0);
ram_m_axi_awlock : out std_logic;
ram_m_axi_awcache : out std_logic_vector(3 downto 0);
ram_m_axi_awprot : out std_logic_vector(2 downto 0);
ram_m_axi_awqos : out std_logic_vector(3 downto 0);
ram_m_axi_awregion : out std_logic_vector(3 downto 0);
ram_m_axi_awvalid : out std_logic;
ram_m_axi_awready : in std_logic;
ram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ram_m_axi_wlast : out std_logic;
ram_m_axi_wvalid : out std_logic;
ram_m_axi_wready : in std_logic;
ram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_bresp : in std_logic_vector(1 downto 0);
ram_m_axi_bvalid : in std_logic;
ram_m_axi_bready : out std_logic;
ram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_arlen : out std_logic_vector(7 downto 0);
ram_m_axi_arsize : out std_logic_vector(2 downto 0);
ram_m_axi_arburst : out std_logic_vector(1 downto 0);
ram_m_axi_arlock : out std_logic;
ram_m_axi_arcache : out std_logic_vector(3 downto 0);
ram_m_axi_arprot : out std_logic_vector(2 downto 0);
ram_m_axi_arqos : out std_logic_vector(3 downto 0);
ram_m_axi_arregion : out std_logic_vector(3 downto 0);
ram_m_axi_arvalid : out std_logic;
ram_m_axi_arready : in std_logic;
ram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_rresp : in std_logic_vector(1 downto 0);
ram_m_axi_rlast : in std_logic;
ram_m_axi_rvalid : in std_logic;
ram_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
gpio_m_axi_awlock : out std_logic;
gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
gpio_m_axi_awvalid : out std_logic;
gpio_m_axi_awready : in std_logic;
gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
gpio_m_axi_wlast : out std_logic;
gpio_m_axi_wvalid : out std_logic;
gpio_m_axi_wready : in std_logic;
gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
gpio_m_axi_bvalid : in std_logic;
gpio_m_axi_bready : out std_logic;
gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
gpio_m_axi_arlock : out std_logic;
gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
gpio_m_axi_arvalid : out std_logic;
gpio_m_axi_arready : in std_logic;
gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
gpio_m_axi_rlast : in std_logic;
gpio_m_axi_rvalid : in std_logic;
gpio_m_axi_rready : out std_logic;
cdma_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_awlen : out std_logic_vector(7 downto 0);
cdma_m_axi_awsize : out std_logic_vector(2 downto 0);
cdma_m_axi_awburst : out std_logic_vector(1 downto 0);
cdma_m_axi_awlock : out std_logic;
cdma_m_axi_awcache : out std_logic_vector(3 downto 0);
cdma_m_axi_awprot : out std_logic_vector(2 downto 0);
cdma_m_axi_awqos : out std_logic_vector(3 downto 0);
cdma_m_axi_awregion : out std_logic_vector(3 downto 0);
cdma_m_axi_awvalid : out std_logic;
cdma_m_axi_awready : in std_logic;
cdma_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cdma_m_axi_wlast : out std_logic;
cdma_m_axi_wvalid : out std_logic;
cdma_m_axi_wready : in std_logic;
cdma_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_bresp : in std_logic_vector(1 downto 0);
cdma_m_axi_bvalid : in std_logic;
cdma_m_axi_bready : out std_logic;
cdma_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cdma_m_axi_arlen : out std_logic_vector(7 downto 0);
cdma_m_axi_arsize : out std_logic_vector(2 downto 0);
cdma_m_axi_arburst : out std_logic_vector(1 downto 0);
cdma_m_axi_arlock : out std_logic;
cdma_m_axi_arcache : out std_logic_vector(3 downto 0);
cdma_m_axi_arprot : out std_logic_vector(2 downto 0);
cdma_m_axi_arqos : out std_logic_vector(3 downto 0);
cdma_m_axi_arregion : out std_logic_vector(3 downto 0);
cdma_m_axi_arvalid : out std_logic;
cdma_m_axi_arready : in std_logic;
cdma_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cdma_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cdma_m_axi_rresp : in std_logic_vector(1 downto 0);
cdma_m_axi_rlast : in std_logic;
cdma_m_axi_rvalid : in std_logic;
cdma_m_axi_rready : out std_logic;
uart_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_awlen : out std_logic_vector(7 downto 0);
uart_m_axi_awsize : out std_logic_vector(2 downto 0);
uart_m_axi_awburst : out std_logic_vector(1 downto 0);
uart_m_axi_awlock : out std_logic;
uart_m_axi_awcache : out std_logic_vector(3 downto 0);
uart_m_axi_awprot : out std_logic_vector(2 downto 0);
uart_m_axi_awqos : out std_logic_vector(3 downto 0);
uart_m_axi_awregion : out std_logic_vector(3 downto 0);
uart_m_axi_awvalid : out std_logic;
uart_m_axi_awready : in std_logic;
uart_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
uart_m_axi_wlast : out std_logic;
uart_m_axi_wvalid : out std_logic;
uart_m_axi_wready : in std_logic;
uart_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_bresp : in std_logic_vector(1 downto 0);
uart_m_axi_bvalid : in std_logic;
uart_m_axi_bready : out std_logic;
uart_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_arlen : out std_logic_vector(7 downto 0);
uart_m_axi_arsize : out std_logic_vector(2 downto 0);
uart_m_axi_arburst : out std_logic_vector(1 downto 0);
uart_m_axi_arlock : out std_logic;
uart_m_axi_arcache : out std_logic_vector(3 downto 0);
uart_m_axi_arprot : out std_logic_vector(2 downto 0);
uart_m_axi_arqos : out std_logic_vector(3 downto 0);
uart_m_axi_arregion : out std_logic_vector(3 downto 0);
uart_m_axi_arvalid : out std_logic;
uart_m_axi_arready : in std_logic;
uart_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_rresp : in std_logic_vector(1 downto 0);
uart_m_axi_rlast : in std_logic;
uart_m_axi_rvalid : in std_logic;
uart_m_axi_rready : out std_logic;
timer_extra_0_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_awlock : out std_logic;
timer_extra_0_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_awvalid : out std_logic;
timer_extra_0_m_axi_awready : in std_logic;
timer_extra_0_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_extra_0_m_axi_wlast : out std_logic;
timer_extra_0_m_axi_wvalid : out std_logic;
timer_extra_0_m_axi_wready : in std_logic;
timer_extra_0_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_bvalid : in std_logic;
timer_extra_0_m_axi_bready : out std_logic;
timer_extra_0_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_extra_0_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_extra_0_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_extra_0_m_axi_arlock : out std_logic;
timer_extra_0_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_extra_0_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_extra_0_m_axi_arvalid : out std_logic;
timer_extra_0_m_axi_arready : in std_logic;
timer_extra_0_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_extra_0_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_extra_0_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_extra_0_m_axi_rlast : in std_logic;
timer_extra_0_m_axi_rvalid : in std_logic;
timer_extra_0_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_0_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
b4c2ede24d20058fbf1ed7a3f4c04b7d
| 0.675743 | 2.460099 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_afifo_autord.vhd
| 4 | 17,927 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_cdc_v1_0_2;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
ASYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
end generate ASYNC_CDC_SYNC;
SYNC_CDC_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
AFIFO_Ainit_d2 <= AFIFO_Ainit;
end generate SYNC_CDC_SYNC;
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
bsd-3-clause
|
cdb881acb176e26790af9f3849786af3
| 0.475874 | 4.070618 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/jump_pack.vhd
| 2 | 792 |
library ieee;
use ieee.std_logic_1164.all;
package jump_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 10;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body jump_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C080100";
ram_buffer(1) := X"35080000";
ram_buffer(2) := X"01000008";
ram_buffer(3) := X"00000000";
ram_buffer(4) := X"00000100";
ram_buffer(5) := X"01010001";
ram_buffer(6) := X"00000000";
ram_buffer(7) := X"00000000";
ram_buffer(8) := X"00000000";
ram_buffer(9) := X"00000000";
return ram_buffer;
end;
end;
|
mit
|
f85e8d6f2819a29eaace27d12dca587e
| 0.665404 | 2.703072 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Pdashofkplusone.vhd
| 1 | 3,104 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Pdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Q : in std_logic_vector(31 downto 0);
Pdashofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Pdashofkplusone;
architecture struct of k_ukf_Pdashofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkofzero,
datab => Vactcapdashofkplusone,
result => Z1);
M2 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkofone,
datab => Vactcapdashofkplusone,
result => Z4);
M3 : k_ukf_sub port map
( clock => clock,
dataa => Vsigactofkoftwo,
datab => Vactcapdashofkplusone,
result => Z7);
M4 : k_ukf_mult port map
( clock => clock,
dataa => Z1,
datab => Z1,
result => Z2);
M5 : k_ukf_mult port map
( clock => clock,
dataa => Z4,
datab => Z4,
result => Z5);
M6 : k_ukf_mult port map
( clock => clock,
dataa => Z7,
datab => Z7,
result => Z8);
M7 : k_ukf_mult port map
( clock => clock,
dataa => Z2,
datab => Wofcofzero,
result => Z3);
M8 : k_ukf_mult port map
( clock => clock,
dataa => Z5,
datab => Wofcofone,
result => Z6);
M9 : k_ukf_mult port map
( clock => clock,
dataa => Z8,
datab => Wofcoftwo,
result => Z9);
M10 : k_ukf_add port map
( clock => clock,
dataa => Z3,
datab => Z6,
result => Z10);
M11 : k_ukf_add port map
( clock => clock,
dataa => Z10,
datab => Z9,
result => Z11);
M12 : k_ukf_add port map
( clock => clock,
dataa => Q,
datab => Z11,
result => Pdashofkplusone);
end struct;
|
gpl-2.0
|
5d39d310b2c5fbf172b722bc2894697e
| 0.551869 | 3.243469 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_cmd_status.vhd
| 4 | 20,356 |
-------------------------------------------------------------------------------
-- axi_datamover_cmd_status.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
Use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_cmd_status;
architecture implementation of axi_datamover_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
CACHE_ENABLE : if C_ENABLE_CACHE_USER = 1 generate
begin
I_CACHE_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
end generate;
CACHE_DISABLE : if C_ENABLE_CACHE_USER = 0 generate
begin
cache2mstr_command <= (others => '0');
end generate CACHE_DISABLE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
bsd-3-clause
|
84c8f125b51bc575c1bdf7dfa987ffbe
| 0.424199 | 4.938379 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_receive_transmit_reg.vhd
| 2 | 16,493 |
-------------------------------------------------------------------------------
-- qspi_receive_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_receive_reg.vhd
-- Version: v3.0
-- Description: Quad Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Bus2IP_Reg_RdCE -- Read CE for receive register
-- IP2Bus_RdAck_sa -- IP2Bus read acknowledgement
-- IP2Bus_Receive_Reg_Data -- Data to be send on the bus
-- Receive_ip2bus_error -- Receive register error signal
-- SPI MODULE INTERFACE
-- DRR_Overrun -- DRR Overrun bit
-- SR_7_Rx_Empty -- Receive register empty signal
-- SPI_Received_Data -- Data received from receive register
-- SPIXfer_done -- SPI transfer done flag
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_receive_transmit_reg is
generic
(
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
---------------------
C_NUM_TRANSFER_BITS : integer -- Number of bits to be transferred
---------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
------------------------------------
-- RECEIVER RELATED SIGNALS
--=========================
Bus2IP_Receive_Reg_RdCE : in std_logic;
Receive_ip2bus_error : out std_logic;
IP2Bus_Receive_Reg_Data : out std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
-- SPI module ports
SPIXfer_done : in std_logic;
SPI_Received_Data : in std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
-- receive & transmit reg signals
-- DRR_Overrun : out std_logic;
SR_7_Rx_Empty : out std_logic;
------------------------------------
-- TRANSMITTER RELATED SIGNALS
--============================
-- Slave attachment ports
Bus2IP_Transmit_Reg_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Bus2IP_Transmit_Reg_WrCE : in std_logic;
Wr_ce_reduce_ack_gen : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
--SPI Transmitter signals
Transmit_ip2bus_error : out std_logic;
-- SPI module ports
DTR_underrun : in std_logic;
SR_5_Tx_Empty : out std_logic;
tx_empty_signal_handshake_req : out std_logic;
tx_empty_signal_handshake_gnt : in std_logic;
DTR_Underrun_strobe : out std_logic;
Transmit_Reg_Data_Out : out std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1))
);
end qspi_receive_transmit_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_receive_transmit_reg is
---------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal Received_register_Data : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_7_Rx_Empty_reg : std_logic;
signal drr_Overrun_strobe : std_logic;
--------------------------------------------
signal sr_5_Tx_Empty_i : std_logic;
signal tx_empty_signal_handshake_req_i : std_logic;
signal tx_Reg_Soft_Reset_op : std_logic;
signal dtr_Underrun_strobe_i : std_logic;
signal dtr_underrun_d1 : std_logic;
signal SPIXfer_done_delay : std_logic;
constant RESET_ACTIVE : std_logic := '1';
--------------------------------------------
begin
-----
-- RECEIVER LOGIC
--=================
-- Combinatorial operations
----------------------------
SR_7_Rx_Empty <= sr_7_Rx_Empty_reg;
-- DRR_Overrun <= drr_Overrun_strobe;
DELAY_XFER_DONE_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_delay <= '0';
else
SPIXfer_done_delay <= SPIXfer_done;
end if;
end if;
end process DELAY_XFER_DONE_P;
-------------------------------------------------------------------------------
-- RECEIVE_REG_GENERATE : Receive Register Read Operation from SPI_Received_Data
-- register
--------------------------
RECEIVE_REG_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
RECEIVE_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Received_register_Data(i) <= '0';
elsif (SPIXfer_done_delay = '1') then--((sr_7_Rx_Empty_reg and SPIXfer_done) = '1') then
Received_register_Data(i) <= SPI_Received_Data(i);
end if;
end if;
end process RECEIVE_REG_PROCESS_P;
-----
end generate RECEIVE_REG_GENERATE;
-------------------------------------------------------------------------------
-- RECEIVE_REG_RD_GENERATE : Receive Register Read Operation
-----------------------------
RECEIVE_REG_RD_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
IP2Bus_Receive_Reg_Data(i) <= Received_register_Data(i) and
Bus2IP_Receive_Reg_RdCE;
end generate RECEIVE_REG_RD_GENERATE;
-------------------------------------------------------------------------------
-- RX_ERROR_ACK_REG_PROCESS_P : Strobe error when receive register is empty
--------------------------------
RX_ERROR_ACK_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
Receive_ip2bus_error <= sr_7_Rx_Empty_reg and
Bus2IP_Receive_Reg_RdCE;
end if;
end process RX_ERROR_ACK_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- SR_7_RX_EMPTY_REG_PROCESS_P : SR_7_Rx_Empty register
-------------------------------
SR_7_RX_EMPTY_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
sr_7_Rx_Empty_reg <= '1';
elsif (SPIXfer_done = '1') then
sr_7_Rx_Empty_reg <= '0';
elsif ((rd_ce_reduce_ack_gen and Bus2IP_Receive_Reg_RdCE) = '1') then
sr_7_Rx_Empty_reg <= '1';
end if;
end if;
end process SR_7_RX_EMPTY_REG_PROCESS_P;
----******************************************************************************
-- TRANSMITTER LOGIC
--==================
-- Combinatorial operations
----------------------------
tx_empty_signal_handshake_req <= tx_empty_signal_handshake_req_i;
SR_5_Tx_Empty <= sr_5_Tx_Empty_i;
DTR_Underrun_strobe <= dtr_Underrun_strobe_i;
tx_Reg_Soft_Reset_op <= SPIXfer_done or Soft_Reset_op;
--------------------------------------
-------------------------------------------------------------------------------
-- TRANSMIT_REG_GENERATE : Transmit Register Write
---------------------------
TRANSMIT_REG_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
TRANSMIT_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (tx_Reg_Soft_Reset_op = RESET_ACTIVE) then
Transmit_Reg_Data_Out(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_Transmit_Reg_WrCE) = '1')then
Transmit_Reg_Data_Out(i) <=
Bus2IP_Transmit_Reg_Data
(C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS+i) after 100 ps;
end if;
end if;
end process TRANSMIT_REG_PROCESS_P;
-----
end generate TRANSMIT_REG_GENERATE;
-----------------------------------
-- TX_ERROR_ACK_REG_PROCESS_P : Strobe error when transmit register is full
--------------------------------
TX_ERROR_ACK_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
Transmit_ip2bus_error <= not(sr_5_Tx_Empty_i) and
Bus2IP_Transmit_Reg_WrCE;
end if;
end process TX_ERROR_ACK_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- SR_5_TX_EMPTY_REG_PROCESS_P : Tx Empty generate
-------------------------------
SR_5_TX_EMPTY_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
sr_5_Tx_Empty_i <= '1';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_Transmit_Reg_WrCE) = '1') then
sr_5_Tx_Empty_i <= '0';
elsif (SPIXfer_done = '1') then
sr_5_Tx_Empty_i <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- tx_empty_signal_handshake_req_i
-------------------------------
process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_empty_signal_handshake_req_i <= '1';
elsif (sr_5_Tx_Empty_i = '1') then
tx_empty_signal_handshake_req_i <= '1';
elsif (sr_5_Tx_Empty_i = '0' and tx_empty_signal_handshake_gnt = '1') then
tx_empty_signal_handshake_req_i <= '0';
end if;
end if;
end process ;
-------------------------------------------------------------------------------
-- DTR_UNDERRUN_REG_PROCESS_P : Strobe to interrupt for transmit data underrun
-- which happens only in slave mode
-----------------------------
DTR_UNDERRUN_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
dtr_underrun_d1 <= '0';
else
dtr_underrun_d1 <= DTR_underrun;
end if;
end if;
end process DTR_UNDERRUN_REG_PROCESS_P;
---------------------------------------
dtr_Underrun_strobe_i <= DTR_underrun and (not dtr_underrun_d1);
--******************************************************************************
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
934ba4c70568a2fe83496b677a09da40
| 0.450373 | 4.508748 | false | false | false | false |
tmeissner/cryptocores
|
tdes/rtl/vhdl/tdes.vhd
| 1 | 4,171 |
-- ======================================================================
-- TDES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity tdes is
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 to 63); -- key input
key2_i : in std_logic_vector(0 to 63); -- key input
key3_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity tdes;
architecture rtl of tdes is
signal s_mode : std_logic;
signal s_des1_validout : std_logic;
signal s_des2_validout : std_logic;
signal s_des2_acceptout : std_logic;
signal s_des3_acceptout : std_logic;
signal s_key1 : std_logic_vector(0 to 63);
signal s_key2 : std_logic_vector(0 to 63);
signal s_key3 : std_logic_vector(0 to 63);
signal s_des1_key : std_logic_vector(0 to 63);
signal s_des3_key : std_logic_vector(0 to 63);
signal s_des1_dataout : std_logic_vector(0 to 63);
signal s_des2_dataout : std_logic_vector(0 to 63);
begin
s_des1_key <= key1_i when mode_i = '0' else key3_i;
s_des3_key <= s_key3 when s_mode = '0' else s_key1;
inputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_mode <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
elsif(rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
s_mode <= mode_i;
s_key1 <= key1_i;
s_key2 <= key2_i;
s_key3 <= key3_i;
end if;
end if;
end process inputregister;
i1_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => mode_i,
key_i => s_des1_key,
data_i => data_i,
valid_i => valid_i,
accept_o => accept_o,
data_o => s_des1_dataout,
valid_o => s_des1_validout,
accept_i => s_des2_acceptout
);
i2_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => not s_mode,
key_i => s_key2,
data_i => s_des1_dataout,
valid_i => s_des1_validout,
accept_o => s_des2_acceptout,
data_o => s_des2_dataout,
valid_o => s_des2_validout,
accept_i => s_des3_acceptout
);
i3_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_mode,
key_i => s_des3_key,
data_i => s_des2_dataout,
valid_i => s_des2_validout,
accept_o => s_des3_acceptout,
data_o => data_o,
valid_o => valid_o,
accept_i => accept_i
);
end architecture rtl;
|
gpl-2.0
|
3dfeb9560ea4dba3dcbbbb5628b9a1a4
| 0.539199 | 3.266249 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd
| 2 | 173,134 |
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xxEDsb8=
`protect end_protected
|
bsd-3-clause
|
44d60e0e90a8503670ee21d37637c78c
| 0.953909 | 1.832203 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/dualport_bram.vhdl
| 1 | 1,780 |
-- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
-- https://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils.all;
use work.txt_utils.all;
entity dualport_bram is
generic (
WORD_WIDTH : integer := 8;
ADDR_WIDTH : integer := 8
);
port (
-- Port A
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(WORD_WIDTH-1 downto 0);
a_dout : out std_logic_vector(WORD_WIDTH-1 downto 0);
a_wr : in std_logic;
a_clk : in std_logic;
-- Port B
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_din : in std_logic_vector(WORD_WIDTH-1 downto 0);
b_dout : out std_logic_vector(WORD_WIDTH-1 downto 0);
b_wr : in std_logic;
b_clk : in std_logic
);
end dualport_bram;
architecture rtl of dualport_bram is
-- Shared memory
type mem_type is array ( (2**ADDR_WIDTH)-1 downto 0 ) of std_logic_vector(WORD_WIDTH-1 downto 0);
shared variable mem : mem_type;
signal first_byte : std_logic_vector(WORD_WIDTH-1 downto 0);
begin
first_byte <= mem(0);
-- Port A
process(a_clk)
begin
if(rising_edge(a_clk)) then
if(a_wr='1') then
printf(ANSI_GREEN & "writing %s to %s\n", a_din, a_addr);
mem(vtou(a_addr)) := a_din;
end if;
a_dout <= mem(vtou(a_addr));
end if;
end process;
-- Port B
process(b_clk)
begin
if(rising_edge(b_clk)) then
if(b_wr='1') then
mem(vtou(b_addr)) := b_din;
end if;
-- FIXME
end if;
-- If use synchronous RAM we would haveto run at double the VGA clock, I think
b_dout <= mem(vtou(b_addr));
end process;
end rtl;
|
gpl-3.0
|
6dcd52bcefe2b469aa629c156df94a95
| 0.605618 | 2.937294 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/pass_through.vhd
| 1 | 8,880 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name: Pass-through filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter passes the video signals from input to output.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Pass-through architecture
architecture Behavioral of Video_Box is
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--the user can edit the rgb values here
USER_LOGIC <= RGB_IN_reg;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when b"000000101" =>
reg_data_out <= slv_reg5;
when b"000000110" =>
reg_data_out <= slv_reg6;
when b"000000111" =>
reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End Pass-through architecture
|
bsd-3-clause
|
8f1c986fde74027036faaf10bd96fe58
| 0.612387 | 2.987887 | false | false | false | false |
tmeissner/cryptocores
|
des/sim/vhdl/tb_des_pkg.vhd
| 1 | 7,208 |
-- ======================================================================
-- DES encryption/decryption testbench
-- tests according to NIST 800-17 special publication
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
package tb_des_pkg is
type t_array is array (natural range <>) of std_logic_vector(0 to 63);
constant c_variable_plaintext_known_answers : t_array(0 to 63) :=
(x"95F8A5E5DD31D900", x"DD7F121CA5015619", x"2E8653104F3834EA",
x"4BD388FF6CD81D4F", x"20B9E767B2FB1456", x"55579380D77138EF",
x"6CC5DEFAAF04512F", x"0D9F279BA5D87260", x"D9031B0271BD5A0A",
x"424250B37C3DD951", x"B8061B7ECD9A21E5", x"F15D0F286B65BD28",
x"ADD0CC8D6E5DEBA1", x"E6D5F82752AD63D1", x"ECBFE3BD3F591A5E",
x"F356834379D165CD", x"2B9F982F20037FA9", x"889DE068A16F0BE6",
x"E19E275D846A1298", x"329A8ED523D71AEC", x"E7FCE22557D23C97",
x"12A9F5817FF2D65D", x"A484C3AD38DC9C19", x"FBE00A8A1EF8AD72",
x"750D079407521363", x"64FEED9C724C2FAF", x"F02B263B328E2B60",
x"9D64555A9A10B852", x"D106FF0BED5255D7", x"E1652C6B138C64A5",
x"E428581186EC8F46", x"AEB5F5EDE22D1A36", x"E943D7568AEC0C5C",
x"DF98C8276F54B04B", x"B160E4680F6C696F", x"FA0752B07D9C4AB8",
x"CA3A2B036DBC8502", x"5E0905517BB59BCF", x"814EEB3B91D90726",
x"4D49DB1532919C9F", x"25EB5FC3F8CF0621", x"AB6A20C0620D1C6F",
x"79E90DBC98F92CCA", x"866ECEDD8072BB0E", x"8B54536F2F3E64A8",
x"EA51D3975595B86B", x"CAFFC6AC4542DE31", x"8DD45A2DDF90796C",
x"1029D55E880EC2D0", x"5D86CB23639DBEA9", x"1D1CA853AE7C0C5F",
x"CE332329248F3228", x"8405D1ABE24FB942", x"E643D78090CA4207",
x"48221B9937748A23", x"DD7C0BBD61FAFD54", x"2FBC291A570DB5C4",
x"E07C30D7E4E26E12", x"0953E2258E8E90A1", x"5B711BC4CEEBF2EE",
x"CC083F1E6D9E85F6", x"D2FD8867D50D2DFE", x"06E7EA22CE92708F",
x"166B40B44ABA4BD6");
constant c_variable_key_known_answers : t_array(0 to 55) :=
(x"95A8D72813DAA94D", x"0EEC1487DD8C26D5", x"7AD16FFB79C45926",
x"D3746294CA6A6CF3", x"809F5F873C1FD761", x"C02FAFFEC989D1FC",
x"4615AA1D33E72F10", x"2055123350C00858", x"DF3B99D6577397C8",
x"31FE17369B5288C9", x"DFDD3CC64DAE1642", x"178C83CE2B399D94",
x"50F636324A9B7F80", x"A8468EE3BC18F06D", x"A2DC9E92FD3CDE92",
x"CAC09F797D031287", x"90BA680B22AEB525", x"CE7A24F350E280B6",
x"882BFF0AA01A0B87", x"25610288924511C2", x"C71516C29C75D170",
x"5199C29A52C9F059", x"C22F0A294A71F29F", x"EE371483714C02EA",
x"A81FBD448F9E522F", x"4F644C92E192DFED", x"1AFA9A66A6DF92AE",
x"B3C1CC715CB879D8", x"19D032E64AB0BD8B", x"3CFAA7A7DC8720DC",
x"B7265F7F447AC6F3", x"9DB73B3C0D163F54", x"8181B65BABF4A975",
x"93C9B64042EAA240", x"5570530829705592", x"8638809E878787A0",
x"41B9A79AF79AC208", x"7A9BE42F2009A892", x"29038D56BA6D2745",
x"5495C6ABF1E5DF51", x"AE13DBD561488933", x"024D1FFA8904E389",
x"D1399712F99BF02E", x"14C1D7C1CFFEC79E", x"1DE5279DAE3BED6F",
x"E941A33F85501303", x"DA99DBBC9A03F379", x"B7FC92F91D8E92E9",
x"AE8E5CAA3CA04E85", x"9CC62DF43B6EED74", x"D863DBB5C59A91A0",
x"A1AB2190545B91D7", x"0875041E64C570F7", x"5A594528BEBEF1CC",
x"FCDB3291DE21F0C0", x"869EFD7F9F265A09");
constant c_permutation_operation_known_answers_keys : t_array(0 to 31) :=
(x"1046913489980131", x"1007103489988020", x"10071034C8980120",
x"1046103489988020", x"1086911519190101", x"1086911519580101",
x"5107B01519580101", x"1007B01519190101", x"3107915498080101",
x"3107919498080101", x"10079115B9080140", x"3107911598080140",
x"1007D01589980101", x"9107911589980101", x"9107D01589190101",
x"1007D01598980120", x"1007940498190101", x"0107910491190401",
x"0107910491190101", x"0107940491190401", x"19079210981A0101",
x"1007911998190801", x"10079119981A0801", x"1007921098190101",
x"100791159819010B", x"1004801598190101", x"1004801598190102",
x"1004801598190108", x"1002911598100104", x"1002911598190104",
x"1002911598100201", x"1002911698100101");
constant c_permutation_operation_known_answers_cipher : t_array(0 to 31) :=
(x"88D55E54F54C97B4", x"0C0CC00C83EA48FD", x"83BC8EF3A6570183",
x"DF725DCAD94EA2E9", x"E652B53B550BE8B0", x"AF527120C485CBB0",
x"0F04CE393DB926D5", x"C9F00FFC74079067", x"7CFD82A593252B4E",
x"CB49A2F9E91363E3", x"00B588BE70D23F56", x"406A9A6AB43399AE",
x"6CB773611DCA9ADA", x"67FD21C17DBB5D70", x"9592CB4110430787",
x"A6B7FF68A318DDD3", x"4D102196C914CA16", x"2DFA9F4573594965",
x"B46604816C0E0774", x"6E7E6221A4F34E87", x"AA85E74643233199",
x"2E5A19DB4D1962D6", x"23A866A809D30894", x"D812D961F017D320",
x"055605816E58608F", x"ABD88E8B1B7716F1", x"537AC95BE69DA1E1",
x"AED0F6AE3C25CDD8", x"B3E35A5EE53E7B8D", x"61C79C71921A2EF8",
x"E2F5728F0995013C", x"1AEAC39A61F0A464");
constant c_substitution_table_test_keys : t_array(0 to 18) :=
(x"7CA110454A1A6E57", x"0131D9619DC1376E", x"07A1133E4A0B2686",
x"3849674C2602319E", x"04B915BA43FEB5B6", x"0113B970FD34F2CE",
x"0170F175468FB5E6", x"43297FAD38E373FE", x"07A7137045DA2A16",
x"04689104C2FD3B2F", x"37D06BB516CB7546", x"1F08260D1AC2465E",
x"584023641ABA6176", x"025816164629B007", x"49793EBC79B3258F",
x"4FB05E1515AB73A7", x"49E95D6D4CA229BF", x"018310DC409B26D6",
x"1C587F1C13924FEF");
constant c_substitution_table_test_plain : t_array(0 to 18) :=
(x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802",
x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA",
x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA",
x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2",
x"305532286D6F295A");
constant c_substitution_table_test_cipher : t_array(0 to 18) :=
(x"690F5B0D9A26939B", x"7A389D10354BD271", x"868EBB51CAB4599A",
x"7178876E01F19B2A", x"AF37FB421F8C4095", x"86A560F10EC6D85B",
x"0CD3DA020021DC09", x"EA676B2CB7DB2B7A", x"DFD64A815CAF1A0F",
x"5C513C9C4886C088", x"0A2AEEAE3FF4AB77", x"EF1BF03E5DFA575A",
x"88BF0DB6D70DEE56", x"A1F9915541020B56", x"6FBF1CAFCFFD0556",
x"2F22E49BAB7CA1AC", x"5A6B612CC26CCE4A", x"5F4C038ED12B2E41",
x"63FAC0D034D9F793");
end package tb_des_pkg;
|
gpl-2.0
|
1448d42d120dd4013831dcb5f360d2fc
| 0.721698 | 2.258853 | false | false | false | false |
makestuff/vga_test
|
vhdl/clk_gen/clk_gen_xilinx.vhdl
| 1 | 1,172 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen_wrapper is
port(
clk_in : in std_logic;
clk_out : out std_logic;
locked_out : out std_logic
);
end entity;
architecture structural of clk_gen_wrapper is
begin
clk_gen : entity work.clk_gen
port map(
CLKIN_IN => clk_in,
CLKDV_OUT => clk_out,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => locked_out
);
end architecture;
|
gpl-3.0
|
8beb9ced68fbb8e69e22d06ea26735ba
| 0.696246 | 3.551515 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_gpio_cntrl.vhd
| 1 | 2,217 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! GPIO Core's Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity plasoc_gpio_cntrl is
generic (
constant data_in_width : integer := 16 );
port (
clock : in std_logic;
nreset : in std_logic;
enable : in std_logic;
ack : in std_logic;
int : out std_logic;
data_in_axi : out std_logic_vector(data_in_width-1 downto 0);
data_in_periph : in std_logic_vector(data_in_width-1 downto 0) );
end plasoc_gpio_cntrl;
architecture Behavioral of plasoc_gpio_cntrl is
signal data_in_axi_buff : std_logic_vector(data_in_width-1 downto 0) := (others=>'0');
signal int_buff : std_logic := '0';
begin
data_in_axi <= data_in_axi_buff;
int <= int_buff;
process (clock)
begin
-- Perform operations in synch with positive edge of clock.
if rising_edge(clock) then
-- Reset on low.
if nreset='0' then
int_buff <= '0';
-- Normal operation occurs when reset is high.
else
-- The interrupt operation only occurs when enable is set high.
if enable='1' then
-- If no interrupt is occurring, check for new data.
if int_buff='0' and data_in_axi_buff/=data_in_periph then
-- If new data is available, sample the input and set the interrupt.
data_in_axi_buff <= data_in_periph;
int_buff <= '1';
-- Once the interrupt is acknowledged, set the interrupt to low.
elsif ack='1' then
int_buff <= '0';
end if;
-- If interrupts are not enabled, always register the input.
else
data_in_axi_buff <= data_in_periph;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
a84820c8793841ee1633320fc417b548
| 0.520072 | 4.263462 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/memory_map.vhdl
| 1 | 1,823 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
package memory_map is
constant BOOT_ADDR : addr_t := X"0000_0000";
constant B : natural := 1; constant K : natural := 1024*B; constant M : natural := K*K;
subtype memchipsel_t is std_logic_vector(11 downto 0);
type mblock_t is record
base : addr_t; size : natural; chip_select : memchipsel_t;
end record;
type mmap_t is array (natural range <>) of mblock_t;
constant mmap : mmap_t := (
(X"A0000000", 128*M, X"001"), -- RAM
(BOOT_ADDR, 128*K, X"002"), -- ROM
(X"14000000", 1*B, X"004"), -- LEDs
(X"14000001", 1*B, X"008"), -- DIP-Switch
(X"14000002", 1*B, X"010"), -- Pushbuttons
(X"14000004", 4*B, X"020"), -- Timestamp counter
(X"140003f8", 7*B, X"040"), -- UART
(X"10000000", 16*M, X"080"), -- VRAM
(X"14000010", 16*B, X"100") -- Video configuration
);
constant mmap_ram : natural := 0;
constant mmap_rom : natural := 1;
constant mmap_led : natural := 2;
constant mmap_dipswitch : natural := 3;
constant mmap_push : natural := 4;
constant mmap_tsc : natural := 5;
constant mmap_uart : natural := 6;
constant mmap_vram : natural := 7;
constant mmap_videocfg : natural := 8;
function inside(addr_vec, base_vec: addr_t; len : natural) return boolean;
end memory_map;
package body memory_map is
function inside(addr_vec, base_vec: addr_t; len : natural) return boolean is
variable addr: unsigned(31 downto 0) := unsigned(addr_vec);
variable base: unsigned(31 downto 0) := unsigned(base_vec);
begin
return base <= addr and addr < base + len;
end inside;
end memory_map;
|
gpl-3.0
|
4b469efee388a2f7fd976ae62a8a05c4
| 0.583653 | 3.261181 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/AXI_DPTI_1.0/src/HandshakeData.vhd
| 1 | 6,879 |
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 20116
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed though.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
--
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aReset: signal is "TRUE";
begin
DetectPush: process(aReset, InClk)
begin
if (aReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aReset, InClk)
begin
if (aReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aReset, OutClk)
begin
if (aReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aReset, OutClk)
begin
if (aReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aReset into the InClk domain
-- We need it to keep iRdy low, when aReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aReset,
OutClk => InClk,
oRst => iReset);
ReadySignal: process(aReset, InClk)
begin
if (aReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
bsd-3-clause
|
344e756cf11d5d035d18349db37fb0dc
| 0.658671 | 4.32098 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/pipeline.vhd
| 15 | 5,657 |
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
mit
|
0cecb2fea2b1732b9cedceb188154b52
| 0.583702 | 3.430564 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_0/sim/fifo_generator_0.vhd
| 1 | 35,042 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_0 IS
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 master_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 1,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 1,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 1,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 1,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 12,
C_IMPLEMENTATION_TYPE_WDCH => 11,
C_IMPLEMENTATION_TYPE_WRCH => 12,
C_IMPLEMENTATION_TYPE_RACH => 12,
C_IMPLEMENTATION_TYPE_RDCH => 11,
C_IMPLEMENTATION_TYPE_AXIS => 11,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 41,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1021,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1021,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1021,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => m_aclk,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => s_axis_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tuser => m_axis_tuser,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_overflow => axis_overflow,
axis_underflow => axis_underflow
);
END fifo_generator_0_arch;
|
bsd-3-clause
|
20657613bc7509b6781753c177906e85
| 0.611951 | 3.069283 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd
| 1 | 157,786 |
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`protect end_protected
|
apache-2.0
|
9cc5ad7fcc74c2ee05b9a06db01c31d0
| 0.953868 | 1.832228 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/pc_next.vhd
| 14 | 2,101 |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
mit
|
52846ee70a3ebd2c702f7fb032c9a8b7
| 0.561637 | 3.366987 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/hdl/mig_wrap.vhd
| 1 | 87,871 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Wed Apr 05 00:15:23 2017
--Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
--Command : generate_target mig_wrap.bd
--Design : mig_wrap
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_GVFDLK is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC;
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC;
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_GVFDLK;
architecture STRUCTURE of s00_couplers_imp_GVFDLK is
component mig_wrap_s00_regslice_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component mig_wrap_s00_regslice_0;
component mig_wrap_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component mig_wrap_auto_cc_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_cc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_cc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_cc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_s00_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_regslice_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_regslice_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_regslice_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_regslice_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_regslice_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_ARREADY : STD_LOGIC;
signal s00_couplers_to_s00_regslice_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_regslice_ARVALID : STD_LOGIC;
signal s00_couplers_to_s00_regslice_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_regslice_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_regslice_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_regslice_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_regslice_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_regslice_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_AWREADY : STD_LOGIC;
signal s00_couplers_to_s00_regslice_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_regslice_AWVALID : STD_LOGIC;
signal s00_couplers_to_s00_regslice_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_BREADY : STD_LOGIC;
signal s00_couplers_to_s00_regslice_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_regslice_BVALID : STD_LOGIC;
signal s00_couplers_to_s00_regslice_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_regslice_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_RLAST : STD_LOGIC;
signal s00_couplers_to_s00_regslice_RREADY : STD_LOGIC;
signal s00_couplers_to_s00_regslice_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_regslice_RVALID : STD_LOGIC;
signal s00_couplers_to_s00_regslice_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_regslice_WLAST : STD_LOGIC;
signal s00_couplers_to_s00_regslice_WREADY : STD_LOGIC;
signal s00_couplers_to_s00_regslice_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_regslice_WVALID : STD_LOGIC;
signal s00_regslice_to_auto_cc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_regslice_to_auto_cc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_regslice_to_auto_cc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_regslice_to_auto_cc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_regslice_to_auto_cc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_regslice_to_auto_cc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_ARREADY : STD_LOGIC;
signal s00_regslice_to_auto_cc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_regslice_to_auto_cc_ARVALID : STD_LOGIC;
signal s00_regslice_to_auto_cc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_regslice_to_auto_cc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_regslice_to_auto_cc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_regslice_to_auto_cc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_regslice_to_auto_cc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_regslice_to_auto_cc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_AWREADY : STD_LOGIC;
signal s00_regslice_to_auto_cc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_regslice_to_auto_cc_AWVALID : STD_LOGIC;
signal s00_regslice_to_auto_cc_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_BREADY : STD_LOGIC;
signal s00_regslice_to_auto_cc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_regslice_to_auto_cc_BVALID : STD_LOGIC;
signal s00_regslice_to_auto_cc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_regslice_to_auto_cc_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_RLAST : STD_LOGIC;
signal s00_regslice_to_auto_cc_RREADY : STD_LOGIC;
signal s00_regslice_to_auto_cc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_regslice_to_auto_cc_RVALID : STD_LOGIC;
signal s00_regslice_to_auto_cc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_regslice_to_auto_cc_WLAST : STD_LOGIC;
signal s00_regslice_to_auto_cc_WREADY : STD_LOGIC;
signal s00_regslice_to_auto_cc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_regslice_to_auto_cc_WVALID : STD_LOGIC;
signal NLW_auto_cc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_cc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1 <= M_ARESETN;
M_AXI_araddr(31 downto 0) <= auto_cc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_cc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_cc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(3 downto 0) <= auto_cc_to_s00_couplers_ARID(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_cc_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock <= auto_cc_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_cc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_cc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_cc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_cc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_cc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_cc_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_cc_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(3 downto 0) <= auto_cc_to_s00_couplers_AWID(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_cc_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock <= auto_cc_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_cc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_cc_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_cc_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_cc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_cc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_cc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_cc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast <= auto_cc_to_s00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_cc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_cc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_s00_regslice_ARREADY;
S_AXI_awready <= s00_couplers_to_s00_regslice_AWREADY;
S_AXI_bid(3 downto 0) <= s00_couplers_to_s00_regslice_BID(3 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_regslice_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_s00_regslice_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_regslice_RDATA(31 downto 0);
S_AXI_rid(3 downto 0) <= s00_couplers_to_s00_regslice_RID(3 downto 0);
S_AXI_rlast <= s00_couplers_to_s00_regslice_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_regslice_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_s00_regslice_RVALID;
S_AXI_wready <= s00_couplers_to_s00_regslice_WREADY;
auto_cc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_cc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_cc_to_s00_couplers_BID(3 downto 0) <= M_AXI_bid(3 downto 0);
auto_cc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_cc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_cc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_cc_to_s00_couplers_RID(3 downto 0) <= M_AXI_rid(3 downto 0);
auto_cc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_cc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_cc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_cc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_s00_regslice_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_regslice_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_regslice_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_regslice_ARID(3 downto 0) <= S_AXI_arid(3 downto 0);
s00_couplers_to_s00_regslice_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_regslice_ARLOCK(0) <= S_AXI_arlock(0);
s00_couplers_to_s00_regslice_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_regslice_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_s00_regslice_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
s00_couplers_to_s00_regslice_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_regslice_ARVALID <= S_AXI_arvalid;
s00_couplers_to_s00_regslice_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_regslice_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_s00_regslice_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_s00_regslice_AWID(3 downto 0) <= S_AXI_awid(3 downto 0);
s00_couplers_to_s00_regslice_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_s00_regslice_AWLOCK(0) <= S_AXI_awlock(0);
s00_couplers_to_s00_regslice_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_regslice_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_s00_regslice_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
s00_couplers_to_s00_regslice_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_s00_regslice_AWVALID <= S_AXI_awvalid;
s00_couplers_to_s00_regslice_BREADY <= S_AXI_bready;
s00_couplers_to_s00_regslice_RREADY <= S_AXI_rready;
s00_couplers_to_s00_regslice_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_regslice_WLAST <= S_AXI_wlast;
s00_couplers_to_s00_regslice_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_regslice_WVALID <= S_AXI_wvalid;
auto_cc: component mig_wrap_auto_cc_0
port map (
m_axi_aclk => M_ACLK_1,
m_axi_araddr(31 downto 0) => auto_cc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_cc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_cc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_aresetn => M_ARESETN_1,
m_axi_arid(3 downto 0) => auto_cc_to_s00_couplers_ARID(3 downto 0),
m_axi_arlen(7 downto 0) => auto_cc_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_cc_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_cc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_cc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_cc_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_cc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_cc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_cc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_cc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_cc_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_cc_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awid(3 downto 0) => auto_cc_to_s00_couplers_AWID(3 downto 0),
m_axi_awlen(7 downto 0) => auto_cc_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_cc_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_cc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_cc_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_cc_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_cc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_cc_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_cc_to_s00_couplers_AWVALID,
m_axi_bid(3 downto 0) => auto_cc_to_s00_couplers_BID(3 downto 0),
m_axi_bready => auto_cc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_cc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_cc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_cc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rid(3 downto 0) => auto_cc_to_s00_couplers_RID(3 downto 0),
m_axi_rlast => auto_cc_to_s00_couplers_RLAST,
m_axi_rready => auto_cc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_cc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_cc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_cc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wlast => auto_cc_to_s00_couplers_WLAST,
m_axi_wready => auto_cc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_cc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_cc_to_s00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_regslice_to_auto_cc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_regslice_to_auto_cc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_regslice_to_auto_cc_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arid(3 downto 0) => s00_regslice_to_auto_cc_ARID(3 downto 0),
s_axi_arlen(7 downto 0) => s00_regslice_to_auto_cc_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_regslice_to_auto_cc_ARLOCK(0),
s_axi_arprot(2 downto 0) => s00_regslice_to_auto_cc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_regslice_to_auto_cc_ARQOS(3 downto 0),
s_axi_arready => s00_regslice_to_auto_cc_ARREADY,
s_axi_arregion(3 downto 0) => s00_regslice_to_auto_cc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => s00_regslice_to_auto_cc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_regslice_to_auto_cc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_regslice_to_auto_cc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_regslice_to_auto_cc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_regslice_to_auto_cc_AWCACHE(3 downto 0),
s_axi_awid(3 downto 0) => s00_regslice_to_auto_cc_AWID(3 downto 0),
s_axi_awlen(7 downto 0) => s00_regslice_to_auto_cc_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_regslice_to_auto_cc_AWLOCK(0),
s_axi_awprot(2 downto 0) => s00_regslice_to_auto_cc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_regslice_to_auto_cc_AWQOS(3 downto 0),
s_axi_awready => s00_regslice_to_auto_cc_AWREADY,
s_axi_awregion(3 downto 0) => s00_regslice_to_auto_cc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => s00_regslice_to_auto_cc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_regslice_to_auto_cc_AWVALID,
s_axi_bid(3 downto 0) => s00_regslice_to_auto_cc_BID(3 downto 0),
s_axi_bready => s00_regslice_to_auto_cc_BREADY,
s_axi_bresp(1 downto 0) => s00_regslice_to_auto_cc_BRESP(1 downto 0),
s_axi_bvalid => s00_regslice_to_auto_cc_BVALID,
s_axi_rdata(31 downto 0) => s00_regslice_to_auto_cc_RDATA(31 downto 0),
s_axi_rid(3 downto 0) => s00_regslice_to_auto_cc_RID(3 downto 0),
s_axi_rlast => s00_regslice_to_auto_cc_RLAST,
s_axi_rready => s00_regslice_to_auto_cc_RREADY,
s_axi_rresp(1 downto 0) => s00_regslice_to_auto_cc_RRESP(1 downto 0),
s_axi_rvalid => s00_regslice_to_auto_cc_RVALID,
s_axi_wdata(31 downto 0) => s00_regslice_to_auto_cc_WDATA(31 downto 0),
s_axi_wlast => s00_regslice_to_auto_cc_WLAST,
s_axi_wready => s00_regslice_to_auto_cc_WREADY,
s_axi_wstrb(3 downto 0) => s00_regslice_to_auto_cc_WSTRB(3 downto 0),
s_axi_wvalid => s00_regslice_to_auto_cc_WVALID
);
s00_regslice: component mig_wrap_s00_regslice_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => s00_regslice_to_auto_cc_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => s00_regslice_to_auto_cc_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => s00_regslice_to_auto_cc_ARCACHE(3 downto 0),
m_axi_arid(3 downto 0) => s00_regslice_to_auto_cc_ARID(3 downto 0),
m_axi_arlen(7 downto 0) => s00_regslice_to_auto_cc_ARLEN(7 downto 0),
m_axi_arlock(0) => s00_regslice_to_auto_cc_ARLOCK(0),
m_axi_arprot(2 downto 0) => s00_regslice_to_auto_cc_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => s00_regslice_to_auto_cc_ARQOS(3 downto 0),
m_axi_arready => s00_regslice_to_auto_cc_ARREADY,
m_axi_arregion(3 downto 0) => s00_regslice_to_auto_cc_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => s00_regslice_to_auto_cc_ARSIZE(2 downto 0),
m_axi_arvalid => s00_regslice_to_auto_cc_ARVALID,
m_axi_awaddr(31 downto 0) => s00_regslice_to_auto_cc_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => s00_regslice_to_auto_cc_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => s00_regslice_to_auto_cc_AWCACHE(3 downto 0),
m_axi_awid(3 downto 0) => s00_regslice_to_auto_cc_AWID(3 downto 0),
m_axi_awlen(7 downto 0) => s00_regslice_to_auto_cc_AWLEN(7 downto 0),
m_axi_awlock(0) => s00_regslice_to_auto_cc_AWLOCK(0),
m_axi_awprot(2 downto 0) => s00_regslice_to_auto_cc_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => s00_regslice_to_auto_cc_AWQOS(3 downto 0),
m_axi_awready => s00_regslice_to_auto_cc_AWREADY,
m_axi_awregion(3 downto 0) => s00_regslice_to_auto_cc_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => s00_regslice_to_auto_cc_AWSIZE(2 downto 0),
m_axi_awvalid => s00_regslice_to_auto_cc_AWVALID,
m_axi_bid(3 downto 0) => s00_regslice_to_auto_cc_BID(3 downto 0),
m_axi_bready => s00_regslice_to_auto_cc_BREADY,
m_axi_bresp(1 downto 0) => s00_regslice_to_auto_cc_BRESP(1 downto 0),
m_axi_bvalid => s00_regslice_to_auto_cc_BVALID,
m_axi_rdata(31 downto 0) => s00_regslice_to_auto_cc_RDATA(31 downto 0),
m_axi_rid(3 downto 0) => s00_regslice_to_auto_cc_RID(3 downto 0),
m_axi_rlast => s00_regslice_to_auto_cc_RLAST,
m_axi_rready => s00_regslice_to_auto_cc_RREADY,
m_axi_rresp(1 downto 0) => s00_regslice_to_auto_cc_RRESP(1 downto 0),
m_axi_rvalid => s00_regslice_to_auto_cc_RVALID,
m_axi_wdata(31 downto 0) => s00_regslice_to_auto_cc_WDATA(31 downto 0),
m_axi_wlast => s00_regslice_to_auto_cc_WLAST,
m_axi_wready => s00_regslice_to_auto_cc_WREADY,
m_axi_wstrb(3 downto 0) => s00_regslice_to_auto_cc_WSTRB(3 downto 0),
m_axi_wvalid => s00_regslice_to_auto_cc_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_s00_regslice_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_s00_regslice_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_s00_regslice_ARCACHE(3 downto 0),
s_axi_arid(3 downto 0) => s00_couplers_to_s00_regslice_ARID(3 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_s00_regslice_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_s00_regslice_ARLOCK(0),
s_axi_arprot(2 downto 0) => s00_couplers_to_s00_regslice_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_s00_regslice_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_s00_regslice_ARREADY,
s_axi_arregion(3 downto 0) => s00_couplers_to_s00_regslice_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_s00_regslice_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_s00_regslice_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_s00_regslice_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_s00_regslice_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_s00_regslice_AWCACHE(3 downto 0),
s_axi_awid(3 downto 0) => s00_couplers_to_s00_regslice_AWID(3 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_s00_regslice_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_s00_regslice_AWLOCK(0),
s_axi_awprot(2 downto 0) => s00_couplers_to_s00_regslice_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_s00_regslice_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_s00_regslice_AWREADY,
s_axi_awregion(3 downto 0) => s00_couplers_to_s00_regslice_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => s00_couplers_to_s00_regslice_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_s00_regslice_AWVALID,
s_axi_bid(3 downto 0) => s00_couplers_to_s00_regslice_BID(3 downto 0),
s_axi_bready => s00_couplers_to_s00_regslice_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_s00_regslice_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_s00_regslice_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_s00_regslice_RDATA(31 downto 0),
s_axi_rid(3 downto 0) => s00_couplers_to_s00_regslice_RID(3 downto 0),
s_axi_rlast => s00_couplers_to_s00_regslice_RLAST,
s_axi_rready => s00_couplers_to_s00_regslice_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_s00_regslice_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_s00_regslice_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_s00_regslice_WDATA(31 downto 0),
s_axi_wlast => s00_couplers_to_s00_regslice_WLAST,
s_axi_wready => s00_couplers_to_s00_regslice_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_s00_regslice_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_s00_regslice_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC;
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC;
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end mig_wrap_axi_interconnect_0_0;
architecture STRUCTURE of mig_wrap_axi_interconnect_0_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARLOCK : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWLOCK : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0);
M00_AXI_arid(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARID(3 downto 0);
M00_AXI_arlen(7 downto 0) <= s00_couplers_to_axi_interconnect_0_ARLEN(7 downto 0);
M00_AXI_arlock <= s00_couplers_to_axi_interconnect_0_ARLOCK;
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0);
M00_AXI_awid(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWID(3 downto 0);
M00_AXI_awlen(7 downto 0) <= s00_couplers_to_axi_interconnect_0_AWLEN(7 downto 0);
M00_AXI_awlock <= s00_couplers_to_axi_interconnect_0_AWLOCK;
M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0);
M00_AXI_awvalid <= s00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= s00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= s00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wlast <= s00_couplers_to_axi_interconnect_0_WLAST;
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(3 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(3 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(3 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(3 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= M00_ACLK;
axi_interconnect_0_ARESETN_net <= M00_ARESETN;
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(0) <= S00_AXI_arlock(0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARREGION(3 downto 0) <= S00_AXI_arregion(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(3 downto 0) <= S00_AXI_awid(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(0) <= S00_AXI_awlock(0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWREGION(3 downto 0) <= S00_AXI_awregion(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
s00_couplers_to_axi_interconnect_0_BID(3 downto 0) <= M00_AXI_bid(3 downto 0);
s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_axi_interconnect_0_RID(3 downto 0) <= M00_AXI_rid(3 downto 0);
s00_couplers_to_axi_interconnect_0_RLAST <= M00_AXI_rlast;
s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
s00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_GVFDLK
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN => axi_interconnect_0_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0),
M_AXI_arid(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARID(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_axi_interconnect_0_ARLEN(7 downto 0),
M_AXI_arlock => s00_couplers_to_axi_interconnect_0_ARLOCK,
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0),
M_AXI_awid(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWID(3 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_axi_interconnect_0_AWLEN(7 downto 0),
M_AXI_awlock => s00_couplers_to_axi_interconnect_0_AWLOCK,
M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bid(3 downto 0) => s00_couplers_to_axi_interconnect_0_BID(3 downto 0),
M_AXI_bready => s00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rid(3 downto 0) => s00_couplers_to_axi_interconnect_0_RID(3 downto 0),
M_AXI_rlast => s00_couplers_to_axi_interconnect_0_RLAST,
M_AXI_rready => s00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wlast => s00_couplers_to_axi_interconnect_0_WLAST,
M_AXI_wready => s00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => axi_interconnect_0_to_s00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => axi_interconnect_0_to_s00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(3 downto 0) => axi_interconnect_0_to_s00_couplers_BID(3 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(3 downto 0) => axi_interconnect_0_to_s00_couplers_RID(3 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap is
port (
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_cas_n : out STD_LOGIC;
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
SYS_CLK_clk_n : in STD_LOGIC;
SYS_CLK_clk_p : in STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_rst : in STD_LOGIC;
ui_addn_clk_0 : out STD_LOGIC;
ui_clk_sync_rst : out STD_LOGIC
);
attribute core_generation_info : string;
attribute core_generation_info of mig_wrap : entity is "mig_wrap,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mig_wrap,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
attribute hw_handoff : string;
attribute hw_handoff of mig_wrap : entity is "mig_wrap.hwdef";
end mig_wrap;
architecture STRUCTURE of mig_wrap is
component mig_wrap_mig_7series_0_0 is
port (
sys_rst : in STD_LOGIC;
ddr3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr3_ras_n : out STD_LOGIC;
ddr3_cas_n : out STD_LOGIC;
ddr3_we_n : out STD_LOGIC;
ddr3_reset_n : out STD_LOGIC;
ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ui_clk_sync_rst : out STD_LOGIC;
ui_clk : out STD_LOGIC;
ui_addn_clk_0 : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 29 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
mmcm_locked : out STD_LOGIC;
sys_clk_p : in STD_LOGIC;
sys_clk_n : in STD_LOGIC;
init_calib_complete : out STD_LOGIC;
aresetn : in STD_LOGIC
);
end component mig_wrap_mig_7series_0_0;
component mig_wrap_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mig_wrap_proc_sys_reset_0_0;
component mig_wrap_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mig_wrap_proc_sys_reset_1_0;
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S00_AXI_1_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC;
signal S00_AXI_1_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S00_AXI_1_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC;
signal S00_AXI_1_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC;
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_RLAST : STD_LOGIC;
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC;
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WLAST : STD_LOGIC;
signal S00_AXI_1_WREADY : STD_LOGIC;
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal SYS_CLK_1_CLK_N : STD_LOGIC;
signal SYS_CLK_1_CLK_P : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_M00_AXI_ARLOCK : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_M00_AXI_AWLOCK : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_RLAST : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WLAST : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal mig_7series_0_DDR3_ADDR : STD_LOGIC_VECTOR ( 13 downto 0 );
signal mig_7series_0_DDR3_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal mig_7series_0_DDR3_CAS_N : STD_LOGIC;
signal mig_7series_0_DDR3_CKE : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CK_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CK_P : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CS_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_DM : STD_LOGIC_VECTOR ( 7 downto 0 );
signal mig_7series_0_DDR3_DQ : STD_LOGIC_VECTOR ( 63 downto 0 );
signal mig_7series_0_DDR3_DQS_N : STD_LOGIC_VECTOR ( 7 downto 0 );
signal mig_7series_0_DDR3_DQS_P : STD_LOGIC_VECTOR ( 7 downto 0 );
signal mig_7series_0_DDR3_ODT : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_RAS_N : STD_LOGIC;
signal mig_7series_0_DDR3_RESET_N : STD_LOGIC;
signal mig_7series_0_DDR3_WE_N : STD_LOGIC;
signal mig_7series_0_mmcm_locked : STD_LOGIC;
signal mig_7series_0_ui_addn_clk_0 : STD_LOGIC;
signal mig_7series_0_ui_clk : STD_LOGIC;
signal mig_7series_0_ui_clk_sync_rst : STD_LOGIC;
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_1_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_1_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_rst_1 : STD_LOGIC;
signal NLW_mig_7series_0_init_calib_complete_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
DDR3_addr(13 downto 0) <= mig_7series_0_DDR3_ADDR(13 downto 0);
DDR3_ba(2 downto 0) <= mig_7series_0_DDR3_BA(2 downto 0);
DDR3_cas_n <= mig_7series_0_DDR3_CAS_N;
DDR3_ck_n(0) <= mig_7series_0_DDR3_CK_N(0);
DDR3_ck_p(0) <= mig_7series_0_DDR3_CK_P(0);
DDR3_cke(0) <= mig_7series_0_DDR3_CKE(0);
DDR3_cs_n(0) <= mig_7series_0_DDR3_CS_N(0);
DDR3_dm(7 downto 0) <= mig_7series_0_DDR3_DM(7 downto 0);
DDR3_odt(0) <= mig_7series_0_DDR3_ODT(0);
DDR3_ras_n <= mig_7series_0_DDR3_RAS_N;
DDR3_reset_n <= mig_7series_0_DDR3_RESET_N;
DDR3_we_n <= mig_7series_0_DDR3_WE_N;
S00_AXI_1_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
S00_AXI_1_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
S00_AXI_1_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
S00_AXI_1_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0);
S00_AXI_1_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
S00_AXI_1_ARLOCK(0) <= S00_AXI_arlock(0);
S00_AXI_1_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
S00_AXI_1_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
S00_AXI_1_ARREGION(3 downto 0) <= S00_AXI_arregion(3 downto 0);
S00_AXI_1_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
S00_AXI_1_ARVALID <= S00_AXI_arvalid;
S00_AXI_1_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
S00_AXI_1_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
S00_AXI_1_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
S00_AXI_1_AWID(3 downto 0) <= S00_AXI_awid(3 downto 0);
S00_AXI_1_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
S00_AXI_1_AWLOCK(0) <= S00_AXI_awlock(0);
S00_AXI_1_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
S00_AXI_1_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
S00_AXI_1_AWREGION(3 downto 0) <= S00_AXI_awregion(3 downto 0);
S00_AXI_1_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
S00_AXI_1_AWVALID <= S00_AXI_awvalid;
S00_AXI_1_BREADY <= S00_AXI_bready;
S00_AXI_1_RREADY <= S00_AXI_rready;
S00_AXI_1_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
S00_AXI_1_WLAST <= S00_AXI_wlast;
S00_AXI_1_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
S00_AXI_1_WVALID <= S00_AXI_wvalid;
S00_AXI_arready <= S00_AXI_1_ARREADY;
S00_AXI_awready <= S00_AXI_1_AWREADY;
S00_AXI_bid(3 downto 0) <= S00_AXI_1_BID(3 downto 0);
S00_AXI_bresp(1 downto 0) <= S00_AXI_1_BRESP(1 downto 0);
S00_AXI_bvalid <= S00_AXI_1_BVALID;
S00_AXI_rdata(31 downto 0) <= S00_AXI_1_RDATA(31 downto 0);
S00_AXI_rid(3 downto 0) <= S00_AXI_1_RID(3 downto 0);
S00_AXI_rlast <= S00_AXI_1_RLAST;
S00_AXI_rresp(1 downto 0) <= S00_AXI_1_RRESP(1 downto 0);
S00_AXI_rvalid <= S00_AXI_1_RVALID;
S00_AXI_wready <= S00_AXI_1_WREADY;
SYS_CLK_1_CLK_N <= SYS_CLK_clk_n;
SYS_CLK_1_CLK_P <= SYS_CLK_clk_p;
interconnect_aresetn(0) <= proc_sys_reset_1_interconnect_aresetn(0);
peripheral_aresetn(0) <= proc_sys_reset_1_peripheral_aresetn(0);
sys_rst_1 <= sys_rst;
ui_addn_clk_0 <= mig_7series_0_ui_addn_clk_0;
ui_clk_sync_rst <= mig_7series_0_ui_clk_sync_rst;
axi_interconnect_0: entity work.mig_wrap_axi_interconnect_0_0
port map (
ACLK => mig_7series_0_ui_addn_clk_0,
ARESETN => proc_sys_reset_1_interconnect_aresetn(0),
M00_ACLK => mig_7series_0_ui_clk,
M00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(3 downto 0) => axi_interconnect_0_M00_AXI_ARID(3 downto 0),
M00_AXI_arlen(7 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock => axi_interconnect_0_M00_AXI_ARLOCK,
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(3 downto 0) => axi_interconnect_0_M00_AXI_AWID(3 downto 0),
M00_AXI_awlen(7 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock => axi_interconnect_0_M00_AXI_AWLOCK,
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bid(3 downto 0) => axi_interconnect_0_M00_AXI_BID(3 downto 0),
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(3 downto 0) => axi_interconnect_0_M00_AXI_RID(3 downto 0),
M00_AXI_rlast => axi_interconnect_0_M00_AXI_RLAST,
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wlast => axi_interconnect_0_M00_AXI_WLAST,
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
S00_ACLK => mig_7series_0_ui_addn_clk_0,
S00_ARESETN => proc_sys_reset_1_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
S00_AXI_arid(3 downto 0) => S00_AXI_1_ARID(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_1_ARLEN(7 downto 0),
S00_AXI_arlock(0) => S00_AXI_1_ARLOCK(0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
S00_AXI_arready => S00_AXI_1_ARREADY,
S00_AXI_arregion(3 downto 0) => S00_AXI_1_ARREGION(3 downto 0),
S00_AXI_arsize(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
S00_AXI_arvalid => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
S00_AXI_awid(3 downto 0) => S00_AXI_1_AWID(3 downto 0),
S00_AXI_awlen(7 downto 0) => S00_AXI_1_AWLEN(7 downto 0),
S00_AXI_awlock(0) => S00_AXI_1_AWLOCK(0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
S00_AXI_awready => S00_AXI_1_AWREADY,
S00_AXI_awregion(3 downto 0) => S00_AXI_1_AWREGION(3 downto 0),
S00_AXI_awsize(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
S00_AXI_awvalid => S00_AXI_1_AWVALID,
S00_AXI_bid(3 downto 0) => S00_AXI_1_BID(3 downto 0),
S00_AXI_bready => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid => S00_AXI_1_BVALID,
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rid(3 downto 0) => S00_AXI_1_RID(3 downto 0),
S00_AXI_rlast => S00_AXI_1_RLAST,
S00_AXI_rready => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid => S00_AXI_1_RVALID,
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wlast => S00_AXI_1_WLAST,
S00_AXI_wready => S00_AXI_1_WREADY,
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid => S00_AXI_1_WVALID
);
mig_7series_0: component mig_wrap_mig_7series_0_0
port map (
aresetn => proc_sys_reset_0_peripheral_aresetn(0),
ddr3_addr(13 downto 0) => mig_7series_0_DDR3_ADDR(13 downto 0),
ddr3_ba(2 downto 0) => mig_7series_0_DDR3_BA(2 downto 0),
ddr3_cas_n => mig_7series_0_DDR3_CAS_N,
ddr3_ck_n(0) => mig_7series_0_DDR3_CK_N(0),
ddr3_ck_p(0) => mig_7series_0_DDR3_CK_P(0),
ddr3_cke(0) => mig_7series_0_DDR3_CKE(0),
ddr3_cs_n(0) => mig_7series_0_DDR3_CS_N(0),
ddr3_dm(7 downto 0) => mig_7series_0_DDR3_DM(7 downto 0),
ddr3_dq(63 downto 0) => DDR3_dq(63 downto 0),
ddr3_dqs_n(7 downto 0) => DDR3_dqs_n(7 downto 0),
ddr3_dqs_p(7 downto 0) => DDR3_dqs_p(7 downto 0),
ddr3_odt(0) => mig_7series_0_DDR3_ODT(0),
ddr3_ras_n => mig_7series_0_DDR3_RAS_N,
ddr3_reset_n => mig_7series_0_DDR3_RESET_N,
ddr3_we_n => mig_7series_0_DDR3_WE_N,
init_calib_complete => NLW_mig_7series_0_init_calib_complete_UNCONNECTED,
mmcm_locked => mig_7series_0_mmcm_locked,
s_axi_araddr(29 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(29 downto 0),
s_axi_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0),
s_axi_arid(3 downto 0) => axi_interconnect_0_M00_AXI_ARID(3 downto 0),
s_axi_arlen(7 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(7 downto 0),
s_axi_arlock => axi_interconnect_0_M00_AXI_ARLOCK,
s_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0),
s_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s_axi_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s_axi_awaddr(29 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(29 downto 0),
s_axi_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0),
s_axi_awid(3 downto 0) => axi_interconnect_0_M00_AXI_AWID(3 downto 0),
s_axi_awlen(7 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(7 downto 0),
s_axi_awlock => axi_interconnect_0_M00_AXI_AWLOCK,
s_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0),
s_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s_axi_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s_axi_bid(3 downto 0) => axi_interconnect_0_M00_AXI_BID(3 downto 0),
s_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s_axi_rid(3 downto 0) => axi_interconnect_0_M00_AXI_RID(3 downto 0),
s_axi_rlast => axi_interconnect_0_M00_AXI_RLAST,
s_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s_axi_wlast => axi_interconnect_0_M00_AXI_WLAST,
s_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID,
sys_clk_n => SYS_CLK_1_CLK_N,
sys_clk_p => SYS_CLK_1_CLK_P,
sys_rst => sys_rst_1,
ui_addn_clk_0 => mig_7series_0_ui_addn_clk_0,
ui_clk => mig_7series_0_ui_clk,
ui_clk_sync_rst => mig_7series_0_ui_clk_sync_rst
);
proc_sys_reset_0: component mig_wrap_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => mig_7series_0_mmcm_locked,
ext_reset_in => mig_7series_0_ui_clk_sync_rst,
interconnect_aresetn(0) => NLW_proc_sys_reset_0_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => mig_7series_0_ui_clk
);
proc_sys_reset_1: component mig_wrap_proc_sys_reset_1_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED(0),
dcm_locked => mig_7series_0_mmcm_locked,
ext_reset_in => mig_7series_0_ui_clk_sync_rst,
interconnect_aresetn(0) => proc_sys_reset_1_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_1_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_1_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => mig_7series_0_ui_addn_clk_0
);
end STRUCTURE;
|
mit
|
2d09ed951f3779de0f0c9799ee74841d
| 0.670608 | 2.818818 | false | false | false | false |
Ttl/pic16f84
|
testbenches/cpu_core_testalu_tb.vhd
| 1 | 2,546 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_core_testalu_tb IS
END cpu_core_testalu_tb;
ARCHITECTURE behavior OF cpu_core_testalu_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
PORT(
clk : IN std_logic;
reset : IN std_logic;
porta : INOUT std_logic_vector(4 downto 0);
portb : INOUT std_logic_vector(7 downto 0);
pc_out : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--BiDirs
signal porta : std_logic_vector(4 downto 0);
signal portb : std_logic_vector(7 downto 0);
--Outputs
signal pc_out : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cpu_core
Generic map(instruction_file => "scripts/instructions_testalu.mif")
PORT MAP (
clk => clk,
reset => reset,
porta => porta,
portb => portb,
pc_out => pc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for clk_period*10;
wait until rising_edge(clk);
reset <= '0';
wait for clk_period/2;
wait until pc_out = std_logic_vector(to_unsigned(14,13));
assert portb = std_logic_vector(to_unsigned(2,8)) report "Line 11, incf result wrong" severity failure;
wait until pc_out = std_logic_vector(to_unsigned(17,13));
assert portb = std_logic_vector(to_unsigned(0,8)) report "Line 14, subwf result wrong" severity failure;
wait until pc_out = std_logic_vector(to_unsigned(20,13));
assert portb = "00011111" report "Line 17, STATUS wrong" severity failure;
wait until pc_out = std_logic_vector(to_unsigned(24,13));
assert portb = std_logic_vector(to_unsigned(16,8)) report "Line 21, ADDWF wrong" severity failure;
wait until pc_out = std_logic_vector(to_unsigned(27,13));
assert portb = "00011010" report "Line 21, STATUS wrong" severity failure;
wait for clk_period;
reset <= '1';
assert false report "Success" severity note;
wait;
end process;
END;
|
lgpl-3.0
|
8d612c13a8c4bf60ee855716a72d08ba
| 0.618617 | 3.596045 | false | true | false | false |
a3f/r3k.vhdl
|
vhdl/tb/cpu_no_bus_tb.vhdl
| 1 | 8,903 |
-- SKIP because we need to buffer pipeline stages in registers first, I think
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
use work.memory_map.all;
entity cpu_no_bus_tb is
end;
architecture struct of cpu_no_bus_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
signal readreg1, readreg2 : reg_t := R0;
signal writereg: reg_t := R0;
signal regReadData1, regReadData2, regWriteData : word_t := ZERO;
signal regWrite : ctrl_t := '0';
component mem is
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic
);
end component;
component InstructionFetch is
generic(PC_ADD, CPI : natural; SINGLE_ADDRESS_SPACE : boolean);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end component;
component InstructionDecode is
port(
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread, memwrite : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
component Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end component;
component MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
component WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end component;
-- control signals
signal Link, Branch, JumpReg, JumpDir, memToreg, TakeBranch, Shift, ALUSrc, MemSex : ctrl_t;
signal MemRead, MemWrite : ctrl_memwidth_t;
signal memReadData : word_t;
signal new_pc : addr_t;
signal pc_plus_4, jump_addr, branch_addr : addr_t;
signal instr : instruction_t;
signal zeroxed, sexed, aluResult: word_t;
signal aluop : alu_op_t;
signal cpuclk : std_logic := '0';
signal regclk : std_logic := '0';
signal halt_cpu : boolean := false;
signal cpurst : std_logic := '0';
signal regrst : std_logic := '0';
signal done : boolean := false;
constant ESC : Character := Character'val(27);
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
begin
regFile1: regFile
port map(
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg, writedata => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => regclk, rst => regrst,
regWrite => regWrite
);
if1: InstructionFetch
generic map (PC_ADD => 4, CPI => 7, SINGLE_ADDRESS_SPACE => false)
port map(
clk => cpuclk,
rst => cpurst,
new_pc => new_pc,
pc_plus_4 => pc_plus_4,
instr => instr,
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr
);
mem_bus: mem port map (
addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
clk => cpuclk
);
id1: InstructionDecode
port map(instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr,
regwrite => regwrite, link => link, jumpreg => jumpreg, jumpdirect => jumpdir, branch => Branch,
memread => memread, memwrite => memwrite,
memtoreg => memtoreg, memsex => memsex,
shift => shift, alusrc => aluSrc,
aluop => aluOp,
readreg1 => readReg1, readreg2 => readReg2, writeReg => writeReg,
zeroxed => zeroxed, sexed => sexed,
clk => cpuclk,
rst => cpurst
);
ex1: Execute
port map(
pc_plus_4 => pc_plus_4,
regReadData1 => regReadData1, regReadData2 => regReadData2,
branch_addr => branch_addr,
branch_in => Branch,
shift_in => shift, alusrc_in => ALUSrc,
aluop_in => ALUOp,
zeroxed => zeroxed, sexed => sexed,
takeBranch => takeBranch,
ALUResult => ALUResult,
clk => cpuclk,
rst => cpurst
);
ma1: memoryAccess
port map(
-- inbound
Address_in => AluResult,
WriteData_in => regReadData2,
ReadData_in => memReadData,
MemRead_in => memRead, MemWrite_in => memWrite,
MemSex_in => memSex,
clk => cpuclk,
-- outbound to top level module
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr);
wb1: WriteBack
port map(
Link => Link,
JumpReg => JumpReg,
JumpDir => JumpDir,
MemToReg => MemToReg,
TakeBranch => TakeBranch,
pc_plus_4 => pc_plus_4,
branch_addr => branch_addr,
jump_addr => jump_addr,
aluResult => aluResult,
memReadData => memReadData,
regReadData1 => regReadData1,
regWriteData => regWriteData,
new_pc => new_pc);
test : process
begin
-- This halt_cpu thing doesn't work yet
--halt_cpu <= true;
--regrst <= '0';
--wait for 2 ns;
--regrst <= '1';
--wait for 2 ns;
--regrst <= '0';
--wait for 20 ns;
--readreg1 <= R1;
--wait for 2 ns;
--assert regReadData1 = ZERO report
-- ANSI_RED "Failed to reset. 0 /= " & to_hstring(regReadData1) & ANSI_NONE
--severity error;
--halt_cpu <= false;
cpurst <= '0';
wait for 2 ns;
cpurst <= '1';
wait for 2 ns;
cpurst <= '0';
wait for 60 ns;
cpurst <= '0';
--halt_cpu <= true;
readreg1 <= R1;
wait for 8 ns;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
readreg1 <= R1;
readreg2 <= R2;
wait for 8 ns;
assert regReadData2 = X"0000_FBAD" report
ANSI_RED & "Failed to ori. 0xFBAD /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
done <= true;
wait;
end process;
clkproc: process
begin
regclk <= not regclk;
if not halt_cpu then
cpuclk <= not cpuclk;
end if;
wait for 1 ns;
if done then wait; end if;
end process;
end struct;
|
gpl-3.0
|
bfe48ee0f9521571f5441efc70745722
| 0.509154 | 4.116043 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP_Bonus_feu_rouge/L3TP5/fsm.vhd
| 1 | 2,413 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:38:51 10/03/2014
-- Design Name:
-- Module Name: fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm is
Port ( clk : in STD_LOGIC;
cpt : in STD_LOGIC_VECTOR (3 downto 0);
travaux : in STD_LOGIC;
reset_cpt : out STD_LOGIC;
Led : out STD_LOGIC_VECTOR (7 downto 0));
end fsm;
architecture Behavioral of fsm is
signal Led_i : STD_LOGIC_VECTOR (7 downto 0);
type state_type is (RV, RO, VR, ORE,ORANGE_ON, ORANGE_OFF);
signal state, next_state: state_type;
signal reset_cpt_i : STD_LOGIC;
begin
Next_ouptut : process (state,cpt)
begin
-- init des tous les signaux inter..
Led_i <="11111111";
reset_cpt_i<='0';
case state is
when RV =>
Led_i<="10000001";
when RO =>
Led_i<="10000010";
reset_cpt_i<='1';
when VR =>
Led_i<="00100100";
when ORE =>
Led_i <="01000001";
when ORANGE_ON =>
Led_i<="01000010";
when ORANGE_OFF =>
Led_i<="00000000";
when others =>
Led_i<="10100101";
end case;
end process;
synchro : process (clk)
begin
if clk'event and clk='1' then
-- changement d etat
state <=next_state;
-- mise a jour des ports de sortie
Led <=Led_i;
reset_cpt<=reset_cpt_i;
end if;
end process;
next_node : process (state,cpt)
begin
next_state<=state;
case state is
when RV =>
if travaux ='1' then
next_state<= ORANGE_ON;
else
next_state<=RO;
end if;
when RO =>
next_state<=VR;
when VR =>
if cpt="0110" then
next_state<=ORE;
else
next_state<=VR;
end if;
when ORE =>
next_state<=RV;
when ORANGE_ON =>
if travaux = '0' then
next_state<=RO;
else
next_state<=ORANGE_OFF;
end if;
when ORANGE_OFF =>
next_state<=ORANGE_ON;
when others =>
next_state<=RV;
end case;
end process;
end Behavioral;
|
gpl-2.0
|
e59e2aa8c79e97bc5b363ec8bd8f4473
| 0.606299 | 3.125648 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_input_buffer/sim/fifo_generator_input_buffer.vhd
| 1 | 33,811 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_input_buffer IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_input_buffer;
ARCHITECTURE fifo_generator_input_buffer_arch OF fifo_generator_input_buffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4093,
C_PROG_FULL_THRESH_NEGATE_VAL => 4092,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_input_buffer_arch;
|
bsd-3-clause
|
9d8427b619ec91038f363c60ecc574ae
| 0.608382 | 3.074286 | false | false | false | false |
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