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andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_1_0/synth/mig_wrap_proc_sys_reset_1_0.vhd
| 1 | 6,622 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mig_wrap_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_1_0;
ARCHITECTURE mig_wrap_proc_sys_reset_1_0_arch OF mig_wrap_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mig_wrap_proc_sys_reset_1_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mig_wrap_proc_sys_reset_1_0_arch : ARCHITECTURE IS "mig_wrap_proc_sys_reset_1_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mig_wrap_proc_sys_reset_1_0_arch: ARCHITECTURE IS "mig_wrap_proc_sys_reset_1_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=virtex7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "virtex7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_1_0_arch;
|
mit
|
ac64d2d4c727f9ef429eb21089957121
| 0.713078 | 3.463389 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/Invert.vhd
| 1 | 4,258 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 01/30/2017 10:24:00 AM
-- Design Name: Invert Filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter inverts the image passing through the filter. This is
-- done by taking the make RGB value and subtracting the actual from
-- the max, creating the inverse of the RGB value.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Invert Architecture Design
architecture Behavioral of Video_Box is
--Complete RGB value
signal full_const : unsigned(7 downto 0):= "11111111";
--Inverted signals for the red, green, and blue values
signal red_i,green_i,blue_i : unsigned(7 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--Take the max value and subtract away the RGB values to invert the image
red_i <= full_const - unsigned(RGB_IN_reg(23 downto 16));
green_i <= full_const - unsigned(RGB_IN_reg(15 downto 8));
blue_i <= full_const - unsigned(RGB_IN_reg(7 downto 0));
--Concatenate the inverted Red, Green, and Blue values together
--Route the inverted RGB values out
USER_LOGIC <= std_logic_vector(red_i&green_i&blue_i);
--Pass all the other signals through the region
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
end Behavioral;
--End Invert Architecture Design
|
bsd-3-clause
|
d7d14333a8717a77b68474226497db2a
| 0.625881 | 3.363349 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_uart.vhd
| 1 | 13,682 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's UART Core.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_uart_pack.all;
--! The Plasma-SoC's Universeral Asynchronous Rceiver and
--! Transmitter is implemented so that the CPU can perform
--! 8N1 serial transactions with a host computer. The serial transactions
--! are useful for printing detailed statuses, debugging problems related
--! to software, and in-circuit serial programming. The UART Core depends
--! on the UART developed by (THE AUTHOR'S NAME AND INFORMATION NEEDS TO BE
--! ADDED LATER) for its essential functionality. In other words, the UART Core
--! acts as a wrapper so that the UART has an Master AXI4-Lite interface and
--! and interruption capabilities.
--!
--! The UART Core behaves like any other UART. In order to take advantage of
--! this core, the CPU must read and write to the core's register space. The
--! Control register doesn't actually require any configuration. Instead, the
--! control bits Status In Avail and Status Out Avail indicate the status of the
--! UART Core. If Status In Avail is high, then 8-bit data is available in the In Fifo
--! register. If Status Out Avail is high, then 8-bit data can be written to the Out
--! Fifo Avail register. Both the In Fifo Avail and Out Fifo Avail registers have a width
--! of axi_data_width, however the data is always the least significant bits.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_uart is
generic (
fifo_depth : integer := 8; --! Defines the number of 8-bit words that can be bufferred for each of the respective input and output queues.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
axi_control_offset : integer := 0; --! Defines the offset for the Control register.
axi_control_status_in_avail_bit_loc : integer := 0; --! Defines the bit location of Status In Avail in the Control register.
axi_control_status_out_avail_bit_loc : integer := 1; --! Defines the bit location of Status Out Avail in the Control register.
axi_in_fifo_offset : integer := 4; --! Defines the offset of the In Fifo register.
axi_out_fifo_offset : integer := 8; --! Defines the offset of the Out Fifo register.
baud : positive := 115200; --! The baud rate of the UART.
clock_frequency : positive := 50000000 --! The frequency of the input clock aclk.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low. Technically supposed to be asynchronous, however asynchronous resets aren't used.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- UART interface.
tx : out std_logic; --! Serially sends bits at the rate approximately equal to the baud. The communication protocol is always 8N1.
rx : in std_logic; --! Serially receives bits at the rate approximately equal to the baud. The communication protocol should always be 8N1.
-- CPU interface.
status_in_avail : out std_logic --! A signal indicating the state of the Status In Avail bit in the Control register. This signal can be used to interrupt the CPU.
);
end plasoc_uart;
architecture Behavioral of plasoc_uart is
component uart is
generic (
baud : positive;
clock_frequency : positive
);
port (
clock : in std_logic;
nreset : in std_logic;
data_stream_in : in std_logic_vector(7 downto 0);
data_stream_in_stb : in std_logic;
data_stream_in_ack : out std_logic;
data_stream_out : out std_logic_vector(7 downto 0);
data_stream_out_stb : out std_logic;
tx : out std_logic;
rx : in std_logic
);
end component;
component plasoc_uart_axi4_write_cntrl is
generic (
fifo_depth : integer := 8;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_status_in_avail_bit_loc : integer := 0;
reg_control_status_out_avail_bit_loc : integer := 1;
reg_in_fifo_offset : std_logic_vector := X"0004";
reg_out_fifo_offset : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
reg_out_fifo : out std_logic_vector(7 downto 0);
reg_out_fifo_valid : out std_logic;
reg_out_fifo_ready : in std_logic;
reg_in_avail : out std_logic);
end component;
component plasoc_uart_axi4_read_cntrl is
generic (
fifo_depth : integer := 8;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_status_in_avail_bit_loc : integer := 0;
reg_control_status_out_avail_bit_loc : integer := 1;
reg_in_fifo_offset : std_logic_vector := X"0004";
reg_out_fifo_offset : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
reg_control_status_in_avail : out std_logic;
reg_control_status_out_avail : in std_logic;
reg_in_fifo : in std_logic_vector(7 downto 0);
reg_in_valid : in std_logic;
reg_in_ready : out std_logic);
end component;
constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width));
constant axi_in_fifo_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_in_fifo_offset,axi_address_width));
constant axi_out_fifo_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_out_fifo_offset,axi_address_width));
signal out_fifo : std_logic_vector(7 downto 0);
signal out_fifo_valid : std_logic;
signal out_fifo_ready : std_logic;
signal in_fifo : std_logic_vector(7 downto 0);
signal in_fifo_valid : std_logic;
signal in_fifo_ready : std_logic;
signal reg_in_avail : std_logic;
begin
uart_inst : uart
generic map (
baud => baud,
clock_frequency => clock_frequency)
port map (
clock => aclk,
nreset => aresetn,
data_stream_in => out_fifo,
data_stream_in_stb => out_fifo_valid,
data_stream_in_ack => out_fifo_ready,
data_stream_out => in_fifo,
data_stream_out_stb => in_fifo_valid,
tx => tx, rx => rx);
plasoc_uart_axi4_write_cntrl_inst : plasoc_uart_axi4_write_cntrl
generic map (
fifo_depth => fifo_depth,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_status_in_avail_bit_loc => axi_control_status_in_avail_bit_loc,
reg_control_status_out_avail_bit_loc => axi_control_status_out_avail_bit_loc,
reg_in_fifo_offset => axi_in_fifo_offset_slv,
reg_out_fifo_offset => axi_out_fifo_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
reg_out_fifo => out_fifo,
reg_out_fifo_valid => out_fifo_valid,
reg_out_fifo_ready => out_fifo_ready,
reg_in_avail => reg_in_avail);
plasoc_uart_axi4_read_cntrl_inst : plasoc_uart_axi4_read_cntrl
generic map (
fifo_depth => fifo_depth,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_status_in_avail_bit_loc => axi_control_status_in_avail_bit_loc,
reg_control_status_out_avail_bit_loc => axi_control_status_out_avail_bit_loc,
reg_in_fifo_offset => axi_in_fifo_offset_slv,
reg_out_fifo_offset => axi_out_fifo_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
reg_control_status_in_avail => status_in_avail,
reg_control_status_out_avail => reg_in_avail,
reg_in_fifo => in_fifo,
reg_in_valid => in_fifo_valid,
reg_in_ready => in_fifo_ready);
end Behavioral;
|
mit
|
2e3a710b10206a852c24110fcbbaf57c
| 0.541003 | 4.217633 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_crossbar_base.vhd
| 1 | 3,030 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! the base crossbar component of the Plasma-SoC's
--! AXI Crossbar.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity plasoc_crossbar_base is
generic (
width : integer := 16;
input_amount : integer := 2;
output_amount : integer := 2);
port (
inputs : in std_logic_vector(width*input_amount-1 downto 0);
enables : in std_logic_vector(input_amount*output_amount-1 downto 0);
outputs : out std_logic_vector(width*output_amount-1 downto 0));
end plasoc_crossbar_base;
architecture Behavioral of plasoc_crossbar_base is
subtype word_type is std_logic_vector(width-1 downto 0);
type input_vector_type is array(0 to input_amount-1) of word_type;
type output_vector_type is array(0 to output_amount-1) of word_type;
type tristate_type is array(0 to input_amount-1) of output_vector_type;
signal input_vector : input_vector_type := (others=>(others=>'0'));
signal output_vector : output_vector_type := (others=>(others=>'0'));
signal tristate_matrix : tristate_type := (others=>(others=>(others=>'Z')));
begin
-- Connect the tristate array.
gen_output_col:
for each_col in 0 to output_amount-1 generate
gen_output_row:
for each_row in 0 to input_amount-1 generate
output_vector(each_col) <= tristate_matrix(each_row)(each_col);
end generate gen_output_row;
end generate gen_output_col;
-- Convert inputs into input vector.
process (inputs)
variable input_vector_buff : input_vector_type;
begin
for each_word in 0 to input_amount-1 loop
input_vector_buff(each_word) := inputs((1+each_word)*width-1 downto each_word*width);
end loop;
input_vector <= input_vector_buff;
end process;
-- Convert output vector to outputs.
process (output_vector)
variable outputs_buff : std_logic_vector(width*output_amount-1 downto 0);
begin
for each_word in 0 to output_amount-1 loop
outputs_buff((1+each_word)*width-1 downto each_word*width) := output_vector(each_word);
end loop;
outputs <= outputs_buff;
end process;
-- Set the tristates based on the enables.
process (input_vector,enables)
variable tristate_matrix_buff : tristate_type;
begin
for each_col in 0 to output_amount-1 loop
for each_row in 0 to input_amount-1 loop
if enables(each_row+each_col*input_amount)='1' then
tristate_matrix_buff(each_row)(each_col) := input_vector(each_row);
else
tristate_matrix_buff(each_row)(each_col) := (others=>'Z');
end if;
end loop;
end loop;
tristate_matrix <= tristate_matrix_buff;
end process;
end Behavioral;
|
mit
|
5c18926f3cd98b7b6c0fe54afef68b49
| 0.613531 | 3.929961 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP3_Roulette/ipcore_dir/timer/simulation/timer_tb.vhd
| 1 | 4,818 |
-- file: timer_tb.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity timer_tb is
end timer_tb;
architecture test of timer_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
signal COUNTER_RESET : std_logic := '0';
component timer_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : timer_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT);
end test;
|
gpl-2.0
|
94007c1340b714152180159c950f0428
| 0.650477 | 4.391978 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_mm2s_cmdsts_if.vhd
| 4 | 15,457 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
bsd-3-clause
|
f004905a3d5bc18a3a231cd0377030b4
| 0.44323 | 4.387454 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/src/PmodNAV_axi_gpio_0_0/synth/PmodNAV_axi_gpio_0_0.vhd
| 1 | 10,488 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_11;
USE axi_gpio_v2_0_11.axi_gpio;
ENTITY PmodNAV_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END PmodNAV_axi_gpio_0_0;
ARCHITECTURE PmodNAV_axi_gpio_0_0_arch OF PmodNAV_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodNAV_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF PmodNAV_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF PmodNAV_axi_gpio_0_0_arch : ARCHITECTURE IS "PmodNAV_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF PmodNAV_axi_gpio_0_0_arch: ARCHITECTURE IS "PmodNAV_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=1,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x0000000F,C_TRI_DEFAULT=0x00000000,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0x00000001}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 1,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"0000000F",
C_TRI_DEFAULT => X"00000000",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"00000001"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i,
gpio2_io_o => gpio2_io_o,
gpio2_io_t => gpio2_io_t
);
END PmodNAV_axi_gpio_0_0_arch;
|
bsd-3-clause
|
a3fd1f9e2e795b681d9d7ebe8525fa66
| 0.687166 | 3.135426 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/boot_pack.vhd
| 2 | 13,895 |
library ieee;
use ieee.std_logic_1164.all;
package boot_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 398;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body boot_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C1C0001";
ram_buffer(1) := X"279C8630";
ram_buffer(2) := X"3C050000";
ram_buffer(3) := X"24A50638";
ram_buffer(4) := X"3C040000";
ram_buffer(5) := X"24840A94";
ram_buffer(6) := X"3C1D0000";
ram_buffer(7) := X"27BD0838";
ram_buffer(8) := X"ACA00000";
ram_buffer(9) := X"00A4182A";
ram_buffer(10) := X"1460FFFD";
ram_buffer(11) := X"24A50004";
ram_buffer(12) := X"0C00007C";
ram_buffer(13) := X"00000000";
ram_buffer(14) := X"0800000E";
ram_buffer(15) := X"23BDFF98";
ram_buffer(16) := X"AFA10010";
ram_buffer(17) := X"AFA20014";
ram_buffer(18) := X"AFA30018";
ram_buffer(19) := X"AFA4001C";
ram_buffer(20) := X"AFA50020";
ram_buffer(21) := X"AFA60024";
ram_buffer(22) := X"AFA70028";
ram_buffer(23) := X"AFA8002C";
ram_buffer(24) := X"AFA90030";
ram_buffer(25) := X"AFAA0034";
ram_buffer(26) := X"AFAB0038";
ram_buffer(27) := X"AFAC003C";
ram_buffer(28) := X"AFAD0040";
ram_buffer(29) := X"AFAE0044";
ram_buffer(30) := X"AFAF0048";
ram_buffer(31) := X"AFB8004C";
ram_buffer(32) := X"AFB90050";
ram_buffer(33) := X"AFBF0054";
ram_buffer(34) := X"401A7000";
ram_buffer(35) := X"235AFFFC";
ram_buffer(36) := X"AFBA0058";
ram_buffer(37) := X"0000D810";
ram_buffer(38) := X"AFBB005C";
ram_buffer(39) := X"0000D812";
ram_buffer(40) := X"AFBB0060";
ram_buffer(41) := X"0C0000D9";
ram_buffer(42) := X"23A50000";
ram_buffer(43) := X"8FA10010";
ram_buffer(44) := X"8FA20014";
ram_buffer(45) := X"8FA30018";
ram_buffer(46) := X"8FA4001C";
ram_buffer(47) := X"8FA50020";
ram_buffer(48) := X"8FA60024";
ram_buffer(49) := X"8FA70028";
ram_buffer(50) := X"8FA8002C";
ram_buffer(51) := X"8FA90030";
ram_buffer(52) := X"8FAA0034";
ram_buffer(53) := X"8FAB0038";
ram_buffer(54) := X"8FAC003C";
ram_buffer(55) := X"8FAD0040";
ram_buffer(56) := X"8FAE0044";
ram_buffer(57) := X"8FAF0048";
ram_buffer(58) := X"8FB8004C";
ram_buffer(59) := X"8FB90050";
ram_buffer(60) := X"8FBF0054";
ram_buffer(61) := X"8FBA0058";
ram_buffer(62) := X"8FBB005C";
ram_buffer(63) := X"03600011";
ram_buffer(64) := X"8FBB0060";
ram_buffer(65) := X"03600013";
ram_buffer(66) := X"23BD0068";
ram_buffer(67) := X"341B0001";
ram_buffer(68) := X"03400008";
ram_buffer(69) := X"409B6000";
ram_buffer(70) := X"40026000";
ram_buffer(71) := X"03E00008";
ram_buffer(72) := X"40846000";
ram_buffer(73) := X"3C050000";
ram_buffer(74) := X"24A50150";
ram_buffer(75) := X"8CA60000";
ram_buffer(76) := X"AC06003C";
ram_buffer(77) := X"8CA60004";
ram_buffer(78) := X"AC060040";
ram_buffer(79) := X"8CA60008";
ram_buffer(80) := X"AC060044";
ram_buffer(81) := X"8CA6000C";
ram_buffer(82) := X"03E00008";
ram_buffer(83) := X"AC060048";
ram_buffer(84) := X"3C1A0000";
ram_buffer(85) := X"375A003C";
ram_buffer(86) := X"03400008";
ram_buffer(87) := X"00000000";
ram_buffer(88) := X"AC900000";
ram_buffer(89) := X"AC910004";
ram_buffer(90) := X"AC920008";
ram_buffer(91) := X"AC93000C";
ram_buffer(92) := X"AC940010";
ram_buffer(93) := X"AC950014";
ram_buffer(94) := X"AC960018";
ram_buffer(95) := X"AC97001C";
ram_buffer(96) := X"AC9E0020";
ram_buffer(97) := X"AC9C0024";
ram_buffer(98) := X"AC9D0028";
ram_buffer(99) := X"AC9F002C";
ram_buffer(100) := X"03E00008";
ram_buffer(101) := X"34020000";
ram_buffer(102) := X"8C900000";
ram_buffer(103) := X"8C910004";
ram_buffer(104) := X"8C920008";
ram_buffer(105) := X"8C93000C";
ram_buffer(106) := X"8C940010";
ram_buffer(107) := X"8C950014";
ram_buffer(108) := X"8C960018";
ram_buffer(109) := X"8C97001C";
ram_buffer(110) := X"8C9E0020";
ram_buffer(111) := X"8C9C0024";
ram_buffer(112) := X"8C9D0028";
ram_buffer(113) := X"8C9F002C";
ram_buffer(114) := X"03E00008";
ram_buffer(115) := X"34A20000";
ram_buffer(116) := X"00850019";
ram_buffer(117) := X"00001012";
ram_buffer(118) := X"00002010";
ram_buffer(119) := X"03E00008";
ram_buffer(120) := X"ACC40000";
ram_buffer(121) := X"0000000C";
ram_buffer(122) := X"03E00008";
ram_buffer(123) := X"00000000";
ram_buffer(124) := X"3C040000";
ram_buffer(125) := X"27BDFFE8";
ram_buffer(126) := X"AFBF0014";
ram_buffer(127) := X"0C0000F6";
ram_buffer(128) := X"24840214";
ram_buffer(129) := X"8FBF0014";
ram_buffer(130) := X"00001025";
ram_buffer(131) := X"03E00008";
ram_buffer(132) := X"27BD0018";
ram_buffer(133) := X"27BDFFC0";
ram_buffer(134) := X"AFB30024";
ram_buffer(135) := X"3C13F0F0";
ram_buffer(136) := X"AFB70034";
ram_buffer(137) := X"AFB60030";
ram_buffer(138) := X"AFB5002C";
ram_buffer(139) := X"AFBF003C";
ram_buffer(140) := X"AFBE0038";
ram_buffer(141) := X"AFB40028";
ram_buffer(142) := X"AFB20020";
ram_buffer(143) := X"AFB1001C";
ram_buffer(144) := X"AFB00018";
ram_buffer(145) := X"3673F0F0";
ram_buffer(146) := X"3C160100";
ram_buffer(147) := X"241500E6";
ram_buffer(148) := X"24170003";
ram_buffer(149) := X"0C00015F";
ram_buffer(150) := X"00000000";
ram_buffer(151) := X"1453FFFD";
ram_buffer(152) := X"00000000";
ram_buffer(153) := X"0C000129";
ram_buffer(154) := X"24040001";
ram_buffer(155) := X"3C110100";
ram_buffer(156) := X"00008025";
ram_buffer(157) := X"3C120100";
ram_buffer(158) := X"0C00015F";
ram_buffer(159) := X"00000000";
ram_buffer(160) := X"0C000133";
ram_buffer(161) := X"0040A025";
ram_buffer(162) := X"0C000133";
ram_buffer(163) := X"AFA20010";
ram_buffer(164) := X"16A00002";
ram_buffer(165) := X"0295001B";
ram_buffer(166) := X"0007000D";
ram_buffer(167) := X"8FA30010";
ram_buffer(168) := X"305E00FF";
ram_buffer(169) := X"306300FF";
ram_buffer(170) := X"00001010";
ram_buffer(171) := X"1462000B";
ram_buffer(172) := X"24040002";
ram_buffer(173) := X"AE340000";
ram_buffer(174) := X"16170016";
ram_buffer(175) := X"26310004";
ram_buffer(176) := X"02402825";
ram_buffer(177) := X"24060010";
ram_buffer(178) := X"0C000174";
ram_buffer(179) := X"24040004";
ram_buffer(180) := X"02209025";
ram_buffer(181) := X"00008025";
ram_buffer(182) := X"24040001";
ram_buffer(183) := X"0C000129";
ram_buffer(184) := X"00000000";
ram_buffer(185) := X"24020002";
ram_buffer(186) := X"17C2FFE3";
ram_buffer(187) := X"24060010";
ram_buffer(188) := X"02402825";
ram_buffer(189) := X"0C000174";
ram_buffer(190) := X"24040004";
ram_buffer(191) := X"0C00011C";
ram_buffer(192) := X"00000000";
ram_buffer(193) := X"02C00008";
ram_buffer(194) := X"00000000";
ram_buffer(195) := X"1000FFD1";
ram_buffer(196) := X"00000000";
ram_buffer(197) := X"1000FFF0";
ram_buffer(198) := X"26100001";
ram_buffer(199) := X"8F828010";
ram_buffer(200) := X"00000000";
ram_buffer(201) := X"8C440004";
ram_buffer(202) := X"8F82800C";
ram_buffer(203) := X"8F838008";
ram_buffer(204) := X"24420001";
ram_buffer(205) := X"304201FF";
ram_buffer(206) := X"10430008";
ram_buffer(207) := X"00000000";
ram_buffer(208) := X"8F83800C";
ram_buffer(209) := X"3C050000";
ram_buffer(210) := X"24A50850";
ram_buffer(211) := X"308400FF";
ram_buffer(212) := X"00651821";
ram_buffer(213) := X"A0640000";
ram_buffer(214) := X"AF82800C";
ram_buffer(215) := X"03E00008";
ram_buffer(216) := X"00000000";
ram_buffer(217) := X"3C030000";
ram_buffer(218) := X"8C620A50";
ram_buffer(219) := X"27BDFFE0";
ram_buffer(220) := X"8C420004";
ram_buffer(221) := X"AFB10018";
ram_buffer(222) := X"3C110000";
ram_buffer(223) := X"AFB00014";
ram_buffer(224) := X"AFBF001C";
ram_buffer(225) := X"00608025";
ram_buffer(226) := X"26310A54";
ram_buffer(227) := X"2C430008";
ram_buffer(228) := X"14600006";
ram_buffer(229) := X"00000000";
ram_buffer(230) := X"8FBF001C";
ram_buffer(231) := X"8FB10018";
ram_buffer(232) := X"8FB00014";
ram_buffer(233) := X"03E00008";
ram_buffer(234) := X"27BD0020";
ram_buffer(235) := X"000210C0";
ram_buffer(236) := X"02221021";
ram_buffer(237) := X"8C430000";
ram_buffer(238) := X"8C440004";
ram_buffer(239) := X"0060F809";
ram_buffer(240) := X"00000000";
ram_buffer(241) := X"8E020A50";
ram_buffer(242) := X"00000000";
ram_buffer(243) := X"8C420004";
ram_buffer(244) := X"1000FFEF";
ram_buffer(245) := X"2C430008";
ram_buffer(246) := X"27BDFFE8";
ram_buffer(247) := X"3C0244A0";
ram_buffer(248) := X"3C030000";
ram_buffer(249) := X"AC620A50";
ram_buffer(250) := X"AFB00010";
ram_buffer(251) := X"3C020000";
ram_buffer(252) := X"00808025";
ram_buffer(253) := X"3C040000";
ram_buffer(254) := X"AFBF0014";
ram_buffer(255) := X"24420A54";
ram_buffer(256) := X"24840A94";
ram_buffer(257) := X"24420008";
ram_buffer(258) := X"1444FFFE";
ram_buffer(259) := X"AC40FFF8";
ram_buffer(260) := X"3C0244A4";
ram_buffer(261) := X"AF828010";
ram_buffer(262) := X"3C020000";
ram_buffer(263) := X"24640A50";
ram_buffer(264) := X"2442031C";
ram_buffer(265) := X"AC82001C";
ram_buffer(266) := X"AC800020";
ram_buffer(267) := X"8C630A50";
ram_buffer(268) := X"24040001";
ram_buffer(269) := X"8C620000";
ram_buffer(270) := X"00000000";
ram_buffer(271) := X"34420008";
ram_buffer(272) := X"0C000046";
ram_buffer(273) := X"AC620000";
ram_buffer(274) := X"12000005";
ram_buffer(275) := X"0200C825";
ram_buffer(276) := X"8FBF0014";
ram_buffer(277) := X"8FB00010";
ram_buffer(278) := X"03200008";
ram_buffer(279) := X"27BD0018";
ram_buffer(280) := X"8FBF0014";
ram_buffer(281) := X"8FB00010";
ram_buffer(282) := X"03E00008";
ram_buffer(283) := X"27BD0018";
ram_buffer(284) := X"27BDFFE8";
ram_buffer(285) := X"AFBF0014";
ram_buffer(286) := X"0C000046";
ram_buffer(287) := X"00002025";
ram_buffer(288) := X"3C020000";
ram_buffer(289) := X"8C430A50";
ram_buffer(290) := X"8FBF0014";
ram_buffer(291) := X"8C620000";
ram_buffer(292) := X"2404FFF7";
ram_buffer(293) := X"00441024";
ram_buffer(294) := X"AC620000";
ram_buffer(295) := X"03E00008";
ram_buffer(296) := X"27BD0018";
ram_buffer(297) := X"8F838010";
ram_buffer(298) := X"00000000";
ram_buffer(299) := X"8C620000";
ram_buffer(300) := X"00000000";
ram_buffer(301) := X"30420002";
ram_buffer(302) := X"1040FFFC";
ram_buffer(303) := X"00000000";
ram_buffer(304) := X"AC640008";
ram_buffer(305) := X"03E00008";
ram_buffer(306) := X"00000000";
ram_buffer(307) := X"27BDFFE8";
ram_buffer(308) := X"AFBF0014";
ram_buffer(309) := X"AFB00010";
ram_buffer(310) := X"0C000046";
ram_buffer(311) := X"00002025";
ram_buffer(312) := X"8F83800C";
ram_buffer(313) := X"8F828008";
ram_buffer(314) := X"00000000";
ram_buffer(315) := X"14620005";
ram_buffer(316) := X"00000000";
ram_buffer(317) := X"0C000046";
ram_buffer(318) := X"24040001";
ram_buffer(319) := X"1000FFF6";
ram_buffer(320) := X"00000000";
ram_buffer(321) := X"8F828008";
ram_buffer(322) := X"3C030000";
ram_buffer(323) := X"24630850";
ram_buffer(324) := X"00431021";
ram_buffer(325) := X"90500000";
ram_buffer(326) := X"8F828008";
ram_buffer(327) := X"24040001";
ram_buffer(328) := X"24420001";
ram_buffer(329) := X"304201FF";
ram_buffer(330) := X"AF828008";
ram_buffer(331) := X"0C000046";
ram_buffer(332) := X"321000FF";
ram_buffer(333) := X"8FBF0014";
ram_buffer(334) := X"02001025";
ram_buffer(335) := X"8FB00010";
ram_buffer(336) := X"03E00008";
ram_buffer(337) := X"27BD0018";
ram_buffer(338) := X"27BDFFE8";
ram_buffer(339) := X"00803025";
ram_buffer(340) := X"24050004";
ram_buffer(341) := X"AFBF0014";
ram_buffer(342) := X"0C000129";
ram_buffer(343) := X"30C400FF";
ram_buffer(344) := X"24A5FFFF";
ram_buffer(345) := X"14A0FFFC";
ram_buffer(346) := X"00063202";
ram_buffer(347) := X"8FBF0014";
ram_buffer(348) := X"00000000";
ram_buffer(349) := X"03E00008";
ram_buffer(350) := X"27BD0018";
ram_buffer(351) := X"27BDFFE0";
ram_buffer(352) := X"AFB20018";
ram_buffer(353) := X"AFB10014";
ram_buffer(354) := X"AFB00010";
ram_buffer(355) := X"AFBF001C";
ram_buffer(356) := X"00008025";
ram_buffer(357) := X"00008825";
ram_buffer(358) := X"24120020";
ram_buffer(359) := X"0C000133";
ram_buffer(360) := X"00000000";
ram_buffer(361) := X"02021004";
ram_buffer(362) := X"26100008";
ram_buffer(363) := X"1612FFFB";
ram_buffer(364) := X"02228825";
ram_buffer(365) := X"8FBF001C";
ram_buffer(366) := X"02201025";
ram_buffer(367) := X"8FB20018";
ram_buffer(368) := X"8FB10014";
ram_buffer(369) := X"8FB00010";
ram_buffer(370) := X"03E00008";
ram_buffer(371) := X"27BD0020";
ram_buffer(372) := X"10C0000C";
ram_buffer(373) := X"00C53021";
ram_buffer(374) := X"2402FFF0";
ram_buffer(375) := X"00C21824";
ram_buffer(376) := X"0066302B";
ram_buffer(377) := X"00A22824";
ram_buffer(378) := X"00063100";
ram_buffer(379) := X"24620010";
ram_buffer(380) := X"00463021";
ram_buffer(381) := X"2484FF00";
ram_buffer(382) := X"2402FFF0";
ram_buffer(383) := X"14C50003";
ram_buffer(384) := X"00A21824";
ram_buffer(385) := X"03E00008";
ram_buffer(386) := X"00000000";
ram_buffer(387) := X"AC830000";
ram_buffer(388) := X"AC600000";
ram_buffer(389) := X"1000FFF9";
ram_buffer(390) := X"24A50010";
ram_buffer(391) := X"00000000";
ram_buffer(392) := X"00000100";
ram_buffer(393) := X"01010001";
ram_buffer(394) := X"00000000";
ram_buffer(395) := X"00000000";
ram_buffer(396) := X"00000000";
ram_buffer(397) := X"00000000";
return ram_buffer;
end;
end;
|
mit
|
16cbce7edbd2ec028d58f660af29de2a
| 0.61792 | 2.307756 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_rst_module.vhd
| 4 | 24,259 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_dma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000
-- Scatter Gather clock frequency in hertz
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
----------------------------------------------------------------------- --
-- Soft Reset --
----------------------------------------------------------------------- --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_all_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_all_idle : in std_logic ; --
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_mm2s_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
mm2s_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
mm2s_cntrl_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
mm2s_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
--
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_s2mm_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
s2mm_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
s2mm_sts_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
s2mm_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out
----------------------------------------------------------------------- --
-- AXI Scatter Gather Reset Out
m_axi_sg_aresetn : out std_logic := '1' ; --
-- AXI Scatter Gather Datamover Reset Out
dm_m_axi_sg_aresetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_hrdresetn : out std_logic := '1' ; --
s_axi_lite_resetn : out std_logic := '1' --
);
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of s_axi_lite_resetn : signal is "TRUE";
Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no";
end axi_dma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
ATTRIBUTE async_reg : STRING;
signal hrd_resetn_i_cdc_tig : std_logic := '1';
signal hrd_resetn_i_d1_cdc_tig : std_logic := '1';
--ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true";
-- Soft reset support
signal mm2s_soft_reset_clr : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
signal soft_reset_clr_i : std_logic := '0';
signal mm2s_soft_reset_done : std_logic := '0';
signal s2mm_soft_reset_done : std_logic := '0';
signal mm2s_scndry_resetn_i : std_logic := '0';
signal s2mm_scndry_resetn_i : std_logic := '0';
signal dm_mm2s_scndry_resetn_i : std_logic := '0';
signal dm_s2mm_scndry_resetn_i : std_logic := '0';
signal sg_hard_reset : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register hard reset in
REG_HRD_RST : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => sg_hard_reset,
scndry_vect_out => open
);
m_axi_sg_hrdresetn <= sg_hard_reset;
--REG_HRD_RST : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- hrd_resetn_i_cdc_tig <= axi_resetn;
-- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig;
-- end if;
-- end process REG_HRD_RST;
-- Regsiter hard reset out for axi lite interface
REG_HRD_RST_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s_axi_lite_resetn,
scndry_vect_out => open
);
--REG_HRD_RST_OUT : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig;
-- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig;
-- end if;
-- end process REG_HRD_RST_OUT;
dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i;
dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i;
-- mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface (default)
MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate
begin
-- both must be low before sg reset is asserted.
m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_BOTH;
-- Only s2mm channel included therefore map secondary resets to
-- from s2mm reset module to scatter gather interface
MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate
begin
m_axi_sg_aresetn <= s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_S2MM;
-- Only mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface
MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= mm2s_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i;
end generate MAP_SG_FOR_MM2S;
-- Invalid configuration for axi dma - simply here for completeness
MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= '1';
dm_m_axi_sg_aresetn <= '1';
end generate MAP_NO_SG;
s2mm_scndry_resetn <= s2mm_scndry_resetn_i;
mm2s_scndry_resetn <= mm2s_scndry_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
RESET_I : entity axi_dma_v7_1_8.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_mm2s_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
-- Secondary Reset
scndry_resetn => mm2s_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_mm2s_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_mm2s_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => mm2s_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => mm2s_cntrl_reset_out_n
);
-- Sample an hold mm2s soft reset done to use in
-- combined reset done to DMACR
MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
mm2s_soft_reset_done <= '0';
elsif(mm2s_soft_reset_clr = '1')then
mm2s_soft_reset_done <= '1';
end if;
end if;
end process MM2S_SOFT_RST_DONE;
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_reset_out_n <= '1';
mm2s_cntrl_reset_out_n <= '1';
dm_mm2s_scndry_resetn_i <= '1';
dm_mm2s_prmry_resetn <= '1';
mm2s_prmry_resetn <= '1';
mm2s_scndry_resetn_i <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
mm2s_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
RESET_I : entity axi_dma_v7_1_8.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_s2mm_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
-- Secondary Reset
scndry_resetn => s2mm_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_s2mm_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_s2mm_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => s2mm_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => s2mm_sts_reset_out_n
);
-- Sample an hold s2mm soft reset done to use in
-- combined reset done to DMACR
S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
s2mm_soft_reset_done <= '0';
elsif(s2mm_soft_reset_clr = '1')then
s2mm_soft_reset_done <= '1';
end if;
end if;
end process S2MM_SOFT_RST_DONE;
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_reset_out_n <= '1';
dm_s2mm_scndry_resetn_i <= '1';
dm_s2mm_prmry_resetn <= '1';
s2mm_prmry_resetn <= '1';
s2mm_scndry_resetn_i <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
s2mm_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_S2MM;
-- When both mm2s and s2mm are done then drive soft reset clear and
-- also clear s_h registers above
soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done;
soft_reset_clr <= soft_reset_clr_i;
end implementation;
|
bsd-3-clause
|
f73be027480680dcf8a564e88c77177d
| 0.421946 | 4.422789 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/AXI_DPTI_1.0/src/DPTI_To_AXI_S_Converter.vhd
| 1 | 13,287 |
------------------------------------------------------------------------------
--
-- File: DPTI_to_AXI_S_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module reads data from the DPTI interface and converts it so that it is
-- compatible with the AXI STREAM interface. Along with 32 bit TDATA, it also generates
-- the 4 bit TKEEP, TVALID and TLAST, using TREADY as an input. On the DPTI side,
-- it uses the interface clock PROG_CLK, it reads data from pDataIn and uses pRxf
-- to identify valid data and it generates the output enable pOe signal and pRd which
-- requests more data. All these ports will be connected to the DPTI ports in the top.
-- The pDataIn bus will also pass through an IOBUF controlled by pOe. The converter works
-- by reading a data byte fron the DPTI, it then determines if the data is valid,
-- and if it is, it then uses it to create the TDATA bus and the TKEEP bus. The module
-- will wait until it has 4 valid bytes in order to avoid sending incomplete transfers,
-- except for the last transfer which can be incomplete due to the nature of the length
-- which is requested (if the number is not divisible by 4). When a transfer is prepared,
-- the TVALID signal is generated which acomplishes the actual transfer along with the
-- TLAST signal when the transfer is the last one. During this time, it monitors the
-- TREADY signal as well as pRxf signal coming from the DPTI interface. In order to
-- control the module, two AXI Lite registers are used, one for direction/control and
-- one for the lenght of the transfer, which are synchronized in the top module.
-- The module also uses a reset signal aResetRx which is generated in the top module.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;
entity DPTI_to_AXI_S_converter is
Port (
-- clock, reset and DPTI signals
pResetRx : in std_logic;
PROG_CLK : in std_logic;
pRxf : in std_logic;
pRd : out std_logic;
pOe : out std_logic;
pDataIn : in std_logic_vector (7 downto 0);
-- AXI Stream signals
pInTready : in std_logic;
pOutTdata : out std_logic_vector (31 downto 0);
pOutTvalid : out std_logic;
pOutTlast : out std_logic;
pOutTkeep : out std_logic_vector (3 downto 0);
-- AXI Lite registers
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pRxLengthEmpty : out std_logic
);
end DPTI_to_AXI_S_converter;
architecture Behavioral of DPTI_to_AXI_S_converter is
--------------------------------------------------------------------------------------------------------------------------
signal Index: integer range 0 to 3;
signal pCountSentBytes : std_logic_vector (1 downto 0);
signal pCountBytesIncrFlag : std_logic := '1';
signal pRxEnDir : std_logic := '0';
signal pLengthRxCnt : std_logic_vector (23 downto 0);
signal pCtlRd : std_logic := '1';
signal pCtlOutTvalid : std_logic := '0';
signal pCtlOutTlast : std_logic := '0';
signal pLengthRxCntDepletedFlag : std_logic := '0';
signal pAuxLengthRxDecrFlag : std_logic := '0';
signal pLastTransferFlag : std_logic := '0';
signal pRxfDelay : std_logic := '1';
--------------------------------------------------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------------------------------------------------
pOutTlast <= pCtlOutTlast;
pOutTvalid <= pCtlOutTvalid;
pOe <= not pRxEnDir ;
pRd <= pCtlRd;
pCtlOutTvalid <= '1' when pCountSentBytes = 0 and pCountBytesIncrFlag = '0' else '0'; -- TVALID signal is generated
-- pCountSentBytes = 0 - allows TVALID to be '1' only after 4 valid data bytes have been processed
-- pCountBytesIncrFlag = '0' - This signal will ensure that the TVALID signal is high for only one Clock period. It checks if the current byte is valid or not. The counter will only increment when the data byte is valid.
pCtlOutTlast <= '1' when pCountSentBytes = 0 and pCountBytesIncrFlag = '0' and pLengthRxCnt < 4 else '0'; -- TLAST signal is generated
-- TLAST is very similar to TVALID however it must only be asserted at the end of the last AXI STREAM transfer. In order to accomplish this, pLengthRxCnt must be less than 4 (no more than 4 bytes left to transfer) so that only one more STREAM transfer is needed.
pCtlRd <= '0' when pLastTransferFlag = '0' and pInTready = '1' and pRxfDelay = '0' else '1'; -- PROG_RDN is generated
-- the signal must be 0 only when TREADY (input) is '1' since that means that the STREAM interface is ready for at least one extra set of data since the date currently being read will be transfered in the next AXI STREAM transfer
-- pLastTransferFlag indicatges that only one more transfer will be required. Once this signal is '1' this indicates that there is no more data required for the dpti to stream transfer
-- pRxfDelay will mirror the PROG_RXEN signal received from the DPTI interface. when the FTDI empties its internal FIFO, it will drive PROG_RXEN high and even if the FPGA can still receive data, PROG_RDN must be driven high, otherwise the FTDI will provide the wrong data when PROG_RXEN becomes '0'
pLastTransferFlag <= '1' when pLengthRxCnt < 4 else '0'; -- This signal will indicate when the module has reached the last AXI Stream transfer. If there are less than 4 bytes left to be transfered
-- this signal is used to determine when there is only one STREAM transfer left
pRxLengthEmpty <= '1' when pLengthRxCnt = 0 else '0'; -- this signal (used by driver) will indicate the status of the module. when high, the module is ready to do another transfer
--------------------------------------------------------------------------------------------------------------------------
generate_pRxfDelay: process(PROG_CLK) -- the signal pRxfDelay will be identical to PROG_RXEN delayed by one clock period which will then become the PROG_RDN signal.
begin
if rising_edge (PROG_CLK) then
if pRxf = '1' then
pRxfDelay <= '1';
else
pRxfDelay <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pCountSentBytes: process (PROG_CLK, pResetRx) -- this counter will increment when a valid byte was read from the DPTI interface and processed
begin
if pResetRx = '0' then
pCountSentBytes <= (others => '0');
elsif rising_edge(PROG_CLK) then
if pLengthRxCnt > 0 and ((pRxf = '0' and pRxfDelay = '0') or pLastTransferFlag = '1') and pInTready = '1' then -- check if a transfer is in progress and all the conditions are in place to read and process a byte
pCountSentBytes <= pCountSentBytes + '1'; -- the counter is incremented
pCountBytesIncrFlag <= '0'; -- the flag which indicates a change in the counter's value
elsif pLengthRxCnt = 0 then -- if a transfer was completed
pCountSentBytes <= (others => '0'); -- counter is reset
pCountBytesIncrFlag <= '1'; -- flag is set
else
pCountSentBytes <= pCountSentBytes; -- when a transfer is in progress and conditions for a valid byte to be processed are not met
pCountBytesIncrFlag <= '1'; -- flag is set
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_Index: process (PROG_CLK, pResetRx) -- the Index integer is used for positioning the individual bytes in the 4 byte TDATA register
begin
if pResetRx = '0' then
Index <= 0;
elsif rising_edge(PROG_CLK) then
if pLengthRxCnt > 0 and pRxf = '0' and pRxfDelay = '0' and pInTready = '1' then -- in order to increment Index, the data provided must be valid and the receivind FIFO must not be full
if Index < 3 then -- index will have values between 0 and 3
Index <= Index + 1; -- when conditions are met, index is incremented
else
Index <= 0;
end if;
elsif pLengthRxCnt = 0 then -- when a transfer is completed, Index becomes 0
Index <= 0;
else
Index <= Index;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pOutTdata: process (PROG_CLK, pResetRx, Index, pLengthRxCnt) is -- TDATA is generated from data received from the DPTI interface
begin
if (pResetRx = '0') then
pOutTdata <= (others => '0');
elsif rising_edge(PROG_CLK) then
if pLengthRxCnt > 3 and pRxEnDir = '1' and pRxf = '0' and pRxfDelay = '0' and pInTready = '1' then -- conditions for data to be considered valid
pOutTdata(( 8 * (Index + 1)) - 1 downto ( 8 * (Index))) <= pDataIn(7 downto 0); -- TDATA bus is being built. the new byte's position is determined by the value of Index
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
gen_pOutTkeep_read_AXI_Lite_registers: process (PROG_CLK, pResetRx, Index, pLengthRxCnt) is -- reading the AXI Lite registers, controlling the main counters, generating TKEEP
begin
if (pResetRx = '0') then
pLengthRxCnt <= (others => '0');
elsif rising_edge(PROG_CLK) then
if pOvalidControl = '1' and pLengthRxCnt = 0 then -- the control bit (and the direction) can only be changed when the module is idle
pRxEnDir <= pAXI_L_Control (1); -- Reading control byte from AXI LITE register. Bit (1) sets the transfer's direction.
end if;
if pOvalidLength = '1' and pRxEnDir = '1' then -- checking if the module was enabled and if valid value is present in the LENGTH register
pLengthRxCnt (23 downto 0) <= pAXI_L_Length(23 downto 0) + "11"; -- The counter will be the requested transfer length + 3 so that after all of the valid bytes are received and processed, there will be 3 more clock periods where it will decrement which will allow us to generate the signals required to send the last STREAM transfer, especially TLAST.
end if;
if pLengthRxCnt > 0 and (pLastTransferFlag = '1' or (pRxf = '0' and pRxfDelay = '0' and pInTready = '1')) then -- here the module checks if the byte received is valid or if we are going to send the last STREAM package
pLengthRxCnt <= pLengthRxCnt - '1'; -- the counter is decremented.
end if;
if pLengthRxCnt > 3 and pRxf = '0' and pRxfDelay = '0' and pInTready = '1' then -- check when a valid byte has been read from the DPTI interface
pOutTkeep (Index) <= '1'; -- the TKEEP bit of the byte sent to AXI STREAM in the "generate_pOutTdata" process is set
else
pOutTkeep (Index) <= '0'; -- if the byte is not valid, the bit will be '0'
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
end Behavioral;
|
bsd-3-clause
|
1c18a4b0c647d81b65c173f7a7ec897e
| 0.633702 | 4.600762 | false | false | false | false |
tmeissner/cryptocores
|
des/rtl/vhdl/des.vhd
| 1 | 23,212 |
-- ======================================================================
-- DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity des is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 to 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end entity des;
architecture rtl of des is
begin
PipeG : if design_type = "PIPE" generate
begin
crypt : process (clk_i, reset_i) is
-- variables for key calculation
variable c0 : std_logic_vector(0 to 27) := (others => '0');
variable c1 : std_logic_vector(0 to 27) := (others => '0');
variable c2 : std_logic_vector(0 to 27) := (others => '0');
variable c3 : std_logic_vector(0 to 27) := (others => '0');
variable c4 : std_logic_vector(0 to 27) := (others => '0');
variable c5 : std_logic_vector(0 to 27) := (others => '0');
variable c6 : std_logic_vector(0 to 27) := (others => '0');
variable c7 : std_logic_vector(0 to 27) := (others => '0');
variable c8 : std_logic_vector(0 to 27) := (others => '0');
variable c9 : std_logic_vector(0 to 27) := (others => '0');
variable c10 : std_logic_vector(0 to 27) := (others => '0');
variable c11 : std_logic_vector(0 to 27) := (others => '0');
variable c12 : std_logic_vector(0 to 27) := (others => '0');
variable c13 : std_logic_vector(0 to 27) := (others => '0');
variable c14 : std_logic_vector(0 to 27) := (others => '0');
variable c15 : std_logic_vector(0 to 27) := (others => '0');
variable c16 : std_logic_vector(0 to 27) := (others => '0');
variable d0 : std_logic_vector(0 to 27) := (others => '0');
variable d1 : std_logic_vector(0 to 27) := (others => '0');
variable d2 : std_logic_vector(0 to 27) := (others => '0');
variable d3 : std_logic_vector(0 to 27) := (others => '0');
variable d4 : std_logic_vector(0 to 27) := (others => '0');
variable d5 : std_logic_vector(0 to 27) := (others => '0');
variable d6 : std_logic_vector(0 to 27) := (others => '0');
variable d7 : std_logic_vector(0 to 27) := (others => '0');
variable d8 : std_logic_vector(0 to 27) := (others => '0');
variable d9 : std_logic_vector(0 to 27) := (others => '0');
variable d10 : std_logic_vector(0 to 27) := (others => '0');
variable d11 : std_logic_vector(0 to 27) := (others => '0');
variable d12 : std_logic_vector(0 to 27) := (others => '0');
variable d13 : std_logic_vector(0 to 27) := (others => '0');
variable d14 : std_logic_vector(0 to 27) := (others => '0');
variable d15 : std_logic_vector(0 to 27) := (others => '0');
variable d16 : std_logic_vector(0 to 27) := (others => '0');
-- key variables
variable key1 : std_logic_vector(0 to 47) := (others => '0');
variable key2 : std_logic_vector(0 to 47) := (others => '0');
variable key3 : std_logic_vector(0 to 47) := (others => '0');
variable key4 : std_logic_vector(0 to 47) := (others => '0');
variable key5 : std_logic_vector(0 to 47) := (others => '0');
variable key6 : std_logic_vector(0 to 47) := (others => '0');
variable key7 : std_logic_vector(0 to 47) := (others => '0');
variable key8 : std_logic_vector(0 to 47) := (others => '0');
variable key9 : std_logic_vector(0 to 47) := (others => '0');
variable key10 : std_logic_vector(0 to 47) := (others => '0');
variable key11 : std_logic_vector(0 to 47) := (others => '0');
variable key12 : std_logic_vector(0 to 47) := (others => '0');
variable key13 : std_logic_vector(0 to 47) := (others => '0');
variable key14 : std_logic_vector(0 to 47) := (others => '0');
variable key15 : std_logic_vector(0 to 47) := (others => '0');
variable key16 : std_logic_vector(0 to 47) := (others => '0');
-- variables for left & right data blocks
variable l0 : std_logic_vector( 0 to 31) := (others => '0');
variable l1 : std_logic_vector( 0 to 31) := (others => '0');
variable l2 : std_logic_vector( 0 to 31) := (others => '0');
variable l3 : std_logic_vector( 0 to 31) := (others => '0');
variable l4 : std_logic_vector( 0 to 31) := (others => '0');
variable l5 : std_logic_vector( 0 to 31) := (others => '0');
variable l6 : std_logic_vector( 0 to 31) := (others => '0');
variable l7 : std_logic_vector( 0 to 31) := (others => '0');
variable l8 : std_logic_vector( 0 to 31) := (others => '0');
variable l9 : std_logic_vector( 0 to 31) := (others => '0');
variable l10 : std_logic_vector( 0 to 31) := (others => '0');
variable l11 : std_logic_vector( 0 to 31) := (others => '0');
variable l12 : std_logic_vector( 0 to 31) := (others => '0');
variable l13 : std_logic_vector( 0 to 31) := (others => '0');
variable l14 : std_logic_vector( 0 to 31) := (others => '0');
variable l15 : std_logic_vector( 0 to 31) := (others => '0');
variable l16 : std_logic_vector( 0 to 31) := (others => '0');
variable r0 : std_logic_vector( 0 to 31) := (others => '0');
variable r1 : std_logic_vector( 0 to 31) := (others => '0');
variable r2 : std_logic_vector( 0 to 31) := (others => '0');
variable r3 : std_logic_vector( 0 to 31) := (others => '0');
variable r4 : std_logic_vector( 0 to 31) := (others => '0');
variable r5 : std_logic_vector( 0 to 31) := (others => '0');
variable r6 : std_logic_vector( 0 to 31) := (others => '0');
variable r7 : std_logic_vector( 0 to 31) := (others => '0');
variable r8 : std_logic_vector( 0 to 31) := (others => '0');
variable r9 : std_logic_vector( 0 to 31) := (others => '0');
variable r10 : std_logic_vector( 0 to 31) := (others => '0');
variable r11 : std_logic_vector( 0 to 31) := (others => '0');
variable r12 : std_logic_vector( 0 to 31) := (others => '0');
variable r13 : std_logic_vector( 0 to 31) := (others => '0');
variable r14 : std_logic_vector( 0 to 31) := (others => '0');
variable r15 : std_logic_vector( 0 to 31) := (others => '0');
variable r16 : std_logic_vector( 0 to 31) := (others => '0');
-- variables for mode & valid shift registers
variable mode : std_logic_vector(0 to 16) := (others => '0');
variable valid : std_logic_vector(0 to 17) := (others => '0');
begin
if(reset_i = '0') then
data_o <= (others => '0');
valid_o <= '0';
elsif rising_edge( clk_i ) then
-- shift registers
valid(1 to 17) := valid(0 to 16);
valid(0) := valid_i;
mode(1 to 16) := mode(0 to 15);
mode(0) := mode_i;
-- output stage
accept_o <= '1';
valid_o <= valid(17);
data_o <= ipn( ( r16 & l16 ) );
-- 16. stage
if mode(16) = '0' then
c16 := c15(1 to 27) & c15(0);
d16 := d15(1 to 27) & d15(0);
else
c16 := c15(27) & c15(0 to 26);
d16 := d15(27) & d15(0 to 26);
end if;
key16 := pc2( ( c16 & d16 ) );
l16 := r15;
r16 := l15 xor ( f( r15, key16 ) );
-- 15. stage
if mode(15) = '0' then
c15 := c14(2 to 27) & c14(0 to 1);
d15 := d14(2 to 27) & d14(0 to 1);
else
c15 := c14(26 to 27) & c14(0 to 25);
d15 := d14(26 to 27) & d14(0 to 25);
end if;
key15 := pc2( ( c15 & d15 ) );
l15 := r14;
r15 := l14 xor ( f( r14, key15 ) );
-- 14. stage
if mode(14) = '0' then
c14 := c13(2 to 27) & c13(0 to 1);
d14 := d13(2 to 27) & d13(0 to 1);
else
c14 := c13(26 to 27) & c13(0 to 25);
d14 := d13(26 to 27) & d13(0 to 25);
end if;
key14 := pc2( ( c14 & d14 ) );
l14 := r13;
r14 := l13 xor ( f( r13, key14 ) );
-- 13. stage
if mode(13) = '0' then
c13 := c12(2 to 27) & c12(0 to 1);
d13 := d12(2 to 27) & d12(0 to 1);
else
c13 := c12(26 to 27) & c12(0 to 25);
d13 := d12(26 to 27) & d12(0 to 25);
end if;
key13 := pc2( ( c13 & d13 ) );
l13 := r12;
r13 := l12 xor ( f( r12, key13 ) );
-- 12. stage
if mode(12) = '0' then
c12 := c11(2 to 27) & c11(0 to 1);
d12 := d11(2 to 27) & d11(0 to 1);
else
c12 := c11(26 to 27) & c11(0 to 25);
d12 := d11(26 to 27) & d11(0 to 25);
end if;
key12 := pc2( ( c12 & d12 ) );
l12 := r11;
r12 := l11 xor ( f( r11, key12 ) );
-- 11. stage
if mode(11) = '0' then
c11 := c10(2 to 27) & c10(0 to 1);
d11 := d10(2 to 27) & d10(0 to 1);
else
c11 := c10(26 to 27) & c10(0 to 25);
d11 := d10(26 to 27) & d10(0 to 25);
end if;
key11 := pc2( ( c11 & d11 ) );
l11 := r10;
r11 := l10 xor ( f( r10, key11 ) );
-- 10. stage
if mode(10) = '0' then
c10 := c9(2 to 27) & c9(0 to 1);
d10 := d9(2 to 27) & d9(0 to 1);
else
c10 := c9(26 to 27) & c9(0 to 25);
d10 := d9(26 to 27) & d9(0 to 25);
end if;
key10 := pc2( ( c10 & d10 ) );
l10 := r9;
r10 := l9 xor ( f( r9, key10 ) );
-- 9. stage
if mode(9) = '0' then
c9 := c8(1 to 27) & c8(0);
d9 := d8(1 to 27) & d8(0);
else
c9 := c8(27) & c8(0 to 26);
d9 := d8(27) & d8(0 to 26);
end if;
key9 := pc2( ( c9 & d9 ) );
l9 := r8;
r9 := l8 xor ( f( r8, key9 ) );
-- 8. stage
if mode(8) = '0' then
c8 := c7(2 to 27) & c7(0 to 1);
d8 := d7(2 to 27) & d7(0 to 1);
else
c8 := c7(26 to 27) & c7(0 to 25);
d8 := d7(26 to 27) & d7(0 to 25);
end if;
key8 := pc2( ( c8 & d8 ) );
l8 := r7;
r8 := l7 xor ( f( r7, key8 ) );
-- 7. stage
if mode(7) = '0' then
c7 := c6(2 to 27) & c6(0 to 1);
d7 := d6(2 to 27) & d6(0 to 1);
else
c7 := c6(26 to 27) & c6(0 to 25);
d7 := d6(26 to 27) & d6(0 to 25);
end if;
key7 := pc2( ( c7 & d7 ) );
l7 := r6;
r7 := l6 xor ( f( r6, key7 ) );
-- 6. stage
if mode(6) = '0' then
c6 := c5(2 to 27) & c5(0 to 1);
d6 := d5(2 to 27) & d5(0 to 1);
else
c6 := c5(26 to 27) & c5(0 to 25);
d6 := d5(26 to 27) & d5(0 to 25);
end if;
key6 := pc2( ( c6 & d6 ) );
l6 := r5;
r6 := l5 xor ( f( r5, key6 ) );
-- 5. stage
if mode(5) = '0' then
c5 := c4(2 to 27) & c4(0 to 1);
d5 := d4(2 to 27) & d4(0 to 1);
else
c5 := c4(26 to 27) & c4(0 to 25);
d5 := d4(26 to 27) & d4(0 to 25);
end if;
key5 := pc2( ( c5 & d5 ) );
l5 := r4;
r5 := l4 xor ( f( r4, key5 ) );
-- 4. stage
if mode(4) = '0' then
c4 := c3(2 to 27) & c3(0 to 1);
d4 := d3(2 to 27) & d3(0 to 1);
else
c4 := c3(26 to 27) & c3(0 to 25);
d4 := d3(26 to 27) & d3(0 to 25);
end if;
key4 := pc2( ( c4 & d4 ) );
l4 := r3;
r4 := l3 xor ( f( r3, key4 ) );
-- 3. stage
if mode(3) = '0' then
c3 := c2(2 to 27) & c2(0 to 1);
d3 := d2(2 to 27) & d2(0 to 1);
else
c3 := c2(26 to 27) & c2(0 to 25);
d3 := d2(26 to 27) & d2(0 to 25);
end if;
key3 := pc2( ( c3 & d3 ) );
l3 := r2;
r3 := l2 xor ( f( r2, key3 ) );
-- 2. stage
if mode(2) = '0' then
c2 := c1(1 to 27) & c1(0);
d2 := d1(1 to 27) & d1(0);
else
c2 := c1(27) & c1(0 to 26);
d2 := d1(27) & d1(0 to 26);
end if;
key2 := pc2( ( c2 & d2 ) );
l2 := r1;
r2 := l1 xor ( f( r1, key2 ) );
-- 1. stage
if mode(1) = '0' then
c1 := c0(1 to 27) & c0(0);
d1 := d0(1 to 27) & d0(0);
else
c1 := c0;
d1 := d0;
end if;
key1 := pc2( ( c1 & d1 ) );
l1 := r0;
r1 := l0 xor ( f( r0, key1 ) );
-- input stage
l0 := ip( data_i )(0 to 31);
r0 := ip( data_i )(32 to 63);
c0 := pc1_c( key_i );
d0 := pc1_d( key_i );
end if;
end process crypt;
end generate PipeG;
AreaG : if design_type = "ITER" generate
signal s_accept : std_logic;
signal s_valid : std_logic;
signal s_l : std_logic_vector( 0 to 31);
signal s_r : std_logic_vector( 0 to 31);
begin
cryptP : process (clk_i, reset_i) is
variable v_c : std_logic_vector(0 to 27);
variable v_d : std_logic_vector(0 to 27);
variable v_key : std_logic_vector(0 to 47);
variable v_mode : std_logic;
variable v_rnd_cnt : natural;
begin
if(reset_i = '0') then
v_c := (others => '0');
v_d := (others => '0');
v_key := (others => '0');
s_l <= (others => '0');
s_r <= (others => '0');
v_rnd_cnt := 0;
v_mode := '0';
s_accept <= '0';
s_valid <= '0';
elsif rising_edge(clk_i) then
case v_rnd_cnt is
-- input stage
when 0 =>
s_accept <= '1';
s_valid <= '0';
if (valid_i = '1' and s_accept = '1') then
s_accept <= '0';
s_valid <= '0';
s_l <= ip(data_i)(0 to 31);
s_r <= ip(data_i)(32 to 63);
v_c := pc1_c(key_i);
v_d := pc1_d(key_i);
v_mode := mode_i;
v_rnd_cnt := v_rnd_cnt + 1;
end if;
-- stage 1
when 1 =>
if (v_mode = '0') then
v_c := v_c(1 to 27) & v_c(0);
v_d := v_d(1 to 27) & v_d(0);
end if;
v_key := pc2((v_c & v_d));
s_l <= s_r;
s_r <= s_l xor (f(s_r, v_key));
v_rnd_cnt := v_rnd_cnt + 1;
when 2 =>
if (v_mode = '0') then
v_c := v_c(1 to 27) & v_c(0);
v_d := v_d(1 to 27) & v_d(0);
else
v_c := v_c(27) & v_c(0 to 26);
v_d := v_d(27) & v_d(0 to 26);
end if;
v_key := pc2((v_c & v_d));
s_l <= s_r;
s_r <= s_l xor (f(s_r, v_key));
v_rnd_cnt := v_rnd_cnt + 1;
when 3 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 4 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 5 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 6 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 7 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 8 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 9 =>
if (v_mode = '0') then
v_c := v_c(1 to 27) & v_c(0);
v_d := v_d(1 to 27) & v_d(0);
else
v_c := v_c(27) & v_c(0 to 26);
v_d := v_d(27) & v_d(0 to 26);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 10 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 11 =>
-- 11. stage
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 12 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 13 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 14 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 15 =>
if (v_mode = '0') then
v_c := v_c(2 to 27) & v_c(0 to 1);
v_d := v_d(2 to 27) & v_d(0 to 1);
else
v_c := v_c(26 to 27) & v_c(0 to 25);
v_d := v_d(26 to 27) & v_d(0 to 25);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 16 =>
if (v_mode = '0') then
v_c := v_c(1 to 27) & v_c(0);
v_d := v_d(1 to 27) & v_d(0);
else
v_c := v_c(27) & v_c(0 to 26);
v_d := v_d(27) & v_d(0 to 26);
end if;
v_key := pc2( ( v_c & v_d ) );
s_l <= s_r;
s_r <= s_l xor ( f( s_r, v_key ) );
v_rnd_cnt := v_rnd_cnt + 1;
when 17 =>
s_valid <= '1';
if (s_valid = '1') then
if(accept_i = '1') then
s_valid <= '0';
v_rnd_cnt := 0;
end if;
end if;
when others =>
null;
end case;
end if;
end process cryptP;
valid_o <= s_valid;
accept_o <= s_accept;
data_o <= ipn(s_r & s_l) when s_valid = '1' else (others => '0');
end generate AreaG;
end architecture rtl;
|
gpl-2.0
|
29f325a4d5f75d4540932839f9e126be
| 0.411037 | 2.874551 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP3_roulette_vhdl/roulette.vhd
| 1 | 3,846 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:25:25 10/17/2014
-- Design Name:
-- Module Name: roulette - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity roulette is
Port ( switches : in STD_LOGIC_VECTOR (7 downto 0);
btn : in STD_LOGIC_VECTOR (2 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC);
end roulette;
architecture Behavioral of roulette is
signal position: std_logic_vector(7 downto 0);
signal afficheur_in : std_logic_vector(15 downto 0);
signal random : std_logic_vector(3 downto 0);
signal clk100, clk3, rnvp, E190: std_logic;
signal fvj, state, E190_3 : std_logic;
signal chenillard: std_logic_vector(7 downto 0);
COMPONENT rdm
PORT(
clk : IN std_logic;
E : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT afficheur
PORT( clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
sevenseg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
anodes : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
COMPONENT pulse
PORT( outp : OUT STD_LOGIC;
inp : IN STD_LOGIC;
clk : IN STD_LOGIC;
E : IN STD_LOGIC);
END COMPONENT;
COMPONENT enable190
PORT( clk : IN STD_LOGIC;
enable190 : OUT STD_LOGIC);
END COMPONENT;
COMPONENT timer
PORT(
CLK_IN1 : IN std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic
);
END COMPONENT;
COMPONENT decodeur3_8
PORT(
A : IN std_logic_vector(3 downto 0);
D : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT shiftled
PORT(
clk : IN std_logic;
E : IN std_logic;
Q : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT fsm
PORT(
clk : IN std_logic;
J : IN std_logic;
K : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
begin
led<= position when state = '1' else chenillard;
afficheur_in <= x"FFFF" when position=switches else x"0000";
Inst_shiftled: shiftled PORT MAP(
clk => clk3,
E => E190_3,
Q => chenillard
);
Inst_fsm: fsm PORT MAP(
clk => clk100,
J => rnvp,
K => fvj,
Q => state
);
btn1_pulse: pulse PORT MAP(
inp => btn(1),
clk => clk100,
outp => fvj, -- faites vos jeux
E => E190
);
shift_enable: Enable190 PORT MAP(
Enable190 => E190_3,
clk => clk3
);
Inst_decodeur3_8: decodeur3_8 PORT MAP(
A => random,
D => position
);
Inst_rdm: rdm PORT MAP(
clk =>clk100 ,
E => rnvp,
Q => random
);
mon_afficheur: afficheur PORT MAP(
clk => clk100,
din => afficheur_in,
sevenseg => sevenseg,
anodes => anodes
);
btn0_pulse: pulse PORT MAP(
outp => rnvp,
inp => btn(0),
clk => clk100,
E => E190
);
mon_enable: enable190 PORT MAP(
clk => clk100,
enable190 => E190
);
Inst_timer: timer PORT MAP(
CLK_IN1 => clk,
CLK_OUT1 => clk100,
CLK_OUT2 => clk3
);
end Behavioral;
|
gpl-2.0
|
12d670a5cffcbda276b4bf6087da1b35
| 0.569423 | 3.234651 | false | false | false | false |
makestuff/vga_test
|
vhdl/clk_gen/s3board/clk_gen.vhdl
| 1 | 2,961 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.1
-- \ \ Application : xaw2vhdl
-- / / Filename : clk_gen.vhd
-- /___/ /\ Timestamp : 05/07/2013 12:25:48
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st /home/chris/makestuff/hdlmake/apps/makestuff/vga_test/vhdl/clk_gen/./clk_gen.xaw /home/chris/makestuff/hdlmake/apps/makestuff/vga_test/vhdl/clk_gen/./clk_gen
--Design Name: clk_gen
--Device: xc3s200-5ft256
--
-- Module clk_gen
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clk_gen is
port ( CLKIN_IN : in std_logic;
CLKDV_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end clk_gen;
architecture BEHAVIORAL of clk_gen is
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (I=>CLKDV_BUF,
O=>CLKDV_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_INST : DCM
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"8080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>CLKDV_BUF,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
gpl-3.0
|
d82fdd01468f74bac7bc23113ddf4726
| 0.470787 | 3.757614 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_axi4_full2lite_read_cntrl.vhd
| 1 | 5,558 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Full2Lite Core's Read Controller. Please refer to the documentation
--! in plasoc_axi4_full2lite.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.plasoc_axi4_full2lite_pack.all;
entity plasoc_axi4_full2lite_read_cntrl is
generic (
axi_slave_id_width : integer := 1;
axi_address_width : integer := 32;
axi_data_width : integer := 32);
port(
aclk : in std_logic;
aresetn : in std_logic;
s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
s_axi_arlen : in std_logic_vector(8-1 downto 0);
s_axi_arsize : in std_logic_vector(3-1 downto 0);
s_axi_arburst : in std_logic_vector(2-1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(4-1 downto 0);
s_axi_arprot : in std_logic_vector(3-1 downto 0);
s_axi_arqos : in std_logic_vector(4-1 downto 0);
s_axi_arregion : in std_logic_vector(4-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0) := (others=>'0');
s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0) := (others=>'0');
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rresp : in std_logic_vector(1 downto 0));
end plasoc_axi4_full2lite_read_cntrl;
architecture Behavioral of plasoc_axi4_full2lite_read_cntrl is
signal id_buff_0 : std_logic_vector(axi_slave_id_width-1 downto 0) := (others=>'0');
signal s_axi_arready_buff : std_logic := '0';
signal m_axi_arvalid_buff : std_logic := '0';
signal s_axi_rvalid_buff : std_logic := '0';
signal m_axi_rready_buff : std_logic := '0';
begin
s_axi_arready <= s_axi_arready_buff;
m_axi_arvalid <= m_axi_arvalid_buff;
s_axi_rvalid <= s_axi_rvalid_buff;
s_axi_rlast <= s_axi_rvalid_buff;
m_axi_rready <= m_axi_rready_buff;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
s_axi_arready_buff <= '1';
m_axi_arvalid_buff <= '0';
else
if s_axi_arvalid='1' and s_axi_arready_buff='1' then
id_buff_0 <= s_axi_arid;
m_axi_araddr <= s_axi_araddr;
m_axi_arprot <= s_axi_arprot;
end if;
if s_axi_arvalid='1' and s_axi_arready_buff='1' then
m_axi_arvalid_buff <= '1';
elsif m_axi_arvalid_buff='1' and m_axi_arready='1' then
m_axi_arvalid_buff <= '0';
end if;
if m_axi_arready='1' then
s_axi_arready_buff <= '1';
elsif s_axi_arvalid='1' and s_axi_arready_buff='1' then
s_axi_arready_buff <= '0';
end if;
end if;
end if;
end process;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
s_axi_rvalid_buff <= '0';
m_axi_rready_buff <= '1';
else
if m_axi_rvalid='1' and m_axi_rready_buff='1' then
s_axi_rid <= id_buff_0;
s_axi_rresp <= m_axi_rresp;
s_axi_rdata <= m_axi_rdata;
end if;
if m_axi_rvalid='1' and m_axi_rready_buff='1' then
s_axi_rvalid_buff <= '1';
elsif s_axi_rvalid_buff='1' and s_axi_rready='1' then
s_axi_rvalid_buff <= '0';
end if;
if s_axi_rready='1' then
m_axi_rready_buff <= '1';
elsif m_axi_rvalid='1' and m_axi_rready_buff='1' then
m_axi_rready_buff <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
1cae5a4f541e41301ac900fd62dcfb37
| 0.446743 | 3.97 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Video_PR_1.0/hdl/Video_PR_v1_0_S_AXI.vhd
| 1 | 16,260 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity Video_PR_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
-- Users to add ports here
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Video_PR_v1_0_S_AXI;
architecture arch_imp of Video_PR_v1_0_S_AXI is
component pixel_counter is
port(
clk : in std_logic;
hs : in std_logic;
vs : in std_logic;
vde : in std_logic;
pixel_x : out std_logic_vector(15 downto 0);
pixel_y : out std_logic_vector(15 downto 0)
);
end component pixel_counter;
component Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end component Video_Box;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
--constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal x_coord,y_coord : std_logic_vector(15 downto 0);
signal RGB_IN_reg, RGB_OUT_reg,RGB_OUT_next: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal VDE_OUT_next,HS_OUT_next,VS_OUT_next : std_logic ;
begin
Pixel_Counter_0 : Pixel_Counter
port map(
clk => PIXEL_CLK,
hs => HS_IN,
vs => VS_IN,
vde => VDE_IN,
pixel_x => x_coord,
pixel_y => y_coord
);
Video_Box_0: Video_Box
generic map(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map(
S_AXI_ARESETN => S_AXI_ARESETN,
slv_reg_wren => slv_reg_wren,
slv_reg_rden => slv_reg_rden,
S_AXI_WSTRB => S_AXI_WSTRB,
axi_awaddr => axi_awaddr,
S_AXI_WDATA => S_AXI_WDATA,
axi_araddr => axi_araddr,
reg_data_out => reg_data_out,
--Bus Clock
S_AXI_ACLK => S_AXI_ACLK,
--Video
RGB_IN => RGB_IN_reg,
VDE_IN => VDE_IN_reg,
HS_IN => HS_IN_reg,
VS_IN => VS_IN_reg,
-- additional ports here
RGB_OUT => RGB_OUT_next,
VDE_OUT => VDE_OUT_next,
HS_OUT => HS_OUT_next,
VS_OUT =>VS_OUT_next,
PIXEL_CLK => PIXEL_CLK,
X_Coord => X_Coord_reg,
Y_Coord => Y_Coord_reg
);
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= RGB_OUT_next;
VDE_OUT_reg <= VDE_OUT_next;
HS_OUT_reg <= HS_OUT_next;
VS_OUT_reg <= VS_OUT_next;
end if;
end process;
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
|
bsd-3-clause
|
6b0325d2410f552db1de24f3cb8f57e5
| 0.623555 | 3.373444 | false | false | false | false |
tmeissner/cryptocores
|
cbcaes/rtl/vhdl/cbcaes.vhd
| 1 | 4,410 |
-- ======================================================================
-- CBC-AES encryption/decryption
-- Copyright (C) 2021 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity cbcaes is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
mode_i : in std_logic; -- aes-modus: 0 = encrypt, 1 = decrypt
key_i : in std_logic_vector(0 to 127); -- key input
iv_i : in std_logic_vector(0 to 127); -- iv input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- ready to encrypt/decrypt
data_o : out std_logic_vector(0 to 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity cbcaes;
architecture rtl of cbcaes is
signal s_mode : std_logic;
signal s_aes_mode : std_logic;
signal s_start : std_logic;
signal s_key : std_logic_vector(0 to 127);
signal s_aes_key : std_logic_vector(0 to 127);
signal s_iv : std_logic_vector(0 to 127);
signal s_datain : std_logic_vector(0 to 127);
signal s_datain_d : std_logic_vector(0 to 127);
signal s_aes_datain : std_logic_vector(0 to 127);
signal s_aes_dataout : std_logic_vector(0 to 127);
signal s_dataout : std_logic_vector(0 to 127);
begin
s_aes_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
s_dataout xor data_i when s_mode = '0' and start_i = '0' else
data_i;
data_o <= s_iv xor s_aes_dataout when s_mode = '1' and s_start = '1' else
s_datain_d xor s_aes_dataout when s_mode = '1' and s_start = '0' else
s_aes_dataout;
s_aes_key <= key_i when start_i = '1' else s_key;
s_aes_mode <= mode_i when start_i = '1' else s_mode;
inputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_mode <= '0';
s_start <= '0';
s_key <= (others => '0');
s_iv <= (others => '0');
s_datain <= (others => '0');
s_datain_d <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
s_start <= start_i;
s_datain <= data_i;
s_datain_d <= s_datain;
if (start_i = '1') then
s_mode <= mode_i;
s_key <= key_i;
s_iv <= iv_i;
end if;
end if;
end if;
end process inputregister;
outputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_dataout <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_o = '1' and accept_i = '1') then
s_dataout <= s_aes_dataout;
end if;
end if;
end process outputregister;
i_aes : entity work.aes
generic map (
design_type => "ITER"
)
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_aes_mode,
key_i => s_aes_key,
data_i => s_aes_datain,
valid_i => valid_i,
accept_o => accept_o,
data_o => s_aes_dataout,
valid_o => valid_o,
accept_i => accept_i
);
end architecture rtl;
|
gpl-2.0
|
4cd54b8ffc30e591f1aee94073aa5ac0
| 0.527891 | 3.437256 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/mips.vhdl
| 1 | 5,048 |
-- This is the top level MIPS architecture
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity mips is
generic ( DEMO : boolean := false);
port (
sysclk : in std_logic;
rst : in std_logic;
-- VGA I/O
vgaclk : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic;
-- LEDs
leds : out std_logic_vector(7 downto 0);
-- Push buttons
buttons : in std_logic_vector(3 downto 0);
-- DIP Switch IO
switch : in std_logic_vector(7 downto 0)
);
end;
architecture struct of mips is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
component mem is
generic (ROM : string := "");
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic;
-- VGA I/O
vgaclk, rst : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic;
-- LEDs
leds : out std_logic_vector(7 downto 0);
-- Push buttons
buttons : in std_logic_vector(3 downto 0);
-- DIP Switch IO
switch : in std_logic_vector(7 downto 0)
);
end component;
component cpu is
generic(PC_ADD : natural := 4;
SINGLE_ADDRESS_SPACE : boolean := true);
port(
clk : in std_logic;
rst : in std_logic;
-- Register File
readreg1, readreg2 : out reg_t;
writereg: out reg_t;
regWriteData: out word_t;
regReadData1, regReadData2 : in word_t;
regWrite : out std_logic;
-- Memory
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t;
-- Debug info
instruction : out instruction_t
);
end component;
component clkdivider is
port (
ticks : in natural;
bigclk : in std_logic;
rst : in std_logic;
smallclk : out std_logic
);
end component;
signal readreg1, readreg2 : reg_t;
signal writereg: reg_t;
signal regWriteData: word_t;
signal regReadData1, regReadData2 : word_t;
signal regWrite : std_logic;
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
signal clk : std_logic := '0';
signal instruction : instruction_t;
begin
normal_clk: if not DEMO generate
clkdivider1: clkdivider port map (
ticks => 10, bigclk => sysclk, rst => rst, smallclk => clk
);
end generate;
clk_is_6hz: if DEMO generate
clkdivider1: clkdivider port map (
ticks => VGA_PIXELFREQ / 6, bigclk => sysclk, rst => rst, smallclk => clk
);
end generate;
-- One instruction every two seconds
regfile_inst: regFile port map (
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg,
writeData => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => clk,
rst => rst,
regWrite => regWrite
);
connect_leds_to_bus: if not DEMO generate
mem_bus: mem
generic map (ROM => "VGA")
port map (
addr => addr, din => din, dout => dout, size => size, wr => wr, clk => clk,
vgaclk => vgaclk, rst => rst, r => r, g => g, b => b, hsync => hsync, vsync => vsync,
leds => leds, buttons => buttons, switch => switch
);
end generate;
connect_leds_to_instruction: if DEMO generate
mem_bus: mem
generic map (ROM => "VGA")
port map (
addr => addr, din => din, dout => dout, size => size, wr => wr, clk => clk,
vgaclk => vgaclk, rst => rst, r => r, g => g, b => b, hsync => hsync, vsync => vsync,
leds => open, buttons => buttons, switch => switch
);
leds(7) <= wr;
leds(6) <= clk;
leds(5 downto 0) <= instruction(31 downto 26);
end generate;
cpu_inst: cpu
generic map (SINGLE_ADDRESS_SPACE => false)
port map (
clk => clk,
rst => rst,
-- Register File
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg,
regWriteData => regWriteData,
regReadData1 => regReadData1, regReadData2 => regReadData2,
regWrite => regWrite,
-- Memory
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr,
-- Debug info
instruction => instruction
);
end struct;
|
gpl-3.0
|
d67918744318ef582b747178b6c1f1f9
| 0.532092 | 3.981073 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/axi_qspi_enhanced_mode.vhd
| 2 | 39,164 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_qspi_enhanced_mode.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- enhanced mode with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library interrupt_control_v3_1_4;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
entity axi_qspi_enhanced_mode is
generic (
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_AXI4_CLK_PS : integer := 10000;--AXI clock period
C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
C_SPI_MEM_ADDR_BITS : integer -- newly added
);
port (
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESETN : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
Bus2IP_Clk : out std_logic;
Bus2IP_Reset : out std_logic;
--Bus2IP_Addr : out std_logic_vector
-- (C_S_AXI4_ADDR_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic;
---------------------------------
burst_tr : out std_logic;
rready : out std_logic
);
end entity axi_qspi_enhanced_mode;
architecture imp of axi_qspi_enhanced_mode is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant ACTIVE_LOW_RESET : std_logic := '0';
-- local type declarations
type STATE_TYPE is (
IDLE,
AXI_SINGLE_RD,
AXI_RD,
AXI_SINGLE_WR,
AXI_WR,
CHECK_AXI_LENGTH_ERROR,
AX_WRONG_BURST_TYPE,
WR_RESP_1,
WR_RESP_2,
RD_RESP_1,RD_LAST,
RD_RESP_2,
ERROR_RESP,
RD_ERROR_RESP
);
-- Signal Declaration
-----------------------------
signal axi_full_sm_ps : STATE_TYPE;
signal axi_full_sm_ns : STATE_TYPE;
-- function declaration
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
-- code coverage -- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
-- code coverage -- variable i : integer := 0;
-- code coverage -- begin
-- code coverage -- for i in 31 downto 0 loop
-- code coverage -- if y(i)='1' then
-- code coverage -- return (i);
-- code coverage -- end if;
-- code coverage -- end loop;
-- code coverage -- return -1;
-- code coverage -- end function Get_Addr_Bits;
-- constant declaration
constant C_ADDR_DECODE_BITS : integer := 6; -- Get_Addr_Bits(C_S_AXI_SPI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector(31 downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-- type decode_bit_array_type is Array(natural range 0 to (
-- (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
-- integer;
-- type short_addr_array_type is Array(natural range 0 to
-- C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
-- std_logic_vector(0 to(C_ADDR_DECODE_BITS-1));
-- signal declaration
signal axi_size_reg : std_logic_vector(2 downto 0);
signal axi_size_cmb : std_logic_vector(2 downto 0);
signal bus2ip_rnw_i : std_logic;
signal bus2ip_addr_i : std_logic_vector(31 downto 0); -- (31 downto 0); -- 8/18/2013
signal wr_transaction : std_logic;
signal wr_addr_transaction : std_logic;
signal arready_i : std_logic;
signal awready_i, s_axi_wready_i : std_logic;
signal S_AXI4_RID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal S_AXI4_BID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal s_axi_mem_bresp_reg : std_logic_vector(2 downto 0);
signal axi_full_sm_ps_IDLE_cmb : std_logic;
signal s_axi_mem_bvalid_reg : std_logic;
signal bus2ip_BE_reg : std_logic_vector(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
signal axi_length_cmb : std_logic_vector(7 downto 0);
signal axi_length_reg : std_logic_vector(7 downto 0);
signal burst_transfer_cmb : std_logic;
signal burst_transfer_reg : std_logic;
signal axi_burst_cmb : std_logic_vector(1 downto 0);
signal axi_burst_reg : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(7 downto 0);
signal last_data_cmb : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal pr_state_idle : std_logic;
signal length_error : std_logic;
signal rnw_reg, rnw_cmb : std_logic;
signal arready_cmb : std_logic;
signal awready_cmb : std_logic;
signal wready_cmb : std_logic;
signal store_axi_signal_cmb : std_logic;
signal combine_ack, start, temp_i, response : std_logic;
signal s_axi4_rdata_i : std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
signal s_axi4_rresp_i : std_logic_vector(1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal S_AXI4_BRESP_i : std_logic_vector(1 downto 0);
signal s_axi_bvalid_i : std_logic;
signal pr_state_length_chk : std_logic;
signal axi_full_sm_ns_IDLE_cmb : std_logic;
signal last_data_reg: std_logic;
signal rst_en : std_logic;
signal s_axi_rvalid_cmb, last_data, burst_tr_i,rready_i, store_data : std_logic;
signal Bus2IP_Reset_i : std_logic;
-----
begin
-----
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
-- REGISTERING_RESET_P: Invert the reset coming from AXI4
-----------------------
REGISTERING_RESET_P : process (S_AXI4_ACLK) is
-----
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
Bus2IP_Reset_i <= not S_AXI4_ARESETN;
end if;
end process REGISTERING_RESET_P;
Bus2IP_Reset <= Bus2IP_Reset_i;
Bus2IP_Clk <= S_AXI4_ACLK;
--Bus2IP_Resetn <= S_AXI4_ARESETN;
--bus2ip_rnw_i <= rnw_reg;-- '1' when S_AXI4_ARVALID='1' else '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_Data <= S_AXI4_WDATA;
--Bus2IP_Addr <= bus2ip_addr_i;
wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
bus2ip_addr_i <= ZEROS & S_AXI4_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI4_ARVALID='1')
else
ZEROS & S_AXI4_AWADDR(C_ADDR_DECODE_BITS downto 0);
--S_AXI4_ARADDR(C_ADDR_DECODE_BITS+1 downto 0) when (S_AXI4_ARVALID='1')
--else
--S_AXI4_AWADDR(C_ADDR_DECODE_BITS+1 downto 0);
-- read and write transactions should be separate
-- preferencec of read over write
-- only narrow transfer of 8-bit are supported
-- for 16-bit and 32-bit transactions error should be generated - dont provide these signals to internal logic
--wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
--wr_addr_transaction <= S_AXI4_AWVALID and (not S_AXI4_WVALID);
-------------------------------------------------------------------------------
AXI_ARREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
arready_i <='0';
else
arready_i <= arready_cmb;
end if;
end if;
end process AXI_ARREADY_P;
--------------------------
S_AXI4_ARREADY <= arready_i; -- arready_i;--IP2Bus_RdAck; --arready_i;
--------------------------
AXI_AWREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
awready_i <='0';
else
awready_i <= awready_cmb;
end if;
end if;
end process AXI_AWREADY_P;
--------------------------
S_AXI4_AWREADY <= awready_i;
--------------------------
S_AXI4_BRESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
S_AXI4_BRESP_i <= (others => '0');
elsif (axi_full_sm_ps = AXI_WR) or (axi_full_sm_ps = AXI_SINGLE_WR) then
S_AXI4_BRESP_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI4_BRESP_P;
---------------------------
S_AXI4_BRESP <= S_AXI4_BRESP_i;
-------------------------------
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_bvalid_i <= '0';
elsif(axi_full_sm_ps = WR_RESP_1)then
s_axi_bvalid_i <= '1';
elsif(S_AXI4_BREADY = '1')then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------
S_AXI4_BVALID <= s_axi_bvalid_i;
--------------------------------
----S_AXI_WREADY_I_P: below process provides logic for valid write response signal
---------------------
S_AXI_WREADY_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_wready_i <= '0';
else
s_axi_wready_i <= wready_cmb;
end if;
end if;
end process S_AXI_WREADY_I_P;
-------------------------------
S_AXI4_WREADY <= s_axi_wready_i;
--------------------------------
-------------------------------------------------------------------------------
-- REG_BID_P,REG_RID_P: Below process makes the RID and BID '0' at POR and
-- : generate proper values based upon read/write
-- transaction
-----------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_RID_reg;
-----------------------------
REG_BID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
S_AXI4_BID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_BID_reg <= S_AXI4_AWID;-- and pr_state_length_chk;
end if;
end if;
end process REG_BID_P;
-----------------------
S_AXI4_BID <= S_AXI4_BID_reg;
------------------------------
------------------------
-- BUS2IP_BE_P:Register Bus2IP_BE for write strobe during write mode else '1'.
------------------------
BUS2IP_BE_P: process (S_AXI4_ACLK) is
------------
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if ((Bus2IP_Reset_i = RESET_ACTIVE)) then
bus2ip_BE_reg <= (others => '0');
else
if (rnw_cmb = '0'-- and
--(wready_cmb = '1')
) then
bus2ip_BE_reg <= S_AXI4_WSTRB;
else -- if(rnw_cmb = '1') then
bus2ip_BE_reg <= (others => '1');
end if;
end if;
end if;
end process BUS2IP_BE_P;
------------------------
Bus2IP_BE <= bus2ip_BE_reg;
axi_length_cmb <= S_AXI4_ARLEN when (rnw_cmb = '1')
else
S_AXI4_AWLEN;
burst_transfer_cmb <= (or_reduce(axi_length_cmb));
BURST_LENGTH_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_length_reg <= (others => '0');
burst_transfer_reg <= '0';
elsif((store_axi_signal_cmb = '1'))then
axi_length_reg <= axi_length_cmb;
burst_transfer_reg <= burst_transfer_cmb;
end if;
end if;
end process BURST_LENGTH_REG_P;
-----------------------
burst_tr_i <= burst_transfer_reg;
burst_tr <= burst_tr_i;
-------------------------------------------------------------------------------
axi_size_cmb <= S_AXI4_ARSIZE(2 downto 0) when (rnw_cmb = '1')
else
S_AXI4_AWSIZE(2 downto 0);
SIZE_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_size_reg <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
axi_size_reg <= axi_size_cmb;
end if;
end if;
end process SIZE_REG_P;
-----------------------
axi_burst_cmb <= S_AXI4_ARBURST when (rnw_cmb = '1')
else
S_AXI4_AWBURST;
BURST_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
axi_burst_reg <= (others => '0');
elsif(store_axi_signal_cmb = '1')then
axi_burst_reg <= axi_burst_cmb;
end if;
end if;
end process BURST_REG_P;
-----------------------
combine_ack <= IP2Bus_WrAck or IP2Bus_RdAck;
--------------------------------------------
LENGTH_CNTR_P:process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
length_cntr <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
length_cntr <= axi_length_cmb;
elsif (wready_cmb = '1' and S_AXI4_WVALID = '1') or
(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then -- burst length error
length_cntr <= length_cntr - '1';
end if;
end if;
end process LENGTH_CNTR_P;
--------------------------
--last_data_cmb <= or_reduce(length_cntr(7 downto 1)) and length_cntr(1);
rready <= rready_i;
last_bt_one_data_cmb <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0) and S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(length_cntr(7 downto 0)));
--temp_i <= (combine_ack and last_data_reg)or rst_en;
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(axi_full_sm_ps_IDLE_cmb = '1') then
last_data_acked <= '0';
elsif(burst_tr_i = '0')then
if(S_AXI4_RREADY = '1' and last_data_acked = '1')then
last_data_acked <= '0';
else
last_data_acked <= last_data_cmb and s_axi_rvalid_cmb;
end if;
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then
last_data_acked <= '1';
else
last_data_acked <= last_data and s_axi_rvalid_i and S_AXI4_RREADY;
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= last_data_acked;
--------------------------------
-- S_AXI4_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RRESP_i <= (others => '0');
S_AXI4_RDATA_i <= (others => '0');
elsif(S_AXI4_RREADY = '1' )or(store_data = '1') then --if --((axi_full_sm_ps = AXI_SINGLE_RD) or (axi_full_sm_ps = AXI_BURST_RD)) then
S_AXI4_RRESP_i <= (IP2Bus_Error) & '0';
S_AXI4_RDATA_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
S_AXI4_RRESP <= S_AXI4_RRESP_i;
S_AXI4_RDATA <= S_AXI4_RDATA_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
s_axi_rvalid_i <= '0';
elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
s_axi_rvalid_i <= s_axi_rvalid_i;
else
s_axi_rvalid_i <= s_axi_rvalid_cmb;
end if;
end if;
end process S_AXI_RVALID_I_P;
-----------------------------
S_AXI4_RVALID <= s_axi_rvalid_i;
-- -----------------------------
-- Addr_int <= S_AXI_ARADDR when(rnw_cmb_dup = '1')
-- else
-- S_AXI_AWADDR;
axi_full_sm_ns_IDLE_cmb <= '1' when (axi_full_sm_ns = IDLE) else '0';
axi_full_sm_ps_IDLE_cmb <= '1' when (axi_full_sm_ps = IDLE) else '0';
pr_state_idle <= '1' when axi_full_sm_ps = IDLE else '0';
pr_state_length_chk <= '1' when axi_full_sm_ps = CHECK_AXI_LENGTH_ERROR
else
'0';
REGISTER_LOWER_ADDR_BITS_P:process(S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (axi_full_sm_ps_IDLE_cmb = '1') then
length_error <= '0';
elsif(burst_transfer_cmb = '1')then -- means its a burst
--if (bus2ip_addr_i (7 downto 3) = "01101")then
if (bus2ip_addr_i (6 downto 3) = "1101")then
length_error <= '0';
else
length_error <= '1';
end if;
end if;
end if;
end process REGISTER_LOWER_ADDR_BITS_P;
---------------------------------------
-- length_error <= '0';
---------------------------
REG_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
axi_full_sm_ps <= IDLE;
last_data_reg <= '0';
else
axi_full_sm_ps <= axi_full_sm_ns;
last_data_reg <= last_data_cmb;
end if;
end if;
end process REG_P;
-------------------------------------------------------
STORE_SIGNALS_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
rnw_reg <= '0';
else-- if(store_axi_signal_cmb = '1')then
rnw_reg <= rnw_cmb;
end if;
end if;
end process STORE_SIGNALS_P;
-------------------------------------------------------
AXI_FULL_STATE_MACHINE_P:process(
axi_full_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_AWVALID ,
S_AXI4_WVALID ,
S_AXI4_BREADY ,
S_AXI4_RREADY ,
wr_transaction ,
wr_addr_transaction ,
length_error ,
IP2Bus_WrAck ,
last_data_cmb ,
IP2Bus_RdAck ,
IP2Bus_Error ,
burst_transfer_cmb ,
last_bt_one_data_cmb ,
rnw_reg ,
length_cntr
)is
-----
begin
-----
arready_cmb <= '0';
awready_cmb <= '0';
wready_cmb <= '0';
start <= '0';
rst_en <= '0';
temp_i <= '0';
store_axi_signal_cmb <= '0';
s_axi_rvalid_cmb <= '0';
rready_i <= '0';
rnw_cmb <= '0';
last_data <= '0';
store_data <= '0';
case axi_full_sm_ps is
when IDLE => if(S_AXI4_ARVALID = '1') then
start <= '1';
store_axi_signal_cmb <= '1';
arready_cmb <= '1';
if(burst_transfer_cmb = '1') then
axi_full_sm_ns <= AXI_RD;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
elsif(wr_transaction = '1')then
start <= '1';
store_axi_signal_cmb <= '1';
if(burst_transfer_cmb = '1') then
awready_cmb <= '1';
wready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
else
axi_full_sm_ns <= IDLE;
end if;
rnw_cmb <= S_AXI4_ARVALID and (not S_AXI4_AWVALID);
------------------------------
when CHECK_AXI_LENGTH_ERROR => if (length_error = '0') then
if(rnw_reg = '1')then
arready_cmb <= '1';
axi_full_sm_ns <= AXI_RD;
else
awready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
end if;
start <= '1';
else
axi_full_sm_ns <= ERROR_RESP;
end if;
---------------------------------------------------------
when AXI_SINGLE_RD => --arready_cmb <= IP2Bus_RdAck;
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error;
temp_i <= IP2Bus_RdAck or IP2Bus_Error;
rready_i <= '1';
if(IP2Bus_RdAck = '1')or (IP2Bus_Error = '1') then
store_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
rnw_cmb <= rnw_reg;
when AXI_RD =>
rready_i <= S_AXI4_RREADY and not last_data_cmb;
last_data <= last_bt_one_data_cmb;
if(last_data_cmb = '1') then
if(S_AXI4_RREADY = '1')then
temp_i <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
axi_full_sm_ns <= IDLE;
else
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
last_data <= not S_AXI4_RREADY;
temp_i <= '1';
axi_full_sm_ns <= RD_LAST;
end if;
else
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error; -- not last_data_cmb;
axi_full_sm_ns <= AXI_RD;
end if;
rnw_cmb <= rnw_reg;
----------------------------------------------------------
when AXI_SINGLE_WR => awready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
wready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
temp_i <= IP2Bus_WrAck or IP2Bus_Error;
if(IP2Bus_WrAck = '1')or (IP2Bus_Error = '1')then
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
rnw_cmb <= rnw_reg;
when AXI_WR => --if(IP2Bus_WrAck = '1')then
wready_cmb <= '1';--IP2Bus_WrAck;
if(last_data_cmb = '1') then
wready_cmb <= '0';
temp_i <= '1';--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_WrAck;
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_WR;
end if;
rnw_cmb <= rnw_reg;
-----------------------------------------------------------
when WR_RESP_1 => --if(S_AXI4_BREADY = '1') then
-- axi_full_sm_ns <= IDLE;
--else
axi_full_sm_ns <= WR_RESP_2;
-- end if;
-----------------------------------------------------------
when WR_RESP_2 => if(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= WR_RESP_2;
end if;
-----------------------------------------------------------
when RD_LAST => if(S_AXI4_RREADY = '1') then -- and (TX_FIFO_Empty = '1') then
last_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= IDLE;
else
last_data <= not S_AXI4_RREADY;
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
temp_i <= '1';
end if;
-----------------------------------------------------------
when RD_RESP_2 => if(S_AXI4_RREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= RD_RESP_2;
end if;
-----------------------------------------------------------
when ERROR_RESP => if(length_cntr = "00000000") and
(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= ERROR_RESP;
end if;
response <= '1';
when others => axi_full_sm_ns <= IDLE;
end case;
end process AXI_FULL_STATE_MACHINE_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
I_DECODER : entity axi_quad_spi_v3_2_8.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK,
Bus_rst => S_AXI4_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), -- (C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI4_ARVALID,
Bus_RNW_Erly => S_AXI4_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
end architecture imp;
------------------------------------------------------------------------------
|
bsd-3-clause
|
9d6a3d3256b29aa6df250f498bdffdf8
| 0.449443 | 3.83022 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_0/synth/fifo_generator_0.vhd
| 1 | 40,197 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_0 IS
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC
);
END fifo_generator_0;
ARCHITECTURE fifo_generator_0_arch OF fifo_generator_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_0_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_v13_0_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_0_arch : ARCHITECTURE IS "fifo_generator_0,fifo_generator_v13_0_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_0_arch: ARCHITECTURE IS "fifo_generator_0,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=1,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=1,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=1,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=1,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=12,C_IMPLEMENTATION_TYPE_WDCH=11,C_IMPLEMENTATION_TYPE_WRCH=12,C_IMPLEMENTATION_TYPE_RACH=12,C_IMPLEMENTATION_TYPE_RDCH=11,C_IMPLEMENTATION_TYPE_AXIS=11,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx36,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=41,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=13,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1021,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=13,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=13,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1021,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1021,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 master_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 1,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 1,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 1,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 1,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 12,
C_IMPLEMENTATION_TYPE_WDCH => 11,
C_IMPLEMENTATION_TYPE_WRCH => 12,
C_IMPLEMENTATION_TYPE_RACH => 12,
C_IMPLEMENTATION_TYPE_RDCH => 11,
C_IMPLEMENTATION_TYPE_AXIS => 11,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx36",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 41,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1021,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 13,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1021,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1021,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => m_aclk,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => s_axis_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tuser => m_axis_tuser,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_overflow => axis_overflow,
axis_underflow => axis_underflow
);
END fifo_generator_0_arch;
|
bsd-3-clause
|
d1afab464a1cdca14c9484df56129ee4
| 0.631639 | 2.920232 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_wr_sf.vhd
| 4 | 50,561 |
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Write (S2MM) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. This module buffers write data and provides status and
-- control features such that the DataMover Write Master is only allowed
-- to post AXI WRite Requests if the associated write data needed to complete
-- the Write Data transfer is present in the Data FIFO. In addition, the Write
-- side logic is such that Write transfer requests can be pipelined to the
-- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data
-- transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_wr_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
-- C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- -- Indicates the max burst length being used by the external
-- -- AXI4 Master for each AXI4 transfer request.
-- C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- -- Indicates if the external Master is utilizing a DRE on
-- -- the stream input to this module.
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 16;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs -----------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
-------------------------------------------------------------------------
-- Slave Stream Input ------------------------------------------------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
sin2sf_error : In std_logic; --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. --
-----------------------------------------------------------------------------------
-- DataMover Write Side Address Pipelining Control Interface ----------------------
--
ok_to_post_wr_addr : Out Std_logic; --
-- Indicates that the internal FIFO has enough data --
-- physically present to supply one more max length --
-- burst transfer or a completion burst --
-- (tlast asserted) --
--
wr_addr_posted : In std_logic; --
-- Indication that a write address has been posted to AXI4 --
--
--
wr_xfer_cmplt : In Std_logic; --
-- Indicates that the Datamover has completed a Write Data --
-- transfer on the AXI4 --
--
--
wr_ld_nxt_len : in std_logic; --
-- Active high pulse indicating a new transfer LEN qualifier --
-- has been queued to the DataMover Write Data Controller --
--
wr_len : in std_logic_vector(7 downto 0); --
-- The actual LEN qualifier value that has been queued to the --
-- DataMover Write Data Controller --
-----------------------------------------------------------------------------------
-- Write Side Stream Out to DataMover S2MM ----------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic; --
-- Write LAST output to the Stream Master --
--
sf2sout_error : Out std_logic --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
);
end entity axi_datamover_wr_sf;
architecture implementation of axi_datamover_wr_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant EOP_ERR_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
-- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
--WSTB_WIDTH +
TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
-- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
-- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
-- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
signal sig_sf2sout_eop_err_out : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
sf2sout_error <= sig_sf2sout_eop_err_out ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_good_fifo_write <= sig_good_sin_strm_dbeat;
sig_strm_sin_ready <= not(sig_data_fifo_full);
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_error &
sin2sf_tlast &
-- sin2sf_tkeep &
sin2sf_tdata;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_err_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
-- Generate the stream ready
sig_strm_sin_ready <= not(lsig_packer_full) or
lsig_good_push2fifo ;
-- Format the FIFO input data
sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit
lsig_tlast_or &
lsig_combined_data ; -- LS Bits
-- Generate a write to the Data FIFO input
sig_push_data_fifo <= lsig_packer_full;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_sin_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sin_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_sin_strm_dbeat and
(sin2sf_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_sin_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice for the packer.
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= sin2sf_tdata;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1
sin2sf_error; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or
--lsig_partial_eop_err_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register outputs into a single
-- vector for input to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Input attachments
-- sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= sin2sf_error &
-- sin2sf_tlast &
-- sin2sf_tkeep &
-- sin2sf_tdata;
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
-- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
-- TSTRB_OUT_LSB_INDEX);
-- When this Store and Forward is enabled, the Write Data Controller ignores the
-- TKEEP input so this is not sent through the FIFO.
sig_sf2sout_tkeep <= (others => '1');
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ;
-- FIFO Rd/WR Controls
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
-- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
sig_incr_uncom_wrcnt <= sig_good_fifo_write;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
-- The LEN FIFO stores the xfer lengths needed for each queued
-- write transfer in the DataMover S2MM Write Data Controller.
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
|
bsd-3-clause
|
bd1887b70397454c5f86d267f59d62e5
| 0.418663 | 4.994666 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_refsigma.vhd
| 1 | 1,109 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_refsigma is
port (
clock : in std_logic;
Pdashofkplusone : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
refsigma : out std_logic_vector(31 downto 0)
);
end k_ukf_refsigma;
architecture struct of k_ukf_refsigma is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sqrt IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_sqrt port map
( clock => clock,
data => Pdashofkplusone,
result => Z);
M2 : k_ukf_mult port map
( clock => clock,
dataa => T,
datab => Z,
result => refsigma);
end struct;
|
gpl-2.0
|
f19b8a7b7b2702bad009e6e56eac7881
| 0.583408 | 3.080556 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_fifo_ifmodule.vhd
| 2 | 16,822 |
-------------------------------------------------------------------------------
-- qspi_fifo_ifmodule.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_fifo_ifmodule.vhd
-- Version: v3.0
-- Description: Quad Serial Peripheral Interface (QSPI) Module for interfacing
-- with a 32-bit axi Bus. FIFO Interface module
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Bus2IP_RcFIFO_RdCE -- Bus2IP receive FIFO read CE
-- Bus2IP_TxFIFO_WrCE -- Bus2IP transmit FIFO write CE
-- Rd_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- Wr_ce_reduce_ack_gen -- commong logid to generate the write ACK
-- IP2Bus_RX_FIFO_Data -- Data to send on the bus
-- Transmit_ip2bus_error -- Transmit FIFO error signal
-- Receive_ip2bus_error -- Receive FIFO error signal
-- FIFO INTERFACE
-- Data_From_TxFIFO -- Data from transmit FIFO
-- Tx_FIFO_Data_WithZero -- Components to put zeros on input
-- to Shift Register when FIFO is empty
-- Data_From_Rc_FIFO -- Receive FIFO data output
-- Rc_FIFO_Empty -- Receive FIFO empty
-- Rc_FIFO_Full -- Receive FIFO full
-- Rc_FIFO_Full_strobe -- 1 cycle wide receive FIFO full strobe
-- Tx_FIFO_Empty -- Transmit FIFO empty
-- Tx_FIFO_Empty_strobe -- 1 cycle wide transmit FIFO full strobe
-- Tx_FIFO_Full -- Transmit FIFO full
-- Tx_FIFO_Occpncy_MSB -- Transmit FIFO occupancy register
-- MSB bit
-- Tx_FIFO_less_half -- Transmit FIFO less than half empty
-- SPI MODULE INTERFACE
-- DRR_Overrun -- DRR Overrun bit
-- SPIXfer_done -- SPI transfer done flag
-- DTR_Underrun_strobe -- DTR Underrun Strobe bit
-- DTR_underrun -- DTR underrun generation signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_fifo_ifmodule is
generic
(
C_NUM_TRANSFER_BITS : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_RcFIFO_RdCE : in std_logic;
Bus2IP_TxFIFO_WrCE : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
-- FIFO ports
Data_From_TxFIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Data_From_Rc_FIFO : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Tx_FIFO_Data_WithZero: out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
IP2Bus_RX_FIFO_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
---------------------
Rc_FIFO_Full : in std_logic;
Rc_FIFO_Full_strobe : out std_logic;
---------------------
Tx_FIFO_Empty : in std_logic;
Tx_FIFO_Empty_strobe : out std_logic;
---------------------
Rc_FIFO_Empty : in std_logic;
Receive_ip2bus_error : out std_logic;
Tx_FIFO_Full : in std_logic;
Transmit_ip2bus_error: out std_logic;
---------------------
Tx_FIFO_Occpncy_MSB : in std_logic;
Tx_FIFO_less_half : out std_logic;
---------------------
DTR_underrun : in std_logic;
DTR_Underrun_strobe : out std_logic;
---------------------
SPIXfer_done : in std_logic;
rready : in std_logic
--DRR_Overrun_reg : out std_logic
---------------------
);
end qspi_fifo_ifmodule;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_fifo_ifmodule is
---------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
-- signal drr_Overrun_i : std_logic;
signal rc_FIFO_Full_d1 : std_logic;
signal dtr_Underrun_strobe_i : std_logic;
signal tx_FIFO_Empty_d1 : std_logic;
signal tx_FIFO_Occpncy_MSB_d1 : std_logic;
signal dtr_underrun_d1 : std_logic;
signal RST_TxFIFO_ptr_int : std_logic;
--signal DRR_Overrun_reg_int : std_logic;
---------------------------------------------
begin
-----
-- Combinatorial operations
-------------------------------------------------------------------------------
-- DRR_Overrun_reg <= DRR_Overrun_reg_int;
-------------------------------------------------------------------------------
-- SPI_RECEIVE_FIFO_RD_GENERATE : Read of SPI receive FIFO
----------------------------------
SPI_RECEIVE_FIFO_RD_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
-----
begin
-----
IP2Bus_RX_FIFO_Data(i) <= Data_From_Rc_FIFO(i) and
(
(Rd_ce_reduce_ack_gen or rready) and
Bus2IP_RcFIFO_RdCE
);
end generate SPI_RECEIVE_FIFO_RD_GENERATE;
-------------------------------------------------------------------------------
-- PUT_ZEROS_IN_SR_GENERATE : Put zeros on input to SR when FIFO is empty.
-- Requested by software designers
------------------------------
PUT_ZEROS_IN_SR_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
Tx_FIFO_Data_WithZero(i) <= Data_From_TxFIFO(i) and (not Tx_FIFO_Empty);
end generate PUT_ZEROS_IN_SR_GENERATE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RX_ERROR_ACK_REG_PROCESS : Strobe error when receive FIFO is empty.
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
RX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Receive_ip2bus_error <= '0';
else
Receive_ip2bus_error <= Rc_FIFO_Empty and Bus2IP_RcFIFO_RdCE;
end if;
end if;
end process RX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- TX_ERROR_ACK_REG_PROCESS : Strobe error when transmit FIFO is full
-------------------------------- This signal will be OR'ed to generate IP2Bus_Error signal.
TX_ERROR_ACK_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Transmit_ip2bus_error <= '0';
else
Transmit_ip2bus_error <= Tx_FIFO_Full and Bus2IP_TxFIFO_WrCE;
end if;
end if;
end process TX_ERROR_ACK_REG_PROCESS;
-------------------------------------------------------------------------------
-- **********************************************************
-- Below logic will generate the inputs to the Interrupt bits
-- **********************************************************
-------------------------------------------------------------------------------
-- I_DRR_OVERRUN_REG_PROCESS:DRR overrun strobe-1 cycle strobe will be generated
-----------------------------
--DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-------
--begin
-------
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- DRR_Overrun_reg_int <= '0';
-- else
-- DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
-- Rc_FIFO_Full and
-- SPIXfer_done;
-- end if;
-- end if;
--end process DRR_OVERRUN_REG_PROCESS;
-------------------------------------------------------------------------------
-- RX_FIFO_STROBE_REG_PROCESS : Strobe when receive FIFO is full
----------------------------------
RX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk) is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
rc_FIFO_Full_d1 <= '0';
else
rc_FIFO_Full_d1 <= Rc_FIFO_Full;
end if;
end if;
end process RX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Rc_FIFO_Full_strobe <= (not rc_FIFO_Full_d1) and Rc_FIFO_Full;
-- TX_FIFO_STROBE_REG_PROCESS : Strobe when transmit FIFO is empty
----------------------------------
TX_FIFO_STROBE_REG_PROCESS:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Empty_d1 <= '1';
else
tx_FIFO_Empty_d1 <= Tx_FIFO_Empty;
end if;
end if;
end process TX_FIFO_STROBE_REG_PROCESS;
-----------------------------------------
Tx_FIFO_Empty_strobe <= (not tx_FIFO_Empty_d1) and Tx_FIFO_Empty;
-------------------------------------------------------------------------------
-- DTR_UNDERRUN_REG_PROCESS_P : Strobe to interrupt for transmit data underrun
-- which happens only in slave mode
-----------------------------
DTR_UNDERRUN_REG_PROCESS_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
dtr_underrun_d1 <= '0';
else
dtr_underrun_d1 <= DTR_underrun;
end if;
end if;
end process DTR_UNDERRUN_REG_PROCESS_P;
---------------------------------------
DTR_Underrun_strobe <= DTR_underrun and (not dtr_underrun_d1);
-------------------------------------------------------------------------------
-- TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P : Strobe for when transmit FIFO is
-- less than half full
-------------------------------------------
TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_FIFO_Occpncy_MSB_d1 <= '0';
else
tx_FIFO_Occpncy_MSB_d1 <= Tx_FIFO_Occpncy_MSB;
end if;
end if;
end process TX_FIFO_HALFFULL_STROBE_REG_PROCESS_P;
--------------------------------------------------
Tx_FIFO_less_half <= tx_FIFO_Occpncy_MSB_d1 and (not Tx_FIFO_Occpncy_MSB);
--------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
9ca7abbff1f582596c6b879d4f07aa53
| 0.439543 | 4.683185 | false | false | false | false |
Apollinaire/GameOfLife_FPGA
|
sources/CellArray.vhd
| 1 | 59,492 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.01.2017 10:52:07
-- Design Name:
-- Module Name: CellArray - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.TableType.ALL;
entity CellArray is
Generic ( HEIGHT : integer := 60;
WIDTH : integer := 80);
Port ( CLK : in STD_LOGIC;
CLK_SLOW : in STD_LOGIC;
RST : in STD_LOGIC;
STATE : out TABLE(WIDTH downto 1, HEIGHT downto 1));
end CellArray;
architecture Behavioral of CellArray is
signal tableNumber : integer range 0 to 4 := 0;
--constant voidTable : TABLE(33 downto 0, 25 downto 0) := ((others=> (others=>'0')));
--constant voidTable : TABLE(41 downto 0, 31 downto 0) := ((others=> (others=>'0')));
--constant voidTable : TABLE(65 downto 0, 49 downto 0) := ((others=> (others=>'0')));
--constant initTable : TABLE(33 downto 0, 25 downto 0) :=
-- ("00000000000000000000000000",
-- "00100000000000000000000000",
-- "00010000000000000000000000",
-- "01110000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000",
-- "00000000000000000000000000");
--constant initTable : TABLE(41 downto 0, 31 downto 0) :=
-- ("00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000011000000",
-- "00000000000000000000000011000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000111000000",
-- "00000000000000000000001000100000",
-- "00000000000000000000010000010000",
-- "00000000000000000000010000010000",
-- "00000000000000000000000010000000",
-- "00000000000000000000001000100000",
-- "00000000000000000000000111000000",
-- "00000000000000000000000010000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000001110000",
-- "00000000000000000000000001110000",
-- "00000000000000000000000010001000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000110001100",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000110000",
-- "00000000000000000000000000110000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000",
-- "00000000000000000000000000000000");
--constant initTable : TABLE(65 downto 0, 49 downto 0) :=
-- ("00000000000000000000000000000000000000000000000000",
-- "00100000000000000000000000000000000000000000000000",
-- "00010000000000000000000000000000000000000000000000",
-- "01110000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000");
signal initTable : TABLE(81 downto 0, 61 downto 0) :=
("00000000000000000000000000000000000000000000000000000000000000",
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"00010000000000000000000000000000000000000000000000000000000000",
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"00111000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000");
constant initTable0 : TABLE(81 downto 0, 61 downto 0) :=
("00000000000000000000000000000000000000000000000000000000000000",
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"00010000000000000000000000000000000000000000000000000000000000",
"00001000000000000000000000000000000000000000000000000000000000",
"00111000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000");
constant initTable1 : TABLE(81 downto 0, 61 downto 0) :=
("00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000100000000000000000000000000000",
"00000000000000000000000000000000101000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000010000000000000000000000000000",
"00000000000000000000000000000000100000000000000000000000000000",
"00000000000000000000000000000000100000000000000000000000000000",
"00000000000000000000000000000000100000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000");
constant initTable2 : TABLE(81 downto 0, 61 downto 0) :=
("00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000");
constant initTable3 : TABLE(81 downto 0, 61 downto 0) :=
("00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000011000000",
"00000000000000000000000000000000000000000000000000000011000000",
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"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000");
constant initTable4 : TABLE(81 downto 0, 61 downto 0) :=
("00000000000000000000000000000000000000000000000000000000000000",
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"00010000000000000000000000000000000000000000000000000000000000",
"00001000000000000000000000000000000000000000000000000000000000",
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"00000000000000000000000000000000000000000000000000000000000000",
"00000000000000000000000000000000000000000000000000000000000000");
--constant initTable : TABLE(129 downto 0, 97 downto 0) :=
-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "01110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
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-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
-- "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000");
signal internalState : TABLE(WIDTH+1 downto 0, HEIGHT+1 downto 0) := initTable;
component Cell is
generic (CELL_INIT : STD_LOGIC := '0');
Port ( CLK : in STD_LOGIC;
CLK_E : in STD_LOGIC;
PROX : in STD_LOGIC_VECTOR(7 downto 0);
RST : in STD_LOGIC;
RST_VALUE : in STD_LOGIC;
STATE : out STD_LOGIC);
end component;
begin
-- Using a generate loop for the Cell matrix
MAPGEN: FOR i IN 1 TO WIDTH generate
LINGEN: FOR j IN 1 TO HEIGHT generate
CellX : Cell generic map (initTable1(i,j)) port map (CLK => CLK,
CLK_E => CLK_SLOW,
PROX => (internalState(i+1,j)&internalState(i+1,j+1)&internalState(i,j+1)&internalState(i-1,j+1)&internalState(i-1,j)&internalState(i-1,j-1)&internalState(i,j-1)&internalState(i+1,j-1)),
RST => RST,
RST_VALUE => initTable(i,j),
STATE => internalState(i,j));
end generate LINGEN;
end generate MAPGEN;
-- Connect internalState to STATE output. FOR LOOP needs to be in a process.
process(internalState)
begin
STATE_CONNECT_LINE: FOR i IN 1 TO WIDTH loop
STATE_CONNECT_CELL: FOR j IN 1 TO HEIGHT loop
STATE(i,j) <= internalState(i,j);
end loop STATE_CONNECT_CELL;
end loop STATE_CONNECT_LINE;
end process;
process(RST) -- reset button changes the original map between 5 maps
begin
if (RST = '1' AND RST'EVENT) then
if (tableNumber = 0) then
initTable <= initTable1;
tableNumber <= tableNumber+1;
elsif (tableNumber = 1) then
initTable <= initTable1;
tableNumber <= tableNumber+1;
elsif (tableNumber = 2) then
initTable <= initTable2;
tableNumber <= tableNumber+1;
elsif (tableNumber = 3) then
initTable <= initTable3;
tableNumber <= tableNumber+1;
elsif (tableNumber = 4) then
initTable <= initTable4;
tableNumber <= 0;
end if;
end if;
end process;
end Behavioral;
|
mit
|
4d7959fc7e1597023fdb044b0f83c8b9
| 0.857762 | 12.70925 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP3_roulette_vhdl/shiftled.vhd
| 1 | 1,260 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:01:25 10/17/2014
-- Design Name:
-- Module Name: shiftled - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shiftled is
Port ( clk : in STD_LOGIC;
E : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end shiftled;
architecture Behavioral of shiftled is
signal count : std_logic_vector (7 downto 0):= x"01";
begin
process(clk)
begin
if clk'event and clk='1' then
if E='1' then
count<= count(6 downto 0) & count(7);
end if;
end if;
end process;
Q <= count;
end Behavioral;
|
gpl-2.0
|
6a87268e3c29ee6dca48d54aadf15e2f
| 0.563492 | 3.925234 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_cmd_split.vhd
| 4 | 22,816 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
|
bsd-3-clause
|
a839e2a6e0423e21f9a8fa414fa1bc6c
| 0.504427 | 3.72263 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_crossbar_axi4_read_cntrl.vhd
| 1 | 12,673 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! Crossbar's Read Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.all;
entity plasoc_crossbar_axi4_read_cntrl is
generic (
axi_slave_amount : integer := 2;
axi_master_amount : integer := 4);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_read_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0);
axi_read_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0);
axi_address_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_data_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
s_axi_arvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_arready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rlast : in std_logic_vector(axi_master_amount*1-1 downto 0));
end plasoc_crossbar_axi4_read_cntrl;
architecture Behavioral of plasoc_crossbar_axi4_read_cntrl is
constant axi_slave_iden_width : integer := clogb2(axi_slave_amount);
constant axi_master_iden_width : integer := clogb2(axi_master_amount);
function reduce_enables_master(
enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable or_reduced : std_logic;
variable reduce_enables : std_logic_vector(axi_master_amount-1 downto 0);
begin
for each_master in 0 to axi_master_amount-1 loop
or_reduced := '0';
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount);
end loop;
reduce_enables(each_master) := or_reduced;
end loop;
return reduce_enables;
end;
function get_slave_handshakes (
valid : in std_logic_vector(axi_slave_amount-1 downto 0);
ready : in std_logic_vector(axi_master_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0) )
return std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
begin
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if valid(each_slave)='1' and ready(master_iden_buff)='1' then
slave_handshakes(each_slave) := '1';
end if;
end loop;
return slave_handshakes;
end;
function get_slave_permissions (
slave_valid : in std_logic_vector(axi_slave_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
reduced_address_enables : in std_logic_vector(axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
begin
for each_master in 0 to axi_master_amount-1 loop
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if each_master=master_iden_buff and slave_valid(each_slave)='1' and reduced_address_enables(master_iden_buff)='0' then
slave_permissions(each_slave) := '1';
exit;
end if;
end loop;
end loop;
return slave_permissions;
end;
function set_slave_enables_ff(
slave_permissions : in std_logic_vector(axi_slave_amount-1 downto 0);
slave_handshakes : in std_logic_vector(axi_slave_amount-1 downto 0);
master_iden : in std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
slave_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable master_iden_buff : integer range 0 to axi_master_amount-1;
variable slave_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
begin
slave_enables_buff := slave_enables;
for each_slave in 0 to axi_slave_amount-1 loop
master_iden_buff := to_integer(unsigned(master_iden((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width)));
if slave_permissions(each_slave)='1' then
slave_enables_buff(each_slave+master_iden_buff*axi_slave_amount) := '1';
elsif slave_handshakes(each_slave)='1' then
for each_master in 0 to axi_master_amount-1 loop
slave_enables_buff(each_slave+each_master*axi_slave_amount) := '0';
end loop;
end if;
end loop;
return slave_enables_buff;
end;
function reduce_enables_slave(
enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable or_reduced : std_logic;
variable reduce_enables : std_logic_vector(axi_slave_amount-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := '0';
for each_master in 0 to axi_master_amount-1 loop
or_reduced := or_reduced or enables(each_slave+each_master*axi_slave_amount);
end loop;
reduce_enables(each_slave) := or_reduced;
end loop;
return reduce_enables;
end;
function get_master_handshakes (
valid : in std_logic_vector(axi_master_amount-1 downto 0);
ready : in std_logic_vector(axi_slave_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0) )
return std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if valid(each_master)='1' and ready(slave_iden_buff)='1' then
master_handshakes(each_master) := '1';
end if;
end loop;
return master_handshakes;
end;
function get_master_permissions (
master_valid : in std_logic_vector(axi_master_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
reduced_data_enables : in std_logic_vector(axi_slave_amount-1 downto 0) ) return
std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
for each_slave in 0 to axi_slave_amount-1 loop
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if each_slave=slave_iden_buff and master_valid(each_master)='1' and reduced_data_enables(slave_iden_buff)='0' then
master_permissions(each_master) := '1';
exit;
end if;
end loop;
end loop;
return master_permissions;
end;
function set_master_enables_ff (
master_permissions : in std_logic_vector(axi_master_amount-1 downto 0);
master_handshakes : in std_logic_vector(axi_master_amount-1 downto 0);
master_last : in std_logic_vector(axi_master_amount-1 downto 0);
slave_iden : in std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
master_enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return
std_logic_vector is
variable slave_iden_buff : integer range 0 to axi_slave_amount-1;
variable master_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
begin
master_enables_buff := master_enables;
for each_master in 0 to axi_master_amount-1 loop
slave_iden_buff := to_integer(unsigned(slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width)));
if master_permissions(each_master)='1' then
master_enables_buff(slave_iden_buff+each_master*axi_slave_amount) := '1';
elsif master_handshakes(each_master)='1' and master_last(each_master)='1' then
for each_slave in 0 to axi_slave_amount-1 loop
master_enables_buff(each_slave+each_master*axi_slave_amount) := '0';
end loop;
end if;
end loop;
return master_enables_buff;
end;
signal address_slave_handshakes : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal axi_address_read_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0');
signal reduced_address_read_enables : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
signal slave_permissions : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal data_master_handshakes : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
signal axi_data_read_enables_buff : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) := (others=>'0');
signal reduced_data_read_enables : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
signal master_permissions : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
begin
axi_address_read_enables <= axi_address_read_enables_buff;
axi_data_read_enables <= axi_data_read_enables_buff;
process (s_axi_arvalid,m_axi_arready,axi_read_master_iden)
begin
address_slave_handshakes <= get_slave_handshakes(s_axi_arvalid,m_axi_arready,axi_read_master_iden);
end process;
process (axi_address_read_enables_buff)
begin
reduced_address_read_enables <= reduce_enables_master(axi_address_read_enables_buff);
end process;
process (s_axi_arvalid,axi_read_master_iden,reduced_address_read_enables)
begin
slave_permissions <= get_slave_permissions(s_axi_arvalid,axi_read_master_iden,reduced_address_read_enables);
end process;
process (m_axi_rvalid,s_axi_rready,axi_read_slave_iden)
begin
data_master_handshakes <= get_master_handshakes(m_axi_rvalid,s_axi_rready,axi_read_slave_iden);
end process;
process (axi_data_read_enables_buff)
begin
reduced_data_read_enables <= reduce_enables_slave(axi_data_read_enables_buff);
end process;
process (m_axi_rvalid,axi_read_slave_iden,reduced_data_read_enables)
begin
master_permissions <= get_master_permissions(m_axi_rvalid,axi_read_slave_iden,reduced_data_read_enables);
end process;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_address_read_enables_buff <= (others=>'0');
axi_data_read_enables_buff <= (others=>'0');
else
axi_address_read_enables_buff <= set_slave_enables_ff(slave_permissions,address_slave_handshakes,axi_read_master_iden,axi_address_read_enables_buff);
axi_data_read_enables_buff <= set_master_enables_ff(master_permissions,data_master_handshakes,m_axi_rlast,axi_read_slave_iden,axi_data_read_enables_buff);
end if;
end if;
end process;
end Behavioral;
|
mit
|
b995e090b4daab1c0f82d8a6339ba950
| 0.636629 | 3.620857 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/ponq/pynq_ponq.vhd
| 1 | 2,498 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Alexander West
--
-- Create Date: 03/27/2017 02:41:10 PM
-- Design Name:
-- Module Name: pynq_ponq - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.filter_lib.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pynq_ponq is
generic(
NUM_BALLS : natural
);
port(
-- Video Interface
vid_i : in rgb_interface_t;
vid_o : out rgb_interface_t;
-- Pixel Coordinates
x_pos : in std_logic_vector(15 downto 0);
y_pos : in std_logic_vector(15 downto 0);
-- Register Inputs
--ball_in : ball_t;
balls : ball_vector_t(NUM_BALLS-1 downto 0);
-- Reference Clock
PIXEL_CLK : std_logic
);
end pynq_ponq;
architecture Behavioral of pynq_ponq is
signal ball_active : std_logic_vector(NUM_BALLS downto 0);
signal any_ball_active : std_logic;
signal temp_rgb : std_logic_vector(23 downto 0);
begin
-- Bounds check for each ball
for_balls:
for n in 0 to NUM_BALLS - 1 generate
ball_active(n)
<= '1'
when ((unsigned(x_pos) - balls(n).x) < balls(n).w)
and ((unsigned(y_pos) - balls(n).y) < balls(n).h)
else '0';
end generate;
-- Or reduce
any_ball_active <= or_reduce(ball_active);
-- Priority Decoder
process(balls, ball_active, vid_i)
begin
temp_rgb <= vid_i.rgb;
for ball in balls'range loop
if (ball_active(ball) = '1') then
temp_rgb <= balls(ball).color;
end if;
end loop;
end process;
-- Display logic
-- temp_rgb
-- <= (others=>'1')
-- when (any_ball_active = '1')
-- and (vid_i.vde = '1')
-- else vid_i.rgb;
-- Outputs
vid_o.vde <= vid_i.vde;
vid_o.hs <= vid_i.hs;
vid_o.vs <= vid_i.vs;
vid_o.rgb <= temp_rgb;
end Behavioral;
|
bsd-3-clause
|
4afc4f5cf3d2887cc02632f0527b945f
| 0.530424 | 3.563481 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/reset_sync_module.vhd
| 2 | 7,796 |
-------------------------------------------------------------------------------
-- reset_sync_module.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: reset_sync_module.vhd
-- Version: v3.0
-- Description: This is the reset sync module.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity reset_sync_module is
--generic();
port(EXT_SPI_CLK : in std_logic;
Soft_Reset_frm_axi: in std_logic;
Rst_to_spi : out std_logic
);
end entity reset_sync_module;
architecture imp of reset_sync_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal Soft_Reset_frm_axi_d1 : std_logic;
signal Soft_Reset_frm_axi_d2 : std_logic;
signal Soft_Reset_frm_axi_d3 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of RESET_SYNC_AX2S_1 : label is "TRUE";
-----
begin
-----
--RESET_SYNC_FROM_AXI_TO_SPI: process(EXT_SPI_CLK)is
-------
--begin
-------
-- if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1') then
-- Soft_Reset_frm_axi_d1 <= Soft_Reset_frm_axi;
-- Soft_Reset_frm_axi_d2 <= Soft_Reset_frm_axi_d1;
-- Soft_Reset_frm_axi_d3 <= Soft_Reset_frm_axi_d2;
-- end if;
--end process RESET_SYNC_FROM_AXI_TO_SPI;
-----------------------------------------
RESET_SYNC_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d1,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi,
R => '0'
);
RESET_SYNC_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Soft_Reset_frm_axi_d2,
C => EXT_SPI_CLK,
D => Soft_Reset_frm_axi_d1,
R => '0'
);
Rst_to_spi <= Soft_Reset_frm_axi_d2;
---------------------------------------
end architecture imp;
-------------------------------------------------------------------------------
|
bsd-3-clause
|
cf9c74509969529cf82cc682a59029f7
| 0.453822 | 4.785758 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_s2mm_basic_wrap.vhd
| 4 | 50,366 |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset;
use axi_datamover_v5_1_9.axi_datamover_cmd_status;
use axi_datamover_v5_1_9.axi_datamover_scc;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl;
use axi_datamover_v5_1_9.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_9.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_9.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_9.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_9.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
|
bsd-3-clause
|
282c7b5631f83a836d0e697c91da2470
| 0.443017 | 4.132425 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/img_overlay_duotone.vhd
| 1 | 13,531 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 03/17/2017 11:07:04 AM
-- Design Name: RGB filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter allows the edit of the RGB values of the pixel through
-- through user registers
--
-- Revision:
-- Revision 1.1
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin RGB Control architecture
architecture Behavioral of Video_Box is
--Create Red, Blue, Green signals that contain the actual Red,
--Blue, and Green signals
signal red, blue, green : std_logic_vector(7 downto 0);
--Create the register controlled Red, Green, and Blue signals
signal lred, lblue, lgreen : std_logic_vector(7 downto 0);
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
--signal USER_LOGIC : std_logic_vector(23 downto 0);
constant N : integer := 19;
component blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END component blk_mem_gen_0;
signal RGB_IN_reg0, RGB_IN_reg1 : std_logic_vector(23 downto 0);
signal VDE_IN_reg0, VDE_IN_reg1 : std_logic;
signal HB_IN_reg0, HB_IN_reg1 : std_logic;
signal VB_IN_reg0, VB_IN_reg1 : std_logic;
signal HS_IN_reg0, HS_IN_reg1 : std_logic;
signal VS_IN_reg0, VS_IN_reg1 : std_logic;
signal ID_IN_reg0, ID_IN_reg1 : std_logic;
signal rgb_next : std_logic_vector(23 downto 0);
signal use_image : std_logic;
--signal color_index, color_index_next : unsigned(7 downto 0);
signal image_index, image_index_next : unsigned(N-1 downto 0);
signal pixel : std_logic_vector(23 downto 0);
signal transparent : std_logic;
signal int_X_Coord_reg0, int_X_Coord_reg1 : unsigned(15 downto 0);
signal int_Y_Coord_reg0, int_Y_Coord_reg1 : unsigned(15 downto 0);
signal int_X_Orig_reg0, int_X_Orig_reg1 : unsigned(15 downto 0);
signal int_Y_Orig_reg0, int_Y_Orig_reg1 : unsigned(15 downto 0);
signal int_X_Coord : unsigned(15 downto 0);
signal int_Y_Coord : unsigned(15 downto 0);
signal int_X_Orig : unsigned(15 downto 0);
signal int_Y_Orig : unsigned(15 downto 0);
signal img_width : unsigned(15 downto 0);
signal img_height : unsigned(15 downto 0);
--signal din, dout : std_logic_vector(23 downto 0);
signal we, rden, wren : std_logic;
signal dout0 : std_logic_vector(0 downto 0); --std_logic_vector(7 downto 0);
signal rdaddr : std_logic_vector(N-1 downto 0);
signal wraddr : std_logic_vector(15 downto 0);
signal din : std_logic_vector(7 downto 0);
begin
--the user can edit the rgb values here
process(PIXEL_CLK)
begin
if(PIXEL_CLK'event and PIXEL_CLK='1') then
RGB_IN_reg0 <= RGB_IN_reg;
VDE_IN_reg0 <= VDE_IN_reg;
HS_IN_reg0 <= HS_IN_reg;
VS_IN_reg0 <= VS_IN_reg;
int_X_Coord_reg0 <= unsigned(X_Coord_reg);
int_Y_Coord_reg0 <= unsigned(Y_Coord_reg);
int_X_Orig_reg0 <= unsigned(slv_reg0(15 downto 0));
int_Y_Orig_reg0 <= unsigned(slv_reg1(15 downto 0));
RGB_IN_reg1 <= RGB_IN_reg0;
VDE_IN_reg1 <= VDE_IN_reg0;
HS_IN_reg1 <= HS_IN_reg0;
VS_IN_reg1 <= VS_IN_reg0;
int_X_Coord_reg1 <= int_X_Coord_reg0;
int_Y_Coord_reg1 <= int_Y_Coord_reg0;
int_X_Orig_reg1 <= int_X_Coord_reg0;
int_Y_Orig_reg1 <= int_Y_Coord_reg0;
image_index <= image_index_next;
end if;
end process;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= rgb_next;
VDE_OUT_reg <= VDE_IN_reg1;
HS_OUT_reg <= HS_IN_reg1;
VS_OUT_reg <= VS_IN_reg1;
end if;
end process;
-- process(S_AXI_ACLK) is
-- begin
-- if(rising_edge(S_AXI_ACLK)) then
wraddr <= slv_reg6(23 downto 8);
din <= slv_reg6(7 downto 0);
wren <= slv_reg_wren;
-- end if;
-- end process;
bram0: blk_mem_gen_0
port map(
clka => S_AXI_ACLK,
ena => wren,
wea(0) => we,
addra => wraddr,
dina => din,
clkb => PIXEL_CLK,
enb => rden,
addrb => rdaddr,
doutb => dout0
);
we <= '1';
rden <= '1';
rdaddr <= std_logic_vector(image_index);
-- Add user logic here
int_X_Coord <= int_X_Coord_reg1;
int_Y_Coord <= int_Y_Coord_reg1;
int_X_Orig <= unsigned(slv_reg0(15 downto 0));
int_Y_Orig <= unsigned(slv_reg1(15 downto 0));
img_width <= unsigned(slv_reg2(15 downto 0));
img_height <= unsigned(slv_reg3(15 downto 0));
use_image <= '1' when int_X_Coord >= int_X_Orig and
int_X_Coord < int_X_Orig + img_width and
int_Y_Coord >= int_Y_Orig and
int_Y_Coord < int_Y_Orig + img_height
else '0';
image_index_next <= (others => '0') when unsigned(X_Coord_reg) = int_X_Orig and unsigned(Y_Coord_reg) = int_Y_Orig and VDE_IN_reg='1' else
image_index + 1 when use_image = '1' and VDE_IN_reg='1' else
image_index;
pixel <= slv_reg4(23 downto 0) when dout0 = "0" else slv_reg5(23 downto 0);
transparent <= '1' when dout0(0)='0' and slv_reg4(24)='1' else '1' when dout0(0) = '1' and slv_reg5(24)='1' else '0';
--transparent <= '1' when dout0(0) = '0' else '0';
rgb_next <= pixel when use_image = '1' and transparent = '0' else RGB_IN_reg1;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
-- Route the registers through
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if( S_AXI_WSTRB(byte_index) = '1') then
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End RGB Control architecture
|
bsd-3-clause
|
f3044879e1e787aefb6e3d1119297dd5
| 0.584805 | 3.130002 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_axi4_full2lite.vhd
| 1 | 18,521 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Slave AXI4-Full to Master AXI4-Lite
--! (Full2Lite) Core.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! The Full2Lite Core reduces a single Slave AXI4-Full interface down
--! to a Master AXI4-Lite interface so that peripherals that don't require
--! burst transactions can be accessed by the CPU through its Full interface.
--! Because AXI4-Lite excludes support of burst transactions, the Full2Lite Core
--! is implemented such that burst sizes greater than 1 result in undefined behavior.
--!
--! Utilizing this Core simply consists performing a AXI4-Full transaction through its
--! Slave interface. The equivalent AXI4-Lite operation will occur on the Core's Master
--! interface. More information on the Advanced eXtensible Interfaces can be found in
--! official ARM AMBA4 documentation.
entity plasoc_axi4_full2lite is
generic (
axi_slave_id_width : integer := 1; --! Defines the ID width of the Slave AXI4-Full interface.
axi_address_width : integer := 32; --! Defines the address width of both Slave and Master AXI4 interfaces.
axi_data_width : integer := 32 --! Defines the data width of both Slave and Master AXI4 interfaces
);
port (
-- Global interface.
aclk : in std_logic; --! Defines the AXI4-Lite Address Width.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Full Write interface.
s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awlen : in std_logic_vector(8-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awsize : in std_logic_vector(3-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awburst : in std_logic_vector(2-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awlock : in std_logic; --! AXI4-Full Address Write signal.
s_axi_awcache : in std_logic_vector(4-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awprot : in std_logic_vector(3-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awqos : in std_logic_vector(4-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awregion : in std_logic_vector(4-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_awvalid : in std_logic; --! AXI4-Full Address Write signal.
s_axi_awready : out std_logic; --! AXI4-Full Address Write signal.
s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Full Write Data signal.
s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Full Write Data signal.
s_axi_wlast : in std_logic; --! AXI4-Full Write Data signal.
s_axi_wvalid : in std_logic; --! AXI4-Full Write Data signal.
s_axi_wready : out std_logic; --! AXI4-Full Write Data signal.
s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0); --! AXI4-Full Write Response signal.
s_axi_bresp : out std_logic_vector(2-1 downto 0); --! AXI4-Full Write Response signal.
s_axi_bvalid : out std_logic; --! AXI4-Full Write Response signal.
s_axi_bready : in std_logic; --! AXI4-Full Write Response signal.
-- Slave AXI4-Full Read outterface.
s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_arlen : in std_logic_vector(8-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_arsize : in std_logic_vector(3-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_arburst : in std_logic_vector(2-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_arlock : in std_logic; --! AXI4-Full Address Read signal.
s_axi_arcache : in std_logic_vector(4-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_arprot : in std_logic_vector(3-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_arqos : in std_logic_vector(4-1 downto 0); --! AXI4-Full Address Read signal.
s_axi_arregion : in std_logic_vector(4-1 downto 0); --! AXI4-Full Address Write signal.
s_axi_arvalid : in std_logic; --! AXI4-Full Address Read signal.
s_axi_arready : out std_logic; --! AXI4-Full Address Read signal.
s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0); --! AXI4-Full Read Data signal.
s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Full Read Data signal.
s_axi_rresp : out std_logic_vector(2-1 downto 0); --! AXI4-Full Read Data signal.
s_axi_rlast : out std_logic; --! AXI4-Full Read Data signal.
s_axi_rvalid : out std_logic; --! AXI4-Full Read Data signal.
s_axi_rready : in std_logic; --! AXI4-Full Read Data signal.
-- Master AXI4-Lite Write interface.
m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
m_axi_awprot : out std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
m_axi_awvalid : out std_logic; --! AXI4-Lite Address Write signal.
m_axi_awready : in std_logic; --! AXI4-Lite Address Write signal.
m_axi_wvalid : out std_logic; --! AXI4-Lite Write Data signal.
m_axi_wready : in std_logic; --! AXI4-Lite Write Data signal.
m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
m_axi_bvalid : in std_logic; --! AXI4-Lite Write Response signal.
m_axi_bready : out std_logic; --! AXI4-Lite Write Response signal.
m_axi_bresp : in std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Master AXI4-Lite Read interface.
m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
m_axi_arprot : out std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
m_axi_arvalid : out std_logic; --! AXI4-Lite Address Read signal.
m_axi_arready : in std_logic; --! AXI4-Lite Address Read signal.
m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
m_axi_rvalid : in std_logic; --! AXI4-Lite Read Data signal.
m_axi_rready : out std_logic; --! AXI4-Lite Read Data signal.
m_axi_rresp : in std_logic_vector(1 downto 0) --! AXI4-Lite Read Data signal.
);
end plasoc_axi4_full2lite;
architecture Behavioral of plasoc_axi4_full2lite is
component plasoc_axi4_full2lite_write_cntrl is
generic (
axi_slave_id_width : integer := 1;
axi_address_width : integer := 32;
axi_data_width : integer := 32);
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
s_axi_awlen : in std_logic_vector(8-1 downto 0);
s_axi_awsize : in std_logic_vector(3-1 downto 0);
s_axi_awburst : in std_logic_vector(2-1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(4-1 downto 0);
s_axi_awprot : in std_logic_vector(3-1 downto 0);
s_axi_awqos : in std_logic_vector(4-1 downto 0);
s_axi_awregion : in std_logic_vector(4-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0) := (others=>'0');
s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others=>'0');
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0) := (others=>'0');
m_axi_awprot : out std_logic_vector(2 downto 0) := (others=>'0');
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0) := (others=>'0');
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0));
end component;
component plasoc_axi4_full2lite_read_cntrl is
generic (
axi_slave_id_width : integer := 1;
axi_address_width : integer := 32;
axi_data_width : integer := 32);
port(
aclk : in std_logic;
aresetn : in std_logic;
s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
s_axi_arlen : in std_logic_vector(8-1 downto 0);
s_axi_arsize : in std_logic_vector(3-1 downto 0);
s_axi_arburst : in std_logic_vector(2-1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(4-1 downto 0);
s_axi_arprot : in std_logic_vector(3-1 downto 0);
s_axi_arqos : in std_logic_vector(4-1 downto 0);
s_axi_arregion : in std_logic_vector(4-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0) := (others=>'0');
s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rresp : in std_logic_vector(1 downto 0));
end component;
begin
plasoc_axi4_full2lite_write_cntrl_inst : plasoc_axi4_full2lite_write_cntrl
generic map (
axi_slave_id_width => axi_slave_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awqos => s_axi_awqos,
s_axi_awregion => s_axi_awregion,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awprot => m_axi_awprot,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp => m_axi_bresp);
plasoc_axi4_full2lite_read_cntrl_inst : plasoc_axi4_full2lite_read_cntrl
generic map (
axi_slave_id_width => axi_slave_id_width,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width)
port map (
aclk => aclk,
aresetn => aresetn,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arqos => s_axi_arqos,
s_axi_arregion => s_axi_arregion,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_araddr => m_axi_araddr,
m_axi_arprot => m_axi_arprot,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rdata => m_axi_rdata,
m_axi_rvalid => m_axi_rvalid, --! AXI4-Lite Read Data signal.
m_axi_rready => m_axi_rready,
m_axi_rresp => m_axi_rresp);
end Behavioral;
|
mit
|
e356b49fea0c50633edb9f8e5a3b6eae
| 0.44868 | 4.376418 | false | false | false | false |
makestuff/dvr-connectors
|
conv-72to8/vhdl/conv_72to8.vhdl
| 1 | 4,307 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_72to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 72-bit data coming in
data72_in : in std_logic_vector(71 downto 0);
valid72_in : in std_logic;
ready72_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_72to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3,
S_WRITE4,
S_WRITE5,
S_WRITE6,
S_WRITE7,
S_WRITE8
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(63 downto 0) := (others => '0');
signal wip_next : std_logic_vector(63 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data72_in, valid72_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(63 downto 56);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(55 downto 48);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE3;
end if;
-- Write byte 3
when S_WRITE3 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(47 downto 40);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE4;
end if;
-- Write byte 4
when S_WRITE4 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(39 downto 32);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE5;
end if;
-- Write byte 5
when S_WRITE5 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(31 downto 24);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE6;
end if;
-- Write byte 6
when S_WRITE6 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE7;
end if;
-- Write byte 7
when S_WRITE7 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE8;
end if;
-- Write byte 8 (LSB)
when S_WRITE8 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready72_out <= ready8_in; -- ready for data from 72-bit side
data8_out <= data72_in(71 downto 64);
valid8_out <= valid72_in;
if ( valid72_in = '1' and ready8_in = '1' ) then
wip_next <= data72_in(63 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
c6b802d250a38d68101dde61fc2e9e4c
| 0.595542 | 2.856101 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_mode_control_logic.vhd
| 2 | 175,152 |
--
---- qspi_mode_control_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_control_logic.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
entity qspi_mode_control_logic is
generic(
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_SUB_FAMILY : string
);
port(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
--------------------
DTR_FIFO_Data_Exists : in std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Data_To_Rx_FIFO_1 : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
SPIXfer_done_Rx_Wr_en: out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
--SR_6_Rx_Full : in std_logic;
--Last_count : in std_logic;
---------------------- from control register
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
---------------------- from look up table
Data_Dir : in std_logic;
Data_Mode_1 : in std_logic;
Data_Mode_0 : in std_logic;
Data_Phase : in std_logic;
----------------------
Quad_Phase : in std_logic;
--Dummy_Bits : in std_logic_vector(3 downto 0);
----------------------
Addr_Mode_1 : in std_logic;
Addr_Mode_0 : in std_logic;
Addr_Bit : in std_logic;
Addr_Phase : in std_logic;
----------------------
CMD_Mode_1 : in std_logic;
CMD_Mode_0 : in std_logic;
CMD_Error : in std_logic;
CMD_decoded : in std_logic;
----------------------
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
IO0_I : in std_logic;
IO0_O : out std_logic; -- MOSI
IO0_T : out std_logic;
IO1_I : in std_logic; -- MISO
IO1_O : out std_logic;
IO1_T : out std_logic;
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
Control_bit_7_8 : in std_logic_vector(0 to 1); --(7 to 8)
pr_state_idle : out std_logic;
Rx_FIFO_Full : in std_logic ;
DRR_Overrun_reg : out std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic
);
end entity qspi_mode_control_logic;
----------------------------------
architecture imp of qspi_mode_control_logic is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-- function declaration
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
return 2;
end if;
end spcl_log2;
-- type declaration
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
CMD_SEND,
ADDR_SEND,TEMP_ADDR_SEND,
--DUMMY_SEND,
DATA_SEND,TEMP_DATA_SEND,
DATA_RECEIVE,TEMP_DATA_RECEIVE
);
signal qspi_cntrl_ps: STATE_TYPE;
signal qspi_cntrl_ns: STATE_TYPE;
-----------------------------------------
-- signal declaration
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector(COUNT_WIDTH downto 0);
signal Count_1 : std_logic_vector(COUNT_WIDTH downto 0);
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
signal Serial_Dout_0 : std_logic;
signal Serial_Dout_1 : std_logic;
signal Serial_Dout_2 : std_logic;
signal Serial_Dout_3 : std_logic;
signal Serial_Din_0 : std_logic;
signal Serial_Din_1 : std_logic;
signal Serial_Din_2 : std_logic;
signal Serial_Din_3 : std_logic;
signal io2_i_sync : std_logic;
signal io3_i_sync : std_logic;
signal serial_dout_int : std_logic;
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal master_tri_state_en_control : std_logic;
signal IO0_tri_state_en_control : std_logic;
signal IO1_tri_state_en_control : std_logic;
signal IO2_tri_state_en_control : std_logic;
signal IO3_tri_state_en_control : std_logic;
signal SCK_tri_state_en_control : std_logic;
signal SPISEL_sync : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal MODF_strobe_int : std_logic;
signal Load_tx_data_to_shift_reg_int : std_logic;
signal mode_0 : std_logic;
signal mode_1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_d3 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SCK_O_1 : std_logic;-- :='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--:=(others => '0');
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal pr_state_cmd_ph : std_logic;
signal pr_state_addr_ph : std_logic;
signal pr_state_dummy_ph : std_logic;
signal pr_state_data_receive : std_logic;
signal pr_state_non_idle : std_logic;
signal addr_cnt : std_logic_vector(2 downto 0);
signal dummy_cnt : std_logic_vector(3 downto 0);
signal stop_clock : std_logic;
signal IO0_T_control : std_logic;
signal IO1_T_control : std_logic;
signal IO2_T_control : std_logic;
signal IO3_T_control : std_logic;
signal dummy : std_logic;
signal no_slave_selected : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Data_To_Rx_FIFO_2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
------------------------attribute IOB : string;
------------------------attribute IOB of QSPI_SCK_T : label is "true";
signal Mst_Trans_inhibit_d1 : std_logic;
signal Mst_Trans_inhibit_pulse : std_logic;
signal stop_clock_reg : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal transfer_start_pulse_11: std_logic;
signal DRR_Overrun_reg_int : std_logic;
signal Rx_FIFO_Full_reg : std_logic;
signal SPIXfer_done_drr : std_logic;
-----
begin
-----
SPIXfer_done <= SPIXfer_done_drr;
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
IO0_O <= Serial_Dout_0;
IO1_O <= Serial_Dout_1;
IO2_O <= Serial_Dout_2;
IO3_O <= Serial_Dout_3;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(Rx_FIFO_Full = '1')then
-- Rx_FIFO_Full_reg <= '1';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
--
--DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-------
--begin
-------
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- DRR_Overrun_reg_int <= '0';
-- else
-- DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
-- Rx_FIFO_Full_reg and
-- SPIXfer_done_int_pulse_d2;
-- end if;
-- end if;
--end process DRR_OVERRUN_REG_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full and
SPIXfer_done_drr;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_SS_T: tri-state register for SS,ideal state-deactive
QSPI_SS_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--------------------------------------
--QSPI_SCK_T : Tri-state register for SCK_T, ideal state-deactive
SCK_tri_state_en_control <= '0' when
(
-- (pr_state_non_idle = '1') and -- CR#619275 - this is commented to operate the mode 3 with SW flow
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
QSPI_SCK_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => SCK_tri_state_en_control
);
IO0_tri_state_en_control <= '0' when
(
(IO0_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO0_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO0_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO0_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO1_tri_state_en_control <= '0' when
(
(IO1_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO1_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO1_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO1_tri_state_en_control
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
QSPI_NO_MODE_2_T_CONTROL: if C_SPI_MODE = 1 or C_SPI_MODE = 0 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '1';
IO3_tri_state_en_control <= '1';
IO2_T <= '1';
IO3_T <= '1';
--------------------------------------
end generate QSPI_NO_MODE_2_T_CONTROL;
--------------------------------------
-------------------------------------------------------------------------------
QSPI_MODE_2_T_CONTROL: if C_SPI_MODE = 2 generate
----------------------
begin
-----
--------------------------------------
IO2_tri_state_en_control <= '0' when
(
(IO2_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MOSI, ideal state-deactive
QSPI_IO2_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO2_T, -- MOSI_T,
C => Bus2IP_Clk,
D => IO2_tri_state_en_control -- master_tri_state_en_control
);
--------------------------------------
IO3_tri_state_en_control <= '0' when
(
(IO3_T_control = '0') and
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0')-- no mode fault
) else
'1';
--QSPI_IO0_T: tri-state register for MISO, ideal state-deactive
QSPI_IO3_T: component FD
generic map
(
INIT => '1'
)
port map
(
Q => IO3_T, -- MISO_T,
C => Bus2IP_Clk,
D => IO3_tri_state_en_control
);
--------------------------------------
end generate QSPI_MODE_2_T_CONTROL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_SPISEL: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
QSPI_SPISEL: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
-- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-----------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
else
spisel_d1 <= SPISEL_sync;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not SPISEL_sync) and spisel_d1;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- __________|--|_____ -- SPISEL_pulse_op
SPISEL_pulse_op <= not SPISEL_sync; -- spisel_pulse;
SPISEL_d1_reg <= spisel_d1;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,
CPHA,
SPIXfer_done_int,
transfer_start_pulse,
Mst_Trans_inhibit_pulse) is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)is
-----
begin
-----
--if(SPIXfer_done_int = '1' or transfer_start_pulse = '1') then
if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') then -- Tranfer not in progress
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in (C_NUM_SS_BITS-1) downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
----------------------------
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and
(Allow_MODF_Strobe = '1')
) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
--------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF
)is
-----
begin
-----
if(Soft_Reset_op = RESET_ACTIVE) then
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
(--(Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
)
)
)then
Load_tx_data_to_shift_reg_int <= '1'; --Set flag
else
Load_tx_data_to_shift_reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
------------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1' -- core is in Data Receive State and DRR is not full
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') -- or
--(SPIXfer_done_int_pulse_d1 = '1')-- or
--(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- glitch at the end of
-- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
--------------------------------
--TRANSFER_START_PROCESS: process(Bus2IP_Clk)is
-------
--begin
-------
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- (
-- (
-- SPI_En = '0' or -- enable not asserted or
-- (SR_5_Tx_Empty = '1' and Data_Phase = '0' and Addr_Phase = '0') or -- no data in Tx reg/FIFO or
-- SR_3_MODF = '1' or -- mode fault error
-- Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
-- stop_clock = '1' -- core is in Data Receive State and DRR is not full
-- )
-- )
-- )then
--
-- transfer_start <= '0';
-- else
---- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
---- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
-- if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1')-- or
-- --(SPIXfer_done_int_pulse_d2='1')
-- ) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
-- transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
-- end if;
-- end if;
--end process TRANSFER_START_PROCESS;
-------------------------------------
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
transfer_start_pulse_11 <= transfer_start_d2 and (not transfer_start_d3);
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
--------------------------------------------
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(mode_1 = '1' and mode_0 = '0')then
SPIXfer_done_int <= Count(1) and
not(Count(0));
elsif(mode_1 = '0' and mode_0 = '1')then
SPIXfer_done_int <= not(Count(0)) and
Count(2) and
Count(1);
else
SPIXfer_done_int <= --Count(COUNT_WIDTH);
Count(COUNT_WIDTH-1) and
Count(COUNT_WIDTH-2) and
Count(COUNT_WIDTH-3) and
not Count(COUNT_WIDTH-4);
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_1 <= (others => '0');
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d2 = '1')then
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
receive_Data_int <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
receive_Data_int <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
Data_To_Rx_FIFO_1 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
receive_Data_int <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
RECEIVE_DATA_STROBE_PROCESS_1: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
Data_To_Rx_FIFO_2 <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
Data_To_Rx_FIFO_2 <= Data_To_Rx_FIFO_1;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_1;
--receive_Data_int <= Data_To_Rx_FIFO_2;
-- Done strobe delayed to match receive data
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d3;
-- SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_d1; -- SPIXfer_done_int_pulse_d1;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
-- SPIXfer_done_rd_tx_en <= SPIXfer_done_int;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
RATIO_2_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if((Soft_Reset_op = RESET_ACTIVE) or
-- (transfer_start_d1 = '0') or
-- --(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
-- (Mst_N_Slv = '0')
-- )then
--
-- Count <= (others => '0');
-- elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
-- end if;
-- end if;
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPIXfer_done_int = '1') or
(transfer_start = '0')
--(transfer_start = '0' and SPIXfer_done_int_d1 = '1') or
--(Mst_N_Slv = '0')
)then
Count <= (others => '0');
elsif (Count(COUNT_WIDTH) = '0') and ((CPOL and CPHA) = '0') then
Count <= Count + 1;
elsif(transfer_start_d2 = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process RATIO_2_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
RATIO_2_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
--sck_o_int <= (not sck_o_int) xor Count(COUNT_WIDTH);
sck_o_int <= (not sck_o_int);
end if;
end if;
end process RATIO_2_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
RATIO_2_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
sck_d3 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
sck_d3 <= sck_d2;
end if;
end if;
end process RATIO_2_DELAY_CLK;
------------------------------------
-- Rising egde pulse
sck_rising_edge <= sck_d2 and (not sck_d1);
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
RATIO_2_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then --SPIXfer_done_int_pulse_d2
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_d3='0') and --(sck_rising_edge = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
)then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I ; --MISO_I;
elsif(mode_1 = '0' and mode_0 = '1')then -- for Dual transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I & -- MISO_I - MSB first
IO0_I ; -- MOSI_I
elsif(mode_1 = '1' and mode_0 = '0')then -- for Quad transfer
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I ;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process RATIO_2_CAPT_RX_FE_MODE_00_11;
----------------------------------
RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2
or
C_SPI_MODE = 1
)and
(C_SPI_MEMORY = 2
)
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
RATIO_2_CAP_QSPI_QUAD_MODE_SP_MEM_GEN: if (
(C_SPI_MODE = 2
or
C_SPI_MODE = 1
)and
(
C_SPI_MEMORY = 3)
)generate
--------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
--if(Load_tx_data_to_shift_reg_int = '1') then
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0')
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I ;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_SP_MEM_GEN;
RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
) generate
-----------------------------------------
begin
-----
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
RATIO_2_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
elsif(transfer_start = '1') then --(Mst_N_Slv = '1') then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then --
Shift_Reg <= Transmit_Data;
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;-- this is to make the DQ3 bit 1 in quad command transfer mode.
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
elsif(
(Count(0) = '0') --and
)then -- Shift Data on even
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
elsif(
(Count(0) = '1') --and
) then -- Capture Data on odd
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) &
IO1_I;-- MISO_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) &
IO1_I &
IO0_I ;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) &
IO3_I &
IO2_I &
IO1_I &
IO0_I ;
end if;
end if;
end if;
end if;
end process RATIO_2_CAPTURE_AND_SHIFT_PROCESS;
----------------------------------------------
end generate RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
------------------------------------------------------
-----
end generate RATIO_OF_2_GENERATE;
---------------------------------
--------==================================================================-----
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
------------------------------
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal. This will stop the SPI clock.
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1') then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
else
if(CPHA = '0' and CPOL = '0') then
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(0) and Count(1);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);--- and
--(and_reduce(Ratio_Count));-- dual mode
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
else
if(mode_1 = '1' and mode_0 = '0')then -- quad mode
SPIXfer_done_int <= Count(1) and
Count(0);
elsif(mode_1 = '0' and mode_0 = '1')then -- for dual mode
SPIXfer_done_int <= Count(2) and
Count(1) and
Count(0);
else
SPIXfer_done_int <= Count(COUNT_WIDTH-COUNT_WIDTH+3) and
Count(COUNT_WIDTH-COUNT_WIDTH+2) and
Count(COUNT_WIDTH-COUNT_WIDTH+1) and
Count(COUNT_WIDTH-COUNT_WIDTH);
end if;
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)then
receive_Data_int <= (others => '0');
elsif(SPIXfer_done_int_pulse_d1 = '1')then
receive_Data_int <= rx_shft_reg_mode_0011;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
begin
-----
-------------------------------------------------------------------------------
IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => mosi_i_sync,
C => Bus2IP_Clk,
D => IO0_I --MOSI_I
);
IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => miso_i_sync,
C => Bus2IP_Clk,
D => IO1_I -- MISO_I
);
NO_IO_x_I_SYNC_MODE_1_GEN: if C_SPI_MODE = 1 generate
-----
begin
-----
io2_i_sync <= '0';
io3_i_sync <= '0';
end generate NO_IO_x_I_SYNC_MODE_1_GEN;
---------------------------------------
IO_x_I_SYNC_MODE_2_GEN: if C_SPI_MODE = 2 generate
----------------
-----
begin
-----
-----------------------
IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io2_i_sync,
C => Bus2IP_Clk,
D => IO2_I
);
-----------------------
IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io3_i_sync,
C => Bus2IP_Clk,
D => IO3_I
);
-----------------------
end generate IO_x_I_SYNC_MODE_2_GEN;
------------------------------------
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
OTHER_RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process OTHER_RATIO_COUNT_PROCESS;
--------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
--(SPIXfer_done_int = '1') or
(transfer_start = '0')
) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_GEN_PROCESS;
--------------------------------------
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process OTHER_RATIO_COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE)or
(SPIXfer_done_int = '1') or
(transfer_start = '0') then
Count <= (others => '0');
--elsif (transfer_start = '0') then
-- Count <= (others => '0');
elsif (Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0') then
Count <= Count + 1;
end if;
end if;
end process OTHER_RATIO_SCK_CYCLE_COUNT_PROCESS;
------------------------------------
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
OTHER_RATIO_SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process OTHER_RATIO_SCK_SET_RESET_PROCESS;
----------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
OTHER_RATIO_DELAY_CLK: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process OTHER_RATIO_DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
OTHER_RATIO_CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and
(transfer_start = '1') and
(Data_Dir='0') -- data direction = 0 is read mode
--(pr_state_data_receive = '1')
) then
-------
if(mode_1 = '0' and mode_0 = '0')then -- for Standard transfer
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I;-- MISO_I
elsif((mode_1 = '0' and mode_0 = '1') -- for Dual transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(2 to (C_NUM_TRANSFER_BITS-1)) &
IO1_I &-- MSB first
IO0_I;
elsif((mode_1 = '1' and mode_0 = '0') -- for Quad transfer
)then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(4 to (C_NUM_TRANSFER_BITS-1)) &
IO3_I & -- MSB first
IO2_I &
IO1_I &
IO0_I;
end if;
-------
else
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011;
end if;
end if;
end process OTHER_RATIO_CAPT_RX_FE_MODE_00_11;
---------------------------------------------------------------------
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN: if (
(C_SPI_MODE = 2 or
C_SPI_MODE = 1) and
(C_SPI_MEMORY = 2)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_NM_MEM_GEN;
-------------------------------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_SP_MEM_GEN: if (
(C_SPI_MODE = 2 or
C_SPI_MODE = 1) and
(
C_SPI_MEMORY = 3)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_SP_MEM_GEN;
-------------------------------------------------------
OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN: if (
(C_SPI_MODE = 2 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
or
(C_SPI_MODE = 1 and
(C_SPI_MEMORY = 0
or
C_SPI_MEMORY = 1)
)
)generate
--------------------------------------
begin
-----
OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk) is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout_0 <= '0';-- default values of the IO0_O
Serial_Dout_1 <= '0';
Serial_Dout_2 <= '0';
Serial_Dout_3 <= '0';
else--if(
-- (transfer_start = '1') and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Load_tx_data_to_shift_reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
Shift_Reg <= Transmit_Data;-- loading trasmit data in SR
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Transmit_Data(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Transmit_Data(0); -- msb to IO1_O
Serial_Dout_0 <= Transmit_Data(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Transmit_Data(0); -- msb to IO3_O
Serial_Dout_2 <= Transmit_Data(1);
Serial_Dout_1 <= Transmit_Data(2);
Serial_Dout_0 <= Transmit_Data(3);
end if;
-- Capture Data on even Count
elsif(
(Count(0) = '0')
)then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Serial_Dout_0 <= Shift_Reg(0);
Serial_Dout_3 <= pr_state_cmd_ph and Quad_Phase;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Serial_Dout_1 <= Shift_Reg(0); -- msb to IO1_O
Serial_Dout_0 <= Shift_Reg(1);
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Serial_Dout_3 <= Shift_Reg(0); -- msb to IO3_O
Serial_Dout_2 <= Shift_Reg(1);
Serial_Dout_1 <= Shift_Reg(2);
Serial_Dout_0 <= Shift_Reg(3);
end if;
-- Shift Data on odd Count
elsif(
(Count(0) = '1') and
(Count_trigger_pulse = '1')
) then
if(mode_1 = '0' and mode_0 = '0') then -- standard mode
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & IO1_I;
elsif(mode_1 = '0' and mode_0 = '1') then -- dual mode
Shift_Reg <= Shift_Reg
(2 to C_NUM_TRANSFER_BITS -1) & IO1_I
& IO0_I;
elsif(mode_1 = '1' and mode_0 = '0') then -- quad mode
Shift_Reg <= Shift_Reg
(4 to C_NUM_TRANSFER_BITS -1) & IO3_I
& IO2_I
& IO1_I
& IO0_I;
end if;
end if;
end if;
end if;
end process OTHER_RATIO_CAPTURE_AND_SHIFT_PROCESS;
--------------------------------------------------
end generate OTHER_RATIO_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN;
-------------------------------------------------------
end generate OTHER_RATIO_GENERATE;
----------------------------------
--------------------------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
qspi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
qspi_cntrl_ps <= qspi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
pr_state_data_receive <= '1' when qspi_cntrl_ps = DATA_RECEIVE else
'0';
pr_state_non_idle <= '1' when qspi_cntrl_ps /= IDLE else
'0';
pr_state_idle <= '1' when qspi_cntrl_ps = IDLE else
'0';
pr_state_cmd_ph <= '1' when qspi_cntrl_ps = CMD_SEND else
'0';
--------------------------------
QSPI_DUAL_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 1 and
(
C_SPI_MEMORY = 0 or
C_SPI_MEMORY = 1
)
)generate
--------------------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO1_T_control <= (CMD_Mode_1) or (not CMD_Mode_0);
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
--stop_clock <= not SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => --if((SPIXfer_done_int_pulse='1')
-- )then
-- if (no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
-- else
-- stop_clock <= SR_5_Tx_Empty;
-- if(SR_5_Tx_Empty='1')then
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
-- else
-- qspi_cntrl_ns <= ADDR_SEND;
-- end if;
-- end if;
--else
-- qspi_cntrl_ns <= TEMP_ADDR_SEND;
--end if;
mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
--if(no_slave_selected = '1')then
-- qspi_cntrl_ns <= IDLE;
--else
-- qspi_cntrl_ns <= DATA_RECEIVE;
--end if;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when (qspi_cntrl_ps = ADDR_SEND) else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_MIXED_WB_MEM_GEN: if (C_SPI_MODE = 2 and
(C_SPI_MEMORY = 1 or
C_SPI_MEMORY = 0
)
)
generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Error ,
CMD_Mode_1 ,
CMD_Mode_0 ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
---------------------
qspi_cntrl_ps ,
no_slave_selected
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
--------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;--
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only
IO3_T_control <= not (Data_Mode_1);-- active only
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
-- -- coverage off
-- -- below piece of code is for 32-bit address check, and left for future use
-- elsif(
-- (addr_cnt = "100") and -- 32 bit
-- (Addr_Bit = '1') and (Data_Phase='1')
-- )then
-- if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
-- else
-- qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
-- end if;
-- -- coverage on
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
-----------------------------------------------------------------------
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0'; -- data output active only in Dual mode
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);-- active only in quad mode
IO3_T_control <= not (Data_Mode_1);-- active only in quad mode
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
------------------------------------------
end generate QSPI_QUAD_MODE_MIXED_WB_MEM_GEN;
------------------------------------------
--------------------------------------------------
QSPI_DUAL_MODE_NM_MEM_GEN: if C_SPI_MODE = 1 and (C_SPI_MEMORY = 2 ) generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_NM_MEM_GEN;
--------------------------------
QSPI_DUAL_MODE_SP_MEM_GEN: if C_SPI_MODE = 1 and (C_SPI_MEMORY = 3) generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
---------------------
SR_5_Tx_Empty ,
--SR_6_Rx_Full ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
--------------
stop_clock <= '0';
--------------
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_1;
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and (Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and (Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);-- (Addr_Mode_1) or(not Addr_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
--stop_clock <= SR_5_Tx_Empty;
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND =>
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= Data_Mode_1;
IO1_T_control <= not(Data_Mode_0);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
-- coverage off
when others => qspi_cntrl_ns <= IDLE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_DUAL_MODE_SP_MEM_GEN;
--------------------------------
--------------------------------------------------
QSPI_QUAD_MODE_NM_MEM_GEN: if C_SPI_MODE = 2 and (C_SPI_MEMORY = 2 )generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
--mode_1 <= Data_Mode_1;
--mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
--if((Data_Dir='1'))then
-- qspi_cntrl_ns <= DATA_SEND; -- o/p
--else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
--end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_QUAD_MODE_NM_MEM_GEN;
---------------------------------------
QSPI_QUAD_MODE_SP_MEM_GEN: if C_SPI_MODE = 2 and (C_SPI_MEMORY = 3)generate
-------------------
begin
-----
QSPI_CNTRL_PROCESS: process(
---------------------
CMD_decoded ,
CMD_Mode_1 ,
CMD_Mode_0 ,
CMD_Error ,
---------------------
Addr_Phase ,
Addr_Bit ,
Addr_Mode_1 ,
Addr_Mode_0 ,
---------------------
Data_Phase ,
Data_Dir ,
Data_Mode_1 ,
Data_Mode_0 ,
---------------------
addr_cnt ,
Quad_Phase ,
---------------------
SR_5_Tx_Empty ,
--SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse,
stop_clock_reg,
no_slave_selected ,
---------------------
qspi_cntrl_ps
---------------------
)is
-----
begin
-----
mode_1 <= '0';
mode_0 <= '0';
--------------
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
-------------
stop_clock <= '0';
case qspi_cntrl_ps is
when IDLE => if((CMD_decoded = '1') and
(CMD_Error = '0')-- proceed only when there is no command error
)then
qspi_cntrl_ns <= CMD_SEND;
else
qspi_cntrl_ns <= IDLE;
end if;
stop_clock <= '1';
------------------------------------------------
when CMD_SEND => mode_1 <= CMD_Mode_1;
mode_0 <= CMD_Mode_0;
IO0_T_control <= CMD_Mode_0;
IO3_T_control <= not Quad_Phase;-- this is due to sending '1' on DQ3 line during command phase for Quad instructions only.
--if(SPIXfer_done_int_pulse_d2 = '1')then
if(SPIXfer_done_int_pulse = '1')then
if(Addr_Phase='1')then
if(SR_5_Tx_Empty = '1') then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
else
qspi_cntrl_ns <= IDLE;
end if;
else
qspi_cntrl_ns <= CMD_SEND;
end if;
------------------------------------------------
when ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if((SR_5_Tx_Empty='1') and
(Data_Phase='0')
)then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
if(
(addr_cnt = "011") and -- 24 bit address
(Addr_Bit='0') and
(Data_Phase='1')
)then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
--mode_1 <= Data_Mode_1;
--mode_0 <= Data_Mode_0;
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
elsif(
(addr_cnt = "100") and -- 32 bit
(Addr_Bit = '1') and
(Data_Phase='1')
) then
if((Data_Dir='1'))then
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
qspi_cntrl_ns <= DATA_SEND; -- o/p
else
IO0_T_control <= '1';
IO1_T_control <= '1';
IO2_T_control <= '1';
IO3_T_control <= '1';
mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
qspi_cntrl_ns <= DATA_RECEIVE;-- i/p
end if;
else
qspi_cntrl_ns <= ADDR_SEND;
end if;
end if;
-- ------------------------------------------------
when TEMP_ADDR_SEND => mode_1 <= Addr_Mode_1;
mode_0 <= Addr_Mode_0;
IO0_T_control <= Addr_Mode_0 and Addr_Mode_1;
IO1_T_control <= not(Addr_Mode_0 xor Addr_Mode_1);
IO2_T_control <= (not Addr_Mode_1);
IO3_T_control <= (not Addr_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_ADDR_SEND;
else
qspi_cntrl_ns <= TEMP_ADDR_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= ADDR_SEND;
end if;
when DATA_SEND => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
qspi_cntrl_ns <= DATA_SEND;
end if;
------------------------------------------------
when TEMP_DATA_SEND=> mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
IO0_T_control <= '0';
IO1_T_control <= not(Data_Mode_1 xor Data_Mode_0);
IO2_T_control <= not (Data_Mode_1);
IO3_T_control <= not (Data_Mode_1);
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_SEND;
else
qspi_cntrl_ns <= TEMP_DATA_SEND;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_SEND;
end if;
when DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
--stop_clock <= SR_5_Tx_Empty;
if(SR_5_Tx_Empty='1')then
if(no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
when TEMP_DATA_RECEIVE => mode_1 <= Data_Mode_1;
mode_0 <= Data_Mode_0;
stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
if (no_slave_selected = '1')then
qspi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse='1')then
stop_clock <= SR_5_Tx_Empty;
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
else
qspi_cntrl_ns <= TEMP_DATA_RECEIVE;
end if;
else
stop_clock <= '0';
qspi_cntrl_ns <= DATA_RECEIVE;
end if;
------------------------------------------------
-- coverage off
when others => qspi_cntrl_ns <= IDLE; -- CMD_DECODE;
------------------------------------------------
-- coverage on
end case;
-------------------------------
end process QSPI_CNTRL_PROCESS;
-------------------------------
pr_state_addr_ph <= '1' when qspi_cntrl_ps = ADDR_SEND else
'0';
QSPI_ADDR_CNTR_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(pr_state_addr_ph = '0') then
addr_cnt <= (others => '0');
elsif(pr_state_addr_ph = '1')then
--addr_cnt <= addr_cnt + SPIXfer_done_int_pulse_d2;
addr_cnt <= addr_cnt + SPIXfer_done_int_pulse;
end if;
end if;
end process QSPI_ADDR_CNTR_PROCESS;
-----------------------------------
end generate QSPI_QUAD_MODE_SP_MEM_GEN;
---------------------------------------
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
-----
begin
-----
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(--Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
--(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
slave_mode <= not (Mst_N_Slv); -- create the reset condition by inverting the mst_n_slv signal. 1 - master mode, 0 - slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk). during slave mode no clock should be generated from the core.
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (’0’ or ’1’)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-------------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int ,
CPOL ,
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH)
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0'))then -- SM is in IDLE state or core in slave mode
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
-----
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv ,-- in master mode
sck_o_int ,-- value driven on sck_int
CPOL ,-- CPOL mode thr SPICR
transfer_start ,
transfer_start_d1 ,
Count(COUNT_WIDTH),
pr_state_non_idle -- State machine is in Non-idle state
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(pr_state_non_idle = '1')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
slave_mode <= not (Mst_N_Slv);-- dont allow SPI clock to go out when core is in slave mode.
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (’0’ or ’1’)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv, -- in master mode
sck_o_int, -- value driven on sck_int
CPOL, -- CPOL mode thr SPICR
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH)
)is
-----
begin
-----
if(--(Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') --and
--(Count(COUNT_WIDTH) = '0')--and
--(pr_state_non_idle = '1')
)then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE)
) then
SCK_O_reg <= '0';
elsif((pr_state_non_idle='0') or -- dont allow sck to go out when
(Mst_N_Slv = '0') -- SM is in IDLE state or core in slave mode
)then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
---------------------
end architecture imp;
---------------------
|
bsd-3-clause
|
6696d6d16ebd6a2637373a69c6b72a3d
| 0.338217 | 4.875181 | false | false | false | false |
tmeissner/cryptocores
|
cbcmac_des/sim/vhdl/tb_cbcmac_des.vhd
| 1 | 3,991 |
-- ======================================================================
-- CBC-MAC-DES testbench
-- Copyright (C) 2015 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_cbcmac_des is
end entity tb_cbcmac_des;
architecture sim of tb_cbcmac_des is
type t_array is array (natural range <>) of std_logic_vector(0 to 63);
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_start : std_logic := '0';
signal s_key : std_logic_vector(0 to 63) := (others => '0');
signal s_datain : std_logic_vector(0 to 63) := (others => '0');
signal s_validin : std_logic := '0';
signal s_acceptout : std_logic;
signal s_dataout : std_logic_vector(0 to 63);
signal s_validout : std_logic;
signal s_acceptin : std_logic;
component cbcmac_des is
port (
reset_i : in std_logic;
clk_i : in std_logic;
start_i : in std_logic;
key_i : in std_logic_vector(0 to 63);
data_i : in std_logic_vector(0 to 63);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 63);
valid_o : out std_logic;
accept_i : in std_logic
);
end component cbcmac_des;
-- key, plain & crypto stimuli values
-- taken from NIST website:
-- http://csrc.nist.gov/publications/fips/fips113/fips113.html
constant C_KEY : std_logic_vector(0 to 63) := x"0123456789abcdef";
constant C_PLAIN : t_array := (
x"3736353433323120", x"4e6f772069732074",
x"68652074696d6520", x"666f722000000000");
constant C_CRYPT : t_array := (
x"21fb193693a16c28", x"6c463f0cb7167a6f",
x"956ee891e889d91e", x"f1d30f6849312ca4");
begin
s_clk <= not(s_clk) after 10 ns;
s_reset <= '1' after 100 ns;
StimuliP : process is
begin
s_start <= '0';
s_key <= (others => '0');
s_datain <= (others => '0');
s_validin <= '0';
wait until s_reset = '1';
s_start <= '1';
for i in C_PLAIN'range loop
wait until rising_edge(s_clk);
s_validin <= '1';
s_key <= C_KEY;
s_datain <= C_PLAIN(i);
wait until rising_edge(s_clk) and s_acceptout = '1';
s_start <= '0';
s_validin <= '0';
end loop;
wait;
end process StimuliP;
CheckerP : process is
begin
s_acceptin <= '0';
wait until s_reset = '1';
for i in C_CRYPT'range loop
wait until rising_edge(s_clk);
s_acceptin <= '1';
wait until rising_edge(s_clk) and s_validout = '1';
assert s_dataout = C_CRYPT(i)
report "Encryption error"
severity failure;
s_acceptin <= '0';
end loop;
report "CBCMAC test successful :)";
wait;
end process CheckerP;
i_cbcmac_des : cbcmac_des
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
key_i => s_key,
data_i => s_datain,
valid_i => s_validin,
accept_o => s_acceptout,
data_o => s_dataout,
valid_o => s_validout,
accept_i => s_acceptin
);
end architecture sim;
|
gpl-2.0
|
9119bb377b2cb670d451c33c344f2720
| 0.574543 | 3.348154 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_mm2s_sg_if.vhd
| 4 | 47,020 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sg_if.vhd
-- Description: This entity is the MM2S Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Master AXI Control Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
desc_fetch_done : out std_logic ; --
updt_pending : out std_logic ;
packet_in_progress : out std_logic ; --
--
-- MM2S Descriptor Update Request (from mm2s_sm) --
desc_update_done : out std_logic ; --
--
mm2s_sts_received_clr : out std_logic ; --
mm2s_sts_received : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_done : in std_logic ; --
mm2s_interr : in std_logic ; --
mm2s_slverr : in std_logic ; --
mm2s_decerr : in std_logic ; --
mm2s_tag : in std_logic_vector(3 downto 0) ; --
mm2s_halt : in std_logic ; --
--
-- Control Stream Output --
cntrlstrm_fifo_wren : out std_logic ; --
cntrlstrm_fifo_din : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : in std_logic ; --
--
--
-- MM2S Descriptor Field Output --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_new_curdesc_wren : out std_logic ; --
--
mm2s_desc_baddress : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : out std_logic ; --
mm2s_desc_sof : out std_logic ; --
mm2s_desc_cmplt : out std_logic ; --
mm2s_desc_info : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_mm2s_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(4 downto 0) := (others => '0');
-- Used to determine when Control word is coming, in order to check SOF bit.
-- This then indicates that the app fields need to be directed towards the
-- control stream fifo.
-- Word Five Count
-- Incrementing these counts by 2 as i am now sending two extra fields from BD
--constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "1011"; --"0111";
constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "0001";
-- Word Six Count
--constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0101"; --"1000";
constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0010";
-- Word Seven Count
--constant NINE_COUNT : std_logic_vector(3 downto 0) := "1010"; --"1001";
constant NINE_COUNT : std_logic_vector(3 downto 0) := "0011";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal desc_fetch_done_i : std_logic := '0';
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Fetch control signals for driving out control app stream
signal analyze_control : std_logic := '0';
signal redirect_app : std_logic := '0';
signal redirect_app_d1 : std_logic := '0';
signal redirect_app_re : std_logic := '0';
signal redirect_app_hold : std_logic := '0';
signal mask_fifo_write : std_logic := '0';
-- Current descriptor control and fetch throttle control
signal mm2s_new_curdesc_wren_i : std_logic := '0';
signal mm2s_pending_update : std_logic := '0';
signal mm2s_pending_ptr_updt : std_logic := '0';
-- Descriptor Update Signals
signal mm2s_complete : std_logic := '0';
signal mm2s_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_xferd_bytes_int : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- Update Descriptor Pointer Holding Registers
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_64_reg0 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
-- Update Descriptor Status Holding Register
signal updt_desc_reg2 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
-- Pointer shift control
signal updt_shftenbl : std_logic := '0';
-- Update pointer stream
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Update status stream
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status control
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal packet_start : std_logic := '0';
signal packet_end : std_logic := '0';
signal mm2s_halt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cdc_d2 : std_logic := '0';
signal mm2s_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cdc_d2 : SIGNAL IS "true";
signal temp : std_logic := '0';
signal m_axis_mm2s_ftch_tlast_new : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
mm2s_desc_blength <= mm2s_desc_blength_i;
mm2s_desc_blength_v <= mm2s_desc_blength_v_i;
mm2s_desc_blength_s <= mm2s_desc_blength_s_i;
-- Drive fetch request done on tlast
desc_fetch_done_i <= m_axis_mm2s_ftch_tlast_new
and m_axis_mm2s_ftch_tvalid_new;
-- pass out of module
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_mm2s_ftch_tvalid_new
and ftch_tready
and desc_fetch_req
and not mm2s_pending_update;
-- Passed curdes write out to register module
mm2s_new_curdesc_wren <= desc_fetch_done_i; --mm2s_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch1_desc_available; --m_axis_mm2s_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_d1_cdc_tig <= '0';
-- -- mm2s_halt_d2 <= '0';
-- -- else
-- mm2s_halt_d1_cdc_tig <= mm2s_halt;
-- mm2s_halt_cdc_d2 <= mm2s_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_d2 <= mm2s_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_d2 <= mm2s_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
packet_start <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_SOF_BIT) = '1'
else '0';
packet_end <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_EOF_BIT) = '1'
else '0';
REG_PACKET_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or packet_end = '1')then
packet_in_progress <= '0';
elsif(packet_start = '1')then
packet_in_progress <= '1';
end if;
end if;
end process REG_PACKET_PROGRESS;
-- Status/Control stream enabled therefore APP fields are included
GEN_FTCHIF_WITH_APP : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
-- Control Stream Ethernet TAG
constant ETHERNET_CNTRL_TAG : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH - 1 downto 0)
:= X"A000_0000";
begin
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); -- downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65);
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 5 are reserved and thus don't care
-- CR 583779, need to pass on tuser and cache information
mm2s_desc_info <= (others => '0'); --desc_reg4; -- this coincides with desc_fetch_done
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= desc_reg8;
mm2s_desc_app1 <= desc_reg9;
mm2s_desc_app2 <= desc_reg10;
mm2s_desc_app3 <= desc_reg11;
mm2s_desc_app4 <= desc_reg12;
-- Drive ready if descriptor fetch request is being made
-- If not redirecting app fields then drive ready based on sm request
-- If redirecting app fields then drive ready based on room in cntrl strm fifo
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
redirect_app <= '0';
cntrlstrm_fifo_din <= (others => '0');
cntrlstrm_fifo_wren <= '0';
end generate GEN_FTCHIF_WITH_APP;
-- Status/Control stream diabled therefore APP fields are NOT included
GEN_FTCHIF_WITHOUT_APP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7(DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
ADDR1_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR1_64BIT;
ADDR1_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR1_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 4 and desc 5 are reserved and thus don't care
-- CR 583779, need to send the user and xchache info
mm2s_desc_info <= (others => '0'); --desc_reg4;
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_mm2s_ftch_tdata_mcdma_new (31 downto 0); --63 downto 32);
desc_reg5 <= m_axis_mm2s_ftch_tdata_mcdma_new (63 downto 32);
ADDR2_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR2_64BIT;
ADDR2_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR2_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- As per new MCDMA descriptor
mm2s_desc_info <= desc_reg4; -- (31 downto 24) & desc_reg7 (23 downto 0);
mm2s_desc_blength_s_i <= "0000000" & desc_reg5(15 downto 0);
mm2s_desc_blength_v_i <= "0000000000" & desc_reg5(31 downto 19);
mm2s_desc_blength_i <= "0000000" & desc_reg6(15 downto 0);
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= '0' ; --desc_reg7(DESC_STS_CMPLTD_BIT); -- we are not considering the completed bit
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_MCDMA;
-- Drive ready if descriptor fetch request is being made
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
end generate GEN_FTCHIF_WITHOUT_APP;
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_msb & mm2s_desc_baddr_lsb;
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_msb & mm2s_desc_curdesc_lsb;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_lsb;
end generate GEN_NEW_32BIT_CURDESC;
mm2s_new_curdesc_wren_i <= desc_fetch_done_i;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= mm2s_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
UPDT_ADDR_64BIT : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
begin
UPDT_DESC_WRD0_1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= mm2s_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD0_1;
end generate UPDT_ADDR_64BIT;
-----------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg1 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg1 <= DESC_LAST
& mm2s_desc_curdesc_msb;
-- Shift data out on shift enable
elsif(updt_shftenbl = '1')then
updt_desc_reg1 <= (others => '0');
end if;
end if;
end process UPDT_DESC_WRD1;
-- Shift in data from SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_mm2s_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1'
and s_axis_mm2s_updtptr_tready = '1'
else '0';
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
--*****************************************************************************
--** Status Update Logic
--*****************************************************************************
mm2s_complete <= '1'; -- Fixed at '1'
---------------------------------------------------------------------------
-- Descriptor queuing turned on in sg engine therefore need to instantiate
-- fifo to hold fetch buffer lengths. Also need to throttle fetches
-- if pointer has not been updated yet or length fifo is full
---------------------------------------------------------------------------
GEN_UPDT_FOR_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic; -- xfer'ed bytes fifo reset
signal xb_fifo_full : std_logic; -- xfer'ed bytes fifo full
begin
-----------------------------------------------------------------------
-- Need to flag a pending pointer update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
mm2s_pending_ptr_updt <= '0';
elsif (desc_fetch_done_i = '1') then --(mm2s_new_curdesc_wren_i = '1')then
mm2s_pending_ptr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pointer pending update or xferred bytes fifo full
mm2s_pending_update <= mm2s_pending_ptr_updt or xb_fifo_full;
updt_pending <= mm2s_pending_update;
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
mm2s_xferd_bytes <= (others => '0');
xb_fifo_full <= '0';
end generate GEN_MICRO_DMA;
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => desc_fetch_done_i, --mm2s_new_curdesc_wren_i ,
Data_In => mm2s_desc_blength_i ,
FIFO_Read => sts_received_re ,
Data_Out => mm2s_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
end generate GEN_NO_MICRO_DMA;
xb_fifo_reset <= not m_axi_sg_aresetn;
-- clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
mm2s_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= mm2s_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= mm2s_sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_QUEUE;
---------------------------------------------------------------------------
-- If no queue in sg engine then do not need to instantiate a
-- fifo to hold buffer lengths. Also do not need to hold off
-- fetch based on if status has been updated or not because
-- descriptors are only processed one at a time
---------------------------------------------------------------------------
GEN_UPDT_FOR_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
mm2s_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
mm2s_pending_update <= '0'; -- Not needed for the No Queue configuration
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_xferd_bytes <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
mm2s_xferd_bytes <= mm2s_desc_blength_i;
end if;
end if;
end process REG_XFERRED_BYTES;
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= mm2s_done or mm2s_interr or mm2s_decerr or mm2s_slverr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_NO_QUEUE;
-----------------------------------------------------------------------
-- Receive Status SG Update Logic
-----------------------------------------------------------------------
-- clear flag when updating status and see a tlast and target
-- (i.e. sg engine) is ready
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tlast = '1'
and updtsts_tvalid = '1'
and s_axis_mm2s_updtsts_tready = '1'
else '0';
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done
-- or datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- -- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg2 <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_reg2 <= DESC_LAST
& mm2s_tag(DATAMOVER_STS_TAGLSB_BIT) -- Desc_IOC
& mm2s_complete
& mm2s_decerr
& mm2s_slverr
& mm2s_interr
& RESERVED_STS
& mm2s_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
updtsts_tdata <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- MSB asserts last on last word of update stream
updtsts_tlast <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive tvalid
updtsts_tvalid <= updt_sts;
-- Drive update done to mm2s sm for the no queue case to indicate
-- readyd to fetch next descriptor
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
-- Update Pointer Stream
s_axis_mm2s_updtptr_tvalid <= updtptr_tvalid;
s_axis_mm2s_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_mm2s_updtptr_tdata <= updtptr_tdata ;
-- Update Status Stream
s_axis_mm2s_updtsts_tvalid <= updtsts_tvalid;
s_axis_mm2s_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
s_axis_mm2s_updtsts_tdata <= updtsts_tdata ;
-----------------------------------------------------------------------
end implementation;
|
bsd-3-clause
|
c30694fb1e2db5262c6e16d4e2c9fedb
| 0.468141 | 4.027409 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Uofk.vhd
| 1 | 2,294 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Uofk is
port (
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactofk : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
clock : in std_logic;
Uofk : out std_logic_vector(31 downto 0)
);
end k_ukf_Uofk;
architecture struct of k_ukf_Uofk is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_exp IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2,Z3,Z4,Z5,Z6 : std_logic_vector(31 downto 0);
signal Z : std_logic_vector(31 downto 0) := "00111111100000000000000000000000";
begin
M1 : k_ukf_sub port map
( clock => clock,
dataa => D,
datab => Z,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => B,
datab => Z1,
result => Z2);
M3 : k_ukf_exp port map
( clock => clock,
data => Z2,
result => Z3);
M4 : k_ukf_mult port map
( clock => clock,
dataa => D,
datab => Z3,
result => Z4);
M5 : k_ukf_mult port map
( clock => clock,
dataa => Isc,
datab => Vactofk,
result => Z5);
M6 : k_ukf_mult port map
( clock => clock,
dataa => Z5,
datab => Z4,
result => Z6);
M7 : k_ukf_add port map
( clock => clock,
dataa => I,
datab => Z6,
result => Uofk);
end struct;
|
gpl-2.0
|
c2a438c65cd5893f44e7319f706d0427
| 0.560593 | 2.907478 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/rgb.vhd
| 1 | 7,469 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name: RGB filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter allows the edit of the RGB values of the pixel through
-- through user registers
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin RGB Control architecture
architecture Behavioral of Video_Box is
--Create Red, Blue, Green signals that contain the actual Red,
--Blue, and Green signals
signal red, blue, green : std_logic_vector(7 downto 0);
--Create the register controlled Red, Green, and Blue signals
signal lred, lblue, lgreen : std_logic_vector(7 downto 0);
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--the user can edit the rgb values here
-- Get the original Red, Green, and Blue signals
red <= RGB_IN_reg(23 downto 16);
green <= RGB_IN_reg(15 downto 8);
blue <= RGB_IN_reg(7 downto 0);
-- Set the Red value to the register0 value if it is less than the original red value
-- Otherwise, keep at the original red value
lred <= slv_reg0(7 downto 0) when slv_reg0(7 downto 0) < red else red;
-- Set the Green value to the register0 value if it is less than the original green value
-- Otherwise, keep at the original green value
lgreen <= slv_reg1(7 downto 0) when slv_reg1(7 downto 0) < green else green;
-- Set the Blue value to the register0 value if it is less than the original blue value
-- Otherwise, keep at the original blue value
lblue <= slv_reg2(7 downto 0) when slv_reg2(7 downto 0) < blue else blue;
-- Concatenate the new RED, Green, Blue values and route them out
USER_LOGIC <= lred&lgreen&lblue;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
-- Route the registers through
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End RGB Control architecture
|
bsd-3-clause
|
996b624a7efae2f97ed5de399807bd99
| 0.628598 | 3.174246 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/cross_clk_sync_fifo_1.vhd
| 2 | 91,337 |
-------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity cross_clk_sync_fifo_1 is
generic (
C_FAMILY : string;
Async_Clk : integer;
C_FIFO_DEPTH : integer;
C_DATA_WIDTH : integer;
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_S_AXI_DATA_WIDTH : integer;
C_NUM_TRANSFER_BITS : integer;
--C_AXI_SPI_CLK_EQ_DIFF : integer;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
Rst_cdc_to_spi : in std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi : in std_logic;
SPISR_0_CMD_Error_cdc_to_axi : out std_logic;
----------------------------------------
spisel_d1_reg_cdc_from_spi : in std_logic;
spisel_d1_reg_cdc_to_axi : out std_logic;
----------------------------------------
spisel_pulse_cdc_from_spi : in std_logic;
spisel_pulse_cdc_to_axi : out std_logic;
----------------------------
Mst_N_Slv_mode_cdc_from_spi : in std_logic;
Mst_N_Slv_mode_cdc_to_axi : out std_logic;
----------------------------
slave_MODF_strobe_cdc_from_spi : in std_logic;
slave_MODF_strobe_cdc_to_axi : out std_logic;
----------------------------
modf_strobe_cdc_from_spi : in std_logic;
modf_strobe_cdc_to_axi : out std_logic;
----------------------------
Rx_FIFO_Full_cdc_from_axi : in std_logic;
Rx_FIFO_Full_cdc_to_spi : out std_logic;
----------------------------
reset_RcFIFO_ptr_cdc_from_axi : in std_logic;
reset_RcFIFO_ptr_cdc_to_spi : out std_logic;
----------------------------
Rx_FIFO_Empty_cdc_from_axi : in std_logic;
Rx_FIFO_Empty_cdc_to_spi : out std_logic;
----------------------------
Tx_FIFO_Empty_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_cdc_to_axi : out std_logic;
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_SPISR_cdc_to_axi : out std_logic;
----------------------------
Tx_FIFO_Full_cdc_from_axi : in std_logic;
Tx_FIFO_Full_cdc_to_spi : out std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi : out std_logic;
----------------------------
dtr_underrun_cdc_from_spi : in std_logic;
dtr_underrun_cdc_to_axi : out std_logic;
----------------------------
SPICR_0_LOOP_cdc_from_axi : in std_logic;
SPICR_0_LOOP_cdc_to_spi : out std_logic;
----------------------------
SPICR_1_SPE_cdc_from_axi : in std_logic;
SPICR_1_SPE_cdc_to_spi : out std_logic;
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi : in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi : out std_logic;
----------------------------
SPICR_3_CPOL_cdc_from_axi : in std_logic;
SPICR_3_CPOL_cdc_to_spi : out std_logic;
----------------------------
SPICR_4_CPHA_cdc_from_axi : in std_logic;
SPICR_4_CPHA_cdc_to_spi : out std_logic;
----------------------------
SPICR_5_TXFIFO_cdc_from_axi : in std_logic;
SPICR_5_TXFIFO_cdc_to_spi : out std_logic;
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi: in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi : out std_logic;
----------------------------
SPICR_7_SS_cdc_from_axi : in std_logic;
SPICR_7_SS_cdc_to_spi : out std_logic;
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi: in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi : out std_logic;
----------------------------
SPICR_9_LSB_cdc_from_axi : in std_logic;
SPICR_9_LSB_cdc_to_spi : out std_logic;
----------------------------
SPICR_bits_7_8_cdc_from_axi : in std_logic_vector(1 downto 0); -- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi : out std_logic_vector(1 downto 0);
----------------------------
SR_3_modf_cdc_from_axi : in std_logic;
SR_3_modf_cdc_to_spi : out std_logic;
----------------------------
SPISSR_cdc_from_axi : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SPISSR_cdc_to_spi : out std_logic_vector(0 to (C_NUM_SS_BITS-1));
----------------------------
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
drr_Overrun_int_cdc_from_spi : in std_logic;
drr_Overrun_int_cdc_to_axi : out std_logic
);
end entity cross_clk_sync_fifo_1;
-------------------------------------------------------------------------------
architecture imp of cross_clk_sync_fifo_1 is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
signal SPISR_0_CMD_Error_cdc_from_spi_d1: std_logic;
signal SPISR_0_CMD_Error_cdc_from_spi_d2: std_logic;
signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d1 : std_logic;
signal spisel_pulse_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d3 : std_logic;-- 2/21/2012
signal spisel_pulse_cdc_from_spi_d4 : std_logic;
signal Mst_N_Slv_mode_cdc_from_spi_d1 : std_logic;
signal Mst_N_Slv_mode_cdc_from_spi_d2 : std_logic;
signal slave_MODF_strobe_cdc_from_spi_d1: std_logic;
signal slave_MODF_strobe_cdc_from_spi_d2: std_logic;
signal slave_MODF_strobe_cdc_from_spi_d3: std_logic; -- 2/21/2012
signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
signal modf_strobe_cdc_from_spi_d1 : std_logic;
signal modf_strobe_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d3 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
signal Rx_FIFO_Full_cdc_from_axi_d1 : std_logic;
signal Rx_FIFO_Full_cdc_from_axi_d2 : std_logic;
signal reset_RcFIFO_ptr_cdc_from_axi_d1 : std_logic;
signal reset_RcFIFO_ptr_cdc_from_axi_d2 : std_logic;
signal Rx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
signal Rx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic_vector(2 downto 0);
signal Tx_FIFO_Full_cdc_from_axi_d1 : std_logic;
signal Tx_FIFO_Full_cdc_from_axi_d2 : std_logic;
signal modf_strobe_cdc_to_axi_d1 : std_logic;
signal modf_strobe_cdc_to_axi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_cdc_from_spi_d1 : std_logic;
signal spiXfer_done_cdc_from_spi_d2 : std_logic;
signal dtr_underrun_cdc_from_spi_d1 : std_logic;
signal dtr_underrun_cdc_from_spi_d2 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
signal SR_3_modf_cdc_from_axi_d1 : std_logic;
signal SR_3_modf_cdc_from_axi_d2 : std_logic;
signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal rx_fifo_full_int, RST_RX_FF : std_logic;
signal rx_fifo_full_int_2 : std_logic;
signal RST_spiXfer_done_FF : std_logic;
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_cdc_from_spi_int : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
signal reset_RX_FIFO_Rst_pulse : std_logic;
signal SPICR_RX_FIFO_Rst_en_d1 : std_logic;
signal SPICR_RX_FIFO_Rst_en : std_logic;
signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
signal SPISSR_cdc_from_axi_d1_and_reduce : std_logic;
signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
signal SPICR_RX_FIFO_Rst_en_d2 : std_logic;
-- signal SPISR_0_CMD_Error_cdc_from_spi_d1: std_logic;
-- signal SPISR_0_CMD_Error_cdc_from_spi_d2: std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d1 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d3 : std_logic;-- 2/21/2012
-- signal Mst_N_Slv_mode_cdc_from_spi_d1 : std_logic;
-- signal Mst_N_Slv_mode_cdc_from_spi_d2 : std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d1: std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d2: std_logic;
-- signal slave_MODF_strobe_cdc_from_spi_d3: std_logic; -- 2/21/2012
-- signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d1 : std_logic;
-- signal modf_strobe_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d3 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
-- signal Rx_FIFO_Full_cdc_from_axi_d1 : std_logic;
-- signal Rx_FIFO_Full_cdc_from_axi_d2 : std_logic;
-- signal reset_RcFIFO_ptr_cdc_from_axi_d1 : std_logic;
-- signal reset_RcFIFO_ptr_cdc_from_axi_d2 : std_logic;
-- signal Rx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
-- signal Rx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic;
-- -- signal Tx_FIFO_Empty_cdc_from_spi_d2 : std_logic_vector(2 downto 0);
-- signal Tx_FIFO_Full_cdc_from_axi_d1 : std_logic;
-- signal Tx_FIFO_Full_cdc_from_axi_d2 : std_logic;
-- signal modf_strobe_cdc_to_axi_d1 : std_logic;
-- signal modf_strobe_cdc_to_axi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d1 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d2 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d1 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d2 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
-- signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
-- signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
-- signal SR_3_modf_cdc_from_axi_d1 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal rx_fifo_full_int, RST_RX_FF : std_logic;
-- signal rx_fifo_full_int_2 : std_logic;
-- signal RST_spiXfer_done_FF : std_logic;
-- signal spiXfer_done_d1 : std_logic;
-- signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
-- signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_int : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
-- signal reset_RX_FIFO_Rst_pulse : std_logic;
-- signal SPICR_RX_FIFO_Rst_en_d1 : std_logic;
-- signal SPICR_RX_FIFO_Rst_en : std_logic;
-- signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1_and_reduce : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
--------------------------
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of CMD_ERR_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPISEL_D1_REG_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPISEL_PULSE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of MST_N_SLV_MODE_S2AX_1_CDC : label is "TRUE";
-- -- attribute ASYNC_REG of SLAVE_MODF_STROBE_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of RX_FIFO_EMPTY_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_EMPTY_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_FULL_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPIXFER_DONE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of RX_FIFO_RST_AX2S_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of RX_FIFO_FULL_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of SYNC_SPIXFER_DONE_S2AX_1_CDC: label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of DTR_UNDERRUN_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
-- attribute ASYNC_REG of SPICR_0_LOOP_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_1_SPE_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_2_MST_N_SLV_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_3_CPOL_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_4_CPHA_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_5_TXFIFO_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_6_RXFIFO_RST_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_7_SS_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_8_TR_INHIBIT_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SPICR_9_LSB_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SR_3_MODF_AX2S_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of SLV_MODF_STRB_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of MODF_STROBE_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of TX_EMPT_4_SPISR_S2AX_1_CDC : label is "TRUE";
-- attribute ASYNC_REG of DRR_OVERRUN_S2AX_1_CDC : label is "TRUE"; -- 3/25/2013
attribute KEEP : string;
attribute KEEP of SPISR_0_CMD_Error_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_d1_reg_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_pulse_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of spisel_pulse_cdc_from_spi_d1: signal is "TRUE";
attribute KEEP of Mst_N_Slv_mode_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of Slave_MODF_strobe_cdc_from_spi_d2: signal is "TRUE";
attribute KEEP of Slave_MODF_strobe_cdc_from_spi_d1: signal is "TRUE";
attribute KEEP of modf_strobe_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of modf_strobe_cdc_from_spi_d1 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
-----
SPISSR_cdc_from_axi_d1_and_reduce <= and_reduce(SPISSR_cdc_from_axi_d2);
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
--==============================================================================
CMD_ERR_S2AX_1_CDC: component FDR
generic map(INIT => '0' -- added on 16th Feb
)port map (
Q => SPISR_0_CMD_Error_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => SPISR_0_CMD_Error_cdc_from_spi,
R => Soft_Reset_op
);
CMD_ERR_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPISR_0_CMD_Error_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => SPISR_0_CMD_Error_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISR_0_CMD_Error_cdc_to_axi <= SPISR_0_CMD_Error_cdc_from_spi_d2;
-----------------------------------------------------------
--==============================================================================
SPISEL_D1_REG_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_d1_reg_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_D1_REG_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_d1_reg_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi_d1,
R => Soft_Reset_op
);
spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_from_spi_d2;
-------------------------------------------------
--==============================================================================
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= --((not SPISSR_cdc_from_axi_d1_and_reduce) and
spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2, -- spisel_pulse_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d3 xor spisel_pulse_cdc_from_spi_d2; -- 2/21/2012
-----------------------------------------------
--==============================================================================
MST_N_SLV_MODE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Mst_N_Slv_mode_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Mst_N_Slv_mode_cdc_from_spi,
R => Soft_Reset_op
);
MST_N_SLV_MODE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Mst_N_Slv_mode_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Mst_N_Slv_mode_cdc_from_spi_d1,
R => Soft_Reset_op
);
Mst_N_Slv_mode_cdc_to_axi <= Mst_N_Slv_mode_cdc_from_spi_d2;
---------------------------------------------------
--==============================================================================
SLAVE_MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
SLV_MODF_STRB_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SLV_MODF_STRB_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
SLV_MODF_STRB_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor Slave_MODF_strobe_cdc_from_spi_d1; --spiXfer_done_cdc_from_spi_d2;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d3 xor Slave_MODF_strobe_cdc_from_spi_d2;-- 2/21/2012
--==============================================================================
MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1;
MODF_STROBE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
MODF_STROBE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
MODF_STROBE_S2AX_3: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
-- modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d1; --spiXfer_done_cdc_from_spi_d2;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d3 xor modf_strobe_cdc_from_spi_d2; -- 2/21/2012
-----------------------------------------------
--==============================================================================
RX_FIFO_EMPTY_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Empty_cdc_from_axi_d1,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Rx_FIFO_Empty_cdc_from_axi,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
RX_FIFO_EMPTY_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Empty_cdc_from_axi_d2,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Rx_FIFO_Empty_cdc_from_axi_d1,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
Rx_FIFO_Empty_cdc_to_spi <= Rx_FIFO_Empty_cdc_from_axi_d2;
-------------------------------------------------
--==============================================================================
TX_FIFO_EMPTY_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Empty_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_cdc_from_spi,
R => Soft_Reset_op
);
TX_FIFO_EMPTY_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Empty_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_cdc_from_spi_d1,
R => Soft_Reset_op
);
Tx_FIFO_Empty_cdc_to_axi <= Tx_FIFO_Empty_cdc_from_spi_d2;
-------------------------------------------------
--==============================================================================
TX_EMPT_4_SPISR_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_SPISR_cdc_from_spi,
R => Soft_Reset_op
);
TX_EMPT_4_SPISR_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
R => Soft_Reset_op
);
Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d2;
--==============================================================================
TX_FIFO_FULL_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Full_cdc_from_axi_d1,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Tx_FIFO_Full_cdc_from_axi,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
TX_FIFO_FULL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => Tx_FIFO_Full_cdc_from_axi_d2,
C => EXT_SPI_CLK, -- Bus2IP_Clk,
D => Tx_FIFO_Full_cdc_from_axi_d1,
R => Rst_cdc_to_spi -- Soft_Reset_op
);
Tx_FIFO_Full_cdc_to_spi <= Tx_FIFO_Full_cdc_from_axi_d2;
-----------------------------------------------
--==============================================================================
SPIXFER_DONE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi,
R => Soft_Reset_op
);
SPIXFER_DONE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_d1,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi <= spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
SPICR_RX_FIFO_Rst_en <= reset_RcFIFO_ptr_cdc_from_axi xor SPICR_RX_FIFO_Rst_en_d1;
SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P:process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1') then -- or reset_RX_FIFO_Rst_pulse = '1')then
SPICR_RX_FIFO_Rst_en_d1 <= '0';
else
SPICR_RX_FIFO_Rst_en_d1 <= SPICR_RX_FIFO_Rst_en;
end if;
end if;
end process SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P;
-------------------------------------------------
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
RX_FIFO_RST_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_RX_FIFO_Rst_en_d1,
R => Rst_cdc_to_spi
);
RX_FIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d1 xor
reset_RcFIFO_ptr_cdc_from_axi_d2;
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
-----------------------------------------------------------
------------------------------------------
RX_FIFO_FULL_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Full_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => Rx_FIFO_Full_cdc_from_axi,
R => Rst_cdc_to_spi
);
RX_FIFO_FULL_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => Rx_FIFO_Full_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => Rx_FIFO_Full_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
Rx_FIFO_Full_cdc_to_spi <= Rx_FIFO_Full_cdc_from_axi_d2;
------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
SYNC_SPIXFER_DONE_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => Bus2IP_Clk,
D => spiXfer_done_d1,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_S2AX_3: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => Bus2IP_Clk,
D => spiXfer_done_d2,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------
DTR_UNDERRUN_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi,
R => Soft_Reset_op
);
DTR_UNDERRUN_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi_d1,
R => Soft_Reset_op
);
dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_from_spi_d2;
-------------------------------------------------
SPICR_0_LOOP_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_0_LOOP_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_from_axi_d2;
-----------------------------------------------
SPICR_1_SPE_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_1_SPE_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_from_axi_d2;
---------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_2_MST_N_SLV_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_from_axi_d2;
---------------------------------------------------------
SPICR_3_CPOL_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_3_CPOL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_from_axi_d2;
-----------------------------------------------
SPICR_4_CPHA_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_4_CPHA_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_from_axi_d2;
-----------------------------------------------
SPICR_5_TXFIFO_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_5_TXFIFO_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_from_axi_d2;
---------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_6_RXFIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_7_SS_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_7_SS_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_from_axi_d2;
-------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_8_TR_INHIBIT_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_9_LSB_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi,
R => Rst_cdc_to_spi
);
SPICR_9_LSB_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_from_axi_d2;
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi(i),
R => Rst_cdc_to_spi
);
SPICR_BITS_7_8_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi_d1(i),
R => Rst_cdc_to_spi
);
end generate SPICR_BITS_7_8_SYNC_GEN;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
---------------------------------------------------
SR_3_MODF_AX2S_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi,
R => Rst_cdc_to_spi
);
SR_3_MODF_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_from_axi_d2;
-----------------------------------------
SPISSR_SYNC_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1_CDC : label is "TRUE";
-----
begin
-----
SPISSR_AX2S_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi(i),
R => Rst_cdc_to_spi
);
SPISSR_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi_d1(i),
R => Rst_cdc_to_spi
);
end generate SPISSR_SYNC_GEN;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_S2AX_1_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_S2AX_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
--drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d2 xor drr_Overrun_int_cdc_from_spi_d1;
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d3 xor drr_Overrun_int_cdc_from_spi_d2; -- 2/21/2012
end generate LOGIC_GENERATION_FDR ;
LOGIC_GENERATION_CDC : if Async_Clk = 1 generate
--==============================================================================
CMD_ERR_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPISR_0_CMD_Error_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => SPISR_0_CMD_Error_cdc_to_axi
);
--==============================================================================
SPISEL_D1_REG_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => spisel_d1_reg_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_d1_reg_cdc_to_axi
);
--==============================================================================
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= --((not SPISSR_cdc_from_axi_d1_and_reduce) and
spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_S2AX_1_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2, -- spisel_pulse_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_2: component FDR
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_3: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
SPISEL_PULSE_S2AX_4: component FDR -- 2/21/2012
generic map(INIT => '1'
)port map (
Q => spisel_pulse_cdc_from_spi_d4,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d3,
R => Soft_Reset_op
);
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d3 xor spisel_pulse_cdc_from_spi_d4;
--==============================================================================
MST_N_SLV_MODE_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Mst_N_Slv_mode_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Mst_N_Slv_mode_cdc_to_axi
);
--==============================================================================
SLAVE_MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
--Slave_MODF_strobe_cdc_from_spi_d1 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
--Slave_MODF_strobe_cdc_from_spi_d1 <= Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1_CDC;
SLV_MODF_STRB_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Slave_MODF_strobe_cdc_from_spi_int_2,--Slave_MODF_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Slave_MODF_strobe_cdc_from_spi_d2
);
SLAVE_MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
Slave_MODF_strobe_cdc_from_spi_d3 <= Slave_MODF_strobe_cdc_from_spi_d2 ;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d3 xor Slave_MODF_strobe_cdc_from_spi_d2;
--==============================================================================
MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
-- modf_strobe_cdc_from_spi_d1 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
-- modf_strobe_cdc_from_spi_d1 <= modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1_CDC;
MODF_STROBE_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => modf_strobe_cdc_from_spi_int_2,--modf_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => modf_strobe_cdc_from_spi_d2
);
MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
modf_strobe_cdc_from_spi_d3 <= modf_strobe_cdc_from_spi_d2;
end if;
end process MODF_STROBE_STRETCH_1;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d3 xor modf_strobe_cdc_from_spi_d2;
--==============================================================================
RX_FIFO_EMPTY_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => Rx_FIFO_Empty_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => Rx_FIFO_Empty_cdc_to_spi
);
--==============================================================================
TX_FIFO_EMPTY_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_cdc_to_axi
);
--==============================================================================
TX_EMPT_4_SPISR_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_SPISR_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_SPISR_cdc_to_axi
);
--==============================================================================
TX_FIFO_FULL_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Full_cdc_from_axi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Full_cdc_to_spi
);
--==============================================================================
SPIXFER_DONE_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => spiXfer_done_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_cdc_to_axi
);
--==============================================================================
RX_FIFO_FULL_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Rx_FIFO_Full_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => Rx_FIFO_Full_cdc_to_spi
);
--==============================================================================
SPI_XFER_DONE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
-- spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
-- spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
SYNC_SPIXFER_DONE_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
spiXfer_done_d3 <= spiXfer_done_d2;
end if;
end process SPI_XFER_DONE_STRETCH_1;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
--==============================================================================
DTR_UNDERRUN_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => dtr_underrun_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => dtr_underrun_cdc_to_axi
);
--==============================================================================
SPICR_0_LOOP_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => SPICR_0_LOOP_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_0_LOOP_cdc_to_spi
);
--==============================================================================
SPICR_1_SPE_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => SPICR_1_SPE_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_1_SPE_cdc_to_spi
);
--==============================================================================
SPICR_2_MST_N_SLV_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_2_MST_N_SLV_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_2_MST_N_SLV_cdc_to_spi
);
--==============================================================================
SPICR_3_CPOL_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_3_CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_3_CPOL_cdc_to_spi
);
--==============================================================================
SPICR_4_CPHA_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_4_CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_4_CPHA_cdc_to_spi
);
--==============================================================================
SPICR_5_TXFIFO_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_5_TXFIFO_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_5_TXFIFO_cdc_to_spi
);
--==============================================================================
SPICR_6_RXFIFO_RST_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_6_RXFIFO_RST_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_6_RXFIFO_RST_cdc_to_spi
);
--==============================================================================
SPICR_7_SS_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_7_SS_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_7_SS_cdc_to_spi
);
--==============================================================================
SPICR_8_TR_INHIBIT_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_8_TR_INHIBIT_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_8_TR_INHIBIT_cdc_to_spi
);
--==============================================================================
SPICR_9_LSB_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_9_LSB_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_9_LSB_cdc_to_spi
);
--==============================================================================
SR_3_MODF_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SR_3_modf_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SR_3_modf_cdc_to_spi
);
--==============================================================================
SPISSR_SYNC_GEN_CDC: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1_CDC : label is "TRUE";
-----
begin
SPISSR_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_in => SPISSR_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi,
scndry_out => SPISSR_cdc_from_axi_d2(i)
);
end generate SPISSR_SYNC_GEN_CDC;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
DRR_OVERRUN_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
-- drr_Overrun_int_cdc_from_spi_d1 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
--drr_Overrun_int_cdc_from_spi_d1 <= drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1_CDC;
DRR_OVERRUN_S2AX_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_cdc_to_spi ,
prmry_in => drr_Overrun_int_cdc_from_spi_int_2,--drr_Overrun_int_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => drr_Overrun_int_cdc_from_spi_d2
);
DRR_OVERRUN_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
drr_Overrun_int_cdc_from_spi_d3 <= drr_Overrun_int_cdc_from_spi_d2;
end if;
end process DRR_OVERRUN_STRETCH_1;
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d3 xor drr_Overrun_int_cdc_from_spi_d2;
-------------------------------------------------------------
SPICR_RX_FIFO_Rst_en <= reset_RcFIFO_ptr_cdc_from_axi xor SPICR_RX_FIFO_Rst_en_d1;
SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P_CDC:process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1') then -- or reset_RX_FIFO_Rst_pulse = '1')then
SPICR_RX_FIFO_Rst_en_d1 <= '0';
else
SPICR_RX_FIFO_Rst_en_d1 <= SPICR_RX_FIFO_Rst_en;
end if;
end if;
end process SPICR_RX_FIFO_RST_REG_SPI_DOMAIN_P_CDC;
-------------------------------------------------
RX_FIFO_RST_AX2S_1: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 1 --AXI to SPI as already 2 stages included
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_RX_FIFO_Rst_en_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_RX_FIFO_Rst_en_d2
);
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
RX_FIFO_RST_AX2S_1_CDC_1: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_RX_FIFO_Rst_en_d2,
R => Rst_cdc_to_spi
);
RX_FIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_cdc_to_spi
);
reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d1 xor
reset_RcFIFO_ptr_cdc_from_axi_d2;
--reset_RcFIFO_ptr_cdc_to_spi <= reset_RcFIFO_ptr_cdc_from_axi_d2;
----------------------------------------------------------------------------------
SPICR_BITS_7_8_SYNC_GEN_CDC: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_bits_7_8_cdc_from_axi(i) ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_cdc_to_spi ,
scndry_out => SPICR_bits_7_8_cdc_from_axi_d2(i)
);
end generate SPICR_BITS_7_8_SYNC_GEN_CDC;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
SPISR_0_CMD_Error_cdc_from_spi_d2 <= '0';
spisel_d1_reg_cdc_from_spi_d2 <= '0';
Mst_N_Slv_mode_cdc_from_spi_d2 <= '0';
slave_MODF_strobe_cdc_from_spi_d1 <= '0';
modf_strobe_cdc_from_spi_d1 <= '0';
end generate LOGIC_GENERATION_CDC ;
end architecture imp;
---------------------
|
bsd-3-clause
|
2718ffc10d283163aab5c830a10f0135
| 0.420487 | 3.759653 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd
| 1 | 24,644 |
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`protect end_protected
|
apache-2.0
|
24fde38b36045e1a2398d50c6c6f420b
| 0.942907 | 1.883954 | false | false | false | false |
Apollinaire/GameOfLife_FPGA
|
sources/Echantilloneur.vhd
| 1 | 930 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10.01.2017 10:50:44
-- Design Name:
-- Module Name: Echantilloneur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Echantilloneur is
Port ( S_E : in STD_LOGIC;
CLK : in STD_LOGIC;
Q_E : out STD_LOGIC :='0');
end Echantilloneur;
architecture Behavioral of Echantilloneur is
signal A : integer := 0;
begin
process(S_E, CLK)
begin
if CLK'event and CLK = '1' then
if A>100000 then
A <= 0;
Q_E <= S_E;
else
A <= A+1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
b19913482b6f22abd64e6fa8756a079b
| 0.496774 | 3.522727 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd
| 4 | 92,853 |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM FULL Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all ;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset ;
use axi_datamover_v5_1_9.axi_datamover_cmd_status ;
use axi_datamover_v5_1_9.axi_datamover_pcc ;
use axi_datamover_v5_1_9.axi_datamover_ibttcc ;
use axi_datamover_v5_1_9.axi_datamover_indet_btt ;
use axi_datamover_v5_1_9.axi_datamover_s2mm_realign ;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl ;
use axi_datamover_v5_1_9.axi_datamover_wrdata_cntl ;
use axi_datamover_v5_1_9.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_9.axi_datamover_skid2mm_buf ;
Use axi_datamover_v5_1_9.axi_datamover_skid_buf ;
Use axi_datamover_v5_1_9.axi_datamover_wr_sf ;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_full_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 1;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) General Purpose Store and Forward function
-- 0 = Omit GP Store and Forward
-- 1 = Include GP Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and Reset inputs ----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
-------------------------------------------------------------------
-- S2MM Primary Reset input ---------------------------------------
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- S2MM Halt request input control --------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------------
-- S2MM Error discrete output -------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------------
-- Optional Command and Status Clock and Reset -------------------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls ---------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_full_wrap;
architecture implementation of axi_datamover_s2mm_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
if (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_status_width
--
-- Function Description:
-- This function sets the width of the Status pipe depending on the
-- Store and Forward inclusion or ommision.
--
-------------------------------------------------------------------
function funct_set_status_width (store_forward_enabled : integer)
return integer is
Variable temp_status_bit_width : Integer := 8;
begin
If (store_forward_enabled = 1) Then
temp_status_bit_width := 32;
Else
temp_status_bit_width := 8;
End if;
Return (temp_status_bit_width);
end function funct_set_status_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_bits_needed
--
-- Function Description:
--
--
-------------------------------------------------------------------
function get_bits_needed (max_bytes : integer) return integer is
Variable fvar_temp_bit_width : Integer := 1;
begin
if (max_bytes <= 1) then
fvar_temp_bit_width := 1;
elsif (max_bytes <= 3) then
fvar_temp_bit_width := 2;
elsif (max_bytes <= 7) then
fvar_temp_bit_width := 3;
elsif (max_bytes <= 15) then
fvar_temp_bit_width := 4;
elsif (max_bytes <= 31) then
fvar_temp_bit_width := 5;
elsif (max_bytes <= 63) then
fvar_temp_bit_width := 6;
elsif (max_bytes <= 127) then
fvar_temp_bit_width := 7;
elsif (max_bytes <= 255) then
fvar_temp_bit_width := 8;
elsif (max_bytes <= 511) then
fvar_temp_bit_width := 9;
elsif (max_bytes <= 1023) then
fvar_temp_bit_width := 10;
elsif (max_bytes <= 2047) then
fvar_temp_bit_width := 11;
elsif (max_bytes <= 4095) then
fvar_temp_bit_width := 12;
elsif (max_bytes <= 8191) then
fvar_temp_bit_width := 13;
else -- 8k - 16K
fvar_temp_bit_width := 14;
end if;
Return (fvar_temp_bit_width);
end function get_bits_needed;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_need_realigner
--
-- Function Description:
-- Determines if the Realigner module needs to be included.
--
-------------------------------------------------------------------
function funct_need_realigner (indet_btt_enabled : integer;
dre_included : integer;
gp_sf_included : integer) return integer is
Variable temp_val : Integer := 0;
begin
If ((indet_btt_enabled = 1) or
(dre_included = 1) or
(gp_sf_included = 1)) Then
temp_val := 1;
else
temp_val := 0;
End if;
Return (temp_val);
end function funct_need_realigner;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others =>
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for S2MM
-- modules downstream from the upsizing Store and Forward. If
-- Store and forward is present, then the effective Stream width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Stream width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled > 0) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_bytes_per_dbeat
--
-- Function Description:
-- This function calculates the number of bytes transfered per
-- databeat on the MMap AXI4 Write Data Channel by the S2MM. The
-- value is based on input parameterization of included functions
-- in the S2MM block.
--
-------------------------------------------------------------------
function funct_get_bytes_per_dbeat (ibtt_enabled : integer ;
gpsf_enabled : integer ;
stream_dwidth : integer ;
mmap_dwidth : integer ) return integer is
Variable fvar_temp_bytes_per_xfer : Integer := 4;
begin
If (ibtt_enabled > 0 or
gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width
fvar_temp_bytes_per_xfer := mmap_dwidth/8;
Else -- transfers will be in stream data widths (may be narrow transfers on mmap)
fvar_temp_bytes_per_xfer := stream_dwidth/8;
End if;
Return (fvar_temp_bytes_per_xfer);
end function funct_get_bytes_per_dbeat;
-- Constant Declarations ----------------------------------------
Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH,
C_S2MM_SDATA_WIDTH,
SF_ENABLED);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant IS_NOT_MM2S : integer range 0 to 1 := 0;
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH;
Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32);
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED;
Constant BITS_PER_BYTE : integer := 8;
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1;
Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT;
Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ;
Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF ,
ENABLE_GP_SF ,
S2MM_SDATA_WIDTH ,
S2MM_MDATA_WIDTH);
Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE;
Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST);
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_STATUS_WIDTH : integer range 8 to 32 :=
funct_set_status_width(ENABLE_INDET_BTT_SF);
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED;
Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF ,
INCLUDE_S2MM_DRE ,
ENABLE_GP_SF);
-- Calculates the minimum needed depth of the GP Store and Forward FIFO
-- based on the S2MM pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE;
-- Assigns the depth of the optional GP Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH,
S2MM_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_dre2ibtt_tvalid : std_logic := '0';
signal sig_ibtt2dre_tready : std_logic := '0';
signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tlast : std_logic := '0';
signal sig_dre2ibtt_eop : std_logic := '0';
signal sig_dre2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2dre_cmd_valid : std_logic := '0';
signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2dre_drr : std_logic := '0';
signal sig_mstr2dre_eof : std_logic := '0';
signal sig_mstr2dre_cmd_cmplt : std_logic := '0';
signal sig_mstr2dre_calc_error : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal sig_dre2all_halted : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal skid2dre_wvalid : std_logic := '0';
signal dre2skid_wready : std_logic := '0';
signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2dre_wlast : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_ibtt2wdc_error : std_logic := '0';
signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal s2mm_awuser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug/Test Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADD_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen adds in the EOP status marker to the debug
-- vector data when Indet BTT Store and Forward is enabled.
--
------------------------------------------------------------
GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate
begin
sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker
end generate GEN_ADD_DEBUG_EOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen zeros the debug vector bit used for the EOP
-- status marker when Indet BTT Store and Forward is not
-- enabled.
--
------------------------------------------------------------
GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate
begin
sig_dbg_data_1(19) <= '0' ; -- EOP Marker
end generate GEN_NO_DEBUG_EOP;
---- End of Debug/Test Support --------------------------------
-- Assign the Address posting control outputs
s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ;
s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ;
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ;
s2mm_wr_len <= sig_s2mm_wr_len ;
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
s2mm_wstrb <= sig_skid2axi_wstrb ;
end generate GEN_S2MM_TKEEP_ENABLE2;
GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
s2mm_wstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE2;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters
s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_PCC
--
-- If Generate Description:
-- Include the normal Predictive Command Calculator function,
-- Store and Forward is not an included feature.
--
--
------------------------------------------------------------
GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_9.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_NOT_MM2S ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => open ,
mstr2data_dre_dest_align => open ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_PCC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_IBTTCC
--
-- If Generate Description:
-- Include the Indeterminate BTT Command Calculator function,
-- Store and Forward is enabled in the S2MM.
--
--
------------------------------------------------------------
GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_MSTR_SFCC
--
-- Description:
-- Instantiates the Store and Forward Command Calculator
-- Block.
--
------------------------------------------------------------
I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_9.axi_datamover_ibttcc
generic map (
C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_IBTTCC;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2dre_wvalid ,
m_ready => dre2skid_wready ,
m_data => skid2dre_wdata ,
m_strb => skid2dre_wstrb ,
m_last => skid2dre_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2dre_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= dre2skid_wready;
skid2dre_wdata <= s2mm_strm_wdata;
skid2dre_wstrb <= s2mm_strm_wstrb;
skid2dre_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_REALIGNER
--
-- If Generate Description:
-- Omit the S2MM Realignment Engine
--
--
------------------------------------------------------------
GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate
begin
-- Set to Always ready for DRE to PCC Command Interface
sig_dre2mstr_cmd_ready <= LOGIC_HIGH;
-- Without DRE and Scatter, the end of packet is the TLAST
--sig_dre2ibtt_eop <= skid2dre_wlast ;
sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version
-- Cant't detect undrrun/overrun here
sig_realign2wdc_eop_error <= '0';
ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_NO_REALIGN_SKID_BUF
--
-- Description:
-- Instance for a Skid Buffer which provides for
-- Fmax timing improvement between the Null Absorber and
-- the Write Data controller when the Realigner is not
-- present (no DRE and no Store and Forward case).
--
------------------------------------------------------------
I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Null Absorber Input)
s_valid => skid2dre_wvalid ,
s_ready => dre2skid_wready ,
s_data => skid2dre_wdata ,
s_strb => skid2dre_wstrb ,
s_last => skid2dre_wlast ,
-- Master Side (Stream Data Output to WData Cntlr)
m_valid => sig_dre2ibtt_tvalid ,
m_ready => sig_ibtt2dre_tready ,
m_data => sig_dre2ibtt_tdata ,
m_strb => sig_dre2ibtt_tstrb ,
m_last => sig_dre2ibtt_tlast
);
end generate ENABLE_NOREALIGNER_SKID;
DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate
begin
sig_dre2ibtt_tvalid <= skid2dre_wvalid;
dre2skid_wready <= sig_ibtt2dre_tready;
sig_dre2ibtt_tdata <= skid2dre_wdata;
sig_dre2ibtt_tstrb <= skid2dre_wstrb;
sig_dre2ibtt_tlast <= skid2dre_wlast;
end generate DISABLE_NOREALIGNER_SKID;
end generate GEN_NO_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_REALIGNER
--
-- If Generate Description:
-- Include the S2MM realigner Module. It hosts the S2MM DRE
-- and the Scatter Block.
--
-- Note that the General Purpose Store and Forward Module
-- needs the Scatter function to detect input overrun and
-- underrun events on the AXI Stream input. Thus the Realigner
-- is included whenever the GP Store and Forward is enabled.
--
------------------------------------------------------------
GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_REALIGNER
--
-- Description:
-- Instance for the S2MM Data Realignment Module.
--
------------------------------------------------------------
I_S2MM_REALIGNER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_realign
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_INCLUDE_DRE => INCLUDE_S2MM_DRE ,
C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER ,
C_BTT_USED => S2MM_BTT_USED ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
-- Write Data Controller or Store and Forward I/O -------
wdc2dre_wready => sig_ibtt2dre_tready ,
dre2wdc_wvalid => sig_dre2ibtt_tvalid ,
dre2wdc_wdata => sig_dre2ibtt_tdata ,
dre2wdc_wstrb => sig_dre2ibtt_tstrb ,
dre2wdc_wlast => sig_dre2ibtt_tlast ,
dre2wdc_eop => sig_dre2ibtt_eop ,
-- Starting offset output -------------------------------
dre2sf_strt_offset => sig_sf_strt_addr_offset ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_wready => dre2skid_wready ,
s2mm_strm_wvalid => skid2dre_wvalid ,
s2mm_strm_wdata => skid2dre_wdata ,
s2mm_strm_wstrb => skid2dre_wstrb ,
s2mm_strm_wlast => skid2dre_wlast ,
-- Command Calculator Interface --------------------------
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ,
-- Premature TLAST assertion error flag
dre2all_tlast_error => sig_realign2wdc_eop_error ,
-- DRE Halted Status
dre2all_halted => sig_dre2all_halted
);
end generate GEN_INCLUDE_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT_SF
--
-- If Generate Description:
-- Include the Indeterminate BTT Logic with specialized
-- Store and Forward function, This also requires the
-- Scatter Engine in the Realigner module.
--
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate
begin
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
------------------------------------------------------------
-- Instance: I_INDET_BTT
--
-- Description:
-- Instance for the Indeterminate BTT with Store and Forward
-- module.
--
------------------------------------------------------------
I_INDET_BTT : entity axi_datamover_v5_1_9.axi_datamover_indet_btt
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_DRE => INCLUDE_S2MM_DRE ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
ibtt2wdc_eop => sig_ibtt2wdc_eop ,
ibtt2wdc_tdata => sig_ibtt2wdc_tdata ,
ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb ,
ibtt2wdc_tlast => sig_ibtt2wdc_tlast ,
ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid ,
wdc2ibtt_tready => sig_wdc2ibtt_tready ,
dre2ibtt_tvalid => sig_dre2ibtt_tvalid ,
ibtt2dre_tready => sig_ibtt2dre_tready ,
dre2ibtt_tdata => sig_dre2ibtt_tdata ,
dre2ibtt_tstrb => sig_dre2ibtt_tstrb ,
dre2ibtt_tlast => sig_dre2ibtt_tlast ,
dre2ibtt_eop => sig_dre2ibtt_eop ,
dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes
);
end generate GEN_ENABLE_INDET_BTT_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_SF
--
-- If Generate Description:
-- Bypasses any store and Forward functions.
--
--
------------------------------------------------------------
GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 0) generate
begin
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
-- Housekeep unused signal in this case
sig_ok_to_post_wr_addr <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
-- Just pass DRE signals through
sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ;
sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ;
sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ;
sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ;
sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ;
sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ;
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
end generate GEN_NO_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_GP_SF
--
-- If Generate Description:
-- Include the General Purpose Store and Forward module.
-- This If Generate can only be enabled when
-- Indeterminate BTT mode is not enabled. The General Purpose
-- Store and Forward is instantiated in place of the Indet
-- BTT Store and Forward.
--
------------------------------------------------------------
GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 1) generate
begin
-- Merge the external address posting control with the
-- SF address posting control.
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and
sig_ok_to_post_wr_addr ;
-- Zero these out since Indet BTT is not enabled, they
-- are only used by the WDC in that mode
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
sig_ibtt2wdc_eop <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
------------------------------------------------------------
-- Instance: I_S2MM_GP_SF
--
-- Description:
-- Instance for the S2MM (Write) General Purpose Store and
-- Forward Module. This module can only be enabled when
-- Indeterminate BTT mode is not enabled. It is connected
-- in place of the IBTT Module when GP SF is enabled.
--
------------------------------------------------------------
I_S2MM_GP_SF : entity axi_datamover_v5_1_9.axi_datamover_wr_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -----------------------------
aclk => s2mm_aclk ,
reset => sig_mmap_rst ,
-- Slave Stream Input --------------------------------
sf2sin_tready => sig_ibtt2dre_tready ,
sin2sf_tvalid => sig_dre2ibtt_tvalid ,
sin2sf_tdata => sig_dre2ibtt_tdata ,
sin2sf_tkeep => sig_dre2ibtt_tstrb ,
sin2sf_tlast => sig_dre2ibtt_tlast ,
sin2sf_error => sig_realign2wdc_eop_error ,
-- Starting Address Offset Input ---------------------
sin2sf_strt_addr_offset => sig_sf_strt_addr_offset ,
-- DataMover Write Side Address Pipelining Control Interface --------
ok_to_post_wr_addr => sig_ok_to_post_wr_addr ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM -------------
sout2sf_tready => sig_wdc2ibtt_tready ,
sf2sout_tvalid => sig_ibtt2wdc_tvalid ,
sf2sout_tdata => sig_ibtt2wdc_tdata ,
sf2sout_tkeep => sig_ibtt2wdc_tstrb ,
sf2sout_tlast => sig_ibtt2wdc_tlast ,
sf2sout_error => sig_ibtt2wdc_error
);
end generate GEN_INCLUDE_GP_SF;
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => s2mm_awcache_int ,
addr2axi_auser => s2mm_awuser_int ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
-- mstr2addr_cache_info => sig_cache2mstr_command ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_s2mm_allow_addr_req ,
addr_req_posted => sig_s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => ADD_REALIGNER ,
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => sig_ibtt2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2ibtt_tready ,
s2mm_strm_wdata => sig_ibtt2wdc_tdata ,
s2mm_strm_wstrb => sig_ibtt2wdc_tstrb ,
s2mm_strm_wlast => sig_ibtt2wdc_tlast ,
s2mm_strm_eop => sig_ibtt2wdc_eop ,
s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
realign2wdc_eop_error => sig_ibtt2wdc_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
--ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
--begin
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
--end generate ENABLE_AXIMMAP_SKID;
end implementation;
|
bsd-3-clause
|
5199857c907e99680fadd8a013c571df
| 0.451692 | 4.153196 | false | false | false | false |
Ttl/pic16f84
|
testbenches/cpu_core_testbranch.vhd
| 1 | 2,441 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_core_testbranch_tb IS
END cpu_core_testbranch_tb;
ARCHITECTURE behavior OF cpu_core_testbranch_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
PORT(
clk : IN std_logic;
reset : IN std_logic;
porta : INOUT std_logic_vector(4 downto 0);
portb : INOUT std_logic_vector(7 downto 0);
pc_out : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--BiDirs
signal porta : std_logic_vector(4 downto 0);
signal portb : std_logic_vector(7 downto 0);
--Outputs
signal pc_out : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cpu_core
Generic map(instruction_file => "scripts/instructions_testbranch.mif")
PORT MAP (
clk => clk,
reset => reset,
porta => porta,
portb => portb,
pc_out => pc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for clk_period*10;
wait until rising_edge(clk);
reset <= '0';
wait for clk_period/2;
wait for clk_period*10;
assert unsigned(pc_out) > to_unsigned(9,13) report "First branch not cleared" severity failure;
wait for clk_period*14;
assert portb /= "00010110" report "Instruction not skipped" severity failure;
assert unsigned(pc_out) > to_unsigned(21,13) report "PCL update failed" severity failure;
wait for clk_period*5;
assert portb = "11111111" report "Instruction not skipped" severity failure;
wait for clk_period*8;
assert portb = "00000011" report "Instruction not skipped (Call/return)" severity failure;
wait for clk_period*4;
assert portb = "00000011" report "Instruction not skipped (goto)" severity failure;
reset <= '1';
wait for clk_period;
assert false report "Succesfully completed" severity failure;
end process;
END;
|
lgpl-3.0
|
c6727c1eb0936cd6d4359e25be756f34
| 0.626383 | 3.784496 | false | true | false | false |
makestuff/dvr-connectors
|
conv-72to8/vhdl/tb_unit/conv_72to8_tb.vhdl
| 1 | 3,651 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_72to8_tb is
end entity;
architecture behavioural of conv_72to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 72-bit interface signals
signal data72 : std_logic_vector(71 downto 0);
signal valid72 : std_logic;
signal ready72 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_72to8
port map(
clk_in => sysClk,
reset_in => '0',
data72_in => data72,
valid72_in => valid72,
ready72_out => ready72,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data72 <= (others => 'Z');
valid72 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data72 <=
to_4(inLine.all(1)) & to_4(inLine.all(2)) & -- byte 0
to_4(inLine.all(3)) & to_4(inLine.all(4)) & -- byte 1
to_4(inLine.all(5)) & to_4(inLine.all(6)) & -- byte 2
to_4(inLine.all(7)) & to_4(inLine.all(8)) & -- byte 3
to_4(inLine.all(9)) & to_4(inLine.all(10)) & -- byte 4
to_4(inLine.all(11)) & to_4(inLine.all(12)) & -- byte 5
to_4(inLine.all(13)) & to_4(inLine.all(14)) & -- byte 6
to_4(inLine.all(15)) & to_4(inLine.all(16)) & -- byte 7
to_4(inLine.all(17)) & to_4(inLine.all(18)); -- byte 8
valid72 <= to_1(inLine.all(20));
ready8 <= to_1(inLine.all(22));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready72);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data72 <= (others => 'Z');
valid72 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
10bdfd2a2fa375da20b9c95f2a2802e6
| 0.654889 | 3.004938 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/dipswitch.vhdl
| 1 | 1,073 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_dipswitch is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- dip switch
switch : in std_logic_vector(7 downto 0)
);
end mmio_dipswitch;
architecture mmio of mmio_dipswitch is
constant reading : std_logic := '0';
signal data_out : word_t;
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
process(clk)
begin
if rising_edge(clk) and en = '1' and size /= "00" then
case wr is
when reading => zeroextend(data_out, switch);
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end;
|
gpl-3.0
|
a6f97d089c7a952112ebb8a555fb553d
| 0.523765 | 3.612795 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_address_decoder.vhd
| 2 | 22,303 |
-------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_address_decoder.vhd
-- Version: v3.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI4_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI4_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex7" -- "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity qspi_address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of qspi_address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI4_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_quad_spi_v3_2_8.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_quad_spi_v3_2_8.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture imp;
|
bsd-3-clause
|
49c4b2086f828bd442d45e3b237be733
| 0.437475 | 4.650334 | false | false | false | false |
tmeissner/cryptocores
|
cbcmac_aes/rtl/vhdl/cbcmac_aes.vhd
| 1 | 3,577 |
-- ======================================================================
-- CBC-MAC-AES
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity cbcmac_aes is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 tO 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end entity cbcmac_aes;
architecture rtl of cbcmac_aes is
-- CBCMAC must have fix IV for security reasons
constant C_IV : std_logic_vector(0 to 127) := (others => '0');
signal s_aes_datain : std_logic_vector(0 to 127);
signal s_aes_dataout : std_logic_vector(0 to 127);
signal s_aes_dataout_d : std_logic_vector(0 to 127);
signal s_aes_key : std_logic_vector(0 to 127);
signal s_key : std_logic_vector(0 to 127);
signal s_aes_accept : std_logic;
signal s_aes_validout : std_logic;
begin
s_aes_datain <= C_IV xor data_i when start_i = '1' else
s_aes_dataout_d xor data_i;
data_o <= s_aes_dataout;
s_aes_key <= key_i when start_i = '1' else s_key;
accept_o <= s_aes_accept;
valid_o <= s_aes_validout;
inputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_key <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and s_aes_accept = '1' and start_i = '1') then
s_key <= key_i;
end if;
end if;
end process inputregister;
outputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_aes_dataout_d <= (others => '0');
elsif (rising_edge(clk_i)) then
if (s_aes_validout = '1') then
s_aes_dataout_d <= s_aes_dataout;
end if;
end if;
end process outputregister;
i_aes : aes_enc
generic map (
design_type => "ITER"
)
port map (
reset_i => reset_i,
clk_i => clk_i,
key_i => s_aes_key,
data_i => s_aes_datain,
valid_i => valid_i,
accept_o => s_aes_accept,
data_o => s_aes_dataout,
valid_o => s_aes_validout,
accept_i => accept_i
);
end architecture rtl;
|
gpl-2.0
|
f8fd6473bff7352c09b034e350b967f4
| 0.554655 | 3.541584 | false | false | false | false |
tmeissner/cryptocores
|
ctraes/rtl/vhdl/ctraes.vhd
| 1 | 4,028 |
-- ======================================================================
-- CTR-AES
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity ctraes is
generic (
NONCE_WIDTH : natural range 64 to 96 := 96
);
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start ctr
nonce_i : in std_logic_vector(0 to NONCE_WIDTH-1); -- nonce
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 tO 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end entity ctraes;
architecture rtl of ctraes is
signal s_aes_datain : std_logic_vector(data_i'range);
signal s_aes_dataout : std_logic_vector(data_o'range);
signal s_aes_key : std_logic_vector(key_i'range);
signal s_key : std_logic_vector(key_i'range);
signal s_nonce : std_logic_vector(nonce_i'range);
signal s_data_in : std_logic_vector(data_i'range);
signal s_counter : unsigned(0 to 127-NONCE_WIDTH);
begin
s_aes_key <= key_i when start_i = '1' else s_key;
s_aes_datain <= nonce_i & (s_counter'range => '0') when start_i = '1' else
s_nonce & std_logic_vector(s_counter);
data_o <= s_aes_dataout xor s_data_in;
inputreg : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_key <= (others => '0');
s_nonce <= (others => '0');
s_data_in <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
s_data_in <= data_i;
if (start_i = '1') then
s_key <= key_i;
s_nonce <= nonce_i;
end if;
end if;
end if;
end process inputreg;
counterreg : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_counter <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
if (start_i = '1') then
s_counter <= (others => '0');
s_counter(s_counter'high) <= '1';
else
s_counter <= s_counter + 1;
end if;
end if;
end if;
end process counterreg;
i_aes_enc : entity work.aes_enc
generic map (
design_type => "ITER"
)
port map (
reset_i => reset_i,
clk_i => clk_i,
key_i => s_aes_key,
data_i => s_aes_datain,
valid_i => valid_i,
accept_o => accept_o,
data_o => s_aes_dataout,
valid_o => valid_o,
accept_i => accept_i
);
end architecture rtl;
|
gpl-2.0
|
41c0a8e2db8d785d91ea838fc163108f
| 0.521351 | 3.567759 | false | false | false | false |
makestuff/dvr-connectors
|
conv-48to8/vhdl/tb_unit/conv_48to8_tb.vhdl
| 1 | 3,377 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_48to8_tb is
end entity;
architecture behavioural of conv_48to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 48-bit interface signals
signal data48 : std_logic_vector(47 downto 0);
signal valid48 : std_logic;
signal ready48 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_48to8
port map(
clk_in => sysClk,
reset_in => '0',
data48_in => data48,
valid48_in => valid48,
ready48_out => ready48,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data48 <= (others => 'Z');
valid48 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data48 <= to_4(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3)) & to_4(inLine.all(4)) & to_4(inLine.all(5)) & to_4(inLine.all(6)) & to_4(inLine.all(7)) & to_4(inLine.all(8)) & to_4(inLine.all(9)) & to_4(inLine.all(10)) & to_4(inLine.all(11)) & to_4(inLine.all(12));
valid48 <= to_1(inLine.all(14));
ready8 <= to_1(inLine.all(16));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready48);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data48 <= (others => 'Z');
valid48 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
c24aa422ebfc96bbd977edb7df25b71e
| 0.669825 | 3.075592 | false | false | false | false |
tmeissner/cryptocores
|
des/rtl/vhdl/des_pkg.vhd
| 1 | 12,677 |
-- ======================================================================
-- DES encryption/decryption
-- package file with functions
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package des_pkg is
component des is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 to 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end component des;
type ip_matrix is array (0 to 63) of natural range 0 to 63;
constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7,
56, 48, 40, 32, 24, 16, 8, 0,
58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6);
constant ipn_table : ip_matrix := (39, 7, 47, 15, 55, 23, 63, 31,
38, 6, 46, 14, 54, 22, 62, 30,
37, 5, 45, 13, 53, 21, 61, 29,
36, 4, 44, 12, 52, 20, 60, 28,
35, 3, 43, 11, 51, 19, 59, 27,
34, 2, 42, 10, 50, 18, 58, 26,
33, 1, 41, 9, 49, 17, 57, 25,
32, 0, 40, 8, 48, 16, 56, 24);
type e_matrix is array (0 to 47) of natural range 0 to 31;
constant e_table : e_matrix := (31, 0, 1, 2, 3, 4,
3, 4, 5, 6, 7, 8,
7, 8, 9, 10, 11, 12,
11, 12, 13, 14, 15, 16,
15, 16, 17, 18, 19, 20,
19, 20, 21, 22, 23, 24,
23, 24, 25, 26, 27, 28,
27, 28, 29, 30, 31, 0);
type s_matrix is array (0 to 3, 0 to 15) of integer range 0 to 15;
constant s1_table : s_matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7),
1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8),
2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0),
3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13));
constant s2_table : s_matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10),
1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5),
2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15),
3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9));
constant s3_table : s_matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8),
1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1),
2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7),
3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12));
constant s4_table : s_matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15),
1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9),
2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4),
3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14));
constant s5_table : s_matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9),
1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6),
2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14),
3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3));
constant s6_table : s_matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11),
1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8),
2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6),
3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13));
constant s7_table : s_matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1),
1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6),
2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2),
3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12));
constant s8_table : s_matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7),
1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2),
2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8),
3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11));
type pc_matrix is array (0 to 27) of natural range 0 to 63;
constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16, 8,
0, 57, 49, 41, 33, 25, 17,
9, 1, 58, 50, 42, 34, 26,
18, 10, 2, 59, 51, 43, 35);
constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
6, 61, 53, 45, 37, 29, 21,
13, 5, 60, 52, 44, 36, 28,
20, 12, 4, 27, 19, 11, 3);
type p_matrix is array (0 to 31) of natural range 0 to 31;
constant p_table : p_matrix := (15, 6, 19, 20,
28, 11, 27, 16,
0, 14, 22, 25,
4, 17, 30, 9,
1, 7, 23, 13,
31, 26, 2, 8,
18, 12, 29, 5,
21, 10, 3, 24);
type pc2_matrix is array (0 to 47) of natural range 0 to 63;
constant pc2_table : pc2_matrix := (13, 16, 10, 23, 0, 4,
2, 27, 14, 5, 20, 9,
22, 18, 11, 3, 25, 7,
15, 6, 26, 19, 12, 1,
40, 51, 30, 36, 46, 54,
29, 39, 50, 44, 32, 47,
43, 48, 38, 55, 33, 52,
45, 41, 49, 35, 28, 31);
function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
function s (input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector;
function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector;
function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector;
end package des_pkg;
package body des_pkg is
function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 63);
begin
for index IN 0 to 63 loop
result( index ) := input_vector( ip_table( index ) );
end loop;
return result;
end function ip;
function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 63);
begin
for index IN 0 to 63 loop
result( index ) := input_vector( ipn_table( index ) );
end loop;
return result;
end function ipn;
function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
variable result : std_logic_vector(0 to 47);
begin
for index IN 0 to 47 loop
result( index ) := input_vector( e_table( index ) );
end loop;
return result;
end function e;
function s ( input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector is
variable int : std_logic_vector(0 to 1);
variable i : integer range 0 to 3;
variable j : integer range 0 to 15;
variable result : std_logic_vector(0 to 3);
begin
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 to 4) ) );
result := std_logic_vector( to_unsigned( s_table( i, j ), 4 ) );
return result;
end function s;
function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
variable result : std_logic_vector(0 to 31);
begin
for index IN 0 to 31 loop
result( index ) := input_vector( p_table( index ) );
end loop;
return result;
end function p;
function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector is
variable intern : std_logic_vector(0 to 47);
variable result : std_logic_vector(0 to 31);
begin
intern := e( input_r ) xor input_key;
result := p( s( intern(0 to 5), s1_table ) & s( intern(6 to 11), s2_table ) & s( intern(12 to 17), s3_table ) &
s( intern(18 to 23), s4_table ) & s( intern(24 to 29), s5_table ) & s( intern(30 to 35), s6_table ) &
s( intern(36 to 41), s7_table ) & s( intern(42 to 47), s8_table ) );
return result;
end function f;
function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 27);
begin
for index IN 0 to 27 loop
result( index ) := input_vector( pc1c_table( index ) );
end loop;
return result;
end function pc1_c;
function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 27);
begin
for index IN 0 to 27 loop
result( index ) := input_vector( pc1d_table( index ) );
end loop;
return result;
end function pc1_d;
function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector is
variable result : std_logic_vector(0 to 47);
begin
for index IN 0 to 47 loop
result( index ) := input_vector( pc2_table( index ) );
end loop;
return result;
end function pc2;
end package body des_pkg;
|
gpl-2.0
|
6dee75b6e57f32c2991cf8105598df90
| 0.441272 | 3.053963 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd
| 4 | 88,974 |
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the width of the alignment control inputs
-- Should be log2(C_DWIDTH)
);
port (
-- Clock and Reset Input ----------------------------------------------
--
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------------------------------------
-- Alignment Control (Independent from Stream Input timing) ----------
--
dre_align_ready : Out std_logic; --
dre_align_valid : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Flush Control (Aligned to input Stream timing) --------------------
--
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Stream Input Channel ----------------------------------------------
--
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Stream Output Channel ---------------------------------------------
--
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_s2mm_dre;
architecture implementation of axi_datamover_s2mm_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
Signal sig_cntl_accept : std_logic := '0';
Signal sig_dre_halted : std_logic := '0';
begin --(architecture implementation)
-- Misc port assignments
dre_align_ready <= sig_dre_halted or
sig_flush_db2_complete ;
dre_in_tready <= sig_input_accept ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
-- Internal logic
sig_cntl_accept <= dre_align_valid and
(sig_dre_halted or
sig_flush_db2_complete);
sig_pipeline_halt <= sig_dre_halted or
(sig_dre_tvalid_i and
not(dre_out_tready));
sig_output_xfer <= sig_dre_tvalid_i and
dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt);
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
not(sig_pipeline_halt) and
not(sig_input_flush_stall);
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or
sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
------------------------------------------------------------------------------------
-- DRE Halted logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_HALTED_FLOP
--
-- Process Description:
-- Implements a flop for the Halted state flag. All DRE
-- operation is halted until a new alignment control is
-- loaded. The DRE automatically goes into halted state
-- at reset and at completion of a flush operation.
--
-------------------------------------------------------------
IMP_DRE_HALTED_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
(sig_flush_db2_complete = '1' and
dre_align_valid = '0'))then
sig_dre_halted <= '1'; -- default to halted state
elsif (sig_cntl_accept = '1') then
sig_dre_halted <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_DRE_HALTED_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Input Register for the flush command
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
Signal s_case_i_64 : Integer range 0 to 7 := 0;
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
Signal s_case_i_32 : Integer range 0 to 3 := 0;
signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
Signal s_case_i_16 : Integer range 0 to 1 := 0;
signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic := '0';
Signal sig_shift_case_reg : std_logic := '0';
Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_9.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
|
bsd-3-clause
|
443dbc4bc87e6b855303bebd8b4c3003
| 0.367388 | 4.619866 | false | false | false | false |
makestuff/dvr-connectors
|
conv-24to8/vhdl/tb_unit/conv_24to8_tb.vhdl
| 1 | 3,246 |
--
-- Copyright (C) 2012-2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_24to8_tb is
end entity;
architecture behavioural of conv_24to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 24-bit interface signals
signal data24 : std_logic_vector(23 downto 0);
signal valid24 : std_logic;
signal ready24 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_24to8
port map(
clk_in => sysClk,
reset_in => '0',
data24_in => data24,
valid24_in => valid24,
ready24_out => ready24,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data24 <= (others => 'Z');
valid24 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data24 <= to_4(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3)) & to_4(inLine.all(4)) & to_4(inLine.all(5)) & to_4(inLine.all(6));
valid24 <= to_1(inLine.all(8));
ready8 <= to_1(inLine.all(10));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready24);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data24 <= (others => 'Z');
valid24 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
770162c79be47b067182b91f129357ec
| 0.672828 | 3.139265 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/Lines.vhd
| 1 | 9,026 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name: Box Overlay Filter 2
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter passes the video signals from input to output except at
-- locations defined by user registers, where instead it will draw lines.
-- This filter draws lines on the image that form a box where the line
-- thickness is defined by a user register.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
-- Begin Box architecture
architecture Behavioral of Video_Box is
-- X location signals
signal x,x1,x2 : signed(15 downto 0);
-- Y location signals
signal y,y1,y2,diff : signed(15 downto 0);
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
-- Get the pixel's x and y coordinates
x <= signed(X_Coord);
y <= signed(Y_Coord);
-- Get the left and right x coordinates from the registers
x1 <= signed(slv_reg0(15 downto 0));
x2 <= signed(slv_reg1(15 downto 0));
-- Get the top and bottom y coordinates from the registers
y1 <= signed(slv_reg2(15 downto 0));
y2 <= signed(slv_reg3(15 downto 0));
-- Get the size of the lines desired by reading register 4
diff <= signed(slv_reg4(15 downto 0));
-- Create a variable width pixel box at the register defined locations
-- When the display isn't being written to, write 0's
USER_LOGIC <= (others => '0') when VDE_IN_reg = '0' else
-- if the y value is greater than y1-diff and less than y1+diff,
-- then make change the color to the line's color
x"FF0000" when (y > (y1-diff) and y < (y1+diff)) else
-- if the y value is greater than y2-diff and less than y2+diff,
-- then make change the color to the line's color
x"00FF00" when (y > (y2-diff) and y < (y2+diff)) else
-- if the x value is greater than x1-diff and less than x1+diff,
-- then make change the color to the line's color
x"0000FF" when (x > (x1-diff) and x < (x1+diff)) else
-- if the x value is greater than x2-diff and less than x2+diff,
-- then make change the color to the line's color
x"FF00FF" when (x > (x2-diff) and x < (x2+diff)) else
-- Otherwise, pass the RGB value straight through
RGB_IN_reg;
-- Pass the other video signals straight through
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
-- End Box architecture
|
bsd-3-clause
|
e59d6aa5e30f1b30766b1aa5ec0aa3ea
| 0.616552 | 3.108127 | false | false | false | false |
Ttl/pic16f84
|
buffer.vhd
| 1 | 1,052 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.picpkg.all;
entity ctrl_buf is
Port ( clk : in STD_LOGIC;
amux : in STD_LOGIC_VECTOR(1 downto 0);
bmux, writew, rwmux: in STD_LOGIC;
alu_op : in alu_ctrl;
instr10 : in STD_LOGIC_VECTOR(10 downto 0);
status_write : in STD_LOGIC_VECTOR(4 downto 0);
skip_dp : in std_logic;
amux_ex : out STD_LOGIC_VECTOR(1 downto 0);
bmux_ex, writew_ex, rwmux_ex : out STD_LOGIC;
alu_op_ex : out alu_ctrl;
instr10_ex : out STD_LOGIC_VECTOR(10 downto 0);
status_write_ex : out STD_LOGIC_VECTOR(4 downto 0);
skip_ex : out std_logic);
end ctrl_buf;
architecture Behavioral of ctrl_buf is
begin
process(clk)
begin
if rising_edge(clk) then
amux_ex <= amux;
bmux_ex <= bmux;
writew_ex <= writew;
rwmux_ex <= rwmux;
alu_op_ex <= alu_op;
instr10_ex <= instr10;
status_write_ex <= status_write;
skip_ex <= skip_dp;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
7d69bb4bbf43a3ee55fdb0386ebb8060
| 0.590304 | 3.217125 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/src/PmodNAV_axi_quad_spi_0_0/synth/PmodNAV_axi_quad_spi_0_0.vhd
| 1 | 16,191 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_8;
USE axi_quad_spi_v3_2_8.axi_quad_spi;
ENTITY PmodNAV_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END PmodNAV_axi_quad_spi_0_0;
ARCHITECTURE PmodNAV_axi_quad_spi_0_0_arch OF PmodNAV_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF PmodNAV_axi_quad_spi_0_0_arch : ARCHITECTURE IS "PmodNAV_axi_quad_spi_0_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "PmodNAV_axi_quad_spi_0_0,axi_quad_spi,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Async_Clk=1,C_FAMILY=zynq,C_SELECT_XPM=0,C_SUB_FAMILY=zynq,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=16,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=0,C_USE_STARTUP=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7" &
",C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '0',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END PmodNAV_axi_quad_spi_0_0_arch;
|
bsd-3-clause
|
07940a38039c63fe1ce0ec9a2cf384f1
| 0.649929 | 2.988372 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/vga/color_util.vhdl
| 1 | 2,850 |
library ieee;
use ieee.std_logic_1164.all;
package color_util is
type rgb_t is record r, g, b : std_logic_vector(3 downto 0); end record;
function rgb (color: std_logic_vector(11 downto 0)) return rgb_t;
function rgb_negate(color : rgb_t) return rgb_t;
procedure nibbles_from_rgb(signal r,g,b : out std_logic_vector (3 downto 0); rgb : in rgb_t);
-- Raylib's color palette
constant BEIGE : rgb_t := ( "1101", "1011", "1000" );
constant BLACK : rgb_t := ( "0000", "0000", "0000" );
constant BLANK : rgb_t := ( "0000", "0000", "0000" );
constant BLUE : rgb_t := ( "0000", "1111", "1111" );
constant BROWN : rgb_t := ( "1111", "1101", "1001" );
constant DARKBLUE : rgb_t := ( "0000", "1010", "1010" );
constant DARKBROWN : rgb_t := ( "1001", "1111", "1011" );
constant DARKGRAY : rgb_t := ( "1010", "1010", "1010" );
constant DARKGREEN : rgb_t := ( "0000", "1110", "1011" );
constant DARKGREY : rgb_t := ( "1010", "1010", "1010" );
constant DARKPURPL : rgb_t := ( "1110", "1111", "1111" );
constant GOLD : rgb_t := ( "1111", "1100", "0000" );
constant GRAY : rgb_t := ( "1000", "1000", "1000" );
constant GREEN : rgb_t := ( "0000", "1110", "1100" );
constant GREY : rgb_t := ( "1000", "1000", "1000" );
constant LIGHTGRAY : rgb_t := ( "1100", "1100", "1100" );
constant LIGHTGREY : rgb_t := ( "1100", "1100", "1100" );
constant LIME : rgb_t := ( "0000", "1001", "1011" );
constant MAGENTA : rgb_t := ( "1111", "0000", "1111" );
constant MAROON : rgb_t := ( "1011", "1000", "1101" );
constant ORANGE : rgb_t := ( "1111", "1010", "0000" );
constant PINK : rgb_t := ( "1111", "1101", "1100" );
constant PURPLE : rgb_t := ( "1100", "1111", "1111" );
constant RED : rgb_t := ( "1110", "1010", "1101" );
constant SKYBLUE : rgb_t := ( "1100", "1011", "1111" );
constant VIOLET : rgb_t := ( "1000", "1111", "1011" );
constant WHITE : rgb_t := ( "1111", "1111", "1111" );
constant YELLOW : rgb_t := ( "1111", "1111", "0000" );
end color_util;
package body color_util is
function rgb (color: std_logic_vector(11 downto 0)) return rgb_t is
subtype r is std_logic_vector (11 downto 8);
subtype g is std_logic_vector ( 7 downto 4);
subtype b is std_logic_vector ( 3 downto 0);
begin
return rgb_t'(color(r'range), color(g'range), color(b'range));
end function;
function rgb_negate(color : rgb_t) return rgb_t is
begin
return rgb_t'(not color.r, not color.g, not color.b);
end function;
procedure nibbles_from_rgb(signal r,g,b : out std_logic_vector (3 downto 0); rgb : in rgb_t) is
begin
r <= rgb.r;
g <= rgb.g;
b <= rgb.b;
end;
end color_util;
|
gpl-3.0
|
b6e3d2ae70e46e95ca1948c6c4271e08
| 0.543158 | 3.081081 | false | false | false | false |
Ttl/pic16f84
|
pc_control.vhd
| 1 | 3,400 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity pc_control is
Port ( clk, reset : in STD_LOGIC;
instr : in STD_LOGIC_VECTOR(13 downto 0);
pc : out STD_LOGIC_VECTOR (12 downto 0);
pc_ret : in STD_LOGIC_VECTOR (12 downto 0);
pc_mem : in STD_LOGIC_VECTOR(12 downto 0);
intcon : in STD_LOGIC_VECTOR(7 downto 0);
branch, skip_next : in STD_LOGIC;
fsr_to_pcl : in STD_LOGIC;
retrn : in STD_LOGIC;
alu_z : in STD_LOGIC;
tmr0_overflow : in STD_LOGIC;
interrupt_out : out interrupt_type;
portb_interrupt : in STD_LOGIC;
portb0_interrupt : in STD_LOGIC;
skip_dp : out STD_LOGIC
);
end pc_control;
architecture Behavioral of pc_control is
signal pc_plus1_int : std_logic_vector(12 downto 0);
signal pc_tmp : std_logic_vector(12 downto 0);
signal skip_tmp : std_logic;
signal skip : std_logic;
signal pcreg_in : std_logic_vector(12 downto 0);
signal pcl_update, pcl_update_delay : std_logic;
signal branch_delay, retrn_delay : std_logic;
signal interrupt : interrupt_type;
begin
-- Forward the information about PCL update (movwf PCL or movwf INDF and FSR = 0x10)
pcl_update <= '1' when (instr = "00000010000010") or (instr = "00000010000000" and fsr_to_pcl = '1') else '0';
pc_plus1_int <= std_logic_vector(unsigned(pc_tmp) + to_unsigned(1,13));
pcreg_in <= std_logic_vector(to_unsigned(4,13)) when interrupt /= I_NONE else
pc_ret when retrn = '1' else
pc_mem when pcl_update = '1' else
pc_plus1_int when branch = '0' or skip = '1'
else pc_tmp(12 downto 11)&instr(10 downto 0);
pc <= pc_tmp;
skip <= (skip_tmp and alu_z) or pcl_update_delay or branch_delay or retrn_delay;
skip_dp <= skip;
-- Skip delay
skip_delay : process(clk)
begin
if rising_edge(clk) then
pcl_update_delay <= pcl_update;
skip_tmp <= skip_next;
branch_delay <= branch;
retrn_delay <= retrn;
end if;
end process;
-- Interrupt logic
process(clk, tmr0_overflow, portb_interrupt, intcon, portb0_interrupt, skip)
variable interrupt_hold : interrupt_type := I_NONE;
alias gie is intcon(7);
alias t0ie is intcon(5);
alias rbie is intcon(3);
alias inte is intcon(4);
begin
if rising_edge(clk) then
interrupt <= I_NONE;
if gie = '1' and interrupt_hold = I_NONE then
-- TMR0
if (tmr0_overflow and t0ie) = '1' then
interrupt_hold := I_TMR0;
end if;
-- PORTB(7 downto 4) changed interrupt
if (portb_interrupt and rbie) = '1' then
interrupt_hold := I_RB;
end if;
-- PORTB(0)/INR interrupt
if (portb0_interrupt and inte) = '1' then
interrupt_hold := I_INT;
end if;
end if;
-- If we are skipping instruction we need to finish executing it
-- before interrupting, because skip signal is not saved
-- and otherwise the skipped instruction would be executed on return
if skip = '0' then
interrupt <= interrupt_hold;
interrupt_hold := I_NONE;
end if;
end if;
end process;
interrupt_out <= interrupt;
pc_reg : entity work.flopr
generic map( WIDTH => 13)
port map(clk => clk,
reset => reset,
d => pcreg_in,
q => pc_tmp
);
end Behavioral;
|
lgpl-3.0
|
8b5f2d92ecf7b47ffee484baf2bb84a3
| 0.614706 | 3.406814 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_b.vhd
| 1 | 1,290 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_b is
port (
q : in std_logic_vector(31 downto 0);
A : in std_logic_vector(31 downto 0);
k : in std_logic_vector(31 downto 0);
T : in std_logic_vector(31 downto 0);
clock : in std_logic;
B : out std_logic_vector(31 downto 0)
);
end k_ukf_b;
architecture struct of k_ukf_b is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_div IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => q,
datab => A,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => k,
datab => T,
result => Z2);
M3 : k_ukf_div port map
( clock => clock,
dataa => Z1,
datab => Z2,
result => B);
end struct;
|
gpl-2.0
|
09ecd7c7b0aabde3b1bda5747c4111b1
| 0.562016 | 2.898876 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/cpu_tb.vhdl
| 1 | 8,806 |
-- SKIP because I still have to get it working
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
use work.memory_map.all;
entity cpu_tb is
end;
architecture struct of cpu_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
signal readreg1, readreg2 : reg_t := R0;
signal writereg: reg_t := R0;
signal regReadData1, regReadData2, regWriteData : word_t := ZERO;
signal regWrite : ctrl_t := '0';
component mem is
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic
);
end component;
component InstructionFetch is
generic(PC_ADD, CPI : natural; SINGLE_ADDRESS_SPACE : boolean);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end component;
component InstructionDecode is
port(
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread, memwrite : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
component Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end component;
component MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
component WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end component;
-- control signals
signal Link, Branch, JumpReg, JumpDir, memToreg, TakeBranch, Shift, ALUSrc, MemSex : ctrl_t;
signal MemRead, MemWrite : ctrl_memwidth_t;
signal memReadData : word_t;
signal new_pc : addr_t;
signal pc_plus_4, jump_addr, branch_addr : addr_t;
signal instr : instruction_t;
signal zeroxed, sexed, aluResult: word_t;
signal aluop : alu_op_t;
signal cpuclk : std_logic := '0';
signal regclk : std_logic := '0';
signal halt_cpu : boolean := false;
signal cpurst : std_logic := '0';
signal regrst : std_logic := '0';
signal done : boolean := false;
constant ESC : Character := Character'val(27);
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
begin
regFile1: regFile
port map(
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg, writedata => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => regclk, rst => regrst,
regWrite => regWrite
);
if1: InstructionFetch
generic map (PC_ADD => 4, CPI => 4, SINGLE_ADDRESS_SPACE => true)
port map(
clk => cpuclk,
rst => cpurst,
new_pc => new_pc,
pc_plus_4 => pc_plus_4,
instr => instr,
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr
);
mem_bus: mem port map (
addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
clk => cpuclk
);
id1: InstructionDecode
port map(instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr,
regwrite => regwrite, link => link, jumpreg => jumpreg, jumpdirect => jumpdir, branch => Branch,
memread => memread, memwrite => memwrite,
memtoreg => memtoreg, memsex => memsex,
shift => shift, alusrc => aluSrc,
aluop => aluOp,
readreg1 => readReg1, readreg2 => readReg2, writeReg => writeReg,
zeroxed => zeroxed, sexed => sexed,
clk => cpuclk,
rst => cpurst
);
ex1: Execute
port map(
pc_plus_4 => pc_plus_4,
regReadData1 => regReadData1, regReadData2 => regReadData2,
branch_addr => branch_addr,
branch_in => Branch,
shift_in => shift, alusrc_in => ALUSrc,
aluop_in => ALUOp,
zeroxed => zeroxed, sexed => sexed,
takeBranch => takeBranch,
ALUResult => ALUResult,
clk => cpuclk,
rst => cpurst
);
ma1: memoryAccess
port map(
-- inbound
Address_in => AluResult,
WriteData_in => regReadData2,
ReadData_in => memReadData,
MemRead_in => memRead, MemWrite_in => memWrite,
MemSex_in => memSex,
clk => cpuclk,
-- outbound to top level module
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr);
wb1: WriteBack
port map(
Link => Link,
JumpReg => JumpReg,
JumpDir => JumpDir,
MemToReg => MemToReg,
TakeBranch => TakeBranch,
pc_plus_4 => pc_plus_4,
branch_addr => branch_addr,
jump_addr => jump_addr,
aluResult => aluResult,
memReadData => memReadData,
regReadData1 => regReadData1,
regWriteData => regWriteData,
new_pc => new_pc);
test : process
begin
-- This halt_cpu thing doesn't work yet
--halt_cpu <= true;
--regrst <= '0';
--wait for 2 ns;
--regrst <= '1';
--wait for 2 ns;
--regrst <= '0';
--wait for 20 ns;
--readreg1 <= R1;
--wait for 2 ns;
--assert regReadData1 = ZERO report
-- ANSI_RED "Failed to reset. 0 /= " & to_hstring(regReadData1) & ANSI_NONE
--severity error;
--halt_cpu <= false;
cpurst <= '0';
wait for 2 ns;
cpurst <= '1';
wait for 2 ns;
cpurst <= '0';
wait for 55 ns;
readreg1 <= R1;
wait for 2 ns;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
readreg1 <= R1;
readreg2 <= R2;
wait for 2 ns;
assert regReadData2 = X"0000_FBAD" report
ANSI_RED & "Failed to ori. 0xFBAD /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
done <= true;
wait;
end process;
clkproc: process
begin
regclk <= not regclk;
if not halt_cpu then
cpuclk <= not cpuclk;
end if;
wait for 1 ns;
if done then wait; end if;
end process;
end struct;
|
gpl-3.0
|
b2674cf4e759e90473b5b2a1344fe042
| 0.508517 | 4.122659 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/generic_fifo.vhd
| 1 | 3,836 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_uart_pack.all;
entity generic_fifo is
generic (
FIFO_WIDTH : positive := 32;
FIFO_DEPTH : positive := 1024
);
port (
clock : in std_logic;
nreset : in std_logic;
write_data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
read_data : out std_logic_vector(FIFO_WIDTH-1 downto 0);
write_en : in std_logic;
read_en : in std_logic;
full : out std_logic;
empty : out std_logic;
level : out std_logic_vector(clogb2(FIFO_DEPTH)-1 downto 0
)
);
end entity;
architecture RTL of generic_fifo is
---------------------------------------------------------------------------
-- Functions
---------------------------------------------------------------------------
function get_fifo_level(
write_pointer : unsigned;
read_pointer : unsigned;
depth : positive) return integer is
begin
if write_pointer > read_pointer then
return to_integer(write_pointer - read_pointer);
elsif write_pointer = read_pointer then
return 0;
else
return (
((depth) - to_integer(read_pointer)) +
to_integer(write_pointer)
);
end if;
end function get_fifo_level;
---------------------------------------------------------------------------
-- Types
---------------------------------------------------------------------------
type memory is array (0 to FIFO_DEPTH-1) of std_logic_vector(
FIFO_WIDTH-1 downto 0
);
---------------------------------------------------------------------------
-- Signals
---------------------------------------------------------------------------
signal fifo_memory : memory := (others => (others => '0'));
signal read_pointer, write_pointer : unsigned(clogb2(FIFO_DEPTH)-1 downto 0) := (others => '0');
signal fifo_empty : std_logic := '1';
signal fifo_full : std_logic := '0';
begin
full <= fifo_full;
empty <= fifo_empty;
FIFO_FLAGS : process(write_pointer, read_pointer) is
variable lev : integer range 0 to FIFO_DEPTH - 1;
begin
lev := get_fifo_level(write_pointer, read_pointer, FIFO_DEPTH);
level <= std_logic_vector(to_unsigned(lev, level'length));
if lev = FIFO_DEPTH - 1 then
fifo_full <= '1';
else
fifo_full <= '0';
end if;
if lev = 0 then
fifo_empty <= '1';
else
fifo_empty <= '0';
end if;
end process;
FIFO_LOGIC : process(clock) is
begin
if rising_edge(clock) then
if nreset = '0' then
write_pointer <= (others => '0');
read_pointer <= (others => '0');
else
-- FIFO WRITE
if write_en = '1' and fifo_full = '0' then
fifo_memory(to_integer(write_pointer)) <= write_data;
if write_pointer < FIFO_DEPTH - 1 then
write_pointer <= write_pointer + 1;
else
write_pointer <= (others => '0');
end if;
end if;
-- FIFO READ
if read_en = '1' and fifo_empty = '0' then
if read_pointer < FIFO_DEPTH - 1 then
read_pointer <= read_pointer + 1;
else
read_pointer <= (others => '0');
end if;
end if;
end if;
end if;
end process;
read_data <= fifo_memory(to_integer(read_pointer));
end RTL;
|
mit
|
a6b80d619f188119e832b44441ea4100
| 0.434567 | 4.566667 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0.vhd
| 1 | 10,812 |
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`protect end_protected
|
apache-2.0
|
e957a08e658087ee781d9c402e930fc6
| 0.923881 | 1.937982 | false | false | false | false |
Apollinaire/GameOfLife_FPGA
|
sources/BSOD.vhd
| 1 | 4,092 |
----------------------------------------------------------------------------------
-- Module Name: vga1440x900 - Behavioral
-- Version: 1.0
-- Author: Mike Field ([email protected])
--
-- Generate 1440 x 900 x 256 colour VGA signals.
--
-- Horizontal timing (frame)
-- Scanline part Pixels Time [µs]
-- Visible area 1440 13.52493660186
-- Front porch 80 0.75138536676998
-- Sync pulse 152 1.427632196863
-- Back porch 232 2.1790175636329
-- Whole line 1904 17.882971729126
--
-- Vertical timing (frame)
-- Polarity of vertical sync pulse is positive.
-- Frame part Lines Time [ms]
-- Visible area 900 16.094674556213
-- Front porch 1 0.017882971729126
-- Sync pulse 3 0.053648915187377
-- Back porch 28 0.50072320841552
-- Whole frame 932 16.666929651545
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BSOD is
port ( CLK : in std_logic;
-- data vga
R1 : in std_logic;
R2 : in std_logic;
R3 : in std_logic;
G1 : in std_logic;
G2 : in std_logic;
G3 : in std_logic;
B1 : in std_logic;
B2 : in std_logic;
Hsync : out std_logic;
Vsync : out std_logic;
vgaBlue : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaRed : out std_logic_vector (3 downto 0);
-- data image
px : in std_logic;
X,Y : out integer range 0 to 800
);
end BSOD;
architecture Behavioral of BSOD is
signal hcounter : integer range 0 to 800 :=0;
signal vcounter : integer range 0 to 525 :=0;
signal slowClk : STD_LOGIC;
signal cpt : integer range 0 to 3 :=0 ;
signal red, blue, green : STD_LOGIC_VECTOR (3 downto 0) :="0000";
signal h, v : STD_LOGIC;
signal xInt,yInt: integer range 0 to 800;
begin
vgaBlue <= blue;
vgaRed <= red;
vgaGreen <= green;
Hsync <= h;
Vsync<=v;
X<=xInt;
Y<=yInt;
xInt<= hcounter-47 when hcounter >=47 else 800;
yInt<= vcounter-32 when vcounter >=32 else 800;
process(hcounter, vcounter, slowClk, CLK) --, R1, R2, R3, G1, G2, G3, B1, B2) --Display
begin
if CLK'EVENT and CLK='1' and slowClk='1' then
if (hcounter>47 and hcounter<47+640 and vcounter>32 and vcounter<32+480) then
-- display instructions
if px = '1' then
red <= '0'&R1&R2&R3;
green<='0'&G1&G2&G3;
blue<='0'&B1&B2&'1';
else
red<="0111";
green<="0111";
blue<="0011";
end if;
else
red<="0000";
green<="0000";
blue<="0000";
end if;
end if;
end process;
process (hcounter,CLK,slowClk) --hsync management
begin
if CLK'EVENT and CLK='1' and slowClk='1' then
if hcounter>=(48+640+16-1) then
h<='0';
else
h<='1';
end if;
end if;
end process;
process (vcounter,CLK,slowClk) --vsync management
begin
if CLK'EVENT and CLK = '1' and slowClk='1' then
if vcounter>=(33+480+10-1) then
v<='0';
else
v<='1';
end if;
end if;
end process;
process(slowClk,hcounter,vcounter,clk) --counters Management
begin
if CLK'EVENT and CLK = '1' then
if slowClk = '1' then
if hcounter=799 then
hcounter<=0;
if vcounter = 524 then
vcounter<=0;
else
vcounter<=vcounter+1;
end if;
else
hcounter<=hcounter+1;
end if;
end if;
end if;
end process;
process (CLK) --slowClk at 25MHz is the standard VGA rate for 640x480 at 60fps
begin
if CLK'EVENT and CLK = '1' then
cpt<=cpt+1;
if cpt >= 3 then
slowClk <= '1';
cpt<=0;
else
slowClk <= '0';
end if;
end if;
end process;
end behavioral;
|
mit
|
f144cf8420afc1c03fa09fcc95389b88
| 0.531525 | 3.527586 | false | false | false | false |
tmeissner/cryptocores
|
aes/sim/vhdl/tb_aes.vhd
| 1 | 5,267 |
-- ======================================================================
-- AES encryption/decryption
-- Copyright (C) 2019 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use std.env.all;
use work.aes_pkg.all;
entity tb_aes is
end entity tb_aes;
architecture rtl of tb_aes is
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_mode : std_logic := '0';
signal s_key : std_logic_vector(0 to 127) := (others => '0');
signal s_datain : std_logic_vector(0 to 127) := (others => '0');
signal s_validin_enc : std_logic := '0';
signal s_acceptout_enc : std_logic;
signal s_dataout_enc : std_logic_vector(0 to 127);
signal s_validout_enc : std_logic;
signal s_acceptin_enc : std_logic := '0';
signal s_validin_dec : std_logic := '0';
signal s_acceptout_dec : std_logic;
signal s_dataout_dec : std_logic_vector(0 to 127);
signal s_validout_dec : std_logic;
signal s_acceptin_dec : std_logic := '0';
procedure cryptData(datain : in std_logic_vector(0 to 127);
key : in std_logic_vector(0 to 127);
mode : in boolean;
dataout : out std_logic_vector(0 to 127);
bytelen : in integer) is
begin
report "VHPIDIRECT cryptData" severity failure;
end procedure;
attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
variable v_data : std_logic_vector(0 to 127);
begin
for i in 0 to 15 loop
for y in 0 to 7 loop
v_data((i*8)+y) := datain((i*8)+7-y);
end loop;
end loop;
return v_data;
end function;
begin
s_clk <= not(s_clk) after 10 ns;
s_reset <= '1' after 100 ns;
i_aes_enc : aes_enc
port map (
reset_i => s_reset,
clk_i => s_clk,
key_i => s_key,
data_i => s_datain,
valid_i => s_validin_enc,
accept_o => s_acceptout_enc,
data_o => s_dataout_enc,
valid_o => s_validout_enc,
accept_i => s_acceptin_enc
);
i_aes_dec : aes_dec
port map (
reset_i => s_reset,
clk_i => s_clk,
key_i => s_key,
data_i => s_datain,
valid_i => s_validin_dec,
accept_o => s_acceptout_dec,
data_o => s_dataout_dec,
valid_o => s_validout_dec,
accept_i => s_acceptin_dec
);
process is
variable v_key : std_logic_vector(0 to 127);
variable v_datain : std_logic_vector(0 to 127);
variable v_dataout : std_logic_vector(0 to 127);
variable v_random : RandomPType;
begin
v_random.InitSeed(v_random'instance_name);
wait until s_reset = '1';
-- ENCRYPTION TESTs
report "Test encryption";
for i in 0 to 63 loop
wait until rising_edge(s_clk);
s_validin_enc <= '1';
v_key := v_random.RandSlv(128);
v_datain := v_random.RandSlv(128);
s_key <= v_key;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), true, v_dataout, v_datain'length/8);
wait until s_acceptout_enc = '1' and rising_edge(s_clk);
s_validin_enc <= '0';
wait until s_validout_enc = '1' and rising_edge(s_clk);
s_acceptin_enc <= '1';
assert s_dataout_enc = swap(v_dataout)
report "Encryption error"
severity failure;
wait until rising_edge(s_clk);
s_acceptin_enc <= '0';
end loop;
-- DECRYPTION TESTs
report "Test decryption";
for i in 0 to 63 loop
wait until rising_edge(s_clk);
s_validin_dec <= '1';
v_key := v_random.RandSlv(128);
v_datain := v_random.RandSlv(128);
s_key <= v_key;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), false, v_dataout, v_datain'length/8);
wait until s_acceptout_dec = '1' and rising_edge(s_clk);
s_validin_dec <= '0';
wait until s_validout_dec = '1' and rising_edge(s_clk);
s_acceptin_dec <= '1';
assert s_dataout_dec = swap(v_dataout)
report "Decryption error"
severity failure;
wait until rising_edge(s_clk);
s_acceptin_dec <= '0';
end loop;
wait for 100 ns;
report "Tests successful";
finish(0);
end process;
end architecture rtl;
|
gpl-2.0
|
02df747ed5f2c35227a0e719512aff1e
| 0.578128 | 3.442484 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/img_overlay_256color.vhd
| 1 | 15,947 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 03/17/2017 11:07:04 AM
-- Design Name: RGB filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter allows the edit of the RGB values of the pixel through
-- through user registers
--
-- Revision:
-- Revision 1.1
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin RGB Control architecture
architecture Behavioral of Video_Box is
--Create Red, Blue, Green signals that contain the actual Red,
--Blue, and Green signals
signal red, blue, green : std_logic_vector(7 downto 0);
--Create the register controlled Red, Green, and Blue signals
signal lred, lblue, lgreen : std_logic_vector(7 downto 0);
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
--signal USER_LOGIC : std_logic_vector(23 downto 0);
constant N : integer := 16;
component blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component blk_mem_gen_0;
type rgb_array is array(0 to 255) of std_logic_vector(23 downto 0);
signal color_array : rgb_array := (
x"000000", x"800000", x"008000", x"808000", x"000080", x"800080", x"008080", x"C0C0C0", x"808080", x"FF0000", x"00FF00", x"FFFF00", x"0000FF", x"FF00FF", x"00FFFF", x"FFFFFF",
x"000000", x"00005F", x"000087", x"0000AF", x"0000D7", x"0000FF", x"005F00", x"005F5F", x"005F87", x"005FAF", x"005FD7", x"005FFF", x"008700", x"00875F", x"008787", x"0087AF",
x"0087D7", x"0087FF", x"00AF00", x"00AF5F", x"00AF87", x"00AFAF", x"00AFD7", x"00AFFF", x"00D700", x"00D75F", x"00D787", x"00D7AF", x"00D7D7", x"00D7FF", x"00FF00", x"00FF5F",
x"00FF87", x"00FFAF", x"00FFD7", x"00FFFF", x"5F0000", x"5F005F", x"5F0087", x"5F00AF", x"5F00D7", x"5F00FF", x"5F5F00", x"5F5F5F", x"5F5F87", x"5F5FAF", x"5F5FD7", x"5F5FFF",
x"5F8700", x"5F875F", x"5F8787", x"5F87AF", x"5F87D7", x"5F87FF", x"5FAF00", x"5FAF5F", x"5FAF87", x"5FAFAF", x"5FAFD7", x"5FAFFF", x"5FD700", x"5FD75F", x"5FD787", x"5FD7AF",
x"5FD7D7", x"5FD7FF", x"5FFF00", x"5FFF5F", x"5FFF87", x"5FFFAF", x"5FFFD7", x"5FFFFF", x"870000", x"87005F", x"870087", x"8700AF", x"8700D7", x"8700FF", x"875F00", x"875F5F",
x"875F87", x"875FAF", x"875FD7", x"875FFF", x"878700", x"87875F", x"878787", x"8787AF", x"8787D7", x"8787FF", x"87AF00", x"87AF5F", x"87AF87", x"87AFAF", x"87AFD7", x"87AFFF",
x"87D700", x"87D75F", x"87D787", x"87D7AF", x"87D7D7", x"87D7FF", x"87FF00", x"87FF5F", x"87FF87", x"87FFAF", x"87FFD7", x"87FFFF", x"AF0000", x"AF005F", x"AF0087", x"AF00AF",
x"AF00D7", x"AF00FF", x"AF5F00", x"AF5F5F", x"AF5F87", x"AF5FAF", x"AF5FD7", x"AF5FFF", x"AF8700", x"AF875F", x"AF8787", x"AF87AF", x"AF87D7", x"AF87FF", x"AFAF00", x"AFAF5F",
x"AFAF87", x"AFAFAF", x"AFAFD7", x"AFAFFF", x"AFD700", x"AFD75F", x"AFD787", x"AFD7AF", x"AFD7D7", x"AFD7FF", x"AFFF00", x"AFFF5F", x"AFFF87", x"AFFFAF", x"AFFFD7", x"AFFFFF",
x"D70000", x"D7005F", x"D70087", x"D700AF", x"D700D7", x"D700FF", x"D75F00", x"D75F5F", x"D75F87", x"D75FAF", x"D75FD7", x"D75FFF", x"D78700", x"D7875F", x"D78787", x"D787AF",
x"D787D7", x"D787FF", x"D7AF00", x"D7AF5F", x"D7AF87", x"D7AFAF", x"D7AFD7", x"D7AFFF", x"D7D700", x"D7D75F", x"D7D787", x"D7D7AF", x"D7D7D7", x"D7D7FF", x"D7FF00", x"D7FF5F",
x"D7FF87", x"D7FFAF", x"D7FFD7", x"D7FFFF", x"FF0000", x"FF005F", x"FF0087", x"FF00AF", x"FF00D7", x"FF00FF", x"FF5F00", x"FF5F5F", x"FF5F87", x"FF5FAF", x"FF5FD7", x"FF5FFF",
x"FF8700", x"FF875F", x"FF8787", x"FF87AF", x"FF87D7", x"FF87FF", x"FFAF00", x"FFAF5F", x"FFAF87", x"FFAFAF", x"FFAFD7", x"FFAFFF", x"FFD700", x"FFD75F", x"FFD787", x"FFD7AF",
x"FFD7D7", x"FFD7FF", x"FFFF00", x"FFFF5F", x"FFFF87", x"FFFFAF", x"FFFFD7", x"FFFFFF", x"080808", x"121212", x"1C1C1C", x"262626", x"303030", x"3A3A3A", x"444444", x"4E4E4E",
x"585858", x"606060", x"666666", x"767676", x"808080", x"8A8A8A", x"949494", x"9E9E9E", x"A8A8A8", x"B2B2B2", x"BCBCBC", x"C6C6C6", x"D0D0D0", x"DADADA", x"E4E4E4", x"EEEEEE"
);
signal RGB_IN_reg0, RGB_IN_reg1 : std_logic_vector(23 downto 0);
signal VDE_IN_reg0, VDE_IN_reg1 : std_logic;
signal HB_IN_reg0, HB_IN_reg1 : std_logic;
signal VB_IN_reg0, VB_IN_reg1 : std_logic;
signal HS_IN_reg0, HS_IN_reg1 : std_logic;
signal VS_IN_reg0, VS_IN_reg1 : std_logic;
signal ID_IN_reg0, ID_IN_reg1 : std_logic;
signal rgb_next : std_logic_vector(23 downto 0);
signal use_image : std_logic;
signal color_index, color_index_next : unsigned(7 downto 0);
signal image_index, image_index_next : unsigned(N-1 downto 0);
signal pixel : std_logic_vector(23 downto 0);
signal int_X_Coord_reg0, int_X_Coord_reg1 : unsigned(15 downto 0);
signal int_Y_Coord_reg0, int_Y_Coord_reg1 : unsigned(15 downto 0);
signal int_X_Orig_reg0, int_X_Orig_reg1 : unsigned(15 downto 0);
signal int_Y_Orig_reg0, int_Y_Orig_reg1 : unsigned(15 downto 0);
signal int_X_Coord : unsigned(15 downto 0);
signal int_Y_Coord : unsigned(15 downto 0);
signal int_X_Orig : unsigned(15 downto 0);
signal int_Y_Orig : unsigned(15 downto 0);
signal img_width : unsigned(15 downto 0);
signal img_height : unsigned(15 downto 0);
--signal din, dout : std_logic_vector(23 downto 0);
signal we, rden, wren : std_logic;
signal dout0, dout1 : std_logic_vector(7 downto 0);
signal rdaddr, wraddr : std_logic_vector(N-1 downto 0);
signal din : std_logic_vector(7 downto 0);
begin
--the user can edit the rgb values here
process(PIXEL_CLK)
begin
if(PIXEL_CLK'event and PIXEL_CLK='1') then
RGB_IN_reg0 <= RGB_IN_reg;
VDE_IN_reg0 <= VDE_IN_reg;
HS_IN_reg0 <= HS_IN_reg;
VS_IN_reg0 <= VS_IN_reg;
int_X_Coord_reg0 <= unsigned(X_Coord_reg);
int_Y_Coord_reg0 <= unsigned(Y_Coord_reg);
int_X_Orig_reg0 <= unsigned(slv_reg0(15 downto 0));
int_Y_Orig_reg0 <= unsigned(slv_reg1(15 downto 0));
RGB_IN_reg1 <= RGB_IN_reg0;
VDE_IN_reg1 <= VDE_IN_reg0;
HS_IN_reg1 <= HS_IN_reg0;
VS_IN_reg1 <= VS_IN_reg0;
int_X_Coord_reg1 <= int_X_Coord_reg0;
int_Y_Coord_reg1 <= int_Y_Coord_reg0;
int_X_Orig_reg1 <= int_X_Coord_reg0;
int_Y_Orig_reg1 <= int_Y_Coord_reg0;
image_index <= image_index_next;
end if;
end process;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= rgb_next;
VDE_OUT_reg <= VDE_IN_reg1;
HS_OUT_reg <= HS_IN_reg1;
VS_OUT_reg <= VS_IN_reg1;
end if;
end process;
-- process(S_AXI_ACLK) is
-- begin
-- if(rising_edge(S_AXI_ACLK)) then
wraddr <= slv_reg5(23 downto 8);
din <= slv_reg5(7 downto 0);
wren <= slv_reg_wren;
-- end if;
-- end process;
bram0: blk_mem_gen_0
port map(
clka => S_AXI_ACLK,
ena => wren,
wea(0) => we,
addra => wraddr,
dina => din,
clkb => PIXEL_CLK,
enb => rden,
addrb => rdaddr,
doutb => dout0
);
we <= '1';
rden <= '1';
rdaddr <= std_logic_vector(image_index);
-- Add user logic here
int_X_Coord <= int_X_Coord_reg1;
int_Y_Coord <= int_Y_Coord_reg1;
int_X_Orig <= unsigned(slv_reg0(15 downto 0));
int_Y_Orig <= unsigned(slv_reg1(15 downto 0));
img_width <= unsigned(slv_reg2(15 downto 0));
img_height <= unsigned(slv_reg3(15 downto 0));
use_image <= '1' when int_X_Coord >= int_X_Orig and
int_X_Coord < int_X_Orig + img_width and
int_Y_Coord >= int_Y_Orig and
int_Y_Coord < int_Y_Orig + img_height
else '0';
image_index_next <= (others => '0') when unsigned(X_Coord_reg) = int_X_Orig and unsigned(Y_Coord_reg) = int_Y_Orig and VDE_IN_reg='1' else
image_index + 1 when use_image = '1' and VDE_IN_reg='1' else
image_index;
--color_index <= unsigned(dout0) when image_index < 40960 else unsigned(dout1);
color_index <= unsigned(dout0);
pixel <= color_array(to_integer(color_index));
rgb_next <= pixel when use_image = '1' and std_logic_vector(color_index) /= slv_reg4(7 downto 0) else RGB_IN_reg1;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
-- Route the registers through
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg5 <= slv_reg4;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End RGB Control architecture
|
bsd-3-clause
|
840749a2ce16022ca4f0a3a0793985ba
| 0.592776 | 2.797719 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/hdl/mig_wrap_wrapper.vhd
| 1 | 9,828 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Wed Apr 05 00:15:23 2017
--Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
--Command : generate_target mig_wrap_wrapper.bd
--Design : mig_wrap_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_wrapper is
port (
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_cas_n : out STD_LOGIC;
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
SYS_CLK_clk_n : in STD_LOGIC;
SYS_CLK_clk_p : in STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_rst : in STD_LOGIC;
ui_addn_clk_0 : out STD_LOGIC;
ui_clk_sync_rst : out STD_LOGIC
);
end mig_wrap_wrapper;
architecture STRUCTURE of mig_wrap_wrapper is
component mig_wrap is
port (
DDR3_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_cas_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
SYS_CLK_clk_p : in STD_LOGIC;
SYS_CLK_clk_n : in STD_LOGIC;
ui_clk_sync_rst : out STD_LOGIC;
sys_rst : in STD_LOGIC;
ui_addn_clk_0 : out STD_LOGIC;
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_awready : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wvalid : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC
);
end component mig_wrap;
begin
mig_wrap_i: component mig_wrap
port map (
DDR3_addr(13 downto 0) => DDR3_addr(13 downto 0),
DDR3_ba(2 downto 0) => DDR3_ba(2 downto 0),
DDR3_cas_n => DDR3_cas_n,
DDR3_ck_n(0) => DDR3_ck_n(0),
DDR3_ck_p(0) => DDR3_ck_p(0),
DDR3_cke(0) => DDR3_cke(0),
DDR3_cs_n(0) => DDR3_cs_n(0),
DDR3_dm(7 downto 0) => DDR3_dm(7 downto 0),
DDR3_dq(63 downto 0) => DDR3_dq(63 downto 0),
DDR3_dqs_n(7 downto 0) => DDR3_dqs_n(7 downto 0),
DDR3_dqs_p(7 downto 0) => DDR3_dqs_p(7 downto 0),
DDR3_odt(0) => DDR3_odt(0),
DDR3_ras_n => DDR3_ras_n,
DDR3_reset_n => DDR3_reset_n,
DDR3_we_n => DDR3_we_n,
S00_AXI_araddr(31 downto 0) => S00_AXI_araddr(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
S00_AXI_arid(3 downto 0) => S00_AXI_arid(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
S00_AXI_arlock(0) => S00_AXI_arlock(0),
S00_AXI_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
S00_AXI_arready => S00_AXI_arready,
S00_AXI_arregion(3 downto 0) => S00_AXI_arregion(3 downto 0),
S00_AXI_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
S00_AXI_arvalid => S00_AXI_arvalid,
S00_AXI_awaddr(31 downto 0) => S00_AXI_awaddr(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_awburst(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_awcache(3 downto 0),
S00_AXI_awid(3 downto 0) => S00_AXI_awid(3 downto 0),
S00_AXI_awlen(7 downto 0) => S00_AXI_awlen(7 downto 0),
S00_AXI_awlock(0) => S00_AXI_awlock(0),
S00_AXI_awprot(2 downto 0) => S00_AXI_awprot(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_awqos(3 downto 0),
S00_AXI_awready => S00_AXI_awready,
S00_AXI_awregion(3 downto 0) => S00_AXI_awregion(3 downto 0),
S00_AXI_awsize(2 downto 0) => S00_AXI_awsize(2 downto 0),
S00_AXI_awvalid => S00_AXI_awvalid,
S00_AXI_bid(3 downto 0) => S00_AXI_bid(3 downto 0),
S00_AXI_bready => S00_AXI_bready,
S00_AXI_bresp(1 downto 0) => S00_AXI_bresp(1 downto 0),
S00_AXI_bvalid => S00_AXI_bvalid,
S00_AXI_rdata(31 downto 0) => S00_AXI_rdata(31 downto 0),
S00_AXI_rid(3 downto 0) => S00_AXI_rid(3 downto 0),
S00_AXI_rlast => S00_AXI_rlast,
S00_AXI_rready => S00_AXI_rready,
S00_AXI_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
S00_AXI_rvalid => S00_AXI_rvalid,
S00_AXI_wdata(31 downto 0) => S00_AXI_wdata(31 downto 0),
S00_AXI_wlast => S00_AXI_wlast,
S00_AXI_wready => S00_AXI_wready,
S00_AXI_wstrb(3 downto 0) => S00_AXI_wstrb(3 downto 0),
S00_AXI_wvalid => S00_AXI_wvalid,
SYS_CLK_clk_n => SYS_CLK_clk_n,
SYS_CLK_clk_p => SYS_CLK_clk_p,
interconnect_aresetn(0) => interconnect_aresetn(0),
peripheral_aresetn(0) => peripheral_aresetn(0),
sys_rst => sys_rst,
ui_addn_clk_0 => ui_addn_clk_0,
ui_clk_sync_rst => ui_clk_sync_rst
);
end STRUCTURE;
|
mit
|
f038df04e870c070dccde2d5c4bd79a1
| 0.608974 | 2.847045 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/shifter.vhd
| 16 | 3,063 |
---------------------------------------------------------------------
-- TITLE: Shifter Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- Matthias Gruenewald
-- DATE CREATED: 2/2/01
-- FILENAME: shifter.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the 32-bit shifter unit.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity shifter is
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end; --entity shifter
architecture logic of shifter is
-- type shift_function_type is (
-- shift_nothing, shift_left_unsigned,
-- shift_right_signed, shift_right_unsigned);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
begin
fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED
and value(31) = '1'
else "0000000000000000";
shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else
ZERO;
end generate;
AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
|
mit
|
728b7b421d04cf7a7e25ff302a86c2ba
| 0.622592 | 3.388274 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_timer_axi4_read_cntrl.vhd
| 1 | 5,286 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 31, 2017
--! @brief Contains the entity and architecture of the
--! Timer Core's Slave AXI4-Lite Read Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_timer_pack.all;
--! The Read Controller implements a Slave AXI4-Lite Read
--! interface in order to allow a Master interface to read from
--! the registers of the core.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_timer_axi4_read_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Register interface.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_trig_value_offset : std_logic_vector := X"0004"; --! Defines the offset for the Trigger Value.
reg_tick_value_offset : std_logic_vector := X"0008" --! Defines the offset for the Tick Value.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- Register interface.
reg_control : in std_logic_vector(axi_data_width-1 downto 0); --! Control regster.
reg_trig_value : in std_logic_vector(axi_data_width-1 downto 0); --! Trigger Value register.
reg_tick_value : in std_logic_vector(axi_data_width-1 downto 0)); --! Tick Value register.
end plasoc_timer_axi4_read_cntrl;
architecture Behavioral of plasoc_timer_axi4_read_cntrl is
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal axi_araddr_buff : std_logic_vector(axi_address_width-1 downto 0);
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
-- Drive the axi read interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Wait for handshake,
if axi_arvalid='1' and axi_arready_buff='1' then
-- Prevent the master from sending any more control information.
axi_arready_buff <= '0';
-- Sample the address sent from the master.
axi_araddr_buff <= axi_araddr;
state <= state_read;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_arready_buff <= '1';
end if;
-- READ mode.
when state_read=>
-- Wait for handshake,
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
-- Set the data and let the master know it's available.
else
axi_rvalid_buff <= '1';
-- Send data according to the bufferred address.
if axi_araddr_buff=reg_control_offset then
axi_rdata <= reg_control;
elsif axi_araddr_buff=reg_trig_value_offset then
axi_rdata <= reg_trig_value;
elsif axi_araddr_buff=reg_tick_value_offset then
axi_rdata <= reg_tick_value;
else
axi_rdata <= (others=>'0');
end if;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
448bab4c95e3b35612e074e60656d75f
| 0.530647 | 4.339901 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bram.vhd
| 3 | 6,275 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.main_pack.all;
use work.jump_pack.all;
use work.boot_pack.all;
--! The Single Port BRAM is effectively defined as an array the
--! compiler can infer as Block RAM. This methodology is useful for verification
--! purposes since the contents of the array can be observed while in simulation.
--! Moreover, binary can be loaded into the BRAM during static elaboration prior
--! to synthesis, allowing the BRAM to be initialized with a bootloader application
--! for hardware deployment.
--!
--! One out of three types of binary can be statically loaded into the BRAM. The first
--! of which is the Jump binary, whose purpose is to make the Plasma-SoC's CPU jump
--! to a particular place in memory. The Jump binary was made so that the Bootloader
--! binary can be bypassed in simulation, allowing the Main binary to begin its execution
--! faster. The second binary is the Bootloader. The purpose of the Bootloader is to load
--! the Main application into memory and then cause the CPU to jump to the starting address
--! of the Main application. Finally, the Main binary is the application under test. Unlike
--! the Jump and Boot binaries, the Main binary can be located at an address other than 0 if
--! compiled and linked correctly. The Jump and Bootloader binaries need to be built such that
--! they are aware where the Main binary is located and needs to go, respectively.
--!
--! Alternatively, the BRAM can be initialized to zero; in other words, without any binary.
--!
--! It is recommended to read over the documentation presented in the corresponding C sources
--! to learn more about these applications.
entity bram is
generic (
select_app : string := "none"; --! Selects the binary to statically load. "none" refers to no binary. "jump" refers to the Jump binary. "boot" refers to the Bootloader binary. "main" refers to the Main application.
address_width : integer := 18; --! Defines the address width.
data_width : integer := 32; --! Defines the data width.
bram_depth : integer := 65536 --! Defines the size of the BRAM in the number of words.
);
port(
bram_rst_a : in std_logic; --! High reset. Since the binary is loaded statically, this reset effectively behaves like another bram_en_a.
bram_clk_a : in std_logic; --! Clock that synchronizes the BRAM's operation.
bram_en_a : in std_logic; --! Enables the BRAM when high.
bram_we_a : in std_logic_vector(data_width/8-1 downto 0); --! Each high bit allows the respective byte in bram_wrdata_a to be written into the BRAM.
bram_addr_a : in std_logic_vector(address_width-1 downto 0); --! Specifies the BRAM's location where the memory access operation will occur on the next positive edge clock cycle. Should be a multiple of (2**address_width)/(data_width/8) and less than bram_depth*(data_width/8).
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0); --! The data that will be written on the next positive edge clock cycle provided that bram_rst_a is low, bram_en_a is high, and at least one bit in bram_we_a is high.
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0') --! The data that will be read on the next positive edge clock cycle provided that bram_rst_a is low and bram_en_a is high.
);
end bram;
architecture Behavioral of bram is
constant bytes_per_word : integer := data_width/8;
type bram_buff_type is array (0 to bram_depth-1) of std_logic_vector(data_width-1 downto 0);
function load_selected_app return bram_buff_type is
variable bram_buff : bram_buff_type := (others=>(others=>'0'));
variable boot_buff : work.boot_pack.ram_type;
variable jump_buff : work.jump_pack.ram_type;
variable main_buff : work.main_pack.ram_type;
begin
case select_app is
when "none"=>
when "main"=>
main_buff := work.main_pack.load_hex;
for each_word in 0 to work.main_pack.ram_size-1 loop
bram_buff(each_word) := main_buff(each_word);
end loop;
when "jump"=>
jump_buff := work.jump_pack.load_hex;
for each_word in 0 to work.jump_pack.ram_size-1 loop
bram_buff(each_word) := jump_buff(each_word);
end loop;
when "boot"=>
boot_buff := work.boot_pack.load_hex;
for each_word in 0 to work.boot_pack.ram_size-1 loop
bram_buff(each_word) := boot_buff(each_word);
end loop;
when others=>
assert false report "Incorrect option for select_app" severity error;
end case;
return bram_buff;
end;
signal bram_buff : bram_buff_type := load_selected_app;
begin
process (bram_clk_a)
variable base_index : integer;
begin
if rising_edge(bram_clk_a) then
if bram_rst_a='0' then
if bram_en_a='1' then
base_index := to_integer(unsigned(bram_addr_a))/bytes_per_word;
for each_byte in 0 to bytes_per_word-1 loop
if bram_we_a(each_byte)='1' then
bram_buff(base_index)(each_byte*8+7 downto each_byte*8) <=
bram_wrdata_a(each_byte*8+7 downto each_byte*8);
end if;
end loop;
bram_rddata_a <= bram_buff(base_index);
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
566b5716f8e67d28730e83c2119d5b5b
| 0.610359 | 4.21707 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_rd_sf.vhd
| 4 | 75,596 |
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
bsd-3-clause
|
b26fa3c8ea81c308ffb70c73f67bfde8
| 0.425578 | 4.843724 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/xip_cross_clk_sync.vhd
| 2 | 55,840 |
-------------------------------------------------------------------------------
-- xip_cross_clk_sync.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
-------------------------------------------------------------------------------
-- Filename: xip_cross_clk_sync.vhd
-- Version: v3.0
-- Description: This is the CDC file for XIP mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Created second version of the core.
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity xip_cross_clk_sync is
generic (
C_S_AXI4_DATA_WIDTH : integer;
C_SPI_MEM_ADDR_BITS : integer;
Async_Clk : integer ;
C_NUM_SS_BITS : integer
);
port (
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESET : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
spiXfer_done_cdc_from_spi : in std_logic;
spiXfer_done_cdc_to_axi_1 : out std_logic;
----------------------------
mst_modf_err_cdc_from_spi : in std_logic;
mst_modf_err_cdc_to_axi : out std_logic;
mst_modf_err_cdc_to_axi4 : out std_logic;
----------------------------
one_byte_xfer_cdc_from_axi : in std_logic;
one_byte_xfer_cdc_to_spi : out std_logic;
----------------------
two_byte_xfer_cdc_from_axi : in std_logic;
two_byte_xfer_cdc_to_spi : out std_logic;
----------------------
four_byte_xfer_cdc_from_axi : in std_logic;
four_byte_xfer_cdc_to_spi : out std_logic;
----------------------
Transmit_Addr_cdc_from_axi : in std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
Transmit_Addr_cdc_to_spi : out std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
----------------------
load_cmd_cdc_from_axi : in std_logic;
load_cmd_cdc_to_spi : out std_logic;
--------------------------
CPOL_cdc_from_axi : in std_logic;
CPOL_cdc_to_spi : out std_logic;
--------------------------
CPHA_cdc_from_axi : in std_logic;
CPHA_cdc_to_spi : out std_logic;
--------------------------
SS_cdc_from_axi : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_cdc_to_spi : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
--------------------------
type_of_burst_cdc_from_axi : in std_logic;-- _vector(1 downto 0);
type_of_burst_cdc_to_spi : out std_logic;-- _vector(1 downto 0);
--------------------------
axi_length_cdc_from_axi : in std_logic_vector(7 downto 0);
axi_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
dtr_length_cdc_from_axi : in std_logic_vector(7 downto 0);
dtr_length_cdc_to_spi : out std_logic_vector(7 downto 0);
--------------------------
load_axi_data_cdc_from_axi : in std_logic;
load_axi_data_cdc_to_spi : out std_logic;
------------------------------
Rx_FIFO_Full_cdc_from_spi : in std_logic;
Rx_FIFO_Full_cdc_to_axi : out std_logic;
Rx_FIFO_Full_cdc_to_axi4 : out std_logic;
------------------------------
wb_hpm_done_cdc_from_spi : in std_logic;
wb_hpm_done_cdc_to_axi : out std_logic
);
end entity xip_cross_clk_sync;
-------------------------------------------------------------------------------
architecture imp of xip_cross_clk_sync is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
signal size_length_cdc_to_spi_d1 : std_logic_vector(1 downto 0);
signal size_length_cdc_to_spi_d2 : std_logic_vector(1 downto 0);
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2 : std_logic;
signal spiXfer_done_d3 : std_logic;
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal byte_xfer_cdc_from_axi_d1 : std_logic;
signal byte_xfer_cdc_from_axi_d2 : std_logic;
signal hw_xfer_cdc_from_axi_d1 : std_logic;
signal hw_xfer_cdc_from_axi_d2 : std_logic;
signal word_xfer_cdc_from_axi_d1 : std_logic;
signal word_xfer_cdc_from_axi_d2 : std_logic;
signal SS_cdc_from_spi_d1 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_cdc_from_spi_d2 : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal mst_modf_err_d1 : std_logic;
signal mst_modf_err_d2 : std_logic;
signal mst_modf_err_d3 : std_logic;
signal mst_modf_err_d4 : std_logic;
signal dtr_length_cdc_from_axi_d1 : std_logic_vector(7 downto 0);
signal dtr_length_cdc_from_axi_d2 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d1 : std_logic_vector(7 downto 0);
signal axi_length_cdc_to_spi_d2 : std_logic_vector(7 downto 0);
signal CPOL_cdc_to_spi_d1 : std_logic;
signal CPOL_cdc_to_spi_d2 : std_logic;
signal CPHA_cdc_to_spi_d1 : std_logic;
signal CPHA_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d1 : std_logic;
signal load_axi_data_cdc_to_spi_d2 : std_logic;
signal load_axi_data_cdc_to_spi_d3 : std_logic;
signal Transmit_Addr_cdc_from_axi_d1 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal Transmit_Addr_cdc_from_axi_d2 : std_logic_vector(C_SPI_MEM_ADDR_BITS-1 downto 0);
signal type_of_burst_cdc_to_spi_d1 : std_logic;-- _vector(1 downto 0);
signal type_of_burst_cdc_to_spi_d2 : std_logic;-- _vector(1 downto 0);
signal load_cmd_cdc_from_axi_d1 : std_logic;
signal load_cmd_cdc_from_axi_d2 : std_logic;
signal load_cmd_cdc_from_axi_d3 : std_logic;
signal load_cmd_cdc_from_axi_int_2 : std_logic;
signal rx_fifo_full_d1 : std_logic;
signal rx_fifo_full_d2 : std_logic;
signal rx_fifo_full_d3 : std_logic;
signal rx_fifo_full_d4 : std_logic;
signal ld_axi_data_cdc_from_axi_int_2 : std_logic;
signal wb_hpm_done_cdc_from_spi_d1 : std_logic;
signal wb_hpm_done_cdc_from_spi_d2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of XFER_DONE_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of MST_MODF_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of BYTE_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of HW_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of WORD_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of TYP_OF_XFER_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_AXI_DATA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of LD_CMD_SYNC_AXI2SPI : label is "TRUE";
-- -- attribute ASYNC_REG of TRANSMIT_DATA_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of CPOL_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of CPHA_SYNC_AXI2SPI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI : label is "TRUE";
-- attribute ASYNC_REG of Rx_FIFO_Full_SYNC_SPI2AXI4 : label is "TRUE";
-- attribute ASYNC_REG of WB_HPM_DONE_SYNC_SPI2AXI : label is "TRUE";
attribute KEEP : string;
attribute KEEP of SS_cdc_from_spi_d2 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d3 : signal is "TRUE";
attribute KEEP of load_axi_data_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of type_of_burst_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of rx_fifo_full_d2 : signal is "TRUE";
attribute KEEP of CPHA_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of CPOL_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of Transmit_Addr_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d3 : signal is "TRUE";
attribute KEEP of load_cmd_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of word_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of hw_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of byte_xfer_cdc_from_axi_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d2 : signal is "TRUE";
attribute KEEP of mst_modf_err_d4 : signal is "TRUE";
attribute KEEP of spiXfer_done_d2 : signal is "TRUE";
attribute KEEP of spiXfer_done_d3 : signal is "TRUE";
attribute KEEP of axi_length_cdc_to_spi_d2 : signal is "TRUE";
attribute KEEP of dtr_length_cdc_from_axi_d2 : signal is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
LOGIC_GENERATION_FDR : if (Async_Clk = 0) generate
-----
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => S_AXI4_ACLK,
D => spiXfer_done_cdc_from_spi_int_2,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => S_AXI4_ACLK,
D => spiXfer_done_d1,
R => S_AXI4_ARESET
);
FER_DONE_SYNC_SPI2AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => S_AXI4_ACLK,
D => spiXfer_done_d2,
R => S_AXI4_ARESET
);
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d1,
C => S_AXI_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI_ARESETN
);
MST_MODF_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d2,
C => S_AXI_ACLK,
D => mst_modf_err_d1,
R => S_AXI_ARESETN
);
mst_modf_err_cdc_to_axi <= mst_modf_err_d2;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d3,
C => S_AXI4_ACLK,
D => mst_modf_err_cdc_from_spi,
R => S_AXI4_ARESET
);
MST_MODF_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => mst_modf_err_d4,
C => S_AXI4_ACLK,
D => mst_modf_err_d3,
R => S_AXI4_ARESET
);
mst_modf_err_cdc_to_axi4 <= mst_modf_err_d4;
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => one_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
BYTE_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => byte_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => byte_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
one_byte_xfer_cdc_to_spi <= byte_xfer_cdc_from_axi_d2;
------------------------------------------------
HW_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => two_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
HW_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => hw_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => hw_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
two_byte_xfer_cdc_to_spi <= hw_xfer_cdc_from_axi_d2;
------------------------------------------------
WORD_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => four_byte_xfer_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
WORD_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => word_xfer_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => word_xfer_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
four_byte_xfer_cdc_to_spi <= word_xfer_cdc_from_axi_d2;
------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
-------------------------------------
-- from AXI4 to SPI
LD_CMD_SYNC_AXI2SPI: component FDR
port map (
Q => load_cmd_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_1: component FDR
port map (
Q => load_cmd_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_CMD_SYNC_AXI2SPI_2: component FDR
port map (
Q => load_cmd_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => load_cmd_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
--------------------------------------------------------------------------
-- from AXI4 to SPI
TRANS_ADDR_SYNC_GEN: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TRANS_ADDR_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Transmit_Addr_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => Transmit_Addr_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TRANS_ADDR_SYNC_GEN;
-- Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2; -- 4/19/2013
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d1; -- 4/19/2013
------------------------------------------------
-- from AXI4 Lite to SPI
CPOL_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPOL_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPOL_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPOL_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPOL_cdc_to_spi <= CPOL_cdc_to_spi_d2;
------------------------------------------------
-- from AXI4 Lite to SPI
CPHA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
CPHA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => CPHA_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => CPHA_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
CPHA_cdc_to_spi <= CPHA_cdc_to_spi_d2;
------------------------------------------------
LD_AXI_DATA_STRETCH: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
-------------------------------------
LD_AXI_DATA_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => ld_axi_data_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
LD_AXI_DATA_SYNC_AXI2SPI_2: component FDR
generic map(INIT => '0'
)port map (
Q => load_axi_data_cdc_to_spi_d3,
C => EXT_SPI_CLK,
D => load_axi_data_cdc_to_spi_d2,
R => Rst_from_axi_cdc_to_spi
);
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
------------------------------------------------
SS_SYNC_AXI_SPI_GEN: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
SS_SYNC_AXI2SPI_CDC: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d1(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SS_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => SS_cdc_from_spi_d2(i),
C => EXT_SPI_CLK,
D => SS_cdc_from_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SS_SYNC_AXI_SPI_GEN;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d1,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
TYP_OF_XFER_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '0'
)port map (
Q => type_of_burst_cdc_to_spi_d2,
C => EXT_SPI_CLK,
D => type_of_burst_cdc_to_spi_d1,
R => Rst_from_axi_cdc_to_spi
);
--end generate TYP_OF_XFER_GEN;
------------------------------
type_of_burst_cdc_to_spi <= type_of_burst_cdc_to_spi_d2;
------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
AXI_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d1(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
AXI_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => axi_length_cdc_to_spi_d2(i),
C => EXT_SPI_CLK,
D => axi_length_cdc_to_spi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
DTR_LEN_SYNC_AXI2SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => dtr_length_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => dtr_length_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
-- from SPI to AXI Lite
Rx_FIFO_Full_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d1,
C => S_AXI_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d2,
C => S_AXI_ACLK,
D => rx_fifo_full_d1,
R => S_AXI_ARESETN
);
Rx_FIFO_Full_cdc_to_axi <= rx_fifo_full_d2;
-------------------------------------------------------------------------------
-- from SPI to AXI4
Rx_FIFO_Full_SYNC_SPI2AXI4: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d3,
C => S_AXI4_ACLK,
D => Rx_FIFO_Full_cdc_from_spi,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_SYNC_SPI2AXI4_1: component FDR
generic map(INIT => '0'
)port map (
Q => rx_fifo_full_d4,
C => S_AXI4_ACLK,
D => rx_fifo_full_d3,
R => S_AXI4_ARESET
);
Rx_FIFO_Full_cdc_to_axi4 <= rx_fifo_full_d4;
-------------------------------------------------------------------------------
-- from SPI to AXI4
WB_HPM_DONE_SYNC_SPI2AXI: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d1,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi,
R => S_AXI4_ARESET
);
WB_HPM_DONE_SYNC_SPI2AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => wb_hpm_done_cdc_from_spi_d2,
C => S_AXI4_ACLK,
D => wb_hpm_done_cdc_from_spi_d1,
R => S_AXI4_ARESET
);
wb_hpm_done_cdc_to_axi <= wb_hpm_done_cdc_from_spi_d2;
-------------------------------------------------------------------------------
end generate LOGIC_GENERATION_FDR;
LOGIC_GENERATION_CDC : if (Async_Clk = 1) generate
-------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
--spiXfer_done_d1 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor spiXfer_done_cdc_from_spi_int_2;
--spiXfer_done_d1 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
XFER_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d1 ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => spiXfer_done_d2
);
SPI_XFER_DONE_STRETCH_1_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK= '1') then
if(S_AXI4_ARESET = '1') then
spiXfer_done_d3 <= '0';
else
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
spiXfer_done_cdc_to_axi_1 <= spiXfer_done_d2 xor spiXfer_done_d3;
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI_ARESETN ,
scndry_out => mst_modf_err_cdc_to_axi
);
-------------------------------------------------------------------------------
MST_MODF_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => mst_modf_err_cdc_from_spi ,
scndry_aclk => S_AXI4_ACLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => S_AXI4_ARESET ,
scndry_out => mst_modf_err_cdc_to_axi4
);
-------------------------------------------------------------------------------
BYTE_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => one_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => one_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
HW_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => two_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => two_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
WORD_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => four_byte_xfer_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => four_byte_xfer_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_CMD_cdc_from_AXI_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
load_cmd_cdc_from_axi_int_2 <= '0';
--load_cmd_cdc_from_axi_d1 <= '0';
else
load_cmd_cdc_from_axi_int_2 <= load_cmd_cdc_from_axi xor load_cmd_cdc_from_axi_int_2;
--load_cmd_cdc_from_axi_d1 <= load_cmd_cdc_from_axi_int_2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH_CDC;
LD_CMD_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => load_cmd_cdc_from_axi_int_2,--load_cmd_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_cmd_cdc_from_axi_d2
);
LD_CMD_cdc_from_AXI_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_cmd_cdc_from_axi_d3 <= '0';
else
load_cmd_cdc_from_axi_d3 <= load_cmd_cdc_from_axi_d2;
end if;
end if;
end process LD_CMD_cdc_from_AXI_STRETCH;
load_cmd_cdc_to_spi <= load_cmd_cdc_from_axi_d3 xor
load_cmd_cdc_from_axi_d2;
-------------------------------------------------------------------------------
TRANS_ADDR_SYNC_GEN_CDC: for i in C_SPI_MEM_ADDR_BITS-1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TRANS_ADDR_SYNC_AXI2SPI_CDC : label is "TRUE";
-----
begin
-----
TRANS_ADDR_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => Transmit_Addr_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => Transmit_Addr_cdc_from_axi_d2(i)
);
end generate TRANS_ADDR_SYNC_GEN_CDC;
Transmit_Addr_cdc_to_spi <= Transmit_Addr_cdc_from_axi_d2;
-------------------------------------------------------------------------------
CPOL_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPOL_cdc_to_spi
);
-------------------------------------------------------------------------------
CPHA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => CPHA_cdc_to_spi
);
-------------------------------------------------------------------------------
LD_AXI_DATA_STRETCH_CDC: process(S_AXI4_ACLK)is
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1')then
if(S_AXI4_ARESET = '1')then
ld_axi_data_cdc_from_axi_int_2 <= '0';
--load_axi_data_cdc_to_spi_d1 <= '0';
else
ld_axi_data_cdc_from_axi_int_2 <= load_axi_data_cdc_from_axi xor
ld_axi_data_cdc_from_axi_int_2;
-- load_axi_data_cdc_to_spi_d1 <= ld_axi_data_cdc_from_axi_int_2;
end if;
end if;
end process LD_AXI_DATA_STRETCH_CDC;
LD_AXI_DATA_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 1 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => ld_axi_data_cdc_from_axi_int_2,--load_axi_data_cdc_to_spi_d1 ,
prmry_vect_in => (others => '0' ),
scndry_aclk => EXT_SPI_CLK ,
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => load_axi_data_cdc_to_spi_d2
);
LD_AXI_DATA_STRETCH: process(EXT_SPI_CLK)is
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK = '1')then
if(Rst_from_axi_cdc_to_spi = '1')then
load_axi_data_cdc_to_spi_d3 <= '0';
else
load_axi_data_cdc_to_spi_d3 <= load_axi_data_cdc_to_spi_d2 ;
end if;
end if;
end process LD_AXI_DATA_STRETCH;
load_axi_data_cdc_to_spi <= load_axi_data_cdc_to_spi_d3 xor load_axi_data_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
SS_SYNC_AXI_SPI_GEN_CDC: for i in (C_NUM_SS_BITS-1) downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of SS_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
SS_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => SS_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
scndry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => (others => '0' ),
scndry_out => SS_cdc_from_spi_d2(i)
);
end generate SS_SYNC_AXI_SPI_GEN_CDC;
SS_cdc_to_spi <= SS_cdc_from_spi_d2;
------------------------------------------------------------------------------------------
TYP_OF_XFER_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => type_of_burst_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => type_of_burst_cdc_to_spi
);
---------------------------------------------------------------------------------------
AXI_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of AXI_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-------------
AXI_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => axi_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => axi_length_cdc_to_spi_d2(i)
);
end generate AXI_LEN_SYNC_AXI_SPI_GEN_CDC;
axi_length_cdc_to_spi <= axi_length_cdc_to_spi_d2;
---------------------------------------------------------------------------------------
DTR_LEN_SYNC_AXI_SPI_GEN_CDC: for i in 7 downto 0 generate
---------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of DTR_LEN_SYNC_AXI2SPI_CDC : label is "TRUE";
begin
-----
DTR_LEN_SYNC_AXI2SPI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_in => dtr_length_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => dtr_length_cdc_from_axi_d2(i)
);
end generate DTR_LEN_SYNC_AXI_SPI_GEN_CDC;
dtr_length_cdc_to_spi <= dtr_length_cdc_from_axi_d2;
------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI_ACLK ,
prmry_resetn => S_AXI_ARESETN ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI_ACLK ,
scndry_resetn => S_AXI_ARESETN ,
scndry_out => Rx_FIFO_Full_cdc_to_axi
);
------------------------------------------------------------------------
Rx_FIFO_Full_SYNC_SPI2AXI4_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => Rx_FIFO_Full_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => Rx_FIFO_Full_cdc_to_axi4
);
-------------------------------------------------------------------------------
WB_HPM_DONE_SYNC_SPI2AXI_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => S_AXI4_ACLK ,
prmry_resetn => S_AXI4_ARESET ,
prmry_in => wb_hpm_done_cdc_from_spi ,
prmry_vect_in => (others => '0' ),
scndry_aclk => S_AXI4_ACLK ,
scndry_resetn => S_AXI4_ARESET ,
scndry_out => wb_hpm_done_cdc_to_axi
);
-------------------------------------------------------------------------------
byte_xfer_cdc_from_axi_d2 <= '0' ;
hw_xfer_cdc_from_axi_d2 <= '0' ;
word_xfer_cdc_from_axi_d2 <= '0' ;
mst_modf_err_d2 <= '0' ;
mst_modf_err_d4 <= '0' ;
CPOL_cdc_to_spi_d2 <= '0' ;
CPHA_cdc_to_spi_d2 <= '0' ;
type_of_burst_cdc_to_spi_d2 <= '0' ;
rx_fifo_full_d2 <= '0' ;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
---------------------
|
bsd-3-clause
|
7ea10bce8cffc27be8d9cb23923d6bd1
| 0.420433 | 3.850238 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_bram18k_v3_0_1/hdl/xbip_bram18k_v3_0.vhd
| 1 | 9,340 |
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`protect end_protected
|
apache-2.0
|
0785148eff871daffb1c6ecfb03efc60
| 0.916595 | 1.949896 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_cpu_l1_cache_cntrl.vhd
| 1 | 29,101 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 13, 2017
--! @brief Contains the entity and architecture of the
--! CPU's Write-Back Cache Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_cpu_pack.all;
--! The CPU's Cache Controller is implemented generically
--! to support cacheable addresses starting from address 0,
--! configurable way width, configurable cache size, configurable
--! block size, and configurable replacement policies. The addresses
--! needed to initiate the flushing and invalidation operations can
--! also be changed.
--!
--! The interfaces of the Cache Controller consist of global,
--! CPU, and Memory. Global refers to the clock and reset on
--! low signals. The CPU interface is intended to connect to the CPU
--! defined in the Plasma-SoC. However, in theory the Cache Controller
--! can be adapted to other CPU's so long as the same communication protocol
--! is followed. The same idea is applicable to the Memory interface, which
--! of course needs to connect to the corresponding Memory Controller.
entity plasoc_cpu_l1_cache_cntrl is
generic (
cpu_address_width : integer := 32; --! Defines the address width of the CPU.
cpu_data_width : integer := 32; --! Defines the data width of the CPU.
cache_cacheable_width : integer := 16; --! Defines the cacheable range. All addresses for which the most cpu_address_width-cache_cacheable_width significant bits are all zero are cacheable.
cache_way_width : integer := 1; --! Defines the association of the cache. If zero, the cache is direct. In other words, 2**cache_index_width way.
cache_index_width : integer := 4; --! Defines the size of the cache. In other words, the number of rows --- where each row consists of a set of tag and block pairs --- in the cache is 2**cache_index_width.
cache_offset_width : integer := 5; --! Defines the size of each block. In other words, the number of bytes in a block is 2**cache_offset_width.
cache_policy : string := "rr"; --! Defines the replacement policy. "rr" is Random Replacement. "plru" is Pseudo Recently Used.
oper_base : std_logic_vector := X"200000"; --! Defines the base address of the cache flushing and invalidation operations. The base address specifies the most significant bits.
oper_invalidate_offset : std_logic_vector := X"00"; --! Defines the invalidation offset from the base address. Provided that the requested line is in the cache, invalidation resets the corresponding valid it.
oper_flush_offset : std_logic_vector := X"04" --! Defines the flushing offset from the base address. Provided that the requested line is in the cache, flushing writes the line back into its corresponding location in memory.
);
port (
clock : in std_logic; --! Clock. Tested with 50 MHz.
resetn : in std_logic; --! Reset on low.
cpu_next_address : in std_logic_vector(cpu_address_width-1 downto 0); --! The address of the next word that needs to be written into memory on the next positive edge clock cycle.
cpu_write_data : in std_logic_vector(cpu_data_width-1 downto 0); --! The word that is written on the next positive edge clock cycle.
cpu_write_enables : in std_logic_vector(cpu_data_width/8-1 downto 0); --! Each high bit indicates the respective byte in cpu_write_data should be written.
cpu_read_data : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! The word that is read from memory on the next positive edge clock cycle.
cpu_pause : out std_logic; --! Forces the CPU to stall in case cpu_next_address isn't accessible on the next positive edge clock cycle.
memory_write_address : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0'); --! The starting address of a memory write operation.
memory_write_data : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! The word that is written to memory when a handshake occurs on a positive edge clock cyle.
memory_write_enable : out std_logic; --! Enables the burst writing operation to memory.
memory_write_enables : out std_logic_vector(cpu_data_width/8-1 downto 0) := (others=>'0'); --! Each high bit corresponds to a respective byte in memory_write_data to write to memory.
memory_write_valid : out std_logic; --! Handshaking signal indicating the word on memory_write_data is valid.
memory_write_ready : in std_logic; --! Handshaking signal indicating the potential word on memory_write_data is ready to be accepted.
memory_read_address : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0'); --! The address of the next word that needs to be read from memory on the next positive edge clock cycle.
memory_read_enable : out std_logic; --! Enables the burst reading operation from memory.
memory_read_data: in std_logic_vector(cpu_data_width-1 downto 0); --! The word that is read from memory when a handshake occurs on a positive edge clock cyle.
memory_read_valid : in std_logic; --! Handshaking signal indicating the word on memory_read_data is valid.
memory_read_ready : out std_logic; --! Handshaking signal indicating the potential word on memory_read_data is ready to be accepted.
memory_cacheable : out std_logic --! Indicates whether the enabled memory access operations are cacheable --- indicating a burst operation of 2**cache_offset_width/(cpu_data_width/8) words is needed --- or noncacheable --- burst size of a single word.
);
end plasoc_cpu_l1_cache_cntrl;
architecture Behavioral of plasoc_cpu_l1_cache_cntrl is
constant tag_width : integer := cache_cacheable_width-cache_index_width-cache_offset_width;
constant block_word_width : integer := cache_offset_width-clogb2(cpu_data_width/8);
constant oper_base_width : integer := oper_base'length;
constant oper_offset_width : integer := oper_invalidate_offset'length;
function plru_width return integer is
variable result : integer := 0;
begin
if cache_way_width/=0 then
for each_way in 1 to 2**cache_way_width/2 loop
result := result+each_way;
end loop;
end if;
return result;
end;
constant rr_lfsr_width : integer := 16;
type block_rows_type is array(0 to 2**cache_index_width-1) of std_logic_vector(2**cache_way_width*2**cache_offset_width*8-1 downto 0);
type tag_rows_type is array(0 to 2**cache_index_width-1) of std_logic_vector(2**cache_way_width*tag_width-1 downto 0);
type valid_rows_type is array(0 to 2**cache_index_width-1) of std_logic_vector(2**cache_way_width-1 downto 0);
type plru_rows_type is array(0 to 2**cache_index_width-1) of std_logic_vector(plru_width-1 downto 0);
type memory_access_mode_type is (msm_read_block,msm_write_block,msm_exchange_block,msm_write_word,msm_read_word);
signal block_rows : block_rows_type := (others=>(others=>'0'));
signal tag_rows : tag_rows_type := (others=>(others=>'0'));
signal valid_rows : valid_rows_type := (others=>(others=>'0'));
signal plru_rows : plru_rows_type := (others=>(others=>'0'));
signal cpu_tag : std_logic_vector(tag_width-1 downto 0) := (others=>'0');
signal cpu_index : integer range 0 to 2**cache_index_width-1 := 0;
signal cpu_offset : integer range 0 to 2**cache_offset_width-1 := 0;
signal cpu_way : integer range 0 to 2**cache_way_width-1 := 0;
signal cpu_hit : Boolean := False;
signal cpu_cacheable : Boolean := False;
signal cpu_pause_buff : std_logic := '0';
signal replace_plru : std_logic_vector(plru_width-1 downto 0);
signal replace_way : integer range 0 to 2**cache_way_width-1 := 0;
signal replace_write_enables : std_logic_vector(cpu_data_width/8-1 downto 0) := (others=>'0');
signal replace_write_data : std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0');
signal replace_offset : integer range 0 to 2**cache_offset_width-1 := 0;
signal memory_prepared : Boolean := False;
signal memory_way : integer range 0 to 2**cache_way_width-1 := 0;
signal memory_access_needed : Boolean := False;
signal memory_access_mode : memory_access_mode_type := msm_read_block;
signal memory_write_counter : integer range 0 to 2**block_word_width-1 := 0;
signal memory_read_counter : integer range 0 to 2**block_word_width-1 := 0;
signal memory_write_enable_buff : std_logic := '0';
signal memory_read_enable_buff : std_logic := '0';
signal memory_write_valid_buff : std_logic := '0';
signal memory_read_ready_buff : std_logic := '0';
signal memory_index : integer range 0 to 2**cache_index_width-1 := 0;
signal oper_request : Boolean := False;
signal oper_request_invalidate : Boolean := False;
signal oper_request_flush : Boolean := False;
signal oper_started : Boolean := False;
signal oper_started_invalidate : Boolean := False;
signal oper_started_flush : Boolean := False;
signal rr_lfsr : std_logic_vector(rr_lfsr_width-1 downto 0) := X"ace1";
-- attribute keep : boolean;
-- attribute keep of cpu_next_address : signal is true;
-- attribute keep of cpu_write_data : signal is true;
-- attribute keep of cpu_write_enables : signal is true;
-- attribute keep of cpu_read_data : signal is true;
-- attribute keep of cpu_tag : signal is true;
-- attribute keep of cpu_index : signal is true;
-- attribute keep of cpu_offset : signal is true;
-- attribute keep of cpu_way : signal is true;
begin
cpu_pause <= cpu_pause_buff;
cpu_tag <= cpu_next_address(cache_cacheable_width-1 downto cache_offset_width+cache_index_width);
cpu_index <= to_integer(unsigned(cpu_next_address(cache_offset_width+cache_index_width-1 downto cache_offset_width)));
cpu_offset <= to_integer(unsigned(cpu_next_address(cache_offset_width-1 downto 0)));
cpu_cacheable <= True when or_reduce(cpu_next_address(cpu_address_width-1 downto cache_cacheable_width))='0' else False;
memory_write_enable <= memory_write_enable_buff;
memory_write_valid <= memory_write_valid_buff;
memory_read_ready <= memory_read_ready_buff;
memory_read_enable <= memory_read_enable_buff;
oper_request <= True when cpu_next_address(cpu_address_width-1 downto cpu_address_width-oper_base_width)=oper_base and and_reduce(cpu_write_enables)='1' else False;
oper_request_invalidate <= True when cpu_next_address(oper_offset_width-1 downto 0)=oper_invalidate_offset else False;
oper_request_flush <= True when cpu_next_address(oper_offset_width-1 downto 0)=oper_flush_offset else False;
oper_started <= True when (oper_started_invalidate or oper_started_flush) and and_reduce(cpu_write_enables)='1' else False;
process(cpu_index,cpu_tag,tag_rows,valid_rows)
variable cpu_hit_buff : Boolean;
variable cpu_way_buff : integer range 0 to 2**cache_way_width-1 := 0;
variable tag_buff : std_logic_vector(tag_width-1 downto 0);
begin
cpu_hit_buff := False;
cpu_way_buff := 0;
for each_way in 0 to 2**cache_way_width-1 loop
tag_buff := tag_rows(cpu_index)((each_way+1)*tag_width-1 downto each_way*tag_width);
if tag_buff=cpu_tag and valid_rows(cpu_index)(each_way)='1' then
cpu_hit_buff := True;
cpu_way_buff := each_way;
exit;
end if;
end loop;
cpu_hit <= cpu_hit_buff;
cpu_way <= cpu_way_buff;
end process;
generate_policy_plru:
if cache_policy= "plru" generate
process (plru_rows,cpu_index)
subtype int_type is integer range 0 to plru_width;
variable plru_buff : std_logic_vector(plru_width-1 downto 0);
variable this_bit : int_type;
variable left_bit : int_type;
variable right_bit : int_type;
variable row_width : int_type;
variable replace_bit : int_type;
begin
if cache_way_width/=0 then
plru_buff := plru_rows(cpu_index);
this_bit := 0;
row_width := 0;
for each_row in 1 to 2**cache_way_width/2-1 loop
row_width := row_width+1;
left_bit := row_width+this_bit;
right_bit := left_bit+1;
if plru_buff(this_bit)='0' then
plru_buff(this_bit) := '1';
this_bit := left_bit;
else
plru_buff(this_bit) := '0';
this_bit := right_bit;
end if;
end loop;
replace_bit := this_bit-row_width;
left_bit := replace_bit*2;
right_bit := left_bit+1;
if plru_buff(this_bit)='0' then
plru_buff(this_bit) := '1';
this_bit := left_bit;
else
plru_buff(this_bit) := '0';
this_bit := right_bit;
end if;
replace_way <= this_bit;
replace_plru <= plru_buff;
else
replace_way <= 0;
replace_plru <= (others=>'0');
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if resetn='0' then
plru_rows <= (others=>(others=>'0'));
elsif not memory_access_needed and
not oper_started and not oper_request and
cpu_cacheable and not cpu_hit and memory_prepared then
plru_rows(cpu_index) <= replace_plru;
end if;
end if;
end process;
end generate
generate_policy_plru;
generate_policy_rr:
if cache_policy= "rr" generate
process (clock)
variable lfsr_buff_0 : unsigned(rr_lfsr_width-1 downto 0);
variable lfsr_buff_1 : unsigned(rr_lfsr_width-1 downto 0);
variable lfsr_buff_2 : unsigned(rr_lfsr_width-1 downto 0);
begin
if rising_edge(clock) then
lfsr_buff_0 := unsigned(rr_lfsr);
lfsr_buff_1 := ((lfsr_buff_0 srl 0) xor (lfsr_buff_0 srl 2) xor (lfsr_buff_0 srl 3) xor (lfsr_buff_0 srl 5)) and to_unsigned(1,rr_lfsr_width);
lfsr_buff_2 := (lfsr_buff_0 srl 1) or (lfsr_buff_1 sll 15);
rr_lfsr <= std_logic_vector(lfsr_buff_2);
end if;
end process;
process (rr_lfsr)
begin
if cache_way_width/=0 then
replace_way <= to_integer(unsigned(rr_lfsr(cache_way_width-1 downto 0)));
else
replace_way <= 0;
end if;
end process;
end generate
generate_policy_rr;
process (clock)
variable memory_write_handshake : Boolean;
variable memory_read_handshake : Boolean;
variable memory_access_exread_block : Boolean;
variable memory_access_exwrite_block : Boolean;
variable memory_access_word : Boolean;
begin
if rising_edge(clock) then
if resetn='0' then
memory_prepared <= False;
memory_access_needed <= False;
memory_write_enable_buff <= '0';
memory_write_valid_buff <= '0';
memory_read_ready_buff <= '0';
memory_read_enable_buff <= '0';
cpu_pause_buff <= '0';
valid_rows <= (others=>(others=>'0'));
oper_started_flush <= False;
oper_started_invalidate <= False;
else
if memory_access_needed then
memory_write_handshake := memory_write_valid_buff='1' and memory_write_ready='1';
memory_read_handshake := memory_read_valid='1' and memory_read_ready_buff='1';
memory_access_exread_block := memory_access_mode=msm_read_block or memory_access_mode=msm_exchange_block;
memory_access_exwrite_block := memory_access_mode=msm_write_block or memory_access_mode=msm_exchange_block;
memory_access_word := memory_access_mode=msm_read_word or memory_access_mode=msm_write_word;
if memory_write_handshake and memory_access_exwrite_block and memory_write_counter/=2**block_word_width-1 then
memory_write_data <=
block_rows(memory_index)(
memory_way*2**cache_offset_width*8+(memory_write_counter+2)*cpu_data_width-1 downto
memory_way*2**cache_offset_width*8+(memory_write_counter+1)*cpu_data_width);
end if;
if memory_read_handshake and memory_access_exread_block then
block_rows(memory_index)(
memory_way*2**cache_offset_width*8+(memory_read_counter+1)*cpu_data_width-1 downto
memory_way*2**cache_offset_width*8+memory_read_counter*cpu_data_width) <=
memory_read_data;
end if;
if memory_read_handshake and memory_access_mode=msm_read_word then
cpu_read_data <= memory_read_data;
end if;
if (memory_access_exwrite_block and memory_write_counter=2**block_word_width-1) or
(memory_access_mode=msm_write_word and memory_write_handshake) then
memory_write_enable_buff <= '0';
end if;
if (memory_access_exread_block and memory_read_counter=2**block_word_width-1) or
(memory_access_mode=msm_read_word and memory_read_handshake) then
memory_read_enable_buff <= '0';
end if;
if (memory_access_exwrite_block and memory_write_counter/=2**block_word_width-1) or
(memory_access_mode=msm_write_word and not memory_write_handshake) then
memory_write_valid_buff <= '1';
else
memory_write_valid_buff <= '0';
end if;
if ((memory_access_mode=msm_read_block or (memory_access_mode=msm_exchange_block and memory_read_counter/=memory_write_counter)) and memory_read_counter/=2**block_word_width-1) or
(memory_access_mode=msm_read_word and not memory_read_handshake) then
memory_read_ready_buff <= '1';
else
memory_read_ready_buff <= '0';
end if;
if memory_access_exwrite_block and
memory_write_handshake and
memory_write_counter/=2**block_word_width-1 then
memory_write_counter <= memory_write_counter+1;
end if;
if (memory_access_mode=msm_read_block or (memory_access_mode=msm_exchange_block and memory_read_counter/=memory_write_counter)) and
memory_read_handshake and
memory_read_counter/=2**block_word_width-1 then
memory_read_counter <= memory_read_counter+1;
end if;
if memory_access_exread_block and memory_read_counter=2**block_word_width-1 then
for each_byte in 0 to cpu_data_width/8-1 loop
if or_reduce(replace_write_enables)='1' then
if replace_write_enables(each_byte)='1' then
block_rows(memory_index)(
memory_way*2**cache_offset_width*8+replace_offset*8+(each_byte+1)*8-1 downto
memory_way*2**cache_offset_width*8+replace_offset*8+each_byte*8) <=
replace_write_data(7+each_byte*8 downto 0+each_byte*8);
end if;
else
cpu_read_data(7+each_byte*8 downto 0+each_byte*8) <=
block_rows(memory_index)(
memory_way*2**cache_offset_width*8+replace_offset*8+(each_byte+1)*8-1 downto
memory_way*2**cache_offset_width*8+replace_offset*8+each_byte*8);
end if;
end loop;
end if;
if ((memory_access_exwrite_block or memory_access_exread_block) and memory_write_enable_buff='0' and memory_read_enable_buff='0') or
(memory_access_word and (memory_write_handshake or memory_read_handshake)) then
memory_access_needed <= False;
cpu_pause_buff <= '0';
end if;
elsif oper_started then
if cpu_hit then
if oper_started_invalidate then
valid_rows(cpu_index)(cpu_way) <='0';
elsif oper_started_flush then
cpu_pause_buff <= '1';
memory_access_mode <= msm_write_block;
memory_access_needed <= True;
memory_way <= cpu_way;
memory_cacheable <= '1';
memory_index <= cpu_index;
memory_write_address(cpu_address_width-1 downto cache_cacheable_width) <= (others=>'0');
memory_write_address(cache_cacheable_width-1 downto cache_offset_width) <=
tag_rows(cpu_index)((1+cpu_way)*tag_width-1 downto cpu_way*tag_width) &
std_logic_vector(to_unsigned(cpu_index,cache_index_width));
memory_write_address(cache_offset_width-1 downto 0) <= (others=>'0');
memory_write_counter <= 0;
memory_write_enables <= (others=>'1');
memory_write_enable_buff <= '1';
memory_write_data <=
block_rows(cpu_index)(
cpu_way*2**cache_offset_width*8+cpu_data_width-1 downto
cpu_way*2**cache_offset_width*8);
end if;
end if;
oper_started_invalidate <= False;
oper_started_flush <= False;
elsif oper_request then
if oper_request_invalidate then
oper_started_invalidate <= True;
elsif oper_request_flush then
oper_started_flush <= True;
end if;
elsif not cpu_cacheable then
cpu_pause_buff <= '1';
memory_access_needed <= True;
memory_cacheable <= '0';
if or_reduce(cpu_write_enables)='1' then
memory_access_mode <= msm_write_word;
memory_write_address <= cpu_next_address;
memory_write_enables <= cpu_write_enables;
memory_write_data <= cpu_write_data;
memory_write_counter <= 0;
memory_write_enable_buff <= '1';
else
memory_access_mode <= msm_read_word;
memory_read_address <= cpu_next_address;
memory_read_counter <= 0;
memory_read_enable_buff <= '1';
end if;
elsif cpu_hit then
for each_byte in 0 to cpu_data_width/8-1 loop
if or_reduce(cpu_write_enables)='1' then
if cpu_write_enables(each_byte)='1' then
block_rows(cpu_index)(
cpu_way*2**cache_offset_width*8+cpu_offset*8+(each_byte+1)*8-1 downto
cpu_way*2**cache_offset_width*8+cpu_offset*8+each_byte*8) <=
cpu_write_data(7+each_byte*8 downto 0+each_byte*8);
end if;
else
cpu_read_data(7+each_byte*8 downto 0+each_byte*8) <=
block_rows(cpu_index)(
cpu_way*2**cache_offset_width*8+cpu_offset*8+(each_byte+1)*8-1 downto
cpu_way*2**cache_offset_width*8+cpu_offset*8+each_byte*8);
end if;
end loop;
elsif not cpu_hit then
cpu_pause_buff <= '1';
if not memory_prepared then
memory_prepared <= True;
replace_write_enables <= cpu_write_enables;
else
memory_access_needed <= True;
memory_prepared <= False;
memory_way <= replace_way;
memory_cacheable <= '1';
replace_write_data <= cpu_write_data;
replace_offset <= cpu_offset;
tag_rows(cpu_index)((1+replace_way)*tag_width-1 downto replace_way*tag_width) <= cpu_tag;
memory_index <= cpu_index;
if valid_rows(cpu_index)(replace_way)='1' then
memory_access_mode <= msm_exchange_block;
memory_write_address(cpu_address_width-1 downto cache_cacheable_width) <= (others=>'0');
memory_write_address(cache_cacheable_width-1 downto cache_offset_width) <=
tag_rows(cpu_index)((1+replace_way)*tag_width-1 downto replace_way*tag_width) &
std_logic_vector(to_unsigned(cpu_index,cache_index_width));
memory_write_address(cache_offset_width-1 downto 0) <= (others=>'0');
memory_write_counter <= 0;
memory_write_enables <= (others=>'1');
memory_write_enable_buff <= '1';
memory_write_data <=
block_rows(cpu_index)(
replace_way*2**cache_offset_width*8+cpu_data_width-1 downto
replace_way*2**cache_offset_width*8);
else
valid_rows(cpu_index)(replace_way) <='1';
memory_access_mode <= msm_read_block;
end if;
memory_read_address(cpu_address_width-1 downto cache_cacheable_width) <= (others=>'0');
memory_read_address(cache_cacheable_width-1 downto cache_offset_width) <=
cpu_tag & std_logic_vector(to_unsigned(cpu_index,cache_index_width));
memory_read_address(cache_offset_width-1 downto 0) <= (others=>'0');
memory_read_counter <= 0;
memory_read_enable_buff <= '1';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
0130fa96206827188cbedc11ad766f3f
| 0.536751 | 4.308068 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd
| 4 | 50,277 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(31 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1_8.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1_8.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1_8.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1_8.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
|
bsd-3-clause
|
d11c356a902568aa6c575eaf33303042
| 0.398592 | 4.339461 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP3_roulette_vhdl/fsm.vhd
| 1 | 1,419 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:38 10/17/2014
-- Design Name:
-- Module Name: fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm is
Port ( clk : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Q : out STD_LOGIC);
end fsm;
architecture Behavioral of fsm is
signal output : std_logic;
begin
process (clk)
begin
if clk'event and clk='1' then
if (J = '0' and K = '0') then
output <= output;
elsif (J = '1' and K = '0') then
output <= '1';
elsif (J = '0' and K = '1') then
output <= '0';
elsif (J = '1' and K = '1') then
output <= not(output);
end if;
end if;
Q <= output;
end process;
end Behavioral;
|
gpl-2.0
|
119276f6e84369362fd1469c2f850c2c
| 0.522903 | 3.877049 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/RegCaster.vhdl
| 1 | 985 |
-- Zero/Sign extend integers before loading them into registers
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.utils.all;
entity RegCaster is
port (input : in word_t;
SignExtend : in ctrl_t;
size : in ctrl_memwidth_t;
extended : out word_t
);
end;
Architecture behav of RegCaster is
constant ZEROS : byte_t := X"00";
constant ONES : byte_t := X"ff";
alias byte is input( 7 downto 0);
alias byte_msb is input(7);
alias half is input(15 downto 0);
alias half_msb is input(15);
alias word is input(31 downto 0);
begin
extended <= X"FFFF_FF" & byte when size = WIDTH_BYTE and SignExtend = '1' and byte_msb = '1'
else X"0000_00" & byte when size = WIDTH_BYTE
else X"FFFF" & half when size = WIDTH_HALF and SignExtend = '1' and half_msb = '1'
else X"0000" & half when size = WIDTH_HALF
else word;
end;
|
gpl-3.0
|
204c976d62bcdfa31cc8c8b9bcb581d7
| 0.594924 | 3.555957 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/roms/default.vhdl
| 1 | 1,958 |
-- Generated by tools/generate-rom.pl
-- Template: https://www.xilinx.com/support/answers/8183.html
-- But changed manually afterwards
library ieee;
use ieee.std_logic_1164.all;
use work.txt_utils.all;
use work.arch_defs.all;
use work.utils.all;
entity rom_default is
port ( a: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0);
en: in std_logic
);
attribute syn_romstyle : string;
attribute syn_romstyle of z : signal is "select_rom";
end rom_default;
architecture rtl of rom_default is
signal my_z : word_t;
begin
z <= my_z when en = '1' else HI_Z;
process(a)
begin
if en = '1' then
printf("Address = %s\n", a);
case a is
-- _start:
-- FIXME the first instruction won't be executed.
-- No idea why, so keep that in mind and place a nop there or something
when X"0000_0000" => my_z <= X"0000_0000";
when X"0000_0004" => my_z <= X"3421_f000"; -- ori $1,$1,0xf000
when X"0000_0008" => my_z <= X"0000_0000";
when X"0000_000C" => my_z <= X"3422_0bad"; -- ori $1,$2,0xbad
when X"0000_0010" => my_z <= X"0000_0000";
when X"0000_0014" => my_z <= X"3c03_A000"; -- lui $3,0xA000
when X"0000_0018" => my_z <= X"0000_0000";
when X"0000_001C" => my_z <= X"a062_0000"; -- sb $2,0($3)
when X"0000_0020" => my_z <= X"0000_0000";
when X"0000_0024" => my_z <= X"0000_0000";
when X"0000_0028" => my_z <= X"8064_0000"; -- lb $4,0($3)
when X"0000_002C" => my_z <= X"0800_0000"; -- j 0 <_start>
when X"0000_0030" => my_z <= X"0000_0000"; -- j 0 <_start>
when others => null;
end case;
end if;
end process;
end rtl;
|
gpl-3.0
|
e802699f59303b9250ab42bcc4d3ba56
| 0.502043 | 3.204583 | false | false | false | false |
makestuff/vga_test
|
vhdl/vga_sync/tb_unit/vga_sync_tb.vhdl
| 1 | 2,433 |
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sync_tb is
end entity;
architecture behavioural of vga_sync_tb is
signal sysClk : std_logic;
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
signal hSync : std_logic;
signal vSync : std_logic;
signal pixX : unsigned(4 downto 0); -- current pixel's X coordinate
signal pixY : unsigned(4 downto 0); -- current pixel's Y coordinate
signal display : std_logic;
constant HRES : integer := 16; -- horizontal resolution
constant VRES : integer := 16; -- vertical resolution
begin
-- Instantiate vga_sync for testing
uut: entity work.vga_sync
generic map (
-- Horizontal parameters (numbers are pixClk counts)
HORIZ_DISP => HRES,
HORIZ_FP => 4,
HORIZ_RT => 2,
HORIZ_BP => 4,
-- Vertical parameters (in line counts)
VERT_DISP => VRES,
VERT_FP => 4,
VERT_RT => 2,
VERT_BP => 4,
-- Coordinate bit-width
COORD_WIDTH => 5
)
port map(
clk_in => sysClk,
reset_in => '0',
hSync_out => hSync,
vSync_out => vSync,
pixX_out => pixX,
pixY_out => pixY
);
-- Drive high when in active screen area
display <=
'1' when pixX < HRES and pixY < VRES
else '0';
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time for
-- signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
end architecture;
|
gpl-3.0
|
78f64d542951a68a12aa43949beceebc
| 0.656391 | 3.34663 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vsigactofkofzero.vhd
| 1 | 1,735 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vsigactofkofzero is
port (
clock : in std_logic;
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Vsigactofkofzero : out std_logic_vector(31 downto 0)
);
end k_ukf_Vsigactofkofzero;
architecture struct of k_ukf_Vsigactofkofzero is
component k_ukf_Uofk is
port (
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactofk : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
clock : in std_logic;
Uofk : out std_logic_vector(31 downto 0)
);
end component;
component k_ukf_Vactcapofk is
port (
clock : in std_logic;
Vactofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Uofk : in std_logic_vector(31 downto 0);
Vactcapofk : out std_logic_vector(31 downto 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_Uofk port map
( clock => clock,
I => I,
Isc => Isc,
Vactofk => Vactcapofk,
D => D,
B => B,
Uofk => Z);
M2 : k_ukf_Vactcapofk port map
( clock => clock,
Vactofk => Vactcapofk,
M => M,
Uofk => Z,
Vactcapofk => Vsigactofkofzero);
end struct;
|
gpl-2.0
|
02d3cf861344e71703251e1d06865b9b
| 0.554467 | 3.362403 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/EX.vhdl
| 1 | 2,292 |
-- Execute
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end;
architecture struct of Execute is
-- multi used componets
component Adder is
port(
src1: in addr_t;
src2: in addrdiff_t;
result: out addr_t);
end component;
component ShiftLeftImm is
port(
imm: in std_logic_vector (31 downto 0);
output: out std_logic_vector (31 downto 0));
end component;
component shiftMux is
port (
Shift: in ctrl_t;
reg1data : in word_t;
shamt : in word_t;
output : out word_t);
end component;
component ALUSrcMux is
port (
ALUSrc: in ctrl_t;
reg2data : in word_t;
immediate : in word_t;
output : out word_t);
end component;
component alu is
port(
Src1 : in word_t;
Src2 : in word_t;
ALUOp : in alu_op_t;
Immediate : in ctrl_t;
AluResult : out word_t;
isZero : out ctrl_t;
trap : out traps_t
);
end component;
-- pc
signal branch_offset : addrdiff_t;
-- ALU signals
signal Src1, Src2 : word_t;
signal isZero : ctrl_t;
begin
shiftLeftImm1: shiftLeftImm
port map(imm => sexed, output => branch_offset);
branchAdd: Adder
port map(
src1 => pc_plus_4,
src2 => branch_offset,
result => branch_addr
);
shiftMux1: shiftMux
port map (Shift => Shift_in, reg1data => regReadData1, shamt => zeroxed, output => Src1);
--alu
aluSrc2Mux1: aluSrcMux
port map (ALUSrc => AluSrc_in, reg2data => regReadData2, immediate => sexed, output => Src2);
alu1: alu
port map (Src1 => Src1, Src2 => Src2, AluOp => ALUOp_in, Immediate => AluSrc_in, AluResult => AluResult, isZero => isZero);
takebranch <= Branch_in and isZero;
end struct;
|
gpl-3.0
|
1fdf8f12a26908d6d8e471ca05584e2f
| 0.564136 | 3.592476 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/cpu.vhdl
| 1 | 14,194 |
-- The CPU, only the stateless parts
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.memory_map.all;
-- We keep keep all state (registers, memory) out of the CPU
-- This allows for testbenches that can instantiate them internally
-- and check whether everything works as expected
entity cpu is
generic(PC_ADD : natural := 4;
SINGLE_ADDRESS_SPACE : boolean := true);
port(
clk : in std_logic;
rst : in std_logic;
-- Register File
readreg1, readreg2 : out reg_t;
writereg: out reg_t;
regWriteData: out word_t;
regReadData1, regReadData2 : in word_t;
regwrite : out std_logic;
-- Memory
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t;
-- Debug info
instruction : out instruction_t
);
end;
architecture struct of cpu is
component Pipeliner is
port(
clk, rst : in std_logic;
ID_en, IF_en, EX_en, MEM_en, MEM_read, WB_en : out std_logic;
Instruction_done : out std_logic
);
end component;
component PipeReg is
generic (BITS : natural := 32);
port(
data : in std_logic_vector(BITS-1 downto 0);
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out std_logic_vector(BITS-1 downto 0) -- output.
);
end component;
component CtrlReg is port(
data : in std_logic;
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out std_logic
);
end component;
component AluOpReg is port(
data : in alu_op_t;
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out alu_op_t
);
end component;
component MUX is
generic (BITS : natural := 32);
port (
sel: in ctrl_t;
input0 : in std_logic_vector(BITS-1 downto 0);
input1 : in std_logic_vector(BITS-1 downto 0);
output : out std_logic_vector(BITS-1 downto 0)
);
end component;
component MUX1bit is
port (
sel: in ctrl_t;
input0 : in std_logic;
input1 : in std_logic;
output : out std_logic
);
end component;
component InstructionFetch is
generic(PC_ADD : natural := PC_ADD;
SINGLE_ADDRESS_SPACE : boolean := SINGLE_ADDRESS_SPACE);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end component;
component InstructionDecode is
port(
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread, memwrite : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
component Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end component;
component MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
component WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end component;
signal IF_en : std_logic := '0';
signal ID_en : std_logic := '0';
signal EX_en : std_logic := '0';
signal MEM_en : std_logic := '0';
signal MEM_read : std_logic := '0';
signal WB_en : std_logic := '0';
signal Instruction_done : std_logic := '0';
signal regwrite_no_wb : std_logic := '0';
signal regwrite_pre_reg : ctrl_t;
signal Link, JumpReg, JumpDir, Branch, MemToReg, Shift, ALUSrc, MemSex : ctrl_t;
signal Link_pre_reg, JumpReg_pre_reg, JumpDir_pre_reg, Branch_pre_reg, MemToReg_pre_reg, Shift_pre_reg, ALUSrc_pre_reg, MemSex_pre_reg : ctrl_t;
signal TakeBranch, TakeBranch_pre_reg : ctrl_t;
signal MemRead, MemWrite : ctrl_memwidth_t;
signal MemRead_pre_reg, MemWrite_pre_reg : ctrl_memwidth_t;
signal memReadData, memReadData_pre_reg : word_t;
signal new_pc, new_pc_pre_reg : addr_t := BOOT_ADDR;
signal pc_plus_4, pc_plus_4_pre_reg, jump_addr, jump_addr_pre_reg, branch_addr : addr_t;
signal instr, instr_pre_reg : instruction_t;
signal zeroxed, sexed, zeroxed_pre_reg, sexed_pre_reg, aluResult, aluResult_pre_reg: word_t;
signal readreg1_pre_reg, readreg2_pre_reg, writereg_pre_reg : reg_t;
signal regwritedata_pre_reg : word_t;
signal aluop : alu_op_t;
signal aluop_slv : natural; -- debug only;
signal aluop_pre_reg : alu_op_t;
signal selMEM : ctrl_t := '0';
signal top_addr_mem, top_addr_if : addr_t;
signal top_din_mem, top_din_if : word_t;
signal top_size_mem, top_size_if : ctrl_memwidth_t;
signal top_wr_mem, top_wr_if : ctrl_t;
begin
aluop_slv <= alu_op_t'pos(aluop);
if1: InstructionFetch
generic map (PC_ADD => PC_ADD)
port map(
clk => clk,
rst => rst,
new_pc => new_pc,
pc_plus_4 => pc_plus_4_pre_reg,
instr => instr_pre_reg,
top_addr => top_addr_if,
top_dout => top_dout,
top_din => top_din_if,
top_size => top_size_if,
top_wr => top_wr_if
);
regwrite <= WB_en and regwrite_no_wb;
new_pc_reg: PipeReg
generic map(32)
port map (
data => new_pc_pre_reg,
enable => WB_en,
clr => rst,
clk => clk,
output => new_pc
);
pc_plus_4_reg: PipeReg
generic map(32)
port map (
data => pc_plus_4_pre_reg,
enable => IF_en,
clr => rst,
clk => clk,
output => pc_plus_4
);
instr_reg: PipeReg
generic map(32)
port map (
data => instr_pre_reg,
enable => IF_en,
clr => rst,
clk => clk,
output => instr
);
instruction <= instr;
id1: InstructionDecode
port map(
instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr_pre_reg,
regwrite => regwrite_pre_reg, link => link_pre_reg, jumpreg => jumpreg_pre_reg, jumpdirect => jumpDir_pre_reg, branch => Branch_pre_reg,
memread => memRead_pre_reg, memwrite => memWrite_pre_reg,
memtoreg => memToReg_pre_reg, memsex => memSex_pre_reg,
shift => shift_pre_reg, alusrc => aluSrc_pre_reg,
aluop => aluOp_pre_reg,
readreg1 => readReg1_pre_reg, readreg2 => readReg2_pre_reg, writeReg => writeReg_pre_reg,
zeroxed => zeroxed_pre_reg, sexed => sexed_pre_reg,
clk => clk,
rst => rst
);
readreg1_reg: PipeReg
generic map(5)
port map (
data => readreg1_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => readreg1
);
readreg2_reg: PipeReg
generic map(5)
port map (
data => readreg2_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => readreg2
);
writereg_reg: PipeReg
generic map(5)
port map (
data => writereg_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => writereg
);
pipeliner1: pipeliner port map (
clk => clk,
rst => rst,
IF_en => IF_en,
ID_en => ID_en,
EX_en => EX_en,
MEM_en => MEM_en,
MEM_read => MEM_read,
WB_en => WB_en,
Instruction_done => Instruction_done
);
ctrlvec_regwrite_reg : CtrlReg port map (data => regwrite_pre_reg, enable => ID_en, clr => rst, clk => clk, output => regwrite_no_wb);
--ctrlvec_regdst_reg : CtrlReg port map (data => regdst_pre_reg, enable => ID_en, clr => rst, clk => clk, output => regdst);
ctrlvec_link_reg : CtrlReg port map (data => link_pre_reg, enable => ID_en, clr => rst, clk => clk, output => link);
ctrlvec_jumpreg_reg : CtrlReg port map (data => jumpreg_pre_reg, enable => ID_en, clr => rst, clk => clk, output => jumpreg);
ctrlvec_jumpdirect_reg : CtrlReg port map (data => jumpdir_pre_reg, enable => ID_en, clr => rst, clk => clk, output => jumpdir);
ctrlvec_branch_reg : CtrlReg port map (data => branch_pre_reg, enable => ID_en, clr => rst, clk => clk, output => branch);
ctrlvec_memread_reg : PipeReg generic map(2) port map (data => memread_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memread);
ctrlvec_memtoreg_reg : CtrlReg port map (data => memtoreg_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memtoreg);
ctrlvec_memsex_reg : CtrlReg port map (data => memsex_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memsex);
ctrlvec_memwrite_reg : PipeReg generic map (2) port map (data => memwrite_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memwrite);
ctrlvec_shift_reg : CtrlReg port map (data => shift_pre_reg, enable => ID_en, clr => rst, clk => clk, output => shift);
ctrlvec_alusrc_reg : CtrlReg port map (data => alusrc_pre_reg, enable => ID_en, clr => rst, clk => clk, output => alusrc);
ctrlvec_aluop_reg : AluOpReg port map (data => aluop_pre_reg, enable => ID_en, clr => rst, clk => clk, output => aluop);
jump_addr_reg: PipeReg
generic map(32)
port map (
data => jump_addr_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => jump_addr
);
zeroxed_reg: PipeReg
generic map(32)
port map (
data => zeroxed_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => zeroxed
);
sexed_reg: PipeReg
generic map(32)
port map (
data => sexed_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => sexed
);
ex1: Execute
port map(
pc_plus_4 => pc_plus_4,
regReadData1 => regReadData1, regReadData2 => regReadData2,
branch_addr => branch_addr,
branch_in => Branch,
shift_in => shift, alusrc_in => ALUSrc,
aluop_in => ALUOp,
zeroxed => zeroxed, sexed => sexed,
takeBranch => takeBranch_pre_reg,
ALUResult => ALUResult_pre_reg,
clk => clk,
rst => rst
);
takeBranch_reg: CtrlReg
port map (
data =>takeBranch_pre_reg,
enable => EX_en,
clr => rst,
clk => clk,
output => takeBranch
);
aluResult_reg: PipeReg
generic map(32)
port map (
data => aluResult_pre_reg,
enable => EX_en,
clr => rst,
clk => clk,
output => aluResult
);
process (clk)
begin
if rising_edge(clk) and (EX_en = '1' or WB_en = '1') then
selMEM <= not selMEM;
end if;
end process;
addrMux: MUX port map(sel=>selMEM,input0=>top_addr_if,input1=>top_addr_mem,output=>top_addr);
dinMux: MUX port map(sel=>selMEM,input0=>top_din_if, input1=>top_din_mem,output=>top_din);
sizeMux: MUX generic map(2) port map(sel=>selMEM,input0=>top_size_if,input1=>top_size_mem,output=>top_size);
wrMux: MUX1bit port map(sel=>selMEM,input0=>top_wr_if, input1=>top_wr_mem,output=>top_wr);
ma1: memoryAccess
port map(
-- inbound
Address_in => AluResult,
WriteData_in => regReadData2,
ReadData_in => memReadData_pre_reg,
MemRead_in => memRead,
MemWrite_in => memWrite,
MemSex_in => MemSex,
clk => clk,
-- outbound to top level module
top_addr => top_addr_mem,
top_dout => top_dout,
top_din => top_din_mem,
top_size => top_size_mem,
top_wr => top_wr_mem);
memReadData_reg: PipeReg
generic map (32)
port map (
data => memReadData_pre_reg,
enable => MEM_en,
clr => rst,
clk => clk,
output => memReadData
);
-- TODO: Remove this?
regWrite_data_reg: PipeReg
generic map(32)
port map (
data => regwritedata_pre_reg,
enable => '1',
clr => rst,
clk => clk,
output => regwritedata
);
wb1: WriteBack
port map(
Link => Link,
JumpReg => JumpReg,
JumpDir => JumpDir,
MemToReg => MemToReg,
TakeBranch => TakeBranch,
pc_plus_4 => pc_plus_4,
branch_addr => branch_addr,
jump_addr => jump_addr,
aluResult => aluResult,
memReadData => memReadData,
regReadData1 => regReadData1,
regWriteData => regWriteData_pre_reg,
new_pc => new_pc_pre_reg);
end struct;
|
gpl-3.0
|
3b9f5be34dfd044160901b92ad3a0237
| 0.553896 | 3.488326 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/synth/axi_dma_0.vhd
| 1 | 26,023 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY axi_dma_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END axi_dma_0;
ARCHITECTURE axi_dma_0_arch OF axi_dma_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_dma_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axi_dma_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_dma_0_arch : ARCHITECTURE IS "axi_dma_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF axi_dma_0_arch: ARCHITECTURE IS "axi_dma_0,axi_dma,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=1,C_FAMILY=kintex7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "kintex7"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END axi_dma_0_arch;
|
bsd-3-clause
|
cc3f19a2f08455470107d5859fef2ba5
| 0.677862 | 2.753174 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP3_roulette_vhdl/rdm.vhd
| 1 | 1,329 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:42:13 10/17/2014
-- Design Name:
-- Module Name: rdm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rdm is
Port ( clk : in STD_LOGIC;
E : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end rdm;
architecture Behavioral of rdm is
signal count : std_logic_vector (3 downto 0):="0001";
signal LF : std_logic;
begin
LF <= count(3) xor count(2);
process (clk)
begin
if clk'event and clk='1' then
if E='1' then
count <= count(2) & count(1) & count(0) & LF;
end if;
end if;
end process;
Q<= count;
end Behavioral;
|
gpl-2.0
|
f09ed58382a2023d7cf1569e2661f4f0
| 0.545523 | 3.920354 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_uart_axi4_read_cntrl.vhd
| 1 | 4,863 |
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_uart_pack.all;
entity plasoc_uart_axi4_read_cntrl is
generic (
fifo_depth : integer := 8;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_status_in_avail_bit_loc : integer := 0;
reg_control_status_out_avail_bit_loc : integer := 1;
reg_in_fifo_offset : std_logic_vector := X"0004";
reg_out_fifo_offset : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
reg_control_status_in_avail : out std_logic;
reg_control_status_out_avail : in std_logic;
reg_in_fifo : in std_logic_vector(7 downto 0);
reg_in_valid : in std_logic;
reg_in_ready : out std_logic);
end plasoc_uart_axi4_read_cntrl;
architecture Behavioral of plasoc_uart_axi4_read_cntrl is
component generic_fifo is
generic (
FIFO_WIDTH : positive := 32;
FIFO_DEPTH : positive := 1024
);
port (
clock : in std_logic;
nreset : in std_logic;
write_data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
read_data : out std_logic_vector(FIFO_WIDTH-1 downto 0);
write_en : in std_logic;
read_en : in std_logic;
full : out std_logic;
empty : out std_logic;
level : out std_logic_vector(clogb2(FIFO_DEPTH)-1 downto 0
)
);
end component;
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal reg_control : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal reg_out_fifo_buff : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
signal out_fifo : std_logic_vector(7 downto 0);
signal out_ready : std_logic := '0';
signal in_not_ready : std_logic;
signal out_not_valid : std_logic;
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
reg_control_status_in_avail <= not out_not_valid;
reg_control(reg_control_status_in_avail_bit_loc) <= not out_not_valid;
reg_control(reg_control_status_out_avail_bit_loc) <= reg_control_status_out_avail;
reg_out_fifo_buff(7 downto 0) <= out_fifo;
reg_in_ready <= not in_not_ready;
soc_uart_fifo_inst : generic_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => fifo_depth)
port map (
clock => aclk,
nreset => aresetn,
write_data => reg_in_fifo,
read_data => out_fifo,
write_en => reg_in_valid,
read_en => out_ready,
full => in_not_ready,
empty => out_not_valid,
level => open);
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
out_ready <= '0';
state <= state_wait;
else
case state is
when state_wait=>
if axi_arvalid='1' and axi_arready_buff='1' then
axi_arready_buff <= '0';
out_ready <= '1';
axi_rvalid_buff <= '1';
if axi_araddr=reg_control_offset then
axi_rdata <= reg_control;
elsif axi_araddr=reg_in_fifo_offset and out_not_valid='0' then
axi_rdata <= reg_out_fifo_buff;
else
axi_rdata <= (others=>'0');
end if;
state <= state_read;
else
axi_arready_buff <= '1';
end if;
when state_read=>
out_ready <= '0';
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
fdf24ca348343bcbc2bab0bad8bff67e
| 0.508123 | 3.796253 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bd/mig_wrap/hdl/mig_wrap.vhd
| 1 | 73,027 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
--Date : Mon Mar 27 01:47:30 2017
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target mig_wrap.bd
--Design : mig_wrap
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_GVFDLK is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_GVFDLK;
architecture STRUCTURE of s00_couplers_imp_GVFDLK is
component mig_wrap_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component mig_wrap_auto_cc_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_cc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_cc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_cc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_cc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_cc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_cc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_auto_cc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_cc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_auto_cc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_cc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_cc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_cc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_cc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_cc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_cc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_cc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_cc_WVALID : STD_LOGIC;
signal NLW_auto_cc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_cc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1 <= M_ARESETN;
M_AXI_araddr(31 downto 0) <= auto_cc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_cc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_cc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(3 downto 0) <= auto_cc_to_s00_couplers_ARID(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_cc_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_cc_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_cc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_cc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_cc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_cc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_cc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_cc_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_cc_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(3 downto 0) <= auto_cc_to_s00_couplers_AWID(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_cc_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_cc_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_cc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_cc_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_cc_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_cc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_cc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_cc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_cc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast <= auto_cc_to_s00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_cc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_cc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_cc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_cc_AWREADY;
S_AXI_bid(3 downto 0) <= s00_couplers_to_auto_cc_BID(3 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_cc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_cc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_cc_RDATA(31 downto 0);
S_AXI_rid(3 downto 0) <= s00_couplers_to_auto_cc_RID(3 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_cc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_cc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_cc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_cc_WREADY;
auto_cc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_cc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_cc_to_s00_couplers_BID(3 downto 0) <= M_AXI_bid(3 downto 0);
auto_cc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_cc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_cc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_cc_to_s00_couplers_RID(3 downto 0) <= M_AXI_rid(3 downto 0);
auto_cc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_cc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_cc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_cc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_cc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_cc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_cc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_cc_ARID(3 downto 0) <= S_AXI_arid(3 downto 0);
s00_couplers_to_auto_cc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_cc_ARLOCK(0) <= S_AXI_arlock(0);
s00_couplers_to_auto_cc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_cc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_cc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
s00_couplers_to_auto_cc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_cc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_cc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_cc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_cc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_cc_AWID(3 downto 0) <= S_AXI_awid(3 downto 0);
s00_couplers_to_auto_cc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_auto_cc_AWLOCK(0) <= S_AXI_awlock(0);
s00_couplers_to_auto_cc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_cc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_cc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
s00_couplers_to_auto_cc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_cc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_cc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_cc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_cc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_cc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_cc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_cc_WVALID <= S_AXI_wvalid;
auto_cc: component mig_wrap_auto_cc_0
port map (
m_axi_aclk => M_ACLK_1,
m_axi_araddr(31 downto 0) => auto_cc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_cc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_cc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_aresetn => M_ARESETN_1,
m_axi_arid(3 downto 0) => auto_cc_to_s00_couplers_ARID(3 downto 0),
m_axi_arlen(7 downto 0) => auto_cc_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_cc_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_cc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_cc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_cc_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_cc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_cc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_cc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_cc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_cc_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_cc_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awid(3 downto 0) => auto_cc_to_s00_couplers_AWID(3 downto 0),
m_axi_awlen(7 downto 0) => auto_cc_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_cc_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_cc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_cc_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_cc_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_cc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_cc_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_cc_to_s00_couplers_AWVALID,
m_axi_bid(3 downto 0) => auto_cc_to_s00_couplers_BID(3 downto 0),
m_axi_bready => auto_cc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_cc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_cc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_cc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rid(3 downto 0) => auto_cc_to_s00_couplers_RID(3 downto 0),
m_axi_rlast => auto_cc_to_s00_couplers_RLAST,
m_axi_rready => auto_cc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_cc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_cc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_cc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wlast => auto_cc_to_s00_couplers_WLAST,
m_axi_wready => auto_cc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_cc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_cc_to_s00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_cc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_cc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_cc_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arid(3 downto 0) => s00_couplers_to_auto_cc_ARID(3 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_cc_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_auto_cc_ARLOCK(0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_cc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_cc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_cc_ARREADY,
s_axi_arregion(3 downto 0) => s00_couplers_to_auto_cc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_cc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_cc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_cc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_cc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_cc_AWCACHE(3 downto 0),
s_axi_awid(3 downto 0) => s00_couplers_to_auto_cc_AWID(3 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_auto_cc_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_auto_cc_AWLOCK(0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_cc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_cc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_cc_AWREADY,
s_axi_awregion(3 downto 0) => s00_couplers_to_auto_cc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_cc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_cc_AWVALID,
s_axi_bid(3 downto 0) => s00_couplers_to_auto_cc_BID(3 downto 0),
s_axi_bready => s00_couplers_to_auto_cc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_cc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_cc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_cc_RDATA(31 downto 0),
s_axi_rid(3 downto 0) => s00_couplers_to_auto_cc_RID(3 downto 0),
s_axi_rlast => s00_couplers_to_auto_cc_RLAST,
s_axi_rready => s00_couplers_to_auto_cc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_cc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_cc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_cc_WDATA(31 downto 0),
s_axi_wlast => s00_couplers_to_auto_cc_WLAST,
s_axi_wready => s00_couplers_to_auto_cc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_cc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_cc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end mig_wrap_axi_interconnect_0_0;
architecture STRUCTURE of mig_wrap_axi_interconnect_0_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0);
M00_AXI_arid(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARID(3 downto 0);
M00_AXI_arlen(7 downto 0) <= s00_couplers_to_axi_interconnect_0_ARLEN(7 downto 0);
M00_AXI_arlock(0) <= s00_couplers_to_axi_interconnect_0_ARLOCK(0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0);
M00_AXI_awid(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWID(3 downto 0);
M00_AXI_awlen(7 downto 0) <= s00_couplers_to_axi_interconnect_0_AWLEN(7 downto 0);
M00_AXI_awlock(0) <= s00_couplers_to_axi_interconnect_0_AWLOCK(0);
M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0);
M00_AXI_awvalid <= s00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= s00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= s00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wlast <= s00_couplers_to_axi_interconnect_0_WLAST;
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(3 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(3 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(3 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(3 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= M00_ACLK;
axi_interconnect_0_ARESETN_net <= M00_ARESETN;
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(0) <= S00_AXI_arlock(0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARREGION(3 downto 0) <= S00_AXI_arregion(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(3 downto 0) <= S00_AXI_awid(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(0) <= S00_AXI_awlock(0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWREGION(3 downto 0) <= S00_AXI_awregion(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
s00_couplers_to_axi_interconnect_0_BID(3 downto 0) <= M00_AXI_bid(3 downto 0);
s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_axi_interconnect_0_RID(3 downto 0) <= M00_AXI_rid(3 downto 0);
s00_couplers_to_axi_interconnect_0_RLAST <= M00_AXI_rlast;
s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
s00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_GVFDLK
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN => axi_interconnect_0_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARCACHE(3 downto 0),
M_AXI_arid(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARID(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_axi_interconnect_0_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_axi_interconnect_0_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_interconnect_0_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWCACHE(3 downto 0),
M_AXI_awid(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWID(3 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_axi_interconnect_0_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_axi_interconnect_0_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_axi_interconnect_0_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_interconnect_0_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bid(3 downto 0) => s00_couplers_to_axi_interconnect_0_BID(3 downto 0),
M_AXI_bready => s00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rid(3 downto 0) => s00_couplers_to_axi_interconnect_0_RID(3 downto 0),
M_AXI_rlast => s00_couplers_to_axi_interconnect_0_RLAST,
M_AXI_rready => s00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wlast => s00_couplers_to_axi_interconnect_0_WLAST,
M_AXI_wready => s00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => axi_interconnect_0_to_s00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => axi_interconnect_0_to_s00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(3 downto 0) => axi_interconnect_0_to_s00_couplers_BID(3 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(3 downto 0) => axi_interconnect_0_to_s00_couplers_RID(3 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mig_wrap is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
sys_rst : in STD_LOGIC
);
attribute core_generation_info : string;
attribute core_generation_info of mig_wrap : entity is "mig_wrap,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mig_wrap,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=3,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute hw_handoff : string;
attribute hw_handoff of mig_wrap : entity is "mig_wrap.hwdef";
end mig_wrap;
architecture STRUCTURE of mig_wrap is
component mig_wrap_mig_7series_0_0 is
port (
sys_rst : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ui_clk_sync_rst : out STD_LOGIC;
ui_clk : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
mmcm_locked : out STD_LOGIC;
sys_clk_i : in STD_LOGIC;
init_calib_complete : out STD_LOGIC;
aresetn : in STD_LOGIC
);
end component mig_wrap_mig_7series_0_0;
component mig_wrap_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mig_wrap_proc_sys_reset_0_0;
signal ACLK_1 : STD_LOGIC;
signal ARESETN_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S00_AXI_1_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC;
signal S00_AXI_1_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S00_AXI_1_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC;
signal S00_AXI_1_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC;
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_RLAST : STD_LOGIC;
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC;
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WLAST : STD_LOGIC;
signal S00_AXI_1_WREADY : STD_LOGIC;
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_0_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_RLAST : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WLAST : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal clk_ref_i_1 : STD_LOGIC;
signal mig_7series_0_DDR2_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal mig_7series_0_DDR2_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal mig_7series_0_DDR2_CAS_N : STD_LOGIC;
signal mig_7series_0_DDR2_CKE : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_CK_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_CK_P : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_CS_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_DM : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR2_DQ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal mig_7series_0_DDR2_DQS_N : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR2_DQS_P : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR2_ODT : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR2_RAS_N : STD_LOGIC;
signal mig_7series_0_DDR2_WE_N : STD_LOGIC;
signal mig_7series_0_mmcm_locked : STD_LOGIC;
signal mig_7series_0_ui_clk : STD_LOGIC;
signal mig_7series_0_ui_clk_sync_rst : STD_LOGIC;
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_rst_1 : STD_LOGIC;
signal NLW_mig_7series_0_init_calib_complete_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
ACLK_1 <= ACLK;
ARESETN_1 <= ARESETN;
DDR2_addr(12 downto 0) <= mig_7series_0_DDR2_ADDR(12 downto 0);
DDR2_ba(2 downto 0) <= mig_7series_0_DDR2_BA(2 downto 0);
DDR2_cas_n <= mig_7series_0_DDR2_CAS_N;
DDR2_ck_n(0) <= mig_7series_0_DDR2_CK_N(0);
DDR2_ck_p(0) <= mig_7series_0_DDR2_CK_P(0);
DDR2_cke(0) <= mig_7series_0_DDR2_CKE(0);
DDR2_cs_n(0) <= mig_7series_0_DDR2_CS_N(0);
DDR2_dm(1 downto 0) <= mig_7series_0_DDR2_DM(1 downto 0);
DDR2_odt(0) <= mig_7series_0_DDR2_ODT(0);
DDR2_ras_n <= mig_7series_0_DDR2_RAS_N;
DDR2_we_n <= mig_7series_0_DDR2_WE_N;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_1_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
S00_AXI_1_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
S00_AXI_1_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
S00_AXI_1_ARID(3 downto 0) <= S00_AXI_arid(3 downto 0);
S00_AXI_1_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
S00_AXI_1_ARLOCK(0) <= S00_AXI_arlock(0);
S00_AXI_1_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
S00_AXI_1_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
S00_AXI_1_ARREGION(3 downto 0) <= S00_AXI_arregion(3 downto 0);
S00_AXI_1_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
S00_AXI_1_ARVALID <= S00_AXI_arvalid;
S00_AXI_1_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
S00_AXI_1_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
S00_AXI_1_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
S00_AXI_1_AWID(3 downto 0) <= S00_AXI_awid(3 downto 0);
S00_AXI_1_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
S00_AXI_1_AWLOCK(0) <= S00_AXI_awlock(0);
S00_AXI_1_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
S00_AXI_1_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
S00_AXI_1_AWREGION(3 downto 0) <= S00_AXI_awregion(3 downto 0);
S00_AXI_1_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
S00_AXI_1_AWVALID <= S00_AXI_awvalid;
S00_AXI_1_BREADY <= S00_AXI_bready;
S00_AXI_1_RREADY <= S00_AXI_rready;
S00_AXI_1_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
S00_AXI_1_WLAST <= S00_AXI_wlast;
S00_AXI_1_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
S00_AXI_1_WVALID <= S00_AXI_wvalid;
S00_AXI_arready <= S00_AXI_1_ARREADY;
S00_AXI_awready <= S00_AXI_1_AWREADY;
S00_AXI_bid(3 downto 0) <= S00_AXI_1_BID(3 downto 0);
S00_AXI_bresp(1 downto 0) <= S00_AXI_1_BRESP(1 downto 0);
S00_AXI_bvalid <= S00_AXI_1_BVALID;
S00_AXI_rdata(31 downto 0) <= S00_AXI_1_RDATA(31 downto 0);
S00_AXI_rid(3 downto 0) <= S00_AXI_1_RID(3 downto 0);
S00_AXI_rlast <= S00_AXI_1_RLAST;
S00_AXI_rresp(1 downto 0) <= S00_AXI_1_RRESP(1 downto 0);
S00_AXI_rvalid <= S00_AXI_1_RVALID;
S00_AXI_wready <= S00_AXI_1_WREADY;
clk_ref_i_1 <= clk_ref_i;
sys_rst_1 <= sys_rst;
axi_interconnect_0: entity work.mig_wrap_axi_interconnect_0_0
port map (
ACLK => ACLK_1,
ARESETN => ARESETN_1,
M00_ACLK => mig_7series_0_ui_clk,
M00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(3 downto 0) => axi_interconnect_0_M00_AXI_ARID(3 downto 0),
M00_AXI_arlen(7 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => axi_interconnect_0_M00_AXI_ARLOCK(0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(3 downto 0) => axi_interconnect_0_M00_AXI_AWID(3 downto 0),
M00_AXI_awlen(7 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => axi_interconnect_0_M00_AXI_AWLOCK(0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bid(3 downto 0) => axi_interconnect_0_M00_AXI_BID(3 downto 0),
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(3 downto 0) => axi_interconnect_0_M00_AXI_RID(3 downto 0),
M00_AXI_rlast => axi_interconnect_0_M00_AXI_RLAST,
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wlast => axi_interconnect_0_M00_AXI_WLAST,
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
S00_ACLK => ACLK_1,
S00_ARESETN => S00_ARESETN_1,
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
S00_AXI_arid(3 downto 0) => S00_AXI_1_ARID(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_1_ARLEN(7 downto 0),
S00_AXI_arlock(0) => S00_AXI_1_ARLOCK(0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
S00_AXI_arready => S00_AXI_1_ARREADY,
S00_AXI_arregion(3 downto 0) => S00_AXI_1_ARREGION(3 downto 0),
S00_AXI_arsize(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
S00_AXI_arvalid => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
S00_AXI_awid(3 downto 0) => S00_AXI_1_AWID(3 downto 0),
S00_AXI_awlen(7 downto 0) => S00_AXI_1_AWLEN(7 downto 0),
S00_AXI_awlock(0) => S00_AXI_1_AWLOCK(0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
S00_AXI_awready => S00_AXI_1_AWREADY,
S00_AXI_awregion(3 downto 0) => S00_AXI_1_AWREGION(3 downto 0),
S00_AXI_awsize(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
S00_AXI_awvalid => S00_AXI_1_AWVALID,
S00_AXI_bid(3 downto 0) => S00_AXI_1_BID(3 downto 0),
S00_AXI_bready => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid => S00_AXI_1_BVALID,
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rid(3 downto 0) => S00_AXI_1_RID(3 downto 0),
S00_AXI_rlast => S00_AXI_1_RLAST,
S00_AXI_rready => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid => S00_AXI_1_RVALID,
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wlast => S00_AXI_1_WLAST,
S00_AXI_wready => S00_AXI_1_WREADY,
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid => S00_AXI_1_WVALID
);
mig_7series_0: component mig_wrap_mig_7series_0_0
port map (
aresetn => proc_sys_reset_0_peripheral_aresetn(0),
clk_ref_i => clk_ref_i_1,
ddr2_addr(12 downto 0) => mig_7series_0_DDR2_ADDR(12 downto 0),
ddr2_ba(2 downto 0) => mig_7series_0_DDR2_BA(2 downto 0),
ddr2_cas_n => mig_7series_0_DDR2_CAS_N,
ddr2_ck_n(0) => mig_7series_0_DDR2_CK_N(0),
ddr2_ck_p(0) => mig_7series_0_DDR2_CK_P(0),
ddr2_cke(0) => mig_7series_0_DDR2_CKE(0),
ddr2_cs_n(0) => mig_7series_0_DDR2_CS_N(0),
ddr2_dm(1 downto 0) => mig_7series_0_DDR2_DM(1 downto 0),
ddr2_dq(15 downto 0) => DDR2_dq(15 downto 0),
ddr2_dqs_n(1 downto 0) => DDR2_dqs_n(1 downto 0),
ddr2_dqs_p(1 downto 0) => DDR2_dqs_p(1 downto 0),
ddr2_odt(0) => mig_7series_0_DDR2_ODT(0),
ddr2_ras_n => mig_7series_0_DDR2_RAS_N,
ddr2_we_n => mig_7series_0_DDR2_WE_N,
init_calib_complete => NLW_mig_7series_0_init_calib_complete_UNCONNECTED,
mmcm_locked => mig_7series_0_mmcm_locked,
s_axi_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => axi_interconnect_0_M00_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => axi_interconnect_0_M00_AXI_ARCACHE(3 downto 0),
s_axi_arid(3 downto 0) => axi_interconnect_0_M00_AXI_ARID(3 downto 0),
s_axi_arlen(7 downto 0) => axi_interconnect_0_M00_AXI_ARLEN(7 downto 0),
s_axi_arlock => axi_interconnect_0_M00_AXI_ARLOCK(0),
s_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => axi_interconnect_0_M00_AXI_ARQOS(3 downto 0),
s_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s_axi_arsize(2 downto 0) => axi_interconnect_0_M00_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => axi_interconnect_0_M00_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => axi_interconnect_0_M00_AXI_AWCACHE(3 downto 0),
s_axi_awid(3 downto 0) => axi_interconnect_0_M00_AXI_AWID(3 downto 0),
s_axi_awlen(7 downto 0) => axi_interconnect_0_M00_AXI_AWLEN(7 downto 0),
s_axi_awlock => axi_interconnect_0_M00_AXI_AWLOCK(0),
s_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => axi_interconnect_0_M00_AXI_AWQOS(3 downto 0),
s_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s_axi_awsize(2 downto 0) => axi_interconnect_0_M00_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s_axi_bid(3 downto 0) => axi_interconnect_0_M00_AXI_BID(3 downto 0),
s_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s_axi_rid(3 downto 0) => axi_interconnect_0_M00_AXI_RID(3 downto 0),
s_axi_rlast => axi_interconnect_0_M00_AXI_RLAST,
s_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s_axi_wlast => axi_interconnect_0_M00_AXI_WLAST,
s_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID,
sys_clk_i => clk_ref_i_1,
sys_rst => sys_rst_1,
ui_clk => mig_7series_0_ui_clk,
ui_clk_sync_rst => mig_7series_0_ui_clk_sync_rst
);
proc_sys_reset_0: component mig_wrap_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => mig_7series_0_mmcm_locked,
ext_reset_in => mig_7series_0_ui_clk_sync_rst,
interconnect_aresetn(0) => NLW_proc_sys_reset_0_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => mig_7series_0_ui_clk
);
end STRUCTURE;
|
mit
|
83f77914bacd5069c7c9907efbf6db70
| 0.670492 | 2.807219 | false | false | false | false |
Ttl/pic16f84
|
testbenches/timer_tb.vhd
| 1 | 2,180 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY timer_tb IS
END timer_tb;
ARCHITECTURE behavior OF timer_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT timer
PORT(
clk : IN std_logic;
reset : IN std_logic;
option : IN std_logic_vector(7 downto 0);
porta4 : IN std_logic;
tmr0_overflow : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal option : std_logic_vector(7 downto 0) := (others => '0');
signal porta4 : std_logic := '0';
--Outputs
signal tmr0_overflow : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: timer PORT MAP (
clk => clk,
reset => reset,
option => option,
porta4 => porta4,
tmr0_overflow => tmr0_overflow
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period;
option <= "11111001";
porta4 <= '0';
wait for clk_period*3;
porta4 <= '1';
wait for clk_period*3;
porta4 <= '0';
wait for clk_period*3;
porta4 <= '1';
wait for clk_period*3;
porta4 <= '0';
wait for clk_period*3;
porta4 <= '1';
wait for clk_period*3;
porta4 <= '0';
wait for clk_period*3;
porta4 <= '1';
wait for clk_period*3;
porta4 <= '0';
wait for clk_period*3;
porta4 <= '1';
wait for clk_period*3;
porta4 <= '0';
wait for clk_period*3;
porta4 <= '1';
wait for clk_period*3;
porta4 <= '0';
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
8bfae0198edec84a481ff6a4c5febb1e
| 0.55367 | 3.585526 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_int_cntrl.vhd
| 1 | 4,026 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 28, 2017
--! @brief Contains the entity and architecture of the
--! Interrupt Controller's main functionality.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_int_pack.all;
--! The functionality of the Interrupt Controller is defined
--! in this entity. For more information on how the Interrupt Controller
--! operates as a whole, please see the hardware description of the top entity
--! plasoc_int.
entity plasoc_int_cntrl is
generic (
interrupt_total : integer := 8 --! Defines the number of available device interrupts.
);
port (
-- Global interface.
clock : in std_logic; --! Clock. Tested with 50 MHz.
nreset : in std_logic; --! Reset on low.
-- CPU interface.
cpu_int : out std_logic := '0'; --! CPU interrupt. This signal is set high when there is an active interrupt.
cpu_int_id : out std_logic_vector(clogb2(interrupt_total) downto 0); --! Interrupt Identifier. This signal is set to the the identifier of the lowest identifier of the active interrupt, otherwise it is set to interrupt_total.
cpu_int_enables : in std_logic_vector(interrupt_total-1 downto 0); --! Interrupt Enables. Each bit enables the corresponding device interrupt.
cpu_int_active : out std_logic_vector(interrupt_total-1 downto 0); --! Interrupt Active. Each bit refers to an active interrupt.
-- Device interface.
dev_ints : in std_logic_vector(interrupt_total-1 downto 0) --! Device interrupts. The devices must set their corresponding device interrupt high to signal an interrupt.
);
end plasoc_int_cntrl;
architecture Behavioral of plasoc_int_cntrl is
signal cpu_int_active_buff : std_logic_vector(interrupt_total-1 downto 0);
signal cpu_int_id_buff : std_logic_vector(clogb2(interrupt_total) downto 0);
signal dev_int_occurred : boolean;
begin
-- Look for the active enabled interrupts.
cpu_int_active_buff <= dev_ints and cpu_int_enables;
cpu_int_active <= cpu_int_active_buff;
-- Determine whether or not an interrupt occurred.
dev_int_occurred <= True when or_reduce(cpu_int_active_buff)='1' else False;
-- Generate interrupt id for devices, for which the
-- lower the id the higher the priority.
process (cpu_int_active_buff)
variable triggerred_int : integer range 0 to interrupt_total;
begin
triggerred_int := interrupt_total;
for each_int in cpu_int_active_buff'low to cpu_int_active_buff'high loop
if cpu_int_active_buff(each_int)='1' then
triggerred_int := each_int;
exit;
end if;
end loop;
cpu_int_id_buff <= std_logic_vector(to_unsigned(triggerred_int,cpu_int_id_buff'length));
end process;
-- This process block generates the interrupt for the CPU and also
-- sets which interrupt is occurring.
process (clock)
begin
-- All operations occur on positive edge of the clock.
if rising_edge(clock) then
if nreset='0' then
cpu_int <= '0';
cpu_int_id <= (others=>'0');
else
-- Wait until an enabled interrupt occurs.
if dev_int_occurred then
-- Interrupt the process of the CPU, and let it know
-- which interrupt occurred with priority on the lowest interrupt.
cpu_int <= '1';
-- If no enabled interrupts are occurring, no need to
-- let the CPU anything is happening.
else
cpu_int <= '0';
end if;
cpu_int_id <= cpu_int_id_buff;
end if;
end if;
end process;
end Behavioral;
|
mit
|
f46e0cba019610fd27f7486011c63140
| 0.616493 | 4.224554 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP2/ipcore_dir/timer.vhd
| 1 | 6,526 |
-- file: timer.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 100.000 0.000 50.0 200.000 50.000
-- CLK_OUT2 100.000 0.000 50.0 200.000 50.000
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 100.000 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity timer is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end timer;
architecture xilinx of timer is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "timer,clk_wiz_v1_8,{component_name=timer,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK_OUT1 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clk0);
end xilinx;
|
gpl-2.0
|
32e18bdd40a1dbd560bf8ddc2b466305
| 0.559608 | 4.172634 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/maindec.vhdl
| 1 | 6,993 |
-- Use tools/assemble.pl to test control vector assignment
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity maindec is
port ( instr : in std_logic_vector(31 downto 0); -- instruction_t
regwrite, regdst, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
memwrite : out ctrl_memwidth_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t);
end;
architecture behave of maindec is
alias op is instr(31 downto 26);
alias rs is instr(25 downto 21);
alias rt is instr(20 downto 16);
alias rd is instr(15 downto 11);
alias shamt is instr(10 downto 6);
alias func is instr(5 downto 0);
alias imm is instr(15 downto 0);
constant i_regwrite : natural := 11;
constant i_regdst : natural := 10;
constant i_link : natural := 9;
constant i_jumpreg : natural := 8;
constant i_jumpdirect : natural := 7;
constant i_branch : natural := 6;
constant i_memread : natural := 5;
constant i_memtoreg : natural := 4;
constant i_memsex : natural := 3;
constant i_memwrite : natural := 2;
constant i_shift : natural := 1;
constant i_alusrc : natural := 0;
signal ctrl: std_logic_vector(i_regwrite downto i_alusrc);
signal memwidth : ctrl_memwidth_t := WIDTH_NONE;
begin
-- : 6 : 5 : 5 : 5 : 5 : 6 :
-- .------------------------------------------.
-- R |opcode| rs | rt | rd | shamt | func |
-- '------------------------------------------'
-- :31 26:25 21:20 16:15 11:10 6:5 0:
-- .------------------------------------------.
-- I |opcode| rs | rt | immediate |
-- '------------------------------------------'
-- :31 26:25 21:20 16:15 0:
-- .------------------------------------------.
-- J |opcode| address |
-- '------------------------------------------'
-- :31 26:25 0:
process (instr)
begin
case op is
when B"000_000" => ctrl <= "110000000000"; -- R-Type
case func is
when B"10_0000" => aluop <= ALU_ADD;
when B"10_0001" => aluop <= ALU_ADDU;
when B"10_0100" => aluop <= ALU_AND;
when B"10_0111" => aluop <= ALU_NOR;
when B"10_0101" => aluop <= ALU_OR;
when B"10_1010" => aluop <= ALU_SLT;
when B"10_1011" => aluop <= ALU_SLTU;
when B"10_0010" => aluop <= ALU_SUB;
when B"10_0011" => aluop <= ALU_SUBU;
when B"10_0110" => aluop <= ALU_XOR;
when B"00_0000" => aluop <= ALU_SLL; ctrl(i_shift) <= '1';
when B"00_0100" => aluop <= ALU_SLL; -- sllv
when B"00_0011" => aluop <= ALU_SRA; ctrl(i_shift) <= '1';
when B"00_0111" => aluop <= ALU_SRA; -- srav
when B"00_0010" => aluop <= ALU_SRL; ctrl(i_shift) <= '1';
when B"00_0110" => aluop <= ALU_SRL; -- srav
when B"01_1010" => aluop <= ALU_DIV;
when B"01_1011" => aluop <= ALU_DIVU;
when B"01_0000" => aluop <= ALU_MFHI;
when B"01_0010" => aluop <= ALU_MFLO;
when B"01_0001" => ctrl <= "0X000000000X"; aluop <= ALU_MTHI;
when B"01_0011" => ctrl <= "0X000000000X"; aluop <= ALU_MTLO;
when B"01_1000" => aluop <= ALU_MULT;
when B"01_1001" => aluop <= ALU_MULTU;
when B"00_1000" => ctrl <= "0XX1XX0XX00X"; -- jr
when B"00_1001" => ctrl <= "1111000XX00X"; -- jalr
when others => null; -- should be Illegal instruction instead
end case;
-- when OP_SHIFT => ctrl <= "1100000X0010"; aluop <= ALU_SHIFT; -- shift
when B"000_010" => ctrl <= "0XX01X00X00X"; -- j
when B"000_011" => ctrl <= "1X101X00X00X"; -- jal
when B"100_000" => ctrl <= "100000111001"; aluop <= ALU_ADD; memwidth <= WIDTH_BYTE; -- lb
when B"100_100" => ctrl <= "100000110001"; aluop <= ALU_ADD; memwidth <= WIDTH_BYTE; -- lbu
when B"100_001" => ctrl <= "100000111001"; aluop <= ALU_ADD; memwidth <= WIDTH_HALF; -- lh
when B"100_101" => ctrl <= "100000110001"; aluop <= ALU_ADD; memwidth <= WIDTH_HALF; -- lhu
when B"100_011" => ctrl <= "00000011X001"; aluop <= ALU_ADD; memwidth <= WIDTH_WORD; -- lw
when B"101_000" => ctrl <= "00000000X101"; aluop <= ALU_ADD; memwidth <= WIDTH_BYTE; -- sb
when B"101_001" => ctrl <= "00000000X101"; aluop <= ALU_ADD; memwidth <= WIDTH_HALF; -- sh
when B"101_011" => ctrl <= "00000000X101"; aluop <= ALU_ADD; memwidth <= WIDTH_WORD; -- sw
when B"000_100" => ctrl <= "0X0001000000"; aluop <= ALU_EQ; -- beq
when B"000_101" => ctrl <= "0X0001000000"; aluop <= ALU_NE; -- bne
-- Zero-relative branches
when B"000_001" => case rt is
when B"0_0000" => ctrl <= "000001000000"; aluop <= ALU_LTZ; -- bltz
when B"1_0000" => ctrl <= "011001000000"; aluop <= ALU_LTZ; -- bltzal
when B"0_0001" => ctrl <= "000001000000"; aluop <= ALU_GEZ; -- bgez
when B"1_0001" => ctrl <= "011001000000"; aluop <= ALU_GEZ; -- bgezal
when others => null;
end case;
when B"000_111" => ctrl <= "000001000000"; aluop <= ALU_GTZ; -- bgtz
when B"000_110" => ctrl <= "000001000000"; aluop <= ALU_LEZ; -- blez
when others => ctrl <= "100000000001"; -- I-Type
case op is
when B"0010_00" => aluop <= ALU_ADD;
when B"0010_01" => aluop <= ALU_ADDU;
when B"0011_00" => aluop <= ALU_AND;
when B"0011_11" => aluop <= ALU_LU;
when B"0011_01" => aluop <= ALU_OR;
when B"0010_10" => aluop <= ALU_SLT;
when B"0010_11" => aluop <= ALU_SLTU;
when B"0011_10" => aluop <= ALU_XOR;
when others => ctrl <= "------------";
end case;
end case;
end process;
memread <= memwidth when ctrl(i_memread) = '1' else WIDTH_NONE;
memwrite <= memwidth when ctrl(i_memwrite) = '1' else WIDTH_NONE;
regwrite <= ctrl(i_regwrite);
regdst <= ctrl(i_regdst);
link <= ctrl(i_link);
jumpreg <= ctrl(i_jumpreg);
jumpdirect <= ctrl(i_jumpdirect);
branch <= ctrl(i_branch);
memtoreg <= ctrl(i_memtoreg);
memsex <= ctrl(i_memsex);
shift <= ctrl(i_shift);
alusrc <= ctrl(i_alusrc);
end;
|
gpl-3.0
|
26c78890adf299ab5de149a101057b44
| 0.46761 | 3.707847 | false | false | false | false |
makestuff/dvr-connectors
|
conv-8to24/vhdl/conv_8to24.vhdl
| 1 | 3,011 |
--
-- Copyright (C) 2013 Joel Pérez Izquierdo
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Modified from conv_8to16.vhdl by Chris McClelland
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_8to24 is
port(
-- System clock
clk_in : in std_logic;
reset_in : in std_logic;
-- 8-bit data coming in
data8_in : in std_logic_vector(7 downto 0);
valid8_in : in std_logic;
ready8_out : out std_logic;
-- 24-bit data going out
data24_out : out std_logic_vector(23 downto 0);
valid24_out : out std_logic;
ready24_in : in std_logic
);
end entity;
architecture rtl of conv_8to24 is
type StateType is (
S_WAIT_MSB,
S_WAIT_MID,
S_WAIT_LSB
);
signal state : StateType := S_WAIT_MSB;
signal state_next : StateType;
signal msb : std_logic_vector(7 downto 0) := (others => '0');
signal msb_next : std_logic_vector(7 downto 0);
signal mid : std_logic_vector(7 downto 0) := (others => '0');
signal mid_next : std_logic_vector(7 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WAIT_MSB;
msb <= (others => '0');
mid <= (others => '0');
else
state <= state_next;
msb <= msb_next;
mid <= mid_next;
end if;
end if;
end process;
-- Next state logic
process(state, msb, mid, data8_in, valid8_in, ready24_in)
begin
state_next <= state;
msb_next <= msb;
mid_next <= mid;
valid24_out <= '0';
case state is
-- Wait for the LSB to arrive:
when S_WAIT_LSB =>
ready8_out <= ready24_in; -- ready for data from 8-bit side
data24_out <= msb & mid & data8_in;
if ( valid8_in = '1' and ready24_in = '1' ) then
valid24_out <= '1';
state_next <= S_WAIT_MSB;
end if;
-- Wait for the mid byte to arrive:
when S_WAIT_MID =>
ready8_out <= '1'; -- ready for data from 8-bit side
data24_out <= (others => 'X');
if ( valid8_in = '1' ) then
mid_next <= data8_in;
state_next <= S_WAIT_LSB;
end if;
-- Wait for the MSB to arrive:
when others =>
ready8_out <= '1'; -- ready for data from 8-bit side
data24_out <= (others => 'X');
if ( valid8_in = '1' ) then
msb_next <= data8_in;
state_next <= S_WAIT_MID;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
e94bbd9eb4a78328e6ecb3cf6bfe1321
| 0.626246 | 2.933723 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/comp_defs.vhd
| 2 | 17,530 |
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: comp_defs.vhd
---- Version: v3.0
-- Description: Component declarations for all black box netlists generated by
-- running COREGEN when XST elaborated the client core
----
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
--library dist_mem_gen_v6_3;
-- use dist_mem_gen_v6_3.all;
--
--library dist_mem_gen_v6_4;
-- use dist_mem_gen_v6_4.all;
library dist_mem_gen_v8_0_10;
use dist_mem_gen_v8_0_10.all;
package comp_defs is
--
-- -- component declaration
-- component dist_mem_gen_v6_3
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_2 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type : string;
-- -- attribute GENERATOR_DEFAULT : string;
-- --
-- -- attribute box_type of dist_mem_gen_v6_3 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_3 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_3.dist_mem_gen_v6_3";
-- --xcc include
--
-- -- component declaration for dist_mem_gen_v6_4
-- component dist_mem_gen_v6_4
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_4 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type of dist_mem_gen_v6_4 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_4 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_4.dist_mem_gen_v6_4";
--
-- --xcc include
-- 1/8/2013 added the latest version of dist_mem_gen_v8_0_10
-- component declaration for dist_mem_gen_v8_0_10
component dist_mem_gen_v8_0_10
-------------------
generic(
C_HAS_CLK : integer := 1;
C_READ_MIF : integer := 0;
C_HAS_QSPO : integer := 0;
C_ADDR_WIDTH : integer := 8;
C_WIDTH : integer := 15;
C_FAMILY : string := "virtex7"; -- "virtex6";
C_SYNC_ENABLE : integer := 1;
C_DEPTH : integer := 256;
C_HAS_QSPO_SRST : integer := 1;
C_MEM_INIT_FILE : string := "null.mif";
C_DEFAULT_DATA : string := "0";
------------------------
C_HAS_QDPO_CLK : integer := 0;
C_HAS_QDPO_CE : integer := 0;
C_PARSER_TYPE : integer := 1;
C_HAS_D : integer := 0;
C_HAS_SPO : integer := 0;
C_REG_A_D_INPUTS : integer := 0;
C_HAS_WE : integer := 0;
C_PIPELINE_STAGES : integer := 0;
C_HAS_QDPO_RST : integer := 0;
C_REG_DPRA_INPUT : integer := 0;
C_QUALIFY_WE : integer := 0;
C_HAS_QDPO_SRST : integer := 0;
C_HAS_DPRA : integer := 0;
C_QCE_JOINED : integer := 0;
C_MEM_TYPE : integer := 0;
C_HAS_I_CE : integer := 0;
C_HAS_DPO : integer := 0;
-- C_HAS_SPRA : integer := 0; -- removed from dist mem gen core
C_HAS_QSPO_CE : integer := 0;
C_HAS_QSPO_RST : integer := 0;
C_HAS_QDPO : integer := 0
-------------------------
);
port(
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0'); -- 2/12/2013
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0)
);
end component;
-- The following tells XST that dist_mem_gen_v8_0_10 is a black box which
-- should be generated. The command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
--xcc exclude
-- attribute box_type of dist_mem_gen_v8_0_10 : component is "black_box";
-- attribute GENERATOR_DEFAULT of dist_mem_gen_v8_0_10 : component is "generatecore com.xilinx.ip.dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10";
--xcc include
end comp_defs;
|
bsd-3-clause
|
9362805d7cef717ed125b7d25b746360
| 0.403765 | 4.069174 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/Pipeliner.vhdl
| 1 | 1,575 |
library ieee ;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity Pipeliner is
port(
clk, rst : in std_logic;
IF_en, ID_en, EX_en, MEM_en, MEM_read, WB_en : out std_logic;
Instruction_done : out std_logic
);
end;
architecture behav of Pipeliner is
begin
process (clk, rst)
variable ticks : natural := 1;
--constant CPI : natural := 8;
begin
if rst = '1' then
ticks := 1;
elsif rising_edge(clk) then
IF_en <= '0';
ID_en <= '0';
EX_en <= '0';
MEM_en <= '0';
MEM_read <= '0';
WB_en <= '0';
Instruction_done <= '0';
case ticks is
when 2 => IF_en <= '1';
printf("===== IF ===== \n");
when 3 => ID_en <= '1';
printf("===== ID ===== \n");
when 4 => EX_en <= '1';
printf("===== EX ===== \n");
when 5 => MEM_en <= '1';
printf("===== MEM ===== \n");
when 9 => MEM_read <= '1';
when 10 => WB_en <= '1';
printf("===== WB ===== \n");
when 11 => Instruction_done <= '1'; ticks := 0;
when others => null;
end case;
--if ticks = CPI then
--ticks := 0;
--end if;
ticks := ticks + 1;
end if;
end process;
end architecture;
|
gpl-3.0
|
73410f1f4e408e880f9317a0e1555ada
| 0.375873 | 3.908189 | false | false | false | false |
randomisresistance/whirlygig
|
whirlygig-cpld/whirlygig.vhdl
| 1 | 3,120 |
----------------------------------------------------------------------------------
-- Company: Crash Barrier Ltd
-- Engineer: Andy Green
--
-- Create Date: 20:43:12 11/05/2007
-- Design Name: "whirlygig" Random number generator
-- Module Name: whirlygig - Behavioral
-- Project Name: whirlygig
-- Target Devices:
-- Tool versions:
-- Description: Serial random number generator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity whirlygig is
Port (
pClock : in STD_LOGIC;
pSerialOut : out std_logic_vector(7 downto 0)
);
constant cCountResultWidth : integer := 8;
constant cCountInvsInRing : integer := 3;
constant cCountUnitsPool : integer := 16;
constant cCountAddressBits : integer := 4;
constant cCountAddressLatches : integer := (cCountResultWidth * cCountAddressBits);
constant cCountUnits : integer := cCountUnitsPool + cCountAddressLatches + cCountResultWidth;
constant cCountRingsPerBit : integer := 7;
end whirlygig;
architecture Behavioral of whirlygig is
attribute keep : string;
signal sInv : std_logic_vector((cCountUnits * cCountInvsInRing) - 1 downto 0);
signal sLatch : std_logic_vector(cCountUnits - 1 downto 0);
signal sSerialOut : std_logic_vector(cCountResultWidth - 1 downto 0);
signal ctr : std_logic_vector(3 downto 0); -- 7 24MHz clocks per sample
signal flip : STD_LOGIC;
attribute keep of
sInv
: signal is "true";
begin
processRings: process(
sInv
)
begin
for i in 0 to cCountUnits - 1 loop
sInv(i * cCountInvsInRing + 0) <= not sInv(i * cCountInvsInRing + cCountInvsInRing - 1);
sInv(i * cCountInvsInRing + 1) <= not sInv(i * cCountInvsInRing);
sInv(i * cCountInvsInRing + 2) <= not sInv(i * cCountInvsInRing + 1);
-- sInv(i * cCountInvsInRing + 3) <= not sInv(i * cCountInvsInRing + 2);
-- sInv(i * cCountInvsInRing + 4) <= not sInv(i * cCountInvsInRing + 3);
-- sInv(i * cCountInvsInRing + 5) <= not sInv(i * cCountInvsInRing + 4);
-- sInv(i * cCountInvsInRing + 6) <= not sInv(i * cCountInvsInRing + 5);
end loop;
end process processRings;
processSample: process(
pClock
)
variable j: integer := 0;
begin
if (pClock'EVENT and pClock = '1') then
for i in 0 to (sLatch'LENGTH - 1) loop
sLatch(i) <= sLatch((i - 1) mod (cCountUnits)) xor sInv(i * cCountInvsInRing + 1) xor flip;
end loop;
flip <= not flip;
ctr <= ctr + 1;
if (ctr = "1101") then
ctr <= "0000";
pSerialOut <= sSerialOut;
end if;
for i in 0 to (sSerialOut'LENGTH - 1) loop
sSerialOut(i) <= (
sSerialOut(i) xor (sLatch( CONV_INTEGER(
sLatch( cCountUnitsPool + i * cCountAddressBits + cCountAddressBits - 1 downto
cCountUnitsPool + i * cCountAddressBits)) )));
end loop;
end if;
end process processSample;
end Behavioral;
|
gpl-2.0
|
76c05c3f89078d0e0866f2d3a736ca91
| 0.661218 | 3.545455 | false | false | false | false |
makestuff/dvr-connectors
|
conv-48to8/vhdl/conv_48to8.vhdl
| 1 | 3,548 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_48to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 48-bit data coming in
data48_in : in std_logic_vector(47 downto 0);
valid48_in : in std_logic;
ready48_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_48to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3,
S_WRITE4,
S_WRITE5
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(39 downto 0) := (others => '0');
signal wip_next : std_logic_vector(39 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data48_in, valid48_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready48_out <= '0'; -- not ready for data from 48-bit side
data8_out <= wip(39 downto 32);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready48_out <= '0'; -- not ready for data from 48-bit side
data8_out <= wip(31 downto 24);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE3;
end if;
-- Write byte 3
when S_WRITE3 =>
ready48_out <= '0'; -- not ready for data from 48-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE4;
end if;
-- Write byte 4
when S_WRITE4 =>
ready48_out <= '0'; -- not ready for data from 48-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE5;
end if;
-- Write byte 5 (LSB)
when S_WRITE5 =>
ready48_out <= '0'; -- not ready for data from 48-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready48_out <= ready8_in; -- ready for data from 48-bit side
data8_out <= data48_in(47 downto 40);
valid8_out <= valid48_in;
if ( valid48_in = '1' and ready8_in = '1' ) then
wip_next <= data48_in(39 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
3db42297e22a855fef24629e0970a6a5
| 0.609639 | 2.901063 | false | false | false | false |
makestuff/dvr-connectors
|
conv-8to16/vhdl/tb_unit/conv_8to16_tb.vhdl
| 1 | 3,212 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_8to16_tb is
end entity;
architecture behavioural of conv_8to16_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
-- 16-bit interface signals
signal data16 : std_logic_vector(15 downto 0);
signal valid16 : std_logic;
signal ready16 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_8to16
port map(
clk_in => sysClk,
reset_in => '0',
data8_in => data8,
valid8_in => valid8,
ready8_out => ready8,
data16_out => data16,
valid16_out => valid16,
ready16_in => ready16
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data8 <= (others => 'Z');
valid8 <= '0';
ready16 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data8 <= to_4(inLine.all(1)) & to_4(inLine.all(2));
valid8 <= to_1(inLine.all(4));
ready16 <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(data16(15 downto 12)) & from_4(data16(11 downto 8)) & from_4(data16(7 downto 4)) & from_4(data16(3 downto 0)));
write(outLine, ' ');
write(outLine, valid16);
write(outLine, ' ');
write(outLine, ready8);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data8 <= (others => 'Z');
valid8 <= '0';
ready16 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
6d0872809cea042769db773a8c9835ba
| 0.674658 | 3.173913 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
| 1 | 86,743 |
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7Vfa20xUmA==
`protect end_protected
|
apache-2.0
|
3e1ee1ae668d1e9a0e9220ce2cb10911
| 0.952307 | 1.842616 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/rgb2dvi/src/rgb2dvi.vhd
| 1 | 7,780 |
-------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 source interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure (optional), encoding and serialization logic.
-- On the input side it has 24-bit RGB video data bus, pixel clock and synchronization
-- signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2dvi is
Generic (
kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kRstActiveHigh : boolean := true); --true, if active-high; false, if active-low
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
-- Auxiliary signals
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video in
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic; --pixel-clock recovered from the DVI interface
SerialClk : in std_logic); -- 5x PixelClk
end rgb2dvi;
architecture Behavioral of rgb2dvi is
type dataOut_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type dataOutRaw_t is array (2 downto 0) of std_logic_vector(9 downto 0);
signal pDataOut : dataOut_t;
signal pDataOutRaw : dataOutRaw_t;
signal pVde, pC0, pC1 : std_logic_vector(2 downto 0);
signal aRst_int, aPixelClkLckd : std_logic;
signal PixelClkIO, SerialClkIO, aRstLck, pRstLck : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
-- Generate SerialClk internally?
ClockGenInternal: if kGenerateSerialClk generate
ClockGenX: entity work.ClockGen
Generic map (
kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive => kClkPrimitive) -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port map (
PixelClkIn => PixelClk,
PixelClkOut => PixelClkIO,
SerialClk => SerialClkIO,
aRst => aRst_int,
aLocked => aPixelClkLckd);
--TODO revise this
aRstLck <= not aPixelClkLckd;
end generate ClockGenInternal;
ClockGenExternal: if not kGenerateSerialClk generate
PixelClkIO <= PixelClk;
SerialClkIO <= SerialClk;
aRstLck <= aRst_int;
end generate ClockGenExternal;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRstLck,
OutClk => PixelClk,
oRst => pRstLck);
-- Clock needs no encoding, send a pulse
ClockSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Clk_p,
sDataOut_n => TMDS_Clk_n,
--Encoded parallel data (raw)
pDataOut => "1111100000",
aRst => pRstLck);
DataEncoders: for i in 0 to 2 generate
DataEncoder: entity work.TMDS_Encoder
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
pDataOutRaw => pDataOutRaw(i),
aRst => pRstLck,
pDataOut => pDataOut(i),
pC0 => pC0(i),
pC1 => pC1(i),
pVde => pVde(i)
);
DataSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Data_p(i),
sDataOut_n => TMDS_Data_n(i),
--Encoded parallel data (raw)
pDataOut => pDataOutRaw(i),
aRst => pRstLck);
end generate DataEncoders;
-- DVI Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason vid_data is packed in RBG order
pDataOut(2) <= vid_pData(23 downto 16); -- red is channel 2
pDataOut(1) <= vid_pData(15 downto 8); -- green is channel 1
pDataOut(0) <= vid_pData(7 downto 0); -- blue is channel 0
pC0(2 downto 1) <= (others => '0'); -- default is low for control signals
pC1(2 downto 1) <= (others => '0'); -- default is low for control signals
pC0(0) <= vid_pHSync; -- channel 0 carries control signals too
pC1(0) <= vid_pVSync; -- channel 0 carries control signals too
pVde <= vid_pVDE & vid_pVDE & vid_pVDE; -- all of them are either active or blanking at once
end Behavioral;
|
bsd-3-clause
|
ac312d25123d78d4a61b916ca99d156d
| 0.662082 | 4.373243 | false | false | false | false |
makestuff/dvr-connectors
|
conv-40to8/vhdl/conv_40to8.vhdl
| 1 | 3,295 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_40to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 40-bit data coming in
data40_in : in std_logic_vector(39 downto 0);
valid40_in : in std_logic;
ready40_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_40to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3,
S_WRITE4
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(31 downto 0) := (others => '0');
signal wip_next : std_logic_vector(31 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data40_in, valid40_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(31 downto 24);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE3;
end if;
-- Write byte 3
when S_WRITE3 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE4;
end if;
-- Write byte 4 (LSB)
when S_WRITE4 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready40_out <= ready8_in; -- ready for data from 40-bit side
data8_out <= data40_in(39 downto 32);
valid8_out <= valid40_in;
if ( valid40_in = '1' and ready8_in = '1' ) then
wip_next <= data40_in(31 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
32a98baff14667d5fb1db708cc6be90c
| 0.615781 | 2.921099 | false | false | false | false |
tmeissner/cryptocores
|
cbcdes/rtl/vhdl/cbcdes.vhd
| 1 | 4,549 |
-- ======================================================================
-- CBC-DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
-- Revision 0.1 2011/09/23
-- Initial release, incomplete and may contain bugs
-- Revision 0.2 2011/10/06
-- corrected some bugs which were found while testing cbc ability
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity cbcdes is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : in std_logic_vector(0 to 63); -- key input
iv_i : in std_logic_vector(0 to 63); -- iv input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- ready to encrypt/decrypt
data_o : out std_logic_vector(0 to 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity cbcdes;
architecture rtl of cbcdes is
signal s_mode : std_logic;
signal s_des_mode : std_logic;
signal s_start : std_logic;
signal s_key : std_logic_vector(0 to 63);
signal s_des_key : std_logic_vector(0 to 63);
signal s_iv : std_logic_vector(0 to 63);
signal s_datain : std_logic_vector(0 to 63);
signal s_datain_d : std_logic_vector(0 to 63);
signal s_des_datain : std_logic_vector(0 to 63);
signal s_des_dataout : std_logic_vector(0 to 63);
signal s_dataout : std_logic_vector(0 to 63);
begin
s_des_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
s_dataout xor data_i when s_mode = '0' and start_i = '0' else
data_i;
data_o <= s_iv xor s_des_dataout when s_mode = '1' and s_start = '1' else
s_datain_d xor s_des_dataout when s_mode = '1' and s_start = '0' else
s_des_dataout;
s_des_key <= key_i when start_i = '1' else s_key;
s_des_mode <= mode_i when start_i = '1' else s_mode;
inputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_mode <= '0';
s_start <= '0';
s_key <= (others => '0');
s_iv <= (others => '0');
s_datain <= (others => '0');
s_datain_d <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
s_start <= start_i;
s_datain <= data_i;
s_datain_d <= s_datain;
if (start_i = '1') then
s_mode <= mode_i;
s_key <= key_i;
s_iv <= iv_i;
end if;
end if;
end if;
end process inputregister;
outputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_dataout <= (others => '0');
elsif (rising_edge(clk_i)) then
if (valid_o = '1' and accept_i = '1') then
s_dataout <= s_des_dataout;
end if;
end if;
end process outputregister;
i_des : entity work.des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_des_mode,
key_i => s_des_key,
data_i => s_des_datain,
valid_i => valid_i,
accept_o => accept_o,
data_o => s_des_dataout,
valid_o => valid_o,
accept_i => accept_i
);
end architecture rtl;
|
gpl-2.0
|
03f9617519ab434f809278ae2b0c057d
| 0.541218 | 3.428033 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/leds.vhdl
| 1 | 1,122 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
entity mmio_leds is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- leds
leds : out std_logic_vector(7 downto 0)
);
end mmio_leds ;
architecture mmio of mmio_leds is
constant reading : std_logic := '0';
constant writing : std_logic := '1';
signal data_out : word_t;
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
process(clk) begin
if rising_edge(clk) and en = '1' and size /= "00" then
case wr is
when reading => data_out <= NEG_ONE;
when writing => leds <= din(7 downto 0);
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end mmio;
|
gpl-3.0
|
43bc3056fc5cac88887dcc96a5410570
| 0.508021 | 3.642857 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/mips_vga_tb.vhdl
| 1 | 4,934 |
-- SKIP because sb $v0, $gp; sb $v1, $gp doesn't read $v0's value back
-- This is the top level MIPS architecture
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity mips_vga_tb is
end;
architecture struct of mips_vga_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
component mem is
generic (ROM : string := "");
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic;
-- VGA I/O
vgaclk, rst : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic;
-- LEDs
leds : out std_logic_vector(7 downto 0);
-- Push buttons
buttons : in std_logic_vector(3 downto 0);
-- DIP Switch IO
switch : in std_logic_vector(7 downto 0)
);
end component;
component cpu is
generic(PC_ADD : natural := 4;
SINGLE_ADDRESS_SPACE : boolean := false);
port(
clk : in std_logic;
rst : in std_logic;
-- Register File
readreg1, readreg2 : out reg_t;
writereg: out reg_t;
regWriteData: out word_t;
regReadData1, regReadData2 : in word_t;
regWrite : out std_logic;
-- Memory
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t;
-- Debug info
instruction : out instruction_t
);
end component;
signal readreg1, readreg2 : reg_t;
signal writereg: reg_t;
signal regWriteData: word_t;
signal regReadData1, regReadData2 : word_t;
signal regWrite : std_logic;
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
signal sysclk : std_logic := '0';
signal regrst : std_logic := '0';
signal rst : std_logic := '0';
signal online : boolean := true;
signal cpu_regWrite : std_logic;
signal cpu_readreg1 : reg_t;
signal cpu_readreg2 : reg_t;
signal test_readreg1 : reg_t;
signal test_readreg2 : reg_t;
alias clk is sysclk;
-- VGA
-- nothing yet
begin
regfile_inst: regFile port map (
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg,
writeData => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => clk,
rst => regrst,
regWrite => regWrite
);
mem_bus: mem
generic map (ROM => "vga")
port map (
addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
clk => clk,
vgaclk => '0', rst => '1',
r => open, g => open, b => open,
hsync => open, vsync => open,
leds => open,
-- Push buttons
buttons => B"0000",
-- DIP Switch IO
switch => B"1010_1010"
);
cpu_inst: cpu
generic map(SINGLE_ADDRESS_SPACE => false)
port map (
clk => clk,
rst => rst,
-- Register File
readreg1 => cpu_readreg1, readreg2 => cpu_readreg2,
writereg => writereg,
regWriteData => regWriteData,
regReadData1 => regReadData1, regReadData2 => regReadData2,
regWrite => cpu_RegWrite,
-- Memory
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr,
-- Debug info
instruction => open
);
regwrite <= cpu_RegWrite when online else '0';
readreg1 <= cpu_readreg1 when online else test_readreg1;
readreg2 <= cpu_readreg2 when online else test_readreg2;
test: process begin
wait for 4 ns;
rst <= '1';
wait for 4 ns;
rst <= '0';
wait for 4 ns;
wait for 1600 ns;
rst <= '0';
online <= false;
wait for 20 ns;
test_readreg1 <= GP;
test_readreg2 <= V0;
wait for 16 ns;
assert regReadData1 = X"1000_0000" report
ANSI_RED & "[$gp] Failed to ori. 0x1000_0000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
assert regReadData2 = X"0000_00" & B"0001_1100" report
ANSI_RED & "[$v1] Failed to ori. 0x1C /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
wait;
end process;
clkproc: process begin
sysclk <= not sysclk; wait for 1 ns; if not online then sysclk <= '0'; wait; end if;
end process;
end struct;
|
gpl-3.0
|
3ce1193bff2cdac23b69defd491c2cd5
| 0.539116 | 3.810039 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Video_PR_1.0/hdl/Video_PR_v1_0.vhd
| 1 | 6,150 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Video_PR_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end Video_PR_v1_0;
architecture arch_imp of Video_PR_v1_0 is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of RGB_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN DATA";
ATTRIBUTE X_INTERFACE_INFO of VDE_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO of HS_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN HSYNC";
ATTRIBUTE X_INTERFACE_INFO of VS_IN: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_IN VSYNC";
ATTRIBUTE X_INTERFACE_INFO of RGB_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT DATA";
ATTRIBUTE X_INTERFACE_INFO of VDE_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO of HS_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT HSYNC";
ATTRIBUTE X_INTERFACE_INFO of VS_OUT: SIGNAL is "xilinx.com:interface:vid_io:1.0 RGB_OUT VSYNC";
-- component declaration
component Video_PR_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Video_PR_v1_0_S_AXI;
begin
-- Instantiation of Axi Bus Interface S_AXI
Video_PR_v1_0_S_AXI_inst : Video_PR_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
--video signals
RGB_IN => RGB_IN,
VDE_IN => VDE_IN,
HS_IN => HS_IN,
VS_IN => VS_IN,
-- additional ports here
RGB_OUT => RGB_OUT,
VDE_OUT => VDE_OUT,
HS_OUT => HS_OUT,
VS_OUT => VS_OUT,
PIXEL_CLK => PIXEL_CLK,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
bsd-3-clause
|
adc831784fb5d21d6df0d632159a6155
| 0.637724 | 2.762803 | false | false | false | false |
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