repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
makestuff/dvr-connectors
|
conv-40to8/vhdl/tb_unit/conv_40to8_tb.vhdl
| 1 | 3,331 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_40to8_tb is
end entity;
architecture behavioural of conv_40to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 40-bit interface signals
signal data40 : std_logic_vector(39 downto 0);
signal valid40 : std_logic;
signal ready40 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_40to8
port map(
clk_in => sysClk,
reset_in => '0',
data40_in => data40,
valid40_in => valid40,
ready40_out => ready40,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data40 <= (others => 'Z');
valid40 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data40 <= to_4(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3)) & to_4(inLine.all(4)) & to_4(inLine.all(5)) & to_4(inLine.all(6)) & to_4(inLine.all(7)) & to_4(inLine.all(8)) & to_4(inLine.all(9)) & to_4(inLine.all(10));
valid40 <= to_1(inLine.all(12));
ready8 <= to_1(inLine.all(14));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready40);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data40 <= (others => 'Z');
valid40 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
a616cec8fdb7ae087a08359571376da3
| 0.670669 | 3.095725 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vactcapofk.vhd
| 1 | 1,204 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vactcapofk is
port (
clock : in std_logic;
Vactofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Uofk : in std_logic_vector(31 downto 0);
Vactcapofk : out std_logic_vector(31 downto 0)
);
end k_ukf_Vactcapofk;
architecture struct of k_ukf_Vactcapofk is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => M,
datab => Uofk,
result => Z);
M2 : k_ukf_add port map
( clock => clock,
dataa => Vactofk,
datab => Z,
result => Vactcapofk);
end struct;
|
gpl-2.0
|
e1ceff4d9ae947150b9d9bda374b2263
| 0.58887 | 3.025126 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/sim/I16ToSGL_convert_BAEB0EFF4B15497ABBB37471944D9EC5.vhd
| 1 | 10,342 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY I16ToSGL_convert_BAEB0EFF4B15497ABBB37471944D9EC5 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END I16ToSGL_convert_BAEB0EFF4B15497ABBB37471944D9EC5;
ARCHITECTURE I16ToSGL_convert_BAEB0EFF4B15497ABBB37471944D9EC5_arch OF I16ToSGL_convert_BAEB0EFF4B15497ABBB37471944D9EC5 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF I16ToSGL_convert_BAEB0EFF4B15497ABBB37471944D9EC5_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 16,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 16,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 16,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 16,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 16,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 16,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END I16ToSGL_convert_BAEB0EFF4B15497ABBB37471944D9EC5_arch;
|
apache-2.0
|
db44bceb997980810204c59ec94f9a21
| 0.63276 | 3.201858 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vrefcapofkplusone.vhd
| 1 | 1,853 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vrefcapofkplusone is
port (
clock : in std_logic;
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
Wofmofzero : in std_logic_vector(31 downto 0);
Wofmofone : in std_logic_vector(31 downto 0);
Wofmoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vrefcapofkplusone;
architecture struct of k_ukf_Vrefcapofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z4,Z5,Z6,Z7 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofzero,
datab => Vsigrefofkofzero,
result => Z4);
M2 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofone,
datab => Vsigrefofkofone,
result => Z5);
M3 : k_ukf_mult port map
( clock => clock,
dataa => Wofmoftwo,
datab => Vsigrefofkoftwo,
result => Z6);
M4 : k_ukf_add port map
( clock => clock,
dataa => Z4,
datab => Z5,
result => Z7);
M5 : k_ukf_add port map
( clock => clock,
dataa => Z7,
datab => Z6,
result => Vrefcapofkplusone);
end struct;
|
gpl-2.0
|
211f2265cb1a261a4ce0c9f1ba17a443
| 0.589315 | 3.233857 | false | false | false | false |
makestuff/dvr-connectors
|
conv-24to8/vhdl/conv_24to8.vhdl
| 1 | 3,150 |
--
-- Copyright (C) 2013 Joel Pérez Izquierdo
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Modified from conv_16to8.vhdl by Chris McClelland
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_24to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 24-bit data coming in
data24_in : in std_logic_vector(23 downto 0);
valid24_in : in std_logic;
ready24_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_24to8 is
type StateType is (
S_WRITE_MSB,
S_WRITE_MID,
S_WRITE_LSB
);
signal state : StateType := S_WRITE_MSB;
signal state_next : StateType;
signal lsb : std_logic_vector(7 downto 0) := (others => '0');
signal lsb_next : std_logic_vector(7 downto 0);
signal mid : std_logic_vector(7 downto 0) := (others => '0');
signal mid_next : std_logic_vector(7 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE_MSB;
lsb <= (others => '0');
mid <= (others => '0');
else
state <= state_next;
lsb <= lsb_next;
mid <= mid_next;
end if;
end if;
end process;
-- Next state logic
process(state, lsb, mid, data24_in, valid24_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
lsb_next <= lsb;
mid_next <= mid;
case state is
-- Write the LSB and return to MSB:
when S_WRITE_LSB =>
ready24_out <= '0'; -- not ready for data from 24-bit side
data8_out <= lsb;
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE_MSB;
end if;
-- Write the mid byte and move on to LSB
when S_WRITE_MID =>
ready24_out <= '0'; -- not ready for data from 24-bit side
data8_out <= mid;
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE_LSB;
end if;
-- When a word arrives, write the MSB and move on to mid byte:
when others =>
ready24_out <= ready8_in; -- ready for data from 24-bit side
data8_out <= data24_in(23 downto 16);
valid8_out <= valid24_in;
if ( valid24_in = '1' and ready8_in = '1' ) then
mid_next <= data24_in(15 downto 8);
lsb_next <= data24_in(7 downto 0);
state_next <= S_WRITE_MID;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
6a9024fe78ca9862d15f7e213971f8da
| 0.629724 | 2.967955 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodJSTK_v1_0/src/PmodJSTK_axi_quad_spi_0_0/synth/PmodJSTK_axi_quad_spi_0_0.vhd
| 1 | 16,131 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_6;
USE axi_quad_spi_v3_2_6.axi_quad_spi;
ENTITY PmodJSTK_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END PmodJSTK_axi_quad_spi_0_0;
ARCHITECTURE PmodJSTK_axi_quad_spi_0_0_arch OF PmodJSTK_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodJSTK_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF PmodJSTK_axi_quad_spi_0_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF PmodJSTK_axi_quad_spi_0_0_arch : ARCHITECTURE IS "PmodJSTK_axi_quad_spi_0_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF PmodJSTK_axi_quad_spi_0_0_arch: ARCHITECTURE IS "PmodJSTK_axi_quad_spi_0_0,axi_quad_spi,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Async_Clk=1,C_FAMILY=artix7,C_SUB_FAMILY=zynq,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=48,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=0,C_USE_STARTUP=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "artix7",
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 48,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '0',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END PmodJSTK_axi_quad_spi_0_0_arch;
|
bsd-3-clause
|
e90ad4c6eb37b546c973770f9613c19d
| 0.650859 | 2.992764 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_cpu_mem_cntrl.vhd
| 1 | 5,930 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 17, 2017
--! @brief Contains the entity and architecture of the
--! CPU's Noncacheable Memory Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_cpu_pack.all;
--! The Noncacheable Memory Controller is an alternative to the
--! Cache Controller. As its name suggests, the Noncacheable Memory
--! Controller should be instantiated if the entire address space
--! needs to be noncacheable.
entity plasoc_cpu_mem_cntrl is
generic (
-- CPU parameters.
cpu_address_width : integer := 16; --! Defines the address width of the CPU. This should normally be equal to the CPU's width.
cpu_data_width : integer := 32 --! Defines the data width of the CPU. This should normally be equal to the CPU's width.
);
port (
-- Global interface.
clock : in std_logic; --! Clock. Tested with 50 MHz.
resetn : in std_logic; --! Reset on low.
-- CPU interface.
cpu_address : in std_logic_vector(cpu_address_width-1 downto 0); --! The requested address of the next word to either be written to or read from memory.
cpu_in_data : in std_logic_vector(cpu_data_width-1 downto 0); --! The word that the CPU is writing.
cpu_out_data : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! The word that is written to the CPU.
cpu_strobe : in std_logic_vector(cpu_data_width/8-1 downto 0); --! Determines whether a the CPU is writing or reading a word. Each bit that is high enables writing for the corresponding byte in cpu_out_data.
cpu_pause : out std_logic; --! Stalls the CPU.
-- Cache interface.
cache_cacheable : out std_logic; --! Indicates whether the requested address of the CPU is cacheable or noncacheable. Should always be noncacheable.
-- Memory interface.
mem_in_address : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0'); --! The requested address sent to the read memory controller.
mem_in_data : in std_logic_vector(cpu_data_width-1 downto 0); --! The word read from the read memory controller.
mem_in_enable : out std_logic; --! Enables the operation of the read memory controller.
mem_in_valid : in std_logic; --! Indicates the read memory controller has a valid word on mem_in_data.
mem_in_ready : out std_logic; --! Indicates the cache is ready to sample a word from mem_in_data.
mem_out_address : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0'); --! The requested address sent to the write memory controller.
mem_out_data : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! The word written to the write memory controller.
mem_out_strobe : out std_logic_vector(cpu_data_width/8-1 downto 0) := (others=>'0'); --! Each bit that is high enables writing for the corresponding byte in mem_out_data.
mem_out_enable : out std_logic := '0'; --! Enables the operation of the write memory controller.
mem_out_valid : out std_logic; --! Indicates the cache has a valid word on mem_out_data.
mem_out_ready : in std_logic --! Indicates the read memory controller is ready to sample a word from mem_out_data.
);
end plasoc_cpu_mem_cntrl;
architecture Behavioral of plasoc_cpu_mem_cntrl is
subtype address_type is std_logic_vector(cpu_address_width-1 downto 0);
subtype strobe_type is std_logic_vector(cpu_data_width/8-1 downto 0);
subtype flag_type is std_logic;
signal cpu_pause_enable : boolean := False;
signal cpu_write_access : boolean;
signal mem_in_ready_buff : std_logic := '0';
signal mem_out_valid_buff : std_logic := '0';
begin
cache_cacheable <= '0';
cpu_pause <= '1' when cpu_pause_enable else '0';
cpu_write_access <= True when or_reduce(cpu_strobe)/='0' else False;
mem_in_ready <= mem_in_ready_buff;
mem_out_valid <= mem_out_valid_buff;
process (clock)
variable write_occurred : boolean;
variable read_occurred : boolean;
procedure reset_state is
begin
mem_in_ready_buff <= '0';
mem_out_valid_buff <= '0';
mem_out_enable <= '0';
mem_in_enable <= '0';
cpu_pause_enable <= False;
end procedure;
begin
if rising_edge(clock) then
if resetn='0' then
reset_state;
else
if not cpu_pause_enable then
cpu_pause_enable <= True;
if cpu_write_access then
mem_out_address <= cpu_address;
mem_out_strobe <= cpu_strobe;
mem_out_enable <= '1';
mem_out_valid_buff <= '1';
mem_out_data <= cpu_in_data;
else
mem_in_address <= cpu_address;
mem_in_enable <= '1';
mem_in_ready_buff <= '1';
end if;
else
write_occurred := mem_out_valid_buff='1' and mem_out_ready='1';
read_occurred := mem_in_valid='1' and mem_in_ready_buff='1';
if not cpu_write_access and read_occurred then
cpu_out_data <= mem_in_data;
end if;
if write_occurred or read_occurred then
reset_state;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
8ab41240465794e63c4d0ab2ac0975cb
| 0.578921 | 4.025798 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/uart_tb.vhdl
| 1 | 2,466 |
-- SKIP FIXME: Niklas remove this line, when the test succeeds
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity uart_tb is
end uart_tb;
architecture behav of uart_tb is
component uart_tx
port(
clk : in std_logic;
reset : in std_logic;
tx_start : in std_logic;
baud_tick : in std_logic;
tx_data : in std_logic_vector( 7 downto 0 );
tx_done_tick : out std_logic;
tx : out std_logic
);
end component;
component uart_rx
port (
clk : in std_logic;
reset : in std_logic;
rx : in std_logic;
baud_tick : in std_logic;
rx_done_tick : out std_logic;
rx_data : out std_logic_vector( 7 downto 0 )
);
end component;
type state_t is (idle, received, transmit);
signal rx_data: std_logic_vector(7 downto 0);
signal rx_done_tick, tx_done_tick: std_logic;
signal tx_data_next, tx_data: std_logic_vector(7 downto 0);
signal tx_start: std_logic;
signal reset, rx, tx: std_logic;
signal state_next, state: state_t;
signal clk : std_logic; -- system clock
signal baud_tick : std_logic; -- 19200
begin
tx_instance: uart_tx port map (clk, reset, tx_start, baud_tick, tx_data, tx_done_tick, tx);
rx_instance: uart_rx port map (clk, reset, rx, baud_tick, rx_done_tick, rx_data);
clk_process :process
begin
clk <= '0';
wait for 1 ns; --for 0.5 ns signal is '0'.
clk <= '1';
wait for 1 ns; --for next 0.5 ns signal is '1'.
end process;
baud_tick_process :process
begin
baud_tick <= '0';
wait for 1 ns; --for 0.5 ns signal is '0'.
baud_tick <= '1';
wait for 1 ns; --for next 0.5 ns signal is '1'.
end process;
reset_ctrl: process (clk, reset) is
begin
if reset = '1' then
tx_data <= "00000000";
elsif (clk'EVENT and (clk = '1')) then
tx_data <= tx_data_next;
end if;
end process;
test: process (state, rx_done_tick, tx_done_tick) is
begin
state_next <= state;
case(state) is
when idle =>
if(rx_done_tick = '1') then
tx_data_next <= rx_data;
tx_start <= '0';
state_next <= received;
end if;
when received =>
tx_start <= '1';
state_next <= transmit;
when transmit =>
if(tx_done_tick = '1') then
tx_start <= '0';
state_next <= idle;
end if;
end case;
end process;
end behav;
|
gpl-3.0
|
d8a5c4a6e2ae8bcabb0e889063b23506
| 0.593674 | 2.981862 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_s2mm_sg_if.vhd
| 4 | 81,371 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
bsd-3-clause
|
345cfa443f50ae7725b3e849e8bde2c0
| 0.438178 | 4.443589 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP3_roulette_vhdl/timer.vhd
| 2 | 6,400 |
-- file: timer.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 100.000 0.000 50.0 300.000 50.000
-- CLK_OUT2 3.125 0.000 50.0 300.000 50.000
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 100.000 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity timer is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end timer;
architecture xilinx of timer is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "timer,clk_wiz_v1_8,{component_name=timer,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk2x : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 16.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => TRUE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "2X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk2x);
CLK_OUT1 <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkdv);
end xilinx;
|
gpl-2.0
|
3964b4158cbf5d9940c791b07964a6f5
| 0.574063 | 4.238411 | false | false | false | false |
Ttl/pic16f84
|
testbenches/cpu_core_testio_tb.vhd
| 1 | 2,105 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Testbench for testing processors IO.
-- This test bench reads and writes and also check
-- the correct operation of btfsc instruction
ENTITY cpu_core_testio IS
END cpu_core_testio;
ARCHITECTURE behavior OF cpu_core_testio IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
PORT(
clk : IN std_logic;
reset : IN std_logic;
porta : INOUT std_logic_vector(4 downto 0);
portb : INOUT std_logic_vector(7 downto 0);
pc_out : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal porta : std_logic_vector(4 downto 0);
signal portb : std_logic_vector(7 downto 0);
signal pc_out : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cpu_core
Generic map(instruction_file => "scripts/instructions_testio.mif")
PORT MAP (
clk => clk,
reset => reset,
porta => porta,
portb => portb,
pc_out => pc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
porta <= "HHHHH";
portb <= "HHHHHHHH";
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*15;
assert porta(2 downto 0) = "101" severity failure;
assert portb(2 downto 0) = "111" severity failure;
wait for clk_period;
portb <= "LLHLLLLL";
wait for clk_period*10;
assert unsigned(pc_out) > 24 severity failure;
reset <= '1';
wait for clk_period;
assert false report "Succesfully completed" severity failure;
end process;
END;
|
lgpl-3.0
|
b0557368000dd26477f1ea5adf96be63
| 0.604751 | 3.738899 | false | true | false | false |
a3f/r3k.vhdl
|
vhdl/arch/JumpRegMux.vhdl
| 1 | 691 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity JumpRegMux is
port (
JumpReg: in ctrl_t;
reg1data : in addr_t;
JumpDirMux : in addr_t;
output : out addr_t
);
end entity;
architecture behav of JumpRegMux is
begin
output <= reg1data when JumpReg = '1' else JumpDirMux;
printer: process(JumpReg, reg1data, JumpDirMux)
variable output : addr_t;
begin
if JumpReg = '1' then
output := reg1data;
else
output := JumpDirMux;
end if;
printf("pc_new = %s\n", output);
end process;
end architecture behav;
|
gpl-3.0
|
b93daa743731e580b1786a4aece47f26
| 0.580318 | 3.796703 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/lib_fifo_v1_0_4/hdl/src/vhdl/async_fifo_fg.vhd
| 4 | 124,572 |
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_1 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
--library lib_fifo_v1_0_4;
--use lib_fifo_v1_0_4.lib_fifo_pkg.all;
--use lib_fifo_v1_0_4.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
|
bsd-3-clause
|
18e536024e548813246ac16670c4f0d5
| 0.402137 | 3.928601 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/ponq/Video_Box.vhd
| 1 | 7,490 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Alexander West
--
-- Create Date: 03/23/2017
-- Design Name: PYNQ PONQ
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
--
-- This handles display logic for the Pynq Ponq game.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.filter_lib.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
C_S_AXI_DATA_WIDTH : integer := 32; -- Width of S_AXI data bus
C_S_AXI_ADDR_WIDTH : integer := 11 -- Width of S_AXI address bus
);
port (
-- AXI interface ports
S_AXI_ARESETN : in std_logic; -- Reset the registers
slv_reg_wren : in std_logic; -- Write enable
slv_reg_rden : in std_logic; -- Read enable
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); -- Selector for writing individual bytes
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- Write Address
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Write Data
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- Read Address
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Read Data
-- Bus Clock
S_AXI_ACLK : in std_logic;
-- Pixel Clock
PIXEL_CLK : in std_logic;
-- Video Input
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data
VDE_IN : in std_logic; -- Active video Flag
HS_IN : in std_logic; -- Horizontal sync signal
VS_IN : in std_logic; -- Veritcal sync signal
-- Input Coordinates
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0);
-- Video Output
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data
VDE_OUT : out std_logic; -- Active video Flag
HS_OUT : out std_logic; -- Horizontal sync signal
VS_OUT : out std_logic -- Veritcal sync signal
);
end Video_Box;
architecture PYNQ_PONQ of Video_Box is
-- Bus Constants
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32) + 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH - ADDR_LSB - 1;
-- Video Interface
signal vid_in_reg, vid_mod, vid_out_reg : rgb_interface_t;
signal X_Coord_reg, Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
-- Balls
constant NUM_BALLS : natural := 12; -- 16 is too many
signal balls_temp : ball_vector_t(NUM_BALLS-1 downto 0);
-- Registers
constant NUM_REG : natural := NUM_BALLS * 5;
subtype reg_t is std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
type reg_array_t is array(natural range <>) of reg_t;
signal slv_reg : reg_array_t(NUM_REG-1 downto 0);
begin
-- I/O Buffering
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
vid_in_reg.rgb <= RGB_IN;
vid_in_reg.vde <= VDE_IN;
vid_in_reg.hs <= HS_IN;
vid_in_reg.vs <= VS_IN;
-- Coordinates
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
-- Video Output Signals
vid_out_reg <= vid_mod;
end if;
end process;
-- Convert Registers into ball_t
ball_in:
for ball in 0 to NUM_BALLS-1 generate
balls_temp(ball).x <= unsigned(slv_reg(ball*5 + 0)(ball_t.x'range));
balls_temp(ball).y <= unsigned(slv_reg(ball*5 + 1)(ball_t.y'range));
balls_temp(ball).w <= unsigned(slv_reg(ball*5 + 2)(ball_t.w'range));
balls_temp(ball).h <= unsigned(slv_reg(ball*5 + 3)(ball_t.h'range));
balls_temp(ball).color <= slv_reg(ball*5 + 4)(ball_t.color'range);
end generate;
-- Filter Module
PONQ : entity work.pynq_ponq(Behavioral)
generic map (
NUM_BALLS => NUM_BALLS
)
port map (
-- Video Interface
vid_i => vid_in_reg,
vid_o => vid_mod,
-- Pixel Coordinates
x_pos => X_Coord_reg,
y_pos => Y_Coord_reg,
-- Register Inputs
balls => balls_temp,
-- Reference Clock
PIXEL_CLK => PIXEL_CLK
);
-- Module Output
RGB_OUT <= vid_out_reg.rgb;
VDE_OUT <= vid_out_reg.vde;
HS_OUT <= vid_out_reg.hs;
VS_OUT <= vid_out_reg.vs;
-- Register Bus Logic
-- Register Input Logic
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg <= (others => (others => '0'));
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-- Default Value
slv_reg <= slv_reg;
-- For each register
--for reg in 0 to (NUM_REG-1) loop
if (slv_reg_wren = '1') then
--if ( loc_addr = std_logic_vector(to_unsigned(reg, ADDR_LSB + OPT_MEM_ADDR_BITS + 1)) ) then
if ( unsigned(loc_addr) < NUM_REG ) then
-- Respective byte enables are asserted as per write strobes
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
slv_reg(to_integer(unsigned(loc_addr)))(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--else
-- slv_reg <= slv_reg;
end if;
--end if; -- loc_addr = reg
end if; -- slv_reg_wren = '1'
--end loop; -- reg in 0 to (NUM_REG-1)
end if; -- S_AXI_ARESETN = '0'
end if; -- rising_edge(S_AXI_ACLK)
end process;
-- Register Output Logic
process (slv_reg, S_AXI_ARESETN, slv_reg_rden, axi_araddr)
variable loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-- -- Default data out
-- reg_data_out <= (others => '0');
-- for reg in 0 to (NUM_REG-1) loop
-- if ( unsigned(loc_addr) = to_unsigned(reg, ADDR_LSB + OPT_MEM_ADDR_BITS + 1) ) then
-- reg_data_out <= slv_reg(to_integer(unsigned(loc_addr)));
-- end if;
-- end loop;
if unsigned(loc_addr) < NUM_REG then
reg_data_out <= slv_reg(to_integer(unsigned(loc_addr)));
else
reg_data_out <= (others=>'0');
end if;
end process;
end PYNQ_PONQ;
--End Pynq Ponq Top-Level Module
|
bsd-3-clause
|
30cf9e1691b7fa2f7065f1441b3eb8e4
| 0.538585 | 3.526365 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_axi4_full2lite_pack.vhd
| 1 | 6,253 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Full2Lite Core. Please refer to the documentation
--! in plasoc_axi4_full2lite.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package plasoc_axi4_full2lite_pack is
constant axi_burst_fixed : std_logic_vector := "00";
constant axi_burst_incr : std_logic_vector := "01";
component plasoc_axi4_full2lite is
generic (
axi_slave_id_width : integer := 1;
axi_address_width : integer := 32;
axi_data_width : integer := 32);
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
s_axi_awlen : in std_logic_vector(8-1 downto 0);
s_axi_awsize : in std_logic_vector(3-1 downto 0);
s_axi_awburst : in std_logic_vector(2-1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(4-1 downto 0);
s_axi_awprot : in std_logic_vector(3-1 downto 0);
s_axi_awqos : in std_logic_vector(4-1 downto 0);
s_axi_awregion : in std_logic_vector(4-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
s_axi_arlen : in std_logic_vector(8-1 downto 0);
s_axi_arsize : in std_logic_vector(3-1 downto 0);
s_axi_arburst : in std_logic_vector(2-1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(4-1 downto 0);
s_axi_arprot : in std_logic_vector(3-1 downto 0);
s_axi_arqos : in std_logic_vector(4-1 downto 0);
s_axi_arregion : in std_logic_vector(4-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rresp : in std_logic_vector(1 downto 0)
);
end component;
end package;
|
mit
|
9d7bd82aa35bb0727882d59519df0383
| 0.3747 | 4.990423 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/cpu_no_IF_tb.vhdl
| 1 | 8,001 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
use work.memory_map.all;
entity cpu_no_IF_tb is
end;
architecture struct of cpu_no_IF_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
signal readreg1, readreg2 : reg_t := R0;
signal writereg: reg_t := R0;
signal regReadData1, regReadData2, regWriteData : word_t := ZERO;
signal regWrite : ctrl_t := '0';
component InstructionFetch is
generic(PC_ADD, CPI : natural);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end component;
component InstructionDecode is
port(
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread, memwrite : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
component Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end component;
component MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
component WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end component;
-- control signals
signal Link, Branch, JumpReg, JumpDir, memToreg, TakeBranch, Shift, ALUSrc, MemSex : ctrl_t;
signal MemRead, MemWrite : ctrl_memwidth_t;
signal memReadData : word_t;
signal new_pc : addr_t;
signal pc_plus_4, jump_addr, branch_addr : addr_t;
signal instr : instruction_t;
signal zeroxed, sexed, aluResult: word_t;
signal aluop : alu_op_t;
signal cpuclk : std_logic := '0';
signal regclk : std_logic := '0';
signal halt_cpu : boolean := false;
signal cpurst : std_logic := '0';
signal regrst : std_logic := '0';
signal done : boolean := false;
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
begin
regFile1: regFile
port map(
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg, writedata => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => regclk, rst => regrst,
regWrite => regWrite
);
id1: InstructionDecode
port map(instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr,
regwrite => regwrite, link => link, jumpreg => jumpreg, jumpdirect => jumpdir, branch => Branch,
memread => memread, memwrite => memwrite,
memtoreg => memtoreg, memsex => memsex,
shift => shift, alusrc => aluSrc,
aluop => aluOp,
readreg1 => readReg1, readreg2 => readReg2, writeReg => writeReg,
zeroxed => zeroxed, sexed => sexed,
clk => cpuclk,
rst => cpurst
);
ex1: Execute
port map(
pc_plus_4 => pc_plus_4,
regReadData1 => regReadData1, regReadData2 => regReadData2,
branch_addr => branch_addr,
branch_in => Branch,
shift_in => shift, alusrc_in => ALUSrc,
aluop_in => ALUOp,
zeroxed => zeroxed, sexed => sexed,
takeBranch => takeBranch,
ALUResult => ALUResult,
clk => cpuclk,
rst => cpurst
);
ma1: memoryAccess
port map(
-- inbound
Address_in => AluResult,
WriteData_in => regReadData2,
ReadData_in => memReadData,
MemRead_in => memRead, MemWrite_in => memWrite,
MemSex_in => memSex,
clk => cpuclk,
-- outbound to top level module
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr);
wb1: WriteBack
port map(
Link => Link,
JumpReg => JumpReg,
JumpDir => JumpDir,
MemToReg => MemToReg,
TakeBranch => TakeBranch,
pc_plus_4 => pc_plus_4,
branch_addr => branch_addr,
jump_addr => jump_addr,
aluResult => aluResult,
memReadData => memReadData,
regReadData1 => regReadData1,
regWriteData => regWriteData,
new_pc => new_pc);
test : process
begin
-- This halt_cpu thing doesn't work yet
--halt_cpu <= true;
--regrst <= '0';
--wait for 2 ns;
--regrst <= '1';
--wait for 2 ns;
--regrst <= '0';
--wait for 20 ns;
--readreg1 <= R1;
--wait for 2 ns;
--assert regReadData1 = ZERO report
-- ANSI_RED "Failed to reset. 0 /= " & to_hstring(regReadData1) & ANSI_NONE
--severity error;
--halt_cpu <= false;
cpurst <= '0';
wait for 2 ns;
cpurst <= '1';
wait for 2 ns;
cpurst <= '0';
instr <= B"001101"& R1 & R1 &X"F000"; -- ori r1, r1, 0xF000
wait for 100 ns;
instr <= B"001101"& R1 & R2 &X"0BAD"; -- ori r1, r2, 0x0BAD
wait for 50 ns;
readreg1 <= R1;
wait for 4 ns;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
readreg1 <= R1;
readreg2 <= R2;
wait for 4 ns;
assert regReadData2 = X"0000_FBAD" report
ANSI_RED & "Failed to ori. 0xFBAD /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
done <= true;
wait;
end process;
clkproc: process
begin
regclk <= not regclk;
if not halt_cpu then
cpuclk <= not cpuclk;
end if;
wait for 1 ns;
if done then wait; end if;
end process;
end struct;
|
gpl-3.0
|
7a82a15ef1b85aee7fa7cf8e9722cebf
| 0.51706 | 4.057302 | false | false | false | false |
Ttl/pic16f84
|
alu.vhd
| 1 | 3,821 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity alu is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
ctrl : in alu_ctrl;
bit_clr_set : in std_logic;
bit_sel : in std_logic_vector(2 downto 0);
status_c : in std_logic;
r : out STD_LOGIC_VECTOR (7 downto 0);
z : out STD_LOGIC;
c : out STD_LOGIC;
dc : out STD_LOGIC);
end alu;
-- Main computing unit of the microprocessor.
-- a and b are inputs, others are control signals
-- cit_clr_set if instr(10), it's 0 for bit clear and 1 for bit set
-- using this signal decrease amount of ctrl signals when clear and set
-- can be combined to one control signal
-- bit_sel is bit selection for bit set and clear instructions
-- status_c is current carry flag, used for shfits
-- r = result
-- flags: z = zero, c = carry, dc = digit carry (used for BCD)
architecture Behavioral of alu is
signal adder_a, adder_b : std_logic_vector(7 downto 0);
signal adder_r : std_logic_vector(8 downto 0);
begin
process(adder_a, adder_b)
variable add_low : std_logic_vector(4 downto 0);
begin
add_low := std_logic_vector(unsigned('0'&adder_a(3 downto 0))
+ unsigned('0'&adder_b(3 downto 0)));
dc <= add_low(4);
--adder_r <= std_logic_vector(unsigned(adder_a(7 downto 4))&to_unsigned(0,4)
-- +unsigned(adder_b(7 downto 4))&to_unsigned(0,4)
-- +to_unsigned(0,3)&unsigned(add_low));
adder_r <= std_logic_vector(unsigned('0'&adder_a)+unsigned('0'&adder_b));
end process;
process(a, b, ctrl, bit_clr_set, status_c, adder_r)
variable tmp : std_logic_vector(8 downto 0);
begin
-- Default values
tmp := '0'&a;
z <= '0';
c <= '0';
adder_a <= "--------";
adder_b <= "--------";
case ctrl is
when A_PASSA => -- PASS A
tmp := "0"&a;
when A_ADD => --ADD
adder_a <= a;
adder_b <= b;
tmp := adder_r;
when A_SUBAB => -- SUB A-B
adder_a <= a;
adder_b <= std_logic_vector(unsigned(not b) +1);
tmp := adder_r;
when A_AND => -- AND
tmp := '0'&(a and b);
when A_OR => -- OR
tmp := '0'&(a or b);
when A_XOR => -- XOR
tmp := '0'&(a xor b);
when A_NOTA => -- NOT A
tmp := '0'&(not A);
when A_BITSET => -- Set bit 'bit_sel' of A to 'bit_clr_set'
for I in 0 to 7 loop
if to_integer(unsigned(bit_sel)) = I then
if I = 7 then
tmp := '0'&bit_clr_set&a(6 downto 0);
elsif I = 0 then
tmp := '0'&a(7 downto 1)&bit_clr_set;
else
tmp := '0'&a(7 downto I+1)&bit_clr_set&a(I-1 downto 0);
end if;
end if;
end loop;
when A_BITTST => -- Test if bit 'bit_sel' of A is 'bit_clr_set'
for I in 0 to 7 loop
if to_integer(unsigned(bit_sel)) = I then
z <= (bit_clr_set xnor a(I)); -- Equals
end if;
end loop;
when A_SWAPA => -- Swap nibbles in A
tmp := '0'&a(3 downto 0)&a(7 downto 4);
when A_RLFA => -- Rotate A left through carry
tmp := '0'&a(6 downto 0)&status_c;
c <= a(7);
when A_RRFA => -- Rotate A right through carry
tmp := '0'&status_c&a(7 downto 1);
c <= a(0);
when others =>
tmp := "---------";
z <= '-';
c <= '-';
end case;
-- Z-flag
if ctrl /= A_BITTST then
if unsigned(tmp(7 downto 0)) = 0 then
z <= '1';
else
z <= '0';
end if;
end if;
if ctrl /= A_RLFA or ctrl /= A_RRFA then
c <= adder_r(8);
end if;
-- Set output
r <= tmp(7 downto 0);
end process;
end Behavioral;
|
lgpl-3.0
|
3fe544d41828e007f261ce831dedce5d
| 0.522115 | 3.181515 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
| 1 | 73,491 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EQDqRTFU2v0Yr4ayqnCPWtZtOvmwqvkP0Xi9isxy2JtVyIKS9L7Wvrrkjz2Vu63BA55BfHAKE5x5
Pb0s5EPqQg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OifBT6nHozgZcDQWxGkfvVvQ+jUft0Pli2Dww9olhkPpIC0ivjVW/s7JR+L+P8WMJWv5lLBYUO8o
IUtJDeIGjm9xpDxku707rwzpukUbcH0v6tLSaFP/8WA0uG5uaM0OlJik1KcNpf4GnhWdWrljuLtM
/Xw/fmPusBCAjypI7W8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
q/HCqeI7pjLZP7dTRc9Wsm0ELyKVRBTbBIQceFsa7XBrwSB/Hxn+c9ZemJdK3ZQqnTgalYuqvGzT
rgezwqTc8fC0IfJykmk+kJ7Tt1HAD2DU8plht5HEfgDVlW5NYt0S3EMFjihMwfFjRhF5Y23oRq10
ipBrbE4rlQ+tx6yRDbm/BTbIycVZYZWY1+5eTN2a0ZzlBJkL/MUGtaar97hacQaH8EnTtMrB6hxe
R8qCgPnes/+Eas1kurVGcpZW7nGEIBHgz9x8A3Fu5+gXZxTz008tRVrD08TwMaArg3Y0yUxxr9FC
5GsyZ5fS8fCECjX6zWuv/hbEbAYwMw5FsbVNLw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
qUbKCxMXw/nnIulYkN5pe93HmQQ5N3ma/VsYjdHh6IzsScZTOE91XnA/FIXOznDfdlDJ7l56wCrD
OV1RIEQjOyYByz/RfMl8YpwiQzF4Adq3BP97T3g2FgZyywAaw2p+pP3NJxGHTUf1PPSaJQB52pVV
j8YlkVnGzaHwXMVAkuQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Fd3OnEDpF37ORSCftR3VqfnsY5rDUuZleCcIBB3zorEz5/eeLtCPdzFI7aHMmcin75j4X8b5NBmg
pLcIB4yDkzRxSB0GZVzH6dGQ6To8T2UW860zTu6AzG8W2MAVgJ//Q4wrelF68iPpuCeM+JSgRG20
OtFkOHqBaOeJW0uxYxh3SLZFPi+4zJHZaH2s8uz6e34hLVoCCocd3xqdV4SaH9ohsctwglEkjAws
eUFgVHofyA0obqa19+4glTSKH000l5y5Y/FBdNidKD9OaAbSu6KYQe2iKAQF+rG+I8i1ORu4ME1Q
UG+FTLWF3eQptYgGPO1l+wDJ6LNKgIdZWc712w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YqBAcMlmStICdrufAXi53kftO4qBclLx/B/0rL3TZvNv+N6RXZSOQF3NcRIeIoKDOUEsasbr3Q1F
4R9e8bPfliUoKsPERwqTQNShWSXBHMJHZl42+yT1D49+x7ALuyegtFJvE5i4MeAGXLtu5E1jdDye
MhratXvJnnhtLO6ix7Hu9jJ6pCV8hlfKB6UxVkgy1ELdJuw5K/B4ddltYde0eJnwyZE0ApH5HSc2
oIHfQAgbMIFf7h6+0OlFYVf+yYPvfwQoRFvJ/5WsLcyEIzzYs+gRLoYx0qhh+kwL4nOQk348TWpz
lKi9OSHc+sAGQLf46joESuhuInipfrkgBi+Sbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
`protect data_block
Yatxwr91DdPkx4SMx9Ly0yryWHzlRgNwS1BoDI+GTB0MFIDMVkrtOqbyZcn6+OWckNN2Aat/Dwsx
wsMfhduWop6a2/Do/9q/UkvP3C2mLl6+owI70Gl9nZBoZfdonboIPxdx3CEsflmmWyM46AVyRad5
OhWv47ssY1CYw4+W77UAoTdR98GDZDYtb6S0yi3LQx3m0fx+MsA/qrDAjhZrX1q1eSz+euI3tEHM
2oznIM9xi4hT+e9OX1zRqVjcn1Dc18IpX2A1DSTe+msmbsbfzNHJnow2ZHcT2d0/BdVMaWCcEN5y
/1j2fC9I2c4nMiGFdj/QJZhGkE6R0FA5AJyXg9KJnadT3TVXALuX0ZWqKAqgvo/UdQlHt/9oVjlN
JVavtymQF2XAai3GFYTYE1w5J09riPjtrYe4XY3Rl0E9OrCv8mRxNSZeLLjzsdnphiMPuzNYmu+K
gq/KBvuvMHJeTKOrnUtEQ2XJoOLlkbSMauzD8RIPHCKoNqC65Wz7ZIfZS/5wHaHRLOEnombowXNT
vtTF8By/U5VIh48A+pfuPESHuRxWc0cZIhuhRQzzW+OxGQ1DgfiP8hWlHK9Dy8dFc2DBq8BUnXit
y8nLrWh9gF+mLb5NhxMETJPWGy5VQCmL3GKp902H2k25UA03yr981FGvtJCPkJ/e162mcbuaxN9j
kpCB72wCvuUGIOoRpmhr2lrCAu4U435Sz4XmvN8kgs/BoW1H/XXDtoEFkBOjYAqp/Dcc+Qt5ymW5
JNkyhl8bxjNNURNm4NrBYxxZDyh6OXiI3DEvtMPuh/Df0zOFOX/AI1++/LgS823h9NhNLp86Zfnk
oxxLWMb03HhaWhW9yr9AzuT4mOrQ77xgFshXC1sBxrrk8dXhZYCux/QDmNPXejRrV0G9GRO0ZBFb
7eHAQ69bb4LqDLfA63opCy6cNEsTFrUSd7xj5WVNMsvLWHj7VTpPX1Tko56Npm8rTpdfzvBDNELJ
Hz8o8l/kzVB6YA1g8SEfJ3t1g5I6jDeMiAjcDSohzqVRx7ny+BYJWInDnC23qJecQcPMMeqnBqBx
UakQ9Uz5CmT8dUVptN+qpPzflwynFGPtCntHNMcrO9iqo5HE7JucLL58gUIMMTS0xRoJbV5fvHBn
8xyrzb+WAm/+22p2hDCavmIwBCDKVE8VAsnQTiuIXV7JYwX2lKk1RIATiW5AvlQMSe5GvZBOC9wV
Oo7F/Sb4VdZTXNAzf/t4dP4dBMVlfUmfxlNiEgnCjsAtyP5Ou6Zjf4BzJ59USljwLOoCFus1IQQL
htPISeu1LJXrwuX2nq8RaCgN34RH5GBFldRr1nUIG4s1bZETgg2p5UeSfg/IWi+Y/0YXIsFXL67R
4juzYbAc8BjerkH9zISIHervJajx99OUKcmQWYU0ooHRNZZBOnj9EGZTbEigAMU2I7rs+T8Tqt0K
4E0F9aFvadMLQ8M6IGt957MXOYpO790Xyse8EHQsG7doyZ1gLkpTbVNZb7KYfDhtNlxWcxRdqbeh
Dl5SJz570rkewS03isA2V4naDnsnJ2mADWYROWbtbll3jEfWdM9ViI9bh6gUv+GljICDR7R/yX5V
fSaPim+rt/QkZ3TIuEUtdzlfMmCbYjoo6IcxnyPJeIJs2h9y6P1MU8NsfXXhQDO6qV+/xLgXnfKZ
57HnR2+VSfz6wcS9vb2GNgX0145TwjydQFqeR5jweiKCmtBrE+9rUQcz9c/Lf+ZTtIA6Gu42K+ig
QbtxrUHsgcDdMTVuGVYPWesbEIB/Ab1p+WHVkTwo0Ht9sAgYgsakULfNNTh54M/s14b5gLq9reYb
ZuibZ6dRZ+f8Y3HGG8tCZXSJg0L4Iz6f6EDep4X7esjQrSaOxtJHSgUC+9F8bd7dPA8851ZhghQ1
ekeVZ1jvdx+pxreAgRY38Zsd97JdJsBwn4x0Wj264SB0Cep2Fc97TnQNzyoItPzosWl2fpWoM3hr
cbeuGbk59OD1/90vCV7Qoiau24McEHcmVWX/cK4VIQ5oVdjOfJYkpE++LM15M6PVMSsRAVouhU3W
I4SCbbcdTJpntSlD3RbySFytvZz6RLMv4c1n5QgkpxS+FqQD3zXTg7GX8/lRJulszPvyUFABA61P
MIFibGXkf20fS/jWW2TbSsKiAN2ejKg34vEh6z6VQrjCVKeTT6FVTbS2nrR1frB4bb57V1SuDz3G
OnqP0QSk8mkMTwWya7OWm+8XsXDto1Yg7IHf/ezCOgp65G9X2pa1l87z1VqcQVOG4idwgYC6LR5R
ROLi/iwCWVZdx2BF0UI53T/HkH3ggJU1CdIgf2LtukHQ8XLy5SXBSs2n98LeG2zNK38atFy336hF
muFzsva5PikK1bh0hUufVopNhWFJtv7egYkqLXB2FKR8gbQaVCzQYNzpp51M++qV4tCo/zmc5ay7
y6Iv8J761lTjWfR0O8qKPPRdIJICu5eMmlJybNVAY1EeLybuTm4//rZLjdarWZmw3lvq4w8/Om1A
iJSM9rjMVZBusAmw5anBipgPRXhr4GLwtbAlB+ARqUMcVKUZxAJFbwgoruXpAlbCjM0tr4Ltweuf
EBBjFBSpJXHCQvq+GOCvtnCJp9LB37v8kGsrL990HKO5aucSEcikcQxqh7BXh2HnIw6ZkopcZTgV
cr2/zELegkuYHzKmEMg/pte6qwClEU46OhnPWKdMa6TBiPKum6NX/aXLFeK4LJIhJ04kBtdb+OSV
+YaGCivn3LVo7bOSammD+fFnbAMz9LlmFfn4CUw18BviOs+avr1Hy1uhL67JKYLyO3ZF8sC3wzb7
oktg0NlZTtJYjWyRqhcEGsot1RzE8GbwW7prqJ9XxZhnRj4Zte1PmEuijr0dyvbiXGkZGSo0oLgq
YzCNRrtDNhhos6zKvJ4CPqeBDhg81Jaf3fOsNTRYdY6PpPFAXgBF3P0dYJ+DDbMUYFu9GXYNJO7r
jk/SqR8hCgxr336soRDWlmwXN1gsISB7MtjyFvoxaTYZqGGpapQcrUNIX0jV0kpNhNqSxBVGdbmV
fz9CFVcPMFqMuohWxUKgmtGTN+FPYAJYPhkopPUId7j6Csz49qGDLNZdrbPC1Oa1bTGi+8qFttqz
jJxWBFHPnc7NOFI2DPIYMitZwp5xxyFnqBivDwfCpWAaUlG7o4CEOSm/YKDpi+ks2ZLkl4iYwQ5g
ALTRiUD4em8XdFnB9NxuzoYLO48RMzg6UF6VHONceF75u8JpZJ4Ga2CRjmoBM0jN9Cu6st1fbpcy
b9D09s/0Spsj0fMhozPHTajpVN3F6QPUl92QwauFJSjAZw6Tkrq6Uzm4mtijSn+mX9t8U5zDAype
UVTH6ysLdg7dE98bQ74RhTZhpcg5sytKkBdl35oWVe7zKymuLjtz1N73TpFkJkAW0WsRuLpx25Id
6rc5SW1o9aVkMtdnr6nofkGyboUBGYVQY6pnwmsrOz7Ts/vCMCIk795zMJuej/1bGTs3lxbkTahf
xarB+hWPi00EyKWV8kiaHxq0ULqt2UAAgElMo2jc9RR40ChNEM0PxakVVj7nejL2gQ8s53PO7aGR
NcnUddz7+dHVWjvEaqII75SeD5iSoTb50Sr1bYiIU8S+j4fMBSpe5/un7ATLmFw1RbWMs9lkpyiJ
rsdj93+C6MJjDisdJrB6zgZNGbVFoNAhrVUUDX/WwY3npqAHLZZSsMWeFlTkoXdDo6UHHMcWLOw7
kUxTLV9ggBtQYfm4m82wr0PD3CoisQwytvjkjsHXLR73V0QdSREVHibb6+cSRJnU2cV3iT7ZBMy8
CK6IqZCyng/pnZAhdF4mpVESZ2x5bLSSgRxdbvSmTjDmWahBpqUtVVeNxLbEMWVhHq5g6S7LBPx1
Hh2ECD5qr+ZIVdTxI6ypwPSveMplIV7eS9c9TaV8SRF18FzAOiNhvXNak88b1eTc4hpV+YYj4Hxx
mTtdLDyDJl24N98PdYWr0gZxSg8e11hHvfc1OPjjUAV5Nx213yls4ofNom2BTgKTuzuD48HN9aLp
VQ6cyFSD8/adpoRJxB7WMgSKhfEBhj+mkDJQjRthi8QQG6PGzy83O8mTku0G7pBtJYsvUZYDuU+Z
ooUzDm2JwFtOo54MMIQkvDR8ymPVTpia+TG+PeOdvLl5iECxhDqsnh2V02gkenq2sixaVIEkdr3m
l470AGubroL+aQYKQhvWhmBquJJgxbbq9e6oL/Qxda7eVscFfuZw4BITDr/Y74DWw6itPWhUETGu
JbzPGXBnxddBm6I3RRG9dsZtdw/DBXUd4bma92ffs7GU+FD5EY3HyKCY8vt433ZSy7aR+m3FaTi0
VdCbL14TpSFoq/VQm2Pn/USu4R9dsm8HdNbcAp5mdXp/EKBIjiBwsaBsGk/UbHiYlRBiJMfPUrCY
Xq1lXJYnwma3LnqVALLN+8v58lc4G63/EoW4LdMr8q0jr9ZaX4C7ziKn/Cbtwod1YOGmYBZGwYM3
vtID4QQdq83EPx6h05P8IPfr9yEcshZ35idch7P3IQEvz/u093AeGqdQQ+DiTMn7pfesHranK6Ty
aviD2eheRrIF9SmQnYSNchX5zD7gASKntCMbEGj7H1wPmsYlxonX4oqAUPktpnrhnXHaCzQOwUVu
x3jPzBs+q8wVfR/jYWBh52KmYIQ3pP2nqQkvphhlESKhV0FwUTNbcU+zVMUAwlHaUKk7NRx0icZY
GAVxZDY8z+qON11A53v0UWIKl4N3VFm40LnmlkUzmdjtyl5Vq8HoqCa8VKlf3vS42qpNmeBDlNp0
NQgaHYNVrNef+FXne0yBxJ8dDEdnOvb1G9SXpPHJmCRXKkmxBCDdFWSAhwqq7KsQ0a9W4FI8qRuP
r16aOvct9VzAmfzUs6lIYPQNkw4drODwZHk2kk+o/UaJ9T0Y2+nqupgiX/sR39dRjLMbtBbSLuV6
iq07xXBa/NIaIoMMYoRocgdCoYLQXV853qC5UPAKNkIbWtem/C30P9s5ec2huSRHVfCa2oO+eGo0
tpUH6QdAYsShSrtNyX9/y0I3IwMvDTqWjraOGbnHO8WxpUS3kvYuLKCaYxQjCN/0oFVCaOHzkQBg
LkK548+QmKrlW6S3jPlkiV3kiVeGc7racGCbgXhJeLbHLtENF4HcNh7QT04bOjY/TpdnLbXRayHY
TE69DyvoNVWkPUFHMSk1C9kix/U0ZK2As//WQLsOFIdxRS0JKKCO+Zvng9I41/t3MM7Kz8bCm963
Zz58Sl4iuZrsSkglNzj5bAAvulyTxmOg4jKkOXwXexw/TnW0uo+z/95ulLJlOeQMTS987zZVLZvH
gwrDReBg0XPo9fary4S6L6+RcRwBNP9OMsy3gNaeOLkpslCHwt9qaS2t4CCZap0IjpSV+w3x5dS+
H8SnS5+iUi0xMyFLdE1gQqarXSl5ZFNh71xgjoTU31KjSgCmES2p7LTNwa1UX+Ygwpbq2TpjmrH7
h6wV2CtIWvxQ+efNXfR9Z6l+s51ohTvwzBm0Yn8cfDy7hC+g/LxOSgN1Km5ZDJCCn8zhDQf9n9kI
9YPDE17ruVu73b7cUbqLJJ7Y/vqDasoqq30RSRHEmMcap2gPlVMEYUYXEEW9B5THycOnlox+AYEb
UIHzwexY1l6GgZyRvyBQYY84D/62+kMMPGcgcdjYLZyqceRN4tN+6L1LIJnZkCf6u7KHyWyYETKD
bVJhZLYOOdq0NoXL3uKuyv0/jU7MbN8akCzFW90ePvzpWA9yMfgdYdEpHx5NKsiDTDvKq0R3YnZb
b6GO5TpdNhFgsRm9lu6e761QUN67fh0zkZc+a8cOJ8/eWHHLHKucsi6O3XBo063lYPsw9xqv9Y2w
2n7cwTnJL7X94YnVarOy2iB70rXPnGni4rDJO7AB5c7BpFKPY6zs7CywZ4gyGjlWXyPsXuTH2M27
KAnPa7WDhPiWL1qPs8mddwtIboY1DvFFEdTdSOEQiPYQikT6lH9XM84c1H7uxG0t22CiaMV+tFvA
sFLVODl3unlzEnQdI2eSPGKt/fG9iZASyNlMvDTHSDTbOkTj/p/Fyaho/no+AfTAcSl3hBsM9w6H
C9cO3VcLhET9zopDdMcCEYZMtP9oCuHEysTibvTn3hCM457u6XXWfXHrOMXbcljohoe2/jqQdSZE
CFodglfM9C90jtm3lPI4pc8GU+v0EmA5IYyu4PHCNN6Ha19wCErYrndva6PvjjD5mMgGhOcQ1Iij
Ha/56N3mffEL8tm7GLDHUsfNsKFidH+FPMJ5MAQn+B+mr8pD/7Tp9od8fmkrcBxEcBWvFdAaI9RA
YjUbnTOlLnQzZvsJCwQ5wEAqged9RThElqJ81HcOvu99KM7f8QOCyDNSZ7FCCNsiV3Ygdmot92qJ
A+A2vgPl/TlO1pIy1kw7vF5SKHAo0tTauoHesWzQKHXc2T9avfsQJWe2JVXr6oUcJ/BcI1vGrV9x
r2ifyJugqEyf8yEBffP03n6tBc3RWKrNYi7vzGF7l0RvpZlw98KvbjUI8oiibFBKS5t3q4RGrg3U
6t85yOTW/oLbuQfNLI1V+R93Xbvn9E2dVABreSKCqE6gCEOY5nNngOF/+MafX9Zi4UAoX5vh2BBt
dkdWERE1HYuYEFUI5sfZkHFFaGBG3F3tRBPfCIU73Ez9KdVq8sO4wW1j8+oMTS6KsnnRQSDajx+8
D4Uky16U3NrqU7EGScbvdTkAoKNZznWUyeVhpm7HvMFG9j1ZFrC4+lw20qdFmb3GXpjZceiOf+H+
fT9O07iCYG6vCmZHLzsgeug5Da1CZOBAUtGXA8G9c7WhxLKO8FGemvPae1jerxdSwbF71w/9dI4/
N7oxiVNvBhTkxw4S3jnw30EZl7yd+rn1KqlEOPmVobllkYHLmrWo1gDJF+XZ5OjPwbDg9NzQKJOQ
6wRwVV9SoCBM35+2CP9V0u3VnzZcpL2jdUr3Wx7OthP0dnNLCyNqCNt/H3nvbRmcpzisEnjXzrsF
hBuhYzjCOsJ4JRt7dPmJwUnMhrUnYGqpGtJ3wYhTVVTqwPZ6s/2fRaZdznIMQ+MF1DHHdrkXMEj5
mg0OzxRsdXxENd0ViIAVb43d90DfLqsicv5TPrmhkMve3yYz/30dSl/30vtl9QIRKIPOWnK7O205
hCB9Srr7OSSxTcxee0lWEKzDwHES/SLB46t0BAxbNVcYcnRxWooENWJiq1F23n8a1WDZ6E4Sc88p
JVWwzgiDJ09Hq0NF/fuGQWDFIiQw2s+bQQuzhC2L2cdfKRDkaLC7JRnPXZjqeQLZT3PIcrNXvp1U
HMLQCB+oHdR6/ZKkljfnNxl09gjJ6+8We/fgbARtf+KxAOxH5THd0V9HHj5u0n8Q7cwyqlbXNEgr
3hgdkxU6Cwv1xAQXuWjzpC7jJeIm/XXGVAaEGXJzuC3MxwVTU0eR7EoqVVOf6vyoYEGr3QzkejDY
zHUYCmaVyHt6CtiSuUmnwxWN6MD+/YqKWzgqmD7p3pXFz0QooLX/S5InoRYBla5Atb5soC43xW8i
Ouilz1qwrk15Ir/PJhG3aW+Spzcmz/eMJEdPDK5ovc6HLDOtzSJjyBzrDSWfgOn6zbLC9i7caOQG
DilVWIFfkdxDLpnWQCNPvSSbX/vw4B5Uok79RrKrZkP1vByU+OVwKVrE2Qk7Fr3FrWVJMFuSXPxN
Fy7xzxo8dheR1xF2BtTI2RFioPFZnV7hUfjVw4ag75TmTTB0vmuzKaWh4cvVUq+vjTpusj3ymjQk
5mbfJpMhvUlUXZiMPZMgSAC/PJG9cgM1fAO+9rtVvg4clgyolpIll2+wo4+DJ0S8J5Gfz0L93QXi
OCSe/HWyFE9i7q3GQgCO6za1E2r6VCFWCf9IZ6/r7GLdILfWfcxwjPlYgEac5keYFh13F2a37B3l
TDJr0xORfir90poa5MxNI0t/4/Da/Ng8AOvUwiCyK4PNGM7ys3D2KlRA5n0wWt6aCjb2L582j28Z
Qo+XsGeOOoKzCjtOCB2PiavTjLePAO6bMmQO42NE9WPg12LeMcLkaqERrJbKsTEyyXA3vvtsC1SM
Qw2Mtbxd9lePivuOgRmKmAi1YjzSv3tRbkEmjeftrWd2V5wfapACMxVCphh9TQRDuTNuVDMy8aVB
0AppQL9ejN9tBIu5n/zyC52JZwcwfs3f3ZWUhumDH4YaiEIuNCnAXzEEdLWDRzfIAAlKT/qhmkBT
FpXgw3wqgGMfybPbjngPH2C2IEyF4NdSzKiioeDUeKMTxPF/XlxhHrhP5pIHsmwiD462e+e79UM9
nMkoJQswC70mR/NA+XjNLhcVDUnKRPOu7i42BR7/5oH0KgcGCqUpMFpnX8PgTDSLSUQaY00CgRZ2
B/EzcTCm40tu+7THQLbIgYVGxutZOgVVRAba2A0R1KMQvmqlShu52R7Fa+u3/ZMNPrLzkReZcpRL
6t7DHTRXnyq7amaYkHeJwsmneTtaLuUqyQ6nY3xF5ZbLcbpihjPMQ0mooNNKE0vL2GXXd7IlSX/o
lDKVoGs5E+5G4pN2VoclZR51lP6Uibge58G/UwoYLPgtgOdOxaSYA6YkF4PZrl5ds83Wdj20x5V+
H0UL/3L5fewLbaPzhU5R9n7vow554K8PVc3zsNKlMetrZ4aDYRTBHuAZ044+eYgOChqdjTzS9g0u
GraKijEZn5S4mqUfHEjVgaXtSrj7Y6cTkSUGIOwNOGMhrTwHZfXx7dQcxF2YxYR/8DoUCj0FB8gI
+eX7vVqFfyKoQ0kjGREZLzBMPaPY09DVYeCCjmgI6OYIHmLSXPAC1x1ziVZOGgFXBIX1ucI5U+wR
bzgIPBVqqyBfQT3Nptk3eiQyI3LVu5A4njZv6zwb8kBSAdaP9xlEddQYxrpb/VntIWDwkOTHHpHZ
DExUDEITOyKmdtMvkvclBr4HKO7Nul3ONMBLLyP9aohu8vqtf3I39CfPPZTuj/KVudbkCW7Co5Vr
U1F9ECC1+5k1L8Cih3mHZGFQbEePHZTdwqmLECiYexrZaNVl+oDSkj5m1fbj4mIyHDH+pYF37xJD
K4Y5sxAof+2rnyyqDnKke/ZcDfZiT5wXQh2t96Et71z4mFAM+pZyDgN3+LZAvdwTrwv1DOrgsb9H
zYWxRfyhoIOCmA3P0c8MPahFpY2PLNeKEfPRl3fnjEal2GrqwkKie3NRbsDJMn9V6uyhbXL6nSU4
EyBd+Lfop1KvYBK3d8T7FUXwUzK0/nP7OPbYh/SUxmjDtFw/FJ0nTph/KlrWYbl/aNFnDK47FAz4
/uSE46IcQD7dQ5GGG43jLWkSZ98GZNiWyyQGRsqXvtWqh3x+AyUnayAOWRdVSV0gXlqkBcdVPRc/
CboW2SZNsXsbbUCExnrJ/fM371QAejLgW0L64OCBkOHAX6ZhZmF8CAKbrlkGcWlVPkMYx9Om1/g1
hPyKx+kjUFrKr8zwg4a1FS3aP5ks1vYTGCA575o1Lv8n6qCnnUN2cWY0S7gzhjA7ITPgwQWb85eS
2kqGCzlG6gHdyo6ta/y+LnRp50ROqYhAkwuxwYmYSTuD+03iRncu5YMY4tmmcGTbRHpOAbI0eXfA
tWr1RUIBkAoJzRgBiHQfFlitYs3LBFl69XAtqXvSR0tiELIbr6BK93JuZ4GOwAypmWJcVGTp12Yv
MCwCW9tEY66G365uTD5qo/8ss/fypyVociMOYzyWh2bKYgGM29r0g8CHQZFb09r2AHN9QSak6CK2
vBq1TtjfjV56f+J0y4mbPNcVB/7fVnT3b/yqp0D9htNecJMYb8dIfsbO0N917dnBCoT+4WZ1Zb0V
nW3YwAYO47qQ3SwCxzrflBcxSw+Kx1qKh//xE9cc06Lvpcy0/O4m8b420JhbZSE6UTZoIoYzvBFe
auvNS75k9q6NQeavajvvx3vAeisykz7e6fnSVBEv0uWktoIxjX0hwahukYW+lzDQkBrApLToXFhQ
vnGA4W8IC7NIksr4DplXQbqIRfU6DjkKUQioVwuEJQdp/8OqyTrqloRoqJsYS9/VqNdDLhOHRD+9
KP1lm8qn5fKsMKTiJ2AIRTDdQrNJl/7mjflAT5K5pk1pfeR2e1fwEQz7eeY8KlhaC38KSqTij8bY
t3RaCVOg39a8uwM2wgyU8L9pNWqKcVPcKeI3/GsMjMtQ3DqFLycP81u7hOcFRf9MfBZZmMtXbUPU
a426OnYsKFYKk2DZjupdn2lt0QeRI4wUoYO/VmZ5isGTeyQVb89X+sKR4o+zkXXqRuF7ftp7RCNt
ZVdogOI0GZ5HcjoKnWVBfK8mUgfNdeFa7Zq1430IdHiww8HIYepI8bxIoTJihUetnBzHSOv2YoDO
9Uhu2Rf2hw3eoP4P4DBAwX/TZQ6idtN0Q7q2202IrKNfHXZoj3TTZ41a7YHVC6wq6vhkzbA1W1aG
7NAWv5hSYNmJPwROQuV2ojy8GyaJ3B3afn2uVmaVG5+GLREvh6TmxRcFgbD4d+nbatdiSHzhL0Jg
SNe4pWx2xsnDk5GO7hiAlzJFrusvQWVopjAZTaHXOL/oXYIu+u7OHMtGgfQOOx49cLASdynQVtcQ
pC1Uh3zdVWnVvdxBgeqSG9vahdVC8lxASbx3H3I+vsPHLIPvVlr+qnFoj8hmf5bbA0hkxS3tB5kJ
geqoHp4Xk+HNGWrrA2Gb9FQGzfDzPLbG/hgDzz/tQnJDpA21QeJjD6UxJqH2jBJsoQNcorCkYbAE
spPiaVQH+UTPHyEV8xNFuVgyFcfSFrmIQcJ1kVvC5k301WA/RxYTjW9AgMaUzdJIPKxZy23yUBp1
O+TSQIbBnkfGyw5siM//+GG7v9YY8VPBecGj8S2O4h6q96NxakDfedRgHXWjXt02rYQ8fbUVjWRp
fr3B5+fWYlvxhyP+T2YJyrF8oKAfUOImXmB+OBkBYXPQaa/uc6TF46c455N0iD1/Essjk5guvgMA
VGlcQ7ovsQNo2fCHFvqzTLh/o92gtfMunU26N6exu+5XcZFS0hgYnG1F8FXo3/QYAJ1CeRursocA
dp0mJ/9PD6Y04L3bfNlGy52klFhnk3Z0ssGGB+4qjoRhSv8Gij+PIYi9RhduoHwDr2lsnqL2s18M
8LwzWKX4oWXNAPp8CCIijjB1sZH2bqBMM9YhWLyt+OiJwPBEy0u7SeA7CRhSJ3G4TYQoA0V4NkIw
ElgZNKzMtYMT5nJ2nvSymmprmno46a1ZVnfyK1bxLeZuwDKiWm/A0Aq+nR87L3iixdHMFcE0bdx0
GxCaCArjPDbRHariZkS2WpyvPX2jhPt1aZAsOio52ayNSmQO3qAZIgD4/F/6HpoVc6h9dz3nIE1l
3dHK2gKmNxl0wnGMIthoDu2Q6kpZ5hbJTH4cdXZXOwi9+Kjr54GJwsUAjUMb26WzJ5gb5niM2M9W
NBtgxHaDrKP5Kzzc1T/pZD9XfKQ0YpKJkhWzZ6SfD10HawZsR4RfdnB0pPlO86IEXe1Heae3JDZp
a5n7GfCVyIaWMS/ZVSja7RmLcFOtq8LEjaTOsWg32vlPg7lPwaRlgJiIv5OfLZDoXaBS177QxLL9
Xl9UHSE6+RadDJbIbLiHdWsdCHA+mf4jdcLE1g5CLVWwotP9inY37VxYQgrotDBrf7DmUhCGJz1K
wAFOrfnHE/hsXUHv3Es3PU7rpGYC78QO3fd8+AATHgsm3qxX0Sz43gTuxneG3xJdGxUUukfYy6vc
m2vXykMKSkIzRbHLMwjQz3qpWxxfJYSt2QlMJExPUP9tGYWiIyoogBXo3bSEFPa94/UmkPlpvERR
WMvuwrB1VhYfxRgar/qoeyB+Faf+Mdqb1NaxuToQVyGB5UmTkNObB7EFKmInnm6kuytEc0fWlkFb
50AxHZGCM/eCLt2znhog2OcXBqQANq5Kbdb2tgQRTfYQzwWEKZzJbUszln1D0cos5ej2o4B5pcvo
8Z3ILnfpsUEG7fpUUAQSyuSVo0mgHsmeaFc1UgxYWgTYFLx3XNler3KFpoAvb0KktMxy1u3Ug4wI
17pFLqLcl9BhTNu44VJkH8W5B2fH4+XJxqlzBfeBaovdTZ/Wyrh22VNvD734WcZNgJotnbLHsxkJ
0TbXpkn1NA9f5J1/XsPg6oo3rEGcjQ8sC4p/MIoNJ3InGf3bMFRrorIWod1sSKjlUD9cGkoNTh8c
i5vo+KrBBfUIA+Go8fB9uMBy0fwS1wHPaljEx8e1Ei/dPAoM34ShLowTm88pRQZPXiilQJ88rdwr
jOWExB9oHR1XEs1I3qw/Tw72FlLYg7U4kfe+3IdiB8Njqvw9iCh3rsV/Vx8tURdajKPzfLXb7j8z
bGdz22q/Aa0C9iVSUQaD1CjdZGc0qFPaVMjE3ypwYv8wEMUkhCdPVWrGnHTHp8m5M4sJmw5E/QiG
RQva0JsD1sTqouXp/4rgImYRRFBYeUzZ7vycQMU+5JY1YgwTt8utjaVmG+Bci/yNn8x2Y3tfOuA2
+EsqpK96wkn/8xuAq7woDv2j5L3f9b3MJFp8d4CzFEvFVfweC/Qb6+T8pGOuYDO7JgKj8lDjNVY4
Brcg2ZLGNho2VWHDhDJ6rnB7hw4woXjfDyaMDGXlTQ4Wcyr45iML6WNMUhmK6yZ1K9s6kVI2LkjE
FraSpQ/QQq99atWQarVD0XU9FX3Jv8+vlwHvLki4oHeabIlMr3YLXbR3T5ppQe0sd6dWn6vo7du2
288hd/x7N1diKluQZuoOrRqHBLNEBRTlQHtmZZPOB/3UYIMmALFjcfaFDVjhGDvokzSoX6bj0lTQ
QK5LTgB0Fh94XtTR2MbCBTuZLKvrQx6jxL51PlG1FxfZIdGkbvxdbd3hfdIQpVG/kWPb5nbyiiaQ
uj/Kko9nLL95FW0TvtGwHqrtCTLu9C+MvF/rdDHKDVBC+tWEvFSnDScHvoeuIoojXO7RaUG0oEbh
r8ZWJV8HQgKcZQhqrqEtbR6RKEQG6D81uX7NXzEUbx2TzS2ka5avbovFvUPV26uLrYPihVLh9Ra/
Djsu/2lpimWl6RwHwg36dhe2hflJ3vhm2J33tacX74i+HELx1344V3A3rhr9GGtaYANGy6/3eJvs
r7xcZHEkTPCNMid5FiuC1q8Tb6pM/edereS/nS12euM3+bJFN7/YHT4gLpzrm91pu27FlTibZLme
BgIFAsVlWQQDd4JhE4fYI3XRjpid2nDlwb6i4nCYvRIqno/wGYtZjbn2Q+xchaUNPfheD6e+6HmK
hh35kXMO0ICMrmyN2B+YUtyVEvss2PaMeKumBSgmzuC1gbsTcV1agDEpEkUJCXRT4KYnM25YD4h8
tCKSaROWfuHUE5olbSVRi2rtjuZnj/b6fSdR5i8+cut2ZLC63GggLAb5BzEy5elA/sIVg8W8251y
XcK05YIVmcsawVSkQHKuZ6WjvO4Dml7T2C3g13U4qIgRLfHtfAMY/XbY8MksKa2x5goWp073HqIn
TYz8ZD2TQl82+GFaXAZ5iUibbzV83uhzcgM13H5mPLDCeBNkGIIAOYVVQILf2VQ6mtRPE2vwR5D0
ESxbFQim8kCHL/9X/oNTBg6mekS9UQDYRT7XN+mD02Fldm3p9YkhSsgoZeicQ3PxxhKmOM7cUU77
Uu3yFBaG7vzbKl7ybIlgnnDgbh/3d9mdBpgNPgJR8AAeUXXoxn44pUjJLh4itN6XXXOlq14G3P0O
XN7qftEmMO/48qvQq8IuYzpR+1/8V8OY+4NMN0whCU10kP3QG8zs7tHQH1wEO0tRGUAHpaL38mp+
BrPhpcrKRJ3lW79aEmhK5VE2S8u/s6pWdVdHxIPIezhtZCclXNhz9vl52tvuFH8mNp/rsjB9IFyg
M9gNUKnViEhs27j+/K8MM9bOUNwMbhZgKqZ0svMteKihLd8eL+pNX7xmPC5x5+pOusHBLKChrrWl
E0+KopnIQYhRvP68om65S3MTdUdZ1nwHOykRPMkbib4r1g8a5mt4v39y5MKZZ5W0w9kjpmNTSosx
jsYa2xte0cjM0xRIGS5EJ1IIrFItXqwaEompokIYvWbwV0kuhTUHmY5mxwO8sekW61ESz7UwfAd1
2KO7MHormGH2+YjjA2qDpKkLwXhBnMfecMkUEc2jZSTca1YIP+BptAgcWGyCJTxmqDAjreJexris
9ljBbGUsoEhsgE3Xah39su6URiR0vPO5/n2prTt8VetFkdy1wN35i/l7jVlP38bSyBdsxr5rc75h
WIg9k9jwIJvxErfJYzHa2L68ynYZvwpR8TJ7MFU0zj3kde1CnCJCqLdfVF8Bw/w/HpTjT8sXbPA1
fHw0Ayt+9exad3j/Kywwi0NkeDKIDSIJi9Z9lXUiagk1o9W9gf81hP2hp+krr0fDIT2z8eIXttJ8
U5q6zo7zHt5ZO1xxGu/VrWOwMZgWklnhsS2ZPjCIdgTYNUXAqgJxtqg+FoU2ywDlz4hHteroC1Od
1tn39toIleej18JWpP1CHz5embk8Exsci0cp3HSu1ScLXGpXz7EzYBDns1nhxrRzWhXfS8BKyRs5
1u8jtxxUGIu3WfqCdeIg1sIUvFNBUr30x7bxt8m76+AFJi4k/2/qbgJkGOCnMtEsq8MKvRydjR5E
nESmO93zEPTTtzKZ2MLkKsqV8ty6uJf1zhIGu3V9omB5aK4gzY0xxDg0+HikSVD+DEsEn+HAw9hA
RlHz38oyFfZehOYalHDNEVMQ/kep2XPbrOyEk07bkmEFxjryq4Fb7Wa4P+7R3EzGAsK3osGiJAHq
yWdCMMtna8ZvnbUiCFf0Coeabt8cIoUk7qLaMuSzSn5dbcOQhe8kQvTVGL+sZEdYu9srVe8WjmYI
dPQzWTjhq4dLrMrkqmdgMfG5+4v/tCflA1a7wHuePN1wy+kvfG2bG2m77KJIm2ZHjBtyQ0eMPXmf
PxsPVQOSDNa+nf5hw/RJ2FTbSU3UFhgwxRGtLUw57N7dkLlA6RXBqM59SpfVWAcV42d0oyqvjSvg
dMYJkO043NsrhVfuM18Tqs0jAg8gx6TuR2cCR3copxvSk7IXC+OHbSFCk6GuDN92xdA2mjF8VXla
YR4m4AkOyZ9Csgze4Elj85qCGUO4x2AnUzNgmdbLbV+ZCGD5R/gaE8TAYfgSXOP0qBHCzfgNVq/F
2uL66q76Zwehhco0KvJEaFtNmE8mYQqTCrrvZ1ElIN1u1FdVLLU8ZcQ2wmmwi5Bwgiqu0YmS8+9k
mi2hd8VAZnjHEfkHWv5JJKoF9ACnwnItenI1hWxDpWZTb8I53qs7o7MTFoAAQ/NyxJG7LJyxNcln
ocDPtAtVVl80hEwH8yfpPWRJAc6/6/dXv+rSRQLWRGivILXl39YblI/chtQHf2yP+owGyCAmZQ++
TMlm2zanSjvvUpNclfqE0n+XEGT67ADo0nzu/E+tOYRqCfGbm0AmBR4c3aKLASrDJjgZOU2VKrL+
x6s5B+n8THYy13GQMLqBDMuGVfXF81ZReDaYHPDQ23utpxUu41MBuwWMZvTIYca2ihygXYorBfEb
/q/q5EPK22h1LHh015CIw73zArwcxa2lzPBU6uDPsr3yw2JBAVQbgixexzJJmadSmQIflUUV2AQW
dXbndszqeYnMitGdCLSBlsyJ7CeC3aehZDVpd5VPl65YtcXwfaU/KC4z48+X4dmiDEQDGxFFYKQV
MQl8GNCnbsp8X+1lBpPQWMBkjq8sPSJ3rCkpN/civlxmklGUMuo19ExqdeHO797xSbSaiSWIQf54
9dOnB5tZKycDmanZG+bsjmlEZXLZQzBTyM5Q0fu3jJ97iaP60CQjISSF6wG/DvZiOqHbs5B0Jbki
35DKsaQMIQfHqD8DXcQaARwgDZuPs858y73UAZ2/iXfIG1iXsKMt4I2WpvBRNepxgtg+x3WSpYJG
Ny0PRnAmgA7asAKAPcrQEFWT3Jk3Ixm7v/fPA8OEjyWWsaiTUxcwjWYR0v4N0G7uhMM5CLFRqvBh
NqO6KszWVevWeMnDzCGGEq/w7Q046Y5W6CqEOsk0CrpLud25wxpCKpK7gd5ghUe89uoYFJ6aNP8x
s6aFAODeE/VBGekpibs4Sm3+jttuGrBatucbtylOkcG1KHqJ+ZImFuc4AKiVFK8cCSapJqeq9b33
Y5bCYnU0Fp67A95WPTRJsIZdb7iLhpGFd7bjYHFUSW+Vkqs0gM4DKsqSq2NgAhVbPMWFj6qIGtu1
t/NmVAx+DhO55uUyRxpg7Yb7IIWDzxYayCQP8khvMwMp6++VqZTfENUgoGLl66d45FLQdIzJzdGJ
zMF81omBjPKUISJk6pfd/PvndZbFPQM9RES9ito2QQihbY6mjsYtWJMKuQmRBba0Q3llPVI3iUul
ErL4/8THH8oJpB5ioXaP/wHgAw7laJ9h5nu13RIwtlDSbF6egkGqZUquDK9wNqzshPnq5BQ7w5PT
U+4eDW3p7HpW2WyzAZuhL5DFgaGxqMd7pt7REdxOmfLJoVP9c4m7Gx1s6AJOn+W9tVPaahMW4jOL
9L+ZHpCRDL86gq+lqqsxB5hRpL3iGQIqdkkfqwfKFRQD+fyvQ2ew2Vc4xHvx3+KGmYuPN5g/UZBT
tjA0mA38ZZynuIhTBRegye059R7u4Pfs8QMmQ/zdcF8g/NJRC0E2iOQWkajZwFetRE2GOrWYwJRr
ORTRcqyucywJlOKg3V3gC7CYAXlGrD7EoylFC6Z6aAnc6GcpOTof0kM37N/SZTuu8ghLPBKNZNYt
PMeBGyKKf8zyuFJyPxqGv9qiDo/d/ioMNzXu0sMIeNHxeuwQzGvrocJHmx/Gj68PPckWONbOqN4f
OSJKa15zwQ2Qd6Lkem6FIvRwWi1bP8eYhiBciccad7pMtOVmq/PGRHvvc4JYdCw0mkF9ne0FFZif
GNPRM+vM6M+rOmI2QLLVGEkt11QegkEPEVkoxOJAMSCjBc+E/6mo5pQF3wri/LnmyaeBTidDdKno
l8XnP6i1P0iL6WhUfmOOlX3zzH6q+whTY+RRDD8paoJV+Fl7qmGv7Td7NIJg5gg9lH5bzlBabLs4
TvRP4dtvQhwluSmRKtVqCoEGgXFogdXlPnDhAVGV9LdcArhwatzm+225GIw0+ETpaSM3A+X+tCzI
UgKlwtCwxXZR/cbkorkS/SLPhTl8E3Ob7pgWi48uJMk5rB1aGS4MsMCCvBE+YT2s80XZuOt9Uz4i
Jo4pz/R+9lDIh7tVHAuABCW4yO0Ir3d6j876Fwm2AAzDD2T7GTZM6gKuPBhdi3KMGC3b6st7bwZm
24H7Ns418nd31ET9h9H6PfaPpUML6hw7UwvaIOtYBFUqF/qf4DkoLhziU5b8Tta1mLlgIjQa9iQX
Ck84uYnoOAlhyDMOiXUWCr+qd4u062A92iekGUzddxi0c0UY1C2zUL/Y2+iKpUBOZvFLF7dplDjJ
5YPWVHPY9JY9g244+Sr0B3Mn/VRpf8rovdTlQ80tw2kE8vNR7lAtEVHm4fG393sLdb6gzarRVSTp
rai6GUbsdOv9ckZWCGTUP1JYNdzQnLZpeJG2netKgLn9x6EZ77Os07HXQ+A3n+w9Tqt4ABkTqKfT
GVhxrfWv39Pn/7u5E/bfnAdxvgHOls67wzZDOSWGQsFZjjg241+YRHp3ItfjqrrPESiLLvLgC9N+
ewWhvB5f8R/DCHgWGef9zfzS3PH4cySDQ7Nm32spoUoJAqjsoO/npJWe1MkH+uWpTr1+U5nM7JDI
YtNnTuXr+hpwHo/XpEisJT1D6Ph/+xXu31Yqd/AhzRUvvCQ+gKzQQMDti4b+grBLgUHqI8kD8dkU
RlX263Cqw3fPyAdhaWMjTkz0+lUo8eRDSHpfYwScC/ullWELPf8AEZs3Zlrr4oNyL21EgO/h1xIj
3IYKnKmBJhxfI76hj6SNE2T5tcgO2MTyF2yaBEZDRQ4DWZ5FjwbePTtJ1ju2TjQ/SrzOrSUizIq9
kRZyq8eA4Q3/s5+PS9Zpegk0H+yRbgqDY5ZuUEdI5Y/vS6vwhdyC4S6XqsQAc1uIy5SE3bA+dt+Q
Pb4QhzBfysOW5gwODM3gJ91EeVTOmb6Ebi5rXPcUDoXnVMRSJRIPxr5SqdPMJQXMt0UDtNzWXVDl
0O0mRP7mJcWJ+kJm+/IBu8Zr1i6p65EHN58gv1m9uUvjepfabGISl93kNclHTp0AZOOb8gLDkVgG
dVRIxdCcQdkH6JRhmByd/ofLbJKzrUPm/xEYmyymMp0brOsW/V8q0ChnJVr2yFvmU+j8qqzWL/84
OqQmr4vyHKMQ3ynCyGAb/e8FiifJwYz4y0zFXAajqucPkFaBCk7q2KKINi8yRA8Y19cyVGZ7Ee5p
+8UxZoCwxy/GSZ6qOjzF+MrMz4lqfkFpVWMPAetuAlS1ZIPz/NcFTuIoTi6EjQy84OoaqMq7gjBK
3PbMWXDsb0goeQvMVTBQWLjTtB5eIfTiiXiaiJbrQ4bBRuf4Tphr2F/t/nkj1ItXTpJcEDBkf+OS
GJklgcvnuRExKp+iEaR247J1d8pOfvyWp3dGMpAEO6ntcdN7VEWs17znO/JmHDvBmskOHclu99Rs
WWjgOq1nideHPiPuLccTesoBmXREfHRY0gZF//Z6v+EtcWDColEsaNXxguRi1cn57Wz5EVMFisou
oJpRZcMu99O/QMwgPo/naFqCZsTfgGCvHg5BpRYy1KLZPkHEQzJR2XOeKqMjUxDzho4st1UlM+y+
iPAste7bm7pxj7C/dj1tbqf5atW1WGnPZalB/NtQajNYTyx3wYNAk5KQyXfz9YVDe83i4me6tVDq
tGeKYKd4/KIUKtjzcohi0wjizwSf1uHbu8b1zU4l3JFLjYpbMS4O75AHFnFfhNTXirKh7/opvBfH
H3WABnl+r7a9ZyKQom41mwphu/WNezAQAiU86qcEQs1BMNIUw9GSoxY290JyRJnr8KZ89dLPlAB6
Ykd6dKJoyqNyVby+MI1RK3v6l7hhLHjCyk7Jmpj3Mpa6v5z8OMR3yftm3lhxgy8ujGSpnqJXHONz
NZqL132cH4zR5wvXKX3VT/OMFsUIhfA8RVbRo3BbOFm61Gpznt0gY2hBH/fU6KvxmwRFhai00rXy
kdtkeuktKghMogYBAP25MXvQvZ/RXOdcMhGKqib9TxVHQJpl4s3g6Vj9mSrIZFuheNNELyrujZ3v
GTHiD7I9WbnyD6+O962DujjI7xF+KJUHcf7oNQ8a0id52NuRY9huUeGQwxFi1VLA1XQK22fkGElz
zst+MlhyVRzywgsWFk/X7M0LkmagMX/ZDyKy0YwNySabVxkanTtBkgcJ8JyTfc6nPg0IGH1YORfg
JfEuQMLO6thrfjyGb4I4JmA0QXtXrjpHLwRnL3ZqaTkUwk8LsS9vKL7SvGGlTUMKIOuD68SA54Cc
qO6A08rMw6GSTrxK5NZyChFDuHlEQY6Da1/upY6qmCwgn6eDDuwkqa3IoaovSVaRItRvI88inpyt
vBw8BBh2dqwDk6bqmD7gpF7+u+ZBsKlpZnfDmJpQSRRCIaOdevzAtuvoae1drGjZiPOMcpsZxeWg
/dRIsU/cvFhA9DW9WET69KaM/xy1EJWzVmsu0VBbuyrbvSJNU1Oh6UVVyq0F/zt41gHSjVP0xYin
dSWjQNCl4h//9vR4+u/wemnO6VQR7/Si4aIFQpSRyTJumpGIOgweRsmL+LdGaUiGKyRlxQ9X3vUD
lrYqCEevl0KORrsR+Ox6zTmxNlro5IOrWLwfedXy1ubOiDXc6jweFzc8ny67zXmK4xDCauzdqHot
H6hIenUVBU7J63WbDPb24VPggYL1ycbgvJBLy5hUIGOjeTpAkS35FXNgQw2kIhIwAJlmFBppy7le
ftcI0ALmcjKZ9SuswPwpJRzE3+UXciVVgPbqLkUPVDf0eX4iOK5iDvGYXrl7ZSc0fg1CDt4hRTgN
4MmcIoEmIZt7e9L6v6kxC0ccYec55grzLNCY8VIVuQeuw/LWAtRATXNO5MoYdEj8pxY52Eb6qIvb
jy0BvESQBux0ajEkmuD7urNhAvdroH0MsHjN9CD3ILZ9SSu51TqRx07VH9nF3ZhDUGYCZ+/Qs9cx
ZkTYS6GwmIV9qN25A6B31VydogLBpcoG7FeintKvKoI1XQc7LZv5kIV6NmM2Ubvfv3wbBSu7M/nC
6UXxu3kVYvK96QOlrohMefPFaCf75ETWmfzL3sGOFoBicebosB6dQzwEb73yNFczDHpxa74iQl4P
B9ZsVmpRTXkyeHRHz27uJpD9xowBhuIn/RNHjjTrKGQC8n/45f6fBsHxynraTdfUvWafqLGedYRF
LRJz3X46YxTSmbV9bbbqyYyHOswU5w9ZpdzUIc98Nc1B9WbL/+LMxI16UasUS5uZ/ivIYgohqULQ
6d1pHcuXTIMtm4jGwC7kLzr8TOmqg/DZlL49IDt6m/mn87EkOBZF6aHdQtInXNtpamnf/7E1t269
UkZpOICIfrIug1w1Hr5hp17XqC6R4bsjzNIArc6Gn+IiiC5DwqtsJwVW/sEZz14PhpJPCzwO5IEg
2t3bdFY4efzd+9ngflSrtdJaIcAh1UhPWBKZoBgP1P4yeoib2Ed5femcTZ1LEM8l9yZtO8wpNCmM
4B1QqKUU5Hy9357bV8Vi48HJF5S5g010PqbtqqTMDNv3fFbcWG7vFxRgheoiDvElh3Ce0QfWKWdh
DpJMyAvQngmi/37nAcA2t5Z16jyWCCo299UZAF0s7m5oEVP9MMtroFvN7OkPIK1VaU90AsVJVJQa
EKQfxz0o/HFM9fT3tpON0nL8b6pimER5qe9okTvXtAZrPOG3U+diczZZYL2kVKUAvpancDDwMMWJ
gfL0rukP1Zb+jRvZzGkHi/8qrSu0yV9bFXYXgi62BLAEtdo2Vf4a+30ifFQbxsw+7+aHCvYTH/dx
rArP0IqYO860JRTXOp2mvuwPoRdGxLsDfToF5UNmdvByAvkoVMxWfO8QXqoeQzExuIiagOpSer6l
YI8Ur85E7r8Gi8JCHMN38TlKzYNZYiBPucM2+HYBPlYIXDUVP0WyJz0oe3U3ajIa+08EJJExBjKA
K7qnnhe1vlGcGgscLfjxtqZteeNCIkoKeERw3NrnFP0Lgu4+VTCbum39N9eWwbDvCkj/Csi2S6k9
C6p5FN/6gNwZpuKfmf2NzovC5G36lByv+1W+HLs0uTOrVl3hv+qV3ymZEikmm+8gd/hCrLt5nwEQ
d7+Dweouw2BzemIpGOZCsOjiO4CSIyBUBNRk7qip/uywSzUpmYw0ZjKsAJF5icVEup0Gv6MXmVQA
qNJnAsew3OkxRb0oDlu6+aA0Ld1gT5tIRTSx4tKznmGs4bTrpbhtIPC3ntfWwM6km7cIc1qQA07X
Mgvqk3qXcSL6UbDOWWNCpEpRl1AsEPvDmuEy4sRLLvVNIqGiNz0aW/f/kuT80uaW/J9Ktnn3k1/D
pmPtYM5UHZEuBmrmeKJctGrbniOYGxQ6aIA1/VZ0sPzF5qSrLPSHInvrmgobmGTZ9QGD07yNQ6h6
MZbckzub8d/DHMTYE+BLiplP1+enVmeAOy6FrTunBUrXIecJAeGD4P2oeYHH6qKwbhKtyZU3EOgd
EAtAiN6oXfpDDf/RB+0glQzAusYz7lLZVUw2ViEFARzyyqhFf/EsKoHJE8i/I8oY0dvUr5LU5rjy
qT1tw8rUGqMS+svylS6aClS2UiiKU6lV8sT5tdhZ1vOI1aNHQz2/2pUduGixOF4YQQ2ZNaaaJQca
WVRMXylRzn2Ey3D5SbCOEHdbmIE+3nZemE1Zxc787bNOBQeX1D45Sw9U/lwT02BL37F16TcyEMmh
GJmdOK8oou9+4yhukBoPTFxbe7o0FYLk2dME93K1b7bzTfwwPMDs6vfKJCovhwTztsP92FFEkE+l
6l45Bipw7Phz+j+4G3MO53TD6nQF6Aq8/oXvFa/fsbztX0kJX0krGE56b08J8z0oWZvToXXs/+bu
TCuP29J2d0ZfJNWmXQDhrOqlNZhSHKyvXMaL+xxnc8QaGmVnYT05qdLkgbJNmRJXZGnNNfI+xcwu
hGfrNOMsjBRwzrxe1YD7S4ySF65rNML7/pfGzvrmYHj21T1CsELXfQYzqOrVGHRB+ROKTGAgHvfN
omw9Oq0IXZHznfEYZKzqKuAcqlPrSaPjycXcB0Xop8XTXK2QH9wuYuyVWW7ns6ahg6wxhA6xiDLB
doF6qN4D7gMb0hY34VgnfsFn8I3ZR8/RSw4JJ+RMu0kB2hEt796JbeQZHtYTpqgwP8ZQX9fG5ojP
6Yng5t7RLeFuXk6JJqzSOeqbOSNdETxh3/slEH7P9ITGGI6uvHX/IQcmcT5t1xuGPqydcDU7JT8t
P9OgClQuMKxMrS6ia5ZuIOHdubHtwV++fS8vl4TLD6NXaKCNuXVNM9gju2wvN7nfsZ/mya8v+YTY
dJsrs+BzkL5vO8aPEV0wsr5EhBuhuP3BPlxU7HxADmQWrmYkPZ6l+tj9stqLzTwVMfJwdC8UppT1
O69/7bY30eIysnz32LrJd+z6C7AHI+Q2Z0Mf3pcHuyiBtXwhslGyekDwfyKGc2R6IqPD/9PL+nBv
7rJ2880EDZDGFFFDDG0XZMZRGtjkVyF+EJQltc046dk66dy4ZdFpclels/nc/FLSHfZ7NexbeRC+
awQUzX0sTgox8LQfVaGLsHZs0JdU1YzczcipLgRsUHOm9KxdE56v9z8GWXe6cs0XFTFtRBDsUtlW
+aq6AwNugFTJ6LecIHOUz6Z9vA9UQy7i276HJfAUyl73CVDgQo3UaO0GWQ7JEYyk1lSd4sz22j7j
GGsDHdF4KQ9oYBPXGrT2mI7x6Iz7GSwtVwW5oJ+UPZGIOvbZMYN0b4ppQ/Zn2uVmdUB1Kvj1cNxX
KUFwVOWB7AhuK87fNE4XrubVdULQkdW14Qge5bAvFo4qOSiDIwlNKVsaof4/Pqs7iHmeCAdCyy5u
cptOHDXIlxaZTlJGrVnVsrvQ9Rusko88z8n7gb7GtfbOTl49xMJcirS9bohe1VA2VnH73irnquXU
TSxemLvqgRJkU39aokRM9eRsJdxiG9KmOBE+1/HgDnLzc1Tgi4tJQLYMydA4AqfLfJLSUxg7jFLB
UDK9wIGDKWiaMpbsuqYaZ/D0FdBd0EllEppQ2LJAMtjfjFTB9jZ5HjVgyadrSBKlEcY4fcLP0Mai
osq7aU/4A0sHUK4mU6nxvWgz/2MOTofY3b/KiYkztLzAY/1qQoXZ4Cb864y9heEzcDFln/TEeo6o
0RQ0QgxEeROGT3ihlTyKFaFY7Qf5GYH9y7GsXEqOeFFSlcaMqp0U8lceVIqQTZ41Yl8XO7Pjn/qy
z3YNOlADNdqpABoMNLXkDpJ7KaiVhLLVJIoKuUGsPfxhY/p6Q73E57Mt2xDyHibJ+nOUkXu7DTkJ
ED6N0JYfMgHO7UJsz3MDS4QpCjsm3lgQz0pMfVLSsvl1wTxPprMJO1sY3fDmL0jxTLtQL8n2Po7g
/6TmkRFMUIx7I9LmNduajfnqg8y2IV25tXfoGnEmrFGmGjBkOMRXXx0TxL1wb+0wIzUS40083Hlw
OWcSQ5X9Uzs2Ji/TnL9jppf84+kvibPFIquNbfAYn8hE1OHfsY7OB2DvoVMCA+g93BCHJ7lMULEr
0MJR7PN1bfgheysLJPe3lzLZZWk8RMjPT300sto6fB2ubFue0J/c+5E/i3AegGFeaJ40lZawvHjO
gbNkqDxAoLLQcFiaj46DXbTK/5+wMvGTOx6XpF/Oyxzgt7HF31nncLXHHCF3Ucr4H7oL9cSsKGQj
652ntZ/LpoNCFxG4DpcrYNm8oCelmmYVI9NjnfLQ8Kf4FfgPYWaF5S1YiOz9oy2FE1nxgGNwUqdW
P28crIdhq+6NmHGeUTgsa8ZQAfGwGRlb46IixCdM+CtndNGgM2XnJSW2ym5vPfQXH1L1wlXFuGN+
9QrT+qp/2QmqpnejqWwf3JY9ICHCWEDrrrbfMJQosja3py7oLwCvHFdrgSlhpNIOFgEDzrqgxtZE
1ioC9Bl96ONKLVckpRRdpk1e0c0e1gAjCssT1ON4rUip5RjQ9W1CqwwJrSyzp07BBEcCvkmLJk9I
tzIlVrj8J3MNChlSf5MxE2QVXrMuulBzILPMQ+0/j/rYe3aF5ltSurGZEldGI7as4aYjmRxfugEJ
rtfqyhisAT71DN0LyR1NoAnR0OZeg5Rx86tYeUbbSiBY7uiOxrP9oubTLHpLJWny4Ix/c7gWqPxN
9ShsiYmszBlhyfv7tGTjF0EjK8+JyBgdC4qjRNhtnnG/72plTR9mwhOGi5wnHz9EDzV9Poik4Zlx
PrzmO+NNZ1trk/WM0Jro8xBUTlpREbvmQwRJvhflMIxr/pL5bZyu36GVcNZAsE82zfgPw/G/hmPZ
LW8gEheLSDTXwlp5GoHNk4bPOYXC8O5nqr/0b2vQQ3xRixEsxaVlJa5eQCHJrfwAVIwk/6tBfoy3
nFaTzyuTKEUxcl4GepTqZEzlQQIF0p90VI7IUywlkLn0/GeEr45EdOQG6Y8ap6ueIcbgi2gVVk5h
MVF07i3vn63m8DeM9+wzwnONN8QiC5guSqaJXnhCzaHF6m8qMcVf6P6Wyj3URc2D3aFV01g0Hj51
1gLMc2hB/GZAHaguF/DzX07jtCEzgC55W/2e6yc+TEKt3PbLsJHwZaMZY016wIlheM0xWeLoLt+0
r8VclwNz6Q5/e039fMOJWTinOEGdTWqTLAv+trO8xpwfEluyqO/aQ2lEujMHef20GT7fBTJztMSf
LRyMjMipSYMlvuF6WJQQxiMbKUaJSkriJCOtNnZkkWLNAxQYl7YhSayyG9+FI7oZ4ZaMsFAclN+i
zfPdR2YEX1dbFZ9YId2aFE+iiP34xIzgi/9KeSc6rrfUsl8rSeLYPgjNZRAaJPwhkx2HD30KwZn4
vCZ4NoAdcB0wgOcwaRB7Q8OJwt6p3G1vTKNoMUHcFiKbut4ogeA26CucI7pgRYlXpzuOHq0SNJJs
777I1Hf+m9imJ5RresLZeRPZAk9EIbXetgBfK7N/3mDiMbwQ+bTHJh/wvt8IIgsHr0aDPPckGMGB
+q+xxlrl1z/GnLdkp5vVo6BNY90od+8CasFb97x32vQ86nTSN2M0kCAN0DkCSw9/glhBAeOwtG9v
xQMca8mo1JbVvge8bYrhnGSrefviyrKKCHbFb+CVadf0e6meoYLUIlbGucvpey3KNeTmxuHQBDip
hKGtgTRJ7xD+WyFuTKTgLsUl+wovoei2y02CQ4n0xGemYTLAHc2t0x0TLokzhf6zA76hXv4ehL6C
Eef3g4al1gclNzxpwlFTIzGTMIWf3CqOpPNOEwCDlAayu5gB9Z7/VajAw5aiMgL5bfTxZ+l+OdCm
RkouTjI8RX6jBvnIYVStYWIzO93kKjPrU9KV/9S+w9M40KeUr6Ga8AMS6QCjPLfVR3ivN9sC7l/8
2KvhbK5tWfe7PULIjoaSf/ES+TrH6mlOYodv7ndBdZVait/RBFfcz3WsxzB6bV41LUiQ0anjcR56
UUImmVAjRpphc6LR8iWXli95uRlMWnZharP+9Ocbt9PW8TaY0o8bJuIF33KT/bRSF82WGAvfg6fc
zJdKP3qhuwu0fIhQsyrPkmZQvu6hZkzFV0SlUgNtSt8pNU0uJafvHwLpA0OjaIhxURLIl9upjEki
D3ZvMi/YJbmXyVkXiEe4/MOO4qGeBNcDw49zAscK6klYsudAgbqWeW2CqW3mxV/A1LzJWptAw7X8
mzklYFW0GFC+7CaovZfC1REYwoynN01O4no8p00YNWs0hTeK1lpmm4LZxVY54qy1WBbQBbMDV7wa
khEnSaCYcwicglqYPK9i2vd6JzZs2f2hXqZJv5hnG1pGRguXJdj31s6HN4eQd+rbRriNw3yJ6io5
lSuov96ZHMI2Z1E/35NKoDI2UQmaroSd6AHaQXGdPRsp++Dnwd5FcnMFcVA2jljsR8zoV9cpOmJ4
3TQ3pV7T2Kj7gM41n/ZcAc2YWHWdecslJbwEKDZOQw/y+hvXVJJFCKbQeelaSa6wkplPLqIezAJT
pqfpLenQFT9nkdDZ9c3zsDrHjp/FpeGYs/3tkxjf28w6SJGrvgyCoG1N7+BjL5UMNRLuFTnECAkE
DcpJLBm2vedpnEl4BLmBFu6SdltFfRPiE+GsLPjKAjaItpS6r/RwrtwhW4eAIJoTqHvLqUpN9OQ6
iBLxAPuj+iR3FmykRKxHbXeH9tInCkX6pdWTrs7XH78DgdEm4QLCXd3An90DShac5Ld/otZHwXR3
j2Lzy4UV8RbtjaeTiBDNlbLyBQWK+g60620brEJHP7vMKWIlWiSHcVqT5jGqdaWqUA5ywVHUqnj8
o+8nNsqYqE/xh1aAIeKizDCmYVNL+ccP01I9DjmompGMlHNn6B+mUqgqYdeOZWDwcsCj/wYVx1fL
lYi+jR1XfkoMyvg5lotCbWzCbPhOZ262Yqgt2PhcUKcBCWjn/48VqquC02TUzz4MW+viLTIUKauC
bTnmSyxjFPyFGfZCQdG7Ob0QgwIiLWz3VGnWcnCuN5RVhKuPaFGYC7kXRwQ1jnM4nJoS/MNkHoLQ
jryRP9GvaZ5xLwDyJ0SxcX6V+9Qhk7977sXw9Guk5+ifW8kKB8wixxREH5QC2xT4H8GcXRCoBDl9
/DBrli3jDwizEe1rK7LWDuUks4+A+NIR51t6ojNcT88GClSqpqZNL2pPcnKrntkz5HyqraBhDvKF
wzRN5rcR8YT5X8Oxw306C5DjChxD6kIlgrc5g5odieG6TC6tc0ZJFhmIV4kfKPYPEW8wa8VTuTxF
nOUD3R60dnU9oq+lRGJ+OARSxbvnUjM6btZmlQX0psoGOPcqrdyu5tWFJLbsIT7S83Tk7I9uMogu
AmVjyKt/AkWFSJieXU8++8yZ57b0XfUnCnVDg2NIv+H/L9L2Z0he9V9vJVFbwScl86i9sAdme5oE
LJbsFIBJdukPMy/+MwypIktXtdxm2gXO6NPj1AToF0m063bQ61/QnANgYdeyOniO+P/GQcD/D29u
vyEq6VhTjjaHk/diVv5MjEB8Hr+2VaoTmC4AA3IjwI8fFFvbXAyekLnGtgxDBOH6QsSCNEU205mJ
6S+6setWyW6jPsS5zGySQge+nfN+wQ/aQtmk4988Yg//HZyNiK5fsHQC1aHSwDmDgJc2NKArMcGg
rnOe6Pv0DYlCzM11EILnaESszOWhFhS/NHti+HX4ANsMnFZkTCnw3icNopshwQ0yT2mjWjdWJYk5
2WbXVkqDaZ2HaZ4lzs5X6ZdtGCDOD2Y3HKUbeF1igYzhoSmRiint0PeqemggyEIjVOLf8jk9lCoj
iiFsrXu4rbP+3kvbpYpgtsRSM9gRm7iTG83jPXYdJPETl82q0L3MxuwCiQNX3ZkcTZWusuICZ7qj
+eWiJtzPGswf37LZNMSbq4z7p4Kp8isKYUI4wg8NSnUlHusxq7dRsopKbzB0oH3tfTA4qxSDcIv1
MH5E5N6MxGTWxbOHBQLsKBoXhmoKq6TH97iHeJhr1N8r2EgtVBwcYbGY7ItLgqqErPjiNYNnEue3
ecYwn+5GGnk0wLVayXE6zeME8MJxhjC9SzkrGul0GteWpqqYPygVpzBqYaq+vH+qDpxQb+n+CY97
qmPVuvYIRKILR20dn+nJWpU7Nb3rDwCg0O+7/aJZor5BGvWe6RCf4IOBSh6BDejMuK8HzqpaxwAW
35uVeqieBCXYv8Na8gByu/MvJfsFIamjSTFAR9ErkijcJ75CnoBJ5YF+6v9v5YGAIMzMSvrTHyWD
JdDxm8B6ZPyrsUbW1gscoFwWc4j+mz/RB9+FATeJlIiLNxaa1MdnxYeOYNhSrJ4SMgMR+Av+igk0
IzBZzx6Yo4hzGofaWKLqT5kavgouDhb+lUAMy8StQrc6JM39Ebdo3tecx2fLpJeJBr221jmI9CwS
xSZbuoGEY/PHmKkuc2rI3jylDFG+1eFGJq2NYaKd/acnPo/I3Ru5qJg9SzWoAYr8gKsQiRvYvAQs
HOhQdmALtTW9rtyeqg/MF/kcqiggB7Ifm24/gEoRXb7Mw+ufziWGkGOCk1rMZbD0XJORfAbfV27S
VQSpWxWjNVpjHtZZ1tebHorfQtUBR6LopcVuScP7OGla6WbAekQC6DMyc6EU5kZoQnN0qDpRwAKB
yNMTlR9qCOK0vJMiBhNXABcOC/jqOgJDJ7oDK07CmgL2mmfBtCa5BwOnlvNW6LVqbM8+ATZb6GKe
YiEp1imTqFI7j6CNhKdsVRrD3ffWAF8VpUa6Qkzs2/VHFTEOlIxvCtmmlj0lE5C5V2K+KKf6+9Tn
aqCEbE4JLhQ+k3ii/S8Cr6ufuMwOjjQcJ5v5tYHPa9L3irk/Hd+q7q5B/DlUPuk4pWHDBIKTDdTy
fQI6ckU2L5NPbyZvP09wK0/Bp9c8yWgbtBd7iIE1+lUsPOXHKjqF3pBmCKNn5Dvf4IRhwV2+P33j
/b0+80N9SwnkHItMwYwJLO7zKIOGlDORBxdSc2IfkKGWMr4qvHkZ/YPthpz3lYupJ6Z6APmyrwmY
1laR8va1aWphe8LuMaMn8BRNYM4akzXdEk6a3Jn9EOLB99H9Sg/NxtiSLTVtN/AjqvfFpt16dG4A
pDA5KkxjVpc9GpZ8Fh2zixRG+esOIhJRoL29bQkLivPuJssp5LuuBPK4fuusJV1MkIoITGZzndAO
rY3m7W2RqI3+auvKqE6AVpfDW7cGMUgbYGC5LWS8d6MsQHP6ASCZetVfkVoaTLmwTyUyL5wotM4H
7yrAdXjoBEZ6sk/gY0cutOt9tS2hAhsbdRs/SlQCaX8SUwDcaq1qgVISVEGpdJyirkJXjdQjz8yM
0Y8bDku0GEGZENr5ijAmJKT7r44ivpOgWfYfqpkwc8lqBp4u4GlS37dqCzojCi56Pn1xCcRCTRtL
I1b4cQVptIfepLUlTRJkODkwKpGP1wrF3q9gE5SJPUpDGUl4w55gPJjOccxt1ls4/ZgLgSzxinF1
lneYB5VfYQY0Mnrl0SUYl8KDRRB8yJNbtnZypMSdBP5UrVCxOvAT1ib4YbYnFG2wlZS8LRI7OX7X
fabI5fkyCfxzwvnMjEpqyT1WJmvkz5gbmzbekWwU0KQ4kIzijxct6DEurHI/LoidPkSfY36nDUgc
xoskrJ326tNtY4x5RTJt2LhzPmf0bZ8nXgUFY+N6zNPnrFc0DZSvTdgm16vU1EPXHdvuSsDZUmFS
bG/HU9++BgwI0fon9Zxuh26RwdpC7yHl9T6DBZ4Lve7jdsxboliU9NX6t7jKdT0wySR/1Y6rIr82
fcISlWHrM8ISgbBhVhRfEzwnlfmS5LWzo6STvwm0qwgPQqp21eykWvj5lfOHuC8G8Ukb4v5oeRuF
Oy3KrLQd2HXdA9l6MJrz4dNafhnP7wNR3s7RDt7q4WseNl2YW0TI6yrbdg8keMP34Hv7TMC0VVBj
B5mM9AtpeMdURFcQBeACXwD6cpGeXm89T2NMzaK+HIBA8h9aymH248c38Y62nL/+TkVE1inAOFvP
MpZEhM7ypPRaELgVFxvjCENZF33Xz2r7qUF9YxzFE2hkLUmc8HqAmOxX/CuWJI70y/pk7H4K0WG6
Qm63MAPSZ4XxW0kdnqrnBAe6Z5Og92vA8H3TwLJPVpdzR4KlsndTafxdOD/jqvHbYgS99xwcYcZK
nu3AfUvOERktbc7C9E2lhpsdmnc9z8LyYXfbwXWZHYAWCcvpaPxbKNT6kEGLTSqBbBtCHCshwLTa
EClvddRcQF/k9Cu+3cr178zrxi/BT87YZl12yySLER63PgDgiO/gq6FvqTpoLqejS8OU7NI4L0NC
HqUf5yqGzD8ApNuJ4pJxowJz95XWAhJ16fif6w49aZEDBUVAafYI3nkz6ZmaW31NQzjPbgk0iwa8
JlDxQ1Q/jL7AMoi8GaYskQAdze6aTlEnKtchRswidOPKGESXpxZSQRMOBkqU5JqueyvkffFPWEhN
3SLenJBagYwbgZTazxh4uuKFX/345UdvByz+/rQy7IcVGZWuIEgNdlasvyLQmc81BYasEV+VcCb8
du/1Of2m4lyTmKuVkEnWFvONOAZWiA9ZZEcPjxZLWMnnpHO6QUkhjw6TQKdV0F7YVth7KtKiwcnB
jJTz+iGIN5a+kQbzqLOj97MLgEp1JDeVLnVx4pvh4peJccKz7TCLGO+9rKkJguiDMc65Pol6Hd2R
zfEclqx8TAeGvSAI9Mug4VGq8lz6ZnqHIF4huOwUG1AVz03MNsoFkYCmxRvtzz7HW6uxi0jRuZtY
JivM9d7aQqraxN5RF6FzM1u23lJMsJCXDXCfm31zR6ms9XXlvtZm8B2HVUbB79G0ijvZhbrTJqZB
XEeZ+x7hm68Iyf3pOU2vYnrOvaaz57Q9exkQl74EqjsvWyydiVkVIrey77fhYZb7rwV8UWVjEeGZ
VViHU16fdnKTw0sdFGLFqLnADfBAB11ZguBLbB50BT+Zhb+ENTytFgvuOXXclcLZTICOZ/5fjlhU
IQVewx/+4YxfYsMwHQtmeFYJDR872o1dtP8MSaO9Hnq9CeppsSxkaIalBAU7z+mfJ9bEaUsOMRJ+
rmnRSeZhRmhiltxi7/aWKyyBI2a8cFRKN/ji6EJ7mjBK18cdn9dxnIH9ZKal1/YjLTaiymjpQYLC
ooohRXbOzSb0TR4EGwdSlNxea0OVB975BmMTHoS/1dBCDQZuI7975y8Z+9ANpB1I+zVIUJ3Pdz9x
387WhWZ9Y+QYSl1ovxWODmt9ySqZbsNg7vihLUngYN6dWY9NoGdG5DAMnfVYWzkv4PWU36vVro0Y
69B4gvAEvDj7Wo/7eddT7d3XY1JrTvxuONN7T3iMaYtStGvn8B0rsCEYVk/AGnDq6ngSGUFLlsxr
nDdPOHtUZKpeUubm/DcsO1ipS7arbNbdZSNZnDNsUhwmRusRKkBCcqbPRbUtYkbqlJdjvipl+nCi
o6mCV5yYkx304rxWjnXWzNCf2Gb+ajbWBdRFYfRyaC7OlCKNnlr8WOqEwghyUZLH9b1YSE3noYHi
LUXqC9XWGsdqwYeCUx7ohYnXfTmdDHX5Sccs2HJ04m7j6opVRpZpObtvltMiIykLQhRsiDDsrakN
DSqFyce1p2XJbFw6o2T2/NV9BzabY37LRZV1qMgPKOEfj5Lb97Zx0SqdrzunshyTsqwgM9UXSNS7
JG4rxJS9iVcKo+sTeMetockMQr/7oqVHnaCCaiuj8qFH68grZ5dF1px2PCFKx+Xh677dNz8kOSdO
CMBy2V6G9TRIKwvI3LLUUxhnCE+Z9Qzh8XhjPJNFlte+baWMEbQ7tVJGIbNff7a4sSDyJzZj4y1D
Mc4eCPryxvXYmF2QzQ6ZLNQPf+ICfRpL0x0awKQWjItnptKYHDQJGkHkP2J9AaskkvzjihfGy3Pf
pGwrs7bd8Bcc1Vt840NbokSuZUwmCWnfLKC1/1ptRIdu4aywfLAabaXjW0sJqbt/E8RcvDnR9XYn
UdvHYFlEr8ik0xoxyWmaA3ZUaPFCSYCP6k1OUCNXNizrNgSVSzq/rM1iOxpI90s45cznWTY0rNj+
o6OH0G7N58HlVnjShSw86fSEIjrKdQu3gkOFdI+9fgzJvTXdpgSvIK7D1qQX1jX15o9ghh6WVUhO
DYvKmzZvx9U8i1QRKMgOmwCZdNyN74gkqCwHpZKpLY3S7KftuH6HdYSMrzo8jphK28nok4A/wzQk
2tv8N5XLYyPh8c7BU9Ib5MpmJG0wa3P9WKYWL51+jN4pUd6G/kW7+0BvV82jev/HC8afQVlWEpLi
7zNYnFRZHO8f/2Nnyr4PWTKM1w9mKSNyNDyxYURQKfuitOZj5FC8st2VYJnOJ6XqPV3GhAnhTYFy
4gl2BregoxXYWzIcvwITvDX7XOXY1gh/UZ9fUrOlrZhrG6DIl8pX0pQPlJEfbK+3RAhzuz+SlpHU
s1UvvZaAsRlPPiVKOpVnM3Zg5tm8iMqWLxzTZrcVDQtSDvq0FR8l+ee1MkZVOLEUKT4MZijxb16V
roD49k/rut1DQf4+Ah0xBOCecYZTtkIYZBaYPkrqF2O2HhDcC6ERbQI8yMmhTOXOmlbCCPyOGY1+
oiX5kUSmhlIC5YPHvk8w8ePMzKxXm1kXzfdX3SmtkhhtVzBJtylyoz57bEiWyIs9tlNGVCV9KZs5
Y02mcDBLcYJT4jJckvksmkA95jiXTjPnFJM2393ZFtHKSqmMm/wcnFIp6L/RNTmhwDOPY5fKnAQe
2XRFt0TsXAJucigchlvL/xHfIXQgXEifOsX2tsxSoRwi2DO1kv7fjQycqV16bwJElOznCtSM8AkL
dthiWyiatFB5uK9XGeeTyxe7Zt8IG2/RjjpJ8V1pGtHuGZrow+6GSDoXkH951rguPJhMCgvjsM/r
kL5cY/36N0een8VUcPmJlOs61zcKxdmI492sKLIZF9/wKkhTkWnoL56Eke7MsCbV4U9sniGP+25v
OqKPNpKBJDZYeTbct4A7mTUlJ0qQu/1EKtR/f1D4+kEghO0hcsHXd4L2SPyH89QeKsgK5Dt8+dZe
3GSOIByTfumTVu3NCVfnpftfOWmDvTAw2q7dyI8YRrqUn39zK07rBB1ytIue26rRD4M8e7mnJISV
XLUjCsj6Oo0Vf+WZ9MvVpyiX5IuygVZWBrXbGhSgI75JHHP13gs2fEkVPSf+kaoATKV9Br/1YYVM
i/6oB7Cr0GqjP2SeiFO3wB0iDbptKERtx5ec7CCRkb6/cySZV67l8Jfy0D8gEJWb9RPgRSPpasCm
Mi0H6SZRG01i464bkFCtaz77tGxkQg9KYGW67lHRZMeGenx1i4qirtrVLTmv/0yKIdZZUzyibHEG
6fMbm/4WgWjD08R0vRWtlnkI6mYrdOK05eDKnh06fQhoxr+ofvrxATmkqsBPcdZ4i/twd9svLvkW
klYD3fRr0lRJ+xRDaYMKY3HcF0Cfao1z1uMfk4RZnd5woEl/9V41IPKoQ8dJmfVDq26zh1oEb19X
IETn01W3bklGcc2+3dsrZ7Oc5D86jmxQFSqKc34TfXytNvsh9pekURnAn8T0K+E2KjxfuV9zKml2
u07Mcck3Deoox7LvDt6pE75ZzBAnYK1uaYu+LtIygQIuYHQmAo5249iXSGx5uNVRnFngRuQSdCY4
Kqh4AseVak6QuviaDV0lvL+f2tGEs8rS4Q6dZpZBVP/xB7mkP5Yj64JmMGF4/pcCXMHfmv5qT9qN
lArKV6K2ugySweqoIvpKGjRsj6t2zPbfQuFG5Htdm9Xr/Vm70H4aOf8Myphx991HUpmYG2v0dh3s
jM6cxdmqSW8iu9bpEAFeMk2nRgaKh3ejWQo3eRWYWPSqAlRIZnNVxXzBJlHBt9tN1homVBYG2nOA
WuLkyApn79t/cfc6dzptydnufRBuDa/5hGAib8MHm4uKYC5h0CmXPHuMYcEk+Bok96t5A7R4XPTH
slv8jwVUgxqfaIkWn60cALzlxho1af//Xkw/uf6BGW/iDHTDst1urfo2koSjI1JP6ugUnCNjG1zF
99P6z5FKyh5gZWwL/athFTvFiY+eixonewzzEbHxsPz1ONJA0yW92nhqVxVzJ6p6vDiuowI61hUy
DSYmzapfMJRRVRw/mMDlRWj4ovQrAyvYhOkzwFjXkny5f9/dTtV86lpwVTjEBrKpC5jeEyQeXi/c
tePhPVMdRWU2yxED40Cggkf6yl0rw4LFaiCi5kIGZolfq5V+8FJ4Uxs9BxKJ5RYKuwY1ALJ0Pc7+
voe2KoOM2XBg0w0G/ltqVkwvqnFr4M+mtPuvuS7ega5uPk/kzEvkolCoXWR5COSGs6UT+PHXr6I4
Dzgdud9rw1z45x/4QHFst9dfniYypSQ3yNbwswNp5wuWTfkQr+nFvSH0TgaQe3Dh9qY2xepHAh6X
4iJm9AycuGr0lftTs7zjbq4Sx5kZM6lOIv6sL/Xe5lEAwNrkcZSBozFjSBXdIX+ZMxc9qHKG8CAr
B9i8BAxeTBf0lJqClxKNyDw2Q4rDG8l/JxjJO+rot8FyE2uYjGcg+P8etT30w0zTn5E6a9AiJZGi
mnFUJA3RpKq/xctwgbeqzhvjspugETDLnFP6Rh7eEh23P8zPaTRZSJDlb2teTi1bouYs4k32iAAx
iy9AEndWZ7as7FbBU2ZbJk5EjEPXw46EPFDj8DzlnDL+3irj+/PwLUh6rpLLeQEPPw4OPnPD1n1n
pjvULfiv1dfIpXBhrBZhATBsTXqw4zWWzOAt/lgrov/LpeIXHdh4v0dQP7t1ZhkcI+kFnPYwzUMx
l/3fzHHwIluWTegTv43/tRv/cs5sJU1T5E3CtKs3r7bREe730E4TAyRPVj1iixhCqAQE9hlNecqe
Nc9/w8D7uM3RAObXq98Db7ShYfMM5Nc0IcPjjagDrIU+kpF2YlTHMh+bK0mcKbuH4futfffFWBfU
yW2ebkLF1a7htSKz9FJE83eRNU1Clykj2H2PFAwkEpnXDk5K4qIgKwHjYHiyyocAA6pisNMDGTGO
XT2Y2ty1tnyny/zQu2e+zhzuwfwG+RdLQpI/aQ+8CWEjWxjZrxy9Hy9Kc9zrbF45MRXvTiVu46WT
elwcjRIaEx/PL8lszWSSToes3oYEsPi9nfODOKmUiOmSnMc8Fc+hUjColAso/S9EaWpwv96CNK9r
ev7Y8HjjzJ7grieFfjntPwMLPFn8gbOtVpbwIy1KOxVtX7NmnT0O0eY05zCjGdQYKhSlYmXk5jYN
WEm+Q+vPwWf491J576RopZT+bXh8JbCkCyTaGG90Lv6AgFUCMztbCJhlPhHkep8tfJ6XkYI90Rh/
xDHgOLMayvtyqBf2gKJB98V2yqBaiENo/2uNXX1tyQNriox58tgaCbN6FbtgIKBglteWPX9uR7GY
IXmPbitsHE6/emuybRyg6d09wb0Am+G0SUcDDaMWg77ll5G9Dv3dGCx/pThfi7PaO+iQe0BTLzCt
uysxHQkihF9hJJaJOU+09udf9GzkdmIi1seC7A9/Dnb9yB6lfEL6U6k7aid2NHPqcpX1I5eIH45N
kBWLwaD16hBoTtIGon/4VOFZNCRkbaZcZeTu+bcJq1LyZBzzGJiQoaHPUVgslMBSSlXl7PaF9Kj0
6hdyGeuAPdGs70MROu650djjDklvaHuCKH+S5Cp1y9rKpCW3YJve72QsQVwaCB5p3br2rxScd2CL
H+zhEfU67H3iu1pERvPbPLKqC/IEroitomVPxgzZvgW2nRTL/oDkwBJ4gbyGl1u7wyXbPI3rDBIG
CxWva7KENE0Q1WMAK36rqrADRm01n/G9nWLzXCP3f8VxzN+UAVPTCpMIiuOvhLPu6AxW0pz19S2i
YGTL5uNhHGl2fbAoY004z3UoDB4JO/Pyt9bGAokk1XNkhVk0gDLImqQX0qP+QrxtrW15RoLhMbiz
CVKbiPp/CGbsXVmpifW+XLOeXibNQnpNWH+Z1BTcgKTDHPHrxoy34gYEbpsutq3x/XzgdGdLhrDN
8EeDZ88nKAQGVseX7evtAv8GZgPo7UQxhbuOhTgyrPCt82fqcX2AMt3xi8C6GLGoSsoS9ow7CWRM
Dg2AmgnerPLRmDvl3p4+0luYr6wXhEfG36IhVStaWGo0CvIBGzL8I9tQ6vdrW4wiE86ahtApDolB
7S2TbCmiuTiKfh1Pt+sWpeorRw9PSV3pRuDgLko85SMtKWqtUmxbNaKRgLRVD6WtWsMxeBkonZPC
3q44qG3zy/WGUTQGYoQskl3jztSX420ohXsc5LqGP6R+fTQrdlvtC2IEVH71l6Zu86VEBsyL1oIn
FkBm8ol3BNxiQMhWG/tkx44Qi06mNXfBxzz/okHe/lA+XobGl/2baM2pIQc2JtefFWsoCQgYH+Tq
tfx7WEryT0tkK6ESsCvgEleVFNGwdRYs8ZHuNcJUtx/FN84IuKphh7ZxO3kbM+mv2JEEJSD2/Wz4
plwYaMWrv47MmG3Vr9ws/M9x8AXCu2L1xMBrkSLfUvITPMLdh7vrllo1gRO9YDgdRen1pdG9i3rl
oDSZsQSgwIqDTnudyuoQZAxOaLZC+3yQuFP8GBQrXLm5qu99bLP+GtgE3csfVm4Z2mXNhHSnnzsN
jzZOOuRFOObZw1ixutf3XHLPwctwNMMBrthdQScS6jC165N9iDNyM0+AyGlymDGXwx7+wnVqifmQ
bJ8AU49Lk8m9TLDStA6/hDRIXrWiJPNzJPxXQ7Qn/NEMfIUvTsSet9jsqAH12vsukgt10baWltxH
Osc9J3jbuGrcd4WXFgfboOn86mk1RHsrROCKkBB0AwJJt2HzA7OT8dVZUk+6enTEdLZapttYfUC5
AN+pR9+43YtOqA3Jx42GC4ILxZ2GRtN2XcCxFUIRN8JBQGYdPyVCX1pyBqPD932zVkterm/3zHYD
DO7l2jGi1p5Y7icq46nGQxLXI3xbPOBg3TgvrP7vD7vAAyf862IddEW5Zwf7oXW+01Fh7aRPF7ud
8WGvbbwkfz66oUCigxbEVBLXUzVxZsmqEiVtYhH1AJNY/hqBeMAlSonCFaY3ZLX20+z0HDe9PuUM
SZFZ897h4AX2sMTVsCI+rOYFcRaCSOayY2xVcGlGd5flGVjGMjyqFB1H52tQYxXNgWlTNziqdz7K
+fwkZMLZDH0Im4Dnx9y/3Q/GB3lRHd1ffOuhl0LfCyuhCXNGTd06b4TPdRkxml/eRv5wf9PIXL1r
biO3hYa8/oOEJjWb/kfoPh3xtwHFlp/B6C0ceLsvbADsCZ5OeaveUiNsN44aEyhGXIkE3SqksaTK
udDmlN9KHAC5Smg5s2Z2+7lU+YA8sGSILIigI/QmJzD5KaqRRY4p7hBtwAqVXeWhZCmECuqlZz4L
N2DarXekC6HvjznOe3s2krFGmdg5kBBFPt1zXNACjudOYAGU3tiTlZzFPeC5EFNkJlhsOahDlv6B
U4KuDDk4LJ044oBD/YWkdMYuWAxtTCrFDbrHllKuBnpjqFfrtcflzeUBXU+bChn+8trSbqXJrO4N
jbJ0LWiX3Hcvdt9LASyB21V0QOT9vB3tP5qtHc+vbQs1l4ng6EScPKRe3aOaZ9TR9ReoFvOFXCTT
cUFp1I7v1/oeXDvTLuWdia0zRZHMMggDIhXl1x97RYv7DLZO3SbF6aiQstD9E2iArGh6nRZPel7w
oNYZXeKqaFhFbYMWt5vXI/OKMykes5CuHJQkqOp47gX/Py9IZzI/fp/37AavQb3vPlqO8aDIcyRl
y7lu1BK2Du5DOetmL0tOvZ563y+humsRukEXQkZwCiIRwkq/IjNBc7cmvGtF0lXCr7IiPpLszSSw
4yt0sR8ZUYDRZD4XIWGyyqUTLvpogPpOiWIyat3+ypa5XIwOHIYvswdNVFqR4xKfzOjfi6go3DRI
c0iq7heH7SdBxWUfU5pG5afyLy0+pi3aczZcgW7pTxzayQA4BsJufZi09KadmppH6ZRbb0Te+nsp
UEkAk1FwAkIvcwBy8slXhCCQsnuZ3Ete0dsG5jM8mKS7ta0mfttQR7ykdZ3o4BVFteuUedE5qcqH
kmIAeqaPDQNYofEHpmpHbYiwdvEvgBSFuFcNAqFBZjTJI7IYkhH/KrIB/W5gqtW03Xr1VobiGG7Y
6ykMv8Vg8O6yRw8PxWLvlM0StLMqjOrh/zOgX5KNiOmENbq17gNDVYiMIjmg+g2I17KN3GS/mImw
jYcZ2Z6RdMRm1Ma6sUGmo7+vH53OJZcmA+B0MVtn6Wxs0vXI2oswzl/tIeyvJnMMW9giH/YXsg5R
LYeZLFzSNg/PWbSPjqpmxp7OqM3GvlvAAH3HgolzaMSUA9QPc9mW3mobxBeCDJ4MXNzgcazYX7b4
umw9lXye2GSOIFe8g6SsxvxPOZI/PfYslYubYRR7ed8ouvZPkItM7PTyJRN1vhVrjLiHY095PMDp
4nz9GOfIgCjvkIX7Oaus2VJhY+fLdnjkO/lB4D1qfb4S3ckJjB11yz+gdVG4QtmKH/BCwVXz7lIU
rVB2A1J7dN/IoJseIETfWDVf0Roms1Qem3I24PKYpW0o6agNl7yEA5BBQnLxruEYBrjCy5FW5aAX
t2RQG0RKXTAnPIsi9bWVNS/ToexZyVqA+pS2dyjSyg0DAz0nQX+/PG/BnC3k8irjgcgiF08dDgiT
71FBkCsplJ/M+/MuNc6Tl+Qb99edJ5xfGPsRkZy/wWfMVRdRqqCJIE5buOvsQkKCwb55d5bsNVtg
3LM54j1EOiwluuJfRaELm07VZ1uTNhPD/U/Y2AJC0cV2zHXkw6Luex+KvvlU+c1UkfURUnajrMy3
QID8QDq4Rs3wkH0C/EkXvRzLfETSrWxGZ7kTCrFP1+bQ7tEXFF2Zqvb06J0W7lXuBaSz8QI5wx1w
vDml2bV35UR5o86brai/ipKPVy5xK6Jos9/adzNFXW9lg/b1xuj5xFOMv249KR2sEvy9uvRBMO3z
Ma0+t9vDBG5usqNeV9JvGxaMOk+/ufD3dkWLYKYsmc7Mdjuk/sOE8UX/AhLjOmvW5vpWBa/YEsrO
/DtCcdlsNHNuxLYJt65Mytqu5CgCIhlW9vKIw5VUSp2m6fA7RGFBh65ErlAdXF9ud0/Ta6iKXm4b
njlQhi0T/PcX+OpJcHIm4Zvl/4U7CclHbW05aus/ECiHwMCUvfGAhTzfJp7L84wfOJpIRVInxuMc
9cNoNQxJmrq1TcFi6EPPTCbKaclp2Sf9/tm62/gBP6D31MdxS+9j8pnM+EB83YwDaAuLO5YvR6as
0gLOgnNNy4oCAPlzAyb2QboLJdk2MRDuvlbA5nyBDCbIt3dTy4Zll00RFUO0Y8Uzt+ePfiuRPiV0
gVJ2nF7rBSYr3QUHXb9X8gb3hrcZqOTuHlERK7pXbdWnViND5md8TJNlngT5HS4r5QAO2yCdTW8s
U7gozN796oULNxVTzduS2UTXMt+L5Hfp8pDUjZlknwSAvuY5KBFjsuoRmh94D7LCxHXxjGI9Zqvk
EgK3aMRu1013ibzOC5IOy4drOS66313fs3Lo+dtzPgMnQ47lmLbnOYPEeTQSM0fpiAbf8jB8ZtrG
exEe9wlXRxlvtdg+Ny6K3XJQlJ+LOONVRlWsMEX8xRPchzUdfdu7M80vpGyn6vTACZjQnu9D5e0P
7W45/OOI6xP/L0NRfmm6K6fe1u8xS1b+ECj0crFNvkvTLbqYWn8DlwD5zuNyAHixbNPhAAHZNIE7
aa4f+Ym2BUDoP8CIVn7VxpUUaeGP7+r4kYQTSks+ETzn4AKJOEh8+GPSc0oCiYkRCOeQ+kvHrZqw
l3yhfONCQbv0yEHRGww6PGwv8SSv5LphRsLFZEeFkrKjqouUfVUVBBvwbGn+TnoPHnth4E0gI25R
mFphXIBBJkSFBR8UsKmzYkde8ak32yXf1afkOaf/sNELryFIqzp7OLTaKOb6+Q4D9bwxbZ5xfxAP
EGgyJW5V8E0EfqyzxAla8ikwFwPRa9iLDJ05lFmZuUHJiSc1EJ0qBYNmNF6CqLUdQjBBmWKIzpmj
TOvy86rRHh3JCcLwIlBXg7ZtyBVpK7JnBdi/0+8ymZvILDzVmla/NNa67actwg3YbgmNuiBq9Civ
2uPxR5MinPZ52PeMIGOkrKDzRm6CDHwUE2OoaF8YNJwvWFF0NFXSl9YmJox0aasZypNllR3JrCCc
DFYyT4PDwt9RGJC9NHSgqa9DTGqIcKg+ai4IR1vG0Eo/7sDCRkbcMRhDTDpxEqFZv/FD5iDKvmLK
uFhcHOXFXJUC4Hr+uSZC2ITcHi1+fEb7ECmUvI8bfydRzESdHy6UXMZfGPUdbSotYliwCEp2Maf6
TxfRVh4M+psIB9HXu8IV/35yUqqj3K67//oWuy9z6lif7+KW9qZ9hzDfbhF0hVjtPC8VdP+I4IMd
m88janztwO3Ofokn7ZUD/MbTHsPyqI0TBGTS9WmCw78MiC1sjGn1EkywNeFxKF0CTH4B/nIivfmJ
G6e867NOPaL4/gO7xYMdd8Hi7CTG7grmaDs9vitvHuYGvSFvpx2uwqws5VaIUikWUbob1fSxZQsZ
03NEB5sxHaePmb0uOip/yz1EDVlYfIek9xI3+RWR3arnqtI/kFvR4AHcPyjJtdFCeEkLEuCfu7MN
qH+fQUS1Lb3OyeiB9UdAhgacw/VcPDE+qnN/OI0dUIZwhEdu/NigIQtfdrWJ4xHyEPK+8qz1BkWX
Amk1tWvBh9rzoCETkS23s1YxaD+zd7gxvcYXPaBnNYu3g+Boh786cu8zQFQ930ET5ihYDZ1RXD2o
z9UjevFktC0ZT3iRh0B38VJLVINdu2sQi3SG+R4t2PkuQWkXm/0uRORHLgZDSKOslwwsmgpttq9s
RyBDSJ9R09qBZbCVlx5CrBVq/fpZqPRhYWsRdmsvgAlhX8yJ847mXgh0P+fQVywV0GmJYM2fe3Sv
N2GzMO+AYrlqQopIfoydkur1ZPQOimW/JUX3HY9Tvr6ApYOIx9tkKiJFyeJ3DNg3ocIlaVVGYMiK
8II0knmxuOnGk2AMkYgnvw/eahg4SCZk+h4NKseUM8IXarC0SdZIsHMoDz0wpUszBrUTMgczcTip
wAjGaVP6rpKDioRPPHMOuOwh6v0IQqkCBt5zqyhiuWcidX/KkeIxk84DjEWX3RPGmgbbvwro4G86
KAvN8EhwRd7zFe/o0aS/aClgXGa1kfvAO+3gyCgMwfzcXfarvGvmmqwziCyr8GND4AF2LKE0Q1nz
LyKsgLALLyzCcOvoa0J2JP3s29bEZcTZvPGD6w/NcFCTgVDJpmBbWKpIm2IhU0vzdBsGon9NPdq8
RouRR1h8lIzVUnz+Ev3gd/dVVYbvkk6iJuwF+AwnY/lA6l/IjP8GHq+aEUica+JANlvYYZEkMN/W
EoXavvUwSpEYw/4LaxJUtEmGbbKRtnLnXmbgRABPowjhaXYJGKYI+rgGjiSOWAFdX44/LDlXmQrW
m5HdZj9dDhKNwYZz0L5Oulu8Oz4151VFG5kMQHAtoCdU1UdO6d7i/9TKdh0jDDKorz4fWHpXwXA1
30tYu5Akqh4chOpL77L/K1uZTO8JRE1dC/uKPjJeb8DhXKV02jr1MbFD994haN6lnGBqHjiK14pK
1nqsUld9rbWfurophpHQgepd8OFPvdnlEuurIZnIIFunszshowH8wiwJ5tR9f1u2P4La0SPT6g2t
KrlE3CysXz17++54ZkA+/dpLNZc2VGqlKWrAWTgPlwcYr442m0yRciC/UBzvMT1/DNNarnq/ecHr
n0fahVu55qXuoC6DnpqgW6Un3PH+kmq3javNt6PMTYkv8tqrPthW9MzkRcjBHa5PaChBSprmKjJw
bXPdesjYr23d4/TtEaJubQK1IaJglkISFVXbfeyGi/TqF1XVrvfV2ltpeTBeTtUY+T0b4FkW6E5d
TgXlZGnIeIIL3YAlwg9zbxZvB9CEjGbG8ppMmYFiWaWdV2eWWTjUAFaKWHPadJ6gTIDb7IK7h9sc
Vev4qnM4w9Zt50nM1vI1+E8ymmjK0Uw8U4SX4/jbUxexBStjhw7Dy23UvNCQ8w+f8ZBCI+r7Iz+b
xbcGU05M5xtNcYC7U2DL0gdCmSZszQxOSzSUvwvtljMF7a7N13cql4pqDrDqGb9xNwfH88Q0iaAn
frI1etIf39d/LW7cn9ywanrffVp33PFz/4c4Z2RCrJ1xFDmK1MMfsG3Q70GNxR6L5ftQwVuFEww5
Ue4qzPE5FdFYz0xys7AXM1L7hvxkW6975moBMs5c4H5+pcCXaCZd1ECugr0qKWy3+dhexaq4M/6u
IfREjcDnd4GIBunzhilDmLp4P0FRa9jSqM4cbu/J6e+yvInubVcKTPtHAdaoXiqRZrorZQZfwMaL
HkJMLGzIk7pDIcRHWa4rFILN/641a1BmTJBw3neknxC95KY34oW17aLsMPB+VTWnspLk7c+qtX/C
bJI+32HJSUCWrXTLHLFuj7StKJZ/gSgtTxtauQNgI0VJil1glIxYCBRM2WwRMJnmr1IsEXbnWhfj
YRYnRhhBS+RxZV9ZKej994gShCRs2LpkpOuPL3TWPom7L0lpFYMLhIBjiMDLgN1+YGpFdwF+dhx1
mk1CkeSa3/kqcscondS5peZgToFa0hoEJbkO35aOl1J6W9d3+JAjM1uDVcGSZ+MlZ9nbgP6jFjF0
ele/rLEiV2/c4+WJBSAcFjNHUg5UtnPDcDb+NGJZLxhyC1BH0RtZbV2TRf1nl4p/KCkS/C5g+UKw
ptqq0Zd/Ahh5hdDXJrpP/xMmBUiWZI62F6PidOg1DAt9strCgux8ZDGke4bLvo2XxkBLduVy6TbP
4dnRVi1G3YmoCWyuF+l/0yvVFeTvZiJS1bOgV6A4ioG5MET21GOP3MJwdsqo28Q4iv5OerJ7lo2w
krfvpfAQTiaa0NdbzOVqUYBzr5uaINle2/3t0sMcjkFzaHxTqoZtQmr+k7NgOig7qx8NqPsn+6ho
WkuxM/WJ39cGoXQvvg16PObgokH6E0ybkWqVZZZtg8If3lOvNG9Gj2u12bsPNZGiMtQ5PI0VcziL
VLmfIFQshg50R4PmJtdBbwOUrLRCgDofWW1K826EiL3lnSKrsCvLSajDPIqMJf/zk6CMUclm8f9J
qlOWLzJNKiQX9gPknMnFEL2izBf8yq+Cq/7Uz8t+7d7drlSUOfDdF5OsyKExaFkv33C3ELMk+ett
CcwANEARRVvgO0tc++SPYZ7SMO46BCksZURINYlXza/x/jBJ49fq0jZJaG1AZRXOBvhvJJPMcVFA
4g7j6O5T+eeZ73dTICfQzLmAC8c1LGPJCOU1FVraOZBw44E7VgUb6/tlNYfdw4l52k5SR4jaCNZM
GScDQoWvlR58eQwIbITluUK4c9Pdeyu2dpNlDFGpDexVeWo3S5a2Y4Q0K9mqDi+BIJtORLnDHfc0
veOdycKDXtxZ9HBNh1mt24tm0KdLU8ytig4ZtBuSeoNsCRQtyqGIkHGx0EZJ6CCYYYvOSuHICsUw
4RcIzv44n0s6WLXxAHhi/t2kzbWVfO/OYQGVZax3XN/dHS5R8UM88HdqVQpttZ5NNCEdaDsfoPkH
p2Qeon9+WUzaVOFFp3V57yv3iCWf1Jz84BBoVaCqFDvs7voHFWlIZcphc4MeAl7qQJAKzZkC/Alo
7doIT/bE0L0W4u655DsCGbvl+KBqXwrKicA1SlUHIP1uVI1pPWraomuegqlsRaKd0lKfzOVOMlFO
qKW5mWSQIuFNTs+C1hyRiQr+uXl/u4EFt5SeNFuoSSBDP/RvIV34WGGNV7FQhEyYK7xxekiaI6XH
CTlCM14TcLhkQ3+z7QAOM07IukU3UTRMlX8nWeGaznGAtrrHPF8VoH4rbNjnEZuY+YM6ysOCytpF
HGAhQbDWO3pQcVI9HbMqM1fKpmNbXZdMfRuvU6+QS1PoPUJgRaES0Hl1nJZkIqO4PI0kLv/xxCgp
h/bRH6KjoZYgKkbbNC4nHnxjuMp5p/kWyOy/9z0L7LELXvh5ZVKuO/+i82Ii4dK1bHIePtkP3oe3
gy6pPFN4LBwTMr33JcRIUX8jJvi8D/749ngmliBH4ixyZIX60fxbDbGZbXaq4eViJHufTwfhOmdq
+nXewa0o6J70KFV8hT478+MjNxIuvp3TRW8PCF+UkiM8dyCRT7TwLRNrUDJAQkMfBZUOSzn4M2IV
S6JdBb9V5FEcXcjz/gUjjxejcWA9EOgaLSxMBQ5+fLuxKWuvC1ndQdvp6KQnFLUJvjH2Q8gQ28tR
hGH/pqeQku9WGWwfa9yfjG8IHozadFymqyaya1pM1h0JH1GceCkFxW78WCESEEebW0tXgG1ox4sY
IIIu3OLAR6A2XiFl578jbMR9kdxJOhVU4yJX2PMYPF5dbCdpIlztxyIbTLnVkk6ObnZLFgxOOA1k
kIKrXb6ejBCI8YZFQz072X6lN2Qc75GT3A5DRWa0xe8+8lvINELLFlnbJD1JMj/d3Ftdv1v/EQ6A
gJRm6t2Zo+Drj7sojQQMru1f+3B4vhc83ZD4t3d78tqjYnSaWRSBknIm8aPK/uD5+KlCgpZK5Jl2
1zueNW0/7M3kBf9qLGFJmDBg9vSZ7sDTaIFgX7kKtBNifN+/hlIjkZZ/e6NfXzo80cS8W7Mx0U0U
hp83e5ad8D+2u7gfw72/UUMycBAQ7Dm5Y52zjoKS5C9b3+VeUhC9+Kx8UeODBmih9iYnEYXemeFB
cP2QP3I8nycmb+zqXYqNvEqELL6vow6Y8ILeRyGmjFDp39hC1hZAXeF2lbm9fqZ5Su4Fvrtrl8DU
tfozagtM4/QYpFOikcvYYizisq+CN9w3OggJS7NNx0mUGtiNHGPEPMLNdNB6WFmPyW8X//SiQwqV
ceEYfytmBKx+Kl1WWydHXeZzP3l61kc1yG1exGzWKzjpZnHAyxxx3UijK6nMhNAUD3Ik3Mq5TLpN
vTcMsRQ5/cByIAaxoqOo7IJZiVBaIoIdkVjzUeze5UM9oW6GngfcMsrVD5jSQlc4cbjvIlHoN1y2
Ml/n1DkeiygtORWK8+bPzj/zUaIOkg94Rc1t6n50tnwZywZST0x82RHcmHubEMHF7GmiUrMNRpXB
7PwfIIaPSEpwBqXSlZJHdZzr5f+Lyc6JNveEtVAqR0sE8ELhI5Z1QAqIoGBzdPyavytFcJ43BfSi
njpBA4XYJwe+kbLaJA1UyU3sgQ0w+0ZRy8FWdfZ0pB+FXnHdW1hX0Ej5CzyLKFK1hoX+xgIcHm6H
JyO/2iladiFyZpTVMDkV90bcTX5RrTIHwNyaPijh9ZkVIGzeTyXmuGHpR9YGLiBtqJcjCic5xT2Y
EDZ4ngk/B4w8Pl6/uQ3wb9PiTi0UuLtYhOtqYPgPtSwjuEJQ+DhzN7oO5VQXz4jeA/YjbP/5PDwQ
M9IALFI1VXprQrNekqpy11MAm/Vqu0snR0FuD5Ambt0QHQYXkZu3vDJefrOZlB97Cw8MvwWT+cjQ
VpBNIxvgvbhp4FZL7HLa8ZaovHW1BOHU2yUYLVU4ivWxeKDg9aJwmJtSzV+6k51/DdpRlrHysFws
mh1CtgUgXTgT5+FSRCYzOVAEuRa6bQ3H4v1dm69nDDPwwLW+Ml5tZGypIOrhjD6Se1n5vGGGmCIs
TGmWUV/0Crbqw0k2HUGibcYBfSq+g/+7Xu2R7TNWRvYGGH+TQP3ByOIZRARBkT6onaBY5fogZLqn
8r94oR4w8LuA1z9kcOvvcZfdeC69ZXGJ6bpmCwoiWsUGjsg7I/QiKbTahdImrmqjrsR4hINQqy0Q
O1iKh7GNsv5ZwZCeCfhYaFr+OZxRYMvrCMD1/dBHA1msrIZ3YeoaNR+Con5pl9/mN+07l5w4NGnN
kw5B0dVkuAhZzun1sAnpaeAZkdKjdblfmzVv7lWH0m8yXdEFKSFr5IQom32MN/PXMahKlfpBeoOY
McjGBgxzUVVDOaiXBNe4zxp16aOmy8MLN6T2Y0LGzG1G0fmQgK/uBwt3VV1vVWF/9LrqdOSdxcZd
ksbneWq3RavTFoAv/USjMzZFs/khcuQIT/fYdPQ18TKB5Gh+OIGZ8Y8CFJ8CXMP5N4BZnyuKO4Fh
GWPIE34fHldnhUeU5nNYFs5VgUeOSJ0cuF/kKUfUvjyyzFh9qMEp76/GoYZQkMiO+j78yzXPDwsy
7/QbV5wj0TRr9z0Q7jp9mqQYTcl+yIottSENwwdz3p8E2AwHeO/vz8tO1aYXgbroPy58h7Kkpxh/
SqcKZRyJ7x1dJJP49BryWCvpnQbWYHBnJMfWJRyoYjO0oH0yaj8tt2B/NLxMvQObu32hhE3wC2yA
UZdB8T0uYMlXEQjS7F672iHKDlxxveCChIb7oEPOToDNGaiF+2oPwJcWL7e9Zm11f6t9S25Xtyu8
NGNmcAjRwB9u5STLkXJfNVMG39q0GeNZA5Hal9mQw45h609Eti5+UpRSPcJ9bsX6d3zbD8orURo5
OUVXaOoEW51t1HpwWlUdDkGOs6HOXFAdI9Liy/vhgmrejWD2z0SphEEyO/JK0IwBpHyYLEJ1zwYw
SSDP0nwwM4ajbufKfNG6qqxyB4ikW5uYx8HG79j1i86NR357xm4JA2RUQcMrYZJHyLbzA2llM5Q5
BXdVjaVYgfnan2Lesek4eMiqVQrNDCUYCiWH7a8Zj/SpYQHa0YNLAmMqUj8Lk3n2/6m8dxQS1j72
q7HxBb7ZJuq4vXwvZN5HTnZgC0Oc/MIJfmd/7C1aGvLn7mtR2JdiKMXOz4h1jWEBv0lnDGjgXnQ4
SBzQglYdY72quEFBC2TtBS9j63Ca7NfNKSRuUF625b2YGdEK9cw6YmN1f0uLNBSS8vzhhlL6xNrq
3CiFsMR58a8OZ4/rlHTfe1L9KfZcFzGTKE0htMp07cpKg9DIFBxAuqDPJ4mGsvu3o/JFH+GpDqOo
7OaKrJaGSV2J8vL7x39PxVyCpoSvdPpldIK1M6digMjWp4RHWvnYQIkSkTjmuT0SgfRB0NC0baq0
Mz0N6eccrr2vjeJGPcQj8U+CWDAzik437p1yNm3OZqryjGLta7dPK/fWjDVsw9uqx6+xzU9GBB2L
pdHtA7NS/8jYEoFikvdrapAVtgBpHmOzFID2G15bhnWMa/UcksEo5Img1En4vKxhBRkzRZQfXQGC
h7SWRNE10PXLmmLyRX6yRiPvOBW8NDOSGqWPYVnsVV7n8pJGgwc2+bJZPMPHG9uBMy7e+ld1YHtm
xvS7By+Z/xXq5VTtFqxH2knZbzILpSzRH+P0qZJgmyfrt3m86QjRU67kIw/Sn+8u37PwuNNwGLjm
lOgx9noUXPe3k2WNcarCkHPjKSfyqy/NX1cL3jWAtMSVqGWqsu/50CT9ApekgItseko7KgLQIKam
IwAyV/yF1oGKJ87qdVlXkor0LZkxnfe6TNL8ad5c78jOP0+hXEeYNQSjPU4bW94AT12Hju7RfnX0
CCu6tTcsxXCFZ8YmuD36Gzxrp/wa5yXZOvgLTEEsRiwKqqLJ7KHoROLNF4xFHNbtIhzdIwxDcIYc
Z9stPGUpiJxespVrxE2dd8s3IPNqyBsTuMsgG/SRebWrxHTr9WNC2+MbI+rwEK68nWxlwZ87Bj2A
okKZzQ3rd8H5BoXyMTXYEmAu0y2N7HlPKDHj6zeAaJytybCNBg8MiY36IuehZaSTTIvX8eM1YQ+N
pf3StI49hsWYDCxpHOi4bthxFqpvuPQd3JWiaf14l7Z7CCnxQGdzv3eSCpvU/C5gY/fymNd9EPUg
o49kq1FbBK1CHxvOxxIkZH6vVU84Bete8XaTuNnQJoNS3Fic5y+GKLIaux/PeOSZqumptOqIoYTF
Z1Snv+fAFBaseNPYZfgesbbUOZiSYZa0PaDg3hPjMzfi+H3eMXUY1i4jxJb8sBxEgBNbVwYHJp9e
E/JKv4YLP69IjOj7PWcoZKX20qlDJ3hf5OPoSKsTntJl46aAnf9utqLczGacrG7AfbscA4OpUnlk
5TQR9qS3eJigRFE1aAeRHpq1x1p0HJipqytdDZNAvTCynNxSDBl9Mm2huDOvHD4KB89CM5UD9yEX
z287yOJI671HWxmHhM5LuFco6zxYzalDJMgv1LNl5b65j4PwDOuu7snJFlHQ+4luhs7tOjH8ie4n
HGB3PbOsWm4miTKcy80LFJ6Gk4BdN0MidvT7KBzNHcCvQpHaLB0961XUae1Om9T4tOPX/LkRirE3
khB1OQ8isfeeIR368zP77UomwabGbhiYb4m6JOTd/jEAuyZWcXMywPzr0fjrbBj1XuhMKNfogy/O
SYu7GJwne7mavaPx9P2fHfOhgN/FlHyDLb7OSX6r32j93wRHYplGeCm8n0y6+q4BIKplFEM38WBs
yvSdkme/Y+X3L+PemYpV44EqZ4xY5XZiegnw7ofkhDXYzA+h+9oNMLpaToJKbZU7kBl3Kz1RMLU5
+jtGC/4R2rNaSuqT6RHiz+zktyC1SYwe0o/Hk36TqPjKeXRwwDTYQmF2vcDBg1ou6jZ/lMlUreIt
d3C/Qqc5XGhRMqTpP3uOAo5HqdTJyXT2o+X+e9jPhmRcaBQkZ25mZ6EkHKb94UorvcUBFpdIbOzf
W/mZ4zyw35y4PgMm57cElk6V/SHPw/s/OvnlCESRSSrCza0epJF1IT1bhp8lUpA1o8x3rdvVfxW1
f63/TwD4ShuYymreeXk1TwuPdLx5TPdgxxUSimwJsgsfLAKtIyk311R+4MB5JxQeUnGP/HyPBJ+F
nMRktN+SvvH49PNryKUbvsGxP1d05uuWdJBXsrmiyCmnSeTxz5vRIuLGTDq/dyFP6WjeuHDponX/
wQy7VyhD6/L2DJrMTflDVI8J0TUH+XtcKPHnkoPmR3P84SGNc9R+UYhhtIGkuXaDlT4YYvy5D/LJ
bWPg8qjrpHgHZOlbUlvxdP1fAQ6DJr+WeDe2+uf8TYXhaoW93dQwJe86HkFvBvF0MFHY9qtiLd0R
jkUaIKHx5zbdp1xwMccKCYbQn7cvGOHn/wGKCsCDVlFg9Ec+layKU0GDOvo7JSq+Em3fcNObY9nj
MNCfsMilkJkS1BrMxYSveughrSiy2mBtSHeWN/TRb2CiU/9GamoL5qg2bJ3zIWkFAeUUQ+CoEI4y
TLRcAKESkVAl6z2TU5QF2tg2o72a0Jn9jGVD4WKyTjfZ9BZmooXpMG5WlXYJw2HO58W4jTx6sZ4n
6Jm0D4GuhhLH5wH9/mS2LZLtKI6zje7TT0b7WpYWILvoc7IFkwNMPOhSy767eGOdkNAXtZhndO8n
EW9kfPF6RSX22tqTMy6zqvmUhrc6lZDxzZkD0rgy8cbFIPnTOkHcLxow2l+cFJJMCujpmihPSlWU
+hwDfGnv+ZOX+5nYQ0VOKZTvaN3BxIXyPzGeNxDrmRS9WrHAc3MLnWWMNjsfdH5TCexIblPHOeh+
dmAEzfwmNaVpuc2b59SJwoEmo8S0KVV1gbGBmIMthA/l7FIuVtYBSaj7XchUS1c7kOCwjgQwZjJF
q5KP91OaxT0wfDaZugm4OqWN9Qhq5Ap8nuSq/YTHOFt34m1+X+56vnjUI6KmMokzq4iZNTv7ql5r
UpCVGvdm1BHWnFUjgYl8VgzEjaWmBXhdq4sQUlviv+fPpiSo9/FaxqimJgxtM8AOtjytK7l/cNSC
ZcQowpjhx0JW57OQ94eFkLUHyrKkzx5Uw2o0rUxKS0WfDrjl+A3Xc1BZxAGzbYNnjEW6AVuV3MkH
LgtAJKAX3pc3pwIE3BP/DDOg7gr/cotOPbi6e8rcnlEk4oJFXxQ/jbyMHN0FBuUdOpb/GY9Q/fAR
eTcLmJbU7PBhOEA39Lx6QGEMQ3ET3jKg64hkDa4psrKK8EO00dackKX2odDst5gtZ5YjDQ/UDYHs
Wsuh5siYQxxMSTfXqDzVK5xBJq3CBAP24Z/iY+GiWkTt9AgHfnj5Mv4EYSUfT+hXxIBNbXJY1oD9
kP1UBnDbhedK+iStsr0PPbhN+oCmjxB6b6VIlscmMCCQ8ayQnkFSythbIjALo5LQIDrSCisz/5Aa
ZnvHprxJmB+t3EBRgJFmZPyzLMGYnYSbyzMxQXtI3vgUf8MID9Ql8VM5crIZpOPg42q9bzDO4PuM
yU85vjeZimfL8KMA41U6GeGmoJJunqpaHEHcyI6qh7h/kOphNrrtqR2Uz8d2GsOsaqSafSI44cZ5
O5ZzG3QoharkuxYEfs8ZCZ/TLUEnhI9gwnXTcR4VZPykjQUk0BVcnTRm7t1ekSozmT+Rycrs8bke
fhcebMbafeLnPLZgy8PqPYYZRJhFLV8r5XoaLQr8hbIYbwF5chTJ/Xuu1i0S77wwP49+TRVYiw+e
4YBE5oRpEfbrehme/FN1KbMTf5VlBkUrKrWuMQP0VCs/RKDJYntjcwAnjG8IrlLbfmugDnfg/EIx
IpEdrWO5uCYDfz2VVYLJ+UKc+L6yHtCZOK1bMgeUm6ZnSlFUVkxBuq7ZUIkBl6KuEAatQE/kkZ3I
2JyiQuLYoj/jcrG6jlK/E17V0eUQzWgqYlXegycj2jWVQm52f3VYc+rBDRoPj0hpWP+98bHAXtye
CFnPzlPkeIh4dnSwyqjRgi0WqrKhFCKg28dijknT+YWpJ96Cr9LwMYXUISoAPRi4gwtbg48HxyBy
inTDPK1WhhyNwxdtKv4KQJBRF3q9Gy7JaD8nV/IOKLQtDXe2GaGM1pVkIBW2SbSYAxZRB8f6tXks
6KcH1inFuwTzRkcnR4qQoNEeTYJvvUQK5vEFDVcZTJudfkZyhQpqbfzgmjY+ZNSW+yNEp2hQrESu
h8Nd1HeclCuNsVqsJlmSZopXK7zRf9kYuweaZtIx8rKDQ3E/lyvk20i66YgogvQ9SVl3Yw0bS+FH
75pu4A8UYvFObn/EAzVpuFrddrsXiuC+rVRJ0cI+R7bK67UsNean8lvAPKUuiPzeIwWL4sOY/Oht
CS7+5Kck4k24lhA9iQ8czMTJVwgTH3AVBRr/rzSxxAIM4DJ5A6bnosfjXWF4TLx0lVlvVjnPEHLB
eomcgLA4ILUrcFO9KHh9Iet+O9uZ7Dt/YkSZQymdp0JskrRgGrQFhQoeRmz8f2lH8Bs1iA+HIKTk
iDju96smb7cZJ0cOx+jy1w2R+nDetiW65+9fSFk0nbtIXZsSlR5vvdsNGi9ENVserxYJUJztyE05
bgDdFGkbaTmCNT6DRYCYLAkMhSNn0kS6GR8aA7MDeuBztXqcNHS9QqcYvj/I0kqnEpZPGqPE1AMO
8iFI4zLOWzYFIksSeaRgzKN9UeqdUFccbqyL0B9sYXLDz9mDMha9+z5vEG2AsM1myl+CVETrGOL2
IIVsxLBPJY40RAtjnFY5DBNr8gOMApsxZ2YOvGd1rgwWfo3e5cRqQSlxb74M3anFm8VEf5dzcpct
AFO0ib0gUGcJmCnt6etKGjxkJ+6n98uNd7MipKmKq9iM6KNT54zBYewaTjpU8TBaU96DfnX7ajdM
xHrC3dMSNll4IJhMxE+qBtA6PMbkqVoQjKmS4GWB1lWIRfqCyK6XVEJU8zk6brkn0q8Z4UlWmmYz
CgWJEOWCWI+Tyt/3IUGG3/adCWskEr+ZQVCKhqGaRIPuu/3lFYj1/UgWdhM8xt9BUSbrkJ/is8iE
DMhX3uDCNYHcDKoH6YBOBp0He/Vr+PVrRoERopRRNkR/gKi+eXkNsimwSN3/OuEJlDlgY3PKT3ay
FNaELToznfP22DlKBP3ghxCyUMa+drUmAOhj6Bb24xDDaMGpx3iJ2uwq3JrnlDo95i3XHTqmlbAi
1GzXBIXrkra0PDe1VQzlnjpcZUKYkXptP++fI4ftuuo+Ek2FKn7D8ypuVlEdzt1V7zuwnEFSBubJ
aKb/UYF95MzKS2mB2O0iV+WT63MxAouJHYOSaewswWZ2RKd/poY1Z97aJ2SNOcT/JzDnWTFky2AZ
nxBi72wrPR+7mOTXawf/+3F82/dA3VfVWElM9426FiOrY8JA4DIOTgybG38zsgeBzwWhHQIWULMg
grmUZT1y0NJP6Ptoe/5E10mCEdLDkb2lgzUseesDQqTAtPgpEj8mXPHHY1b4KfgpdcmRnvkm3RA8
pm7dikjgRmhTWSV+ExfpsUAXEQ5/mqwC7O8nPVa7BJb4aDqPcocaoJPEiPh2/OLJ9ZpJBbNFX8mS
A/Rzd+7YeZMf2qCn8ovyJMdAmoLSAeKEr/TO+VgkMMjQmg6REoTirCsqQA+PevzUavZdcDSKR1C1
SgHUjD021grhWFDqNMpiarn/AfEQJM1wthIMwJcODRzc7pw2pHREO6br9VNUWSZzUGPQ0qnOitn7
Vk9KtaxevwWTWo0Mnwh869zXHvLd3K6FctmqpHbOG/1aeWrXqBJlRWtLLYXd3crJpfI/QULBKsSJ
8W+BZGuFpM/+TILZSfNTm3Weuv1G0JNlukQ7QHR8d30E5sFYhgxaxb+C3lnL3M6BghHToQRvuKBD
GgrgevBchkcBi87GUMqhl7WranNZV/R7klHtzW5n5Kh90uom42kAjmVukuQI9+wSAZglQkV7CPK9
J0Yz9/+qOIrJ3GQPwy3LqdQMBj44BaElY6iQ4NqxeAfGPjW8o30RpoI+REhetqQ08qmrqRhwgSRd
L6JApAbQOnt5C6FFhCk3oR0ePE3O7jSJCNukTpVz4OsXzzmMFZbp9oI83yTfCAiPuL7RCv5P00UT
sasl1uDiYKKVzf1TCNrl32UBgQp1Sqx2ki9bDVPzB8rzWD3o7a3vrAkut1eRcldbYLSMi/Nq3uWt
AORnWNkJ8kWff2anq57tSsiFKdYhnZKjpLk9oazlFjvYhw37ksUb2Mso0RtMbLd9I+HxVKqov+ah
dH04+8XQb1UKgiD+v+s2YtQ0SvztD/SCt5nPNp/qMcqPb4pPOMweDSzD+IrJtFMlIWyncr0LI8Cg
xu1MYq+b2RgxPQuTu4bsWgv3m+rjY+G7dm9tZZ4U6KmD0HStewYbCVx30moT9qQzVAYkShmEzFxs
x7diwQ4apKsSqmmpvSO6wiNdKhtE0Xz+um27YGjvh9IzvkRul0i42ZatpAT1sW9LAPBQYaPhM2A0
4dRVSgKCLIup9CUkaGoNTTtvTObjwef9/K+aqYJvsCk7Yrw04hlA+k5gbYVIUIzXpV9YyrwWigFn
VkvxMN9ip7evTIKmXuBoRYROm+Tk5EhYx5tJRPBDg7YGrB5sYmO6U/v8LimDFcssIYpRUsj1i+nM
FsIgHhUWMx/jNdZOtr46eH/CoUMRPsVtB1ZFXs/4/ubxkbZhOpZeZRPVN/Z877lUXvkUihir9Py+
ufdfE3d+05xVlzjaO3N9rqgN5wNRML7Na9uyxRSgLqO8z7q8mIpqXkfcQBxgPfU3MWYa16TgG992
46BELmG1nmrrogwwvwb1gc2coB1+AWPo6gpf7/i4l0fSvdjyHD59O63xk/fqihZtLnOaM+j3g8cw
T53zo9+mYMVxitesYAhttNWThRYbIcjR7NDxvbC4RJ+nTJtw61xcLAJDtsTZFi9AdJtXIHnssqLP
8ilWHsL69XjssBfMSrC4Rn0aXg1OP8lh/lhlfsvtB82ybRdE6pXHbDbphNd0HHnUt8Y/zWw7tQv4
htUZZYdVUpgxsS2/c8xItmKP06GNU63FqFfkeCc6WGhJ5cqQPsBhFIkmzRxsX538QTnZKHJAhorq
7gbi31FRK4qgTWSluE0ixKBY194SbPV2Cu+kVViXF9c1UhYAMahdtBdLYRdf2M2OXntFpmIMF7NO
LA2IeUonEexq/M1obqcPMJrbfppAp9LL4yvT+G6DrycA7ts3VA4pU1dYDj4sH+myZ5/CoipuvLhL
3fmuNII3gse+yuCgC/EbKaipV/d6MqUQVg/WLz3zJ9utNwNTFFd0RdjrSO3H1kYhgDPUVPZ3ZsYJ
sKcPnpFK23rhRVqeZu0XcPPQsJoBZrqEN1ikSMUUeqMOwyWDWMFEHyyuEbHYPamHuGhMaAVDX0j2
Pk/y9udX3lvCwUp1A5TbpS8PeV86cn37vTWqad0tcCY2y0Qj0A9OA4m+mCghhcOEhuTJOmZE6fXL
rC5qigaxwwDR1N9R6VwPceJMoX3W0KTWPqEesmasz2gxK37DU9qzqNkpB/GyAd12STxb7wJLbWo3
ueOQ0PhgqFD/Veu/wdQMYPYo1iBPM0Z2Gh+kRwujZWFvPWO934UdsWbU3PErTNC8DvW4qPQ+eWKZ
WvoNaGjoCmjuHkWyUFf18IlQm1SJKiy1gEWDuxkvmfiUBGnNJOvBv0Yy4kl2o/228uppDm/AXbHu
Zqzh0vvyM2ivifC0T580uAEDkq7bfvVpOS/2PwIinqxxnzyJXr00capU4Ig7pg7cgIj+WaJ+fZoa
OrbOEJP5MrXHfniDJzEXyJ/nkO/fSpcqwPxHdvvqOoz/EjxE6Z6y0DbA2N+K/rnbu+yJ6m2FmzyY
AvtGtyVmmTTIRgAm/PdpzHTtYEMUZ03bnlVAef2p0XKV232XfO3SWNd8b0qpgQb2xiBAa6XDXhuK
RsrStofY/xf7uE7m2I0c9968h03VQWzHdu5dvWuXbMam0gXYbVAp001RBnEIAeTP6ZlgrWoQGJmG
9pTBcznGloECt2a1q0xRAsDjKswb7npgqar6lqVSYHhg0iTOuhmRplJ872GdjdE5wzxYS9egNtja
WOKZIjZ8n2kPzBQ0/0zgPeZSC0iH6AwLoLONYCqRP6NKkTXGUStIWvxDDQDqb5qTfQVWKq6+VoKL
pNn7BmfKAfvhmA5jTSeBdvJmGTqi5XkWqHLV9hSvDdqD8hcfZIFGIA4zb3FISC+r7IQRExGqFNq3
KQMX/GYHXO+yGYHyzSlgp86nbKlJBO4D5P60JLmLLb1jX/u4mNbT9DEUTrvRYzQtbeFuD5UWJxWN
BSernkWt6N/WvWpebO8hc32BVTl3sQqyw9TG63hQxQAD7Txb8DP6tYzx2xcBTXohrdFwphYeiudm
8PvsrH4mJjIBaZR6SWwli8JfwT4vT+rGixrxaf65nkheQ1Gf/ARz39ykg63imeCrr92l52FnbZLR
dw3l08fb25xHPVZj/s911DU4ZZ7P5td4XEVN3kqmjAQq7Wlz8v+cvwJdgRFnJU6KCUW5c3QOZJuX
8ddK4xmA6a1EZjnIiL9pBHKG8Bar95VT94HnZdW7CsWOlThFoWVrOMnGuZYQ0x65Dmy6ECyxnpaY
EmAU8YPidUIDloBS+8F5Fu4g9defUo6UV22rknFOj58YMD4S2T6VU98yMfRmBcrBrUw+HVJ1APJ+
9dOZQWKc5ThgHGOCp6aFJgfQE9KhMnrpiN+wbVhMt9thauqOW+vZuEQjm0VEqfXF+WLGSmXkOfoW
C0AGTXhQPXYderyLdAE6d7NNJiFNonFzpRzU/5dEDxb4Zw9lzE5fpRO/flkqZChuS04QY+dWVqSx
m0x7qOcZmFM0uxg0K2cLxGT/OkJBj97FXFqUrGyQFXQF+A3dkcyknwy+WRfLIe3mmP4NBpQKsK0M
2AvUWXE/Ryj2JaSXrXZ/YZ9lh93hi55P31NJjzbRoCQs5qLlWTrT09W7hKIcdqYui1tpv41QTM0d
KVu+FauiS7/MhGCuQoTiEF36GIWtGDG+6oJHfGKJLHkTPa0zavmTbm+3Rly0fgWiwRjqLPv9uBuc
4DfztYa9WeXvIoXKt7baeuhhMEe3be1ttb1RR179slcUjP/7oyb79TD1/kYr29lgGblw7kwhS8FZ
hKWmTrNsLk1IpXe2i+S/dOA+G72LI6h7RzCoAiknZ0OkHruB+57gOwv0pLxiIUuWCFHe2oaqK32i
B6ZwkUmFzajm1uZBulr9jBVQ9/Ez+/hINzCbbKo5bEc35zW0cvbJKNeAjUfXNM4gIWGGsXZ8SV3Y
GiKp+KQKzARlI17shLy8CdZSrk8bSM2P0jmnYH+Mk3vb7C2KsgWuy3OvdKZ5pETcQW5iFXuWyY57
jZu7uNJ3JTzV4gSKGFIaKwmto6JU4PG18XpWZIaZX1zkNwrNg2yEAgvwhSrwlTY50b9d/OSXvwcg
ez/PNNv1OgupJUR1QTy8+x/RbDDimlXlpDsKa03yhlfi9+sEYErpH2QB7olQsr0CZOydxeCDQP5j
+WVrT9ZCF/yeTKYYF9QnOnGx/gR7/3BITy2urGLFJJI+ObMKRTIf+VmHT306ohHxixEmCHOrvt0b
Pu9AwkPxgcON6iI5BxMlw9euEV9uukQRjI5qcenY++K7cRUJeeFlZpEh1fbFmHLVN4ka52uDaomA
265kjABTKA/Sr2ceu0FXE4eBWN63Z/h1qyUDszWcaBngeJp9HDYqxjHabtBEmvnUn7+wAVqpoF7U
RTRTtEMWvwBUuTaFNUKgJNAbqWVj6iTec3W2818np7LMhvzApH8pNyVaUzXnrOkQzgzJKq9uF6qS
RDxcRD1Af3ok2ZSAoIjzRVFEaV/D9JJYGS8npep8Fhl6EMkVm12b695LrUK4MBJ90RxuOxMVuXBs
bNIBP4tEuk0DzP9SedIXsD0H8ojOXRt5dK/5ouJamHt1PZKE0fnAppgftVoY3fn1OwK/xHRhDEMQ
AkldBgFt0oXqCPzim9FEjD21Jfr1OmfuTccwpK3puI+hTbZp5h28/ycRa9hmuxXAmo7KLXID/Bx/
eja4sGkMCanSpdXzgXrhKUZlImewix3uHw7Crt4DsJdZMEEUwQGR+tn6Dzs/RHInDd4b6TUxCGFc
IFf9s5VWNHENb9kyAI1U4o+PLr+f+Oo8+8+91D5wEcoh2xvGYYZn5GAzcLeS82GZDYBGJxrAWAFg
8GNoLamY0XwdVPoDVe3/OlH2w95ZMeOgad/8lTFI9zEDq7VjnIZPt6ULoi1OVg2GvBG9PL/GFemv
86/+k1NlD1FhRg0cpeNw4iKjNMiZbiD61dIZK/eJB/JD9kHvI1HFIg/Y66pl54gkCjyf/fUHSIhz
vE36qVGfYkdcFITIRPSaXTlvPus7Pz72/56qqbKMjGiPplaLKQQEzpDzr5Cmdm2gEWF7EsXxtnJu
Ewler9Y+NRWUEbWDWeWr6ULxB0kbCEYGBWbNG6+Rhvmok/vB4Eg8xUU5+QaR5saFtF080OtGDVH3
j45USRIOmO9B3CtmQIw/oNex8iXJ6qFXzTpCftDGrD6juvCyMW4BQTEyWGhRg3M/O6HRHIrVHC8k
ppMKhympQyWVxsQ6SCx6/RfenjdFhXtjaCvDB/W4C2vJn2qsV4JAmVdSZmd0lfJdf9cqgrmv2OcI
CdIH91nAHXzg+SBMlRvpb1qJNY8eIYZeXnUZQ6YBcApBD6MqQpPrvLxATAD90DYbZQa2SfNkVZdY
7/am5U1rp9A5D03pSfsGhDeiUaa7Oe71szs80MCQXjoFEz/m9D78m+AbWjLO69WWee0P8/JdVusd
zp+1Z4iaJbX17dOtP0vcF9f7mzZkQvoPEUVgnbYwz35hmkMb0Q8YIyU3QfpoC2a09DUIbQCp2IQB
DdMq57Knv+Ane5B7/HMsoq8JVjw4S/yGC2sk6iF+YRCV37+6llXHebMdO0icBdL6QcpnGwKUstPh
7+Z3mbcpChLhaJBr3V+11+sDO8KFjI4sYjBpet3+uBlRmlXTexOTcnaUmFbfeJfGHl2vAE4x36HO
wk2esIyiNaGvkMHvFTZMfnrT5iXDvVE7PhrCRcdDcrbgY4fXdx42Wh+0/T198TzX4Jyb5d8oiTMT
vDgp30l9PNi9DLLsoEd54OLv8vtMU7hr8PmE/aVEqaZSvxtnhiScY2lKKgT5kR56UDgTXH7s+/PR
a3wZXTCfCAQizVo0KCnzqlBDs4y7o91PgIutMXgL27pa6/LbHE3a/YJU9DZs1hcxuTytjPg1cqMW
9JWCc4VaFlwKYuWagM6jEUzFtNai33ZsGJ/gQEYxdQdYL+YjcD/WAECOSRzvx8E6xQEhhxSn2/9h
UFZHp547HW/DO/PcCpmVzna1nmhNX1xwz6J55u4hgTiylxMCRHWT2htIvcXfqeEQb/iVYhggCP+S
evdEWcygopDoUfyygjWZTbSQg5KY/JQoRfnR4IuUxy6Lm4hlcl2kP4+6nIWjCIBoC2xvh4zoTnp5
5Qh5fUcXK0OegW8DBhO3ZeaKZS2qXi0cZBh/bfGYqX/mLsMlAHVLAX3wNd+9B2TUXDVKRQKPUj9i
Bk0QH181EfqPmhuhkBXbURZZWPMZQBcLAKEy4+MlVdZoltkgL6EvAqC59K973mHT5jyYILT8GHhy
dOzN8sgUBx3jaT2CbRVxGQDar2lQ5TvOJybcixx2z+284XhJhTVkuPQZcMckFjrHf609mD4JGxzU
qxjrd6gtA3Uv56YFb7j2F/wBQEXt+q3BIMaWrS39rbYQbxguEY15umWJZKZuKpSs1T32zu7vlK9O
3oyEt0SyXg7yU8U1gAKD2hDRRlYtWM6iX5H7d1wlNt8YXk+KCVJ41ICrcuD5qjdeQhjZX7sVFyTh
VIRLAMOYq4WHrc8AEb6y3B2GbIaf5xgX3LjO0O2VllOOoNUJjlU2GLhxS6ifiOqA8+OQnYrp2jv0
1IBVlJAk48WrMZ6+zC8b8QWozfxBeQPZSrLAZeaXFPMa5uFmp2Q7YjSbfvu9b8BNiEhq8WkhWMQp
aBsVzDd7gARkFeRTzbEnzbcQkHzelgxhSAOp+7avIlUF5ds2xkM2OXiLU4J9J2r8rqXuiUR6hwje
9gG5pt6+kTxjZzAUlBWic3i6FZtT0i6Xa/aE896RNGK9C1SUQAj3Ohtw/2k4whEZ3Vd1Y8bBCBIQ
Srfx1YkTFp8OwIzPois9I+6q7uCeIWQmZ3HsfOpdKKbAJ4yrC3s4DH7mvIkge5D165Fr5My0SY6A
s5V3ApwZM1TSJipt0PiFJY90L2koi+RKtgt6OL24ERyEIl9nghFUexzyWY3rINYVMy77gXV6CXGg
Vvw2SqoZptovx0BXMoNf4LxZxeO0+iw7KTMSoss5CmNBd9DzatxiRC9ITyqXDDTXzWXjQshvFBLJ
krGksVsxRht0mxX7Rva8cKREH/eiOmr00tNhL90Q/M24lkTLJTNEv1kIHwbeFCQfk0VDptA+ess5
4Et+CGlP50C7IYGcStqEeXJxRQbASuSKDl8YmbTEgh5ZEeY5Y8/5Fjx0g+pY/T/OZqiFchOLuDlF
6evrXa9pygLlqHGarD1s+ihyYRPeek1raPejzcf3uRs/AdYdV97UJPjEeCUGTQsdFcQigyvbs0y9
GPhJTV+uo7Cdko22t0tvXJnMwgBycEi36FI5tm1CFORewIYyAAa+LEPnHWoJCejPJpzMFfRYeYC/
TJfgqMxmrgbaqaK7tYOoDPqr9qtFZ2i3amNmoMhiOAe5WWzh6n9rLS5OwF7ZPGmIxJ0aPFxuo9e0
F1Elom1tGmGCNxniCFITmwd/QG3/3wn55/sfTuI7VbzC/gUPvQSZ2WAbCNddTGly9degw+XtG4lx
G02nHH3DM+ew8DwJjWL3OO4kq2yJolifOMAU7LjY5I/U3lPjs0yjNNVC+mQd8ieXTvJno+27VBrA
04DgRVnk7KtBYYc2mPXz1UKj+wFCS3y7NqK84RCXNcHFzOFLopeioMZ0qeuim4awXMtFWWO2YMPG
gUNKX7CjQGxdJnFQVzHYmoH17MCaDzPRGxvNpX4Fn+JNp7Qfrt7AH86MdW1H2mhwwn2UdIzT75kR
TRXcKiptD2N0QkwFjmEePO58363qpCIFg1Fv21b6k2xxVvRKcg23qZeyvLJ0quHBEFDbvly/QBOo
eTu1lahKwWmSEOGyycM+4pk9ssdYpKeHFHvetOy4soDRxliEuCSgPDQC8Q2OOiDt2cw2sJ0fQuOY
4FdTplG8ytUBACaZQkqbvRHm5PGzuiPZPZ2kc9yy8qyYZSmOGm3KpZoVx2k/nvWRoRJBO1c/Smd0
Mxmi5u2GZPqg4Icl1DbiUotcxYJVIwSERexgbtzxIWVVtwLFVf8K+QMJumWyzZXcDntioZXnYbAH
5Uy/b17sOiS6uuJtwSqIDDZKtw1yxfau4IgC8PkG19RMS+3u3gFq9CfXxVcLFSitSocqr7SQHetI
0pALcW64EOL9OLsg6PSsEuSfEPp3qaQXc/NntH/beBfQSyMOMSJfGh7PRpGLJq6X7RGQ7C7BvKnr
N4C39nigoS1n1Sth7co8Hx7dZQAkZWHzZ6PAwrbyY1aJLx/rbcLco1UsLT2j+fRP+mUQZfKBdpz0
ZCZabaPeA//E7Ht3wU877p505wIR1VI/S87MwkI6j+zZXxbT6/pjVI22R2OL2l8ys8Pmi8CJGj+n
VhBTs8D3v07eeV6f59cGKNB9+e0uCuELdX0YVnqg2rdje0zTKVXLWBruRujZaDaf3TZfGgSITiRu
ClIeJMyCIo/LS5wpjpbdZPDKxGyNPFVLcJYRjhrz331cY3D/+1Mu/YpriwgKS8dhFxak8tEk32ZK
VpD7dt4qU7SIiwMlzk8lYU7CGHOVXwsdJVqLXmaCF7Eb+N53w29J7smto8IKsuW3f6SVBILZjdhm
uFLI/dyqACsYcezsfDobOG8yS+vjnkCkXkQmwRDfIbwXaNz0vmBXHtMXl7C5vIdS0HP3bzoYxUS/
A/69ozUKuYqU6Nesd1ZCeCU7W/gNZhRtTyZJokOeDGbpdsXqCf31sFpvx8FBOPhC/GsQwdMGmkAQ
59H/CqYFeRpe9PUktCUuEB/ct6K35G995SX2Bgr1QGyispHJUofAL6w/llYTn8SjNpNlJ1X/wa8y
pBqQwB27IuaFZQWksokwGHPlG+BVMMSSi5lO/sKRq/8wpe18/ZiVSLb4GPlyC/C3GlpR0yyjlG2b
3j09rFEjEIKWKINRPikeZrj/7BNGkBXsyZjz3iG7dMowpvjETIVXBsKXAkh8VC1pV0tHFWMQMSXO
eCFtJZOq9iENbtCkH4Hs/28URv+t/vqK1hPlV58yefrw7Nw0cF5WdDuuTBAOvHAXU9GPpNshFsks
R7TLFZa5fes4jM8OspIaoqU5Dndqq6+gaPSxW2dMwyXmtsvnyfdqX6Wd9GfAFYCQ/EiQWOSbpF9D
Q86TjzDcewPp5S0iIyQM1+kEMsxOM3RMPEZYfCe6qHGzJxdwC7wtac4dpU1RTFyuPWlPU8yLnUe+
kedqeFQjMI0zq6fjwNSEDVlfE2FtND+XcjtiG9/472IADKrl4iSpsDgaYRk2Ya27+p1tvNCB/6uT
mSfuuXEDMuk1NB9wdbIRYFlcauYmm8Ba5kIqIAmrCLR9/Uv1F/UH4ppO3WW2otpFhcwwKW5Q+Ac+
68I3Tur2seDyP8OtrjxR7aTuuBGvJFH1EpOOoLNVbvd7sTTXZ1HOhyoCZo3d2vpUWUUl0KV6lNer
/cTJc405O1DR3Be5Y231AziEATf1IPQHb/prSwA144Ql23c5i12vN/zwR50gSmeNefUXRTICOsA0
6CeB2bJrvCYSQnnH8+krBoSKomeswm4jyvZrFCwHrLdmllAdiWCEheTM1pH8VMLmmF6PRjPJm8WL
aQM1/3Ffbd9lFEehGgah0CCdzsMRVoB1Sya0lrVr1RRMtZJ9wBQkIGjtZxKDgCyON6bM/3X7vH8V
+ezeGUTx1x8w6mG+5yumpnGmcRdzYE0w1SxAQIqjWzGCt6HxOnjOWFUTq/9ATG5MyQ3uhdyqxtRX
8/ulZZFgZbF8odg3CLLfS2QYPPqSFbjECq2KCcWlH9ELHwnI6gS801uiUgGmJNrVSwt+X3s62ka/
ByuwsTjXlLM5rGaybsS6p4kLe7WGLeK8PMXDmHMXvbXGlh74EZ1iCbMTj//smsTvEmUeRCDaElNO
3PQ2dq5Jc+uw1l1wtY7i27ZEC79XO9JLJWNN5kkmEM0e+vSrIIawBaweyLt1YnW9NtyKcWAPsfTn
v0jlFaxTpu15881aYrjcqXGiwmopJly/wqINPOIObtSeWJzEIyV1ENSmOI2UBYGSvMywGEZmzc2n
p5i2fmJuQrAeEiOKkUrTDD2QDgM1NJtFSI1podRcC7mQ86nk0p24ycfSJleD+8z8dvvQGirMfa8j
DW5W2jfkhXmCQyejvCyEXVNIOm1g0DPq6RBTwS9LghlLZW3nUqkl15rPhF8IwJ1E0E7oxThOA6JN
prqDmkamKru8eyVW9UsvxibgeMOaW4YTVBRo67KhdydqVLvXzSP/9I00NjM6uZXXyo/OBruDaSdp
TNCzQAw9OsK9FiIhYOEssLfMVTQcWYWxSKSYzu+skioAv5mCoCYMCbTkxybFGVXkvd307koqdiO2
i3uLTpjpsr1DusT1eyL/iif26d8Kn0pgzIxBlJfBxqnwzIG6/nRW7O2/28RE6Jn+cKyAyfJrtE0w
hlxkDUQab8aJQI81ARU0ISJIvH5QEsrT0r1Zg2dDCkrHpLhdGdkMVvqXas9wXtfpmrow3/prbHqq
sTZ9KyYxCBcM0CTDsLOgqrhlpKiIVBhglvVofMXtHGytmLmU+JcS08eBVJgPux2K4io7hWzvPzBd
ZQk0lKD4xkXQvRfV8k7jSQZIA8uPUXzvCoXCBgPcCScgCmnaBOeRfJpV2u1+NQ6GP1rLvGjSYaYK
PWFXhqOi7OB2a3Jw62aKv29W/rIKLCyF8x5glGoqpbA8fUUHmPDxGORYc3skzlWIEwdEXIkEGC1M
Uk51XdkBpYKc46zwEQzwQeEBQafnthA55S3WKhYKTll5aS8Lm24F3TWjbtWaHOx9QJ9zUNnzxcNy
HEo8Tj2mmd4D8lD2GRoUdyuqCHCaWqhaajvbjALoEsmnJQOTRawWXwTge/imZCzpqFMH1SlPryrD
Pe2Ov/YD63BbV3nH+jisdc5YXLOttMV2s/Pg83A8k46jnc6JZxS5S0oaHosDsgZ6Ce2SyhWpdU+b
XUDQtQPNFkjVtGbiKW5ylnJfJMO/II+tLwqLH7wPZFgm2w1cxH5famwJVJzYOo/NFOBRFM53b1IL
CaJjSqUQyQtGW8QbQFpObuOdbBp1EAdFgVIV3jm1smH7HKFqpM9bREpKMk/Eg5QEL2DKMMlaQcWS
nnYhpD6pMXT8ZGcqinwP4yDYRo+ztYZNbjHp2kgv2UqGXFTB0xaIDhVKqxRzG9B8V0Fxl0Inc3PI
pjOeS2mkWRWCN6ROFCFaBVZ8xzlIraLYRyoBP+VDGTrkqFmkL/nsHk6rUdoN6Lp82YtjGH5twmw7
TDNNKVNBuFnJEf3PrTjFtHAQLUTe8XhJjKdQ+r0BII7kn27Up9+h/vRr8b6eD9y5SCxIwMHiCgX1
j5xT0iaSMvHJQ/xnz4E48OSTDRIsu+XVOVeV0MLmoD2538VhdPyeMcp9CVnpmMZfdImYjAhtp4do
wLeNwOw2AAbND6yMjKvrXo3jsUJ11TVxujf5ovCmJfxUAqPzREXU79+N6Ntz5togvkXmTC5DTVUY
ciNQTDJhXzudFTdgqMXP1GV6uQX4MP2yAEIhw3IBU7FBrwbzlZRUuP17u3/9x7tgJO7/vwSNzsgl
nladMPM9BTOXspZhLU+VFd7yKmZeNdXIyUSDZRhdLLUZr/EE4QIw4fTEooOyeG7hDjpZGkYODF9o
U0JwydocoebjlhZFKG/Jrtx0MsryXAIk6BO/g+oio1EAbNtJbabu/gkeUKK7OxPlm8IzB7Jbq7Se
dXUNzrnKgiuLxnKe8tTkqpL9j1jl/Gb+G5xLW0xBnTvryFR5rUmyDS5lowuFcja9BTvJuMEIyaY2
QAEr/3FOBy6PSagD7NF3QMVNW+2c+n9WG1f3VicCCdSiuFT/t8aQW55gRyctlqHA7vY+iSuejxBv
K3YDOUiXG/swogYBwo9TTV71iALhy0O+r/opXD06PkRszoZt59vNl1Y9wDK/0JAAA6+mUmbu4zYI
Avj3MOfSrMQBtpOSkua3j8ArdY/52Flrek6IpFRD5sten0KZOEK55LvL7pHPG0Zxa3Kr5bFSz5BC
JL0Gz+cfjinsSVrz5M6qxWApnP8OAAEkEjByvaz5lGQf/QH499/cl4nGvfi+T6AaajCeK69gkLgH
OWB4LWw2xTdx6Wqv6sgiDDqwOK2XjTjbHrk3yimngCYv6mF5vLiUcq5SKiWjkK2cFzMasGqrtCvO
HqK/gLooQo7b0dpqtYjijXHCpJTzrTKdcMZuZj/w9oYpgCC1nZHL7Jv0q+dNpBTtlVdgaxzx85yz
g+hKRLD9Dm2pxbUSYWIPGKULpw14rsmgQUtkg2jnQWKCCZfYzKh00ths+RkmKKK/5PI3iAiZKroy
nh7cjlCeqRMbFBZvhtTO7Yv+sHSc9v/RUSc9vMSqL+qIuJTfkWaY6TAKZXi+QS1MUACixb0S6DbZ
M1lbgC6ES87ZbgXszAxh/gR6h4LLxiHmu/RPK9ye7vAOBQyYNPtbGbgaKzMy6432Cc3zNOd7SXDA
KsU8f+n+dACcgDdagS9KDzWee3HX48E4Ig4IOyrQCF1+O5/23GSYxh98ZUMl26oMotoYdCSLI/Bt
m2M53X3BfwQ82htWDobMNrH7+P07f6gEp7qvhEEM17wwOjJqo0Tu507WNL2XVAipSU0sjnx1E3V6
ipS9nmPAgBeXW5tQ3t/WanqogMttWnBciYHIVFXIB8W7pfXGpU0X0jpBPSeJ9zqL0SqWI/lssHQN
hFRon3epK5XCjJeAQYRsQiZgHfBvIUY2J+kCSfFRVkeyq5d2+epuL9QMKDKv6D8RaKXuK91XwRiD
VjjniNu8FZrNXeAQx3SKsRid3Z0KEp33842RC50iAMeGAuFg37+p3pN7MDTv3/YzytjylQDp9+84
39vbe6E8zOs2+/kx7RFQI/a2WvQOdS4fFquPyto6UFVXkK7k0S3rp+I3FpXVhGBqFJ9Bhm7fWw8u
anUmEHo0SsDNBBSc/fBW/PAqz7J2bt85bLvoUbAFyQviQGCkkwdCiTjBcHKeytI309kDxKBoDn4g
UBkhreSEIinJv66mwx/MD6EyxLNhKInFRYW+ZiO4leP/Mbn3PfqKMQdeyr/3HPlq0iaRbfF3n+mw
IuoMwoAq36/5SHTpfYV7j2tvLL40M90N8GvE5EoWZbi4E79DIYpntOmITY1XVnXAgGt29fnSlM2I
uyET8OpDBlCeG3+RDw/xShCqA+KrIkQ8TANoLRRBQWO9Ia9jDTbE67tAINsYEaSCg/zqcPxmfXjv
CH/gRQ4zuE/gwbiX9ACCZYH8HvXYZYyEtNLN6ql6AuwP+8fiKULbEOaDcgm8bw67Svo3xbEnM912
4Maqgm4hvkBHAOLmdDwFW0w4lJPYa1XmSwOZpPIGtnBkgurMYt+a9ezFWHADwH5g/a1a+/Qu0vx5
KzUNCG1/l02NwMZpLn+yxXnfv2ArYwS6bLyjoX/qSypTW3E/cNC1YVLw/McK/c6GoM0f2PYRXayj
0v2efOHEGUqALZGGhvJ6Ek+j1qTmS8hmPaqrOPerij+QoyzFE/IBX1rT+QdH+HsOVQRMvBIPvQ/I
2dVY66U7Q8TC5mAHjlBs/tV1KNj/b595BTpAg+XKPB9ju6KeMLeaA2BF+OHWAgeoo2GHOGfAs3hI
lSqsYCI6YyWlxxZf54ZqQIXWAKcAYk07UhBMg5bQRUmrU9meyvl04D6DxkXH1BlTPoxdha18G/hf
h9j9r0H4zdPMqQVxWC+RzsBj3jheZcixFVgKZ7RfXyTCn3pUWKI+mCZmnAr8ycxlb6BzC4XIuPkX
0L50JsGDNkllop9IXJaWz/d+F5tY+uW0pkU5fdk36wJLmDJAEMh0uI9rSXmkBX8Kis2jhy7oirAy
aHIpWfqFa5Lp6aiBeV06cBud+E/7/vctoZIwjN4xf0GTsmJHW1Pe4R9ECwc/37fRm0a9qZWaEac/
eJvqHUU9nttb9eJz3PD6uqkhUI5gJlenVete3SFwB/t4ttxsSIpO0e0y7qwN6BOk8BEmcBKlzosz
xB8k3+J+aLx8G/RftK1LHDFpD4pe7r9B+yW4uzxtpo6ta94HRTngB60nl9i58dEtgGyuhzFzu1HP
b6Vnfnt15ysMiWHvKTgRamI25MYvjxAnwBxAUwUPc3wuL+AWhRoupJsmHkfvAJGgEJt5xWgLj4Ly
E7RpaeKjVlof2wMRpFVLU015FWmY/toriHKo4wWg6Id4Pdt2m5EFpGrJ4teqZrTpVbN86mi/5WMi
KR2rG/0RYemX88iNvSsNcORN0+29fbf8xuEVm5Hz/sb1MvmoB7JVOwOx1FKLdgjn0owGQpcRVGMn
NnLGSgyTnuXypHU67YkEPy1mxXABU1fu3KiVWmafYuqEivmkvgSQ6JEwu0Fztf/K8SH+yzWSWCMx
KJi0KdY8m+p49okhlaTZJ6DsH+v2rsYC8TneBVJefl2+hQ9fcnxRC+Y86N2Z8lXnJbNIXafeGPWm
6MWYsHTf1/lCnL24W0KqUV+5SuYaHUB8OpO5QIfurSQZfMMQNWhHet4LhCNtXkvSr3/WsPeA8iCs
a/vGp3V1yFG3y7iTlg7S6T82vQtXxAHUZPtjI/8stUmGq0hkODBO0EDqWYdpt4tZJKhTCUdnSm6S
bY0dvF8KCn4X1mqfNnhbO31qoI7ZvBbyl/vpS88XFjmYjRwwbpFIVW9RJ4Ec6lVBbzipmw5yBXvd
r6mP3ZB1z4HqKT68s14FoKHSgeztXAjWvxM0WWhj4TI3y9PeRero1lvSk25OllD+QRLy8q5Pn57R
LP/kfM8o1+sze1unrRbvm8vfKiZ+xXNYNRqhPF/0i0/cnolK0+KoJZSnV3aCljjus5zaCodb5Pk0
chTsq+7KSbAS0HKNAKUvjKgaH+0/Urat4YmV2Oe3lt67sMmnplFkfcVWdFQq2x8fCaLOMAakIGij
W7qqyq/nyp+CWNTvADQcT/5cy1kNWhkdHqBTyNcGa94rakhJNEqWj5Y0U6fejxSd7TTv0VEWiZ7j
1m4652Sx02WK/V+Wv4IW+d6cVj0mT0vz6ofb+2RMHZNUrMyWnkouK8FL7dGg439OqdfSc44dcjYq
VpWLtV9lpMuI8OhRBS/DduEJkNnN2HwPey1UkLsprfxUxbBjIy354+NsyjmXUP7LRow2EhFJaTai
a/u1a4PipiUGiXe3KzXbOHq4KETEaNY9bFYwHLiwTAlB2SIxw6qrPsTEFr8i6yex2IGiyIcsSfl4
QlFPqfEd8wS+IcU/+WoJAj5Vvb6Bh0CYWojJPX7VkJ0V8LRDq0LjBv09XoVDEzXqsFI4ySvwAvo5
tYDkaVgsAgGfCIpxh+rOdeWrkjUjm3vvJKxTMbZrO4PfEZU0Fe0u6rVb10M/hVuZGo/HXWrFKsS3
vINBltDfKfuXTzd4/mX1qRNzgE3AZh06DK0nxpA2uoJEymAMs7rpbeyqTxIMFJ7edv1LatOZvpX9
UYMUKtOHO43tHH9f+IngjSehGlnUvW+lKrbuHDjii1dVIX7sZvi6B2i4NRvzJb9Pp2+YFZF7oVTA
7ZHiifknC/1XZgGVE4t5wrVqHhc7Rny2A4BDGQZqul86nD8emKmWt76CZs0Q93h3tnhlzAPlE2nV
nIbrbbheizBXLxA+1JXZPCu4MVNeWaLMpCbjJc3+es/FB7tNe7VI5DySxIzrK8H12/QEIaBy0jdG
Xxw5mjMqVE5CVzHvbW7lh2zPsrKsP0cZdgBlfQyPltjOqACtIUURtJSQORFAg72kAZSH6LZ0FhpS
NnL7w4FfjZ6RrlzL7ilubJd7GPt0fWW2HnM9IvHMHfisJbIk9bjW0JZMZ7XBrIcNsahWZ++V8l9u
vJUmr2FNv05BWVM3W0i4WUcobg3//rWYL3Q32RCbkXQBLts8y/WqseGT71wETs8TrPrtVJnAitOU
ffbUo01EoZrhxnZFskvgYSiY2Ak3E4+JnwrARULM2+Saz/UPGzBalskO20YYVtlm2le/yi9Y6mg6
EUnl0FMySE52ZUHw/0N5nVTKhZN+GaIBilQBfgeOGciZelOPO5Z4tUH+ClrqSiZsT5tawIu+ZiiL
ATC6o4rXmSUiqWJ8ScqR1w5AUXYlrWcQKjia7cwpIC9zKKMLvFXUr8GAEHHrGAgJAhz/JYDFYOMJ
w5X/jfEUfzWs+oi8jpqENFL2qEeFlKsz6tPt19gk3x28MLXz740A+Bh/+8oYMPo9dnFnCtlqWWPo
FKtZ5hrdIiOYewRCK/XDZmlSpDd9Q8ma9JkfPYQVTeh519I8/rSKoY2ldwjVRLEA5KueZiOzTicM
Q0d/1vI4fT/+OxKwepY4psiuDyCsGneJEHd7OnNWB+p/uHBzO/9VEALb1kJBjSzowpFfxTRXrhEU
8jH3ZLz5vWJRtdhvjSjZ7ybqasOznB/lOA7Nmq092vtpWsxgFnJOtmWoXzWWCml+lVmyjojg/Wd3
EZrumFX/R3QfIuCAOqfuBIpAzKMKP0Wl4ZTV13RACfGPLADW2LpsLirj2rwjKp0MNvXWDlsgvOn6
7F7DYkWuUdB2CR21kbCjVLhRLjcYxdwaT2JAYItSf2ra02tavOStycDDC65Yb4wCI+vKRSePJbYq
2qEJri0XkNw5Q1GBp0cXRCZpYezEKpVsdBrl5dm+Bbo42azGnumu+TvAm08HKosvgsgsxTmG2eZa
+xrhGIpwmesxkAZDET8a7qbjrne4GeMeRCtXw+MfK0DcPmIWPE7iJ1OPYlZL1dFORS7TOx5h+OhP
AUquiDYRw7BFj/0cLMdvkXNhRvrKRfaSB4QddCAwhATFwYV4lccQVOJ6usw1b1AHlb//5+Qa7EiU
RFfMMmE5L+RtVTG5OZqGgTrJ1D4mXldOemQrrDZd3E+HWH4ZjmY2zOCqwINngIEZP2/cJiGXCQjk
aUsXyMlaLcsCsQfM5rkjy9if3AuHdCTYWXTn8kUtdGjBKBoo4AfZtEvTGUDk8Sc77votON7t1JAi
jbdD2ftBtKMq8xUFgWmIQ4ISkwhtD0wLuV7rgk+V8gdIxbbXhyVgSts64aGQ8gOmiK0T7mnqliad
qzfMhqPaRfppAJHl5tpeGwBOG8nX68chr7o7jRwbE4NVBZNq6FwSAJySlfM8jL4lYMoCL52gtShE
J1hyDroUFvAepbCOKtYCwcZIQdp47SBGft6f7/m7uKXzwIqqLcyIlsvWw6xnXWcIik+XL+Q5WKQn
ZhATygDaeympGI7v0jcr2FBZJ6mVOJ9uBcSR/ntZHt1YYA2zXi3ANgmofVgULOfRaMmAnWma9TLr
2T9gV3ucmCctkzljZYs/3fwb6I2+YaWKq7mNkyWwI/KKcSWmha70IcRAtCd4j6r7wHneJMNX7QvC
Cu5gOdlUfu50E6/OyBt7nJ5OgS0zC5Sbm/vyzYniQcFc/NDT+mk65tCgwSrG6vIcsHGWHWu41Q11
CCZdv503MfY60YlheE2KlkPHR/TzAFzepnvrd3AxH1nsjwSTyNxPOq9huPPt7ThoaAylkkz64ZMK
tp4YKb4uGhjMxJ6SEq/e+cSLPh0v4ygIVwsnYI6B18Pvl30jrH4M9myBBHzerRB8kgr66nPYjzGe
Hl+wjCBAAOvFte9huampFLNxftrKt3/yIRq+mFIlFSvEQ9dPWT0vZZBAbqpuBV84nR70zvhWoCT9
HL+WcoKWWpH3irxZSxYBFj2NszcaIqK6JNiJPoTseNeiudyzVNHKMzXq+a44mF2oa1KECCeBYnao
ByCW0xGZVXaGJ7uDL3CiBE3cf3nJ5vqCpLcp3Z1UjUslfAg1C61+jKRZQ25iVsGIAzoJ9WjRT/6F
xNcAkjaC91XCRCXbuRp6lLZeAFgUjPoV3Lx7zIUPc7/XeVZXUs+M3uVoHD1nKtekfzhoZME8+7f2
la9DVLRizCts5eeCeX++e7US7E23Sr4Rh92U/9hG1+zlUtUBxD6NCmjuULeoC9yWRvJXj94pjHzp
+kHQqw9kTeg1Wz2rX9CMUTOY+8JCgu5mAeV9wOA4XpniO7EwPPQC2NBlrMbx1MjoLwewRsCIHl/u
FWRY/Mi0GhADIgS1qGRZPnejhYJrnbVnFXI3QD2kw8JitEiuURsrbZfCdytQu7+bUh8xFdMWhSfq
C45V+Nuq/eLxUrX8Wdta3nE6d6ozCGXi/+MYUM0QgyesJOU8c/kXBqKqBOygcvJoz8Bn1v/4QWjo
PqXo
`protect end_protected
|
apache-2.0
|
a2008a0ee159c86d5e52c934cd5afba2
| 0.951885 | 1.837367 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_timer_cntrl.vhd
| 1 | 3,570 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 31, 2017
--! @brief Contains the entity and architecture of the
--! Timer Core's Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
--! The functionality of the Timer Core is defined in this entity and respective
--! architecture. For more information on how the Timer Core operates as a whole,
--! please see the hardware description of the top entity plasoc_timer.
entity plasoc_timer_cntrl is
generic (
timer_width : integer := 32 --! Defines the width of the Trigger and Tick Value registers.
);
port (
-- Global interface.
clock : in std_logic; --! Clock. Tested with 50 MHz.
-- Controller Control interface.
start : in std_logic; --! Starts the operation when high.
reload : in std_logic; --! Enables reloading when high.
ack : in std_logic; --! Sets Done low if the core is running with Reload.
done : out std_logic := '0'; --! If Start is high and Tick Value equals Trigger Value, Done is set high.
-- Controller Data interface.
trig_value : in std_logic_vector(timer_width-1 downto 0); --! The value Tick Value needs to equal in order for Done to be set high.
tick_value : out std_logic_vector(timer_width-1 downto 0) --! Increments every clock cycle when the core is in operation.
);
end plasoc_timer_cntrl;
architecture Behavioral of plasoc_timer_cntrl is
signal trig_value_buff : integer;
signal tick_counter : integer;
begin
-- Output the current tick value.
tick_value <= std_logic_vector(to_unsigned(tick_counter,timer_width));
-- Drive the operation of the simple timer.
process (clock)
begin
-- Perform operations in synch with the rising edge of the clock.
if rising_edge(clock) then
-- The start control signal behaves as the core's enable. The core begins
-- its operation when the start is set high.
if start='1' then
-- Check to if the counter has reached the trigger value.
if tick_counter=trig_value_buff then
-- Have the timer automatically reset if the reload flag is high.
if reload='1' then
tick_counter <= 0;
end if;
-- When the trigger value is reached, set the done signal unless
-- the timer is already being acknowledged.
if ack='0' then
done <= '1';
end if;
-- Increment the counter until the trigger value is reached.
else
-- Reset the done control signal if it is acknowledged.
if ack='1' then
done <= '0';
end if;
-- Increment the counter.
tick_counter <= tick_counter+1;
end if;
-- If the start signal is low, the operation is immediately disabled. Instead, control
-- information can be bufferred into the core.
else
trig_value_buff <= to_integer(unsigned(trig_value));
tick_counter <= 0;
done <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
c90e30302be72342bc3f1a8774542404
| 0.564146 | 4.728477 | false | false | false | false |
makestuff/dvr-connectors
|
conv-32to8/vhdl/tb_unit/conv_32to8_tb.vhdl
| 1 | 3,286 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_32to8_tb is
end entity;
architecture behavioural of conv_32to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 32-bit interface signals
signal data32 : std_logic_vector(31 downto 0);
signal valid32 : std_logic;
signal ready32 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_32to8
port map(
clk_in => sysClk,
reset_in => '0',
data32_in => data32,
valid32_in => valid32,
ready32_out => ready32,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data32 <= (others => 'Z');
valid32 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data32 <= to_4(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3)) & to_4(inLine.all(4)) & to_4(inLine.all(5)) & to_4(inLine.all(6)) & to_4(inLine.all(7)) & to_4(inLine.all(8));
valid32 <= to_1(inLine.all(10));
ready8 <= to_1(inLine.all(12));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready32);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data32 <= (others => 'Z');
valid32 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
5e19f2af3670a34c68c29923b4c056b3
| 0.671637 | 3.117647 | false | false | false | false |
Ttl/pic16f84
|
memory_instruction.vhd
| 1 | 1,678 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use work.picpkg.all;
entity memory_instruction is
Generic (
CONTENTS : string := "scripts/instructions.mif"
);
Port ( clk : in STD_LOGIC;
a1 : in STD_LOGIC_VECTOR (12 downto 0);
d1 : out STD_LOGIC_VECTOR (13 downto 0);
wd : in STD_LOGIC_VECTOR (13 downto 0);
we : in STD_LOGIC);
end memory_instruction;
architecture Behavioral of memory_instruction is
impure function init_mem(mif_file_name : in string) return mem_type14 is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(13 downto 0);
variable temp_mem : mem_type14;
variable i : integer := 0;
begin
for j in 0 to mem_type14'length-1 loop
if not endfile(mif_file) then
readline(mif_file, mif_line);
-- Xilinx ISE implementation fix, uncomment to enable implementation and lose the last instruction
--if not endfile(mif_file) then
read(mif_line, temp_bv);
temp_mem(j) := to_stdlogicvector(temp_bv);
--end if;
else
temp_mem(j) := (others => '0');
end if;
end loop;
return temp_mem;
end function;
signal mem : mem_type14 := init_mem(CONTENTS);
begin
process(clk, we, a1, mem)
begin
if rising_edge(clk) then
if we = '1' then
--Write
mem(to_integer(unsigned(a1(INST_MEM_SIZE - 1 downto 0)))) <= wd;
end if;
-- Set output
d1 <= mem(to_integer(unsigned(a1(INST_MEM_SIZE - 1 downto 0))));
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
6154c752afeffdb27679fdd9b12193f5
| 0.612038 | 3.42449 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch_defs.vhdl
| 1 | 10,347 |
library ieee;
use ieee.std_logic_1164.all;
package arch_defs is
subtype byte_t is std_logic_vector( 7 downto 0);
subtype half_t is std_logic_vector(15 downto 0);
subtype word_t is std_logic_vector(31 downto 0);
subtype addr_t is std_logic_vector(31 downto 0);
subtype intaddr_t is std_logic_vector(31 downto 0);
subtype addrdiff_t is std_logic_vector(31 downto 0);
subtype ctrl_t is std_logic;
subtype ctrl_memwidth_t is std_logic_vector(1 downto 0);
subtype instruction_t is word_t;
subtype mask_t is word_t;
subtype reg_t is std_logic_vector(4 downto 0);
subtype opcode_t is std_logic_vector(5 downto 0);
subtype func_t is std_logic_vector(5 downto 0);
function is_type_r(instr: instruction_t) return boolean;
function is_type_j(instr: instruction_t) return boolean;
function is_type_I(instr: instruction_t) return boolean;
function J(op : std_logic_vector) return std_logic_vector;
function I(op : std_logic_vector; rs : std_logic_vector := "-----"; rt :std_logic_vector := "-----") return std_logic_vector;
function R(op : std_logic_vector := "000000"; rs : std_logic_vector := "-----"; rt : std_logic_vector := "-----"; rd : std_logic_vector := "-----";shift : std_logic_vector := "00000"; func : std_logic_vector(5 downto 0)) return std_logic_vector;
function word(w : word_t) return word_t;
function half(w : word_t) return half_t;
function byte(w : word_t) return byte_t;
constant WIDTH_NONE : ctrl_memwidth_t := "00";
constant WIDTH_BYTE : ctrl_memwidth_t := "01";
constant WIDTH_HALF : ctrl_memwidth_t := "10";
constant WIDTH_WORD : ctrl_memwidth_t := "11";
type alu_op_t is (
ALU_ADD, ALU_ADDU, ALU_SUB, ALU_SUBU,
ALU_AND, ALU_OR, ALU_NOR, ALU_XOR, ALU_LU,
ALU_SLL, ALU_SRL, ALU_SRA,
ALU_MULT, ALU_MULTU, ALU_DIV, ALU_DIVU,
ALU_MFHI, ALU_MFLO, ALU_MTHI, ALU_MTLO,
ALU_SLT, ALU_SLTU, -- TODO zero extend or sign extent?
ALU_EQ, ALU_NE, ALU_LEZ, ALU_LTZ, ALU_GTZ, ALU_GEZ
);
subtype traps_t is std_logic_vector(7 downto 0);
constant TRAP_NONE : traps_t := X"00";
constant TRAP_DIVERROR : traps_t := X"01";
constant TRAP_OVERFLOW : traps_t := X"02";
constant TRAP_SEGFAULT : traps_t := X"04";
constant TRAP_BREAKPOINT : traps_t := X"08";
constant TRAP_SYSCALL : traps_t := X"10";
constant TRAP_EPE : traps_t := X"20";
constant TRAP_UNIMPLEMENTED : traps_t := X"40";
type exception_config_t is (
EXCEPTIONS_IGNORE -- Bad idea!
--EXCEPTIONS_HALT,-- e.g. light a red LED and stop fetching new instructions
--EXCEPTIONS_RESET-- reboot
--EXCEPTIONS_TRAP -- invoke user-programmable exception handlers
);
-- Taken from https://opencores.org/project,plasma,opcodes
-- And http://web.cse.ohio-state.edu/~crawfis.3/cse675-02/Slides/MIPS%20Instruction%20Set.pdf
-- 32 bit defines
constant ZERO : word_t := X"00000000";
constant HI_Z : word_t := (others => 'Z');
constant NEG_ONE : word_t := not ZERO;
constant INT_MIN : word_t := X"8000_0000";
constant INT_MAX : word_t := X"7fff_ffff";
constant DONT_CARE : word_t := (others => 'X');
-- Register file
constant R0 : reg_t := B"0_0000"; -- $zero
constant R1 : reg_t := B"0_0001"; alias AT is R1;
constant R2 : reg_t := B"0_0010"; alias v0 is R2;
constant R3 : reg_t := B"0_0011"; alias v1 is R3;
constant R4 : reg_t := B"0_0100"; alias a0 is R4;
constant R5 : reg_t := B"0_0101"; alias a1 is R5;
constant R6 : reg_t := B"0_0110"; alias a2 is R6;
constant R7 : reg_t := B"0_0111"; alias a3 is R7;
constant R8 : reg_t := B"0_1000"; alias t0 is R8;
constant R9 : reg_t := B"0_1001"; alias t1 is R9;
constant R10 : reg_t := B"0_1010"; alias t2 is R10;
constant R11 : reg_t := B"0_1011"; alias t3 is R11;
constant R12 : reg_t := B"0_1100"; alias t4 is R12;
constant R13 : reg_t := B"0_1101"; alias t5 is R13;
constant R14 : reg_t := B"0_1110"; alias t6 is R14;
constant R15 : reg_t := B"0_1111"; alias t7 is R15;
constant R16 : reg_t := B"1_0000"; alias s0 is R16;
constant R17 : reg_t := B"1_0001"; alias s1 is R17;
constant R18 : reg_t := B"1_0010"; alias s2 is R18;
constant R19 : reg_t := B"1_0011"; alias s3 is R19;
constant R20 : reg_t := B"1_0100"; alias s4 is R20;
constant R21 : reg_t := B"1_0101"; alias s5 is R21;
constant R22 : reg_t := B"1_0110"; alias s6 is R22;
constant R23 : reg_t := B"1_0111"; alias s7 is R23;
constant R24 : reg_t := B"1_1000"; alias t8 is R24;
constant R25 : reg_t := B"1_1001"; alias t9 is R25;
constant R26 : reg_t := B"1_1010"; alias k0 is R26;
constant R27 : reg_t := B"1_1011"; alias k1 is R27;
constant R28 : reg_t := B"1_1100"; alias gp is R28;
constant R29 : reg_t := B"1_1101"; alias sp is R29;
constant R30 : reg_t := B"1_1110"; alias fp is R30;
constant R31 : reg_t := B"1_1111"; alias ra is R31;
constant VGA_PIXELFREQ : natural := 25175*1000;
end arch_defs;
package body arch_defs is
function is_type_r(instr: instruction_t) return boolean is
begin
return instr(31 downto 26) = "000000";
end is_type_r;
function is_type_j(instr: instruction_t) return boolean is
begin
return instr(31 downto 26) = "000010"
or instr(31 downto 26) = "000011";
end is_type_j;
function is_type_i(instr: instruction_t) return boolean is
begin
return not is_type_j(instr) and not is_type_r(instr);
end is_type_i;
function J(op : std_logic_vector) return std_logic_vector is
begin return op & (31-6 downto 0 => '-');
end J;
function I(op : std_logic_vector; rs : std_logic_vector := "-----"; rt :std_logic_vector := "-----") return std_logic_vector is
begin return op & rs & rt & (15 downto 0 => '-');
end I;
function R(op : std_logic_vector := "000000"; rs : std_logic_vector := "-----"; rt : std_logic_vector := "-----"; rd : std_logic_vector := "-----";shift : std_logic_vector := "00000"; func : std_logic_vector(5 downto 0)) return std_logic_vector is
begin return op & (14 downto 0 => '-') & shift & func;
end R;
function word(w : word_t) return word_t is
begin
return w(31 downto 0);
end function;
function half(w : word_t) return half_t is
begin
return w(15 downto 0);
end function;
function byte(w : word_t) return byte_t is
begin
return w( 7 downto 0);
end function;
-- ALU
constant OP_ADD : mask_t := R(func => "100000");
constant OP_ADDU : mask_t := R(func => "100001");
constant OP_AND : mask_t := R(func => "100100");
constant OP_NOR : mask_t := R(func => "100111");
constant OP_OR : mask_t := R(func => "100101");
constant OP_SLT : mask_t := R(func => "101010");
constant OP_SLTU : mask_t := R(func => "101011");
constant OP_SUB : mask_t := R(func => "100010");
constant OP_SUBU : mask_t := R(func => "100011");
constant OP_XOR : mask_t := R(func => "100110");
constant OP_ADDI : mask_t := I(op => "001000");
constant OP_ADDIU : mask_t := I(op => "001001");
constant OP_ANDI : mask_t := I(op => "001100");
constant OP_LUI : mask_t := I(op => "001111");
constant OP_ORI : mask_t := I(op => "001101");
constant OP_SLTI : mask_t := I(op => "001010");
constant OP_SLTIU : mask_t := I(op => "001011");
constant OP_XORI : mask_t := I(op => "001110");
-- Shifter
constant OP_SLL : mask_t := R(shift => "-----", func => "000000");
constant OP_SLLV : mask_t := R(shift => "00000", func => "000100");
constant OP_SRA : mask_t := R(shift => "-----", func => "000011");
constant OP_SRAV : mask_t := R(shift => "00000", func => "000111");
constant OP_SRL : mask_t := R(shift => "-----", func => "000010");
constant OP_SRLV : mask_t := R(shift => "00000", func => "000110");
-- Multiply and Divide
constant OP_DIV : mask_t := R(rd => "00000", func => "011010");
constant OP_DIVU : mask_t := R(rd => "00000", func => "011011");
constant OP_MFHI : mask_t := R(rs => "00000", rt => "00000", func => "010000");
constant OP_MFLO : mask_t := R(rs => "00000", rt => "00000", func => "010010");
constant OP_MTHI : mask_t := R(rt => "00000", rd => "00000", func => "010001");
constant OP_MTLO : mask_t := R(rt => "00000", rd => "00000", func => "010011");
constant OP_MULT : mask_t := R(rd => "00000", func => "011000");
constant OP_MULTU : mask_t := R(rd => "00000", func => "011001");
-- Branch
constant OP_BEQ : mask_t := I(op => "000100");
constant OP_BGEZ : mask_t := I(op => "000001", rt => "00001");
constant OP_BGEZAL: mask_t := I(op => "000001", rt => "10001");
constant OP_BGTZ : mask_t := I(op => "000111", rt => "00000");
constant OP_BLEZ : mask_t := I(op => "000110", rt => "00000");
constant OP_BLTZ : mask_t := I(op => "000001", rt => "00000");
constant OP_BLTZAL: mask_t := I(op => "000001", rt => "10000");
constant OP_BNE : mask_t := I(op => "000101");
constant OP_J : mask_t := J(op => "000010");
constant OP_JAL : mask_t := J(op => "000011");
constant OP_JR : mask_t := R(rt => R0, func => "001000", rd => R0);
constant OP_JALR : mask_t := R(rt => R0, func => "100010");
constant OP_BREAK : mask_t := "000000"&(19 downto 0 => '-')&"001101";
constant OP_MFC0 : mask_t := "010000"&"00000"&(9 downto 0 => '-')&(10 downto 0 => '0');
constant OP_MTC0 : mask_t := "010000"&"00100"&(9 downto 0 => '-')&(10 downto 0 => '0');
constant OP_SYSCALL : mask_t := "000000"&(19 downto 0 => '-')&"001100";
-- Memory Access
constant OP_LB : mask_t := I(op => "100000");
constant OP_LBU : mask_t := I(op => "100100");
constant OP_LH : mask_t := I(op => "100001");
constant OP_LHU : mask_t := I(op => "100101");
constant OP_LW : mask_t := I(op => "100011");
constant OP_SB : mask_t := I(op => "101000");
constant OP_SH : mask_t := I(op => "101001");
constant OP_SW : mask_t := I(op => "101011");
end arch_defs;
|
gpl-3.0
|
55e3c86ce0d96613bd1f122170d30c99
| 0.573113 | 3.089579 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_command/sim/fifo_generator_command.vhd
| 1 | 33,780 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_command IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_command;
ARCHITECTURE fifo_generator_command_arch OF fifo_generator_command IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_command_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 24,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 24,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_command_arch;
|
bsd-3-clause
|
cdaf692df7d1c269c8be4537ca3497b0
| 0.6082 | 3.074823 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/synth/mig_wrap_proc_sys_reset_0_0.vhd
| 1 | 6,622 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mig_wrap_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_0_0;
ARCHITECTURE mig_wrap_proc_sys_reset_0_0_arch OF mig_wrap_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mig_wrap_proc_sys_reset_0_0_arch : ARCHITECTURE IS "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=virtex7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "virtex7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_0_0_arch;
|
mit
|
b259c6d63ed666f95d216aaaef9fb228
| 0.713078 | 3.463389 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_1_0/sim/mig_wrap_proc_sys_reset_1_0.vhd
| 1 | 5,866 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY mig_wrap_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_1_0;
ARCHITECTURE mig_wrap_proc_sys_reset_1_0_arch OF mig_wrap_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "virtex7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_1_0_arch;
|
mit
|
57d1e1726cde7b90a06ff7a528e9166e
| 0.706444 | 3.57465 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/src/PmodNAV_axi_gpio_0_0/sim/PmodNAV_axi_gpio_0_0.vhd
| 1 | 9,592 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_11;
USE axi_gpio_v2_0_11.axi_gpio;
ENTITY PmodNAV_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END PmodNAV_axi_gpio_0_0;
ARCHITECTURE PmodNAV_axi_gpio_0_0_arch OF PmodNAV_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodNAV_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 1,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"0000000F",
C_TRI_DEFAULT => X"00000000",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"00000001"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i,
gpio2_io_o => gpio2_io_o,
gpio2_io_t => gpio2_io_t
);
END PmodNAV_axi_gpio_0_0_arch;
|
bsd-3-clause
|
b95381d16e628dfacef8716eadfd50fb
| 0.679629 | 3.190951 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/regFile.vhdl
| 1 | 1,220 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
use work.txt_utils.all;
entity regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end regFile;
architecture behav of regFile is
type regfile_t is array (31 downto 0) of word_t;
signal reg : regfile_t := (0 => ZERO, others => ZERO);
signal reg1, reg2, reg3, reg4 : word_t; -- for debug purposes only
begin process(clk, rst, readreg1, readreg2)
begin
readdata1 <= reg(vtou(readreg1));
readdata2 <= reg(vtou(readreg2));
if rst = '1' then
for i in 0 to 31 loop reg(i) <= ZERO; end loop;
elsif rising_edge(clk) then
if regWrite = '1' and writereg /= R0 then
printf(ANSI_GREEN & "R%s=%s\n", writereg, writedata);
reg(vtou(writereg)) <= writedata;
end if;
end if;
end process;
reg1 <= reg(1);
reg2 <= reg(2);
reg3 <= reg(3);
reg4 <= reg(4);
end behav;
|
gpl-3.0
|
09f5ce2f2205503c59ab5e7c05fa8241
| 0.568852 | 3.388889 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/AXI_DPTI_1.0/src/AXI_DPTI_v1_0_AXI_LITE.vhd
| 1 | 18,395 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dpti_v1_0_AXI_LITE is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
lAXI_LiteLengthReg : out std_logic_vector (31 downto 0);
lAXI_LiteControlReg : out std_logic_vector (31 downto 0);
lAXI_LiteStatusReg : in std_logic_vector (31 downto 0);
lPushLength : out std_logic;
lPushControl : out std_logic;
lRdyLength : in std_logic;
lRdyControl : in std_logic;
lAckLength : in std_logic;
lAckControl : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dpti_v1_0_AXI_LITE;
architecture arch_imp of axi_dpti_v1_0_AXI_LITE is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
------------------------------------------------------------------------
--User signals
------------------------------------------------------------------------
signal lOneshotTriggerLength : std_logic := '0'; -- used to generate LENGTH handshakedata IPUSH signal
signal lOneshotTriggerControl : std_logic := '0'; -- used to generate CONTROL handshakedata IPUSH signal
signal lCtlPushLength : std_logic ;
signal lCtlPushControl : std_logic ;
signal lLengthTrig : std_logic := '0';
signal lControlTrig : std_logic := '0';
signal lLengthFlag : std_logic := '0';
signal lControlFlag : std_logic := '0';
begin
lPushLength <= lCtlPushLength;
lPushControl <= lCtlPushControl;
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
lAXI_LiteLengthReg <= slv_reg0; -- LENGTH register
lAXI_LiteControlReg <= slv_reg1; -- CONTROL register
slv_reg2 <= lAXI_LiteStatusReg; -- STATUS register
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
-- slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
lOneshotTriggerLength <= '0';
lOneshotTriggerControl <= '0';
else
lOneshotTriggerLength <= '0';
lOneshotTriggerControl <= '0';
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
lOneshotTriggerLength <= '1'; -- oneshot
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
lOneshotTriggerControl <= '1'; -- oneshot
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
-- slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
-- slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--------------------------------------------------------------------------------------------------------------------------
GEN_lPushLength: process (S_AXI_ACLK)
variable count : integer range 0 to 1;
begin
if rising_edge (S_AXI_ACLK) then
if lOneshotTriggerLength = '1' and lLengthFlag = '0' then
lLengthTrig <= '1';
end if;
if lLengthTrig = '0' or lRdyLength = '0' or lControlTrig = '1' then
count := 1;
lCtlPushLength <= '0';
elsif count = 1 and lRdyControl = '1' then
lCtlPushLength <= '1';
count := 0;
else
lCtlPushLength <= '0';
end if;
if lCtlPushLength = '1' then
lLengthTrig <= '0';
lLengthFlag <= '1';
end if;
if lAckLength = '1' then
lLengthFlag <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
GEN_lPushControl: process (S_AXI_ACLK)
variable count : integer range 0 to 1;
begin
if rising_edge (S_AXI_ACLK) then
if lOneshotTriggerControl = '1' and lControlFlag = '0' then
lControlTrig <= '1';
end if;
if lControlTrig = '0' or lRdyControl = '0' then
count := 1;
lCtlPushControl <= '0';
elsif count = 1 then
lCtlPushControl <= '1';
count := 0;
elsif count = 0 then
lCtlPushControl <= '0';
end if;
if lCtlPushControl = '1' then
lControlTrig <= '0';
lControlFlag <= '1';
end if;
if lAckControl = '1' then
lControlFlag <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
-- User logic ends
end arch_imp;
|
bsd-3-clause
|
d95bdd373ad9208331c4bfb274c8be26
| 0.594401 | 3.65125 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/mem_ctrl.vhd
| 13 | 6,562 |
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal address_reg : std_logic_vector(31 downto 2);
signal byte_we_reg : std_logic_vector(3 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
data_r, opcode_reg, next_opcode_reg, mem_state_reg,
address_reg, byte_we_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_we_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_we_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := data_r;
when MEM_READ16 | MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
when MEM_READ8 | MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
when MEM_WRITE32 =>
data_write_var := data_write;
byte_we_var := "1111";
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_we_var := "1100";
else
byte_we_var := "0011";
end if;
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_we_var := "1000";
when "01" =>
byte_we_var := "0100";
when "10" =>
byte_we_var := "0010";
when others =>
byte_we_var := "0001";
end case;
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_we_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_we_var := "0000";
else
address_var := address_in(31 downto 2);
byte_we_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
address_reg <= ZERO(31 downto 2);
byte_we_reg <= "0000";
elsif rising_edge(clk) then
if pause_in = '0' then
address_reg <= address_var;
byte_we_reg <= byte_we_var;
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= data_r;
end if;
end if;
end if;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
address_next <= address_var;
byte_we_next <= byte_we_var;
address <= address_reg;
byte_we <= byte_we_reg;
data_w <= data_write_var;
end process; --data_proc
end; --architecture logic
|
mit
|
9e15a86a31140d713323b5299e3e5c0b
| 0.558671 | 3.392968 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vsigactofkoftwo.vhd
| 1 | 1,419 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vsigactofkoftwo is
port (
clock : in std_logic;
Vactcapofkoftwo : in std_logic_vector(31 downto 0);
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : out std_logic_vector(31 downto 0)
);
end k_ukf_Vsigactofkoftwo;
architecture struct of k_ukf_Vsigactofkoftwo is
component k_ukf_Vsigactofkofzero is
port (
clock : in std_logic;
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Vsigactofkofzero : out std_logic_vector(31 downto 0)
);
end component;
begin
M1 : k_ukf_Vsigactofkofzero port map
( clock => clock,
I => I,
Isc => Isc,
Vactcapofk => Vactcapofkoftwo,
M => M,
D => D,
B => B,
Vsigactofkofzero => Vsigactofkoftwo);
end struct;
|
gpl-2.0
|
7225a8c823184e86b7e156b7a01494f7
| 0.544045 | 3.638462 | false | false | false | false |
edgd1er/M1S1_INFO
|
S1_AEO/TP_Bonus_feu_rouge/L3TP5/fsmtravaux_tb.vhd
| 1 | 2,244 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:29 10/06/2014
-- Design Name:
-- Module Name: /home/m1/dubiez/Documents/AEO_TP/TP_Bonus/L3TP5/fsmtravaux_tb.vhd
-- Project Name: L3TP5
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fsm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fsmtravaux_tb IS
END fsmtravaux_tb;
ARCHITECTURE behavior OF fsmtravaux_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fsm
PORT(
clk : IN std_logic;
travaux : IN std_logic;
Led : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal travaux : std_logic := '0';
--Outputs
signal Led : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fsm PORT MAP (
clk => clk,
travaux => travaux,
Led => Led
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*13;
travaux<= '1';
wait for clk_period*10;
travaux<= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
6b81dc834040b39fe2e25b17840c0c1f
| 0.5918 | 3.842466 | false | true | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/alu.vhd
| 13 | 2,633 |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity alu is
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end; --alu
architecture logic of alu is
signal do_add : std_logic;
signal sum : std_logic_vector(32 downto 0);
signal less_than : std_logic;
begin
do_add <= '1' when alu_function = ALU_ADD else '0';
sum <= bv_adder(a_in, b_in, do_add);
less_than <= sum(32) when a_in(31) = b_in(31) or alu_function = ALU_LESS_THAN
else a_in(31);
GENERIC_ALU: if alu_type = "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else
ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
a_in or b_in when alu_function=ALU_OR else
a_in and b_in when alu_function=ALU_AND else
a_in xor b_in when alu_function=ALU_XOR else
a_in nor b_in when alu_function=ALU_NOR else
ZERO;
end generate;
AREA_OPTIMIZED_ALU: if alu_type /= "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else (others => 'Z');
c_alu <= ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
(others => 'Z');
c_alu <= a_in or b_in when alu_function=ALU_OR else (others => 'Z');
c_alu <= a_in and b_in when alu_function=ALU_AND else (others => 'Z');
c_alu <= a_in xor b_in when alu_function=ALU_XOR else (others => 'Z');
c_alu <= a_in nor b_in when alu_function=ALU_NOR else (others => 'Z');
c_alu <= ZERO when alu_function=ALU_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
|
mit
|
819f470559cb0561411c2729dcc709f0
| 0.550323 | 3.577446 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/dvi2rgb_v1_6/src/dvi2rgb.vhd
| 1 | 11,118 |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "900p_edid.txt"; -- Select EDID file to use
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(0); -- blue is channel 0
pData(15 downto 8) <= pDataIn(1); -- green is channel 1
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
bsd-3-clause
|
354b5671d6dc37057759a2add528f5ac
| 0.606584 | 4.552826 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/txt_utils.vhdl
| 1 | 14,808 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all; --defines line, output
package txt_utils is
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
function TO_BSTRING (value : STD_LOGIC_VECTOR) return STRING;
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
-- can't resolve overload for function call, slice or indexed name, otherwise
--alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
--alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
--function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
--alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
--function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
--alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
--function TO_HSTRING (VALUE : UNSIGNED) return STRING;
--alias TO_HEX_STRING is TO_HSTRING [UNSIGNED return STRING];
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
--pragma synthesis_off
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
--pragma synthesis_on
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- File: debugio_h.vhd
-- Version: 3.0 (June 6, 2004)
-- Source: http://bear.ces.cwru.edu/vhdl
-- Date: June 6, 2004 (Copyright)
-- Author: Francis G. Wolff Email: [email protected]
-- Author: Michael J. Knieser Email: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version: http://www.gnu.org/licenses/gpl.html
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
function sprintf(fmt: string; s0, s1, s2, s3: string; i0: integer) return string;
procedure printf(fmt: string; s0, s1, s2, s3: string; i0: integer);
procedure printf(fmt: string);
procedure printf(fmt: string; s1: string);
procedure printf(fmt: string; s1, s2: string);
procedure printf(fmt: string; i1: integer);
procedure printf(fmt: string; i1: integer; s2: string);
procedure printf(fmt: string; i1: integer; s2, s3: string);
procedure printf(fmt: string; v0: std_logic_vector);
procedure printf(fmt: string; v0, v1: std_logic_vector);
procedure printf(fmt: string; v0, v1, v2: std_logic_vector);
procedure printf(fmt: string; v0, v1, v2, v3: std_logic_vector);
procedure printf(fmt: string; s0 : string; v0: std_logic_vector);
procedure printf(fmt: string; v0 : std_logic_vector; s0: string);
function pf(arg1: in boolean) return string;
constant ANSI_NONE : string := ESC & "[m";
constant ANSI_RED : string := ESC & "[31m";
constant ANSI_GREEN : string := ESC & "[32m";
constant ANSI_BLUE : string := ESC & "[34m";
end txt_utils;
package body txt_utils is
--synth
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1) := "!";
begin
--pragma synthesis_off
result (1) := MVL9_to_char (value);
--pragma synthesis_on
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_string;
-- ISE chokes on function aliases, so duplicating the code here
function to_bstring (value : STD_LOGIC_VECTOR) return STRING is
alias ivalue : STD_LOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_bstring;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_hstring;
function to_hstring (VALUE : UNSIGNED) return STRING is
begin
return TO_HSTRING(std_logic_vector(VALUE));
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
function sprintf(fmt: string; s0, s1, s2, s3: string; i0: integer) return string is
variable W: line; variable i, fi, di: integer:=0;
begin
--pragma synthesis_off
loop
--write(W, string'("n=")); write(W, s0'length);
--write(W, string'(" L=")); write(W, s0'left);
--write(W, string'(" R=")); write(W, s0'right);
--writeline(output, W);
fi:=fi+1; if fi>fmt'length then exit; end if;
if fmt(fi)='%' then
fi:=fi+1; if fi>fmt'length then exit; end if;
if fmt(fi)='s' then
case di is
when 0 => i:=s0'left;
while i<=s0'right loop
if s0(i)=NUL then exit; end if;
write(W, s0(i)); i:=i+1;
end loop;
when 1 => i:=s1'left;
while i<=s1'right loop
if s1(i)=NUL then exit; end if;
write(W, s1(i)); i:=i+1;
end loop;
when 2 => i:=s2'left;
while i<=s2'length loop
if s2(i)=NUL then exit; end if;
write(W, s2(i)); i:=i+1;
end loop;
when 3 => i:=s3'left;
while i<=s3'length loop
if s3(i)=NUL then exit; end if;
write(W, s3(i)); i:=i+1;
end loop;
when others =>
end case;
di:=di+1;
elsif fmt(fi)='d' or fmt(fi)='i' then
case di is
when 0 => write(W, i0); when others => end case;
di:=di+1;
end if;
elsif fmt(fi)='\' then
fi:=fi+1; if fi>fmt'length then exit; end if;
case fmt(fi) is
when 'n' => write(W, LF);
when others => write(W, fmt(fi));
end case;
else write(W, fmt(fi));
end if;
end loop;
return W.all;
--pragma synthesis_on
return "";
end sprintf;
procedure printf(fmt: string; s0, s1, s2, s3: string; i0: integer) is
variable W: line;
variable lastch : string(1 to 2) := fmt(fmt'high-1 to fmt'high);
begin
--pragma synthesis_off
Write(W, ANSI_BLUE);
Write(W, sprintf(fmt(fmt'low to fmt'high-1), s0, s1, s2, s3, i0));
if not (fmt(fmt'high) = 'n' and fmt(fmt'high -1) = '\') then
Write(W, fmt(fmt'high-1 to fmt'high-2));
end if;
Write(W, ANSI_NONE);
writeline(output, W);
--pragma synthesis_on
end printf;
procedure printf(fmt: string) is
begin printf(fmt, "", "", "", "", 0); end printf;
procedure printf(fmt: string; s1: string) is
begin printf(fmt, s1, "", "", "", 0); end printf;
procedure printf(fmt: string; s1, s2: string) is
begin printf(fmt, s1, s2, "", "", 0); end printf;
procedure printf(fmt: string; i1: integer) is
begin printf(fmt, "", "", "", "", i1); end printf;
procedure printf(fmt: string; i1: integer; s2: string) is
begin printf(fmt, "", s2, "", "", i1); end printf;
procedure printf(fmt: string; i1: integer; s2, s3: string) is
begin printf(fmt, "", s2, s3, "", i1); end printf;
procedure printf(fmt: string; v0, v1, v2, v3: std_logic_vector) is
begin printf(fmt, to_hstring(v0), to_hstring(v1), to_hstring(v2), to_hstring(v3), 0); end printf;
procedure printf(fmt: string; v0, v1, v2: std_logic_vector) is
begin printf(fmt, v0, v1, v2, ""); end printf;
procedure printf(fmt: string; v0: std_logic_vector) is
begin printf(fmt, to_hstring(v0), "", "", "", 0); end printf;
procedure printf(fmt: string; v0, v1: std_logic_vector) is
begin printf(fmt, to_hstring(v0), to_hstring(v1), "", "", 0); end printf;
procedure printf(fmt: string; s0 : string; v0: std_logic_vector) is
begin printf(fmt, s0, to_hstring(v0), "", "", 0); end printf;
procedure printf(fmt: string; v0 : std_logic_vector; s0: string) is
begin printf(fmt, to_hstring(v0), s0, "", "", 0); end printf;
function pf(arg1: in boolean) return string is
begin
if arg1 then return "true"; else return "false"; end if;
end pf;
end txt_utils;
|
gpl-3.0
|
59c88cc9dc941a565487dd934011b061
| 0.523096 | 3.601167 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/lib_fifo_v1_0_4/hdl/src/vhdl/sync_fifo_fg.vhd
| 4 | 70,345 |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
bsd-3-clause
|
e10e505f2a127c328d6b5e94db6e06d3
| 0.425219 | 3.864048 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/AXI_DPTI_1.0/src/AXI_DPTI_v1_0.vhd
| 1 | 25,816 |
------------------------------------------------------------------------------
--
-- File: axi_dpti_v1_0.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
--This is the top module for the AXI DPTI project. It defines the top level ports
--for the DPTI interface, AXI Lite interface and the AXI Stream interface. The module
--is also used to declare the FIFOs (RX and TX) and the DPTI to STREAM and STREAM to
--DPTI converters as well as the module responsible for the AXI Lite interface.
--Another function for the module is the clock domain crossings for the LENGTH,
--CONTROL and STATUS AXI Lite registers, using the HandshakeData and SyncAsync
--modules. A PLL is also instantiated here which is used to compensate for the
--prog_clko BUFG delay.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity axi_dpti_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface AXI_LITE
C_AXI_LITE_DATA_WIDTH : integer := 32;
C_AXI_LITE_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
--DPTI INTERFACE
prog_clko : in STD_LOGIC;
prog_rxen : in STD_LOGIC;
prog_txen : in STD_LOGIC;
prog_spien : in STD_LOGIC;
prog_rdn : out STD_LOGIC;
prog_wrn : out STD_LOGIC;
prog_oen : out STD_LOGIC;
prog_siwun : out STD_LOGIC;
prog_d : inout STD_LOGIC_VECTOR (7 downto 0);
--AXI STREAM INTERFACE
m_axis_aclk : in std_logic;
m_axis_aresetn : in std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(31 downto 0);
m_axis_tkeep : out std_logic_vector(3 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
s_axis_aclk : in std_logic;
s_axis_aresetn : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(31 downto 0);
s_axis_tkeep : in std_logic_vector(3 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface AXI_LITE
axi_lite_aclk : in std_logic;
axi_lite_aresetn : in std_logic;
axi_lite_awaddr : in std_logic_vector(C_AXI_LITE_ADDR_WIDTH-1 downto 0);
axi_lite_awprot : in std_logic_vector(2 downto 0);
axi_lite_awvalid : in std_logic;
axi_lite_awready : out std_logic;
axi_lite_wdata : in std_logic_vector(C_AXI_LITE_DATA_WIDTH-1 downto 0);
axi_lite_wstrb : in std_logic_vector((C_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
axi_lite_wvalid : in std_logic;
axi_lite_wready : out std_logic;
axi_lite_bresp : out std_logic_vector(1 downto 0);
axi_lite_bvalid : out std_logic;
axi_lite_bready : in std_logic;
axi_lite_araddr : in std_logic_vector(C_AXI_LITE_ADDR_WIDTH-1 downto 0);
axi_lite_arprot : in std_logic_vector(2 downto 0);
axi_lite_arvalid : in std_logic;
axi_lite_arready : out std_logic;
axi_lite_rdata : out std_logic_vector(C_AXI_LITE_DATA_WIDTH-1 downto 0);
axi_lite_rresp : out std_logic_vector(1 downto 0);
axi_lite_rvalid : out std_logic;
axi_lite_rready : in std_logic
);
end axi_dpti_v1_0;
architecture arch_imp of axi_dpti_v1_0 is
--------------------------------------------------------------------------------------------------------------------------
-- component declaration
component axi_dpti_v1_0_AXI_LITE is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
lAXI_LiteLengthReg : out std_logic_vector (31 downto 0);
lAXI_LiteControlReg : out std_logic_vector (31 downto 0);
lAXI_LiteStatusReg : in std_logic_vector (31 downto 0);
lPushLength : out std_logic;
lPushControl : out std_logic;
lRdyLength : in std_logic;
lRdyControl : in std_logic;
lAckLength : in std_logic;
lAckControl : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dpti_v1_0_AXI_LITE;
--------------------------------------------------------------------------------------------------------------------------
component HandshakeData is
Generic (
kDataWidth : natural := 32);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component fifo_generator_0
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component AXI_S_to_DPTI_converter is
Port (
pResetTx : in std_logic;
PROG_CLK : in std_logic;
pTxe : in std_logic;
pWr : out std_logic;
pDataOut : out std_logic_vector (7 downto 0);
pOutTready : out std_logic;
pInTdata : in std_logic_vector (31 downto 0);
pInTvalid : in std_logic;
pInTlast : in std_logic;
pInTkeep : in std_logic_vector (3 downto 0);
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pTxLengthEmpty : out std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component DPTI_to_AXI_S_converter is
Port (
pResetRx : in std_logic;
PROG_CLK : in std_logic;
pRxf : in std_logic;
pRd : out std_logic;
pOe : out std_logic;
pDataIn : in std_logic_vector (7 downto 0);
pInTready : in std_logic;
pOutTdata : out std_logic_vector (31 downto 0);
pOutTvalid : out std_logic;
pOutTlast : out std_logic;
pOutTkeep : out std_logic_vector (3 downto 0);
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pRxLengthEmpty : out std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
signal pCtlDataOut : std_logic_vector (7 downto 0);
signal pCtlDataIn : std_logic_vector (7 downto 0);
signal pCtlOe : std_logic;
signal pCtlInTready : std_logic;
signal pCtlOutTdata : std_logic_vector(31 downto 0);
signal pCtlOutTvalid : std_logic;
signal pCtlOutTlast : std_logic;
signal pCtlOutTkeep : std_logic_vector(3 downto 0);
signal pCtlOutTready : std_logic;
signal pCtlInTdata : std_logic_vector(31 downto 0);
signal pCtlInTvalid : std_logic;
signal pCtlInTlast : std_logic;
signal pCtlInTkeep : std_logic_vector(3 downto 0);
signal lCtlAXI_LiteLengthReg : std_logic_vector(31 downto 0);
signal lCtlAXI_LiteControlReg : std_logic_vector(31 downto 0);
signal lCtlAXI_LiteStatusReg : std_logic_vector(31 downto 0);
signal lCtlPushLength : std_logic;
signal lCtlPushControl : std_logic;
---------------------------------------------------
--SYNC_ASYNC---------------------------------------
---------------------------------------------------
signal pControlRegSyncd : std_logic_vector (31 downto 0);
signal pLengthRegSyncd : std_logic_vector (31 downto 0);
signal pStatusReg : std_logic_vector (31 downto 0);
signal lCtlRdyLength : std_logic;
signal pCtlAckLength : std_logic := '0';
signal lCtlAckLength : std_logic;
signal pCtlValidLength : std_logic;
signal aCtlResetLength : std_logic :='1';
signal lCtlRdyControl : std_logic;
signal pCtlAckControl : std_logic := '0';
signal lCtlAckControl : std_logic;
signal pCtlValidControl : std_logic;
signal aCtlResetControl : std_logic :='1';
signal iPushStatus : std_logic := '0';
signal iRdyStatus : std_logic;
signal oValidStatus : std_logic;
signal aResetStatus : std_logic :='1';
signal pCtlRxLengthEmpty : std_logic :='1';
signal pCtlTxLengthEmpty : std_logic :='1';
--------------------------------------------------------------------------------------------------------------------------
signal aCtlResetRx : std_logic := '0';
signal aCtlResetTx : std_logic := '0';
signal pAXI_LiteReset : std_logic := '0';
signal pM_AXIS_Reset : std_logic := '0';
signal pS_AXIS_Reset : std_logic := '0';
--------------------------------------------------------------------------------------------------------------------------
-- PLL and BUFG signals
--------------------------------------------------------------------------------------------------------------------------
signal PLL_Fb_OutClk : std_logic;
signal PLL_Fb_InClk : std_logic;
signal PROG_CLK : std_logic;
signal aPLL_Reset : std_logic := '0';
signal aPLL_Pwrdwn : std_logic := '0';
signal pPLL_Locked : std_logic := '0';
--------------------------------------------------------------------------------------------------------------------------
begin
-- reset signals
aCtlResetTx <= pPLL_Locked and pAXI_LiteReset and pS_AXIS_Reset;
aCtlResetRx <= pPLL_Locked and pAXI_LiteReset and pM_AXIS_Reset;
-- status register
pStatusReg (0) <= pCtlTxLengthEmpty;
pStatusReg (16) <= pCtlRxLengthEmpty;
pStatusReg (15 downto 1) <= (others => '0');
pStatusReg (31 downto 17) <= (others => '0');
-- IOBUF is implemented
prog_d <= pCtlDataOut when pCtlOe = '1' else "ZZZZZZZZ";
pCtlDataIn <= prog_d;
-- SIWU signal is not used
prog_siwun <= '1';
prog_oen <= pCtlOe;
aCtlResetLength <= not pPLL_Locked;
aCtlResetControl <= not pPLL_Locked;
PROG_CLK <= Pll_Fb_InClk;
--------------------------------------------------------------------------------------------------------------------------
-- Instantiations
--------------------------------------------------------------------------------------------------------------------------
BUFG_inst : BUFG -- used for PLL feedback clock
port map (
O => Pll_Fb_InClk, -- 1-bit output: Clock output
I => Pll_Fb_OutClk -- 1-bit input: Clock input
);
--------------------------------------------------------------------------------------------------------------------------
PLLE2_BASE_inst : PLLE2_BASE -- PLL used to correct BUFG delay for prog_clko
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 15, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 16.67, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 15,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
-- CLKOUT0 => PROG_CLK, -- 1-bit output: CLKOUT0
-- CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
-- CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
-- CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
-- CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
-- CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => Pll_Fb_OutClk, -- 1-bit output: Feedback clock
LOCKED => pPLL_Locked, -- 1-bit output: LOCK
CLKIN1 => prog_clko, -- 1-bit input: Input clock
-- Control Ports: 1-bit (each) input: PLL control ports
PWRDWN => aPLL_Pwrdwn, -- 1-bit input: Power-down
RST => aPLL_Reset, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => Pll_Fb_InClk -- 1-bit input: Feedback clock
);
--------------------------------------------------------------------------------------------------------------------------
-- Instantiation of Axi Bus Interface AXI_LITE
axi_dpti_v1_0_AXI_LITE_inst : axi_dpti_v1_0_AXI_LITE
generic map (
C_S_AXI_DATA_WIDTH => C_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_AXI_LITE_ADDR_WIDTH
)
port map (
lAXI_LiteLengthReg => lCtlAXI_LiteLengthReg,
lAXI_LiteControlReg => lCtlAXI_LiteControlReg,
lAXI_LiteStatusReg => lCtlAXI_LiteStatusReg,
lPushLength => lCtlPushLength,
lPushControl => lCtlPushControl,
lRdyLength => lCtlRdyLength,
lRdyControl => lCtlRdyControl,
lAckLength => lCtlAckLength,
lAckControl => lCtlAckControl,
S_AXI_ACLK => axi_lite_aclk,
S_AXI_ARESETN => axi_lite_aresetn,
S_AXI_AWADDR => axi_lite_awaddr,
S_AXI_AWPROT => axi_lite_awprot,
S_AXI_AWVALID => axi_lite_awvalid,
S_AXI_AWREADY => axi_lite_awready,
S_AXI_WDATA => axi_lite_wdata,
S_AXI_WSTRB => axi_lite_wstrb,
S_AXI_WVALID => axi_lite_wvalid,
S_AXI_WREADY => axi_lite_wready,
S_AXI_BRESP => axi_lite_bresp,
S_AXI_BVALID => axi_lite_bvalid,
S_AXI_BREADY => axi_lite_bready,
S_AXI_ARADDR => axi_lite_araddr,
S_AXI_ARPROT => axi_lite_arprot,
S_AXI_ARVALID => axi_lite_arvalid,
S_AXI_ARREADY => axi_lite_arready,
S_AXI_RDATA => axi_lite_rdata,
S_AXI_RRESP => axi_lite_rresp,
S_AXI_RVALID => axi_lite_rvalid,
S_AXI_RREADY => axi_lite_rready
);
-- Add user logic here
--------------------------------------------------------------------------------------------------------------------------
in_length_sync : HandshakeData -- synchronization module for AXI LITE LENGTH register crossing to PROG_CLK clock domain
Port map (
InClk => axi_lite_aclk,
OutClk => PROG_CLK,
iData => lCtlAXI_LiteLengthReg,
oData => pLengthRegSyncd, -- synchronized output
iPush => lCtlPushLength,
iRdy => lCtlRdyLength,
oAck => pCtlAckLength,
oValid => pCtlValidLength, -- indicates valid synchronized data
aReset => aCtlResetLength
);
--------------------------------------------------------------------------------------------------------------------------
in_control_sync : HandshakeData -- synchronization module for AXI LITE CONTROL register crossing to PROG_CLK clock domain
Port map (
InClk => axi_lite_aclk,
OutClk => PROG_CLK,
iData => lCtlAXI_LiteControlReg,
oData => pControlRegSyncd, -- synchronized output
iPush => lCtlPushControl,
iRdy => lCtlRdyControl,
oAck => pCtlAckControl,
oValid => pCtlValidControl, -- indicates valid synchronized data
aReset => aCtlResetControl
);
--------------------------------------------------------------------------------------------------------------------------
SyncAsync_oAckLength: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => '0',
aIn => pCtlAckLength,
OutClk => axi_lite_aclk,
oOut => lCtlAckLength);
--------------------------------------------------------------------------------------------------------------------------
SyncAsync_oAckControl: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => '0',
aIn => pCtlAckControl,
OutClk => axi_lite_aclk,
oOut => lCtlAckControl);
--------------------------------------------------------------------------------------------------------------------------
GenSyncStatusReg: for i in 0 to 31 generate -- STATUS register sync module (from PROG_CLK domain to AXI_L_CLK domain)
SyncAsyncMultiple: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => pStatusReg(i),
OutClk => axi_lite_aclk,
oOut => lCtlAXI_LiteStatusReg(i)
);
end generate GenSyncStatusReg;
------------------------------------------------------------------------------------------------
SyncReset_AXI_LITE: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => axi_lite_aresetn,
OutClk => PROG_CLK,
oRst => pAXI_LiteReset);
SyncReset_M_AXIS: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => m_axis_aresetn,
OutClk => PROG_CLK,
oRst => pM_AXIS_Reset);
SyncReset_S_AXIS: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => s_axis_aresetn,
OutClk => PROG_CLK,
oRst => pS_AXIS_Reset);
------------------------------------------------------------------------------------------------
RX_fifo : fifo_generator_0 PORT MAP ( -- AXI STREAM FIFO : used only for clock domain crossing. low capacity
m_aclk => m_axis_aclk,
s_aclk => PROG_CLK,
s_aresetn => aCtlResetRx,
s_axis_tvalid => pCtlOutTvalid,
s_axis_tready => pCtlInTready,
s_axis_tdata => pCtlOutTdata,
s_axis_tkeep => pCtlOutTkeep,
s_axis_tlast => pCtlOutTlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast
);
----------------------------------------------------------------------------------------------------------
TX_fifo : fifo_generator_0 PORT MAP ( -- AXI STREAM FIFO : used only for clock domain crossing. low capacity
m_aclk => PROG_CLK,
s_aclk => s_axis_aclk,
s_aresetn => aCtlResetTx,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => pCtlInTvalid,
m_axis_tready => pCtlOutTready,
m_axis_tdata => pCtlInTdata,
m_axis_tkeep => pCtlInTkeep,
m_axis_tlast => pCtlInTlast
);
----------------------------------------------------------------------------------------------------------
AXI_S_to_DPTI_inst : AXI_S_to_DPTI_converter PORT MAP ( -- converts 32bit AXI STREAM from TX_FIFO data to 8bit data which is then sent to the DPTI interface
pResetTx => aCtlResetTx,
PROG_CLK => PROG_CLK,
pTxe => prog_txen,
pWr => prog_wrn,
pDataOut => pCtlDataOut,
pOutTready => pCtlOutTready,
pInTdata => pCtlInTdata,
pInTvalid => pCtlInTvalid,
pInTlast => pCtlInTlast,
pInTkeep => pCtlInTkeep,
pAXI_L_Length => pLengthRegSyncd,
pOvalidLength => pCtlValidLength,
pAXI_L_Control => pControlRegSyncd,
pOvalidControl => pCtlValidControl,
pTxLengthEmpty => pCtlTxLengthEmpty
);
----------------------------------------------------------------------------------------------------------
DPTI_to_AXI_S_inst : DPTI_to_AXI_S_converter PORT MAP ( -- converts 8bit data received from the DPTI interface to 32bit AXI STREAM data sent to RX_FIFO
pResetRx => aCtlResetRx,
PROG_CLK => PROG_CLK,
pRxf => prog_rxen,
pRd => prog_rdn,
pOe => pCtlOe,
pDataIn => pCtlDataIn,
pInTready => pCtlInTready,
pOutTdata => pCtlOutTdata,
pOutTvalid => pCtlOutTvalid,
pOutTlast => pCtlOutTlast,
pOutTkeep => pCtlOutTkeep,
pAXI_L_Length => pLengthRegSyncd,
pOvalidLength => pCtlValidLength,
pAXI_L_Control => pControlRegSyncd,
pOvalidControl => pCtlValidControl,
pRxLengthEmpty => pCtlRxLengthEmpty
);
----------------------------------------------------------------------------------------------------------
-- processes
----------------------------------------------------------------------------------------------------------
Length_oACK: process (PROG_CLK, pCtlValidLength) is -- generates auxiliary signals for LENGTH register HandshakeData module
variable count : integer range 0 to 2;
begin
if rising_edge (PROG_CLK) then
if pCtlValidLength = '0' then
count := 2;
pCtlAckLength <= '0';
elsif count = 2 then
pCtlAckLength <= '1';
count := count - 1;
elsif count = 1 then
pCtlAckLength <= '0';
count := 0;
else
pCtlAckLength <= '0';
count := count - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------
Control_oACK: process (PROG_CLK, pCtlValidControl) is -- generates auxiliary signals for CONTROL register HandshakeData module
variable count : integer range 0 to 2;
begin
if rising_edge (PROG_CLK) then
if pCtlValidControl = '0' then
count := 2;
pCtlAckControl <= '0';
elsif count = 2 then
pCtlAckControl <= '1';
count := count - 1;
elsif count = 1 then
pCtlAckControl <= '0';
count := 0;
else
pCtlAckControl <= '0';
count := count - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------
-- User logic ends
end arch_imp;
|
bsd-3-clause
|
5e004b6fe5f876dd02b46ff127dcc7e4
| 0.550085 | 4.069357 | false | false | false | false |
Ttl/pic16f84
|
cpu_core.vhd
| 1 | 5,110 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.picpkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity cpu_core is
Generic (instruction_file : string := "scripts/instructions.mif");
Port ( clk, reset : in STD_LOGIC;
porta : inout std_logic_vector(4 downto 0);
portb : inout std_logic_vector(7 downto 0);
pc_out : out std_logic_vector(12 downto 0));
end cpu_core;
architecture Behavioral of cpu_core is
signal bmux, rwmux, branch, writew, skip, retrn : std_logic;
signal amux : std_logic_vector(1 downto 0);
signal alu_op : alu_ctrl;
signal ram_write_en : std_logic;
signal instr : std_logic_vector(13 downto 0);
signal pc : std_logic_vector(12 downto 0);
signal writedata, readdata : std_logic_vector(7 downto 0);
signal status_c : std_logic;
signal status_write, status_flags : std_logic_vector(4 downto 0);
-- Stack signals
signal stack_push : std_logic;
signal stack_out : std_logic_vector(12 downto 0);
signal pc_mem : std_logic_vector(12 downto 0);
signal fsr_to_pcl : std_logic;
-- Signal for pushing PC to stack from decoder
signal call : std_logic;
-- Signal from TMR0 for pushing the PC to stack
signal tmr0_overflow : std_logic;
signal interrupt : interrupt_type;
signal retfie : std_logic;
signal portb_interrupt, portb0_interrupt : std_logic;
signal intcon, option_reg : std_logic_vector(7 downto 0);
-- Execute state signals
signal amux_ex : std_logic_vector(1 downto 0);
signal bmux_ex, rwmux_ex, writew_ex, skip_ex, skip_dp : std_logic;
signal alu_op_ex : alu_ctrl;
signal instr10_ex : std_logic_vector(10 downto 0);
signal status_write_ex : std_logic_vector(4 downto 0);
begin
pc_out <= pc;
datapath : entity work.datapath
port map(
clk => clk,
reset => reset,
instr10 => instr10_ex,
writedata => writedata,
readdata => readdata,
alu_op => alu_op_ex,
write_en => ram_write_en,
amux => amux_ex,
bmux => bmux_ex,
rwmux => rwmux_ex,
writew => writew_ex,
status_flags => status_flags,
status_c_in => status_c,
skip_ex => skip_ex
);
ctrl_flop : entity work.ctrl_buf
port map(
clk => clk,
amux => amux,
bmux => bmux,
writew => writew,
rwmux => rwmux,
alu_op => alu_op,
instr10 => instr(10 downto 0),
status_write => status_write,
skip_dp => skip_dp,
amux_ex => amux_ex,
bmux_ex => bmux_ex,
writew_ex => writew_ex,
rwmux_ex => rwmux_ex,
alu_op_ex => alu_op_ex,
instr10_ex => instr10_ex,
status_write_ex => status_write_ex,
skip_ex => skip_ex
);
pc_ctrl : entity work.pc_control
port map(
clk => clk,
reset => reset,
instr => instr,
pc => pc,
pc_ret => stack_out,
pc_mem => pc_mem,
intcon => intcon,
branch => branch,
skip_next => skip,
fsr_to_pcl => fsr_to_pcl,
retrn => retrn,
alu_z => status_flags(2),
tmr0_overflow => tmr0_overflow,
interrupt_out => interrupt,
portb_interrupt => portb_interrupt,
portb0_interrupt => portb0_interrupt,
skip_dp => skip_dp
);
decoder : entity work.decoder
port map(
instr => instr,
amux => amux,
bmux => bmux,
rwmux => rwmux,
branch => branch,
writew => writew,
retrn => retrn,
pc_push => call,
skip => skip,
aluop => alu_op,
status_write => status_write,
retfie => retfie
);
instr_memory : entity work.memory_instruction
generic map(
CONTENTS => instruction_file
)
port map(
clk => clk,
a1 => pc,
d1 => instr,
wd => (others => '0'),
we => '0'
);
io : entity work.memory
port map(
clk => clk,
reset => reset,
a1 => instr10_ex(6 downto 0),
d1 => readdata,
wd => writedata,
we => ram_write_en,
status_flags => status_flags,
status_write => status_write_ex,
status_c => status_c,
pc_mem_out => pc_mem,
pcl_in => pc(7 downto 0),
porta_inout => porta,
portb_inout => portb,
fsr_to_pcl => fsr_to_pcl,
intcon_out => intcon,
option_reg_out => option_reg,
interrupt => interrupt,
retfie => retfie,
portb_interrupt => portb_interrupt,
portb0_interrupt => portb0_interrupt
);
stack_push <= '1' when (interrupt /= I_NONE) or (call = '1') else '0';
stack : entity work.stack
port map(
clk => clk,
reset => reset,
push => stack_push,
pop => retrn,
pcin => pc,
pcout => stack_out
);
tmr0 : entity work.timer
port map(
clk => clk,
reset => reset,
option => option_reg,
porta4 => porta(4),
tmr0_overflow => tmr0_overflow
);
end Behavioral;
|
lgpl-3.0
|
a83c54c0133c14bfeab87d5dd8afc194
| 0.565558 | 3.591005 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd
| 4 | 75,293 |
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1_9.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When (mm2s_rresp = DECERR and mm2s_rvalid = '1')
Else '0';
sig_slverr <= '1'
When (mm2s_rresp = SLVERR and mm2s_rvalid = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
bsd-3-clause
|
90085cf1e610310dc94a9fedc1c7ae28
| 0.402441 | 5.080499 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/IF.vhdl
| 1 | 2,264 |
-- Instruction Fetch
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity InstructionFetch is
-- NOTE I think, too high a CPI may lead to the same instruction
-- executed multiple times. Problematic with real world
-- access (e.g. writing UART)
-- The pipeliner should fix this
generic(PC_ADD : natural := 4;
SINGLE_ADDRESS_SPACE : boolean := true);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end;
architecture struct of InstructionFetch is
component PC is
port (
next_addr : in addr_t;
clk : in std_logic;
rst : in std_logic;
addr : out addr_t);
end component;
component Adder is
port(
src1: in addr_t;
src2: in addrdiff_t;
result: out addr_t);
end component;
component InstructionMem is
generic ( SINGLE_ADDRESS_SPACE : boolean := SINGLE_ADDRESS_SPACE );
port (
read_addr: in addr_t;
clk : in std_logic;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
signal read_addr: addr_t;
begin
pc1: PC
port map (
next_addr => new_pc,
clk => clk,
rst => rst,
addr => read_addr);
pcAdd: Adder
port map(
src1 => read_addr,
src2 => itow(PC_ADD),
result => pc_plus_4);
instructionMem1: InstructionMem
generic map ( SINGLE_ADDRESS_SPACE => SINGLE_ADDRESS_SPACE )
port map (
read_addr => read_addr,
clk => clk,
instr => instr,
-- outbound to top level module
top_addr => top_addr,
top_dout => top_dout,
top_din => top_din,
top_size => top_size,
top_wr => top_wr);
end struct;
|
gpl-3.0
|
68e5f8c7656e77c83659746a8be21e9b
| 0.560071 | 3.593651 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/arch/PipeReg.vhdl
| 1 | 680 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity PipeReg is
generic ( BITS : natural := 32);
port(
data : in std_logic_vector(BITS-1 downto 0);
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out std_logic_vector(BITS-1 downto 0) -- output.
);
end PipeReg;
architecture behav of PipeReg is
begin
process(clk, clr)
begin
if clr = '1' then
output <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
output <= data;
end if;
end if;
end process;
end behav;
|
gpl-3.0
|
0ed8bd279ea7cabb76c3309fd927805a
| 0.569118 | 3.434343 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd
| 1 | 292,074 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eR4qd4HGf1lcYsNyKkGjA12CwsJ4kb/7y4QmcD7jI5Rqgk7f6Kt7cO7ud0U4655LraOUY251RmIr
k8l24szFKQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jzdxWfa/v1KbhySKveslV0h0sJFu+YsxDeLJ8O+p75gqFeAmCqRZ3qzTgTFtiYYxyJnqV0fmSgNA
xUpv3N95fXyZEYbe4CAGdbxxmw9yWdjurVpI5MoRiKvDz70Ep4us+nSzvkhPYmlv9tcWGJDIjMa5
KCL+rThMG4+CR1ws9xM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DciZZMY0X+fpE5xOQkXrGMXC836+DW/KDWdCccQSJwc9WnKVMQGwJUFxvHLm3S2n0RZgGeXUvlgH
Us2QR7xd5JwHGlQYmaQVs4SJRxQIpWLcEprBFXKrQyNz9YkRHG3ar5BmEQDV7TFknre7NrKXlV2r
G+Q47BkZqQMYRRVOUDpZOIbRGJtbr9cXVxWuuVE70lz/ePHMCaxINGTqA30qZpZ3UsLRotJW8u5Q
tp2hTGz2BZTI/imnleP2WaqeHLenkVDTD9EJKnaHS1PwanH9xzneCrSrpuRqTsO3Pytznzcy7SdF
/iY5Y9THKf7wXtKBtlvMJmDliBpCD/CByN9mKA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
qXxpOaRKXbXhF2ZhFvN4aImOZd9v5YjzuzuS3KY4xBLuE2QgQeIbn14/oyzsCeSOD95tfBZCf3rC
zAcLDPKOVhEWmL418OcdCB7CabLr51CY/NZ3WnHWQi2llQJVKdj87hI7ocFIWYHli4N90N9la4FG
V76y5aGI+puwmC9AvbA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kMpdI3JFYXvuZSzFDfHB3IiqHNXKZz8yHUgeOpGoj5/h0QNRoA14ThJVrV/mqFEQV+Vc5IT9nwDy
CYlIOgcCabFxdyuddWuPhYfCVFUTGgMiRs6tRLVtQKJD/RNUc7Ctmm2khBoaIEvjWPAcs22dbBUd
jizcWa6oFoJdic6DMf38RJeVeKxOCzoi8I5LSXcJOfb1d/ObP/UDmYkRY142L/dE5ThaE4Xu0+7i
UY0/VjDrB5osTr1uLPxieS5u1vLoxqb8oOeXDQZ2qUUd1DXQFCWc6jPvDc2zoxXmgG+VfQlwQdv4
gBvPqlpnog0apAW+SCTTBgQ3BNQO8sgHyKYuzA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
pFMooi/OnTOG1YU7JnxSa8mXvQWPWMiaP1HE74kwHQac/Y2xAPJPa3zjWG4J4GVGpGWRNoVZHmng
sDh3oeG01Oia4IyjPTkUH2dRrFcmLHk5MQedekKuuUyV0doF2U0xkQnBuch4yOV6hbWmoUFwNfKL
YXp2UN6hrYr/NRZN6kMcNoWQq+JtxWjAUxmSeAusajfJT5/2ooyzRRwcRceGKBSwciF8mN5SR4Pv
0pkXGAE/jHaFThHKlbziriz4IJbSlBi/ufYEc+M+T0PNh9WHL+6CbFkgsPwNveR501OMw4iryRy6
dB2K+XJgqW9hTXAcx0yw7afMXBTxfHa2w+NCBg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
Mogjnq8QHZs/nQrEL8FSGi3s8+Tzd/j2U9w9UVuE4kA39V1BPcqkjRtgCU4aZXN1Vw1pgk2eJlSO
mgOwdAzOBzKMbE6MSygVYwk+zeIQnZ2sUdOrq7PGtdGB6QOzQWD0/nrV36qaR/+IfxpzoDH1zRHo
zsZXZSMJY3lt8D/8NNu78Y+W8JC6lcDovAocjCMqBuD3L/gCYJIy2fPnBQ20BUkl7WCRoBudSReM
AlqHEs9tJ/LTFE+VOpEcOfX/c6Pg+8UUmNnauGgHO8cyF56JTVltPxv1pXlPNO4dWN7IG5u6USir
kf+JMDk1Sda6tB1auhvPz8vQfphheKMiyFy+sY9MwrWPks9xcRoyxEoPkXnOh3GBnJY59B+8uyJQ
qaywgNmK1VVOOT7Ae+jgU9LUvQXtTpl9LS3mmoZpxn9CuT4BAOGVfudn2RUMcFvhe9shWMkQ6sQg
+9F5rznN1LdhhuqlHSLTBcbqO+ByDCbBt1kzWkU8lJCMhuzTQsNZ7Y7WiODDUrh5CeAesNFQbr4+
axHYAawJIXRAzalSWwMoYpxgagzbl+YSjs091tRsVRdDXwiN/+8JdquSgkeido5LuPHtZDg4eL3g
Cgso4cRbE8kIc5jduWOY7HoY5qP6EsPsYwxr16K1O9oo0Ae/t2B2ygm/vnOjLQIM+k1Ao4wayFS/
mO5SGvZ0Lc2QSVNJnGbiruOWi6yOZJnSkDsLgWU6hFfhX/ev2RqoUaTDwY7eGhlwhe1n0/o0ex3o
P98lvG4eDjgVc7sgcCXnCIpX9/0hORmqON+jLl56MuTJEbUSyhXJif2/cj804PET8qcLM/qSTEwQ
VP88Ppea/IHAQdm8Smb8SmQKDypfxJBXgaXHKKNfAvqY97P0nX6KXesIzY/FTXB23Rh6OOWChr1+
BeoiapoXiN9MBmCAlGXOhYDo6BPPTsNCjye4ZmZuZZfVYloFDmELeCG1vpejIDFdoGzbG1/OKEsp
e2GORBtpEOFFyw2lYdawTbQbVKNmx9VBwn1lhpniQQScPzHM0L8Gy3P/D1nMRAoGY6lenBdB+xCV
kc7mU9QGG8uCenwmrhPpMNU14wGO3pJjfpNORRul+bAfnDE4ds+RH4uwoPt+vFQG2oQQ6ldw6rH1
1kOzubCR/on/tMchnH+tHwdMWNEFGl4rfeDlrFRqDYZsV6j04RNiP5cw12JzDyGAf/Pdsxd5eAAg
npZu065QYAK9fjppw7AJ/pMtrtAQCV0IrUaDuWo/vq3rHxVNUvFMunQqC5zjlRZ/+E9kfhJK4/Mv
ZnQc3dmU5zdsG9UNYMlCLszmauzkiXy7VURtHoXlBktt5nFPyRBC1NMDQbZ4nRl+Icm7XiM9yzrM
aXI9bPlYpEfTYn1YFyfXg8YJZy8YlqPGQ21o3oGgHilspNvbkJrBuaP8LoV1iwlWSvSFV61eHWiI
SU779BrVwqHbvPqVOPjGs0U0fecXTFFz6348VAmWh0zq/r4PDhPeNiL/mcLgQ9K5/0PZyvcagpu3
4U9+1DZBL58OgopYQGX3BBwDCFd6r8rU+55FDfNIc5s/kQXsR1YNwVFHaGeIX7a86NQHGgE9Gc0R
oVumyCLymjQDavAx3Pwo78KP8V+ZFL2hMwsbWku+XrPVtv8WVs/XTkEz6JWkeuoyFKq1gS00oNt3
2HC1VLijkIUY45qfKYfhUoAk6qp58EWz+FxkJtxxefs0S2EtaRUJvxB35nhA5xsWx7ljK6XZsDJq
fL8IUndoQQXIysGtNhYS9ST6NUVpMTnIlEzNFiIRsAKZ57fSRZx6xsmM741q/5wEfWA9ddbrCyFT
1nW9mqahqGo3xe1AROqdZncctZjlIZ8vndABbSXdJjtafboAtXkxVk+nckAp3gSApzvJgLH20V3H
3wQXXNSLDMNYqp6jwfJmc3QJ2hh64TVbwvd6HKFrxxRMj5UH2OCfLGeBN/Y7ICbyzrKPBE4pRe51
qjuwIAEW+l1E3PVVudvNDDi3rsbji0RbybOJUhkve0Q6KvHR4fHtxdxRMtLzUCDekPIbXzsnSfMQ
Z01biwWAsdduPQ07NxMHMuTNzgSopy2Bgp1OyDeVIIE/ah/klxRRLBVYJ7i1OlHyDEDyswrf0yk0
0I4tTXhH/oPk32qdKzGkuO+fIc6bqSlF8iPXwonrmeyA0CNQPRZgZc3kjJoYiM7aCYeHptJqL1sC
tVYcYcgZGSqlIdiISAvgXTNShyncDDl8o6qdXAXRM6vONRh91rrlIOMAGmKdB/+FQuNg2pYJzdiE
bDDGmPyDMade3IMe1AoYAcTNHHxQMiirXRmrdpuNOlxt+QOVAfVN2191cWDLKwXpCMuZxpXuqzUO
KR1pQgUMYZdnrSr+OQWOanxq531Gi06NJnOzDfwpPKIll6uMeKTxxm/uIL3kK3eM3/XGy3RQz0te
plK7YvqP9ekk7q5EWXMVRXvkxoepKv8Ky+CW7BgavBtqtyFdIdzWbhcD3VP8PNG/xsSTT07ccMPL
0GgSgxzTUZD4pMI1I7Sl2KvOpHdpMla1ljwzTihH4W+wzqw3AsXBybFdEVPvuhb+nljsJ74p0sbk
gYVziyse05eja9dfuIZGgB9ZZ1O5RmjFHp0uGNw1Z91lwjBQ88VXZaQtX1/pM256uZd++259y7DY
GZwSWl6o3E6cnsdAhGI0QBVWTIkjexYOjZy3ycGNbBKcpyn/Adjpc2ww+oSgSPI+IMgKhaeQbAz+
4VAFwTv0yLwvKMH3KgZAb/qTxXWn46zcvlOwq3zJCsg1o9nMXs8VX/L/cbZmaz3GO9EslGFnWSDc
b9WjV627l5y4E1IengYgTpXs2dZ9NR+FWerc1iOxSFVh5YM21oPyJQ5XLyOPT0n9yt860H1tBBIO
AKMvqaYY3bmQYTvHT1bq3iugLWlo9Uj4QAHj71bfySqPxaEuOxhLY6bmAVEgIAXHcGxXvm+XTznP
KKo7ijqB+iV2/OoaHKc93Bu1ajvDaQ/ZbNKF+KeTia/CaCiB4xAHGLzQ2TGlJwhZj38vEpvXS369
9O3rmT6gOvR0iipYP0WWsHvfCmnssve+Jn7vmro/ihqErr0H+Gtvo2Rx0oQb1BVI9+O3imEyMdNH
FYmG0MkYVIHEJb8E6FdnhpjHASWm2bvzWgoBWSXCZDG6HRiFVyRMWL0ej8AlHqMoJ4KEMbx9uC5o
HFzpZJ+TOChFRum5BYlQp3XS1dbSe4NKzz2+EvlwWMeUwILU+zpThulDCLtMunhlc4B6Rc0yNG0v
F0a9At9vdORr7PawWrYlEhSTA/N6IFrP/GZ6nizJ+k2jBhwsPDvShFq3MPS0zB51Tzw7kHpr75E8
mq8aqdzDV7jh7vbEs/BhIrUL1lBiA/jktsTWvjsYxCwwQPlrxB4npaLK2zH3gnEh0hT/Zt8WfUms
MuVeuGmL36WBEs5uM7blOdKIHEWY0sYP9LvKP50kgtRNqER0HiWVH2DAPNDj+b66N1KgijB0vSY6
k76o1s5GIXZwdrhPO29MDua74P8JvMzVoXKuG6hD/hmquQGoDf9hpsNlnANBFjJLlgtXQP9+XqI3
iU202TMdPX+Y5oUwOGDdgKwaP8RkbE42NtsaZ0/It+tz+S3gV6NzaR/k9GLb07CBz5D41oLxXug/
4l2PimtwISqMGeDoJUIFeD4JuSBD20ek4iGOKJWjSiaHOFwNTSkezVplZ1dww0x4APASBT1l17IM
CKBCuecKQpMf/K7hYKrUvApTuBJ5wc7mYSqzFyTUY0u+eHlx2zfHaYYprlKA/FCCSMwWz8+F3ADN
Z20wMiPk0cDNahJUhtRdt8jsZYpYxm01IDEQC66SqxnQVMLWv0Nn86BhQjTjEXbX3gxNza3l/OkR
jpvb0H0vYIjJYhYz+6WiY6VVD0jC1GmdsjwKjXNDBbVL5sXkgbHD6shoVB07VyF0G1PHkXsu30qV
oFhei3g8+LyfV6ms70XFmC9bEu2sZTMWU8hv9lAhOzhSyqVbS7NvsWqQvQ7Ek40VFREUYrRNSIWE
OylpvKFzPbAqaFsUgCfHGFzQcYZl+dkMkCW18K/LqeeMVtHhEDGvtTCsRCYichAEFfjDEi74vo9c
nzjdisYN+CjRQrZFLz4ne0n8/IbuXLfc7f2fuoILeDX8k+ZqWUlbw8xrlEKzcnttbOPRpPXBcJC6
WHALyGLXh6Mri2GkwHQICgjJcJUHYgofydsg4CygaSyl9A1/mEao7nKmhwfV72AP98UofBC3b38c
omisFiKhS+sfRWyc2dEmpU/NKmWI3El5wHMLKWrPqMpakbGJnd0JocYLJZhLr/dWIF2TLbpfCV0J
trgCqbsoy8RzNDVNkdQkT6WFkXcNRCmY0Vw0Z5buHPlP5u7JyonfJAh100XEDy3/2yC9sSbZyfzu
DIRNcagQvytoO8R1UVSs+fQtXgAl01TSLfoqU18fJym1K3zgu8s03aF2B0KS5jl6VtCkraRArfL5
iCdOr1F34huA2BNelEScMgsGC+DJ/kfA/TpmM51TC77s7KJD7TzHjkPIrLkm+bE0xGaTVgCqg4wm
IKGoao3JQ9uPh7zLfjSWwh5bmK7M4TobK7C/6JGBiZsIjZSALriRAyknHGEow0xRNntVso4h1VHM
mXyVBzQdq+mz1cTnIhyohlv2bHQ73pMZy6F6Y5xb/kzMGvu1asYhvJtMepWBzLrFTo0diInzmAju
K2+qKZykIE3WxQj1FI1fhntBdiS/AjEbYMyNDWL43tXagl1MkqYZIt7FaIx04xlPXIEFTw1Xxhfs
IoyVsZxuj4SDl5rAgE6lFx1f4fHfcovS/YxNSZ02XAzY6gGS2ErWhlseQ7VVctRupoChr0d1cbq7
m+Bapd5WXjcYfnIh7sOIMlFubSv+yYGWpPTj/2m9KBmZ4ktLJAi+oosXBBx5aql9Cb+aCJUl2Q/6
PuvT1tNZ6sA+mrMI6gdhSS6kEfk6/+CgediECjnrLD3joerKQcL72OR0qOAy2w17l5dCrUjE/ksn
mQVcynrRHKcuqG2sHQMZoTYQ5w3C/zwwd8jXdIoSkevRAn3zJs5Y8M77dDYIJ8w1L8IFKDpZBLh7
3iCdS3B9lPG18uiybNDyZzrdvhDaGVP+eIG/o556MAVu7AyY4AJU+l8yaJqaoeQwy2FzR4Ggdpml
Q0860rRQnoGoSMDaKnRsL5my5BtHFsb9MJLwLrllHoEEYxEf5qt7FJ3Xei7w7tkq3FLTLCMwUFjW
EXnutlAb2cQpesLv8ZSm7BFL2Em8SXKfP47PScS36pGWtyVvxEMEISssfPS7RrfxbtjPflW1MQl0
UZwXRlUtD9kGFT+vfzdFwY+v7n1VTC9KRhsO2TAq+yUJEj+2fuqTeiKLvSaQbO7vdhlJA1t6j63e
rTY3ZkUXZ9hyBOmDSLCUfsMYU4XzMC8XJFpikKNTBxzLwPzSAU7aLO+1QEuUReqMICRFq57OLs8X
dWlVJC9YTkzdZAq30x44SoWT/htc0xjKHk3UH/JbLW2ReBGdI7L3qOe+qO4q8u1/uetQ3dir0FLZ
WGr8Xx9FjGybclBbNT75djbTw34PTLuyERi7Ux4t4+KhnYS4DxBIPMPkrwwe3TVmkx7gLXMd5j1k
ctspKGUEw6ihNW0vvWsaCgoIpZRgYR+hO+Z+PND5zlJNGS8Kly0MmHVadlU1jzRn1/txHwvycAQM
ZwRho9a2oekfpxeLLim22HOEBITFaGy0tIyGwy+S00y8m15YbyM9pIe+g1wNQGGUVrz3LAfF/KEp
8kSgVXlDzQC/h2nplVJWG1hYokViO/z98vC/gM8sQPZEg7HML7USlQrDJrJUGI3tkmFd1Df1QVgY
3okaiMrq2w8QTlTFF/EiqMi8OgO8HWfh7kMBhzgNhDLBvGXl8xpJP3/7YNGxNRWMNoGcfrk7+7sm
YhosmAcfSfshWtx20u4OAvck4Y0+vdbgzE7MwUoB6XUpVHI9uSr5wxD7ZMnrWWqLonmnSlzwXbVK
KqamxE6p0EkVstPuk03MQgN0h0HnRe8Y0SghfQLNAkN7vfe4kaLQrxMPr3xhIsFgnT9FNIPe9D1a
bLWmKRxMgX/TABONYXt0zd6rAz+ssibl1dwJ+sIWlt9WXdvVZdrCyJCGNj1uPjzXNNVNqTEvUOkB
9xY47g8MIf58JYKxRJA9PAuNpTlbYLh4JJKoRVaO0O4Vf8S5Nyd/oLTaUYNpRelT+ytmqg1XMR0w
yd5eLSJN/CT1AWg7U3pBgyC71M914M0OgOJIP0/DMftJiro87lIu7hKXzkTZNsvvG+K0fu9OMTFt
0EMolMapf9Z0SbLOxXV2jjYW1eyf5KYhwqQYsgWfkfsJi7JpgM/HxpmIAXuQkWB7xxyzQNMpvAii
lwRtoAIAdl8OevlcjV1Mbj9NROjnKi4ilMciPC0Jn/JVJkDtAVhWYWrzFnqbH/Dez3NCWhLnL5H1
SQ8ehgNyPkd/RsEBf9EFAf+B9+bw/G8bK5LeRwkYBBNLZfZGe0TB6kqx1icRcT/4vAC5pk7g4XGp
0p1rT6J5TbVxuY05MdgtddKu98UmZSJVefD9flujLZ52GZWcKmAA9NNLsU4bD4H4KbiqaSfbu6R4
hkIk8IAKYlhHF6o+pq4EiHmF671VwFtNqneuMmuDXP3du2DXWww//znwv7s/D5q/AEywVmOaPoMA
bupp/n6Js/m24ELxcwI1z9t5VtYBpbENzY5NEEWfb++2rqrItC/GNBFy+tjl06sYmfMqTBX02fhm
XG7aXrQU6NHe9456AAi7NggcNHTnC+RqBZYzuFb1aCJdqW2WihJ9GWkp72NmDWMxoB+KG0txYn0O
nR/HhJ5kXCysK5aWC8dWzDenyNPD+S5L1sVy5Mu702YUhzfdAcyPe7j2VQ5xPQBnqDUxT1dsWSbg
wZC2frcX1ryBwZuyLwRQJZcsBtSHyqdktEtLZ6+ICg0FnFSj1ZY6kWuNzSlI9UYS6yEqx8W+daqF
v42XJd+EmG80aoV/MTVugN+P+mBDPRcSKT/gwSVLaIKE7IMVHDXqxFkErMD/wSImsA2VddhLIRyx
wdmdWcc38HfNbqXqOFgoAEZ4rkzw+fnC5p8JCGK3AzEU+hpLjf4g4h873dRwyw6n9zJnPrXSis+r
vydojN6IYPUJ8TZQ/WNSlAfxxbOx3OvIOYaWoygeJ4d+4YXRHvao0mU8ptmYIdI/So/YkiLF0uSd
O7WoZbxfIRtAxz7K0eUkOdJjmypWTTrWFeaXfy3iOHyTR6bVFjz0sbkidY1QZheZkNfObI6ovmuz
yaI34vieHhLC/iWhNq3N8tZo0dXgT4teZ5eolOOE6KHAywYpRNrAy4tpG2nczP3zncjGh2ShYhF0
X+j0icX1CV4Wyr+46sonapJO84jWgjTyWrlNSLeopYj2DOOukTbEcZHNrIosev7LdqDo8TtQxvp9
kvX8LnXsvzxZ2WPHr6GcTXceeSTlPqYc3P5QvGyPQGulVzgEf5ZWb1iup64+WVjgAIjcCbYtM1I7
QIokYIUwj3WSljWcR+oh+qzIjoVqMoLRuQtJJa+KsS/Z+heW+eUgQzXRhUWbpiSEuVkFEZSToaCt
vm582SGRkhh4PU71j0A5plxFZXW/jwc14bzg/wRn1Q4ekZZ1mwCxkLgMS9wzQOFySxyxhKZlMC1s
AAZsh63tMiJFGw6h2A0Rdugbg5oORsazM/9Jc+u5OS4uFRy2YL10J1H1r3Pe8WB24axj67uX4GdX
7YPMfj+bmw42h8HFFcTBQeahp0CK14VOrrNxvswIt+oocztmpdeIvHnv24oeMOP8lRzypSYxQCKq
RLOEIvZ48oMV3chy/FVcHPYldF+uH0kw4vSUcYffQrQc80Mnwi+4uoSI7Vk6QynWqm/9yf1Ja763
8fAp7N4GlaQVDaCOUF8uk3sWnn57oE7YSiRzBvjVWfY2Q4R7vbXO6YypuHPkNkFYwUA9nH+8pGq4
KS9BW2MaSfhZBBXLPkAcMKSLLjR2o6QTTOtzYXqe+Cyzkvws0Ptr4hhRhfRcGoGOHnIbeKO2wk5t
Qq6yHwWSEq9CgQsnu3udWIJgzU60g8UqK+HG1j+OYSwdBPnwQAr9Cp9JcGCPu6ORK9PLPsdLEBKV
+vv0CiQZsCdWW1xSTaf+Ce/7ULxZbI69/uyLFUgY1+Vh8LhSZX1irorPFi+US+p5pTekcSgQ51de
Z+VK4MuBjn1dYuOWcZhETYjiiTDSG1I+mda2ZxaRwugTq23h/FkXnOZuFgstTrPzSTxMVvrqdOma
GVJH2FFADZu3oZAAiJmzo1tRuHsgBSnxasRfBGM8XkQIJoWe5L+eLiZ4pk1JuqKTlFHiN11r8dJo
g3lfpkcdYdtyAvpYqqVF09qgjDTrCBdUs0BPnnoROxud7eXnKOafeezxWVCFXxNDrQyQ2BEngkQ1
lGAYgCVcPWASjW90m6CjV8ggLtkdZJwd70B3ZsRBb7clnz9NdDagRwOPl6eInnnUW4DSJR9H8VUy
jDW71tejxqkbZMhE8SsD/45/2YCfJKzZTyolHKVlAsdVnZ251lTupu5EUuDDShTH/lwXRUukpPsW
48YRP88pJdHo6V3KhTzrBdGxJc6Ujydu0mWmp9ZA9ucuyW4zEWwA0lL1I1+L22CxXT/qhDCfd3v/
1/waHD0JJil6CUjZ2ux/YOg2w9XFL6BrCmJe6u+thN83M1c3VdEw14HBv7VOizTZvoapTUjzt0L+
rbDxpZ2YAuJCNSB94B9jnbKCNFhhRnetNXptTzo/FP2lb3PdU0DZJasS8XuFrojPjr5oGCShuFKP
1T7uGp3SDcESfFcnEnQu/X4rXJmE6wp8mvL1ttux5q2qIvtZ8537RE/ApuIExuqKp0vlAhh1A+TO
tIuDh6Ajfb7WDmzX1bkUpi1FxZOXphXDTm55Fb/ITp8BOpzA7mT3su1fESN2FhIeNr/F+XX5g+U0
zVR2Mw3ew1r02HA5Iq/fBxhvicUXVjd8ZI3afxT6+et19Z++J+uhSOLkLv7F6qC+Q/EnfYLp+EMj
lkCyDWxUWKUMYDwJRuNsxcM/exi1mpNs/kesu6pVoJ5v7HpqbWZJpqhyPQ8+d1+5wmcPHdr1/s5l
sB8hD6c3StD7fRKiJYAAdC8f7Si2pmltWf+VACTqBn3/dZSalyHSQ6El+HPJ6uK3koNn7+gxVGsa
3QQ/Svjyfjg4XsuOUQxrUti3/7ie11dWj93rwyoTKjcDxV3COXo4HKh4+B1w2XuaBsVx/C/DHaQX
wHp4oIU0OMcmwUpvNgJS6IsxWJzRt2LCVvJNA7dYAmUlykmlVc1ALlA7iJW2g9o2JmJRsUJhkZka
RcoYQSvJ/09VIkTUMHHYFDKdhYQtbh+cGMDc1dHkF5a6lXIMRkY41aQIsBPSG7YLFzKwGZpzeqm7
9hlt6LqzrA1dBq49bdXPlUUHa8x2zQhBPsjHt031k7epKhhDdbuSaQrBIDl9gsVAT+xrMyp529YG
GaBNaMaCUg7yi3C5IGmd27bYd/PmFnDflZdGdvY3HH6F6VTxkiAnHsmYdKXfgx3N6YrkmI+wQtkn
fe2EOFv0fw3FRmD+wBASLoV4/maeE3AnygwovhnBuA/1Nyk25MSh+38iiG78txOV+BiauQO2IY8Q
zokDOvO21k8mLeqPCZ/ZUT+QuX34tHIg0fA9UoLcOOX+r3BbL1YA1QYh3JQhthR1QkJz+dN26lPD
vDY65KLkSOTpA2YfrCsUkK5YJ0t6e8yCVefPgylLhpVdjRrs6Sp3NdGEMA6o2BwWrfstGtzDz0UB
U3/jfnZH8EbGt6snaLpS5JC0vabIvI737op1FAZAWFPV9AfnZclIiPqbb32XUkoZsZYzrBW/eWvA
bRfOHg6rPpU5c99CQQbw1SzrwUTPXHoUnk62ezMgjMIOXUnC1pnwhY9JGfcOZhd60Pgm2kpQD5CI
Hj/uUEhNTe8vOCeve+fms8PYlf7H4vhNQ3vHJg2syphiKKylpk4udMfB9jVJicEobmDDQbu0xdU1
cxvM8DOe3unTvgb7Lpeic3bK3jUPIJxLlDAAN/as65WVYfvm8+IzXFpnqY60rW++ZTD9kJ8dU7Oh
CWWiZTEGotftigVxGtRyLVycinj2p6YWVekYSrV6h9WQVdG4oyS69nU2FuVudWCOJJUd5EgyuKUN
zSYLmC5Dr8+tXR2CZvUBqaJTyAyREDGCWGcqwiTL1NmvDFtJ72fqPSP71IDeexH/9ULO5dU6XXCs
nsMe8yNwqMj94cV4sja/3mO1G9O27CxvM0IX+yE63loLBoJEQnY2uUljRWelojaR2NZ+5cgSaHQt
mbkyUuX3AGC6DOsvaxxhu0rGjA3rW/UdsxdZ/dBiBJZVq8uhiiCzZxJSIfhNIYPiAFlzsWvQI4iy
/mFxis9sBHX64NxZZGU72CiXmrQnG238oQHGSIKBBHbADW7g5R3vXCuPgLwb9JGtiCzFGoIHSzoS
Yv7r2exA9DuFIUEDny5REDNe+bW/5C8JMXCWds2HbOotLrcT8zqdDYg3XjcptjH/5MwxEvTZ4l8R
qipaMmbvbuHwgWIw6eXw0ZxOrCt01S5RGkfvP93Bms0V7ij9V49ijbSJY7Odtn7BKjFG7PsYWinn
LWGJ5hsrTOkE3heLDePduCh06FlIhRX4hliM/QiC0vleWl9W+b6ghRm9fCr8kpGkxHcJBp4snBik
nXjntjVR82q+wCkw7ltM9+YVqQKrBnWpnfeuZCM0Wh8mnIeciq9ZzEMnwz2C5fGHsk5BArJ2J1vL
IVo+xC5Q1a8q96zBxdSRtQJBq5C7vBM42/RYXVpgeLyeNWb/1EM2NeqH5hsx7Hs/Q6RHmwyMsOqd
wyNwL2CW1TwWuo5bhcNhbMS4YhJB0aErHI/ibejMpoGSnBoDLy/4++Og+iElFevp5bEFVUFYCuuw
YQZsAnM8K9XBtflVIfHH24grTB8tVJVzWsdIbyW7WPxKOdDyLFVgL+fscy5cEDa/rp0BJVKDoYKA
Ihis+ez1AAPmszaGLnTphPobZ3wSIqKmSrV4QsoeL7kfJHh9ZhQBNulqMUpelb+kOQpP5NqNim1w
Q/G022ldWjKVgpqF6mkIpnJto7Lz6x6yhZTWEehoWg5/oQxYABLQvbKDHBnDNCoixy/+4I+tJv5X
5P0cr+pim6FAh9Mj4PgY1CkN1gRq0aJmpH7zr4X8ix95BzGGPIjtNECNwbz6jr5duow2XjOPkJH7
0yf7+xREP+a3gdKC9+8Nx1p+F3NNyPR21TPWxSAWeXkz83dLudLoXm5hhDQ1TS3zpozLU6CaQT+S
tb4t730XO7mWTJN6HeDmtF/7fhSLlOo8Iz5omrx6sxg+J5ILlWpcXNm9qIJEb1dpxoiXsniTHEPf
VaySpHfXyWWn5/actlszgd6EmmLROVxgzCp0V8AtuHY/MGtWLEMquR0vuvp6RmV9qSwoCPCqRAzH
MH4efVW4r5mL+heG8x/6bfQ5SjBtoou5yjCBFWjk/qAsM5WYw7kPg9La2p7BwzaJ3eqCkA+HfBJK
TFVBZwR4dT6RekFhT5ETFsqdX8vuhkX4LhIspxA5BfuKMPR+EA5MjRGWtYM3OxMq6W02Ou4HVwhl
c+lYM+QqYb3DRCf39A0u7s/yUrMIEBcEeZ/GN7IcfkTMqolckgvMlVAhxoiqCnwhH0FEfQ/5ny2O
iTHpSp2lz12iHqoooizhQhwQ03jqeyIzvTqtR4qni/9FW9VB6QIVqpPhDrtaqrCHmEQYyCH0622U
eG7mblDH3DjyLhkqLX0IS5HJQU65kO1ramoSEb1O5LEhr0HGHWVzGc/1w6QzZ2+kq/6V5seIdFhX
yLiIJuyB96xQmPIWIiyOLguSR0mtvOkD292I8s58+gal2nFTlr7z2Hb/xLBK53UeonK5l9izbWww
UoG51iGAIzPIa+ysxSnZl2UIkCjOsDaUhXFNhcRfFwoOSNjhhDmVhh6VeS3+lD2+OUNhb9unhWo8
zkjwVOQLafrx+/09GJPIbv1brtgNOUhd0VqWjMtAHt/iUTwFck7ev3kzW3EqMfZMB88LkcJQepLz
AoSMXDCAk/VZIhMrh+jvv1MufkbsJzLsyZoLyxhMhaPqRrPFphmFFKCwhXjQhhsPeGAYB7BX4aua
sciryDmhDJrUAEET9oAoL6l9AajCMpJqLi39/IfIAPpHpDDxsxgdMu8AGz0ZAMXg0x/Bcbk6/f1N
Owzb66GKrczM9sAkSbq7/82MW4npzg/EC9N6IUKwmHEiTLEnz28ugkrR4722UvxYqijUzoKpVJez
w+UuP0f8cXk0M4BsxxHh57YI22AoC5m5rW9Kpw1OAo4tnAKWmYiLn7Rh9qaNQVaV/hKy3OoBxPqp
CAsjlvvLaymMzEIBD3KaEN6eiSyU+/K/oSFHcTWTRw96AdMC7DgYjAJNoJvqhzsItLMht5U6BIvi
1S2FucFgA6h7oyvtoXwBCZHNE+C7gL0fw77BKzVtrzj4rr5CWLxc4rQeCpnUBs3bHUzUvQPF3LJZ
O+xOzGwqO0aGR2weh7FJVYlSYOA06w1dAJhGe06Dt6pzJhm7l0AqdoTIhbM+l3lajFhtW7EsPojm
pBO0SyorQxL34PmNieMZTJpjaCMNd9WROAdU8uuvu4fnAuvvGXthZHvING4dOuMDY+4Zg3uM5vRE
VYy446PrIGqrBCbmyGai32OncY+uc3q7ly4tvgEhMX/UqrR+P+shbCn0U3/PeN77jAfX/Cr5OgFU
kj1HJNYvMjvJ94Xd/nymXYbGGHsevQDvVx81KNTOu3CFSFFjft6qOjbAJIsk7iKPDNbLjjBcoxP+
FUd8imuG3A422Kr5v36FTDZV/aKZ25P0sX2gmaolk131cDcFKyo/Yy8E/mJP3L/2SzAmOa7/Jhok
blcGNXApuGqHI21BLaHsD8raXeNlbAeJa0ZuZtssobQLbQ2J1C4BwSACqPpzMjdCb6165e8MyY23
rH4Cwc/nVvFjMF7bV0bcyCOk1GxBRRbGXUg6WPAmxiunejJhHMxpb45KZqiRAk8jpxw6Q1I/0nDQ
pZgdb8eO/mvYTP/aE6ufhsiSlHqUNFI4vhoPOxqbnIkY+6KE7ZZtnQ2sny9Z8zicB07HPykEOlzg
epLDDIxG+V6L4ls8KJrcAcFZ3tyrvFOHNE8goyFjIzktZafkcPzhB1rQJKid3h+WovEQGV82gvlp
hjPXsgdCUw9OCfdqGp/zYN9R1jA7rt/0iJDUZEwHcICzjAXaJ1wuwIWb2aAZve9NUf18c2SQ7fRT
GiTkOfUqyUx5mHRoNy6R/YYjoCDtJ+lboO22tFUgAqLU73cR76Je8avFAPov7WNnuZChU0WZsQEG
nKNhb/apEnZ2SwAze0gsMFaMbdQ8mPgBNtW7o8tTOn5XRNmEovVOLcd/bKGeZQ4+J2Qw/K5I26n0
4qulQZjMFAsF99K3Ff1q4FHOlBXn/4H0JYkVmW7vIF3rUGXBwNy7zz1J4JHXlCnRG2/DKRXK5paq
9jEZxv1hwBrcssi1xpFACXbpupKsovJFMoS9fXWJ29xEnrrsxWDAhDUli1e/Avb6f6S6MVvrP3GK
Ug+i3T9YGgot4LFUuzCm3IwP1vaOAjwHKa6RueM+jgfwf9Pl/2w/ZZIMcJdBvBQdjZ1EkLsa509Y
QPqoFJ2g+jpU405x/6/MYguv5U2F6/6i4Qs+jvld9ofLe3JFmXoZS0Y9uk+LoY5gOl40i4n/kVup
Xx2n4mbvrg8FyO3wfFALf0BbZYactusPGX9Unis6wf2OBUGhe/fIz5phmPKP2Wl09pWNzNBBdhct
WBb29LjaIxixmx8t3XF3UtLEM1UTTLvCbqfbMNdIRvyea0J+gvSberSLwaC7G3qq6JVvjB3btHqr
xB0PlXJBh4hZyBf+3zaXm6v8lQZjnyVQMm2S/HYclDdEeWqaYOiQbK1xfToU9ZNe1lOgUTI+KFK6
4V9dPSwYbOIc8oQ2uAyeHVRPlVR35H/6YOhSy7T4J0EDigVwyuzUDy5WOzSScEOklYqGoSyWVqEF
w6ikF+o2uIK5AqRLdCwuZD5f6B8q/hYqdWJVD2r99eaaJoU9Dwf0++mdsOkbQIM2ooVC752vb/11
t0pmb2VGJKuTjGxYH9YQd9x+LPj2NkzLhZophzNJMewSZUTPIOYAkCJ4/+I6NR4Sm7Lb6THP/ERT
V4tDPbJ3W2WOwv24d7qrhiB9X0iljGrFji9f5E1srL43B67KB3XbNinnDcHUjoZs7aG+cmoF9iMV
mKe7FS30RRYPxOslzQz817uRXu4l43Ep3aGDwjbFq+XD/iNzSSLbR7tYyhdrLOEzyA4Jx1Plrjn1
F4T7ByCFQD5jbCIny3vZ7057JUsaab+s/v07EqsqZ9tIr6zmOzmtusOrRRT4Zne1/7HMwqRzMHln
B07Cb0YDtU7sYSPCYYYauRiFeprgDEgaWN2xpv05ULvtTRDjOEGRaqlJZLAh1bEdwVW0LtFzmh+a
dpZBbCO8yvwzHEgzb2Jqc/VFQRiW1RiPdoHZSCtHHBl4XtTrXkaEdaBwF0K0Bxym2PeDtZ+kvpZv
6eNiuX7a8/q71WGFV/uSTuGjXegIS0x+AOLb/c5SopnS0CQnBEdokPhpX1NwdsI6wfJnQwzfMHxr
lMcC2qpfP//tI3QbRShg3TQDbcE/gcreF9KE0FGGGQGUAV5NHr0R6xb+Ju9gFwEvadmOdkvFTfJD
TgFrRgcouK6EUYOWPM6/N3T+isX7g2US/LQ+osXNLkMLhYkd6/U5B3xNr7GIiB/TH9eMSH392cqj
O0hBwZn/HxOHi39x38rR1pqgIGReaWfBc+uckYB3lVUVP7C4/cC1NOiIXlKaUJBKoG53DSpg/fbZ
n73r85okTIgLuEWnB7+CpFgBXn6gMwcoeiw5rN3gVcJsEtFtXkNhoXuzYg9xf95zFD+zTF1qN05K
7dgyvY6AIwmFP8WRqR7uS1AP92SObl4wb4TQxXIe+WllD4QUCptZktaw9of/6OrDgnwZrhZVZB0F
MQrff/wxC7mHOtcFbPRpwy1GU1uWUai4xRqRuJRVjcoFFxK6i7gwsfbnESP+Q8fmRox1KkvBR00T
ZVZxJ5LEt8EKFUGafMeZOW6ZuuJtTPvgpckyWJDYDNpEcZ2hQ+qlgf8s3Pq6P47cEKy5sKxjHKJ/
xiEcfXV/qpDEbsYo0kZ8qTmAnfDhRARFjUO1x709t46cTDR1roKzfq7Hkvz2TsZA1WtHF+AXgfcP
u1duyCb4nTqyWaaplLJ1bAnLpddebhZpzYFn+cgTiOOBHt9ILrH34Raoc7CCAFgCahjxeCuL83rV
i90BbzWMaqolP7o1rhPjNBNh5ZoSyymcWFTbZ4k8AopxSXENqBDW/JQhm8uBCOrFWLXoPNZlsM+s
UwrWwBlWoutSrM55YkdAQ0LP/0RwXitWBx3ngQAbremmkmx8h3DZ8VgSymwuV92fxCVE1Pc0wmwt
0H75pMQhn6FUUXVMSVBleiyx1kUf00ydi24tw94Oni/QPuazN02z98BQk2hmcDA+pHtWbqn81FXr
Rt9tihJvZW8kvRrpn17QIupT6iAmHaqrvPcEJUizG0V9OGg6MYrR9hyPVcMrWuDw95weiiQx8u5E
9+wlKI3hWfu5kBMjAFa0q4cdvywTyxOIMhz7goDRzgtU6mkZPrn7QY6aGFEaZNoOLVxAq87Eu1v4
1rGDpVLRhQNVP8AydvN7Gl0eckNr/lQFlPl4ZO9JQeLhDYcRAflYc9cVMwu0Br+t0S7WDhMySjhP
AVuAro9uHCp4BwK2ERdzefMb8A3DUdHwPs5bFsUVqSrdpI2HNIehMAfN6fzFiu1kEpTYo7MCTHt5
VKOqs4+Jiz2OQV1oJsY0tbU7nCessqPCxBKj7GlVVC+TcS0iGBlMe7ICj4ipkrJFBGajSbBoTs29
RTiGIpErlI0bhcVvBeaq0xhQ2oFjov7XFwkRQPNZjhFq1NNyJR7+5TN/Sc/rnaCpmEpJbSQ0bcxe
STzTZhMlXMwc86vOze6SqWjqqLpUt2RsnSZe1PDYH7hmrFWuBg8/f0zijTelPk5AE8VjrMJW4y5g
P9Q1xG6lqbLwv0nVmzIY4z+1V6EO2vWsPbyEKbwC8869Ydou7fAYvIiXrmPugwS10uRoLjuBXjtH
hNkiJU/GIm/9DEbi64MDC7qK9A6vI9unRf4fGeOTK5VIivFd31n2Gnzpi9/D/8j/uH1RtkIfIXj5
BkHNQ5yJJSXZfbR51Z/pFTNca/smDPmD2RKTgIVKzl3JeYmmOCIReWOma6c3IgweS3UdNfxmUVOM
n6iWv5slWD8wCSXryfF3zexOlSVZ9RAbu0JsYkIDCNcY/I8yBkIbQN0Kj5EhluaH+9CP1SeUdRBy
lGVwNASaCd5sHaKYCQlu5grKrOQaSCnWYPyY6eErRU6s1ZCicazjN8uh2F9x9i0NRPseMGqNgIGn
dompURG8B/VhVebjNZf+xwiNXeUKjVxRZ70ruqwbBbtsvdZftXT2ipELqc4JcQ1yejxLrduzEFlN
hM0xw7bnA6bjA7ocSyG+ihI/RYH0P4lM3BqkSZykpy8G/QwT3RSn0FE1eIXYrlj4O53aY9yxjU/L
npObcenjMa3UTvVuScpiwr3IwCqnNQ9oI/nzgZAEMtaPXMBUM93kEuZis++3olRhWB0CytTeBAN7
C+oNsM6wFX3g3E6W/JYaxJuIgNHKkGJ4w62Qk4CMo1SRltYTBH0w45KrsyfTEgNguWeYzQXNYRoj
/qxF8MOSZyd1UqHeRrNQ6N+Rh76uuMijKCSD7ZxvRC49/gypvJvcW3ab6aok0bhCHS7S6rO5c+Yc
CXc+Ukst2vQudkQPBcB81lP468H8AasHVUiRa/ktyzpMj1H7Z9Fp8E54Dv6tWFa3uJbHzwP2JAWS
jMFMnHL84md0iuZcuBsCmM4CqwtmMJRIVVIb4dabAy6oMyqlMp1ONhIs3ut7jDxubiB4gdo47f74
NQe5yFTQZG7rRfcTQT/Tu0zwtRJ4svyy3Te/F45QJq4UlfOL7SoqneetUnDxsfGOS0v6dZv8W1w+
rgy2BzvcxDiob8WPvlCnKbx2PZuVtAJaTOfiTUEagus9Y+3upek5kAILJs83PgMhXtv0G0JDcPjJ
epi37+brXf9QGNBgN+crQvLIKwRGAkX81/3EkOMeYP4KX+9PSjpGgKCOR90CDyckVD0rQVABBox+
joQkktA/6egacWcnY1L0291u+wMtPoQYtH/WNTi1MK1S9BxyYtf086iXJZ6bcW/3yih5svSJd80X
PW2HviuxBKjzrrPF2I5CAvHyVH5JYUtcHaiApWVH4Xwo0cuTjLwbqHS3ZkSfZtFTQvtP6Dz8DMVV
MQfYiI7YcbxAEYvFOvBYUr33rrv0OKxUTPivLpJ9KgcUgq4OENYnPrkX/OKU7dL0VfZVTK3qQu1B
CWM2UbIauwkAGp6FXAOeh4uJBpdeQLGUlkX2sriP/Zgq4sy4E5QU8JwffZRnKCTow1iDo0J1eIe7
+FAb3jsgNZi6tb67NvipZ0SmNGL73silaix/8kZ54m3LRadtkdrdl0k/0dA74cQwfOwobpR+BO3U
bO0294GEPxhl+wKfa2nc+XqVTWfjzu8OTR4/MZSPairPTstrpR39Bs4lyRryuAizt/MPlesO9+xl
uGdzMTJ4pkCGwlDKlhPPcmtyt3K2impknBueccaZ2URfYTFLEKX4nmTsgtEAro6dEUD5Y5phGSdX
pwPVU0rl6iV5/TP7Caaq1KH0nPD3M7sJ5GOyKu/5PKs4lmJ9/swmGIdTHizYjcpMsdvzU4kKdGl4
1ow2jocD4q0311ch6PhwJoiBAbjjCdNwMvF+CAsl8IV9Qdx+PcFSCbQ7ERtrYrCtfnx+3YVPzUrH
nb7hHJ22CsTRy4zJnywAB6R0IkmAv4DAguhbLlnva01JUUkXLUyqazuIOoTKGcBqdq+7VljZ50Zz
DaAbAoU6iO70IzElHmjz1YW6REARsiCgrLS4Tdu2TTO3fyJqRR7Oalx5fLBp3q5KJUeo9IK+A5q6
Rhz0ewVon0/AryyvWfNGdVCMCr1xvrWpjvpUP6UpVCx9DAl45gux5LL0vTdD5EoHtadqY27yFgFQ
KgEhCovvI8TapyiN9OKAXlvDTjcK9U+5OgpPrvvpn1iRt2N+a7zMpjRhi7XAMWqxmsjX3avMB8v4
cC4HOolXfNPYNyxAcg+B1zNa1PdqYoXe33DtINQCVzPYuTaze/56i2Y34/2CRGOnOLWsNwZ9SKpL
rx/mB7z3A9o8fdHTm7h8Qxofl0OTzvEGqUxXf4efXhGF6D9zqXPTN/sH2c254zeL44qm3XT/fFYj
E1EiAWO2niuS4RHoBOJboBLttI2RHeZVpNmtzWehX1Aqdyy2EiVYZistILnmgEM0I6gAAmPUGGxO
nFKuiu4d/gYaDMj/Oib/bDAc4LiLHQfr6EXMWaNX/VnBUmKgmc+u+TTFaZOrRsvB/D9/tmjE6hgj
8GflRYU/Loqpo5ZgrI3MpmOggt7nTq7rnLGijveFkiobi91+aguvEcTNezJvyhdVbOJGolEIo07s
QEfs0VOkRxzMW3xCpnNv2V+VAHL2+NdxT/kCY9jmhcJf8RcREj8+0wAlqoKCkw5OlTz0aSoLcA4c
Rtf1ZoCIYfD+hjDub8Ajik6WnO53PddgJ34SQGRvA6/Dz0Ti/MFvIc8nEKC7lVEVbVMwNNNxy2NA
1TN+AgvlebW37sC2CUmkMzwYmRfMl7gm95SQtAJkw2v7vz7dlAk+JXI7zhhCcWjZK+mxMF6rhfAu
mMWT6YYNIaXFqMs2YztCFpsqUtWGM0mdm4tJBygOZJOCqn6ViXEB0pqrC/mCxzyl/1tL/fWR9M02
78G3EUWrQxmPEL7exGL+g9H7D52I71FNe/RTH0QwJlW6I7bynw2io+xaGKZoVprRxtjRHog6Zmql
AgxP2WHNyZo6SkCJbGokQuV/Xwjpu9L6SAq64yiceZiFFNjiR/FtvB3RMEUFfPMnU7kCJxuLqKuR
YxiUMQk3dmEw1ENUo6JKr1LYDS7/cUmSeHGP80gwt8mJuqTIZw+fpbpPiMWsJNsM4atF9mguV/Nv
x9lC977pBew3ZkQn44jqUbgxGxo2YNDiKOkgRwmRMD7JeLFefhylWXBZwCdt2MOffjbHbZ3M0bGu
bsh2Jk3pXK/+963F5Lq+dX1S3F0/DzBnz27D56pNw77Ca66VUHM8jXlDFCX/ABNDgG9eFIuU3bci
ARIV0t5Gq2Qgm7oeyo7840NL+SZh4RZFlP5YlMiXFwZmCJLUuU0oPfo1fMzf24mvIoZHkQb2+1mY
Zu9qACNEhQcYU3PR0L+HUIb9hHsod3NQ7dcm7QdDF7ev2lqymVKB+Z2rqnLMJOuHy71i9CoZWlMG
vjU9KcqAXAXAP4UuUC2cBfz1CvFGpEFRIAVVmR9lJojfJwTGHGh2mqHsZqWtelexrhMNiMJl4F4V
xXz9kKGv3xUqWE/aLPVUSCpvsd9j+ec42ifWI1FvNeT9h5l0JeVl+0PN5wnUL14vXHQ9jDLn4SZ6
NtK5Nrg5ON6qEdqwNXwuEyrXKVjENJ5F7J0fv6AFHZ97d3W0OwPxvg3PJZYHiVpqtsG7WiuH2iS2
yA6dlBeUpRe6ce7MEROFKfn4Jck379xmw714sHdmI8axfvtFms/znTdYJulqDi9ppiisNFPiUYSV
zCgSJtrk679EY/H+yCisdENcg6cP1gZg5wCbyaD4p5xHSGZNSga/z6Wz53x2deldJcrdxS8B/qht
bJdOORyx7qFq6Fc/hgT7eV92arVvZgeM18J0cW/cQpi6SM40KsomQtLuMaYWbdtQiKG//xk0MRWU
FKrbyO3aU9NQ8BhKa9PZY6jd1N1Pae1JyRwBi1/ytlmNhE6EVTIujvWISJw2Vzc7YUgSPNNFNj2m
v06yiKCDXdOY/60OGxENNa/84Wah4eC51gPU+zggava4mKpwoDM3ES5VXkzTKVCX4pA8K+6rTlB6
EFymZ0DsCyUbnsg5gXSiMGkS899n00m/xFmrggrLfxItqqNu4hf5U2Ci9nTezEkQoJ68P3Y88OFp
GhBmTkKWaHBhtYLMhbkrxfZqQLRwfwkjofHMd5IEdF3QVvJj9xapz1F7GoNTspvd+PwKBDXhKcRj
401xd2bTfzJKKif9geZc5xJH09M86As5WCHfBemM4wlqXdMSVG5W6gEszyoyYRAuTpSU8+1MfQMK
X7ndyoX23CAeZ/33DSIN4aEGB/ZMiD0IfMFXVuIJ6pCyFsFgJjtPQ7cVPHuEIQKfDzWOcw7jRPz0
lUOCXmuvF8FVBEWmekL1aQwf9D+SnnoavxYahIse8TqHECxVy+lJaDIXouulzioDqmFkmcZJil+N
lfb59Sy8xWWQC/7KVfAEyzG/RSAElYfyBM80fSOunpBu7AL+8n1tm/dsI9p8qGd8JohK3Qe/13ND
s4X3CiEuJ83Wn/uLClcnfhBbHc+knWDB6ffdpEtBAHDgHmeZmHKBoCFH9S5ab/TgySqa3MAy80oI
GHc69xWCusjmBeczb1MJ9kvaQec7FHE9pFN04P5pQwAV/N1H2CI+qh/8A0tH2Sb8xeteZjgJJHpH
1CjPYppqM0pGVhDwbpuI0c2vPeMi7uZyKBDIgqhWdkV3po+xG6fohO/I2JuLsDe4Xa00r9BrgNBT
9lNu0u5XszhjqmnJP4ZBDWdLmKmjYVPSMOJVFsnfJERZf4mdieik1f/QuuxR7Mtiejjfo8ky05fz
QgvUY295cnV1guXALqPyjG3vxbOiQlm1znGaDfwLv9xFfF0SvIAFd3rtU+0LBkBbz0xOYJPHk05q
m1R5oMWSbdKhglqAn8/BGJqMp8Tqj66pWrzcFxi3I+Pa6X9p7jKhKzfPpAdbr6ZFF/Ijvx3yKEUh
91ujXVH1fAdbK4Gb8zkhMlVBitA7m2848aLC0BR3R1ePXa4nbEA5W6wJqt8Mk96eDtbcwiGIDxFC
Us59+hLTbMcNPvuy6fQIf8c8fAqS0RSSdWxLj3C31CPIY5y4FikeIKp5l4AHBd1Zgs/78dTkyDYY
aXaDRwnNmCeYTZD6aSfVc1aZVlkOoVclzgizpWYhn9F/3TTcnAjp62RaMZAq9z1TrdX9pt3bjvIv
0/g2dxF02mReuFQPqHPgoP21tq4XiP6xzDCWz3fV4OL19YN1KBS3VkEdy0gMH3jOKA44qv5n5JLO
3ejvE9PtafPWS1ywrnRV/DPM8sb8UG6TUEuJzvJO04GEGhq8x11KhCqVS6ijsJOHcq/9d2mzkQWP
l7CfMcEY2sRinYBIf0LS9HH+sa7BjQkNmnAUAYvr9MKituqM5e8J0rYXpOSmBM3Y+Ya/hNGuor2u
9vMP8pv+Eut+oFKIs3aW2eABeeTAmX7lYJxg6xU1CfcqcCFwlA+49J26nkp+dtUAfysXBLg64xOi
DblNAFpJ7msFbFzR7uAEuyjpiRwJh5Qc/ljHpQwIcK3yOzxtxTOk8RpvA5iMMHjDNI8NpjCbbVfc
y9528/HIHb2gJUavmeDm8MLyaEMGQyGcyTlx7HnS6mgXoUXdoHvA+TQjGDBhNvBQwa5n5YyEdYNS
Ij7vcA9ei+vMh/+qOD7Z9LLMoaKk6fRlXDbnDmNg+oRasZ9v/aZHFZLBzh5GiHyTbef65k3pEi50
cEngjKnWHiMy/CUKdA/vYP5a7Ev2GoPDxzUxPWlQJ7fBSy3jl3IeXNa/4ZEAZVTn38YA1o7H1hT3
DFrNfFBbuXw2xvCYOnx5gXr4t9IJEBZ2jDbu1HPP+m0cCK6Y2ES2bPtNirrCuN2AudAlk8EAWxkV
zSCui4QAiH4jzswxVfyR7EX1NpYjFQk7kS6cXo5ezyYz8F6PxBAfvraNquer+WRAnVlPI8MyVEO+
VOlywTnPUkxTFVpB6lVFJ+TF8pJj1wdJ0yM/0pYfjboC9I5pAzjIYG+eslQiPk6x/ToqrfQ7KI+U
qTeG1ZHwhllIeDP8AQ/TX1Ix14Sy27z0/OKP3DQLrsx8QcPIEBTbmSFWDGvwLtbA0zfpzoAiQsQd
KixWJmvG1Uhy8aOPvaEx57HMFbzw/wVWIJ3v7yV/us6VllkqJOp9dIsMUJVKDyeVQci4vfGMif0y
gL7nliPnrvV7mwA4OIjDA4u05BHQeFzpfzJmZXLrkgrJHzmJzKepldWDZn3DgziN9dkGzgeFvqcV
e67/ZgByZfS7Yfg749sCxXYxLhWm7tId87thRsj2amA+3+Jkf2T7j3V7CJXwPNzO/8L088DZ8Qdv
MeIcFWFMdojQ1K3PH6SNuVhWlmWlDzj65OyKor2swioC+JV9RHm5TCGtIJFVZ2P36yaVdH58zvvZ
EPLMhNzca9/31V3pOheQEkO8J6wgxKZMhFxPiPWRrBzNoRGytBjDAqy1LlNUtxKg9XiUSzboFlS6
PMFS41UC30ellpcRYAZ/0tMVIqxMhGIelCteCTMHAWYM/WksYR+LToWlelY1ThXtnSWvFjCDh4hC
Vyg0m2boRnJpurLF1quViuQSR2JrRT9lzRc9gFdEXcYhE9Htl5xrbf1/Yz+VqkdVMVEBnQs4d2bJ
F0e74CMwxjmppbmLLF4ic/55et5y1BqiAWyf1uzRGf+e1LUvRsJqWJYmm7c4mTCd0c5+eafYXChE
WR28nzVumiO/OZuyGBVxDclcA2Uwy2NP04FVQzbz3Uku7MgDjxq5nWp6hWTSFud1o//U3SlMRmKf
sJkU7yHc7hfKr6CCOIkCoBmnCOhyb64BbMC7ki9iGKpCS1jbQjeDicLaVs9mosMqvu9XU4AIDd/O
H4D1ShtoRuLzE0eWuANhp1xipbGaTErlocdMYbaBkA5ZJzJTJQJbp8IwplAwLitzZpIFyBP1VYPV
ZwhAM92puijGTskFLdV2jbFbCSnLZaSOOLmqPcbd3unwBNj7XnCvmcTROffkOm1MZHOakxeWewpA
2HsXtdSveJXOenrlh/WAfA3EWQyFyBBoECQ8ykU0sYgIc2Ac4fAOFFcoQwTbYSc6g4Clph918q40
8jscr27hHIUkS6iWnXwOJGk6Sj155P6LULYnhgTXr0TuAoOwKBcRIbzCoZrG2w4i9vzz5is41f4s
qmpbDsE2+QQen2TZMwdfN+IuGGK+Kt/USzBMyK2il1eUXgviAocoe58xxUcOZmOzOEEjiPqvreE2
JRBZBlh0ybWgJgnUaShZX6iI6iTX/HjLBNkVpJuTsj1IqU3QOwzQbYHqrwLQ6mMnSGwzoZJKhGWj
PWA6iyWVnx/ezJiUInx6PAdD9r7hA0GdeTu/BeTdmCWscPZrs3EZZgQHDA7LhK3fKAZymyC/qwdi
+r0M/1fzGlvRe3g51BKgLftMBYwvoYcdG0SsQ8PsZWLVZKj9kwV4CaidP371eaQRRWla8S3s6PW4
iXpIlnowBtEb9pGmB0HaJk1fbGNIfHbnA9XktbwJIufKlEHkvJOVsMqrWV2kqRxJCukECM373eZ4
q46b8ZhtDWcUKO5QoELTmcmO6CMvdQq6A7xIPPT7AUhmQl2i5Jcq5HFGn5PYMiN0yhx9+aavjpUI
Y8UhX3otQ7cFA2RmCvIVMsEPritnz0yINE4RjKjcMb+BXWCDtdTd9NLzTCPssMXqP+7+kzs9P4OF
A4h35ZwbCoMJ9wMpW32hWTBgMzzKMWg05SYOQoVbMfzQDQ4gOw1O06bLYRya4wxdTEij9smuHT9X
GCD6zjQKycSK7ekMynKzr7M15vnENn/W2GK4v19FQzazFfpG9u0Kt6gpyckYpsJjarIH6jFJgf4u
mAfJ1j/b7T30zKgsinqb7fnYcOBNd5/2EvRhMRxvjk2mza1T27/7ZpQkLPO2e1WBzw/OstC5zy7j
qQwGrZNkNXLa6raqp6p1NQ+KdY0+Vb4OaE5DnVSr82M8R663tcuk9a3IrjlD0atYX0E5JbY+hvFC
8nBtTuNDyxcVCgHB30SSwGxc8vsNA2rhp8t3uT9gGImsF0PGGR7GbljRTKi/WDTCRvh6npw9idsb
YWor5qtIU60SfyA03i+GyhLXGYhvCYoj/rCZjnEkUAYXqxjBqLUgA4grzKykrt2Mk+KNuE4/wu0Q
gA9+0vj/YPlFiVkst8CJ6FLvWo+zpLADjF+jQFO5BkR68Jlw9WWwWhyQK8rvh6U3HfXVFh7Y4yXw
8ib77FDvYLjgoO4zo9yeD7pLha00/K2KKgaccuA8+aGWjStkz4zdElEUYEV7ozt5Ze/9owbAPQxc
Zr1DGXM1b0/OUgzXJEwD/4GnRe2ifnmtrpIeDCLzubgq9VQTi7eyHzRZdpVpzDoyLCdW+UrTC3FQ
UWA614h9yoA3rqy0PM7A4yoyotK7QV42fTxZpHr+000Y+Awyb1AgTObAEE8KXtIQF+2Ob8J6dANG
SHdrJ8mpsY82mNlEqD/af+wh1UShLj2vx3ItNaSay6V06d6oxsKC/dSkRygyw6S+3phqOEhE5GWm
IYXaSV0hiqSzUdpjuwYdIsoG5kr0+Q6al2ZJAUVKoJ+83Tz5/v1WBHdv1Sm1yzezOgiuHIh51s5P
JbcbYSuVQSaNgBqScjOyhtHEKJo9rUNbMW0tbhsren6ypg8SwLdmwu3/rjEm9x3nHtq04WYeSlJZ
WIL9b2+EliE8mEk4xE6NB2WDZBufQmj0JgLHx5fvgPxjat06XQyP1kWhOwlYpuoCHHc23TBujnvN
276A/H0cGZnQ8hjIEijDJk2gbhs8vaiziTbGUBRf1uezh2+vGQartVLWgsNeS73WgS6w1PMmHh40
SUIUmLVHKVxnzPmb8SfMlfkVAM7nuMb2zGp9ZODIlcNsRLFk4azRSp5cGvKcq+oOXWA33JncVIWO
37VhNYJ8RSyw23HvTbayjjHTPESy3yD+OQnmdJvqydm4x86qfd+vGgrSXPlfK8c/Kjur3r40CCDA
efKek3O/wzz/Jl8Y5HQNZuSuFUyC/Pjs+rig4nUR2yO/jKR7VsK7msUmrU9HYBm/NmsLwBw2PV/b
csK8cbpR6/chXheScHmCMNwLO54FcD1ZNj52ZSbHdWxEVNPLu7+gXveq0bcRgh17TOunP+27fQN/
qV1OeFxqtAlqa75O6cEtoWkVEyJZgCl8vJDeDHpZW2xuYmLdieDNqNOz34QvNA+RqK9R+lpBBteX
Z0tVaPQkNI7Reaqonf6+LiNneztzt6M7AMBo/VUX01c9hX2jdRv18PFescu9orfel29ovDBsq7i2
QVnpuYkxne0ZvThB0dJUo4+Z1Xqp/I1RyBF1SnUxd5vA0lFGISB5ZdAVs4uNUy8jKGRKZMARMNfm
rzCjjbLSGS+L90vPz5UmgInQ2n3mAxvjoj4YM47I4Wq/u94WjA+TRSfhPjOrc1Qsbv72pLXv6AJT
ambX8SVTKLZ3UqSklss65fFSj07MSsJlClQIRO7RPsguQp9086QmErxd5WJJrIjZYSmIeViH6iRn
fEt7jJTH+7IGpDTDs/Q8YC8G+HaEG0u4HHb6PP8LFCdyXqHorcVtGXu6/I3YOuf24HE53hiL039+
O6lWudIhj0kaqPiuMfNx3ZpApAjr5CP4cZBAeNglHDxpXBVTWNnGH83HC/h87O5TkY1gFOICpfZR
n7GUhmrhd6G+3Tq8nNeSwaoo3wSmurOP3JxP42kFCoA3rAVN6n9sGp9NxA6d6YGVwLC6VvU1LD30
JwTIwesDNbe6AmNg8/HNCdfE6FlZcq++SPb2KwCQBa4Aaouv7Z1oqeeLd+0RpiIYkT7ons6ndUxL
laUn6O0lO8+z6XXn25vOr1r58qjuFqimklKLHbQPbfWpCF+lA2vjkKs/69O9mpe/HHkXL7/pULNE
dJ7I06mLOAgAZ2rgm6deIXxq2vyIBA4jtctk5PH8spKT14oej29nve3x/bqlC/5pEGsmIANVbYHn
i8N4zIFrLm+nRFXpBDJJKKHOa/WvuseQJ0uqpfNIifQlOPWgwodLFFxBxl2UsH9q6N6gFEP35B63
pSSDRKxkIprLCdIM42bMLG1kC31gt1cg8kKKRb2tcouQSMMok+fCpe+mh5U6+Xh8CeiCALnn9ez5
FpcLQTlWqsuDNdA9saGuwDgQPqBtzsw9HHs+EN9OU6qV82GM5WJIUEN0kikk71vrgkdJ3zoYU7p8
k+qjGeHZNtNlzwnm9vgrlHac+cpU5Jy62kXHqe9DCbqj460knPQKzUCXwI7/scgSMeghI3IUZK8U
6eo0uQ39fT3W2ao1bD5gJV7/plPUp6HZ0Vw49jUG9Xf6W2hn0G7MQgvPtXVcfnWGWL32DUYTtvyA
ju1qymF2SPaF59a23neqC3z/aVD0sMd3LdyzPPprdLK3SqdrGGKmIb1I94fweU1rzJwRKfq+wUQ+
iyM08gt1bPWVeq2gcVd6yHrWy6xWZHts9+MlV+txiby7EYCyl1J8KKBAoxSPzTXXVALODB748NOD
HLkHyfkIoKFkzgWfGxAzDsKDKg02Q8M1/68TUsTUwB2GPKz01yil2MP1SAeQRQnZvIa2MZT4ttL3
G4blq2kLbzh+uhnR8xRg040L2eWN9/bRuMUfRZWgXThWnxJ0UZx4+8PSLh3KKW+SqCOZYwP4ZGIk
0zp/Y9cIz3PpB9ynp7gmymMV0mvUlaoHGa//jBdQhoEkSiX8fiKvI6L0sRqqMHfd986X/ZTpjbEl
K7E/vbGgB9XwszJT+K8vnr/ZxqxIXOmONyaBQZfk+kkvMwHOOo8nf/JXC0uGIC2Y/D8u5plQoUGR
1wROA4wUYLlpWfKwhC3GaNBLDVkaHz+RHNL/TyAbk8ahRXaU1VZhp7hB4GZlyL0jtRcPcLPbP9Me
X4eQX867bLARLdx+0ggrxnupU5lf/+wD7efAOnlcRy6teBt6RsucSWdE9ACIZ7oQE3ZqiQux3Jri
u4nh9HhMt3tKazZoVKZPsRHQeJHRXdAcF42LyZr6+aQWVPzFajNG+NeW06H/z71//OWBvQZ/0/s6
73NzIIMyZskWF0AbgLRRw1N0mRZzVBcV/RAiqRI8QhW2Y8XP/lj5sg7ib6YLf6y0ry84mKGe5UXL
d/Vi5sJ0wV8cYQrwZsTrB5ihH6dEQq63IFrAfl5uXlBQOPmx5nhOli84UG+3DZgWWW5vW9SO5ASf
W3q5znOQZ9Sh6p16vKXVjNy4RkiKCC2ylc0xH903+nndIJThVNbK8Rtz+s19td2jD6c7tN18cKJl
ZPuwqu3mWOrKgApfqkkcY471+zqjT0eG0Ctb10IV/FVaIrcuMUEuTT1BkXkuw2O1eb+4B7kodQru
Mv1VpFIeX6HWeMjqJyXCu9sIlTvM5lIQ9S3nmVvSYssDlcxH80GsUSploBIdsEZ7memITNnA1MFq
/RA2/cn1xs2tKMt+PzFh4Cj78JrcteuPw+Vg4VtnedyV+D3kUiYtB7Yhoz5QCCZ7ZPNICaTe5j9R
zZB8MOicVRznwM+qyNgzMwHtcXujFBTqPcdsGJxVCjlK5eKVjEZPatrBqFZ3s864UX3dyu/DHHfc
DLJjlYNcEdrJyylZ5d5rumxxDVCBg6GZPzV15dDmv4jELJnUF6k9Q5p/l9+XA8HAN1RQ6Ie+wF2h
l20038GRggODDLYMQLDjQ4nGwg8TGJkX1uNe+xhbGFb8q0MW+1QtC9zZcAJrrr1jP+GSgTGb5XtM
Vo5qI6Lj4izxdJsKWivo8PHzf0ZIiUNy7pl4psvo1EqLIV6TR5Zpk+UpP9NK+VWGcDfRp/2A9KUZ
8e1I/OlN8RWrD09LZRjzqURoz5L/XycPgjKnlstuO7RYPb/qelql/kVLm8ofmtQxjaktT7lEcTZF
uj9i2ouz+EdTQ50Sse+tA3M8tFTOLWH1moxcx54WESwRZEZaZFE96VGIkcY8yJQN4NPuqR3I1K6/
HJYP92RV/ZNZhDkTxPfxMLUPvKVpsT6Acj6dley9uUVOObRCI5NjXCArcND5jJ0QYAv+hIN3gTw4
yXRQindl4QJsyKU/ESciMlxU0fldVOxCXxkcu729mVrE6LumYR/mQ7/r8skRsXNl8uAkLZrsYT6p
P7cMv0OwZD4FSC+SdxJNN33ha1E8dC3iJHCnXktovLBUho9kTHeVgAvRLyeO4IeZ2j1sGmzKydhx
+prFW4Dl0zhuSdUDbpQuXlaCW27IA6DxpwIbGQw2VHXGBH4BE96uygQzw6cpaEqHTmPuceMo8xT0
HFRpn2KtxSY5jmNsKutI5Qe9M2w+mMPYMZGgbtmnEqf235XONUcqnpV9rtv0op7G4JobpanGKnDS
Mvzw+4x5QRFueb2g+QcvxOvKXwrt5jm4vbr4JbVr6rmio4GciGgNryJp5YrBHKInBAmCIca+Vf6y
TM/Bfu99qYXSP4BNS+wjfuqplQCJpF2rODhkZOVCRPBF8CQhEeEPUiM4drP79xw28Jq/GWHElZZr
iqHQuNKM6oanK6DN5G+Gy8PkQVWmVItyt6AAkYW7SoTyvvNw5qEW6Kr2sHNSgH6qgJNszXJv1CJS
mB/nKlEFYWYKXp6G43qjmAq4flqmJDcFTFB7tsLn9cTQEJwDmfzOR4ZmWiUMRBR8K3jX9MBwY2ak
QqHVo20SeLdfv6v1fABCp5m8nfpxbOJABfE4N5TplmStrIcjoiqckymoJsDCaQ1K7lEVkpYucKJS
WQvoJsFFZId9w1dyMgPYQgDWYqDIQUjsLa9NasErkK7BfQMvi3bB31wHgHf9k28XqcRIz6Q05C9g
syis3k92kfiz00qcW+myuX6g8dXn8mSH20/rqSeMY7Xfi04d3s6JENkc59T4ZPz3vL3U+qG0o3cP
Gh+ql1SUIJ1OdOgpjk0BLXLsTomMI1Lyd3lWYQYprBO6j35Z+L3HXZp5vI22GMIZGHTEX1vtzZAH
USp1GvB/jtxV3e3Mla7X4CmPC//iXnNHYk8dxIOXUoQlWqGtGzPhugkiDhCvRO+D8PINdmPijSHT
0q+woBZJAszTpxubN6ZoYHrdxnT0jAgdhA66QQ8W6N6bbWXcMcAcJg3aOww0G02kx06NGEmHP1PP
5eOriuHih3ZUxDxith5+jL/PhelMKsZGB6/0ZKw9Bok12ImCHm61vU0PS75x/msdX+/RsqgS4qIm
MvabsOR3294RfKYMt3ijz16L6xBcg1Qp0JZP7oka81Zae2yXAwMtu0L1BQCC11Tp2xnZc0+tTBdt
bBD9X3qyYgYG2c7CZNpQas1kLWTf6OGKF9G3tG8q21UwXuGUIqsL+GtxqDCVx4uGxAbhojhVqWZE
1pB4QtukeE+AMHOkbgWLIXbLP4tkJ4ceRillB4/Es0TmM5NhDnfOE+exP3UnbTRy+YskDSKrXi18
k0vnSFK00E5ceA9b1fhA1xxUD73hmV1chKGwZCOzDlRJPF4smRftUEdoN18rMowUf+rJLzdwkHUt
DqNZ/5n/5oYz1T2X8BX5XGvBG2atbEp34wmI+Y6u9jLllbWNBxc3cLOCqKNJHmHeGRjP4plBNA1U
ucCjnRr/HxIXrjuc3vRhlQBVTEASSxrPdyfcRdmIndHNGFQFshasrRSwOGy0cgjRv13Bkuv7VJ+Z
uqRslUTC2PfblxUlMQZjHbexVWEHKJ72rUIYaAr1Q6nJ+asX95sMYhC3ScNjoJ8bjVtgIgVPQjzp
45sMd7T/+iIfLZmP/FB1NT1f35PJiJAzUg6h0ikuvsY3hhNM16BXc8JqS8tqsWfigH9a8/NRkVeq
qx+qiEM3fjx8pb2yVTHgOTKFhT123hAnZu1fE+fvrkhya0Fm9lF6fITuhrAUXS1zdGb0gFDaZq3v
0Z0UiH001t0MYqMcpDfkf9SZhGDusxWV9XlZkyE4xlSiyWLRnFCHyh4bEXATQBImtNAtLw26RnY2
EssJASqZMJW+ygvbROnPSY+eB6YcQPBgU7hfl1sXUs7MQh3r/KYHNDSBH3wFwrh31oWBfNSD2b+m
6ypgFK4VY+XHZROv0G/hgA+yQ78jQtzBl46T6LcL+1VJXAJ9E6QKASZ3hFgXuLmIal1Bzwad2s6N
hJPW2nMQdgXuk7TUUwgq6YDGRfmBvL0+YhFObuG5JcpqIRudcoECwtGTWj3ZTb/CKgRiyOFje5dn
2hIeJleAkR7abpjYThaZXlaDcKlXzhl4aNxoxGNY6gI5o/pC8RyV/24HdS/n9tAxFJWu5YnPoTr9
Z0E4FXHhWcd2Zpk/wGEdA62K4MEsc7adcSGirMf/aBU8LYiVtvL2VhHRbztQ/oW5FZ2BLz5Kq50g
7ibvKX6GAzIDGd3zvnBPmlbmQZY1lHIpGxAEmy4F40LwIUuf/+NXSgq8XE9Hlo/hdBYVcg42mVee
G9CCbe/dMwOXqDFmNjgm4e5ugFTzN5Sm+dWe8GxxQ0zvjQCx1381//VQAK49x8cB3PqlOIRVuaXz
2l1YzW0lYrqr+bCXLQglDC5rL7edQGUu77cvK8+yyHfgmpgRnxnT6G0cKV8dlTrNdATIsCXbppFo
8vkWEUULD1orojZYS2q62o/vFt9/Xr/UhPWiaNyEVaYeJv1+R9XfTWugXKREjQ6aRy4PWCoYYHDU
y/I+Xn7CNj4cl5umn2K3YBgx41g/VUAaTJVt9siiLLeFxNe+Vbi0rmLNoLcBoJklmXAynvyOGHe+
RByV/BMPbla7a0m5Zy/9NMV+jQOl40T7/XO55WjGplXhg2p7WWweNfprSZYUuVdPGxNOMss9s/js
g6kHQHXrue0rPDsI2LxHJRFCpMlyGdOk8DqvUKfHIZS5dN7WzWcVUFIRLKzWcHg28zPraO7nilaO
klWaZJpPLxzJ7XR5HonF87HYCYQc0PtkI2SInDsf0s/su+ddmWLhcGx1zcQcTWKv8J19I+b1yDSq
JVfidWKu0yysuKbZwFr680dV4lOZH7urtHlHXrSAKYQtTMUHFmOE4VlVhiNEvO9/uB3dtospy9ag
BUqVKXxHJzCprxC6DfETkT13DCztt17ByklqzNcnwh04Sd612s1zQgs/9h7c/yqC1X8D/km0JoAt
3KUfUoZdh+Q27I3ADdDjSCNnad68DX6c2QB68OuBCfM4jgCERIfctyrJl9pJuROMgVA75WRdDpF6
VHTHe/LvHtBDFgAH2zyGLIUTRkGgax3ExXvM9AnECkEhKsWVSA3Rqvwg2e4jrGU/ur+xsJba973A
LWS/Woh3i+MOugTmZNVaIcDdIebr68mR25HcKwuG86as2TEbi51cGXbe0F5smrw5sUWQn5UQiyTj
YtLlTm5afbCwSpckVUyQ/4C7OpdSjcz2avscZ6u8C91Q7HHFstuUAqpLXIlZLztnliLXx1rbG76z
GJ8DF5PULTHG4FcC4v/+Pa1Hk6r/rv0hUWXBQLBbxnE665WTkMaxp4XraUJJu1wQ4fwtZh810pWY
TJdI03BXL0Taemx3p3Y93nPWKMQPQ52v1SQc7Cdo0fVaFwS/G4JqNBE4vU3XbyoZ1mCPhwQ3lasv
VRKapOxTnOxlQqqsdBP9CUXAWrgcvs8a4k8AbWSyykV3xvOEfJXA5J3xPx0Yh5weaoy0qByMY/xK
ADzYhIbVHqB+YSgk/8/pNVceTkoZmTWJpNR7CAbImQe7AHBcaMntqoxeo8o0kTJIZqA30dNIHb/5
tGuscjDH8AEYAKZMhSrMjWxxF0KxkXNN5wVHn4m71aWd3J1z3HEvO+M0m1EO1gn8CP9mKTLyAbDQ
Z7w47NDDqm+r8aZIu54dmjWWBS+fBaZrBOQXoq4LWa0Z9TfwlF9+P/G1YRJTPfLlF+mQqnamBkpe
awe2ED/FjYh1OVBKayWki+Hqmsd0bs5A35m1payq4+j2FjJZ7I5xmrxyPHOFWj7P9u2EJUBgUpqe
F2R0HEKD4HjXNaAi2qNm2s4tnvCYLlDYhA879B+cIh1Fte3l3NOBIf1VF8P0tNXSBsWbhPrwTotS
lh2C3bs1xRIyuTEwbVmceENU5iA8GpVSCDDcs3c4rvdFm0UYizh00vyhLTjGmC55X2lKKzjYoKkz
cX67yktCXYCg0nklR13YRohKdRrP6ck7ckkiU3cRLX9oHIByJgeRtUXWJTi3bcRMs1ToJTBDLedH
6wFkXjdyLTOJVVS+RbdE5spgAFkByNssxxNIeM1n1lgBlzSiVQpRijYUPgkR0tD0jzMrxAACStdL
VvA+dbwmaH4MzjLiysa/hvet8WOaGdS+8zwrISg0ux81xKwh03houLMyQtSPL+9Y6F+chOJqhmpC
LAxWpGs3v/G9ueBNov6Z5J4vQF9Qa4fTZnTiUrracYC28ywrTbAFcYyZCs3AQt2kCn8/QqLCtdiU
YhT5XydLd2/vlL2SuvLIBFV3W/9M/E74niM4lXmeXzhYPsalzYiSWK24qAZY7afuHSyGK8CwR3v9
7LqmtYYsKsPJSDcnK/PaJgohOjP543OapOlsMjmCze38u50BckqPa8gsI6w/7uaRUrh62i/gMN6w
v58r1nW+ZV7/+zbR7S8szfnBiEDaB8C0R5tNtGddNUhfl7Bmi4I8yrDW8EJQ+XWZDGfZSZaUptJM
lBKmY/j98b6WftNrSbUc+jwqay6EdIM1ajgJVcuiFimC78k3tGLkeVfXpXko32lOgGs8KZ2LIdZp
VrLimrKgRL38wbXbyU1utBALoPRcPrp2lr8B+N6bU0ThDBoVkKcRP72467vjVYjZRWWP2apitLxW
C9A9/uogilAWmLqhTV3aV+fu1f6EUq7dG/M4Qh8rXh1Snbej6zEWjbnJrrjwJ5MrVRKrxf2zVXCY
2kRFUvBjR5C/RbsynfCz0630ZQYvNhROJEyCfoaRnhzXuLS5AGvlU9M3t/EDCNuJ0ehVlZkXyUht
60jYcx6yzgdL3AiLGbCUGV8dJnFKa1686V7/1yECb2fHbRLHS+OvbI5bTIgeC4YV9u0h0T9nhp2X
UPogvrLtSxUA3C8WZREAojoyGqthaSgnbgTBho5LB7seiqlPehuHWns/I98CugyzvqgNRP3xYqtv
zxQZKYg07N+8I82e4OsghX14B0GRHeoVQiWbj7EKkuGuNswugtCMcA08/zzHJyb9a5Jytad8pZSZ
3y+MU1T3M3KfEzYly4Wt/ngbf39AlEbIg3m0nsWtXVENzuIeaD6Ztd72HJRE7ZQni87IHq3sAdgK
lMBYZIIljTWwF4loA+GwMxXUpPCWovvO3TcVxNaYq52zBhCQgUfF7fS1PUo8JW11dMSrDBtL+CLX
J9Owz27usnp2jpWxU/jCDvu6gtix+YhGNLJdXrGvu1+05logvHoBoOEuxWmn29PsVumSqUCRYMvy
vwpnMyknyKslUAJfVrjx8TPJxuMzF93CPSv1jkhDeA6MvySSm/iPsAO/zvnwrfQRZmLC0Q7BFwxs
g2KxZfSdaTGWu3j4NHGB3H8t2KMeCAc5eud+K0MftwUO5ziHv0c7GFSgQugjyAzFELg2M5UAD6kd
8zRd0AgzqEkrbnslPHV9SrT6B0gWMWRjPAsKOND0Iai1bW3fU2JkXpgIzXmmaoruDuS5Zh5QwtZQ
v41Eu0j7oa/PpgQUiGiwB7YibgX07QzKlFNkwwRRFlPwcev9X+ynwZ0j/nlHh0lYIYyj3LCNOBS1
3sVr13NmjWnJKZyUEcz2uMNFDx35YiwmUqp3iHVGmmdheywFcjaIx55a7EnvAM3uXa1jHR8wdoeg
uTQLDbjHBdgWL/kQc++xcBFUvxCifcmSdLUx/6GE/G9IbO4qhzn6ZXRXyJZeUZFVzD7sEWWJqjQx
1n8F6cXUG+YSwDVUF9Arjqr6EDO0wxDkrIbf2mjsYzrgtGNQcQdGSLatnr89kFSmd9iR5e9+SYin
pEjrkGZ5BKDZWQN2h5zpTp5Pf4k9PlGvDMkTaUFicyjS9GfmO1RIrISsdy9UU+RBMwRDM3uy5x7k
EZRNC3SrVT/cnVHDc1RXQq/dXPKMeNqyOoSXdlxFWrhVN45fOOcKVO3hgXUcfVB/X27/tCUB8oPI
4mGiZrZUlFee7sSWEHuy36dzBEs3cfANl0lAYS/aYaFWkRjOJ9lZuM35Q0vpmRHbnSHGOxjz+wc8
YUXQNDv5fLPlW5d7LvfiHKy9WGuD4lQjU4Fq7c3j14o1fpndY16WzlsFLFzolQ0F7vdymssUQ0WU
x25IiRuM4+x1F20wF7x17p4P0jEoLNNGAUE8irzIvhF0zmSOzX355UswzlnCJC1WuDxuv+dNtErg
CUudUMQ7wiF/pYv1HE47bhiyQJzo4qvkxYbk+9WCn6C2GSKoW9jqkr4/W09g5uQ+HQIKT3PbGeiv
M+KRYnnD96HmAGNU4QulgXZYDDTKR1aHAU4cazaTTLCXgoC0C5YejXevnk0spwY88tyPXMgwOy8U
2k6E8skpWN1rPeTbb9ZxoxTcZdCvCREHiLXNVog1AzAMUcfo1sX8I/9Ovd9an0QkBfoBzCZfnZ0y
Ks7qOxXUDRLyewLRZBkmGXSijP/yHCE4+znaerWtklXykQrVPFr5jmQB53lE4Vh+VQsnYYSKtERh
LgAaXDBiZktXREd6/3IdtCHFS2Dug7THgA/wcnYFsRi+UBsujBkQzlTeNhxVzF0iFB8hNXFTT5M1
c1TTZjqoimmdpFVjIwR4EKEAp+LdXK6cOUBL+CC1+e1ggPe75CnjzZzGySuuCYzLewyi2N4B4VET
mT4p3xeznLsmDrQkOogcojj6RSj0p6dMhUlvfdiACtS179NTmeMGlJ+l4RDmeNo4/EaqsYGJ/G7q
fOaE0rhqcyfhIJX4IoP9WZ/ucJNulew/cKZqnpXQt0y4+pyyd4payZieD2Kg5BrkGYXPkfsgBJZF
K8An0rHlB/NUcwC3R8FXXNCctxPb+Q3cIM8b64zJqnLgjZz6jr9yIciVGpG/yFGO3/I5IgWtolZ1
KTYg+1RbqKCq/kbWcvq73KtMTxvQ/phTom8Tj+Fe2AlatY/atFqEWZdylfb9N/gUs+vUwNlKcptt
luxMa5M1gvYxPdzr8HJdZso33ZACBVuvlVwBvlTOaRIwbaAyDUqLYbpr9aHBaJ+WLFrLfKlLRNu+
3WLW1sWXrgZ5L4nsKkrRRrPrfnaS0h8AXz/58/Ve8ozCIlyVyFoartPVns4N97iqjKN1T0kAmFMR
EdC49qGmzoxfZyGICCmneuha3nFgJqVrvlqUJBBJQ1/w93CWW0JySI42qtXiMe8OEKRw3xELRcrY
Um4MjXNZR9vl/WJnQgHBgYMpBqm7qxi2cePiIy9/N/8IwTy0mYeu/aAnLIVIlUryMRlL8mgGHYPg
ykNsxYXpRGJsa9SYe0TQdDmmkIFC29UTxwFOmujrZvk7ran2eDkPwGs82UZVAkYFGa4vwSC+XHnk
8KMtzx4hCDIe0bQDjfxXCjmeZyZL7NwYOYFieD90hSdwKiTxjwX42X9z1IPdwYzVSgPI+WWDGjy6
b9pfYpMlEmKh5u9ivxkCz/XcxT1Dz4GT1gx1lslV3Hp2tMmeLgcxlEHbhN7+S85xAWhzkAPDZq9x
sCf2uH75PPRC2CA+Mcu+BEPcL+zjIUQ07anEM8JVYejuMDfnmOSmPs2pgmd4jebGTDsSQtvoKlWu
W1KjHy/7HDaQWpGt5wKm1Zi7pWjRfpohdQX0+fZ25DFLts0QPXFu8FdRNdqP04h+1V98JNGB2YmW
o4HaQyT1VU0pWXunP6krpRV9OHexTj8VQtImpt08RHEJSiU37KLOzn+bKeg2EIxRZrCCCrvNFdfq
80DfAy0UKS3ih7oEFWxh8DlMaGnVzm7XOxTEb4xaG9HOcoDamrWxy/gG7SYykCYxEke+fx61MhxH
/EXTe7GxUyAygeoQ0SZ+819HZd32nAdtoLmZ84F/DI4St55NsJzPDSxlxt5VqipjSs0otxP0c92E
lxbMN90M4Gw4XAKnWrjIcCBuiNs++AgG5DXWs6V25DfsD2jtU1mVw3w0vdPJ4IUpTtgooZE11QwF
fwkwvOVO6xnv8jib3/9p5GNbAsE32f6hDSFiU1JfZLLgV4cx4sfDg04fuBVOergDjaqFmS9nrWBR
G0PPgTbAFggc0wvMHAZfclCE2nyvNJx7eg/YnCCQiWxP8whUsQW7XZDlT/Wl7iglelNv1Jg0LcZF
MoSBFfa62PZ3pblSVnJBvDvPj3TYbroLGL2q+NqmGpjeOT7MV9rssq0haDSPEuveDJb28mLJUJeM
ASQ8pPL8fVyg1FlkTUmqn3bBbVLxC+RVQa9HdRgUjlOUpKoX3k+NuZ4m9TksY0FZRYR9o8rhHPjL
6iAJAngTwscgN5Ho001BdZM16fdkKoXlsxUFHJfqvWZqNZmbw0GyeQsMdVEyjw51Wt3S+hIOZGj9
YWvdLI9fhYEGXbBCPj/tYUV4DzKUfxrX94mHDeYKBeeYiAc8F6aW6Vao3/qPMzsVgIhCmW2WisXk
Nf0j/5Tob9NCtEERAfGe1OaI7MAiHb/Bt/9aNR3agH89rofpyWNIc+haWCOHjQfu+u2Zw+lQR15T
yM+hu25M+Zbhb699DHLwtEo/3SRpNydfglSR+8XC6ZS4WVjzg5nuID1oQKZK7mlTXMi0A8ceTqs+
V2WFaFvqIwLe0GuaLxBEw3GzzPFh03ZTYTNJXB3IaYd8Lz6QEt0sOSfRUOzRDl4roCRegc1XFUpS
JnMP+aeIa/h5Jwk2e5DhAYvUqCoYN9vabKqjTYwLQ2EhqYuaWV94l96GHp7BjIITMyMHONt2cuJH
wYVqJvOQMioqrrIha4k+oJIUN1lHda/fo/fPPZlouuKxi2t3p92PSOPCFwit9ZQUsWnTa0g5qSth
Xk1yqwJweZxZxHx4co75WxpO2tMOgzHTfXwxjSkgmwYvEAjOvXfxvT4v4Uimqv05uDCOb3YWCmjE
MPNvNA0CgBrlTH3qWx54/C2FOvdp5+RMNKpCfBbu2Cjd7pCVOdJRZfGYjBFhAamGAo1nYn+M8f7X
Ygh8TXBRWKDTAk4G0hva5NwBSH8+ml1lUzStDkLuSQ9Vay5+sTkJRi1TlW7F4WXtsf/T5Dd47vnR
hD4HRDcZoDt2mp2kDC/5YpNsvYx/ctZPzF9mhJgbMSXDv86+F0xAF5RtP5XkJOwYCirB7f7r12YG
e08y63gRQRcIvNXnXZiK2lRPi5cEUdz0p2mErSQNAE9txVFvAfnbIeHYWEaoQZMrPpcL7Qb8uFhO
8m3QivvSYEbhGVO+Dc6q4j8UVmspZPmPS8wODEiDC6EeWrZqGxDYKHOtLp05kpmXWZM5+8GIb7eL
UY3T8OkC7hrkf8vWIecIFazlom9977ZJxDQFRo5+Y8nGZHhwvHZlYNr7R+rT5amJ1ohajegYjmPr
2SpcnqGQnDf2eHCqQ8dDkDn3URilFtsQaxONA89Tvf4QgVTR8UYzl5befAcRKGsTEYPW3MSLyuFc
esDHGhFF9c6m4JvpMUDcvXs9OJ6Fs7TGN4IA6cMqnzk+iNrQ9qXbO+6W0rPNL3bhw2bRXsjIqxjM
lm48WeqMO3UevVqGjzeYIxxQ3/0qSmNrskTzc2TeGUnYIAllM1WcQBFFrnsf1tOn3R4YDFbEzgzU
aXbRx+zVXPqYmFM15Dh6elKSP1rd/u7vg3n1ppE3wIlQQixBfsnRSikbk1OCruKnmtKX3FS+Jfrs
3Yo8NTxHXkf2TOtt9KGvNa/9Qdd4Sxk0JZztKDTDjnh8Ap0mgCeGLF0zgr4IUafj5vQkZi9GZ0Gy
8nHFIFljmhFV/r4PV9KqoNfqDaYOJg+r8AIXxoh0x0jYMngdmfdCFnjPPY3t4uxtTn4Rd6dBY4xm
yj/KTQIJiS501hWS+j+62Z+gBO2v904VkVSrnaggdbCjRbL1S1ngb6pcuhlm1GPsRWsft8jYYBDT
susVvGkVXGe6cXTN69itpoEWybjTVANdvlZYOu0jcPdmBXdet/1RiWRON0sKUyjt2y95p29KdNIS
OxHLnrDTIpsro01uNSIpstHu6K2Ki8yPTMYj/kyYuazMfue9V9RlfMcG1QfKj9OHMa9UU84lEeQo
PsCeRTt7RRCuew+6rVoHwiKTFD5RNhfjq4rtyJzj/nRXEDbidTgy/r7xigQx4aCncGasPChvDfMU
uwSECVQClN5wzFrXa+9ieuCpi68st9RH321v4lB1trLJVGyjYmp73JRWNxScWb9h9etWpYs0Sk7J
vA+BzFrcf6N4yfVJmGQgNzpouw+UpWiYLJ8duPxQAH6T182OEchw74F28pH6KJSExIYrmYqXtlos
Nvt9V5CeWyBLA9+Uux2f6s3+n52Ms3y76GEAt5HL9UJUuTg3qmzqUAOSvmWkE1yNtjXXyxj/sPoT
n15pDhKH9l/NMpHFr79fp4WYdEu01Nj4u5/mZ3LPcBM+5xM/SOFgfp755IOeDXWaIA30ZtBpVH9J
8189Zt9ajAxbqEFCSHr+eVY3lHZrL/h8xdJ9Z/yI+S9ligJd5YIJjyjyheuvpKAdvMQJHCBzEHI1
83J59WcO90FC4JSKd89I57uqf5JCzr0rKTWs18s6nYkubtxUoFRHSshxCfx1ZjEJ7zcIyCcrgURt
Uim3HdGnlSXHMSiN6K5qIZc+ch5LXu/ga1mAgP8fTuU8VG0cQ+TISy7EQ2vX/dGzHaQVl3+SR+Wv
PBu1GbJmzHtadcg8G/k4eBTSnsILbaqvtEorFftu1Wbs+rzB9a9zm6i5Vdx+IRHDtbOZzU4wi8CI
qFg0KtKeItLAsEdumpZwJTd3/2SjQunXXbQRdj9GeQ+7sKAHwEnc5AsC0LmqZ3JvMz1pFYCviSmC
t2AQdc6L+d39H3zoD603nstBc5ukwdcYaXfXTS+skmqi7CUhc1oLefHcp/k8c/6MGhvnG0qG2vsa
iRrftHGgK+xv9P7yNwusl65CweFVjItAHhQkPbi7WHQr8/nhvU1TgArDnfTBE4ADaVTXTi3EZNCb
4vn/Jz4+cIUAftpU3SbUDrw4z/x9VANEDuOoY89EUDHEFzGNJmHERzFwnysBSWxNaIfzojmKJA5o
YLtRr9C5yIVUKQmctVhkOB7iK2JubhY7Bm3xSLccixPyCPdZo9e63xK4+eRrqoBGTcJY2ZEEIH8k
BUu0a9FrMZjnslP31Mru6BbR8Nc8lpz6W0bLROGlYC+pO6DKStq7X9nkJvJ24xRzV8XaxcE4wPA2
9geaC2r2gsBoCZp0kvlTYutVreaP14Ll7Zdb2qiFXbTj+N5PNoDRUsCfH/T7Wu4Zj6PKpzgqx2ic
PDQhEBKSBiPBkzIvMbiWLdgX6BKoYT6Nlyu0+ay9e55UwWDX7j+XiEq5KUp2rhawev8wdaR9cHJo
zGOqX58oEibB6CCbYHTaUC40vigyywIqsGjD4TwmQVUkDod+E+UyimbtEkAa6NvF7kNbhJ0blum8
k5CER4deEywSd/63oW4qGqd/JdhrNXXAgtkJRDmp8DUKLeHJXxaXW7SO3tXpfq9BeCVmfT0dbGTG
jmXp//9Odb1wrBxJwltrVJKTY4LwLsvo9Ck4Us32vHucgXfSB86L/Uk2aIVORVWLsh3kZXpeZts0
wCaqylTdzZTI1oz1FMJhR16QE6fFQRq93mJBtbJHytNqm3zkYzKofFLW3ZvBt+74SK32j/F5Lbls
6kKEzzOfh+Rsd7xY/7Q/jePhrEXBFkztbw0eBV8yCW+Hdov7qoHAD4AvkF0FCQ/IZY/ZItz3LwTy
lnj9SsmkgwVfkrBmoLPxXpOMGiU2RjK2Ddvl3Z2qj/knUxOnI/8GFFyC/mWqk3wjcexHsCFY/F2G
akAB5q9L0WygyyvuyHnVzQwN+VbhwaXJQ0Rc7Y5fKkdoIeKeii9gAo18oG8PY5AttcH3+Ej/Oxlb
oOgFEE0gnNGdEUQtHRyAl/jG5FdJHL3Z8bRbj0TrytrZhl5tSly88tySFjeawE7k+FJxL6Bl2q6o
Yoz9B7rfAgyzt9UsK9Ck9v/1Ud3xUdIU19JU9Uf7C1vB0PqNrF55jndUhVaVku64dloboLV5q+Jk
e+o1T3YaeUAcXz0ZtopCc6054PdM/dVuSIHqrF+hlxply/VYbR0Y6v8XvCv/32H2Y9NpF9GsyCv6
tdo3f7ArySwftO0GUDZPSNd6sn/XsowcbtMer7vgdMqKuZMuRGTGYed/DATh0af2y7Uc0XpGcT1g
VwLWuD+bl0DRlOiEHD3vdcZXtP5X3RRTZqbW5IOEE4tFPR837Iy2XYe63ljn/xmAMTrXQ3/arvII
xuY2UUS5aJ0n5wjObrPoOP8+/lyS87GMT/0cSkgmINMcUwvO0zj/gThWQxIR0t/NAkh6Y9eibJvU
DobLih6n8QPjwlRE6OopdMnCDLmdPbIIIP2Ph4vIfzHSe24c3DyIkyKzhZCOv5HlZyHMeZSGm61H
+zlSffSgNQFuEIq5JEU6U59PlcOVdERWrUtsCp/iO54afeRFayk9P1xHuVWC3u+Sp6Tr/x7g9lPn
ByejBob7pRMqgtlNIYjzFkNXA9PJzEm+86VC2Ys4m8JW0CqeO0UpR1N0j4K1iGGExeYbaOViQvbd
7+5IxPeZr00KBaD0d8QqrbYhSKbn4CrRnWkKQe98Xyru7TYoL5SXboQFOAXelhbtFJGHkLy1O3vb
rrGcefOV78hOem1muWjGEVBdrKtsPso9qq2++4vhuJIrlhfzup9XNVlBCVoT/2YxR5DIbGniMfy6
VbidVRXlMcxmLrWyR+V7SNxRqxoFRpE0Ex69tNLtBbvTZqxYrZZLiejkK1oHzu1p0/sniqGYrfLE
OhBh7RmpqoBzz5HPVWwn67QPCprTHGQ+vGIkryrQFsqxtxjNrq7fNoTFHaBKW8RPq7WB/qE9R20Z
G7xvSkiCexyTVJ0MwdALd2T/EWZr/vTJU4J9p+Su/izZ8gAhlfL5RmHO/+3zOsxv89mOM++wQgBx
NMCCEoCNPbqjlAvFsm8hkAqiPCQnaymoumv8VQZcQ2HSnmBCzym0PltUJ9jf6wRWu+u1wBJB9zMh
LVGkrHeapGM3SwvvdzFDD00Ml1NXODFSRrUlPRWDTRUJXMb1BcwqRj9S9t9TbugCfHL0qsZJ+CMS
zQrETQghGP/6iGwGneoxsjLZU/sH28l2AhVbmBMFVPEh9xp52VfYyJ81FQsnd/Xh30JpWwayQlSY
71zugoeIACod/ZRI8Oa1qua0eJPt8cILMvjb5cWY8h0ClqUeAN3p+SJRuANpOosR421O8lsvhczP
4z8RTS9Eoj6iW69VxenLZDdw70HzLm8T9lmdU55FXdNYyKweOG/xKcGaxxZYbatbN2HVzEBwYakZ
JqMRPxfnLBOT5aE16xAYedNH7qGeZFJTIQndD8F7aKmEq+CADYDFOT+c7ILYoE2C6V+F4NAyR6ZH
wXETQm+nI73YtwbvAGYsQLcUHe8LAaSz6rXW68nb/OTszYZ2utH1Srz9q9nVC8QL7iqrIItDLCl8
FIRaIe08PH7JRE7GRz0Z8AkGy3p0LVB0XIjas5xDvQvECUi8s0+qPSpaPFrXejH3rJkFHRYA1IJ/
eAV10gNgtBBpByzGRhIM7IV8Ig/amAYi1pPTNYMZPgZHuqGIlKiXIcxwTgabDeCjvien3/ENvw0K
47cETUJSZPm9Tc+7NVsMnyihiDF/3xznmEq5zs90wiVyv2VFgQfpvlh9quwNq2RcnWvqDJ+OhUOK
ces04AcShhzo9+Y8EU3f/Bof2Khy6gVrxkz0e2AbxwUwQdiwhyiygEn3i4ciwY5Sh2Io02uo0UCQ
ZcuQ3KyMJLzReAqTpoVuj6wFyoJL7F/kHBFtnYPofTaq9T0qEyHfINCIVDT88rTcaY6ojzppnQVD
QNOp+jHZYPbpVlCd3Khj4wR4JSz7RowOcWY8NY+hccJk1jSgd4YJHC4wrCP7U/m/floEsjW6HE0u
1D6h+vfkHQmV/sEY7lCv5qLzEYoQcxckpeo3QfPgv7G8xrgcNg4GIEqvmXGGAeIXloJXc/ZLM4a3
ue/zNtX7KkwQhxabo2de0EV5AyBZNRK0F5AQNMmJ8AJ0kxNFT8RnjT2DYHEkL3frx9ezJAHyf0NH
iwz5vyNMJyCNe4LkPH7yA7ZlUVlG2H9gmb2BewUdoyikwk5GiB743q0JOHglmk4BZD3KnUaJ+3Yq
CYRSvjpOEz1AWV+WCiT8LfKaUrKTpv0RVKm8StxAkJzrKrHt1utJOdd5gvO5wSfUkrjlDvW8SHYt
nBbZaR6IEOKDmSJ9M7VVLPpq2RYmP+CfJTZPo6TBPXZKH6KLEdQtzZAoVvHbDRvPV8F1030FmIT0
jvHZ1hYqlaw+UVW9x1GK2mDxymJwxzG1oeZZ3iel+UO7JqRBf5rYS8s2MPHcI3/2t0fUlq8/wg1m
eH9QQJ/qoRqZus6sby928wpiCLC8wKRgFi+8Gbkd1kvQtBzaJgh24p7DYjVLgIJdupM1Q7HbY5x9
+gb9yyixZWkNU25fcu2ORHx8eJnhLD+rc1TqGRi/jaxnygLgm3PIBXCfKKuR0Ytg+aSPdvlC+xvo
8IApLVfVo+DQU1jQ4iImQV0yLAdoCZUU9Bmf0aywQbKpdOw5mV5CYoFxVJXmMwjreo98Xe80wHHn
ORo+6X+vQ3jwoB0e6UcAbJAlIdKAnrC2eUqqvlcoKu3+BEUgquKVyJS+IYUsFPWHQ0/xoyO/3AW8
DCPwauDnxG+L/R1D05LSV0gU7Pm+jMLnNjBsWjarjzIwXHYSlK1G1sDXWok1Q077bmr88ec7aaI1
7FjuEl3WfRdWHgUIee7KBIVPdUi0Vum7mweSN4xmuYYoVcW/7lYessKXE7B12E3DOJpNxz2v+5lz
XBMnwGvhL0ZkzEO5aCD5eFUtyuOkrgmYhsnP6IxsxdieFTOw8cpJrKzcvYYx7w0E1AcrA+TtAaWw
xjqwQJKTSDsWeoWVLs8WTqLy0iNCP4Fl+9vpWOeyse+uLMqrwgPd5zjNG2U5/ek3VFsk+DmQqkoj
b1SdM+Cby+X5UN54gcj3sZV/ytqYOvAEM03wujd3Qo2xObCT9sUJ+5FmXQy5lZK3FqAQuEisPASD
6sJy5M+l4qnS8zgD8KoUhgiJ0ObyAG0edDNPc9/+P0eElg93mQpyulQgRjEQCuRBqObQTBl9zZbZ
w5WPtFuQ7om28WMsphE0edrHo8IQvZ7B4efjfKeBX2oxe/F6ZhNZMIBdJTopxoOsN6P0DT+BjRnu
8ePg9Ny0jrCvvAL1aL8yl3LBZzTDYoYcREsexH/qZVElXw8MliR5yjBDAAspoeasu4cuMiMw3sLN
IQFL1LUT1lbKXGCqNPTJZG+xNsVIDzt88XOQXCvfJ0BPz1BDyMPiOeO5F8yq+bxmjmzzzNl2wPVc
/XeREPjemJOZQeOYAfJng7t6PSkmmk362+uS1mA4HI6IwZTfEBkc4UHZdZkxP6yQKR2IvFZJcp+j
my8flNVCXkkHQnWtF61TO5ohQsSG9TMssrPOtruN/1uZ8dNVNdDwnXHSQnxC3rae6cVttHHg+O/t
Sp6/CybVYvX5uituYeS2fnAUr7GO+hUru2cHyUCboQEMhyQVZRCL0uMbww8hgTBFiCfn4fFA0PCP
xfxgW7yBg7i4BjksvepONYxha9ZvFn432wZNhRGZaZNk28RZJrrJ3f0ISPodfRfjNIxn/mW+58K/
9YRVoGWJIKXGV/euP1S6XKXa6E56KiyFzoWhX928gKlrjr2oCgDhHs2fSwiZinjqqQrjBlMwdewg
5uBNKw3wfx/V0mNlW/Lu9zOKx8D/Fn3y1KnoWqfvVE1+upiMEcA1nkpvcy3YNBnxqY1AnYCfRxYQ
/dkL6sQvupyiCvvrFVoeLzjsQHjLYs9tN1OPW987cRIIODsHRdGS3IUI11bnaJFoNr3DsKcXS9Ug
LuGzTCfHy6q+YwWhNxbjoS9SMyow6vXOQYynkL8zW7XuF+E0GbkJmxFGoGV31y7m62vdiV6O1df9
6ebOGV/o/P2QvrBOK6ToPG5lsXMLVmuOmDH4on4lWnDpnirF3SRcBq3/NMXdagMcZN62sv/uBGYy
gP97ujxfJg4ZJ4DCGKiLY6SFkS+qaDaFztEBZOPgNT0X+epWJuk20dJtH2R43Dc7WsGUYsCmMtqh
zrdQiqWfMe/y8QU19yabrng4rpJNwXTe114zZicaFSxxiamLi3ktdj6c5czJCiaUey/o3wqVitus
kRqb+R/7g0JC4HpAqvsXVyKEFwuO6xqU24HqrYiZuQ08kWfePnMMADPyuFKj0k0+enQBQ9AMwnxk
sAXL3nCaW2lDUwjVRtomIQhaCh0ovOo6VJVNHkhinpOFAuCPe0XT9tYtunOwm+MCseOego7lMiCk
b41jiJ536unCB5V9O7SmxSY7aCS9sChIUDVcT71CKwMeTDHKVxQ5K+8RyV95YwcQ2khG/M89ZvOj
R5EF0iFjNUz6YVS9uGAdWc3O0YQaR6FOdKqwC3UqjwJmETb4oBubfwn6O3qfv7Eb1MKGJJETCAGr
ephX5NkUOYdTZQuCmFtQI/dYs0qjCNPrjxVnJpBF9ssx+oPLLtJuKkhqIcPfMqhhomopEygumYw4
saOqdC3v3vAkme1aaXerd7PDomUwajX3nOLEecD4RKteZ/AodjjpCd09HTPlTeZgkhXYdjLDp0wB
pleB54+UPGXiVam7Y+cIVRyfpK+hYUhElqjBmMMqzrMtzvOM3mBK59g/rKl6hvTWBEtR17XPzEbf
Oo4I5ZsxP1oi0v+mOwW0LOZZTV14U+qQGcG4CHTZAx0GTD0qCWWajIXgz6JxjPctaAz1OO4RBJ9g
HvxpfhewOriDUihfmZaRy9ZIGzfJQYDvzS3i8wH2K9JLc7g1b4cG/yWgh7MC63hGupPJLqUpkh+d
WV6IUcRdFKStK+pglN2agP1f/zqyCHgnOy1ccgILbpSmH1AhTcaUUQzlpu80LMkOxv2Prmk6R+BS
XjTpO+T9g8eEYM+6U7pCxzyrhHwjZigwyay68vOdKCynKYwWpqUae+pyzqFUMvtI+HygahSXd9G8
F4K0KxfL95Q4a+GhQw+sf6lWYAXsVngDhP9cpfAjKeTrkJnz7za7NO5KBEouoPKJRlQXK3eTWLe6
ceKLn0ZvXSEK2+VwYhdRJ1DBRur3wCElAYvXlsWglPDrswJkfKRiK1m+RgPeEfhtv1D/ujAyzPd0
DJXxJ9uUNcemyvzCiXueyB1halp9+eI5IqKh3XHsABlU2KhxPO6mUJBiCmYndKBCfMtCt0IBaC6y
muKVFbYn7JeC16o5zlE06zeOXyQInjD5N33T4lSdInh2DU+6KlJxUJO0RjTmPwte3A61h+HjofCr
MK7SpTYYzjb+8SnE+A/NlGlV9BBaPIRaBg2fMi4iaZcc6ar8cLMk6/MhHq7RMiQLfezjvLLdNFlx
EYPAcui4YRfIcgpJS0QwNvy+3izA+mN6qbpWr8CoLTFDj0o8+EefpnCdl5vihXEbXTbLCmtAjFKz
4OVo8mRWvgTvTFndWdbehQb25qq3XOMXiIOqswHenN7d2N5++B6gCNQH9WAc1FsU4de+pvEgyBG4
Wj5ys+gwAT314DRDnQHXep5soE1+vnLQfa3X0z5bD1JT8ZFnhy3oqiCGoCY0j75yr8POAM0Nyi4t
38nO5B3UFfdGHoqr1qi5Xf9kG/QSsOPrZEOq01sMtgg3WRuYmHbGHajbx/hteb6G4eMDlkRyvG+w
cbQKlTZzsvA0LOxwTNv+X+Lc/aBCrH45Eq32wAQtFmb8JOqnDwmKd8+WvZ5uk9ZYXqqxZrWHTm4k
t5UKdZClxqG+Cdf2d9Ej2QSsmm9kUqvmgqNk9QRpolIDyhZxR7wjmF5VPu3gsC5/1NFC1DeEsb5l
+SiOyR67OyUugeK19aqoZFDZbM8o2QS51DHBZRn5ozBQ+x3h0CMdHa5bc5MknaHDqquuQ/LBskU6
7Pj2W/mCHksi0AlPxnDnJg3BX7K2JtIe2GUsGNQkzH/H9Lhi2cuSxOv+fsDV8E8H3Umhk+Ks98ba
4RS28TvDiDAw3AdhdsJfS104EWlNeS6xkpfU6kECvOA0uwvqoZCzoRP7zayX0mFYBB5tUvsMaqbG
FvSp2S8m+UwTLp9tUrdUxQ8eRt14VgGgvVRyEAvL4Qb0GfcUX4zt6Lg5VQ1n/XxfwT2rc+tRdRHF
rO7BlqUyDt5CkW83QI21BBLy5CtTXWeX5svoav6uPJKHqczXWUl+GIzhJ2RlDPNcN0WztAejRL3M
e5xMbZYZPuHk9Lg0Zi+cwsvXgFJXZJmlQY9ZkKWNx/j0E5J0Kz1CiYyUvzd0K6D/WqPpFrcTqob5
6oKzww7JPOsCOJ1Kl8Qi/vFizuYXyrxRCC1ejVvY1PxaRP/aA8+5oHIo3DQP13lW74p+fflLpAn6
j4ODO8iVGXsZjpfxvEAESVmLvBdeEuifTphnhGhh82JA3BBe5giPF8pLREQ9Y3+t8vrA0xGWwo1W
LtsqWZjHl0zyv95biExWBZmk7MJD+wjTAtmabzWIHKd2qLAAElbmxSRHXsW+/XTGz0IFfLAZSzdG
DRF92LMqejah5Ut9iLn9foSEsMWsmm0MoNEocnfNUEUhIiAHJ8oZUnvCPr+xnQbFlUP3FDgMkBdg
Hgd0WWA9cUD2lIwjcQ7zbIQWU0krt8BsYxi3S3c4E5O7T0AGnUh+ZwS3+9FicdQmzbOXjX1i6ZkR
yjkOPTApDp5Wv/kTzAUMb9Bng5rcm0vq6i9G01blgP1ZuwOOTDSMoqK78FurqtAbAERGHnTUWx3i
rNIF/txoSVV4FhVDXrN/bm7fG2f+tTaW0c7BzBZ5QgJg5kORiDgO+yEqVxmB3I7ikjjqVjG4Opn0
0JGKfl7NTqVnjVRDRng2fKA2veVwI3NvqeSIkgQS+SNdRDBlwb/qOLnDTj3j5SjL2Nv5oOThTgO1
YuGu8otNEFWpSqH5FK/qwk9AMD9v9OrW4oe12ZDjIF+JLlxYp5Cx2YNpEVwDlOhc4hJNiMwjsrNx
Q0hqDSyDLyfbTTYQzVoaKRzEX92ea7BDDcFCcI8c4ek2jzsJtk3plscs9wou1gmaEbF4pMLPWYDv
9Cs+sNvSifqLF3aRuVa4SZztL0SbJv299mbdBD/yQtvYGSdkS3oL82Bwf0xq11PUUU4fa7CHCPhS
fMHayUtmHFS8Q/a/mRMJC+w5gZEcB8l0tGoypIRdhIXtDQ6PnXTRVUgi6id36iTVBTQk9Wpaa7di
6TM1cp/Bv4TmJJL1ZJ1SLhUZE87JEzvtrQoFO7X+DE33uPaaP2Vb7kL+5QeHC1r5yyJNMswdl+QE
gyUA8/oup/QsLyPkSr3ijqFhzkoFbD28AqJwMcxllqVDAy1+XHef/4lKeoSyCxe/yak/kxVLjqb6
QBI4FL8P1ssRxEsoE2p6VYTi0/T1iPFYpZu2r74b+5zl1NOYsSky2tjrXcIr6pkbFASkY4/HnANq
D+IK0DlCOG/8RMeA07EUxLPCUGYA2yvqgVmrW+1j1OkftxWbTTA8SphR4qU7JTeSC3GvfFB/oNy7
uPCgM3TewcMLCHeu6Z7arJn6KaGEZJPnxGpRNqACRi+S2o5WD7aBWdO8a4tdbYriD36rQk6CQoLg
nCwdqz+S8d4w7s9YSWdivELPzDOgWvTpKhAY+sZwv97ixUNynDHUZ5L4gBfSlX7PqvDquROaF5fi
z+Un9SP+iLX7M5jioSMlqP0wKRGKlQ4iMo/wmtVT/csponcXDpwi/xxaJ0TDOagg541fGJ7RpOQ8
ZkOq27PSLv0yUqxSE7tBJasGUXBc/OTBZMVIgncUvtNNbLAhq1KkqlEnJHVArlpJJpgO3jpa0XGz
8P6yh679KobDQAkfgwfoXoRll6V+xCTuxibX3XFRFJKpfY56+eZpmD9TZwkNaYJnbh5r537dg2x9
EQZ3fx29YllSz3/9OMkz6M+sSqOKIBZWgQkQhB7Ulm15JAn3Re/Fuasmu22ggFgecO9RQYPbcZ1D
DkvHsD7lD0fsuhREUsyWAbfmqSOyx91foCd1PILWNZx8Hfhk5UcAfUN3/Sv1cRy+w6Oxk67i+DDn
S4giS+NgdOOQB8m8x/Bx766At9og7vx/F8SMYfJYLbbt3rs1jRgccwjCqywWm/PHbLnGz05rap7y
/l8utDGkByZSaO5h2elTnZPYV/qWSjaMVyQV6WLv46+w6coW2gPLF+FYb6wJY8W3snv1JZ/xsI6r
Td47Zy+DwQAskcuLF8aiTGA3WZK5JcgCpfliZ9d+k9zEjw9WCsi6SV16Dh0U6M0gwBxObbCS5vAa
pR83jGqIMz93HihmwqWUiaMsYQ5X+WpshbPBwhobjKdY8uEWV8ATMm/n0+oBfoRjvLD8vJiY5cK7
S3Y15NpTD/A351EMbAxSCeJYyPwv+mK27E1LCd/Lz8BEoXbOop4eGj9xUhAoFQcb5M9XbW8bBzY+
a15hhJ8JCPWcBdHRZeEyEX19edX71xYdxzeOYrMOSvTsqRiXk2IMDSoUZOTSidsDh2cmdOGMN2nw
DAJivkkN8/B4Tk7+9wqucizQI4UKcqpAsYzfAQWVitko3RvXvUEk1YzObGuuujPPqyYnG8lXpcLw
6SYiyEUA6KCfSl+lBfKwuH+Z+36PXkwRfapsjV0oyTtODaWav9xY4c+e/yQkGAkt4CBppNx85aow
HWmZxs68a7wDxTuaUxDdIx5jpVClobV/5hF7i87QwcTIvJeZ/UFW8vys3wDwCXsWz+Y67o5MATve
EhDSdCPiEQ78enTHc/LmHmEp/3IooXMb8YKgnKPMcNcKQrOecdqAVPr0JnRsUWi6KxbFOaMOXqpN
ygvmBBcJMKgiScp80Aejl5zCsVM+X8HRThtZcGaYtRBw5bCVvmpS1Tr4dGFLlIOKdsKg4NeOMLx0
TPbxv3knFNamKTEII67wNcs+/VklrLaZrFJx9MifNaI6jjBI0nxECNCsxQVOJKj1Ijw9221ptt+K
xa29ZSvKiRhX5sHOMU8ijevZ2RNiayknOlmx8XBO0MUwrMgOXevuuQUCyCRprIgch44jlnIuNrFn
LHiGPCmS/cra29EFxH6z3bo3FqTU6vAmG9V0raTq1stK8KH+tZP10vgDWl3syPGDHQr20uiG2IDn
S8bCKyOMHBZ4UfLo/MJP5kICrVmwrkDbEsVMdxbOqZuh8+5XU2ID1qRczlXvm2z6wiIPOwIF13uM
MQmtBUXjyuwDpeFyysXn8Cd41xOFzWO4LPp7mD27TsuWxRzNWYCnuoTdp3NnTE2igdksIAxzxVKX
U/0YizR48SpONmpvRicR5fgtABZBfYWrNnNIfbPQruxItwepjkBUV466jRL+0bNCEHi5xhjwjl5H
d/EqwCDEkG35PGZt6ex2a8d4HUHKqpVrSVMmixQYZiNr+6d5+Z7oIu4DlAm81cZALUhZS/Y7vO79
eFJ9+K1XtLfm8jXppWquJAUVLhEWsT8Qg6CVD9l/7Do2hqIUxZtPxKqejTY3RIAizjdoDgSxKa4P
O24k4C7vEudU+DbmcCudemtEAb2LqhRwG2VCyJwZt8BnbdDTl3bZVMMVT3o/Cu2T59NwNuRAXqtN
uSQEI+TNrgZnjEcMOFbPEo9ZcQO1VFK0f4iSo378S7XnBC0J2pzLUY3GjDwAhF1ATAz2eeehES7Z
xL9j+TpfMr6mA26Jcl7DIyynPGoCnnChY/qUbqrKIYDG6CNI3idVmRo7V4LdZQ0RDHcpVvrn0FpX
fkQOjhzgsQ0oqDcy+jP7ZwEhJanPFJe2vND6lEh/fg4/x1o+VpqQhTkYg2xECdgvt1KwNbq/dVCS
MtpgiY+syfAfHggmWFxv9fN8Rl3Iz8ovbf1pm6a4VtbON5WNSLy5VD4WMRCCdtB238vpKPu1yT/i
+zLdYSB3/vby674eKn4csCdZamwO9mZZ+JQfcd1C+tN8Z/+KlnsWBFSJlll0R1mHgVaKBURdk9Id
F0WCRyqTcGYRlQ0MjNkrcsbkQ5haR7BmGS4rweVGy3OROqDrRwr+CHlLaOIGwlHweT+Ouc8fUF5u
/0Ge/992MWHs5HvqS724gHmiuo0VK9pa1AmRNHzSVhCq57hNvissGiH3NgA50IfsgHZvRurx9B86
TQCECFIktCz5h70AplqONJEts8VjIJYFos/xKE6KUlto9lhtLQqZcpeXDktj4MVuZfy6DJfEwvXZ
HT2JmQ6ObViOyiLWGOsukFoZnLn0QoCKGVpF/ngy42l17LzzbLJi2ecBSBr1fShgCU+IOHyZJl2M
UIWJ6KrY6FFiouNNLiyC26OHOOWV/g68TEXYwkWDPqttronIB7kB9+reQG+nk9L3JfqNCdXRcS7b
LV+OubM1c7GxquXSKwSb/4BhLjHUhxX9TKljlh+UJ48RNuI9sLSb2pODLcyMHkBk589vIY2+W1xw
PZkmlpLDSe8QJ3MJMJ7iB5hv2oGUfQBov6doOb2FQqUEiz3+uv31L8iPxvxnFsjn8vtm7y70Vki3
v5gxcuzwBF6fhrECQ6sDmANRS8T9AeUuinCjgTbL6TtgIZSxqTw6WDAHtIyNQI9PFOaHzNBjuHLN
8W+h/Z8+7snHS8vYjwul30fBWXm134jMptEOYq2KjM+Xa9q9qGakddbYTgBfxuUwSSrCZWE6mpWn
2EqHMcbXhu6pu3jdmxPrbZFmobxF5oftHwdVkroxjA61UpswamgE6VLzcLaGENwgG+2l55uPXF3k
GOyIb4WzLnDK1kUjNMlBR/cLd/RDYkxryMYZ3tEIb/6hZ9kEqAVr9H37mg1LMM5NIR575VC53w9P
+pVWMDGNgpprvpf2/PFXHJqsJdmFxjpEYjrsJPMzojbJnNFcDZJeEcF7CMBnUko+Pu8ESkcH13pP
H+QjPv/BsRKwP/LkMBkIBUl2wngxT8eblskAQ5V8XY1SjJeSu/YemM0djI93XZqZQGRigPadMLLJ
hnKu3VdXg6MvVO7rW0Zk2Oe24ZsjYGiP6vcl4hGZZRbV/MN2DdsfotARY3PsoND3cWcevXifCQV5
KEUWVCZJzz+Y6gKfbHMq3GvEvgyhu6fnIWZxOnNf1co9D9pz0LkC8NjZHwtZhmOTB4eQmUP37l1I
IunSOrkJmO94YWbUBCwkXlJKrTPErOdzeC2DJ4gZ8IDwR6kHjCYN3pq0TiOHeBo+2JpKYsMGTDjq
RG1YdVM+drSmdBFBnPa1XyfqmfuTrZGozQ50bKTW8QoWftVE5VNfEozUExE6IWzrr/KRKykve6Lo
loY+GQn2/Tuhaiwl4rtPK5tP/wEW00lIbI7kj3FOvgXIwcudcf6oZGACS688Q2J2eCwH/FZb+mSS
YFKXEsx89Iw6qdA9idTQXwukHwGMGCQ0vkSPo4RiBHXW1ceef44uY6OwW+AkZIsZiChp87wrphbn
6frL786HWgcEVGAVoyDwr/y6+iyaID9CXXcZKOQkNG6+5Js0wJY4u9fD8wfvjFf02lhHtteFOyE9
m+dgFEg5NNDJnhfdmhpESMpIkL1pGjf2DGX2uYoSe7z5TUPNSyNDKd+y+HnRfkliHedpQ3g3Hm/s
sfjGM2VfF4VUAoBoicjkCCNh2fvr6YPMWwVxf4WsHYCaskTCd/Vz/HHoKCU35EKxURcAkeZPfAu2
a3FqpGoztvfOg72ZWzWbZ3RZa6KgyFT6XxqkTzjsKO3quktDXROpXP1rbtRjAjGEyP7pwOcF/7kW
afIe9plCBO/cA2q4NkfYt4RoNav2MHy+nYOtiaLaNs9FYER+Z2AF9DPNWB9r/Ba7HibRr5vJ+Ozq
UUodmYIpSQK8Z3zNvIoTpvmRJHAliSPAyNtFHxCNpNEaBMlEGYysWpnaG/7ss7GrgGndxz2AEqPC
uGDgI7hCImzEdvIpOg6jnL6k9UL7pD4ZQtV6Bvv9IyukiWQSvNhdpjpIkNsVP+kLQ9ozhN1QJZhZ
8Ils79bjDcKKpcTpvbDbAsONvYDrB9GjeMSWzrWUeNzMVFwINoBBBS9SDn3OCYPdSvcahUBJA2Am
YyLuheJwFpBm94Gq6vH9fsemmkSeE25NLtvYGWSLGEu43Kjvt1/jnox+cI5OhZ02F/S9xoZnNT/z
0Nb2cVIITEygvvV0c1odr35lsdBcJ9Qau4e3DpICpFu07L6dvxMIV8xzF7WQ+jyr98leiushc/Bh
8LqP5awOt83dXs5p5rxmBaGWmIRKkBecT2jd3qdJjT7oXo5l4KJLbWdo+Z44KVcsbyqPUTAsSgc9
RHuoiUwF8S+lladq8DDY4vu1WLaHsvX2ZVcvfxk6zE+0VMYTmUYEH+JvDSDfOQHjWp10jVDKirSd
mTpVyRM1ShTw+Domcb/Re6xmJBpDno2CUSgKQPm3M2Y8+3hUXbTUdLyYGKSzkfEplsYVWdL4BvrA
Z2rmvPmCw8K/6Px8jd0g9JhAQWlZrBKHSbX87cgpSmR705dMo/x38ebCW6L3KwkZ6a4qufxnyXyD
QPQgcL9b7hIsfYgLtbl7/ug5nDm+myJeGEwraq7W85PkvKiDGbXPtE4gGHCC3pXYCChQdXEUGFbd
SA/aJnE0M7qgiTdJW9Hn+ctYcixB9DiRAAKHX3QkYlS2WIZ5C6gc4oa1zVsGBs+D+SWro7ge6ocr
CO94jtwURDEpX83Ec/VrFtB6r5fKNhqHSWJIbGDu/lHC94sdT2p9KMEae/+b8j4/5mPm+1m3m4L9
aa40k2927yKEN4nt4c0WmIKgZYJDPnfXmdYALt1mnWHgswvUgzt/hazTjfoGZurGGs6bDuD3O6Nf
8XePMbGwmrihMKn7w6hXEfjDw0BxPMJ7F1J0t72J284EHqTuyXW5Q51l5Bje1UCKhiKdocx+2Q3c
xZKaiPmREYUJU2WdDpu9BYujswk7I4+HiWTApSKVAC6si+hqOcAtEdC5TjOvaEVWp3nqcfpzSaTX
jLu4fhHL2/rr0ncSG2trjYKPJcAa+S2PbNu9majUPBIxp+Sva+CgKv8x7V7ZmC6yfMBswYU+wTZr
qtIKXBSizewcMakkwdf0VykTmGaGiXWHfUmDgsgmF+S09V035hBkvSUFlF34uyRhnl2TZ54Z7/tJ
4UcMJPzoPKhStB/i9Sa4muT6Is8SYnIjKZVoFxnmtgCCfWMHhL2/y2PCgXVv00Qb5Bgp2/gitgOR
7LxQg1L6Mb9jhZRrq7Ssyv2P9Ho66+4NDV+3MxtEeiSSRjnDY6RcvHBNfVQKBf+Uem8YCxB1VIiz
XPxmwBb1OXNFama+0MYRh+xvLA62Mn5SA454MjZU/F3F+uVmgGy1PxyO4NXWf+ytPG1smdODfq3x
hdnGslsL/9mu8TSeTB8S7zHv/vIJUyDEALJ2bCFcCEojmjcjKoz/31v89MqEB4LJKaIOMc0OCpjM
Y4mcbn59m/fvVhIYxZfcrYEmg6quiyDOXWH8qblNgPMV+ddYv5B5lLlEZXnloWUzIaiMxDBh690t
nSkzAvy7NxFPym7b73xzOUjQE5mI1ao4jO2VLD9aYT3NO9xhf7B7AATCalvAbzTFk+yxdPu2JA96
/8ukR4+oEW3CA8SBSWCt1ypz+bfkt/e+0mjigvAIGDPxgysErtHP0Vcd3xg6K4mndUEDnLTk7Zsg
j+KqXnQxUJzTZKc36t/slgrR/9mhk/8Co7I6bhB3op2jfufCA/dKDC2cnFjr80ofn2m102H7V/qM
YgrFhbvwzyawNnoHJneq7Xp/kHrRF77x8I7V0avOoxhqMrY7MAcmSAMmecWZSfNo+hEMahb8pRyn
LZT9aTyDeIWbBc+niUsgFHvzVPP+04ZGv3Ts1W6m+qynOWoU4BFaFd8CvYlJam6Xbmoq5HSQe5bX
7zeic82e6h5XARkc6IhK9VSSMH5pWoz9wMwfTyfyUTPIdN5yfOq2exOclBD/cvNOfU/36H4FePuV
R64A9XcZpUrSUqFBPaI9c8reKd5Sx69gjxISaN9RBRRQuppH7HpGkF6cmG+ksxqjoICIEhjg453M
YMP6WgqE1J6ksFjldtPAhk7eCHWt2pjB70vYqAM9/kYYwNfY0m/RIGeXccDS3I1m97rgxCuT3yIY
OpDbzIra9L7gjeclYbLE8yYEnIid9aHqJxKPuWhpC7wKj+pvpoCAiX9QLztVR+udRiX2NZRyp2S9
uD9krIcKOg5813sl21slKb7vfQrh0ppko1mQjGkXXUs64w6PEGn5u6ctFbcWB1QBKI+zqIO+WzkH
w4V9WERm/6cRqV4pnM4rYNh/hhQf+S3f7v+eKs8OF/8JP6/Rc2J8hkMLqy8ftnMLkvc0yuGdFNT/
zBVKA9u5S8FlkrclGd1uiRMApioA5SiMaEunGanTf2DL7t7SCqRaJGxPQcan8E2xWVirtBLR71YE
Z6NRaRnKJ2GcK9xxdflm5bXC2pVarccYvyh0tjtbondKW0KLG1iEylckQZu2b+puWstm95/WXjwh
zTQm/+9bRy/ekhBG//FzkOZP0FBqu0ertE1rJpGVGRHBZq6g+NoDXldGG2pmHFhIzjGuLaxYrR8F
2pli9ySG+ls4DRYeajWVP4qMhEd61Wm8cLrmVC3AxBWJkL3Pu/VN3yfM4XRn2kvBg8cOM99slC9y
ycM/ZJQrvPtX+m3RetDm5+JB0Nom9C1XWG/7qujxW1aYqwll+QyJ2d3l5/msYu8S7zXFHx0FX7Om
BdNwO5HNN4bAHJu4irjtDUZqIDBYlaLKL5a0BRZaDxRl7+rk9FtXpNYsSZeQZvWoC4wXRykiA/ud
p7T1pYMKg75c0YWaAMVYc9MPnIeX+Oi7JtZTB8DY9Qtu24w1c6yy+CTQEBwuaXyJDTSWckEVQLCx
pF7dlrqkBZyfOIDC/sEUgQUP+dfz6Vxgas9uBT7BRTrqR65XzwKUM4MYrP22PHuRggruxPqz82pW
UXsEHjI4MGyHcUAJGN8vxq+erIDMxpq+TOZ0Go/bkuVvwK0YzlMz/zBAa5qJ5/V6OkGe1bG+7DV5
H1YWVodA5eEcXmHaIM+EmOwWPGV9NcLb6fq30bAB5Y7exwv63bCVxqLMDpthS+BpBKeeZBAaidCu
ftyKtrg6j/QNPzhTOA4YBaIzFwUKpl5D2MxAKuzbzc/VadTo8teqECWxIkJSly3sx8rk46b6SUOC
AqR1maz+O9GrXIF5c3yxA7UVk2hC2xu1iKcZl95xpkR8GDoWwKNZuObgepslnCV0lxcGsbF9NSsg
Ae2X5skhYUrz/95lIkb/ABa8Bd1d1OVBm3ux7AQns44fw7ptpjLqzIVPJzDXjW1mhvLiME0YgTPl
BnC29+eHjwwiviPemOvd7thEgvVd6oCxwggDuceXHgJ5ic6RGf3d2aGyegeG47g4fFgHKrXaWX6Z
LQJfO8hrAC+nsGnztPmiBdnnj0pXQRbomQOZJAlqy3kTE/aDMUfesrYIBd8M5Usza9nLewnq2Mgq
SejbrVekBWkqTmBu6mozWWheCS1YEbHtI6MQjjmhKG+oit5/FQZwFtyts/vWecJSgA5itzOTW5cO
xePR9mJgitZ95JnSSSksIf1UIsBWUVJSReSCAUL71eHBfimc+J/OqztU8aF60MUJ2VMAkORO5yWD
hsn+YqiHJ4qnzadDJ/1bQ9nXLe3tMRhuBmTLOxU9J66vcjNOJrmtW1nFybUizXEo2sV0azqHlzH4
Ayhek5WTMMaViWZwAi87bBfphCEaSkDhEFEZDE67wGHaWpEdThYfR/JV77rpu+5w+NYBFZojAPuy
E+aqdc39z0Bl5qH6RJprLajFvCo8RPkcmnHu6Ls896mil1MlWAoUe/DKGNe82jWFsHEsoWKr3fXB
tbLazRezQQh3Yp/J7ogrSHGgHOLo58/xLR2xOWNDjLGt3rEk00lqqqmkXFMI8KPdwnhraGeaS/RN
pFAypCJ/JpIxsLG0G7AEU4IjGGCURCIvYuhcDblsbkooGbM6yUrutzTAO+NRk3ItgNJZtVAbzxT2
i5Dpr9golyMWSSkXSZpG1VF9HX02CYn0uNObddVbHWJWXoZLoLDi8BH5DtQNr1eey+ICzHW0fYnl
TJN2rpBiW5lo/tmDWjgxxEO2aaO325k1N7lU4KEIFp1AozMCqvIMiBaFXQVNoyXZrlMBd0R/DdKK
VChA7zMmHB9DBs/eQkJEnmJvqfj2EYbR3WKaq4dgL2DxbZe+vlyC0rCDdOWcYN35ddqVH9JuJ1ak
po4Px2u0QvUe83adha1EhanzzZM5fCW4uorPiqRGRFZNSUfUqF7Z+x8Q2vxuhhTgMNTeodGIwC+X
J7LWmCjTw8V8kLc1W86CoabnNh/MqUL10pvN665w8x8GkYiUK81rRSZPv3PDERwlYvoqDHZzB5+z
Uv4nADsr7z7uUS4fb0wHjjS1mSKq7G04m1VDSaQrSRJSN5JX8etRIpUMosnv+iNMYWFSadQrbjAD
RwxDLQFPvWPTusX56meoHApEt3GG9wxHSz6C6eYrRRqzU/JBOmX2GPn111XylGngpDXZi0NClR95
ZVIScHG9gcfXRaWn9c+tnPfAM7GGFDJBh8FIB1R3z9gJZoIJw2sd7evHp+AlOL4+qGupXgUrYlPM
IqWgFld2zU9J5dTlMDlVxjYI+WXT/gOh+CRklhfMYrqLiIEMUog+8wQ83ONwmkz+rKh2jcC4/dYC
UaafEhv6oImDGHz/BTLlLjI7HUINSka1NyGHdwR9xRZJuab/1NhO6P+eGuycOls345MNsCETsbrD
Rq56X4cUH+GuasLHPyP2cvwPDYsyJYcg/fMERsHuqblJVL5OJYBLIImI1Di3ekHPAHAMdHs5X7tZ
gfSUS72TIptU2976rXLYzNESdajwdjdiHRpgNg/8m603KEpowSK999ho1UYIEbQJLvfdqBOsp5BB
SLZTrtUu4zTH6EVcLSgOYcLms1Kz2u+f39zG3otamLoQZUVRoB+qeg8+H4PPyEmMBrK+U27djwKE
1UR5AuF1wSAp9rFd9gQ5ifJvdyS32OMEkGpG5UFo3Q08+I+3jr4nL4VqzVbbd/Jq2tH38hd5zQVS
vFe8qzaYnUXmyCBU4DlUnjMh7OULmAD7eFDSHjhSU6LnG4ei9nsExMJPaNbCz2EcKAWKreEtjHKS
zuOqet9Zlhmy4WZNhLTinvLRExVZf/mF8WWZDtg27rAAFuZgnX/+NhJ3KN/WAkL46LB+CsJWmSev
IlnR4tVu230xw/VweXZ5pVVqzgSh+qoqxcHiih6KZbrmgr21O6X5JOHsSNSMcjMlmoRz+SAgnBRT
Yntb5lAImhhe/c4m3B6xA0hB65+S4Q6DTdFqCz/inFnJMLI2FSnL34DxW6/N+KjVEafltBOdHDQK
V4vsQJ1wZFWLxxUhByNRvlvpX4gqzm3+zMhSamJDqiY4JgR/xxrV2mr5KtiamueNhahflFkl4+Qb
HfgLMugkvH8LeukIXvx0QrdJQj5QVkKGeoEreSI2TTncXfXAx0FSVlxZvdxEYqn90ZrGuGsGpa3A
A9c5LcGz8YyTg/HvnupYwui7xu/y7/9J/X7PTn3cOJPo1XALchmqFauORtbnKmQpMD4o6lyBKT0p
pkGBogaD5e0Jvd4/anasAD+U3rRJOx2GgjMangzfsxSHL+uymK5vjTDIY5IzJfpmKX41rM4Z0DVV
trXTW7R/9PcL6c9YJ3o8eT378atpGj7HghSwzn/1cqqXsmCIcXPm5b/7MKrr6QEb6qkGxjlXrd8I
8KLLvgr2LdxzzxzIOYQWDrwO+hV/wedNQ0f5yk55XfhNIUMuT1YUegPugqUZGoSU4tdn5ZAeWokj
7ReT2FC0jRPDKnl2cXAlcYlOhlBvX4/MdrqyHDsXYT8uYSkQELcAIlMVvu00QgtTZTY+qzz+Pwzw
oXt2ksKJfYMD69lUggqCpiASt988dEida9Vnm8Z0P61XuaeXsQXa6vEE0G91JsB3AIZ82ZikYmij
g+oMsBfhv5rgxan8dJrsgEc6IRzju6tTkzW6cE90biveuwJ/pK56CcrdlmO9+b7+VGNU5HgNeJJg
dFf9ZZYv/7AWYdJlAmRVcsdk+zIHZjbBx8a+GNbo76K+0kcgPONM68+vJ6u1J0EtZdyUnmtoymZs
YduOnG333Pld3c4nggSstbMnIUd/5LBjxlRNDTRH0+3kq1XVaxjGgfsOP8Yq0zpq7cnVhpWMRgw9
FbqzeXjlSZBIVOvDeH3UPEeXAlXCRiCTrChzNgKHdIH8IGwan1auVUKpE79QGwp3O/o5zEETi0Gi
pHEC1FE8BlPlCtaRr8YMZxO4RnuTXQoCws0ocIFlxwj7MqxczHeYFea/pxKsRSGuy+sNyPkF3TlR
xB1Q0HQ/0Q5XJIK+F0K44llNpVS+f5y8JjScEYjORoH40aGDgjfm1Y1GbVTOY81sdLW5sHq0XgZN
7ixzc7bDnsqfDAXk0BJC5IPrLIA2pDhheCHdj1qUPH3yVgcGLQrZ+47Q/bu8RFGyNk79mRyMW0io
kjxc5nANaUTdWN/+xfqWfMCFsIZ8uUZveRzFsrj+9WBoB8+4+k7vuKuzte3s7vSdY39iRonGXwOs
TqQz5VlwEwcwp4AxkL5EMA6dPCfHFccxevOYBsN/2OFxtmyyqXCEyI9uxp1MOj4CYUF9424iDK5V
LdlNZqlZFOYTkKcYV6erY9Q+fOcGk2LWJX/FIPrc9wMnGzM+c+NREBK5NHxlU+CyoS43LcToQhVD
Bl0zdgI06lKMg+XpthKhdLQmeqXgLzztxKGW8KN1oZHGu91rHsGhraz5i3ESQN/zSVriFB32EJwC
bsKB081U5S8gS36Ai3lNNhkcQDT2MkTNeWAkXWbOhSD1D6H4drYCOMHQ2vZhB23UhA6bQ2LXQrNP
k5938bkwcttv0L8gDjwgfj2xVZvDiqbxcx3uymrszejnFizbVZNa4DZg5pmdFG0bQES0/H7gzHRA
dxVkA4HvlJ2/NPi74Su6lV82WWNQeobUYJ2ApRyR86YEAmWWEHA1BQ+iOrt+GqAgzoir4/8GrZv0
vnOS1UYBAWUx5vAYd06T753BnmXE43j0VYfe6YdRrN2NU0CSM4+wqADWAe12tVC/OrWTaEHJS5zn
3wiio8Bh5BC3rB/Grel3Sccq4DrIAnEy1FAMHE6a7g6BJcXk1lY9PRnB6InU9YhCWTCyARSX+NU+
kxZBrR0wrxRJuFLWeQ+jag/ZZjA5Oxj1Gj8qtB7VXqMKXdBNfbLq8uwmo7TGdoQMP2UCMeXTyJ7P
Wq7Am28DpX/eqF0+/oGg7YJwVhALsyS7hkRV3V4LG841eTY/PY8ZcQA/eBgQ51SuiMx4WMe77dkl
JffP8twtNOk2IIbjthUeJQiNkr9duQOcsDRTD0DBGzKrKbRnywu4NIWwGVpYsr1DCwyEWA20XQ4d
HxDHSQoMVH53/hexBEYt8/+zW5lCWY2qY5TeiIUTNosCVfG/kWTvtf6rgWR0YWX/MlXF2lsiXFJY
JwemEWa4kZFrRqzzHPq0MYesB1Em0X8P8Atg1PwxAWZov69zbs1C2344+/h+eM0R9ykLxki55Fln
2p21bdIeZGM1RFKKZNYsQDVDJPF9u1HVpBwbI1hX1F8gkx4qYSqIegFt0sQG3HvNcIJ9bhMxZWx0
ByI19/vR8FdE+cVtRDgtNUBb9uW+OzV2YvEhR1WXhPUuWMVpQXNKjljm8jGNs+QvVNEUSd6ZaKzU
DrLgy/f4p59pT+9S9h3WsFloU+jIJMhuWBzgY7X1m5OzFYzEHDelJlcams/dQJYpD4++npgliUk1
hz3WNqqvsuWhoyipYLxDEmQWc5DG/vBHgpiIfe0gbTZHTFuYgzz+OHTQEYZFSMYX2h8KhVjCLGfL
zq5E5OPBEq8SazKrn1UCxBA/XLVuWPsEN+3ng2ybV8/LNkw9+ZX1vW08JCQFppBNnk32sWJ+qy+s
6rM8jt6Rf2YIswPJ9BOX0F8yXWXuxUuL/uz6KTG2i99b8vQ8dsibu6Bvq/V/F/5ykj4MBr7xNnU6
oMAg9P67CnApt+1C7WFcuO9ulABGu87XP04y5ifX75zQ1BuzGp20UK6p6q5PVBTYbBObklgcm9xB
MLFjVt5+m7G/VK3DCsuSeJ5nVFr8c77Sbsys5kaeiR3mlkmW02OY31RHbZFEaqh5rPA2G2904u+p
7LTwP0gxMRhybnMY5ynVGG2KXF4fZexGw69AONhy+h4SCVEFgHV+0f7poFCnWbh17SP+3t7PvHgH
xCaUASK2VYDcmmqRSrTizAI0i8MMHaKlI3y+jo/6jQEjWMEY/jv2OmlRu7cqm7WKAyUB2ml6GYiE
rwhEn0n+0mFdsmsoiLNgFqw47Ggo7z0z/cTf/GBwr/muDB1PQpu0yP3shtASJ7B8eHF7BnQethQo
eUGTCptAmVbmEHF1TVvdk5Gqlffbm5765jOIhEb4q16uuZXyrZdvru4f8ucs5PGqbMaAs6R9EKan
nj0Jli7RP94+1sfZtmmNd8sSyJi5CaBCYVfwOe2T723af1mJ8qXcRPI0UoBmseJVPLkgW14D9DlV
oGIWzjwVnORyou5j4wPeQ/LmviQRMjRiW9GC3VKDYQ+uSqpSbCnsQZPwYRlKmDCZi+izeE0TPOQU
CKthq9whyryBWmXs/1CbmVCciXpCBt+Ue3MDSfDw7ZB+Kv7mXyf+zILdIfeRQgd7DTwvcdmJLltd
ilkNyxI6lxQ26wyTrVZBa1hecxqxL0iN6tEGAeTLRwFcrhc9YasZgcOwvwF4XYNvfNFn/W440NaR
VT2dnKZKjGlNpw/4xkpbRmX5YD5QO3nt5nC48KNROw6QKsj9M5XqglBw4BZl2snA6sNGGE1FPpPc
4aEyFyjYTK9HLUdLYnGTSvCmvbfXpeIos8uCcnvSHyMjnoRLYWV7PsjIPetCrKdZ5M17dcZhZR5F
ykn99foBGohDkazfDZ637zKd1tqCryqpbUFCHiEEDLCz+a+AISQISBsssfIWwq8i3O7a3zcPcP1C
RA605mXQMu+STQ5fXfcvwvPK2mM9DvilMj6EvT7SxKdMoTHNJVlPApSgrR7tq78oUzXhd1d0T5Yr
IdUXuTa8QwbSjF1wBh0NtNLmfwoSjn9YB9brVU2qmgQEkW8mOaYkY3MI+byQPRyXwRGvww4BB8Nc
AnAZjNv7h80ReaaEzE3Ef1qnxI2O+mdV9maXQ1DzcQc08et85SdnUm3fwltLu2C+NSnuDwc1JXnZ
vGTnSBvoscms97Gfy4WgBFui5hdtY7WY0tUSBxk5oV4OkgXHrLa2TzKv89hV4ANkY4b05cUt68ke
SXEG2b1rzEK17zj7F8VSV34sFwbGyHWCy0wypQDSquslz7dcy0ghalPEycyAr5h8WW1SPRo9Q+X/
d7JOJldD35iKKVJqBJnoZdqLeJvQ680CR2+qwg41l0OUvRSpRjHhu/U6OL8ZnhPKeOKqO5u0qQ9p
bw2PZ4hDLjHT3xcwNHEMHAAsxn8oyIlz0rfVp8XXvpr/jFkwZm1yT6479SAIK2VW7B9F9Z6tltJk
8lSvgEafZRCOhZhhSiGDrICGu5czHqo6U4w7TrVrKdMTDBhjuU/1ZHYVHhM7Ja8Erifz4N4HKTKg
jWaquRl5o8IVtw4kq7xb5VvFFJIQSlb4D/AA2+NZU3xtq5NMZksSEBUkhm3EsN5iB88+gilg3iVA
nLLt8/RX/pbSZviL8zxhf7I0Wex+ccx9Zkg09q0u/pvmpWLSpi+ussPmattyUpRW9D+Zy5VWdhhM
Fox/B0gg6O+OBi1BUyn/gc+2x5s4gF/dJ0ZFQ2wNMpOe/RmoomOwDjUQJei63oXqcFuJ1FxuQiSn
FnOaDko76DDWJVenjJetFk63Eh6EVGDALWlt0BBacilPyOfHdAxIoJpZ+H4+kcpTjUAqp1EUrRMN
Q/iBmyXcRkOJ27jfyfnrW1WLy0NNhe1zZu22LVspYs9m4RcJQps3xLa3qLAPiX7mmnTaz/BNFJ6j
BCeV0216ezpKInpg5pU5EPtErYUGoh6+59/I3Nzrr+pM6fbhcniZlwp5RuQNrS2g5JYGDJNqTgDB
o+6JJmD6c5ZoGfR2dYGmDzXO6NbjgSETT7Az43Kq15xF6b5aDCLk+buwNPGo8Lt0yca/C56GcbMM
eVOXBx3NwAbnRkI1cie62J9M3CDyOMav3rqM3zpb+waVophTV2ml/1h7HJuV5LmoAt5K2oQTvZWf
KPSOWVC2ZNXxfW+BCois0AcjnbuIzUemOg2tDfpsK/HV4Bcf1RZDqnMrxvKP3/nWxDQBDFnshj7Y
Lkdzlxj1wJPFGHMr1lpD0I+fCvVlnS92D335hqFy/HZwEgLhBWWV/SjKCrN4Kqnd0P7xE/Dr93oJ
yiwNgLBlnugWpCZr2wgvNYIUYjoy9wRtaEmI+xMC6ZbiDqIkaTs1WR8balfn5HtT98sdt4Jm2BHw
0NXEq2cobd2JJ5sQwlna4F/fbx3hbc4LGzIWJv5Bhq8Q6q51Rbp0uuvE7H0fHrzZeVJNVzBiKGke
d7lMal10FgHQtRa3iSMn+1WrNPl7Chm3zird4mYRN8+BUPBNrZ8ObW6u9cknZFm1Ngy+G8fcPKL+
5fsFS4goK1eaeQPmAX/kmafxnF9dcxb1zNAzVH4SnwChqj/K1elw+02lZFW+5/wgEddQ46YO0ppJ
YROW0y31Q53lKeTdcPBxlYHmYMlrIPLbHBYlZTXo0bcKTjWP7fGCMUYxO6bs8IiFvPeDf4cJvvaw
3Q0e2FpyIUHoEfT/5CRz3SBYPHd04klbqGMuFDBWAFeUBylu0spTPcmaZa6MTNQm8wxRm8LRLcLV
4ETZp9wVeP2ClIOTuYHzAhPGUd2oUaymVT96urCVG7SZVtLdSxQZ6YiPiP9DE1+we8waRxznDpJr
g12KTebAsLr2pb5tJis03cRk+kjMGfeX+6hKkbcAxN9tI5CzGbR+v9LIdGaFG0pnxipIKxvPnHG7
1k5xwppzYGyQEvfuHjR2Nuv7Tv1rV6JrGM+11F6PwHLJ8Q5MYCFR99yKsMhYDFgJDCcQZuTiFNy/
dBAcceMu2ExpZUMOnAqQ6jZqxQvnVWRlho4T4oU0OvXBiULr7d/WOXZtQNyuPafC/yDfOqQa5nTD
umWVsfG+hSN/L3SKtJSNK5o3fu2ay144lc2KiFo9ZaGUIcnWAzlrJ4E2651mjejaf4KSayaDF1oy
bOlB/YR72zuJ7aaf5+uxDakO6T/LTPeorDb/ArLtc02XPpx19Psp0JhuT+GDMlUeutADdpTA/KsG
p7Q1UxHk0CByutlYqdVTJu+tbcPULNr0Ali9816dEM7Koe/m4XihOj9rLk2554UtMNWMhOBbWJM5
p9aRjAayYys7l7aMOimGlIJMypovx82SBXFxy5K9z58DCcTwalw4RqFShfmA2qiqk2QbIdWwb4EV
8XTNBG5F0jeLmcjwlmpHHL/HGUPLeO8np0rzeFwM5jN4wamKIfWjLUGXl/WyyyuvlZB8ZE8QT0qt
7K0z/8vAPXnEiOPRMi4D7Nb5O6BR4wtwRLqUPJg+7SugsQtNqwzDtn6qAKQ4gIoVyAdqjV/Zedto
cbJ4xMP3z0O3SD0zp/6ANHk4FmLzaVNRp0HTHd07hKclMF/DHnzgCUjrQuM41yGSBjOxXmJfcRW0
/oqoeKyPwmBhGNX9fsZm7Hbwbaz9EtVqP8JfoeoD7chT8YAI+kH2pSv14o/e3ojyijb9y1ZluVyN
ieKtFdo6C/vKXMmpqKkAXOPM0fsHZuOkQDdVJ7Xbf/ekzy/p6qXg7BWb1OjrQwLHCQasAFGLKugY
G0QkwTavTPOCKOBolRBzQlSV+IrQuIx7qAwRAMTFY340kAXSkDnpGSgkrFHk2GWqyT3fVZDEvFe4
BSMSowd4a3Ye+nc1QCs6fbVlIVqyKBcMIYAhMJt/FQiNwQplD0A+LCHNHbbiUEHfyRQy25GMZD23
/+8meuNZfQp3L1tt4d6IgK8Wig4PCtAP2v9Ny2Q0DHA1xw2xwK+N9MMsA8VbvuHr42Dw0DkxDpnf
Y2U07Vtbv52v3gq23RbnGgs0fUK1pTx7G7HeWXeYU2bus6TAoqTqynCbFR4rymVqO/cZJnbVZctW
6VdaqI5GEkEwZ4UIDIWNuMvOCsiNSHrLCW4uPCUTHHmo516LL6Of6FAMZcA4VZuZ9RRhz2rSCJK7
38XZFSltBh0xTwk8CyKhCYjGxhPvzTGXJ4+lV4xfMwN+ehBNFpv8tGuGsccJ3/6SKTvt0MrEbQpC
kcRUl9fbwgaNMjiqMDyw8TnFNlh1Ek9HJ2XF8zFjAq5BKGVpTd4CoRBvHGYil+50/gP7XXAz4T8v
3rU37igKf/xIKvAyFLWSiHh18Thraz2RzWFGSP855gms9WyuykVBTtJtO4x3nWpQ9wsjLqf+dXdj
URDZ9ClJxthXUQpHIDBdCgjHUFDt+6UXHsPa7wlA6UnMbyyWpFhj4UuLVm/hDpxeEzdNZgbWXc04
rbx9t7HpQh9VgdGtI+Zs/fHgbClvMtEYhwrS/ck5tHyYZtVcRw6xIIUQl2FobWF8c6B5WNNQUb4K
4cOjOi9fPdS3ucm0tbeGfsv/9hHkah5bd/BoKxJQ23ERBErJ0XSJhlHuAbgrdQZ3FZhpuvU+HqaB
v9Ol/fYm6jbavglcaHbjK8q4ZW9K8Bh6gq1ncOGn28B9Yan8UdBr1a2g9Xg8t/HHbR8hrNJ7aF1f
wya2F38g2a5TyZGxwq7lWqYCRK7WjBhLZMhuGFfKGKf1+dV4GvkPYa6+1q2yx4BpBaq3iISnZkOP
mAWalX+JXcg/rtYlIuqjxYn3uSZtG0o6d7Oo+tdo8vUT+OzHemzJhSLXqNwLA6VcB6nag7vXmshs
wwftMgTiQaEQsWcqk/Eho55vMvdg6FibpAB1kMQW+XQX9hxX1Qqk6N5mq437gxPnamVJPCFWFQVu
q7hXH/q6h5BKj0E8RUF/uFx31n6lQ2Z3zR4dVUnbEydpH9Kr92gb3gFT7bnaZ0Io/ccj3/OLN8+R
eD9QTDPCu4nZUDJXPxya3T8tJvLZo8WqFtiCq9llw5ujmJDpvq1unNIToFxqiOry2Ee4xGuQ5f/J
wz0iI3Tz+HtPhXDekEgXQXhk+zVBkJTMLlEF0YDFgVpQ5dgEHtBV+ULqmkKuEaSg2jdA6qZsu4Yy
A4brxPuDL5RgGaRj0nT9p8SqSB28+JGvexsb2jvqvv8YwVjsZJ1be72K2x1K+6ZDgfkJBVQvFlbJ
sqUit8NGDKJlrndLUJmDBb+61FREBXdmbTBE3uKtMGp2w2PzKEIvYKA7X8T8I3TjRKj6Wzr3AY0A
L+nOlfjsqfg3vI6K0qMeJfc15y9653qForygGvvfGUtuS4/AU40rxd+LthUosdmk2rocfQkdl8gz
AgGQHteHW3vYQ4suwv+Jn1X8COxK7O4ua1QGPxnRafMFGjba6tiZ2QPRQQEvXKeBVDiC6o3buGcH
S4Y8mdgCd/21XrJddTfOpis2AOzwZhl/IakAm5JpyS3FJMwuR7q6kLE+pXp7xuB4UrNHDx9gWg2l
lDb/Iz+hbK/J4v+EDiIxg9oASfjNvYTHAVT4Jo/zvcIMeKFXHy02oHYiZwk/ELcLhoz1VpUuhlbL
rBc/SfCtZDFb/dcnL2q6pgbdcgGdPy1qZchALwJfd4nMHr12V23aKsRBwrbDb3qA2YepWS/BKD3f
iRcfP8/ioUuOXyYWbsNq3sBEzovTrJ2Y3AzianhDxQiG9Xe3btgO5S64BIwvHqyE3Q6V2R+Tuese
xQAE+AgoebMYX3e3j4eFyHNOXxdzjxQ79NwIKR1J3SA0eTBaVQPT6SQ3MddvcsLFrAmDq+z0tyuo
diWFm229sPS2kF/3V3XikSrrrctbE6HRRUz/5p2oTMbI8bfHS0C/gmfjMAuzNgtuGBSYHno5ov86
pOEQiuk3FlqWRNA9EY7rrwk53AZ/Jb82Eh5JnmaPYnazNrhytluejjW+h8zboqvV0gY71bvS91jW
csRPtuBmmuCo67Ugmv4pnTpw5UKyf23LIHHg+tAvJWdB29J709GDwKJLLX0bXtnUFwcks19NdLMe
qM9c3e0FEISHgTcjs+dtfwk4mqL+SQf4wlaiMut6Uei19emfrMcuUhLA0W9meBZk0g9+Mbk45vNl
JH5BMGOhPi4LemZtdWHHV4B3UoD08IuCO9qZ4PwyOokmSdRf98DtbMBSOJ8nhGu5zGU/o+4IhzEF
DrHsOT3IJnXmWUPasaw7XMFkFDklaEoYYSn3WFk0DFpZkhzu7Yz/4oVv2h0pbQnLwHbPNHpTJpPj
XKAx+AQj7FojD4I+EdNodyVoO1sMFT/obzmtTX6z/FoVlDzJhgBjHpv3D6uBTtAfV4RXs8E98VcC
I8U+icNGKPa/p1w7/+Tdcfe69HVBg+WtqirBtzZEefgwKqQ1WD5/JehqON+wggf+rVK5jLXjnaKl
XJViUBJcQAIO6+1Ln4UiunR0nlfwYJcUf2iR/l6KDwEVZO5hpm8rgOipAmC9U65DtWodZ+mZfzBF
zbwDhZL5RcCKkXt9FCTVsV/jLq5Gw86o2Ay+0NKV7aHD8IkacRMa7LdxQXaE1MpsIt1lH1S8RNu5
w0zbHKOtfjyx1skEnqiREQT3cQVEQFm6bwlz52gy24JTeYQSFPZFwKaXyj6qxBJaVW3HPurZ2i+y
V5FfODHtmcPnWOobOZWRmu5wuN99+rczae+BHmUqlCEv1XKOES9reC0pgb7KR66ffay369f4Kvuq
UBTLvb9yAH3gJnl/N83ZSXeO+cS5oWWfiL71kaciKN4AduxnpChTpCCBZHa6WHaMTt3BuT3C6iZE
/wLYioqjzIEr3PJMWUEzTQ2aEOWJkf6vVOEDcq4oGH7JvpfOsU3/sIUv2sJUpHBAEVPdj8+yWkkl
uLem+OjpI2E39Q2bEDK5dyDetpZq+bi815OM4a/UbJCKj2uIPSpPqUyO7ZGDyjRKXwXNxrpIVhZf
gwJrGoKf5sUvORmSld6SVoOM+dk8eVgsDdd72MQKsRoZpPRGb3gEiFtnjLYQNjONTIMxbSppG9ex
F54dX/xz0cARvByYihmhHtrq6idtnBvwe3xc6ns4jqZrkgjc6O7Q8RTj3Hihypv3bXFOEgBWNazt
EvdS4cMvK7TUgrYujk5taxbMU4R0zkrvkCm2u6iAflWn2h+k7TfRCCuqy1GShRYn9C748ZdY2b2E
CNDtYKOaeSw2tmkk0QzMSRm4HAwrKOKiC46+cySJNMOfDeDfJWSna5ph3syJN0iB/PoNPPrwsIfU
3sp8WqMjqV92r2XPbRetrzgPMFTN8h3eC3rHuy9cYTOZGusruVt/X0JdzPyy+wIKGjrcBaiFfpiM
MGas3wdYcBEt0i/TN9vB7fp01I9ucEqHTbA2K1plc/fMJEh5CK8kohnSW++1Fh/kPozYUIqSDig6
waQMbbbgMePvPp+grkyVky+eIId4oVDUazGAkBraqt0xb4Fy4UTH4pl4wJwc+o/rH+9qRVCA5sr9
b0ofewZgcpYYnyU4tEfdWlGKoZG3OQKbl9YX+zpQPOTfxdb/BTFZ7836G5WFN2C46gCeZCQ43Ry+
3YW+E4d2so6g5CIbT6fEVBxuwW8YTJULzkN+IABXy2FolY+S7WSPr8UADjgOt1fA2TDeA2Xva5YM
lpKGT7zJWwTMgJViCq0jqy1TAjERuKClV4K3w9hhd57uqkkKpvAGMNfKtXkoSuMnT1dgqTQvpVW2
EanJ79y/Dh3+Cobe7fU1tl3NL4/KUsoPqq4Tobr11hdrvgxFaX4EL2twL0e2qQ26fPo4Dfx4780M
XnKwDf1prh2jz+MbjptjCTF3rMqqEycNCvaeE+Xzu8wgOIHYndtw/jjR7mgOuJ/Zq9HpfMSPEIV5
VjAUnq7+TXS702e/hEK37Cct3u0/rQAEMsmpPimehTYsbSB9hoATOENXAmPzcHq5c/RUFR7XtTCr
j7a5rR+17WVlT5S0Vj6AjZuqKNxOeKFdO8tBByuHI7fCDhvcEXwXa2O0ek3l32sRam1uYymAZY4i
TdJ1PPJvXqhNPxQFHppaevLNcD+IqzsFfbKBdXzKgRljcSX6cqrDl9pidE74qoe1yTmBhX8OWZXZ
YhBllO0EiEmuBSiSscYdg4Xu/i6mjMoIXd4AZd/VAD3t1JCibRKYq4WOoTjmzXZn4Vh1HMn25YW8
ykbIwwWa7+bKXYgXxlsZgeBqatrAQaHPGdSKCXXzR7cvlGaJeuBbO7i/BZV+5SuC6tm97SRwzUx9
KGLOj1IqlFdwdwiRjjf8ZOpPvFxMKX72OsAmq6Ep8hnivpYvVX2g+6HZO66jbWurqOnEC0sek2I9
XzpN1qY7m3Sx+DTBVSWKo9ksRYDKaLVbLRlD+FXVHI9duBr5+kC/93EaWJdDpFPIh/4Gdi4cYUQU
0/+TAqHLPOl26o5HTonXzfgodEhU6Mfwh7Lx816Lcxr4egHWwaDDztusrL+f+VkEqqxvLJSz/ebS
22pXxW7g6NQzWdyl05on7vQ0roQV8mB4CQSKQiLkHgIwqiKbe14v+kXhbCYvpwmFDVPm96aWYEeH
svJGbSOpvphGn2sDn/NrgybInFwunYEHwRcUJmx3GDb12sUGda2vq0HzN2Pqum5vWVvy/OXuH3yv
nW9tIUQU28uX6z0158lwMtF666ggijlb5U0pzQgJTLJHKGAQBOs/0fZhc18UpZpiFMRY04YUzvcj
gqCdDNQ3B3V9kyU5JLhBj/N5sMXY3jAWd8YCFhMHFaZCd6JlYoeoMxb8ooBxwlAbL0P+ylEtZXTE
EB8x02m4WOLU2ou5YHCzqAHpE9z7a08RUYXD9KSEgCGdTtCSEdw6NWAw7sZTjGYlLwvD6sJo+YEi
P7pI+Cqtjhz5lTvcyeMb6ujYREDEGlvGA/itZE7mo/Z6tiku8r2uw6gHaV7Kv/sPhyoEI9hgQUFT
M5mhQ8c7l+0+yJtaOKajNqd4cFgnFwNTwpGyLpG8MPq6U5x49s3HltZacviskWWMNRG8sQslICwB
JCiPhelFmP+cxKKKgjCFd7dyiM/lCajO5RzmYCdxlBuVrdwdz4KkluENnqVcUXOrr3ov+vuC8ppi
al4WKkQM/KdGFgGu6JLUlJ2yQzU2U6Yzh8Rg0VL3bgoEZFjyrSATJARnUQDquTU+SQa+qMTMOWR9
AK9kk6ToxOp7ViJDZonY/RjLVIK+guqxWcCxtDH20jKQ2oZTEvwEzU8FVcvavS31dDFT/CuHOZ9Y
IkJUwldy0hDhrNmGILo6B1HVQDnbk2S7NkO3r1s3WqcDDI2AnXsJh8R2Q0b8jsSrXTiUV0UO97X8
XoA3fcKZbn7CptXABde2fUC3Ivbjv2wxmD6cll7uOU9pf/bfdGV+9lQwt1h6fH5h2dAnCn8uacD+
MHuDJwrxRhdZ0fr52rznajtwuEm0TZaTFzNhpZAiTXSaASPNpvLdxNvmKudmMmpR9m/WfXZKDJcC
86sMDnO40ecJcXWwmd0lijMiCUhVNY7jyLXPMRIbyDfW144Gm9k2glxIUeY2EFgtUXBdDNY3tDh1
ErHWsYBxbzfh8wu1Mjl5dKFtwxQhvFJDSgXaBw2od7bI5U3ASPPmlEZgTf4qU/pDsK3CI92Fuxmp
lW9wfUVT+53aiVRV71dhAPwlzkc/pSqmQIVnNeieMl7AVHeTNfyTQV6LOzuxqBUj/WGaQtmDyBsz
+AYAIzJ8eDN7Orls2mVWP3eQO8+mp3+f8ykW9T9rAi9usHpZa/d6HSjNC6ruxWwfH2AfptAWkGvB
Q3sXLsJNGJByW/3egSYbYITFKTlFw6xucA7eKXIEXwvt8Th6ITw8iNNKebXkewsaa+e3umEUnFpc
Yeyv4r3Q8zBnM24jbyyY03tZ47RGsd8v86fnovurYevhKMq5R4ZJjvR+TR/ZNvp/JWMCnFrRGMto
znIEnJPuxijWUPE9pqYNgNouXGJPrQqwMUW734l4HKZOGqD13XRalTOAbWp3aSqosPNYg4O5DK6s
xLsuibaNXJTQBhSFIv4wjX0RwY57vkDJhgg+0ujudJpppHEJQm/rebXSVhzRk4hu2EV+LXMAgTws
qntc7+L6BLKaUQBmUHN2NtrTx+kXQzV0SajpfFAK0rgCOki3xHm2R2HyPXmYK/p2kscKothLUfnv
skRVcF1ssN2Q5Ii2vhmUjaaS9yeuPAj1E1m8bFV2EqA7PksPGhO3CJ4cMfTl0ePLdlCqYxbfNTrP
N4N9AVIWFD3OyRKmYqGAAfUx2q/O3u+nkosJhxVSpYIirslK0AKiKX+ltj5A4PqlcwbzVy8vS54T
qea5d46+7NVk4CV4UBtT+02Y2peJYjFTYll2Gn3hUHHcF3Qtc/qi1Dj8F0Ff0fGeY6ufAyX2l9U6
/4AX6i2LoJfbw4fLIMoUaQ8cPMtz6Pk1wU4bx/ElDL7rXeuLQMbzYoqSOZJ2YfZXZY0vb9rTAXWv
AyXVfR+duXpi1Z9BZDxl02DsyzBRDuYKmiAe+nZX/hGpclKclVVpsKenT1besBKv3yVmh6nCYNi1
C2WpIzaKdTmdP05Bn0kaRTkdcv+tjEgCO8sixUYyfE5pdCjD8SUcFXUmu+RVpR7N7Q7eU+dKJ7Fb
WZ5lDepKtcku8gzNzdEYmwXbe7dOU4kprA0w2SEIELVV7PxkaJ78c2/w2FoR8cCbp4GhmJU3Geom
w/PgjEG5JQmXOfgZjS1eOa0hWNema7Gy3Edq+MWc5hBWWrh79sMySr9RL/ZJfIJeRccHiblW8Zd3
04QLnwyTmhR0E+J1UL4qf8PCcTK4XOXGXqoiMP06WBW17FxrE8cIoFnXEuI5/Yuhca+d4UnM40c7
mWOhZLXsgjH0yEEcOQXMKl+jlzdIv1ICkjP1ktORHzOoxnI08etvSurEXZlpE5A38kRaeVWwkrCc
la4MxQVyflPQ1bPTw6CYXgBQsnMQ3v6JZgAz5J2guL371gRI+BSt8OXas6ScvExhHUiOvD3wqdK1
7eoCwZZT8SMh0ycHnqt8YLlM2beBuOZMANVQPULZaPL5opa6uZDnkIGcIOpJ+5XB1w6SDdhL2C2e
SS6Kv5O/SRdcajiykiH4aeVDZJ0YeOct1FU+6bYK/mxwEeqnEPAOtJSryGAZYZKwGMUYoF2DEHdF
nOvj+48t4+9w4G2DO1MIsbzveVm4vx8fGGAHky7emPtJrT4V3W1oWEEckfF1NwOgfYdPOSELoYee
2OcUuVwEgPsQYP0TODYE4JZgl5Fv6z6hXVLkWIu/cxGgNM+HdmqGu8WW5C86SFOF8wKBUG6v4zbP
BIJKSUA3VXg3BrdfaUScC2MP/xnahoANHycvx5A19GBChkDDjSUeXLTDHwTt7TJ5PNti32RtfCI9
5+vCsoZ+Gh9QM4ANcZJuyxjEVwaOhH9vQN0I77Vc8WZaTvBGn6oYnpRJPku7DhkyBQ8YjuPFKArj
945WFU7WoHmnmYpsdS4lKNIzeXIMacBfuSkDQ3RUeSg5Rr2grcnUsHQIjiVMGUVw14QdvJp05gRH
+SazrqupzyURiyLdpaWRsCj6MlJOJIy6afxmWfDqcHdDhtvlVDz6U2m+b5XxyDiEk4hKAlvnIEIH
wJ56SW97diUewffYfFS4lsjdO09MAI8a37ronqseMD+2A1HYOOOdX6V4J8sHpzQfEOJxv1S+D5Eh
IDYeeRrGIRRZ/5Jhmur07QEgc6fhlFxlmEjGlQtnFlzmxAYHnNhJhxh/FRXNPEmGuiCTMfriIufG
LmuhZbCunh3k3pixPh/jgbpwLmoggagi5/T/evWxs1GOWr8OH9WGYqYBy51ULCxU126ThtD6Q2mk
5uoqejKNgxIWXBraTjLo29ROwnwN0simmvJL9m9CEm1lA3cli1iTSZpX5dCvN0u67WOJmrqFsb+5
+2K72xpbBot+6lDUE88Gq6GNv5aR18MJ9yTQ52OBz7c2BcA+waf73mNZYtmhAQp7MXrqhJIJgDqR
lD+YCYWhKS3F02gaYjghxQOzjhblQ++61F5Qgb47Jpm1PGig0ezmSMe8HwdbTx0CZKW2kfIzM4ME
7vNqYFNyMF+NxQMDt038HUzpjHMqgBEQSlhNPdt05N97Ki3sWKm/x8bDSy9ywcsW+DvBgta8qEvl
tvru1Xbe75If2trj/OGJ/xu9IsjhNMqKqnHwYPExGNRkhSaXH1I0qpCuc8Dh+z01pAaYL0v8LT3S
Ug1uPeSOQZ0vZCX8u55ByuTDKw0qFI6ZyeSxYqf2ibbLQlgyA3MUwjCMtvl62qw/P0AvVwy/lusq
FUvKC20bQsZ3ZnQp9LFT4t0hI90sh4iHBAHdpNM1bnEhjvcSrEeEYoiye84+E12PHLQKayeS4ipA
olviZIuDiIrOge2WQUYLKrdiIhDrdHTr2KeVBzsq2ub+VwYNGByW/tNdmheS9jQpFa73rJW/5BQG
lscPTBjvRJXfnkejiQvZne64W1X7LVIYF7Qsh9y02ID0mZejC72NcZP9i0mgP6a/+o7Pw68E/cJA
kUi3suNo52sovPAbIK4ozVvh82BzpIJyBsklXsh+pzXMJZBc3hqq9FsIW7uqR8bALUfe0k7wSOq1
wpnO1E9SGQSjjVTdo+A2wk19JuDRIgqptFKO/bkKvGy6M5hd7qwkfBKQI0aFbZK9WsBgP7A5rSYy
ZlRgpOjfYVzMcE7FC2yxC1FKa/Jfyx9uqZV5LWtOpzO7GiqrFQZaFz2tDWaWCgNgWOyFLsVo56lZ
YqdVuZPZ9Tc6ALLPaEpz+50LJv2qG6ELE8+FhKKsFmwFfO7nn0BhjveB2t7qg4fFH3Q6NtBppxoE
8jUVIOAgx1XXOFGow26+sUvMeQYNXZ4vmA6a2aS31twBzSDOtW8Ls0mqDcI+hfH2fYLAefeqjXbs
+9XMoqEPRviSHnYFETpne18haiKHgLRx5SKxV29A2+CdMVCIeV4ktQkGyFU2xkVq3L0C2JZBkTOM
R0rfy4L6ekLnINPiToxnZehM4wjTIttY8xzgMfdwgZuH5goYJF0BIwfyPpXqhwIT7z28rG/A3uLW
u6QMtT4NKSb+B8/0mDOmUJwEhDRHbN8WlWDq19ho3+PyA9cX9zeZGRrBe9JjTrk3Jss4mQCAqswK
3adjVnNCgp6bmVbDUASRUWeit7jLC0vFf+ciBgk5SYskqIwsbCtbVKD+Nw7QlswmxK2PEfD9eGQk
fm4PQr7mlmk5wwsWJAi8VCytyWC3gE1qUMZg0EulBvcVtcXgMzmgo4z8jdUyn1YIsgjV0tGzFKuV
VQQUkV0LbHnxst763kk/ADgXceoO0btN6IBLlnK1DfsbfozbofoXiwVtqdmm68QtAdVLy/dkfIF7
VVzNmkm13Dxe5xV49tFMOK+T/czC1SYJkbNU7xPFqwMg/TDpN/Vzw8zBIPof6uHkgN4PR8OG3lWt
lyquzlELE7i04THgkZlR/BC7ofNxxC4gJ+ASkggE5Vcy+4cLTku9CPh9Oowk2Fgnpz9DMessKfpb
FCxZDpR6KKkV+zYTg3oVwEFkuHtCwraNy0cRCXLvIc8xQB/elwIEy74KQ0kK2Ov2PggpULQ8/xxn
vrsglr7EsT7cb7AD1QeBTWmg44j/GOZqsBaRgKx7jb6o/HAJ+Kamm0bZPPNuwPRyq9VOm2XMGnCT
WExRevw05mjdcA6p8ewqHWEi9QTKWq1D+zGlwGDE5dIxlPdro/E/ta7J9B3AeHo3LiW6ey1XwKyj
se9neIg1V41hMJxRU9ciovHi6Xj+JsdpucVpVtPMTWtwbwL+tiR/7rHEhSNiJ/hKvNg29JZSTOS6
ATSmYy4rPb0ju3uGnYmVBFWFzimviVoiIIc1ZZTpX/33FkKXtHS1FexqLG+s4a5LHf8lJTR3TcwL
b8WYNELv87fvIxroYzBNMx71az5g7HD7kh2m6nlTERwUdjlu7uNy4uoI3QtDeRyOUC5qW+LEH46u
0svfKHgFD/KlJiDJ+VojFy9S7Fhn8I6ftMkrJC7APHtzHH4aBZwtVexlWvUfKi7eURCKNDwY0KIP
mVQr6C7UwJYKkYTX/imH3AtmG7wfWLSYq2lhitPQEdISgviTyaULTPtfYpX1C4oYCPY8SrFXOIYQ
vmiy0qzCc6SrS+Ri50KRLjr1SFslCyq7xZGF7ju2YOwqLnror4olDMPN/ISs0gLLYYx7MumQUxEQ
FNn7ZdBZUc2fDAhqxw+912mTdhQJ1LSZZQO6ygHA0wII7wJmCmVBGjU1NvlBTaTtQYOW8ANCSchF
fnlOT5dnCfiNM0JWEsw5cHSEbWwtnLUqTzk3HSTdtjBmXTzzxsqMivElAx0X+lYl6o4NySsrLWxQ
uPMlJSKn9/hMFq2YOMCDlM9zL2GmXUWt/61wBQWg7pn7voRMRD8abHGv4MzGyCGdN9lD8rw6KPsj
nPtiG2U/Ku8PicqZUpPFAJdq8KnGaQ0oo8a2LP+suvbXpPstKNzNJCP/ApcjmHBE08qHZM9+DEXs
42BcL20hmmJAcnUxnxcbjB70uwse1Caoje8HGNpIzs4TRa2mVerEalb5q+swSjc9sqn9mUhcIY3H
JxlksTnVNmz3Uz0LUOGhDMn0HrsuMJB3+GL3MtyHGd+w+PPjwx6sT6rzSvBCexal5YTRWdlYYYMK
kXC42f8LlDFbjyw+4YJfQjRQyY3AuG3bifXtRb9tocV0ncSUuOqwQhG/yDCvJNdk9c6chD1xRmE+
RXF5U7tDhIaQVbdu+W/SvRvmFK699Z1Z+zscKfP+vurfaNqxkwYvgm4kWhudzc9CRUJ3uTNQ5Y7A
fCFeeLrsZ97+iw08Y6Oe/GX4WK08xaLM5eAKMhFxKmlIIZjS0B9h8bXMB+YnS57BWT9mcr6lodz5
ZI1HA614Dd5sQnC3UtFQlh5rockdjKa20H2CTXgCkwEh2vG4dif2fMLOyeeI5KbBdesWpWRNigda
udlkoioiynvzvCFT1t5D3sCB6JW1XcVUNdPu7I9zsyF0TcpO5GPTWJ1OWX2OOGtsIpIJUgHdKZQH
WlySOQrky8Cru4OTdMiJspk1xz5sep2kMxp2YYyupuncor8nfD/WFTcMRbp4gY0WaR/oRXozarlS
LH73mCX6eXUN35wXnl3cRtMCsFvPuLdHCcYqqwvjKAF8k8n+y0hO5B572GEhdoU/zHv8skbzYKWh
/jtonCrb1BNIZUbrsBsAEbKuBVvGdISYlnYrbZ+JP6r63KHj5yJ6x9KeouvmZ/bXH4Edxd6oBQ0n
2NjMtZULtZjlJtQ6Y3ed2hRH2DMpsStbbBBK9EZtEiuQodJzbL5GFKVQf5m/za29UuXHQurC2nCe
N/3DihViqO5rQKGdhG5PywktO3S9pWhFtepenXBA/rJNcY+RbKIeEnCXOhbxsNYw/rOKDv9NHvko
XcGwaq1QUC3ieaVnk2czHbxKzKNzmls8PZ/Od5UT44tNdZAKkbwYqb5x2iCRQUmCvPglLjTReVgC
ie8qi6OpLOtFXlshHfGvqjCSM9NrsF23cAnKejuaj1POoagC+UaBPQ9RJT3lPX0UmzW0PE8zbv8o
j+mB2NQv7vh3WoX9FOUG93rD/6cjxLsKntDhftOrp4bmsBUztHawvmt43QKrQMRJw6hmhjoGkxfM
T/9E8Q96+WiyNNIN1gnW0TtJx2ERw+OXSRlf/yoo2X34T0V16GsavE8g4ZQqGlgEu72GBpY3+PWe
ntSehdiOJZB2zrez5QbZnz2RX7pWyD7aM78yJ4J1+D9oA/9HQb6WoOzsR6PYKlmx93FvpGbhWM/9
yq5GlpNBa4pHlMRcPkzhCSIISxNz6aOCgsPQCMfgNU9fNa0tda8jDVIqjHgqQjLh1qy6tEogVrtn
jhLpfR1Hq3r/ZbUdfgXth/szgubFWUrFQ4e++52CFd6PQY4+FyRDWLoNulQ9YMazhCbxqca1H47D
z1t/2MOJIFBj9sBHxlUrgYTQ5P0URaLX55AdikRHAqDSthkIS71Q8rEWYmSQD+npPP51Vvc1NB2O
FXflu1AUQIer9ljJD0jfgJCaXLCPBOjAtLwHTHqO+PN+mi+tyvnPvK2zpE40zaiYBmW7DHD8Y3Cr
GzwLNbArX0eFi25Wx6/6UNI0S1bt0Rdk8ODb7idh9Y8lrSZ73T8O49wVJk+RdRCB9kaQ5buWUjc1
IS6a11wEqdICdONz07THUL8WV2Q9GJQPB3yNVHfFzMhtlsrkLf9neYzbXQ601x+O2jOJ13HdEyV6
sXHhOJ79E+Or8/l9dzE/Mzsq2NcITlTHb3fjYMEDG/BuamEKNwPlzJmpKRWqbK8AcmSbkbLjBalf
aX+BJmlsixOMm2KxwtEA+aRuKrQoY7iWA5Rt+SmmNA5IHsTD2+Rq+RuadLLYSRdQym6Rcghdl7xX
S3STcA8RkjUtnq9Ka3l7octtgPFEG7Ku7tdjGaMSbeJ2q5MgxGeGmMCarE6RBviX2ICXyMoa0tuO
r8mnkqhWUpuaYCTz7h0hteywTUORm4BW1/sUT88sDapRD7EZbppw7/hG+iCfYGAMd0H3HfYYju0F
OqobQR1jm+eJ3HNHPWBfpGn7CmsAD6nf/7Mwf/Jyq5V4APKwVyhqVjFsroOUxRYX8JUydy5w09qy
grqlZdKoo0yfndrk2UZcrZtfbNKLivqoJlB3FfPhSEdpAmTpwSOmZapIgbnpOolr6D44g+3G/Aro
lJQgY5Lw3+/Ezd62OPHP6hGo5Wr2dSJ9bqEh+LbgR0q+hfCy/Z97nGyyFewRmu5DqkLBXIet9Il8
xTTEFoSbRRiMzuw6coEQtRcSq3nS3NLaZZK9XDkXi1/WWLSf9bKgzIkEI1Nm9H4B0Lu4Kxx5VHeS
68yTPhWFxANLTPxBA7zUgByiN3fgrXptUE1G39Pfk85pJ6kq8YS4TxMr4RrgRC9FB/WRORfkRPzi
BdqUHvnr3kcMY31sDhluELHuwvcOT8LQA33i5WXkjXixWdeX0YQUooPZWkSO+wiwkvqLz0fj4cGl
G/eF24onyFlnErbs0YZh+dlSjEvcqXgKW834fvUTsU/GoTZPettGiB6A7UIRT6zpruAbDyaRgZAw
0OT2nEYKaOr7LuoMqWcXTV/whZsQQdzvAVRiDLoW11ChyExPNq/KtY3675vdgKZF6Htq8ByiJKne
vo4CoKpH+/CnNJ2X4OpONHfByzN9vWsuMLn+mK5+fCxJa95hgby9lyPhouLQcruQGFZjlkbxyquS
yxgRrO4KVBdTuRIkNBjKFaoq6MMk433JFenXz0dPOIqYhPEgJJ+0vgmyjRAkpiI7IQI69hH7hlCS
1SiRRv86a3GQNwilMfRS0IESjxLNx/l7TAAzdNbqlTskHbCvGF4eSMPiWMvi75zpSAl1gfNWshAE
5rg3KyhKpSzAg5Fr2wTl4Mi5/JgGXhXWKhEPmo3WjfmeIRUm3gX/AjKJaBAXe85jPrNByHRj99yt
gKnpozl1Atxn4JdVVix7ZbbYTJ1ivrTxdbMx/4cK9td/M8MUMymRFvK9VqIGHVMSfMdLy6aUH/2Z
spv6rKb5grap9eoz1K3iPp/k1bkJmA5bmzONhhjmAEMvrfcKzxLWiUrglpuojGB5UQN1df4XtzYb
gE2lVbTmO3mVpQaCWfLMjCS4SFExfBCMFDOpgANnk1QKNJ/XQIQux+w/deDipm3aPnIKN8ceU0F5
s75LTBeeaibXSxvm8JVO7WuhsCE4cEKK6qMmYtZNwzpSV4/vNgd4lBJvlcONdfviyFfWWGjcUKGb
/MxglP4/x8TyYEsyV+SAvUuisYSpY4R0XYVM6g2CJJs2EF3G1VpJBbrlJ2sKBjnVBnl+VH/xl0pU
7I8jL7qM8rKH3ZoL4Qcr7Jn38PJDn1jpo5XDd9A0coPLo8U4GtFCMbyNNbu3cghEdJft87eHNUIM
JSxjwEqmsPwuk6/SS5BbXh32wj4V/2ap1xDWmMiJfrlPoLTJGJeDWTk84My4FoyvOELws+mtu5qf
YmIxrIoPvoDrKMbWuoP0Jl+JXwmDTktFC536k3s2ZMtgImrmWro1tOCMTJTI060vzNhB8jYbCLj/
byg8ytKkSF9NtSmQIgTJ58gtwhAy02etxBboZR3dVz3v1YQlOuaubaPJvY6uXSZalBs1aRkqYP01
WZkzC/W3AvYZrr5rFfXTVqWk4nLf7IZIcMQcX0ObM69/G/oymm7UErshhybKNgWqhNL3UlA/SHku
CjJ21ELlc08jfKowfN2ruvE/1kOd3xQQW6O3O/tPufh5SWBf4Ju0MybNo6z5cjDiUfivG4KET1i9
tE2WWpYorlwd/qUDSO9KhYiPsjddTHic1o3OPndRj309ZNP5JkrCjVbH7X7ybttjc6k2a2ieZvUT
JpjnD2xbPSdWXClxGLSdAd8B+91raIQpAxWynK4MQTrdfVvVBXJ/qGJK/nmJpIyjl+57QQvm0OCW
wZMLf7YTBxMc2fu7cR0/AdD41P+81UnrQPK5Fu8YEmctmOfYZ5qxRUzLt7tfbEJVieK0XAqNvcrA
hY0MjIbJHSvzlrlax27WjSr5Ze93J93iwN6v2upJKadY9neEya1KdJIJ1rkgEdECVsjttnaw7qUj
apJCyLsGES1vlO0BlTbhhFd4l2gCAFsxl9zc5jDN4GfYTqoDCZJh2rFe+hRZr2P81xYonXEuHLXV
/R0dFvXsjqgJiJ24nZd9VdlOjGjyaHbpCcjCo4IEz06O7C3lGDtThSsBMyWUNIL0cyvlBIh/CDqH
Zxq4ucSWHij54triVUaJGb30+9WF3Yf+/mPYL9F69wD5ag2Kv5wt0mnPTjzokQxo9atuJGvrUKX+
oC+aRMzjC/VDhqLDxo3fjOPFwi+i8AQJoh3ztR0ciCM0yygJrhGDhHIKnYYo1iWXgsCSGJ99Qzio
/hgOdVJqgWHn+PatpLdMUwxEDG75qDMTZG2wJP6Cf7X8eAcnWeIpE9S6r7Rt0VPJMnFeS3UDQ5hx
VC0GKBAauz2SXfdRuAQeV8Nof8YOwwGZPNxf8ItM4YJ2yQDZ8Hef/75IuQz45EHguwK2BuQYgQ1m
5zYF3wsAiYSlQjFERhh+vQqwO8xtUT0bKLfKagRZxdFouV4VUkgLiZZzF6kTvhllcvq5XcYaQ0fc
1UvKwosArtE38kQ5WtI0Kng0mGAEHmp9jH/rYGow1v33s0noqy4Q2x8u+PoYOAMt6wjOUxwXoK7L
HK3TGEgPoPh4C0l9qP2QVeKTr4ec9BbVo3Zh2mFo15bWhYdT3raQZ4gZ1Yh9PYDV1basGOVfoLSn
j2sZEnYc/PdVNtGnYTh4hhQ7+vWL/t6SV5cigBbk+Z3PjIwv/nIRq+KNFlrj3rwaSE4+WBxSgLGc
xbmWHtbOqAquolXu9g1ZehXRSsgaA765skin+eg1u3CQt9bNtvpA5Br4F/c0o4/pqTSn5G6Y4c18
QolLXxqNBVz3jFY1qCsuxPObnHml5tyJJGQ43fpujBY/RFJ64Q8YdGXwaL0YHJfr0FnXfXcWbYtT
tL760q+kidqVcQleltH8oGlN3gikORaERlrKi0d0+g67+qiU6alCpTw0dSl9Mg0+BOGUPxl4vNwq
uCbSqbhMZieOe35z0+25JgnpyeF/xtqNEDqqrA18d5ACS7fXX3sDKH3AbJVFDQAM/9/6x5DYvl+s
hrCqe2O15pob/LMVSRph5wr6bx0Rf79hdISrU6/A0S1oZ2RYWrPIqEF2OMsYEpqJ9ZHuLTHFpS+r
yyOyBuQzKI7Ocbxv/AnEq5v+OMeDeSy4sOmM02dES8CPZFET27WGQjnXnGtDgXG5s97hjv8H+9S1
bY+TVjUtCBIcU5elEl/neRZkYOQoyGUcSEfW3JVnIOZuw85k03TOKESTZpvEAuG03ZATuc9LSWoV
oqCB0twvEP4NsClW0/BbGhXZBeu5VqoT0rxaCdVUlunzGx0XqSnBLmGexd3FcH2afNv3Fb+JvU5D
qq6J7jkhDH0Uy9Ux3TWBH35WXKgRKx4IGs+G8w/pdARUK5hMk+UG9PRU4WqcxW8mNCpQKt2l4XXr
gl8Rpiz+vFCtF+M0vNA2BcR5qRjqZlXAiHmgHysvYcr71uWeufz63Z4zjQuTtJZS1facpk2Z3eRd
WpNaqhiXUjt8jzsz6+hD3pQPnpMIfHLPSwNac2pqnRoIueS+UKXfsnTFMkU1hU9yXwfdjR+J0hdj
4Uck88B6eFJxrYTG0g/tYpuM5UFfx55nZxkZoHrKTKFqoOgypWORCRRr7cuMhr28mjeol9DMhdUA
tz1czGzOhhjGvVQxmEoQZ1atRFBzMjHKr2iiP7rg5FPUokkhryrLAnSwxEbZvx2bxvIJNh1uzJUu
OSGeU+co/90SZxGi+YYK1F+HIGM+KkDT26X5hdnpp00HZATzpUY1Eo8oXbgR188I+oxnXzyL8W3h
hBWsGly91ORv87xUvd966HXAVIOnj1/SaWGmsGdVTt8RlOijVD5NZpWTLxvly3+SIGH9Xdf4yQ69
ogJUDquji9wwHxT/56Z/BrahvBIWVAT2uhTdhPVFLLK/HDTkx8wzOuniZDkGQaxE9xrlaEMmT233
zSoqNdKHb04kKFVG7N5QSidjNAZ1+dwCIRcCz1m0PZx6xHqrx//RKsqZ2eJFK3axYa9/dXc1SqgM
b9mYjiVErVVRbfmaD4pwIbg8nqcCdwoqBS+JLCy7K71UnuBRCJj6ipvrapMZaeOSVDw09Q4KKoFL
i4hPaVXm4E7dH97Vxx2O5yRs5I0TVDwrmvRvx/GAx0mkkNvtLKfzljxwsDQ/h/vAntKOyxj8bVhp
kYWrwzBUmjdqMljjy/GOatd+QNce7Wg9LLjgyYI790KWEj5diGeb79UPZRhbvmmsqJe5SOqn34rm
gQQvxd461YmUIQMK8Y9GMh0/usSYRH54MrroxyabvINgl70kj4WEAnOZBv+7VuRaXhfI9dxOnRmh
8EpocWmVOnN1LEaDvo1L/fSWm6sskq3kKilFtwtnWAwDojsLW9JwEGeltQykaZOuqZqGgRjXZTsr
iDvWEE9pJ98gDe3RO5Y3YAyWJqeXlHPEF1ktiJuFex8CcJJJ42eibOURHQ8mlD5iv8xRpgmRXuyK
Hu9oL8yYrMB2F5yEG6qL9TdBUEkv13wzmw4ll0m+CazXcztqIV4z6NGMcO/7jgfrv4sdtJJ1DyKc
uAuiQUvbZKMJql0p27c/LFMhNmTm/1z0Z3FvXepkKSeXqpV/WfiSe72XmrQANmcksihQFq3Op/Yx
F1aW3tb1C2rP1G+fL8XGFYMhypIzi9U0OyJ8X8tWwCNqPTk3vvWF7VOShZQsioUx+CpvvBRgUo94
sOzL7towjFHu0jRcjucB2d6yPUxA/oeO6rCEKjjQkEso0fGEZTF3AN1lMIgKQ8Qq2wlwdFMMk4wP
pxGBw9iph4TXsZjTEGEkv54/LFcB+4TiZJ1tdD4rSlTdWGPtJKHjEoHPOSO1Z959xBNnZ7aYE2We
xvLHD4oh0gPd0McQp2lK1xWnSlllRPmtTDsnyWK5ZKoKzx0RD2bMN1pds2yr99Mt+8sz9PxgTrNl
ctrP8jcipTpnup6Kvmnui74EbxhzdiZdTQimHQGFZaoANKfW8dymzw7CcYQ+KWE+9mKKIFawArqn
Mq5ptyqhWmGAJuzKsKu66z14GCAIw4TCzufoD1LhIkWAUxF2Vfw1h09FRlnR+nSCSZmZ3fRyhcHu
E+eYsyZPscKMxUtiM2MvVzhNK7nk+UTOUm88I/qxEMwAg9rmIh+pL2lTWIZbO4rnASNbJLR2Hmua
Gy99v79v1mKqWmoH+iUw5O5zIodlus8ZhBmcYrqfxEc27+wBU5X+sxD8n7bB5XaV6c3mh2KwkGt6
LOV+I3y6D+3nu7ml0vwIzlAwdDo3RB7/sRciNnr6zm4BXCjjX+1GJIXMMWS/E3I2eSdo/z+38jwS
OlOjUhDplkRJ7+PV5sgXtGMK/oBjT+kmdTzmEzQT0coLeExOc892VheCDvu9HIpwbqjKmn8v7fsI
+Aw1NO7EddQHvuBKw5A+7/hPoXq8G25PHKt6QqgU2/VEhlyTGlZC5cj1eRYxCbxThHSPlfI5MOL2
GWTl5FI2kd6dEjV6Qa5wBKp1GSsYDaisJCOmtvbYZzMSIUQ/IKvnkSEwcec4F/nyFGh+eG2biMbj
ixLnb45XiZ6S0XMd8XxKXhjMwyHK8V4dZn6CS9vMFAei6gbMZ+WBw6qljzhyCpBu0oi7s6e1UW6q
M6akxYEhsVApnezsgtKzemwKKTYKotPxS3vAoRgjj7edqt1ZhMMsuMNF+FilXwqJADEyx0iSymUm
IozlETetcEXMpmh2mWVm6CljQZIU15iYENiHKCv8eGYJBJoJBnmkOIl8dMeUwq83PlYxJ1eFZZlZ
I6SMlpIsZVzhaTaqiYiHYEV8yswD2jO7UIy7r8mOlcfuwjyX4C6/ClRZRqIIL11GmR5xgUC2bFWI
zaj5wuGa4dUFAYp3IBmh/08wp8kKOZ8U4huABzNkuk6F2MLilcPwsbHcEBRg9rgrbkzUMl4S171G
BKz2ANzbKRGRPGPZzDrRBCr0/t0/C4heX8xHgZndIxxrAOy7TbUpIaoXFqDSj31gBvbuwl9pEu6t
D0LRkLULWIjfUQEjTM//PODhiL+f3UF8NCPJiECs6uVqHiSqUt9CmumB+qJ9ziAxrEAqPwb6XSMB
uDb/3j9/s7vI3oo3oqPR8SQwo5AzfSLlTFqw8kUQ90ZBqsdmj0Q8t9BbqlkrCp5VYfUt4RjklJ7X
swKegKqhtUbYUvFBYIR0ipZIj6GwKEE7NTzSXrjlFnUdEj8YcSqJh+milHowBzjBWlHH+rwqZzg7
TiRQgXzkAR8pUgyWO7loSkIb58ucUXAF9StfJpa6kYCBZxncPb5kOuYJQTe+jZf8bNNmf+1BfYv0
1ZfhTjaD6SnuvyGBeji9Trtt54JeOR+/shpF+OoEmnxDghqMUQ++SyxAYOTw0kA1CmwpeJUpkPyt
DCL6EYwmz+tRYV2cKyAC6l/2S+cMaipfroB0cIvbtDeVJvVE5Tgd++ba04z9tMK/wErFn0bea1My
FheMtPtCT3t0Gqu9zWVJBMU90zWfB4F42+hpxeDjI93Yu75Ryv3rfhBYHXnbU0tEWhIDGcQD3W9p
D7xhzqsYzxACcnEVfUjMUL54wlKMTkzXXD7wpZrDiP3B4MTQRteP/no9LT4z7xE8t5vvzfIP2OX/
YtZZ/xsyP8abUrvt7Zotw45xrTVP7wMdMwlP+y3wxjX0ZoqWOZCF1aOwHyUZJwV2Ri5nQkfGsMWC
iLJoqOEHmyz38RpVzVPltTMsEjAENju6Jd5zxIURt3MNmhsCWDzKkCiknAtutsIi5dnCHBpg9XIm
gRiztUF8lXEt/ERLb10c+8T6MLHiFJIk/hIyeH2wZNIzp1ZxUEPTSfVGKrc6nD/iwz4KRBG0okX5
n8/fCqC2YcciqXIIMmYXq6eQjyskzhesrQwNwc9yXp1J5lGaHplZZt6t7PdJPv5L4ZbLqHBuA5KU
HDL9Du8oW4Mf25bd83Q1zhxnn7BM+41Q27vca5g2LHNyTa5rz+au7D+Px5dcTNlvlQGqiSg5F2We
QHLnuSSEVpAQHtFpCmnO+VGRiuhP1tVMR2zSQNkF8UGttLGR9/syZs6LZAaKgEetIjzMUArYwZIG
7OC6KDqXiw8PD9U07q5qKBsjJGmuftgSw1BY8SAfKVFu+uB5uzLRq2fYG8AimopQ57/7Sn251cuw
DtlzxHYsBCKZAAcavyYQBABJzLqPiHMRi6YRSsl6BIwR0bpWoj7X+M2xc50klCeX3dxkPIeWTKtj
aYw9JspF3hx3zbcLnoLdKlLr6Fr6OPEPTkF4K0p0+xsxvchG0kbg5+CGGWjsiKhMPbR41mYM21jS
DVqL/QLsvLUB0xfjwpZKNp8y6yYA2NNXdDaMwpXovvFJV3fKNd2RF0A3jDzEk2lH52DP2BpzxFBE
HrrizpmFg7Dk4hYUFTCPWDLlZvcUhXlGge4BoXfBtg5EpzSrcE7pLEVF27szOxYDrMQH3DCcAynW
9ZadxtJuNph/RR48bXOWgjs4NtdEh4CEiT7cV7vsQ5rj5We6fpL0Wp2P3TjWs1w2PUdAIGSn3klW
UWpC9aetxFcO/vHHTRikoEv6fwpj022+Q4uSnOMMFB8+DRLy0tWkX3h+Kz/yY60hRUtbKilrq1Uq
bq1E/OQ20pXge+0lAiHjYzaGGAkQ6bZqAs2sTHzIKnsuxPYFVqcYZNBtLb5Dc/LunP2HY2AE/y06
oTm1w8V6tgPKVhToa1NZ50xcMuHRwLPQoCOcr0pDMk+S4VIvSfxqazKoCtlkSHAVuKwvPP3JGhc1
o8EWJau6p6a5vyNAHpQBoa66VdCovMuwISYPvtDOSiYoVNsyZ/KakRgj9KoIhMrjOAV7ai2Hz/D2
vXnDz5oTtfEOFS8fsQqtR/Ot7zE3jrShptvJcliZKRdvoiYfaHkTRhofYHbYvNRS3yVMG2rCUChk
7iKQ9B2EDFZvq3tb6UOQJUPuzHq/tOYT9LbHipE6MDLyzF8jYpz1Lkv+dQIzmuzgQHCpJHqFY5NI
E+DG2QmajGdOSYiSWg73d/hj7JE4mmR3TxYjD7HRNukWI2Qgy4qXJ3CJ0K55i/3AuQTzNTdg+qSf
nXqlRXuf185wulBVhxYdE9ZThBTYawcxiXhCRBV0gy2UoMS3MIgg2AeHKsiQ6nTtcnVldbRumuRP
vBBTEW82WQGeGSusIS+b/33Qzrxlwo/j4vxv9EwgODsTZNPL9koz2psEmv1l8juEcZZZGNogMQom
oA52vJUJHjqOtxxrLZ/ItgvkLxCJ2mR7t8ELh6vNc9GyVGgtXUFalwtchrBe93fo8FaJ/zZGhhgM
mnvaWXebw3dmMKl6FNXHcuVgmJS4c4wrebOQG/8+kEttAWWOD9rOK/Le0Qd5Q5zdMU1Ix2ME/et9
mTZdl3Hpgsj9qloSR5XIvo8OQYU762jj0tUhvBhSBxCxo69crZZL7FG7U8BMHGvG/eUV0siJxtuj
7BSOovw1AbKwtG8JKzmgC6/q6KjWT4kj6dZ9f7ZFZVgqFHIsAkn+BXJ3shDjrOf8qzgU9XhtZxhB
dmlZ+F1uq/j7LcfZhLvpLBgC1/euoYWDS6j6xUw5pDBgiwt98f4ZTnXxxZdKKxHnewwdT+R+YbOW
pEO2oZpe7xZ4qVzMFinRVAOjG3Jk9cUB5MIvroEalsndFN2PVTunYOjOXG7WeNcye/O9szGeByYM
6X3rzRbcb9UzwDHNPoQeF9RaBqPGbIsQXQ12bC395RBoqTOuB04jEELqE0tB68WXu7EJZ22FjNZU
yiXKAuc2OBvQnDDE5COIIf+IENs2KDSAc1+DY9Qw8p89Mms/7WvfRgwU7LCqrWkay2/VH3qkY/2o
cWR2kfLymTGL3gFlUHdJnYkcVoa2Y8B7vTGxMzW/NAaOlQPJ/jktMf2YCN++DG67gTC+OH61APG/
WnpWe2FEhX/sxlBwSeoU8CUs3fBZTC4HlXECX7smqm8/bDwwPNJs0+ahtaj02m8qXPUVsC3kj0rE
iE+/8BzdQcx3KaL98GUUfKuUXhjjo9E7SgOJeWw2Hr/87P4xwi0ud6G4/5fJyz4jupuhSGJrgWC2
ph9yP0Gvpx1OWaD4gzk6x2EWvVw+7LuHRjmPIWGN/oR0KZvsNP1lde4xpLRy7u2xiKkZr9O/H6dd
jC+4QDy9xIqLfywOqFXSsMO+T4cYtOnZFIolxvnRyubW6utab0xlcX7W/iTTopz1KATl7QQSQYDw
h4miqPtXW3I83Ky18l1199n3m8t2t/rGEl3Z97uMJiFpUcBjzSfbWNi9IWB9vEsSdmq/71aW+akb
BRiGpj4iX27X6Qe7xPHkYhJE3DALp6RN9kyI1Wq9dEuA+cr1k1Yz7C5mBJTkKGwR6mR3Mld0y5Y+
nGg/lWD9v/2bDHbOa5bMkEFdY6IK8jcOYIh4w8UfQVAntv+54QkNfBgd7KGzwyjHyYdhOWcvSwOa
PfshsZ6Y8WtYSdf1l1EDPoaa5cPfF6hG4+czThysh7kldETL6jCNe/Cgrv7902JeB7qD4phVDkeO
gI6CPxQJzX7bYsC2719MA/jN/UjGuuwacJh5qkGpA23c7TLDPFzryG9xUdMjrM6/UhSM/I9ptGUX
DG26RmZcSJZDFsk3zi8zn3X4tRFBMj59/yHerNus5mwwTIMf4G+ABXVjtVZgEOP4nfptbPFOsMPP
au8TcVZLlaVrI8USmo0FYCG10S7C+SIy66NafnRipSBEamt2AMJEUuJw1sMQIiwVhklIKFPglGQZ
EcxJsutp/Xkd4GejSh6l8mr1T05/pje0wDERS0S3rxagtkjCLawOaBACKzsbQuk5rlcLto+YjYIk
gg0izXKlmDvF2BaehPcEFEQWNW6TjanwQPkOdUbz2RDlAhhi/K//rus4XV3YcJsDcHiO7tpWzoqm
YEKZ3HP5X8Qx8XBFwFKC73LtAiTkE3MS4OzVwODMURbVwkTQLlBlXWWIlxLpsIFsD+LTvT4Ya6/k
COjdMq7zfNre5Y/6J31gFZ4vIbm7YlmiZl247id3Y41td7vy0fx817Q9uXmOTrUyhDLZZr+UFjb5
1OGZl+MWXXFoEJBSfnzDa33EZ/AFiZnuLN1DARK92f9Dq3dBlmtvfLVF5UlOU9SNkMEdw2t7XoW/
Rkv9h/Oup4SacFnsGsHuaaGnQdhDFg3tAJiQsfGts4JHoUi4X0l4/ez8cPJ40g4sdJqsyU3Z8Sm/
W3/xQSBzJEldXi0I/A8lQ7Oqc4RI0ELONtjJel7BegCcx6KnI9WBr8UJcxzKwZoCc85fCK22cBQB
R+/6+26LAcwM5eNJfa7E+RfeaN6VSYPzpHBtdO4qGIvpafrJq5yCQwLpPca+niNiPHxGQlRovjUd
J4cacZgvM3th7qRnlTVxgO2ZWrk0lUa5eWHWMSMHuv3emnycHSfnMjeD8tBz2kSjWVpcuN3k5tMY
5wdkCKb6Wolz23I7NdE4EIMOWNL/zNSYmWcK42smHYnGhZmcjfd4N6X2+iB7cJESwcbzLzvD8c0W
sFiifdRCKeWMjxpybVuEu/ikEBjFzxcVM3B14qfGezi6o6ZQwj5MtM6UfsKHgZ1u4VGCF/mvC3Y0
AkKV1BCm9nVOd/h9tIHo1dFdPso2oK04Gsj0eMqCXAM0pp/TTuO6G/Kuaku0mDgbsp9GGCvWSCQh
HINTTNfwUsDOjiexr6d5FU/xp5YQtxvCDmf9EJmcOpfESSD92BKuDFMuxK/h/5yFkDm16gDUJSVC
ZlICJWs7OhZfX7i+IWWNQfUCqfQaV3QXi6fiOa6JUkjMrXdlNspKSxdHT0zzT92U2kDPFRPU7YO6
tSem3Ft9d+B9urnIdQ/8skHI1+cdakpH8d+68cPxl5KhX08coClm3NKZ9COJj4OqQ7KY9WZy67gC
YucHeO/0Q43qWQeiLvDyWIodATVSrbTND1PvMCYc/L/agYljwII7LhsSbF5yc6dBleIDnUgdvwRm
PoZ0MK5sAIlu/FGuNKfRzTpl7DHKTmcMvMCwFBXuxsZNs4eFv6DVotRXKsoSVV4CEXsQn4kiPof1
3zxSXyeHs/Y8LcFHn0SHIbOo1hSSWelNhaGXptnvpo0VSlRTHwzJ1222uxwuHV1BtAvUAE5vJmNK
ra08LRfUjA4POUMR4pcrOC0Atx4V4MtUTYWGxxxteDd7UbnI9VV/k9tggzyUgiBuHaGD4iAGn/Vu
hOK7T6FeMC269GsCo3PXAP67OWmTmlDv6vf9Q75HVt/xrMOs3kxyytCOMBnOjYSOpyaI0IE+Aj9c
YoM2mIWzcGPL61+NLI1jEemGPq7AaLx5a36wVdzCwKknXHwV7yBRShRy86Nb9BJv5VO94ciI7/UU
KUR+CK610R4jrneth4p//+F64SdcyJNKs6QR02SKztog/XWB5hSQAiisQSWswV0EsrdZmAO2Hcd4
I6SgyruX5ukkQDBQkoL5rNyCTtVlo985SbvF1vv90WUSusViayh0tZK5bPX42qf1nLMqnH0jL/mY
JG/aiWC/IgW8CxLiHfJQFyuaPtYGVylcTU+9HexCcL2GF+zPMjuU1TO3Dh2ogUHIOq2/g0WUiU0a
x2i76vGwV9mfhoSTOCa1bz/XQrahSxGIk3HU8eGkac2xLfYFItquMcUEV943J2/rPRwa0MOWYXVr
XmBcT085lPvxf8xBMxYdfwRRr5RFSCuv4YI6Y5h6i71z3bwGwxzlOi8A1tzwau8wQ+J8qMIS8EMN
1yIOD9Ozu7MITP24BH3tq4xZ8oYOIrHLo9YMtDTAe5/hfbyiAi5trio6d0Sk2Dpst1EMBQogSgOp
O0cX922f4279KEpsAFW7Wi7o8d+raix2p3/blLXpqPv8jlWVPw1InyqL1j1qkrT1tXPK7CtOxULB
iwiWhCluySx9X/7TZc4CsaHHqghGtdmhNIWAH3fB/LBXk08UjdJA5Uo99Fdqu4HP5gcj7lWy7qkp
zCHcLto38qBa55nbjQgFXEXCZa5/N53mwQdw7A47l//7l1Lf2/d4IWUyBUMpoc0lvurQmBltm7h4
Y89K/8t1ZK7a7vWTub83nyV+quV00pM7BKK6g2zR8NLzMPEbRfJNrDAwBjtnD+GTcA7v31hho5y2
rTKdMKipaO+vJv0e2yg4/DcMWAJprTWE/4cKBkqbqMG0NcOdgKxQlNWgF9LxxDe2p6fbBKeW9lOu
bRvQkCaiCvKue3t7qN5ZXQiBrtdAfh88dksQs07c6ZiBSjYjDRfMGrmJIxpeLAFOOufL481DULnd
lxgV4ykpc4jIX3meBSKkW62nsiEH7znbiU+SQEJXxNWe9K/3F5VOULnTolx/YApzCrG4Jep0B2s1
2QkNPdLKyEe312o6RXn6llLtTzFkAE1j35dl4MEopCBpwGqUAI4A5Pj6CXb6F7wTGeS8gGQb8PL8
gTeAVKoRifdHwJkJn3LPNjqqmtwzLxQc9ltFRLjJz75Vn9dsvL+mwNzH/FWQq+YKweycH+2DOmFI
ZfLRVConZPcdku8OATz3cT0a9Sg0hWtB1nvzA79jANuQWlf3VIMHjaihoWWdazRCV36YLhBHDms4
z9zQ7DMAsKKibaafKW02FOdggKBLqiHGL+zFVDdmsRF3i1xnnj/tCE+S4UccQN/gPMr0R+6Sr/q7
cdbdou396wHpDfb1jJGWQbjRvYEcUgod1qSgG3IUg69W7Wor60yTtrYNuuyX5/KoBDpjfWLOKWmJ
MZd30gO3+TE1Y52/LvK28fq8CddeucrEzQmrzjfu5l6L/faDPO9gB38VppavTv3mZWj6LHF9wJ8p
Vl9/mDtaGyRRfbF/f/efjyGcm91IxAW3dBEZlYbiHyke0qEH02BzXvb+piIz1g9X/SPmu3NizHjJ
TuZlfPRss2PDA+wX/DQO5GLfvfsAlmNKgPfBTPejYaU+66j7/5a2Kza56JtFE0NWX8ZDDqaNrkXl
iv1LgF2xVghkLV6nGm0rsS3HlS+J8XbdGZWOiSlhi4W/Wxew7tfbpf98ymUScFcFg0BTEXqrvjYj
zVx0cYdTusrdQ6Ir1p6YF2JWnfzqHKwHNkIt9HJfCHZoH02pOHcTTKSTdkYc9UHRHxjU49/oOtQy
d0Lp8+IVzdcQ0dDyyyrM9Fuqj41hibG7J68cGfeXczpIivhG3qK2shxfyLE/vou2ZCt4roMF5AAb
XYr88FsbON1kv5FJVamxLz9UqwXPBDfikzcEXBvXE864hT5sIfB2h58+bNFkuk/flkHsmgPcpfY6
fJVW6WZgse16h2GeMV8PBLdmwKj0knNLowxBo6nrnApSOxfM4YhGkcwLHBGYQoomGm/2z1McT059
VBSjxCV+iFZO8cIPKI83oZjwseR2DAcyKS3ceyQPYZug0a6uJe4pJ1kQLWsg5QMyFQkPM3W3gd66
RG7IRYE2X5oUmHKtVaWX1Z7JWMhcVY0q1dSaKTXhGD9KhxoAwWcsTTh+zld4uKSvDjmoEejOoh8r
tT+lKSxKYffYyeIaRgHZ3/pHjRuWbm1fby13ctU4309GfRL983/yoZqDAtn3dVx2CXZ3h7nd2iw5
P0AONWYEyjBbSrgY8KkMKXpTPvNyXnwcAvBUF2NY8Wau75WG+ONih+/wvSVg7CF+tbJPEUQf6PBb
xSqUMJsna/xqBzLk81IhJLZhNOglDIfhkK8AKKKNq8pFK5ArqjOZVd8Bv/55CFTlzJUIxrsa/akN
Lphs3fRp7d7BQMuFXQo/YyIM78Mo/P5vdTb/RYGc4vkg4hGubN84XlOB/pIC4Pzfhu04ZcxONwGL
sGgQFZ+LWWT/PZhvYnWj4zRFbYYC+xs7mOXHB0vfWVd1TpB0/ub3NfrBm/eEnJNKGhQsOoO75+LW
Dsj/V8GGbuPWxOH+Hs447Oz3KBvu+FArBVFTX5r7RYsPg+FtjUqzc00v/BtFxUGO1u6kwpycsF2j
houOX53lcyEox6VuepLbsrMG1+DH5S14DAwNVp2c674lhs+sxV2PntgRXkoMD7bJrbM8tdhyy/5G
OOXj/J9zBYScQDj6gBr51Gsnr7/lp3txC7cYVa+JodJnbtWkAS85Ct6M1lWw9RS5lx6NqysB1/pE
kIkBnu37enCuMv81I/ZjO17RR0nW6xcyfNzdrcTVy98XJsZZjr5OHRshJQMyEQsQHeKnDa2g5ARz
iPLIhUJRaOhSMJdOwuaMBDFbr3VZGGIxpls61SBJsPEzDghHXvfhHvN/iU7OmI9/cNYdE4QAIBUf
0nAcU98/a1oGQK27klLx7fT88foVIoPVuQyX+tLq1E3+/fk0o7IDcbAALUSnpSPKNOegnQ+ozr9t
Ui27x8PQGJP/1QBOLVySPhaTieo++BF9lScMoiKzbiHB6hqLpUeEZA195a62qJOKykszYEQiW9Gt
VbqVimyZc/HPsDvyQd9MbVsubDqRdb7NJol8KSCyMqHwW99jj3UhFtyo4DIpQY/ihhnwFXh70bji
jLZ6k0wRz/k0YAjUgnE1g7Qx/M08Ff9XXAHEjytE2BKAV9Lh2xc8lEkcCkDEjuooP8RV9llO4LCQ
7METSLkwukaPazNPb9TQ6dGWe4kVGfuzARSl6FeHp3iX4CLD3NeZHlS7BYOjAaBexqroMfLUgbnV
xjZhFoJD9jU1+LjBYcfjmgvZ/6GVxthpiwmanaRMF5AU56a6R6GuLY2itrD7ZmTPibrcP+UcpKcO
9oC0/kCYH5HaZ83Xs5WTsWA4hlyczaPQAoyBMqN2EfWDMmuZ5Q/WEoO37eyZKGZcke7tVmjgRZAu
jJmky2HlecsAl7SJXwu7wl1VQuSsg64um/iWQHCLT/Xq7fZ/JAzt+gJsgqT0ZC5hhOgp0c35PH+T
pwMmAU8IossTinJFDwXa6/BB/Y6GVXNpnFLX59v7iwnnQDlnMe28n5zd+ZHPUCzN3B8Nvv4R75ch
pliG+8ZonLiYHRYqVhduWB5vWnqjng65FgJIcei9cbMsiQc93HMCpJkj+pcQYKJ+kpeaBniDLqvp
PjlmUXo4DMmiRpJkDOkh9n9y3r7COw//ncmHQn/H6HITGxMJx7JnNKon2RBy2J1CB1gG/7zLMT/z
vWUuPJ8W78DJpXwSiAPIEo71elmhMzzfupESjivhxEXdKPq2vB/MXaqvvBmq06UWGSQ0upYpP20Z
0KPRSmW1ijvBsHuVonnu/rg/HcAwg1FdXKYYAtYxjDV4Dn/ieiyZMTLEpk28CHkRGuknVbre7inO
Ets0GxTe1zupGwqQa3J5wfc2ER/Rm0fBs+N+kdLuSzvmUkbVgwUsBtA00sVNrk0Hg+Dsx40hIaBq
hTysP2Ob8AbxvgreIICl/pQ2trCQENdxYaYJWoSotltxyIGXDya+vYg+MzLPR5k3LtT4QfSEbrnc
Az2D5F7Z81N9NTLUKpZXPc+cCS5+YIdRZgZh2tIY+NLw8/2W6W2eOh7xNxydynNdDekwxUkK1I8T
h7OOcJbOMd7K7TX1JOiKLlYeKB388XIywW8U3GrLzyEcTX2vWRzrv+/S3JzUsbacuQVDZF7QjTC2
rcNFVexFhGaF18l5V6qWOA2ZBdWN2E2GuYPR1mYO4feNbu45U4q8iv3h345a6iUxWLe6FFv9PXZC
2SkmQuyrUaSktN74fWWVsgwgPx9QrIdE8PTQRt9y8dQrgt7knYaR0HMxzz1oULUYi2Wb3yR2si45
NM5vSpZFPoEQB+ClX+JM6eWvO0uRT2yuOo8eRw19UxXUiWpVIQ16m/YmDjT/CiTTWgJpFYLMNJi8
jrTeedNXw/uI4tPD9EuyzvRVQoDPiO4ljJ3DPZr3vUixk03W4r1BOxMtXGbK6uzNaHYEzjrMfoXj
X8VXMzOhnBczmJTDQvDkEpjwGDcEFqDa86XMsYIRw0LiYwbnmOT9As30e8mDYiVeQdLY4aZ5P8fW
ByJknQa70VN0rIRJtTttqWO7ibFajRhW7iUbkJ7bS5aOgEEhIf6W/a782TPlN4sHE++Z5gaWXxp9
aTGLeCbjrYXCcHZ7TYeKwQnYdd0ZN9wASamBvE3MugyN4tVbwC3ufiKCbVKpch54x0JairTUHoZh
f2EyKoo++MTZvLbZ18p97i4GsP4+t7QVjLNwD48J6Hc8wwpJUPdqmqlV+xrADkZpd97V0OjJDbu1
aq1d1MiJRGPS5VJKunESIBfkibk+CA2dY7UvYC6M1Y8P+rAWLrmkEr/axBL8USOsIUeuClNslprX
TNBIcBt/SsDCBwOT1r3nO5folNMnmYBl/1SvWq3U+NloZgbxK2I086Avc7W4QzGw0vD9wpUrQDwd
h4uZ3OIBrsSjFb8GHBy3Bq0a9Vo8QznlfVASG6dIX8pSQo658G1gwzGA268xvX9n6jpCXzp5r7hB
eH5/aoNDLUlmQHTiDVbF5rper08ogPfY9kvEPM18UoBhv77eJ9FidgR+anS7mMrYaSlLdHdtP6j/
AyZS9mCLI3b/IQcBxRWRaAMZDVXcByGcTfdjasVcoacHJDEKk9pa73CNy8vs0Yd7CygdDy9R6m99
wMl8jrd3i2kKEVfAvREFNgRTFHVAo1JMZ44T1OlXWn4O9zrPZT/hGNdUiFsAlrg27zpld4As9Soi
XHiNCuo4k1rXeJtSbU0DbhCciDGDUU1EBLV8gLXCPlPB84ZdmLCdQ6r+s+rU4nLkyofCfSzVdOqk
oUY53apC57UrI5uQ95Q6or65bg3cwf09xQ83hENDiX8fAhkMYt+bdDS+1zWWhO5EfovFpldfzJ82
ZYe0PFsheLBA+oaRBMbr54gFQqBryZzo2wSZsgW312S1mjBOCfBeC+s6mj1FIgaUN7tZ3YR5geKt
MQF8sys+YL/anULnCOuQEHeEdFS5MBO6S4xkdImTwhr3r8hFYwMIVLuA1RiwBMQVhA/Dv4EHNyVt
lXoSfbdAG0HJDgzPj1NuEC4fnQ1BGPZ/Z/DF0xTsk/x8LUBrf6MqOGuJagrph3xnlzm8u+mteUPf
DtYtuW72yEx2RB91tTZdKWMXuI0kSuO6u3jidD+tBog/EpV8FfcZlziwDMR4NIl2UWUPFomFnkol
qCF1WbggzgrvtoAZdo2nzKPMTKF55H88EnV2wY6L34MkFlKvNI+cQP7JKbXdr+74kip4zsAmTUgi
SM2+IpcRIgAksy4xQLVduSveqz2FZK6wWwlCW1oiOxRgpb+RQwBKKCQCK6izfjDOjeWJdIw8jOQu
MRFeGlr2jWc52Wl+1j08ilYvQTFef9KRQusA/l2CrbUQnl1cTkbw0XTjpp7cTUi6vNDS0f21bEer
scB6d+Dd5Jp9aqhqQet+xtJS3D/M4EIzeHimLxjk6QA80umnwH/d2I1jCK0oDYkdtsxyTdTJMoq6
XRJw+pz0YKpO5wzYY4m6lA4KxuNI50T819dI5N54xN22rFEkkkH4AYUuE55kKE8fkqt+CLNw4WTT
lWuZ3Cd1q58UhHdK0ikbrFhFqx0nrg6f27V9TY3DCwbjCXrnCNccEh3oY/7W9A1SfzqcRyw/R69j
Sr/6p56IEZxLQja192nWxSIhbp87yxpeBgvaPU7ouuQlPT4CpNPVR7Cwqi5EIVnsgrZm2sDIYZ8X
xnh/ImBVhYktKaZQEPInHaCQZWYH0DBz5AUDrdtfEZceDMekRssFv/sa75znzECopBhprpan97kC
a8LPZiPIcxb9Hob9s8aGi3g/czdHLPAsH7AxLoU1i38Q+i7p4zKOqmt+zC+jmwIE7tUnAKx557KS
Da8qOFHWIzrATPeh38r3T+TG1PZptyzKbSNOptwknDGPtb5picD39TU871U11ONxNGsPZLHynuvA
rTX+7aejtBpQOobiJKBEONsBp7zcd73kGIgqtFnSa4S3AsL452uctLtDbGJwgel1HpZdgc5AAyNV
FIbuuzRCqwdTKEchaZYky7NgShOQ2CkrLcyR78oSdvQ1OfuJ2FtEYZQKM3vZyq5Gdo+oevuMS6Yd
WDIYcxsukXBoLEne52rz0b1q4ozAwIWjl8D4iwOVnyn5YYiQg4vV+8MEGlQXhccYZrOXmFtVQxxQ
22rpLkaHExH85Jt0DnQbzNYtdV1azHQf4u8neINzzIH9fZA5PE1LFq6eBZ1Xf70/EN9Vg533Kcrb
frPXOjiwfQScbwvWhb7QPsuFudxdmN5BbI6fOD/eOyXUlDSkVFTJvcqR/8kFHNQRC+t7pwjX7xSe
bdRu8Zdqwz5WN9+J25KT6SgLrh+w9OAGVtX/sD3/UmsHMjEOGqHqbXXNTzpsHr3vB8MDRF8QHRAX
VzGnx8pOsFG89BjSKnEgZTg3BndxMfHLvK35A0nLDV+xmoaedM5iZuwWT9OZ2/J5KCRvcunLOU/N
l4PNjN0p4/VlQaVRHoqtNY8qtvfNeJ5PMqISDd2omo93yCnangaynNcydhAQkPUQPisx+J2jiF+f
JzyyiSkPHB5wfLu6kt8F1JCc338rkRPP6WEIpmmwOQBFZbcYvyfUyGTOJXtKgu/PPOjuz+n4+2kh
4gFtqMxb2mEkv231SdG+qTzzJM5g+2gLoZuc4vwnX0MiQlQXVnDrWMlZHjRqivexkVyiZbyT2WTl
yYbkf6YKtHeRswnEQdimGU1Ao7aK3DMmXYsKsNLpfIn9/npzrey/mKckGMnBzPL9LrCjIxxAXyEm
WMos2h3aFi8lmhSF0pdyNMH8NC9kUqWBcHbEKvC1tlbzrCnWkW5+NX/iNEmzQiwrb5JZoWJwbJSz
/BehJmJQvLWflBOTuVX0CTGCO1Lice/irPC4MNZ+bECiGq3qpF+KN48dBC4fx02TO6fVlr07n8/f
Q4y4g1Vr+89iHekDQcyo5yMIko4y4pNGugwewHQxm43yDjB5JgA6G1hO40ibwvGlzrSh3cgKvTfx
Zco4oF4NDD2Mnreqsp3c+GbY4DYyAb8fQ4tf/DgfoyFFUoOObE8sztZU3hseeUhgSyDReWCEF/GC
rmlvsDuPGtO+qIFnz+kD2u4XiOTBE1WxzJTKGtOi0r6RsDbXXeycI2t6m0AMvhGD1pswUDF6TTON
c4bIkvS7Nwd6zxIjGVgdSu3aJ1kzehOUGYBbxWEIBBiKiZlbmgWnaYQdF7YCIBAC6rnJwFlcPxKj
6cTZwC4abSyU6Q6NfEvHr89G0U6CTCiCcJKUZl/rz/jJbO5Eh9jUVsTaZiOMCPsf/8XIw7bTGue0
4hOMNJgbAl2DZCKu0hZ8+IQkuAM022tVi0uTCcQup7KlX7jmQhu6B/zCHZN/B/l7+4BirM09SJWp
DNKesj3ZSRD9oTE991na0TmPpvhRkL6HddL1129wsDBEgmu5mY2nKZ9v732MrhAESzJcm04+0UPW
pJuprp6/XPCVmnaATIrcgQpjvQvq66afFnarwGBx7r2mvpfgPIvI+0i7v7z1TAdzX830FRKjOf2y
BXGZrrN2EVOMuI5Q8wVSEZEG30bwBox9Jt97NK8R/IgA+DnaUE+Idx8KNMYC2FKjlZTVoV4xEIDk
MxSnarWAoK/+bY8CXmU8ytlbujLHtWbSrCflV6lt6gcAGRzsbAgR8ybCZuS/W8brnFTxOHKi51eD
mJVtcnWxYvuzti5ONZynF9oLofCLKl4h+rb+ooAoikmOAZkSMnXCuwDNqZNlv9sMaX5U8f6Kx9UR
BAyk09R6kjD7gcukMqXe235RNwODjKDYyrO7q0dZvD7LmQwlgqSfUYflzc3060XkPKR6cr0vxZLZ
2xOFSdJ+hgxKcOkiGUwGVbR81vrFXezCDETIsaZ+TR+U78TexxBBHouFPeOEvBsStDPjR1JAFQrx
+z5GdbeMR/6myWUeDvvpuUjQ3JM3GiNCoZZtvOExrXc76qzS5r1DK0vY/Wni+pE5axhZhjs74y+4
7CCVzxHCpDYS6KbtSmLNWNfqUKPg8nWnRas112CFEEM6znDb4TIhNZNSlXKbcZBzPwKWwc8U9VXn
DerXsroeKDl7v7VeT3eCTWQ3LD7RZY7lDqD2/ToDsxzvC/5eq1wsdfQB2wIYTUrmcte29aJTjhS6
B21TQJhgOAl2Jt75XuLSBgMXJSIt1p2WE9pXKKjwe3zBG9UZb427jHiZ59KvX7N+jU2BrfoHkk1I
VAeNzH9oO+RtApoZFA36RnzWLUn6LV/jMFqZA3+YqWHcvEryb2ElUknKAxW6hzvSrxKRjgV1JdfP
wSJwMVtqgnPxumIqcUFvZJYh096qgxf8jkwNv+WGjgoit1RGkvB9k19veuvWawwMXwN0BeKNDqZP
qF+m0Cxqsr0w5v/xWB+B6Y6t5kqENxCk+kELtXQs0I2aetv7Rk+KlTATmTxpdvqvpaIKQ+7n832J
iJaa65Ag7WxPKx09pcrDIryKU3oFTVDSQnXzF5TKvM+ZfrEYu60oxhiFD/O5Bva8bOz6HbkCnbJK
x/+rIOKpwz6HP38Q+eKNGASQiyatkuLneZC+XSXvanDImhLBdg5s1wjICW3wSX/2JcWLr0xDU2BI
vH6wkENF0Xp5teFYxIr6Daaq4FcaYqE+tjkXGwMWagO0AddJfdiC2QLA1AAoPtjO6+AP2gUpuCc1
91NrjeziaPqUP9UXX5GCJBBsqBRDjAVlVr5Ka/BuDRg+pRL9upG7kr0hWdHkunYImcEoqJZyIJYL
UF5KvJvrRldfVIwSkx0YGv+BISNq1PiBEQOICVprGVe0wwtnk/WSW1kIqHDLrojturnM1ScaXBkm
WKVKZgMj1+tPaXDIlnp6FVTu2UOT/I3/DnvCTigrvHsSIOaOJnWgHgG9PkETEhMgj50ayUQP/Wxc
FSXBVrmMYRaqYUhMEj/jDDLLZzDHHfxxJ9wHNnjfgR62/M63p3tmZh3tSwWd5cazXI9EQ6RYIZx6
MOGQBFuuwlhLGQX7NeFHurOyJxh3n+r9oRobNMVr+tmd4kfkkCO9M7DH9eiXRuk+w+iQArNbBxd4
ixgKD+ntNb1yLIcHWk2lX27QVQJKqNmk4JnPmeMRdhPtbFQ0yg5mLr40gHLJz/w0/zOnx4C8ENG5
zQjzsu7EKrQ93x0LTlaqxNfJEs1xB/Lpp6696O0UYUhm6yXW9d3Gi8FubmVULcmPSb/oVxfgBzBn
TBCJOs9pTbAn3YvqTpQsm9NXvdh1p5uo11KhaDQq9oJLIdtD2lsVqGCSbEaDX6wmRJkkR+k3ZvtK
cJ0ARVHzHIICD1Xe2Ncn4x2NdGzz0WmzmEL4iOAUfMbFipiSPwA/AfdC3/ryrQSqaNgop2YzaVhg
9y64M9g9yhmKtcQqi3A1B1mfv6AQIS61JaMPP4mIiapGs+RlOQ4EmqMHLAigHVak1hK8xh7U7azm
EWUVXBwy7yVPJUjCW9SWDd5eaZch++sJ+74918/k4T6HtwGuLxKs+//xiKm1AnmsEajCAUqumpNR
NRpx5wtfF/saqIrgTIyJUmk1mZuVXlrcm6IE5IG4dA1EsNMR5t5q75xxTZsQFSkczv7nUkWl4ADu
VeWlYuewoQ48jUwyxM8Bd+7TsHMkZUjLfgvIYcEOU5++cIbx/ZqRKcsWvo5iqbEjWjU94rWuezZA
XbuFaUdOE+jvxcbcHQELIkICg243B74Vx+iE2dPOoQ6ba9SnNi+LZrV5X4Ww96lSLV66a0yv/Gcb
Vj/ka692096WakRwuArvHCmcHlYzrcLdsxGAs+agcr/xP1wCphYLiuikI7XuzZvKLwmwpar/InWS
SdvKqv1iERz0hQoARW7on+xK3hKYT0xUaF67h++i63k+89qhVq+ROwA921hoNOuyS35V4qpSVSWD
ZSb45o7cAb1NCqGBpC2UDCXtC7m1r6j7TQCPk0GEpYMA1psluMfdhzDeK4JUbf9V109+ewhEHrcH
fcokJgam8IbBABhB2dL2ctSJYKvsCkQRl6rj+HmHoyTQ1gKYGIkoN7TlY2IUrCfHA8KD7jbmuFa6
g2488IMhEtxWZgKrekuxWmZPe2pYbHXuNcBXoC+SLaE3jJ/gIIabepOSXq+GaD5KvkABKS7c971N
Ek3zzu++U35VNNO3mbCCQdP4qntOV1TaZwUF/yreYkSsLXl+kBHH3kOZpwRaIEjIEDqZQtKLw/k8
QpODhSbUSmsuXs4f/7M4VulyX/15UYEzhUWwsQpbxlF8FhAgWeAr84czUICISNQiKvsQA+JlrsbT
jIBkLlO4kP8/lQn6eOWFkHXGel7mPZoY7GiQLzVwmBqp2JLGE6N/2jMyqUOsFvEq4LpWaw83u1wR
velw1v0PRjqpQkeB1qSOFdyhAoYGQnCO6glnNwf0oAGGVmHIZJhJeGLfoxxiVPa9vDkZKyf74Ey+
iEPLkeVxBWdqoa/VI901+lJ5pfUvJeDOSzjSFVf+EYl54nMecX8CxcbaDril0lwu3iftu06lvEn+
FE5ZvAy2qQ1P+IjENaftqHuf1Rj5nGwmHX7mwnt62LOix1IZYB66AOms9biulcXsbTvaeg9WAFvv
RJyqDxeYTt9+Wachb6ooqDB1rvFQYNjJWliLkwmcjohJ1i7LTqFJwM94cgHMBboTGhDZm+cWFQig
QrnMhSO8uI/xdTEQArbI57BY2wFnpeaJg8u4scmihCNHjt4j+E4J0Ur1axQrq9RH5TyH48+XztrD
hcNIT/cMOGKGx34bENIzBF88XFDopb3a+awblQ1SNib48edCRM7dGVooiRIUzD58QhxUBYe+aaJa
cMNGvbeNEuLdG1aqP1+76+ePHlfRHgmsZ2BTFde3ltwM6bhWbhKbmyK6mF+t9/uva/j7Tw1p23cK
0tl9RHsAJFAnYAh5xmGAzMi8pTb3SUY84tqJ5Ix3JRNRsBILh/Jthi1CoydXkZv+bNihB9s0O1N8
k6xVIrW6uT3WMehpBlIpNA3O2NG8AoQA8NMA1Y4SbYrXo8iP+DHfxBDvEx+WbKXCF/P236sp8AEe
P6U9qoPwlVpqiaCrRGxr+Wg2OJVgpogfQc4rqREOU+oqQiO1WRLf+EkJul/xHGCPb/NSeVpKenzM
qF0EYDbqSOucxMSKHh1xgaI/0vyNX7YRwFe6zJS0NBxkCYl7G83CKj0wFFidNx+an0yrxpDN/PCZ
cWEwsEveqdcxjx+pNhD5jHCpOS85VDEf+3Bsb2HVPmUaZ8i+LlGBF/vFclAmEqclQSf5URglrOTW
+yThs3c1/C+6oCJpUxaNp1AfpOxMaB8R2uXixYse+hjGV5NUz90q6bRkr95SZH6Dm9JsrKQ4tMYZ
JiBvsy1YEN1St18b/LoRX7jlV0+yORRrMZay4V7ET6kaj/FAUfcJ+a55alu3ZSeFbwCZzZK1qUlC
5VIsd9rD3htEbKdcQAvLCGGeKHr3GPfm8xkBTvNCGrqTvNIHO/A4of7oV5Q8MQT9hsPtgHk+1l8A
/szL50j6q8rL0KddMrtpY1rSrS4qdjPYC7FQkudmImo+06QVgAGarzWYfgGMDFk31+O57PViwyBe
N2h83cF+50xGfEajXWsVhkFQy3BIzbEfhsCT+EsgnubifmMqq9mffIw7pH+wkbZq11sp9JG2/LXv
KwYfRJFXx4eQ1+Xps4AFdI0jkOLEWupLO9Ak/LNIrBg1sbDfmSgee/O4R3fuWqi/vLEVbcaDnfqj
FlmU0TR5wZKviGSQsUhxKTnBfoi4l1YTiDdd92AuEtqAd2niW9FstzejQK+r3SI81aWbHB9Me2H8
kuUMfXaOlBKxst5yBlJb5tqdbfGb/0ruJ6Ald0ywSV9S9HskGplDABLwgowx393nSnaWEiiASYBa
y4Z4Uo/YNumm7LhxCqR5cEeEAdiArJyO2GEYrGLGTatc1LUwulpJlGKad5Sbqp1BtarcM8awF2Za
4gt/7ROM+X7MCNafBuWi/QKrspAC75va59AmWq/2J6Zc/Lktb1JjxTRCJgFQ/d1pt8hDzMfEmJrd
95q7F/0IsO91WF+Ojwim+RUBH3NgoPpzJXhwpM5COU4xi4zcD/Bp7L1YpZAOoHyb86KO5hV9NskV
LwvnkMjkatDRLW8ngByKuieebR6TbyYj23liE+XE9kOdvejUQKw2ZIbE4+reFsTcPwZc1et0/i9e
kXYgSHdPx2y4LeeHMUsxas5E7vV+wa5kiFoVf2OKLLpN1wSZPKb/ZfNmaXOATTSvWGi3vWLlk8Ck
VkPBxtPK5V/2awIa+PNBfPwcvgfH2NO89wFFvQkOy/j4kFnV0AVchgsl/LYunLHWSEK0jq+9I8B0
TVoFJK91TiihAAn3rCdZ1qLlJHt0k2lFYXiWvefWUD4OW7NUEaZhxm2JFmTAKPxBSb3LPUM/ru4D
ZEt2Rbm6LehGeSvHBcq6jUbk19niNd7fLV0d4igzOAzy9sKyWl022ldocLQGf15xPuo1ck9e3zQg
VJdoza5WC66NkZPcc/2g/8MzoDd2Nr2D5tDtUhDdNLbAMIpz+17WvkLGzvHdlZJ5W7/dxUD9Qbm/
BzfVNSFJ8stX18e8OdbIG2L9lFpSMuooNJ7R9kIg9L8VcknV9ZNYUlzEyBUnMLpPVdg3MGyeHQ+U
qY0CyPCA+83S69KzroLMboXaecTzTDxrzQJzU0f71FBw41brv9orRZdCJJGAek0x7B528pPmkNbO
ERuC4vBAJnlNF+36QEg8RrcKFUORkGNFK+qxQvBA3Qen8JvWx36QcYjq+Y2qXyhBxn2NDKzieLb+
KAMdw9UVzIwgeskWBCIw9PEef1BND0iaCcQmvz3VuMt5MGREwYJ9ASjrLDVAPXjYu6frrPq1y0Mx
n1bhKWV8LYNi8UtdzLTdacqyDRS9p9nbl/9YUGjnTEVghL+6vQEFKP7AzWbkTiYCS8+WmdhGL1sW
drXPMF7PXm6yyny59K9zp7rvZroVYxgeWkjfnoGUx8n14YJ9lDnpsqAZ9dCyU7p3TbBgU3oL9aOE
n2uWbc+8I/GQ26jY6AO+rrgoX0NHlSgHEsqKerxLPiOAry+z2n+D5YzFn/s94ntbDhhhlXHyxk+Z
ghbBjH38qiT8fAQIjy/IB67dv9UzmJFN36h8iy6wdeIHUZgYVRza0wxFJCuFLiniK0+E+6ha3RC6
PC+JUZc+UIuXl8EB5NRl7SOsde7Vc/Ck+B7JBuimp/0Fgwi1L3v/sWjLmLLh83LSvbDR3m+wH2/4
DH1IUglwXzeOHQEhKrQzra9sL4DszQ1+hDDsJ9otGs1Vvla/jZAqizYXwPKTv7LfuJ6kagX3R5Ey
JtsvN1bXDXKrAqldBZgQUQ5hbicOVOJEuw3gSPminM6CjyHi3FNujt6s24xLitPyESgitIknDC5O
wSdjXORlewVdhN8tZvC1tPMkXnLc0AXjoa5bCCxEEZJiVnVBiTosx6gR3eXltxMUg8QW5N0rasHB
E+j9UL250rBqdJgKWeA7Fj7aFKjk2PKieudLTeyKZLGtABlnVvH4pegYa+m9AqxgzdyBXD1phcFd
aic+/bolyzj9+H702cv9TMX0jO+Ru3Ih2rphsz0vN8pvbhFVeSW8TPS9a82L0oVOp0dBa4+YUAG/
qoyDf2Zl//Q0uIiJCdKrxfDUn6NVy3XKGLgm9VbrVJIsl2RMM6R6bak1f4wLGe9nN40h10nN/RJ+
H6TpjlYQLQ37MhUHV2AhxPFNBeHUh1nET4zPlNLc3d7Ggki1p4nzdC5M9KFRsE+frOwVtUs61vxJ
sOV1uNaLl8BLZ/Bs8PS9MylM2eU5DN9nzciS3gti5gbdofLCJs/7t6Si4/AJRtmEPI93PSZ3PpnN
q6juPVHDhCVDGe2To90k08rj24M5B70sAUpkkxC0KkfMShfu1H2KJlzmJOpz04Cf98WwF2pjZV+g
SlDxs27lt/Sp99LfRARcRIhBzPauUpzeJN0SUBC2T/MaVMDA0S6bXZP8vqw9f7VPCodMhSkBiw5Y
liOkZ9G1BacDKrSjgxPzvqP9ociDtKG2C+Hul7nnxM+Ns2RoG2k7l34GAIJFc2W2XG/E03R8n47+
XBRhj4pg+wqAz7Pls1fHZSFYxxSub239fPKwCxMa70uIdkc04X+drSRrU2hbDws81RfAffe2M7hF
mh2y43e75Z8w2t8CxJjOlk2EyFskWV7UZ1ctU9zhd9QQDqn023qrH/VSVivQtsmK3z4YFHNj8v10
NEKQZwwWpnTBy7hQPGyvNIW9mKBEhNOp7Avuoh0FxpXuCZDR1qCCzOt5+rxT6Xf3ZsZFLcfLwT6N
EGMSuLIJPYUOyDvCoJteoG5+hJPnRhmZ/qIR/hWqTv2C9uOBIH6wX5/Q/ulPDb8/13PEmXHr2FPh
MhNPekh6+98kRICySvkA4eyN4X2QdzzxcLUqNeWFY8VaI1K15eQUNKZf3kPJLg2gNkJCkBHRiIEy
wmQtfA7XZNZJUyHrK9BUEhbFYZsPvchkltqCiLoaIdk5vRL4ri0VzyAbEAv7KbJu9/nQ6en1/D83
dyZSTBA/4kTVto2uUbgkweOGoBQyP02aqZ6F71Hlo+Jlk8CG3CC6AkxE0ZIg+SZtEm8OQhDxWn4U
5V2DQIR/zY3/3xW32aSsfu3mOkWRh9hGayW22okU49GzABHUnXqPzHpZuhG7NmkvAAfPjBKQ+Jl1
rT+vmyBN+A5gvg6x4+f+YDdzZDpS4x1vCSHs8naDga7k7AkfBn+MQeUkzE70SifAUaV9yjIioig+
LkN+oBXX/qjCDn6i13CzsANV7UUFDB4mSWp6zekquMRFthfiJXipBZ+VUwvQgFX/WHlSI8F2lx8e
eL/f4blgftdLJkzWLwquWM6u5tI7sTKs1hiebX9d0eEX3G7m2n1I4OCS4ABCKmgeTNB6NYMXdxA9
tZwkicgYUD1Gyt2QCW/go+vQBs2T35mJwD8P1h/DcD7pXPp437pcNpd6Qm54ksl5P/SXJEdhxTml
SWKCVqsnqhtKFFAY77HBcVzKaREbU3uy+vZI13tLGdDY22yhpC3G16jR9/mtmhQDZlKbf+5R/046
8jata2apMZ5p/BMjUSQ0yzlH1ubirzI8IQTZWrmCElWzxlZkGdd5xFoBn+A2dGnjCkkuJUn/CkKj
h4rGGgHVrWmJNckWPVWMzDfWRPHJbdu8Nfo0VQ7vQGZndUL+XFvlgkU2kxlJO+48UWSWxiANJFkJ
UtAAqr/LuL94iNX+vIIsO/N7FMICv3TjKQwLR5baCcQ0BBcEyaSipicC0oB+HVuNpJaC25r43/WW
tY/7wQ1CO5JT4Uxk1+RLhklZoGy/8tJ01EyKPDpihINr11iPhaYnLEg8Pn2cp6uChMZeP0pnbKaA
e4Eu289u3pNJtOLsMMz6h8BWIvPdD9KNw11IJt7Ik0RXHgNBz4GZxnFArQNC3wUoFnH5C0kYz667
Kb7HwUG12Kms+3tLdmROZV7dRx3/5HrgmcyAlRthlnZ6hiLNm03CQsNbYnNX+GhQ0N3Ru+AF/lMC
Sf7i59aNHGrrqRcFhmTuh69oc1NG5KZsUmtU2rXhbULNx5PRtlq1zy2zXjf3lxn4sRcJR0o1lsj/
xI9UtE4AfxoRbSW9PsaU2XW5W4Th/oPMNXz+ccihIavEo0R4oyjNqmtdBhSok50XAlgvUdpoimCH
aLaOyGGy+759+eIfTSLbb7xZcJZ13Q5US4bObEeRJkrRun38QGr62KIt4hB7Da3pJxTZ/9abIy8R
dBpOfHC4bJi/Q1PF3s9MK/tRAs0vyeWn4/unLMh+94sudz2wh1WKGp2i76QHHrNyzTYelAZzuaJg
f8V7/FSSNFyqxBE4VD/sTSZ7ZbQbXR5vAH0eGn+0IkX9mR0w6URx9C4abgc5g0/psEP6wwLW8/kD
HIjs7FPWs1AcEXV8F7ksUB94Lmu583HZ1NItJ/yhT5g0+bbPVPFK7BGWwZnINWXMDxPTzikeSA9Y
7J9781VU9+AtyZ5A1yLUnuHML+6sU1jWrvCxum/t0bW74ppUUUJEgwHeS7qWMd1ztSAY0c8bqxnH
VafvhrqSbgxOF5BymIyu3u1l1CRSYVCZH59NhA/AUeNbqjnp77Lq8wAEVDWLwrOcfGF8HQi0jez5
c5z8BAEkpRhFBUTsI9khNlGnJpZRsL3z/lsUVoQeI9tfmg2Y2wFY7hK0loGAShskWT+ckEByH/dS
hCzpFMuJzuTKCfhOsld8B2RbfV+YvnOqAw/2b4CxV/QoBdjNF+ZboZFyU19HwBBZgsQsr7BTEBSl
wv+Br8v+PUpfrjxqNQoTCsbKt47scvejrO/DMF456kHz6jKzLvzNX3RFxKOTgqBneX27H1QLqObj
VnW2Cp6/Di8cpqWZ1G46uNrZsZKu0yTLX7vQt4pkajjA4NxuKGHakoFLFyGxWG1KUrQEju/Jeytv
mKmd0Apj7vb1ngRfB1rd3vvwJt8qVFcXLloX/MUWtNR0AjH6fVSpPQ8SKlsJ/8/0hq+O0dTfqyES
ZTd0pjWH0Ww64wrZiLK1oUl5gi4yyRjKSrvTUgAKE/nHfFIegg4+aYNQ9w1Ag5ZEBZDOSE87l2wI
owb9TmoiOdLBaRFBDLJ5DVV7g2gVA3bXeRqQzGA2K+kaBc3+h4Rzid2uoTUHUonG1631Tn9NW1aK
db/T64u2T2lNgEEhAWbR5/pPzOgJkRv1tjRdQngTywHxmFPRycW/PPijQhz/7fuRzL7iy7Xmox9W
9PxLec0kuiHbVTtARIZfLk3PWLohz3sObMkrVi8JeDml0P4/uI5WER9NrmG/mOhwP1H4wFM6g1/t
PC9ckmq55mkVjp+gsmyhlnzeZAxNTyNJSSB4i1sRL4I9wyT3vGpF+XeE64iupWpoEAep3PNYwXcN
gm6UIWgyiGmDYYXnSl1pRGupFkXmEzstykBsCtKgY28Ci2ilw0MepjEm/tAc2m9sZRCPIt5l2ksG
dFjwIC5Sps5Hci8Ct99klUztELqaorXmr0CVj4idgAwix7bT1RLFJjuuzaqyFc8Xjk6MnKRviLne
2rrEK6nHAUlMl0eZbqHb7A9/wXqbMrWGuTX2wKBG7b9MOkkPP36Su7Pj+W0JVNgxUsn7ChiQc9N5
bAboG/j+vOXp/A1zBnKRs+C/dQMVtQIIs/oSrNf+F8bfDb2chJio5SWB23l08yBczl/FWGgaKZmq
D6oGIgqo9QQoF5gnRUBj4t+RtnM8DPXxgwfRrtSmQbo8DvPZ9G5JRiWKt33Nz1fBARW7Z1O8MtgW
GyEeX9eipTbXVWN8Rtuo+lHVXndkkwR2Z+NJLZRPxJPh9n2xLd0jgYPnLpUvUlzEBUwGGB+v2CRh
/HfrHZEmUC75scdwbLjVtxwJrAhp0qL5y3ZoAbgSKdsusbXTwZBF2+hkBajY0712mUgJUpyF7KfT
S2oUPelJePZxUDETfHKhHVoYdqMagvU+unISeWJHPjQ3IWyqnHFv+zpDpoumeORSDga6T7sBSr7b
+XmkMAnoJ66kUEFytsNnIO1nUFddOH/nd7466qpVOYvIjhOmyRPjpOj+/o0eRYZmKwV/E72PgrK3
pvu5Hkpf24T4p7JFzWMxdflqKboKoP2f6KkT2EHhjHXOdDvjx0tRcDDy5i7a9WDt6vTtyAVG4YZz
qs5So39L8wZDuA7MiABk4c8YyZmfzg8v/2SmH/oUmsH6W2fGl8RqcRuaKt6QUYMnZYKv5enfIo0v
y1KjTxghlkrz+LlUHMz5pQ1aa0X3FoV7eNIg4wtD8FhPqHToZORLKS+4sVnnRk7diM7n9vW9ZylM
3Mr2l7baAJGKD0jhYP03D4HxeQwTYxxWOx4x3clYP82vkFqvP8JulMHZubcs8pUkviachE/1n0tF
eaftI2sjt6bZ/SHoWpawNow3gLBevar4c3MI48jY5Lo7HtQKORD+pDhc1KpnAh71HsdkaWEGh3T9
IhnLMEQ9/gkYc/bA47URNM1klCl1VcSMr6w4YdacBqrZXB0RIqZWRpNRBAN3qfQ02Anll1A8K2oo
b541t4GdSaQOSB6H1KhCqDRavRBzDNdObwUZS0vMHd3bKgtbSpq6wgsZesoNZ1IY/lsF8A/EVaZf
V800Glyx4b5hUYwCOX+43hEdTLP3wvRZYTcYiHAJbmDssBJ7lCUD4iDX//9ba043esirjgbVHpeD
Q6gqV+ArNJHd/wa7zRoGvB/OCrcbMtFVv6wZaNI6PuG4xw4k8trFNVafUsG8VySKSXYFxozXPWYa
I7dFnD0gsZYnp+NQ75Qwyz20aRJuV+KZ5htjfkZcNj5sPloyKtH1+700XF21Ct79T5MIyATzPTkN
qZjeLF3XWkDLGXhLerOoip5uxfYJrlnQUhGkyjbaQvuhLBkSPpgMkiY2/R+M4tqtbeQ3FWz50GCt
h6XKfOeji0kmMSFyxKz+9hXTn/tbGgGB8200ow87yXk17UORfcE/w4ioABUPbY/sCeyMiJnofmjb
0Tdhc2TkXkuKB5M+8JHINwlXBkbLyWrBWIx+ki0dEamZBdyGa48GzbwAvs7VgrNSFLIDqi9L9+BY
oTlLeVisY0KQsQ8sOGvMCrn4cO+C2q2JKOWfTnRYPavm0bSRQYb7OQdkXeNld/hh7TqmBf5g9fCy
VsA26Zycj6AGxbvnmiNTD3iYJ2XJdB6sUgbz5jvw82s+1VMRwcPS+F0vNXdGQwdjaD48ZuRWcBT0
IaU8JFojgzdRrXjtj8r+3YOVnLT5D4Tn7I0DqSdM9gYKODI55jNOPKbxfqUrOkNY0fpC5xTkzDsy
yad8FNT8IIt5iPy+dUyw2n+4vLwqIEHYZT150SEPSrNbOQzedgiR5OpHRfZuRO7bCGr+xX7Hw6lk
ebVJRXiwHslkKVjp3KXMzIdPlO8vAffxCWyWROeY4OrNIvJ3jkKDsp+/GxkjukbtwxFDiLw32IBE
52PYnYURQGeZGxqcT6DxqhA1Ktllm/uBWRP74JLgGqx6vWAsmDPUJZ7tL9PtqgPsZ+9MD2itqglm
d0Xj1UiwYpew1Th+sAianDLiAaVxBXzqpAjF3Tg0gjh99JMF8AesXlD0+eSl3SmMXsUx4Qz5fu8t
Q+5QM5IxtTfxiltbHti9BCGFji/pmDnGLLLkmqLucV8wyO5T09xD9el+qoV/z0ZDenzIjpX6J5pU
Bh4kdd2nDw1yc7+CzS/fKtdBPy3jqIO2Krsxzr5XjsSjxuabwdZsa5+6R8hFHFnHIyt5CdLLo85+
mj+iiukmU1AplEeGZd5Ouh9HDBhzOlWRxHtu8ZzUXutC16ehRH7/8cwf5Nsm0TUocM5E9H9FE6li
AAy5U0nkapwactCqWGUhyMltWAMbP3zpLcUyGCodz1XHtD+bH+geXL8FOXrAxLVR6KHUdXg88PtM
P6ydgSdpf5gkQy7If1mn9x1XhP9bI550IUOArLSWtapGyH9kcXpWSh6ehUOHHDfJDQ4dII9CCTgr
0KN3H+7oOyNuELDEU2lXsjtSD+4uHiRP0VOWptC/Biq9QnZH5Uc7vk7/llD3gnnBrMTwIcmjyLJu
s4MKbCR2mXm3UPmrPDzpNBdOp7Zf/xYdyJCCgaI9ic1VSwWjxgudFwBolt05BUzf4jRV357/VtaA
ehnvFuIrgzcit/ILp9R22JyRhKzryHOI4DQbHND9qokeJCuDDIbdYRt/9vLa/3cHlBHsBDPNPFDt
nTkAoR8kn0WmMjJso6m20pJg9o5PR0ZDFpMc0xduNTrZG6Of2zEAn/u/QWGwKiORjC7axh9P7N7g
NrBZHVmSObDfrqVcxk2KovC/o0/zYHgOCJeyMHWSVjORSXHpxNgy+67P3CCPzwmzHUVl5Nxw58rS
LXOLEzBmAOHqoWOkW9PDlhA8XZMsIfCQTqomn9UlK5LbohN70ns1GqWlcDvXAxzTasW1gVnQIx1f
xU1cQAyvCov5lwSH1jcJNVdTN/6XD83wkEKcJNFHj9SD8Ljt+x5vGdGpl7KhBbXhrbMAewxUOCHu
dEXK9EaSv6/8yL547jU6ETWrgktwPUAofc+b8qrWQJXcFWV3Okp9KPuHr3hlRzgjY6UfvFzWT6q/
pTmp5Uaj+Nt+hLvKZQ1fzFDUA8QM9sehnF/kudJ1BYJQ3mRo3fkNBOCrYHkcmQxJfYpuLFxZIfsi
DAJ4VYYZvMZZW3yiqZKbwbbBM39IBLqyvfyh4JI4qlK7fhHCkFvffrCvnvcJayypD7KTbAyjlcEw
0HKaDWWci9NdZ03+82lKb/Vy/LIor6i+AtE+55pMGqMrGtZqqy7UHqjBYUrx/anUJRq5rhZ5DW+R
ra9epbM96Tm77uc5WD1vX8TbmCJxo1qFm3g9OsjmD7GprvlYVu5HvddDE0YrPCns2u+dMItbbO+3
wZfHrgmO2G+x33uuyiz0omtVocKZHgCrNfFkB2IOZGVPqvh4OTkSCpAPm4vmnPe3NOQESRsLQzxn
kTglEeFMgif0T/7VDn4ZNRBqWeGmuD2GCWm07SYQMu4CyZPXu2Zju8cU6QFlow5vaLIHJrMn3xiz
ie+OenR2U/57fZvAlAraXVw+jInq9G6StTCVcv1iMKBS+9kGeGdtuJmD4+qk9UuYGUaJN9I47SsA
ouLDmlCbIb5gXYMw/eSm7Ru5fvz2dWGt26Vty1CqthGBC8fy4zV+2DXq4zMQgUCU5dtWkxk4WLnG
to9HRoAq/WI11RWTAAK9oy6ARlBsArAHLRUb+aW5q0uKkFW8+7DTQB0hq/yoVEYrDRrdSW5cPQXb
kn72D9udZgyFcQA3TeHXX9WNwPmiK5f90Mt9YKHnyN+YG/w45IwRJ32VypLdBHUgnKlM1ZvQ2PqQ
ESDzbzpTjg5kdse7pOsI45yfS0fC891eXMOLV6qu0gN4mQs/clIGdwVOKCBJV7UZPthYu90C6frL
jddsk0L5QsxKODq9Az0ym+biH3YDvUvx0mvQ0KJ0rZ+1i3GV7+KqXNoKV3RvOFParyKMZzlxK/J6
iRIebK1nPctrpi8Thd1YkxoKtS3z3uzimJ9KAvl4f1q8E3+zMv5J+fUuSnVTXA9KJCKk5zLJTw/G
1W5UIqRTBl9pHOJqo65S5ZqfxROvP9SBmlT4ftyfH52t/FmD5NmhjvZ2VMF3cn1E/CMih8tld52O
rPZ9Ftfcx4hT7m6iNpqqYagj5IiMvJARCIaiLEZb8UwK9oEiG0b8hEpHMHLA9BlaUeTnF579993Y
eyWRK3vLezA13AoTBMZTgw4OQDaPTcYWZERQQjLMmqSlAEUp5Pzoud8X3ktJDo/fSr2xGIel/dfd
El1Ouqq2TXRLgkdoh4FO+9+OhezqiomUNvTSEuCAZGvF1u6nrSCBXeL+odraa0PHMAie8OkO9Obu
0mb4IZ41KD46pBHzd9cHJlNPBAfExtOHGDDKamIIsM2E/uIx+rtSkT8ZkukgNk6uU1Wgtu1k805G
0dTekGOrAd1Bt8wndusLdSTd/dKxSMcwFF8bLeCqotLMAns82iNPIqrQJi1ueszauhFNeShjWsOf
Y1RVn0xsj9wrjq5IQir1dsXw0zWUAqO5ZxSFzMpP3rC2ZgsPlz3nS76C+R09xPTpb82K9Z6jCaDM
euOMoe12ex/DOik7OqVft1wQj9nmwQjlSN0mmiW5E9meMonoxaBR83M0Cjqvq7zANX+ruZvv9hpo
/V3m6EDxbBR8WNZMg65w9BhKq7UZ5Apps0gn37Mtwycf16FdR/zmXy85ltQCQpEnOVl5rqiiYOAt
YEtic9m4Ml8xmRJJUta73kxvXtKSU23Hn6GjenM2gWHqo7Mck9zakkFW3hZSW1yGTTuyQYcBQB8i
pB7ydSU+csAkKJwon4CikY8bncsZb0S0jKWvUNaptwpRUpYcG6/V1I5eADmuI3cTWu6R/Xr7gEKI
MABl+2HKQYtcF9efX15HdQLpZxPEYleqmjHMRrbqCIjqKh3PW9+PHyd18hSHuGGrQZKSKUlGuh2a
gnWj/BE+2Axv+FRGzKm9Xxll4/sPlQ4rU6B+Jm3hjZdwgjIqk6LU7TDfGIH2xJ7hsIiT/Tl/a7ZZ
SXiiEpbokUjv0Fj9CVvMxYEupLHHcLv6dD3ICIzVR+rGbxfxVWgk4tQDHbP2A6nyw/AKiWnQON6u
fGXR02rKTNPlIyDf1Jqc3QBOWVoKWmFbjOEtS+7CDluBoFboY9jkYlNAx06oAOlmz2R4EPNEI+Ne
unMtLDTpWdRPcy+3rz7w/X1kG/xmuKFBrnLBCZugi1+7yfOLHMkW2sPTja9GQkWEI73N3FgEgZvN
A9mURXU2jg7MQgZlDfNQXk5CtND5QYGG7SbCyNjWCa1xw62qEfAYZPZNg8+AgZOpcZFBfm5COb4g
GHkEjyJtYr9KbjUpVgXYT+qQKDv58LjAh9mvZ4IX9a9A8CpTEoPuL0H7p23NRflBSIGNY6jI6e3r
04V2oOSvgI3yN6cR8E83jrioOV8XD+1YRk7qw67yrwht/mZcmvInA69uiCKyUWpCC/ZIBBmvbEIh
kkF3/FCGeHOqVLP03EyroP527sKeXwBq/z/tU0Vs1PAJXGb/BOb+zUAiAzt6V10eplOMyzIjZv9p
+PJ4oMjMgRORrOrHZYTTxAxPtAQX3213qEu5FaZYyEoAgbFYApC9S7TYbaH7gdrKpk5WWkhKI8hp
gtvJ/KaK7iidlAFKNT3+LJuARWi+rFLD/C0kBJu9oLZEv0y7epBY8vXGREqdwECnmmR8IxsSkizL
CCRrOZ1yeNXrmHBNP4OwYcCN9+okHoqAPc8FQCYiVn4WQr3xgTfB2VIUevg2DZku5pJeRaanMZAI
GGp+iawxtRFA36H/8fwZ/ecPlXIXryGTttiKC5tRx3EwUTYC5NSLdtts4ASLgnKJcQ2gsKDLrZ9C
zpVnCKxKk2RVYwadOef/Lsd7jyzsnE2F8Ltt6wmOj0SjkbyHx6p9xkpRA/uYC+uWLZazJt+CPnRh
VnpDf3icJWrH+ELPffvsTuObMRK/nuXodibP7pADRlH22NQJSUmgpz0H3IDOKSoGVYskvVNKmteS
76c/Liu0gfStXQTqRL/VgJ1YkFfZ6b1LwLM5dS8ZFXMJZQ8vl/+FziDBTNMJz145VqpSQnWTcmC1
T4+SWyowWyLxI8uFmkcIt7C4PrWk48VCoaJyopvVKbILuef9tIMAHwIaxuYtsy/z8VehqQoeFWxN
3O8a+vpMMWg2FyPA0xU1DDVTpEFO0sutFq/XdJOfY4NOAH0ZBNmqUPG1YorjOtvk9k0YV8li0iBx
DYKwGhx4SGjV5k6Yxz9+ajBu+7jc+KvWNAJaaazJlHhZyLkZHm9fHJbsV9UT8ViRJInHQQVx/16I
M43gEJDRw1rU5NlZg/Z9OWxTGcp0U/Ud1zKCxZ+NUnykMNQ3uA0EDqcZ5nRBe6F+xpEvcbCTck25
D9gFYW/pnHSV6gyX18VYDmitJoA4ijHkoJI3to4dcU/Uab4NEEFPaF6ZshbKM2x0PQaJqBGv7Tyt
uDmGp1qyAKKqgF1EBgLVfP62U+nLZPS6x0lMV9qVpAEHZI2F163d0OI64fqKtElO5IQJ6HPdykKd
zBBeUH1Bft08dpc8F/mvmIUN9ZgXRMNRRdnUMb964WoSXs/JYtnX4cEAV6y9jKWK/HWI/z19TQXD
rDb/p07G67VymZu1N5sWCMxxkDWGyxaJEKFq0hEYc/f4LTahEnuiIOqRUlh4nWXo3eN/K8YiYHdb
qfOZCpGR9hma8al1RJxd9TZaKvj7KDy/l4d+6+ZymKRjlQ+Hdi5a0qxe+rjnrgSURXsAwSKsjeSW
1yeWW7uKzKcQNNMhJRO/2tM/ykCIoDjxV0eM9N6SK1r8+GJM9dsrieiP403t/5I0gB0N2ZFFBOl+
9139iWv1RUBdvgvRF9m9RLuLiw5FMS/jn1Vd592q6xdLHMqxbamfFbWY3E01wfZIe1X7qs9OXzGG
Bta75GkiyULyi+/dhSREoWJa+LKOVu3vbMuLeekH5WVhZOZ4qGrTKeUDAwCGlRf2T8lU2UBeyssc
ayuf+6BcN9XJReQYilFJMVOTYvhNq9qVR9FkgE8eX+EyxEvXrR5I3efx37gKOieAc4xPybbn+VcD
kOoJOmsUkLCJH5Ky7yTM9ZiLI4jXGGndEkVxM1/SwfxZyoiEuK2GUi25HbiCDban2ldosFyCQDzD
wZ3S0I0afId3dpf49lNJd6GZFYDHflBUSU9jd6FPrMMpomrw0506YFNrAF3JNbLZ1yXpDr/DpUGn
6zA/RNrQCsLrXxWt1XBm0JgioRvqEu1hYekX5gh3QHeizDmd85DFdWYaEj9j02FNKaf/DfCHGv7q
ETnWjP9Eml2Z/J8SPbrxolW0ZJLOrtnkp/Hz6Hvq81UW0omqKpik29P8CHZmhRKfML7D3RGbQhyN
UBRv0oKfc82U9b5oZfrxKDH0x/MgIuyTe8ozh5tX13M2VoQOytr8CCjEpbLydLEP5ykEyDnMUIB5
RAvWU93ojcO+K4DpzsDxitGSPPNLvdn9Z6qf6zx1x6MbB2a9RpqQV6OYh+JS3uGzEnWpvm8Fxxf9
dUCq3WY1xEsr6eVPw+WIvZwD9iWRsmHgZd3THpH1rGZN+3TcVFF30yPdpe2qrsezCxbJPyR8NivO
wBhVnmuHpaIsCXhTdcyIQW9WR42TEiEhyinvS31tsgf+cUkuoQk7R0SDVCtJMyJb2+OY32b8xYzL
u5kkvYGRh9WNK34tlSv6C/jklwS/E5KyEv2TK4Z8/guUcZ7jB6ScLHmLos6BWJAtVWZUD0SIl0Aj
ffneKLfDkFHe10dZazpxBSZo+wKRguUnGKVhGzRhsgPdyio6IDGynH1I7tpgVyEA0c2o4OGlwWdM
gqDaL+dcCdylIEUWx7whOP0PyoAhaaNrDxWh1r7Ior1Kkc1Tx1+3LFd8d+W0f5T1B602AX4ALo9L
RfmNv3G1sdAU7szv3U6KxvpFrBzhzLIe/EXD7NYjtP9QD6ppfuyWNaE8IW9ecFxf9rtTd5XV1aBr
3OPe9FCC2T2pz/umXrqzgH3Et23XNVdlZwlP5YbB+DzUbXqlBFrkDyc9397wv1CQow9rdfSGYXAo
S9dYq2mrhqesAmLpq01189i8glCKT14qvIVm9zShW4T91Wi0nt3flYSE0qIt53aSl/md8zKIwc2q
6W1pK4qtn6aASCJB4z6ImRxgUHfvV6FD0F99EEfzqD0WVXSANTLEFIIM+zdttxZIp9ptTa0hG6Ls
hAdKvAR5Ugj/BlOvHWnXKIcfIVbpQPYeJcJUSkoKmfIp1EMqgZJgUrxqVMa3zWdXgXfCNqkMlV0F
JhbFM0bla1+0sX15CnDHYjkRhn4OuPGvcjWTGGcaQ5Jh5YLBXtOrn2WofNpFhPJWuv7Dxj+zCdxN
NtxIS+x+ZvfR+WRE28olI2ULXtBjmJ1QCSduBpmh/4Gq6rVuGvi6L4kAy7XKVzB4kB27x6Oyg/h+
hU2TiZrqSzafSEGsdanAwbGvuHI7MvOUSd87f4JAY3mqGnF4oxxO0m9PllI5xWcA6EoeOA/wm3Gc
OzwL6x7+Q1GMEErmXM3D9EHFlKyoXxclp+GvDwU8IrLg0iegxJYLt8jkyhFZguF3LXcAgJ6wclRz
DSoR6YibxMBWZZGHpGWySa2vMsmL/1a/N7t5f9B5GETvHTYlWkcNScSgWaeSfJKKgrg8IvclQBhP
KxQyq6p5t2Dd/l5ACXqcP2vexQ77jsGjIwXB5A17NE4FBe2TPdGI0oVfyghJCgoloUQ602nsOXS4
0Ds5MMd6YIIj4UrlKAU9iGE5TvHO1mEgc45rg3PlUItC/41J9kw/zMcqpfiko6Y9ewJ3Ff1OHAL7
YPwDuh7Es6YQfh/oQFwaI3Sa8w2wVrLQCFhGukvstWq7RFI6eSW48BHuFdrE5BkNiVMifRJTb/dM
UFT0dG1gyMVR2Q/hLWUlj/ZtRu6L88cxwPqIhzoyFfNW9VWb2hFV+QmDO16Xq1JLY7Z0JkwSTFOV
39iiVtHSObhlSC/GPJJWMLKpx5BYUc22m76aT2/5bKjShGW9IubPwPVQfyY8ZEQCY7gWZzTiuDEG
2XHoRtzeu3pXWUbQ8kaynnbaf302nD8iyisqj7DUxbjXr8Eo77wth9evb76wquwby9m6R2YBgvwO
xZdrbyBpP7cfAxp1nj2brxd28lKUirk03GqZvgbzwyWnxAPyhrJzrVZyasE8ZC0zT29U8b7iCJNF
PHW2ys/4SQmWTXu1ohLX3oANe2qB8iKzEcd0klDoONXuBc2m8EZYC2yRiVOCIzdWNBmIqK5IwXpw
Ltoc5fUUE8N8QxCvR+eVqMkB5MAGtWt3BUhwk3rAlBpWJRWZqaQOAskehnhsOV7P2FIIAGtDU9zh
ckC9/MEJh4wAoL/IQ0axhuofOmpNsLJTM/o7J0DDATiy3fXDyzThSwm9CTtwMhnj5OfLbss6b84h
M7+GxYKBzeckK3rHk3dDZMfUUIqq0e1QR5645qcrCjw+hCth6z0nsDU6rp7tjBhRyu4cfwf1M2S2
sPE76f6GuAawxBoAsih5dLpIypt9lNJdoK5lwNP+mJmcWz0JcMDuJ/ElQPxH6wcQ0d0mMMx1ZQRU
/vAKREclMqvH40f8eAcX22foKdSZm0qxpBnp99Y3oKMuo1tDaep6QS43CYndm97LLQ0k9esYcilw
fQrXP/kRcTgFVP5/tptY1kzpXbvTDRfswdfZgX5EPgxPndWsMZu72zeJbVHaNJiracJsuOt89b/Y
5sfBBFNaG1I3H14VsNOjx8krp18Oj81kPNoSdofSkNVSuwN/O75NJoJ9n2Q5IlM/zX+LDBY70r/S
NvVYu/hxDMutDI6BmifWyrqDkZVAtzU7Vev/TfvfJOZrTVwFMv2gSay3nRTHEz9KvgbFadFpXWeo
9dlAI1rhPIJY2YIgRPSGW58RZNPirHlfSQcMQhXBWEe9a9nOHCm47cOo6gQGAx4qayA2rUWtmeDy
E+lSg3KyOqYW0wOqkXx4XTfUKbLjZXGpVFP6IP7h2o3S38irCkuIu9qlMcHobbCN2/xqmwpYyiq2
znwHjL9aSvzR02AWB87QZ7ECTWf/1Eu5Ij9qA3RbE5RYX8z4TbvYjOVXZhsw24xUKBsjJ8QfR/fi
Qx+Ra5exVX4p8Wx+TVMU6QSEkB4el9v3FGZ+kIrih43WDUEK9uxhnu/0gw0XxMBgirnLst7hUJ7z
hLVsj2kSBc+HoEHl+ryK0N0rgRWB8zOHRUk6yNRo/KFHnZslwGxLzw4UJZbxBFCvP14Nd/TFx41A
Za4e+4xoTITFAI925rJF00A9faX9K4Ll/zcZtzhFVIfBVAQfKDpR8Amh6WJFAmzRlQU0a935cHVB
W9QMqfHlEheoxEfEJYQabCVi0Ra6CxUnfgXoTEbeXRakdxQrFBYQTIJGa/q/PMU6WyEfxbQ9H4+S
FC23K25uq/hspcjKsja8qpUpwH73LKm1uALXT1ZtbzIThmIVRhQKteUkQoh1V1v/fuZVyzWjw2bW
Wfj44tQOXQaOQ88MCK/ppqnq6kIM5j8Yly9f3hGpNt2A7PnxL5t/kHDsHQijit/8DHhP2tjbrHrE
XW0SPmg1SLG44TlC0TqEhMqdG4hKJ2kTnvycY2wYluOGd5hr5Rt/xafXFmgWG8ArOBg8Q4bRO920
wTvkkygfxSXuQLrlaaPPuf50LQ1aucpM2Dbw+mePnvQbf9s13WC5SxVuqDFCILokVbcSnJ70lcgK
qrE0Y+bdwUEnhE/sa+P6wYnZ4pH7bkzq67OWrfi5Q0qermZJfwnAiy6+40yS8KRIIJGsdUTfVTrL
254SjztvwCdEhp3e8NbOz+sVAbvSjz7Q3RM7UzMcng4EqUunFahH+DDT2XF7kUiyu3MC8OD0jF/1
EzUGA+WxOibRoDJFNFqxT3diXb7gzhF1vEXAnffAFerziR5ncszvS70V+MiEpoPUMe/voP+ZJ7Gq
ajZL6lW65/Ak947rud7wzPpk3uRumOooD/DYE5FCix8Rg//rLnTmf5w2do2YIWzDwTcP/0F4J8aW
XfCWkY0pbxKRScDAXPoo8nMJwIc2vCtQFUw9AhoVfBtEvWbHWPx0lq7Sxnn5cS7uCc5ADcOFnc5X
/HxzRX7y9mcM26L2syq5yMQF7CRsyR+TTXF8nXzj5j8Gz0+CNXqB2HAVtpA0zKxhc/l8Xzw0pIgT
xI/ixXrgIT0CQ+hdYAaeClFdzweVxcYdPXkdBW1dF9P7WEDtUCa5mORua0WOdZUFjW0eJ3lS+hMT
DzChEt+vMGAssUE3c2Z2DY6YUXDyjdncfSg/GJrnidQmNKx1F+yS2m1jj/+4a62K75dPn6Jdiit/
cqxWs0dzr71eJnYPQVnqLvpmlsIePQ9NOABOsQ7VCVZT6mQsC/dn9Y8xcf2V6MRNrscIvR+AQUnF
e8pbECE2dJlh4aOXmJbrWkqCZ0ImMFTyXa32LveGzRjwwvVQzNF9q6jwN3Xlx2PBub7gxeJSDkY6
A32SIpR5RqrwodjXL5CmlDgXZNdxPCKLqR/GmJSD9yi5aP4WEaKGe42s+crBApijA0SsJvpAU73+
D1wQvyYRqIbHR8f5/bSHmf3UgABbTsbH2DRrPh9nDLxFqVJF+ARnk2z4g5f5riepbWT9npjBpPEd
JHnJ3NvKcZyWkYfUUNH/yd+MTEHa0JnZsPXwWlpteBe/T+VKwU+/WnGNUECboOLJq09KA3s3Qn2P
w0Ccj9df8DRNCBnC3kzIRTu7FyaNAJ9DaWUVdD/VasCxTSpWTSbc/D9gujGqxFXorJk7PJfSdY77
xT/kFNSSrgHO5E8jf2ixJP7pqZfoAn8/X5R7xLqEjHAYRJq3G/CX5OkZmuPnOj6FyoFBbsZojrzu
5Zt4X9Z0d+VfmwaVmM3cqRl/GHZ6ubAgtcRny1u65FGcwnT7d/XhjD5NRoMFee3SB40B1dd24T+H
f1i7kO5N6NTtgNY2RFwHIOddaDN3tKOdz2Iqw9pu+wvVPKT9Bh8PICxbY2DBCA8WUktTqL46nZLv
+8gKpBNAfZD/a2HNHRM5oiBiobkFI55Q1jUOdbHLmE3niqLpHyeaZxMLfrdE5NKwe3aYR0UBzyu0
TRuXmO2FNhGGFHk8JiYwWAUY7Rf/F+El0Md/+SzwKSiz0YulteyN9+eXbNaLAaGaSGzGYgTt+eJ1
xbAvY9A2Xsnq9IAbhV28D3PqKXIziukgIpC7lBimuAwvKQILqbrXxMdBgpeSBw+HCapz78yb/hou
UPspXz7k6GWFYfscWN/Xu5+AxxgY1PuA8fUQDhpTrRaSBIhXZEM95SfPURWcVimNJdyHEMPkmcKO
kDkcUW/t/5fh3XYIKO+vOdeTeEY+CBeGkoKxEDCbvRsvg1joZo0mKlkPilpxiWnf0c2oeEiLSXc6
YIeAvla0GD6Q0VGWN6OhqK9mSXX/zZmBDU3OtGChXgRJuNU+nMLwgOCSYcJAZzWe28UdmWTiohJ5
2C+YAFTL6LbNdTT7BZSmNMHiaQzAznFRZx/qWgHRwKn4sniRKwgMgxrsQL66zCQx+0SHFCOLFhKr
vWkDzEmjKfs5q72DdJYd1YZ4NhgeCLo9l1COJ8VZ7H9ghGJpDjWmwGpj7Gm9mjZ96X1nA8et/sFe
c3KZ2+oGD2z1I/IOsInyRDFFUwSrxNkhco4XH5o7T1bDhzIEnMcOi8DWgL799FJf1bc9z/YoC0DU
LqkW3wZjxtnYhsiHOFdxmKQBCNsHFhLz8c5WIAKYtpmS05IJUlHoV0/x2f5jRxFF7EHXi4Owe0iR
IlwlSU2Nt2yBEVKvCbmK9AztIuDSuCYe4nUtelsWq6Tm1/PpukVFXdXINBjGTRy7dITXROqtiHJs
mfUeVtQQ2UpIE1dHWr53i0KyXeIFWW4afr/oD7FgaK6xK9VAjKGyPiAYriDdve2q494djKqCbVAH
QAX/TDujCBnmMeWrz3YXWs5A1Btico7rJkQ7+iuUUXE8UUKmt0rYBAl5veAw6gXVRoxnvMsXugcU
PRQKIm/91f0cBIlcDpRLai4DBYblXBRNGTHPn8NeOXxvmtGp2I9RAa1fy8ts5D/KQivurW0HsBuy
DWOXSHY4Zh53CgoR3JJyc6Id3KYlJ1HUjbLsakED5PyxHZnIUu7ukEoAvFRisgH8V2WjEl8YVkMm
sSQm4UlpBAyEqvgjEz9Ifmm2WJF3rvcJaN0xgfPZAlIpYRc/leOcXyVtaq1Uyw2A6Xcxv/b0qmOU
a1nAf21zJ6dwUA/lKKpo/uhl6qxhTt3+MzgvtBQiXuy5LwgccsZXBSTM0MDlI3gUQYzKuLIvpUMQ
ZDMle/ukPJLdhGFZ1NbrRRfOUhWgXPUOW/UnQ0vS/WgWhrPfBhE9HDTLSZAqb7hXFNNK6gh7Tcya
AoJO4jIq3eyZbHF2TZgb2Xu2jyQxM8uE9N5yCLmV/2xJhNy9wwEa5EdLz0g0fDUNe+KSLZtVB0Gn
3dGR2rJKy/Hm7xb8xLw7plfn40Ofc7z8vR9V0nY07A58hfZp1+h/xAoRz4hDchX4otB9nxH+n16h
cbY6RvdYsbIvYN2i3ZelTat4XlJ3/MkgWmf9GyIceodBwbR8Brk3MJpq+s002+Gpea7Ive+ebUgH
mnF1D3OGHQyZUXYDiugda9JcGlhIFL7+9nal6f/iKuXYiUzuTqc0tUV8pp39ZXwV7Xae7Oos6yPS
MHxMpq0/MbSmGmzY4N/C/W5KFH0NalUmutyyUyUq295SoToLbKcdpyiH1Q1wVOfNHbrgQfdnZEq2
k0dvApdaEZY4dB5iocp3Iqa2KvBgynzsP4RJKfa7h9pUGxLON+GA4jNc3Q+c0fD/29Y/bVNWpBnJ
pXVw+tbzPbQqd3mqedDE76Ms3xF1rkEOsmNN8W1r4EUkW5HOgbNPstQ1Rlgv7Uli4WDKZOnMjenP
gHg2fMGVww8PPlpfw2L1beNWnCTj5XvyOAe/ZZAem4rppo652Hgq7k1GMRlJbh7wohQBdu2FZqA3
XpU/mkA+p0TD7QdbmXUvjqFNhIx1Fbl3vGx0/ySJxaQO75ai8PlfDP5PrEEUB5cv+1DYJemJjNcV
w93viRc4DLAJ2XVXVS8qwfXwtyxbU/51DdX+Tq7AZgdy4Cl9HP7Gvsich/tuPUHS3H08tZnKEu4C
aaMPgVo5iI8t/aDBLfb1a/can8FW+Ed+SSPw4cnmFKrRY4Us94+RK3rT4jTxDLxug5OyB94VOXum
nmYmgTxHOzG6Ho1i68krwYQJZ+EG7NG45MByyq8onSb/uFcshlCmj/Cw4RWVWRQx5DGPwamNk8Mt
7U/lqeCoeZyTd2koBnvqZPRqCQQUd/BG5rK2JnWyR5r96RpmJu/2HUCn4AG2XouCDPGTlCpp1R3Z
hPd1MywGbd6VXSpZMjBeK81IiAbb+EAq1qOLxKd1afccj+V07OOKLFYs8buIr/SVjnLlL02JoSuM
OQvD5/x5unEXRsV1XuFyjjxIE11W5YK1UqRrJ8PzL+Vk+yFyFxrtytGS0E54GpGTt5Zo/P8oxWn5
l8/TuAZse5KtHa5WerbAxfTCC3gwEFEpywbrEQy9ii2AObLU/1kcGOamLLVNMNJN/5OgelUyzZpP
9mYmdX5okJjeTTzkdymqGOqKsR5SdSV3yOjr9Ml9DGrNMp29zlX1bJKE/+CnGVfcvIe0wZqCQFLS
CVAaiH/oMyE3qh2yNhcexkptjG4nEgDv2U5R3WUTjnTJ9hUzGksrrohbbr7UfOixIaTnAinlD/Bc
/NBooMOp8W6qEsMkv2W86e99ItLc5spueOWOZn9p8MPT3DbC00quQ96IRXNpdyKVnzJefzKV8FQx
A4gHPbjVb/rAXGo3mORYaRG/F+vHkbEZclqvOCFnVIJ2AOwcY/UBXpv7BHJCyWAGeJ1Mc5qgstHY
yb1tUXR6ChwvnrFkTc+BSiFCj3fHpAafrWbrhNrU9OxsgrAZ6V13YeDgt2EIh+oqik131aS2k+oL
ipBB5SxuitNyd7X4fNAXATWnmfYuExxPy+5tHQYDR88sHoBohKg2EG5YvG/96+rjgC90KeB81DT2
OsPOCUffgvBmICdFwqvTf4scNC9QzGW9EYc+cDCtwUrVv6ckWLzezo08X+bDSrJNvpxAbXn6IN6h
BxAkHQyYqBMiectUZeUH+/kSmTJFPQaUBFNuiPM4n0mrPLxVwDAPYTqIRqxUHATf0D1DB44cNrfw
BcHaFPWI2Mcsw96SuPDgtLPH1NxLA19wQ7cTXSjsavC9jZbo+9nVjHbJyTjq+JBVmDCsZXyhqyi9
5wbG/0NXAfsx94BshtstRcYve7t2BhUltQDt8GIhC2JUJBiPUjxr0KrQPWgioZnE/AeARH1SACYl
NMlO2nQiANs/TciJAZPmMi7ZME9u7VPz8ayMKbjW+bkHpBFPIHXyRYji4Yan32z+MvlTe6kb41nC
uxLMFlxwuoY9XFTcMSpqiVBVPhJyb+CP1eUCeACw86bOtQ4sCrRDwfaKGG0FhhHlw2sK3obLcSWj
CKn3pes+KmsSWXOcIguaLczAh/Y838tR+zX+APh864TQcsx0N2vIdZOn2wu9AIVV0JFC7zB24L5J
8LmDctAafKEZqjkEIG4LgXcHbaOySr6x+lHJER0jjKi7h9tHmuGTphJt2oxV/WCUVsm5WlEsWv9i
KzHKzK4k2MBf45ejmZCU3/EJIbBjXtZOmChZ/i1yEVnb7rj8nz4Jb1gt4YzTuXOJE6i0ST4YNTQa
RzRsY4k0P9znOuiJ2ASPBnrAcgL/Se4IDS1qKKoEZdAUrODd0TrxWytFJErhj2jR7tOZ4kbIeLQZ
EdeKtZklkbUbl2BrBZkssHAT/2FkmlWd1u06WNz3EOVy1uunHBHLvfQ+FlWPpPpB9XpMCSnWIPLU
FTD3NeH+l3hqQWrYx0SptBIhTH7VvnZUa2H+e/TUlxZD6MKX541uImNeztGT2yGsjzJ9SIJm12G2
SNKUTZi49sDw1QirlB7pevWHdZ9AWwCAk8C7tx9pXzmeV1dSfua/fj++7DLCCy8w0MTRlM/+tb8b
jxoYv2Jidz3Xnp3pRlDwLBVdfFsZ0VvUQ7bme6MEpgvJ7pmh3EkP6rfzC0M0nbMPN+MoKRaQ0PbK
hatOEJJB2hSJFrc1RbZtjn2RnYyfN3yE1MVPjIH1meMqPta8BPcKVyC7t2uGJfk+un40zkjgZgci
YdiqUamE4x6rJ+aNnDP+LMODozzhXl41iuTAodL6FkAMKSGRyIT0D9Wo0ZTIDsA/W1kPLIu3JyGj
J1WVEwYpsoCPOel84XUcN7TehaPzMr3Rr1P6Ls+EnE4eKGpYI7dH5DiRs6623psFU/Cr/N5AHQvY
6MsPzGUVcMMs8hsinyC7aAwmRbox3oF8lUyHFS/4//Ho5VMDmieOJeSHwcteSYKIpwobKiQVa0Hj
KhmT/ByjqjOVP6EaK97WcUC/KrJPMPz0Tki0QMa9baE0Ueak4l6mR31jb/KsRI0sT6EH0xVFK2Em
2mqUksKmxeenDoZD5GAEDt5KHi0wY225DB9pMOuVzv+CxzaUkwDw7jxI94CVaVk/70KKnjx62Jo/
bfxb7qxMMNSWf2NiDqqsCxNI9Vh/1rhDH+Cn09i9bRoO4UK0sNwX1IAtrrfnOzMWkUdi9m3aYGip
RyQ2KW75n/BoML5ODNY7XU0AuveNAxpmIN3VYrrHtbV/ADXSty7k1oEfIBhFhg+yN1HsPX7cCG18
vJkrCopSLZeyg6SVDmNU4H0DLjRV9KNk+P4BM/HT52Brdl+hfiXameQI21shnkuxh8OD6MxqVvkE
d3s8APWhTOi3fBJ4glp1yYuKgv1H7n7OazQD498GI/uqIoevBYJ6OJrSeK3DUL+VK0SyBNgmO5pB
3GROg3AYMgnvesGf+zlmwurRfwtJsxdnv6EfzdIpARGcy6EZg1BKuCknKNTNYte6yR2Jc8s/qLoD
Bg86HgB4Priv+ntBztt7tg35C+702D2iuPzPWSImzHk7cDneUoc5f5BBBVSTeH0VLtQ0Qz+Av/W2
/spcM/ZT67oti9z07ikGFDGc0rOid90j3FjTrsZiaZWMpSI1pve1nDl5VAnl+55qJ0gpUZxh5ttD
lDrBCoREoBUshPzdrcQ3R5WD4FjIHEK8qF32TLVfv16N2u5xYSoMaPy9Y1ERgzKvDYhdFzfoTkVg
acDvCAYi5eZBUn19EZV6b6qc8+AQWG4fEiZYk5/+uFobJG59C34zXzmFslH+tGSeg+KdwLQ7uNBU
qTwel1dWE+7Dsc1YU2zFKBq1Cxykzrkpt7VRK6cjGcO+PQNKTKhg5voT0lwZRwT2WpGI7qNO14lz
5ma6s2oca4ViWPjBPr0759u0pM4xlpQkkIaTMczLEVduyjUfwTYaGdoofIcVBsxp2r1od1iwnNX6
FJqwi6/3b3vLrXbjVnjxFW3XCfy34rdLYplJDK/bhZ/uDuc5qdywm5o89s5rJipDixh6/wJSHmNe
iJsbZ05Sdtxv5I519GKYdLShdASzAuL1WgrdPdD1OnGPm1/Dqz7zoMDQDdAszxTDgjTOt6MaKsR0
p2Xh5gEVhcuFXHqpfppzvXuF38PbR0GT6izTPuo96drxfr20qtq60snN5+0EbdpiN7BwaaLX6DXO
Oslo7G8vBIXUvr9i/Oh9gKehatD3xhk9bbjqcJ4GQTbsOdCm1ZHEPYBD7NnuKiAjyIJV7m+OHOHn
yLQ0BJLJEix9HPV84jWOOi/DeXhxyGk40Hc8hajBi/skgCu0wL8HcMb2ACJHXP4qF+/ofYjm5M8C
ubPc52LDrmr5ZlmxNIg/8A5n3JOltgF3Eq7nEBabM7vzVepSivWGOTepuvFDhRW+/vipomcoJOum
24MjAM/UX8rbtVYhhRWoRCofSIEAIOHlgbHmt13+ruvr6oKXLpP7+/KXYsR2tJp6YjfTmMgixXGK
zYmvEAh4VQMGq6t7Bliy3Vp9GzctTEBV0PevRVFy26bGXySlhIwMiRJBdI3bycca76vhlQUkV+4Q
9AIzCU6oRS3xehHLIua287uELR4S2mO7nT02bVKBP8ILwYWV+PuZTfcrEWWyucNMXFi55yKdp23I
g7bYulBFfzygGF9UqiqLyk0OCWG1JmhX4SQTA/Eix/3vrrAdaDjnxS6rr12fNXzRLbot3YaTw8FA
TzTrZ+9OBEa5etfWKy5xcsnhmirW9lmdvq/1jMTHokFJalSPj4VWQvz19q5lfXZH3Ug0VXb7BdUK
AqSVOfjpGDWankta2WDXMf/E6nlmk1c3YqnAMLO1Fng7qQxtBVpfyNKDSzIBZjDH+r1UGy3wPAsZ
pj/VVK+7T0Q0LnfIkpApJyIwJDbKMRPhD8F2qmbL3MDwPqmJP16ddav7zHb4tSQvdspF6/6hbCvE
9AOeNlH/i4lva22vGq5Nc/t7fwzeURrgA9Rz/Rzc/DPHyRFhRoPMNa4O9HH1k1+20z8pz9aHJAbs
EearlaV8TSlf9jhdzLskdDpjkj9EsCJOlcZ6K3okGWXpo9PwEAh0D+KAXjq7/vna8Hg4zKG/fzFc
+u9pFmUn605lRJlNyXhbcppFD5JEsIjeyKHVWQTH8mXTDmlPRP/vv2eSe0gKOzzyLaNVxh6zPl2F
TiT+7byzMPtFXkVxVUFBTyTJ1lhCS/E6U3bRwrP6aNSoQ861BHlKq7El3lOS6uL1pOOVP3qzHQyT
scb2+C9YIfZZ1d7BAJ78J8lvjI2kdoKxnDuaw9/wmb/YlCul+AbZ6ExXTwATUKvaXfLn25rMEr6R
32NpuxlqDvWof51JiMIAfdkkXHVwnLlo0Zl5bktAcp9lYU5cVdYBmQqDsNFm7Q4AGR8nVXJ8xIJE
ZbDRJn/3P2FqG98PvaIcwWwxh3YOpXSlxziTIFN+y57R0HHTNiYgAACcvORxJFE8mSOpRbVFwpl1
e+USCIHEmWmnBCFPsKiPwzELW0aBRpYFRLllAG27+pXxbPrFrLLDQLjr9OkCWqBftJEiZUXrrWZK
vKWzTsWPEJXLlYa1AsVJbq2nN4hDI/EfvihZzGdvmrfKw09v1a9lmxhM9TGpPULKYlaWlJ3EtYD4
R7Uy/l29qRLKeOrABt70d3olJXj/f+4JgzFMOstdOvHhQm2dlviZw2wOj70IhODkPFaTXMnTnulu
rC8BZfTsSyStpVIW4hjUXYgEgIUVSzOA6hPUGGAqfoYeJbejG34p1tCld4SaUTzR8oOSv7ASGevp
1v1zlb4Rcb93BMxrDjJ4kYIQEbU0apPDY08meXDQ4ts2qgwenbfLc33Y0bSeUqdKkp5SL/uDua2Y
Rl+Al+jvT0AZWE458Oxe9Ft8r3tuQiaAn49bqu3coog7AvwrRo8E+xJtEdk3TLtlYXg2KxjNRXdM
c096GSFl4VPOo1CUCnozDnl49def4a8aanmkWIqfAk3X7bhMkB7N0CKoyUL9WEZPyURHZfmbuaWj
klbEX/dpdCD+2c1ankdFm2z1wlxL1tZGawXq/mdQkDXcyJPFTpU7sZ2XvIlChjJu4CeAML/6QaqT
D9gVDjHmFh7IE0kaC3d1YSwVPYMkv0PiGZvV2WDTlkHq2adJ77KqhnoskMjWQ2quqZYyMM7nM437
3sqQY38hE+b88EO9i/cxC0/CJFevBPloXo/32wOEYfimyB8I6djcWUFKdUqaqevS801OU5yW6Ey3
s1xIElPCM9INEB2LdLTtDmTEIRK4LrYzyeje729aft+ZyCKl75g7BNa3xk81puJ0itBu2oPb4QL/
Hp5K0NutsyTqMpmj5qwre5TvVV3Q94JBpKqLjq1/uF9a19UwAWe4aR0rezNrQbDyszfvz0BOq64Y
INvzLLXmw+pRkXCubdGsjdmcoBip+jwx7LhLEzaEl46N6oTOoApYJwqVb4e+r+0/obFEBse6W9+b
UkWETUIrNxrfB4+yjOQxK45gKdnIB1b4VQL3RUXFrbJTW8QXJV9o6GF70FZnhVDtVuFTWlYIaOUJ
fQ7TgHX/LmWTa/Io/XgwuULY5wLsQODKulO49UpYAwXFL+cWfXMtVMZsBGtSAw60SABwAU9PYtZQ
lhNZDBmJq2NVZpkf31Q4kbI25RqbnpPJnHK4jNU4rQbu1RnloX7cNSoJtu7vpx+Vlg1RQ3MbklDD
mpqTV7itDkXw/IutKmX/A9ks3LdRkmCfn5qeInEZ8ltAyk3dODznqUU2FjmYSVffBkUDdP8q6T/I
c9qSg532zKveoZ8E/0KvrM/eSdTp3PRCJfDN/0Tmpeskqqjx+DQcREhBu39VdHkE98aPzFX/GoD4
MsRo90FaG3M/rTXTp6nT7pPS7i/Tz8ezPh+O48yEOxzPXpmw7TPTFtTu/qusK4L292xCO+eTQSMu
BUBU/eTI2iQr4J1nt5/Bc3EEuPUHGAhXsAiFfcJ0MnLkxDkC7drMzsor5BB8lVXhwr2fvDjdkkMd
46FLZclI3B5LYBDMRl3qGQ2+fdwjVAGWsaI2+4PxviRBZQ5cEKvvc3MQ5b6Xl8Z91CeHZbNyHTam
4T3+xeuAu5e4ILXUZlv/hWGPU0P2F6H7jRp44FlLR/VbgvOyJd5U2X/xhVj91FpPutK0ihfUO3UO
U1CkrzbZy4oiFoaST1Kvf7JLYuNN3/oPt+/xQZnCJBOkYXQn4K9TReBXOw6YkUJ3h4JfSR2pcY7+
Lnf+G5lEW1bC6GN9D9gsJM+gL26RZI+OU9r7aJXxOlL+5TvCOsi7OCbrB/1KQOt/ytwuM0J4GTqY
Rvx4AfNrcbc3o62wHFVWmYOOTHoet/LFZs9TTR0qqRZllCW5KRDSjz3fIhokxCMfewdJnoh5lYyp
H6FiXpkEtZK+smh//WbsAs8a+ZLYZfaAt8MHEYkcYDBC3aATYKfWTKNhYhT8R6jGEdhI3spAPTvZ
jyUbnFHRrLJWNhIBTPcfaFcpjrf8x2/22HpbaPNmiqLefl0rzhQnrW2gF4hKrBMZSQ8Oy0T/PwZR
sKo8OG7usVPv+qdsFNYI4mSO0Dv5IF5r1LG3zLP7f8YiHZppVpa6Dfx3z4dsosvlwvtkWkxmYq/z
K9jc7cHJyw/OOsBesa7aZ7/tvFM3xskEvUqd920GPe6fX+It+yi6NI5eJXCt1A6z2Mm40n0+5vVF
dA4JMoEsXQgsWzRvmqNKwSgZbrIodWq+iNTyF6gkEvQ0JOEaI+A4hxo9vZ21Lpu8kNP0HN9wUdOT
kgZRvhnFnaimI6xHtE0fCOU2kHR5DBY6ClJ1U6dGs+tV1OFnFN8UaULPiECkwXu1OxlW3Yunnthb
knbBspo/i4oCAbiRCvR2Nv53c4oCKPXYJYz/SokOxQnXj+xfus2wR3vZXVQYpfdmJxGcjtPwAsKC
NYGCnu0zyaWAb2jUA66b+iLdWMnD3dT6kmvcmxLSIxYRWLFbQbrEykprHcUXEOd2mtZXEhBUv/XQ
6cVV+yKbGcDEVUaB8LmY48UXky/7MqTteVUqh6pK3tooAgvjvueCiCs18jbK54S5uDLIqTNZTm4r
jtDNAWNJjMdQWZO9mjxcpJQg6w2LUZpOR7o5+SVRknzMR5V0yc6J8apBynjvsYKH/JftCrgKQX8R
v7NHh97/ucZ0EpNH8+n4CXELjJ8BJqa+k+a3RM8txPLfKIsgqq4z0F6lbZAfG2YBzbopYgIs5K8s
UygI6A0J2wZOUk+dYBI+70+KA7LsHPDPdDjOCsXVyC3/PLF2KkArVs/r2TtPTFsXmDyBD7MvI/Ic
Lh03nGZI9MH79+6neoeKJEEYxf1dM+NJRM5WFwAoE3iDqSMACqNUQjvgSwJYvUIBKZ19mCY0XuVP
zI2YH5qL60cBHlOxjLx+h0mOmWeoxhWsF/90TB/dM3oZbpHneC0raryMHBtvNaFW3Mw7YBcxL0DA
s4Vdt0iRbVAllZYVFn+FeyAkKRAYPf4LdUUFnVznufdXGo6o+OxjenS1WtcUIweC6Wxv+FnxLFpe
4A1sEJZ3dv0ZasyRoZNpViMEVotchP/D4m6Y2/wi2EO8f/DHrJMu2lE0zgMA7ZjsVcrIUi9nS8C8
OWpHJ7KwAeeH66gm7sTp3RMtYDVfK/zY6yuo71fJWvBDonEKvKuxey0mUHFndq8ALibNgtq9esST
6qfuTanrH8PfS2Q6UgvzPy+RCRGe1OnNnZZPOatDPxVytbZeDUxJwamyhF37V9aOnwDO2N5+xwXP
I1I74o1VuMe/xJN2pDVGDabLFi4HTxBOv5h6Vovac/ilCQvZTyrlCe841WEYJPAj1QG3QKF1EweF
8390+k0d1MY5wu8O820H+H1Z1IKgTA28fdPzAJfTQ9u0k9CqP6xNpDSuRT+AhAXjyGhuyHhfLlQ2
ad5JPKXBs875fWhMA6lDUHiFoQW621pGsJ2UfwUEzKkdTdkyAK2odObC5jxXOerN5o8L5psRisJ+
w7mzj/h+R8iHjBzZYo2dnGumO/QHv9YfH7sTYhYinYATbmHNMMyIRq6cLt+8aGrAUc5E4cT9ow6D
v/m7BabsiP9fVyBavtVHZXvu+Hq7cq4bqZdkIKCaAYVSAHMUmeLmfzWIZJNTW0n2SVbBjNcejMhg
99pUwHYjWKThoGK8OXpimsmZA0Fx1LSxNSi7iUxQTrlqcnv5ko60WKJd2O2lZt88CGKGBWqfMt3v
1oz1hHbYi4SmXRATqZj67JRmdW9PEYd1kvkU+vKuzrrBUYay5K/nGI7KdGGkWvjokTL4hK8DGSPY
8KSZsri41gg2QOmC0dpkucySzduvI7xQ2TGV97tBSFASKYLjUYBdHQ4iDqSe7z0n6lroR+H9LUr6
62EKOACvxKcW9s+e8uOn9iGzsJdmI2Jh+drizHjrgVuwn4pPbPOvQ6ZF1mITNSQCz7cPuPiLs74C
M+00EdZT9nd9FehMG9Mw/YrGtevZrbxC9xRsiKE0Vu/hQVx5JyYgLGY6G0Jz+/LOBqCWhEpO5zPT
GfXrHWRPrbuuHr5nCFsCB34wTE/EexUjAA+ZkLViaPxlRSOUzLT104PgLrXd+Fp0p58C5z3VBrlz
svcqWdBTvnmrKg7my9ybiJaG4E2r5GEau3oHz8j10MG1ZAbcU6hpapPOKEmnZFW9PDtyzvbbmVMV
FuT/xCQbKdeT1AfsZJeIhI1w9rSznr03/bC/tIYLylZR/77nHfUg6H+c6QRk87a9Epu0+5IZwiCA
nRAcwA5LGQg+P4YMiwsI0ngJBr84hHJfmMalppkzTrXdGDocv1c/kvCz+GTtH+HvuctP6KRoIJA0
l1VCT3PqUE3RqMtiI6CwFNpeKjo3vbDuYOYIGLoo+3eL8fKZBptaDzuKZJfaQDXBgUqfgNPdWJii
Tjzoz0gkVxIprldSXVPLAf3YoSzCNWrlRbBZRaxSdAS/azQkhM+SpUhWfAvW7ySg0DBdpXK2hP1F
Ie4icNDEcQB4HtL7L6FJF7wMJE7elso+X1CnGocuhCGLvzpUTThro+PSP9GHiHMDHEpwCEr57y8p
pPn/O/dSSkvCR1UNAeBz9xt1pCYqxSK8O+fdUJqlGnl8kWeVVAlv6BfQVR124ZaVCzY0I6aqMhnO
ufmUw3icrcAuF0/2xCE42uHpIpGdbEDcBqb+TZI++FMg0hGhmxU4V1MOqz/MoDYJF9tCiDN1s00j
ac2qXrH1mUvRdlXAEcWn0jD2OSMk3hF29kHEvTt4FrXTgoAts21WSoVJ15hnoTdIDqV8Z7myi4hQ
ADnKPkqKReesP6gXFklUGKPVDeJjBjJDGMBHkdToJPYPWo5BCT84FvjTsgcItn8PJpkOiIR8oXK3
WnqPHEV7dkYSSuktmPXJlmN/uDnhs++vE+4aX5F8VIpeIm0Rlu3umrgM/iZlanjylMzVUCVjHlaa
ZYH4EDTT8co8A5kWCsUbNUPi8uBO4kKDoQpf8Koh3d4KkrynlRmRLzYtz9hhEP2RtLzP3lRtJFSl
bPOQsq1LHriUB8BRKWrfpkN/OyB9/SuXarC1glO6rNr5XhBFSgtpjXn/ULHiKw6GDFSfUCErJWUI
mWow4aJC4YTTOI0ZuoKIhpjn5Sfx/JuOAt4l3/II0IHZwAOXRC+OPEATnVG9pOO3P7jLU2+GYe5I
0KU6p87AdlXPCxvqJlM9TBRjRDYMs/ssdMBPb1sbklKLID6OLtK8Q3vv9/5jC9DzEx/eV2+BKH05
E5t9EMWnsCFTLCJ2dgvZo2uedRR/1pn3aA2Uq0x9nRtLwysnRuc/S/kBaF/0vMLiVShSEWxmuWRp
dftZiP5iQuE3uit6RSprq+PmZZVEen4o6BU9yQJCWxLk3xK0SodkSRkwNdYikK6DlvuDysm1p3LF
tNAY7dGLRq9xKkU5U0CtO7qCD9qgTdaOXe0csF0nrtCoSskGCf5mDbpkwZALXjcWjzadUvKBmmsg
06hqdWPHgdXaMZNdvzo9+XKuTMhWFY9al9sbVAZy31mDE2DPGoWMlLSqStP8lD/SkoOWYu11ak9n
tfr+UYkUz33nC8dMf1iUONOlixkwFDI1FfmT3uDzQcFdqL9GKlfsERBbxNcFrrfKu2jd1OhO+QZ2
wQNjGTRALEZFEpepcfJXfBCLD8YA0sX4msOMvUfXXYPrE4DY6A/QR6jJihm+mgmoCd2xIh+X69Qt
Azzz9EKQd9t3TFxam/HLlWVtnmjuqe7xB1gSXsxDwB6LMFi0QzxZeyTeptIZw2Ch+XofTCALDUTs
SfX/Us+8rkNUSQpJFkJBzxL38ga625QTWprvdpFyydzDKLbbIWY6a7hg4ZWdqbxBqJ2hrL068rJV
90/3FHduse2F3hHwtpnMrD5YOHS8Ou1DsBG+9+vac3d0PLR3pG/CtivJqXAcJctt5yvqpkfbqnso
eyAWXPPjHTKmp02/0jutHbDvurJwBftV29/9akl4zaJ4mQvPeB7rpUFYhBz09kmVJayHG8xBqr7h
e4UYZwRJo8Wkdi1P/GFg3UACUqNMbaKU6harXG6E+tgY7G4LbQgBGWZiBkgZ6HH2gDZfz2cxgR7f
S0ZZOwuwvNzkrgfNkABsc0jBGtZHgEbemODqDpcDQYCwf4QUDUNZVTB8MhWWdxEMbRuhJ8dnq3Lj
0kdLYkSfVBk1JfsOo9jAAXxSY3qZb7FLRfnDtPoIRZykkZ1WK5T54Bj3WbLhTUkQ9Zn3b3Dqeya8
3m3EM9cbTMBngKds+8RXZFLpo0LC2xEKJxaHI/fsNgcsXf+YA3Urwz4Kyl58o+0pjgRJ7RjkPgFE
/TvExmAYFX/56nxP2G9so7NRGvzWORRJQn5OBa1MGXdFi/8GdWPRjtsEzho8pK38Y5/v1ZvexByj
NTE3cjmAe5psYbkq8c/cQiWIiuQKjNtxtw7FQvvp3mP31SwVxPmpoun6OohF7FMFo0VaEbplieE0
bZ1MI8HS+mfc5Uc/sDAPpTtTaZpPDD+pqwEiHtFTlsQm5dQwYkVcS1OdBEUkwWX/prMX/ITIDh8Q
maDBJKYI5wKo4jmRSIXrMatvtKftAKVMwX1sm7gZy9XYqgi0TNTLAJWH6AMVONpLEJP9fgs9izRu
qA07bL+UyzqIwd/7IlVYpq+kBnOsK+B4RBB5gwd/79a6B9OSXxqvmYj0N8DuBrTjuJT9vRdA4MwC
1SkPMqapk7LEz3PMtE9FPJzSSanSonmc3KYt11J6Ti/AkASdC+f0wzFKLnwq/yg9+ktkVib5W2aO
71gNsHdR5HtwGgILax+9YAepGJlOAr9vzMltiMi3mYjQUFs40Dpq/p2A5yoxhVMEltLq8Iswk/S7
4Ob9VsGaC5QbflDC3jnbW7Wwf4t97exFbFyev/x+rbYEruQR+eg6OJwCEwPLcIZw6x8QQ0Q9nnvp
WYl1A+BL8F3eaTElNJz7gK3VHD4jEd2VUdyKi0wWGmZd2vMi5DaKy4eEI/CoLarRfINZgNkXvgPA
wJHGAxZqeeGOOp3dxR/S4XNrhM8NVJ2hmfjGSgQISDNMAfwS0XIfmHGRKlOBNerPiWmSt93OAcpa
QTOPL/oBDm71FxpDmi3aaMcy564PT/YNoKAqi5bvZpDbJQJYvUNBE9AZNmacMBLllht4MxQK4Nhe
jvd/7ALVZIhz70BPwtpEgouyQ6VGJ8+7O/UmA22RtATTckPbOzmBXza7G7AZkCMkdLo6XOczxlFe
dtgQ5jvR/3GOyH6vGD20WRW4wn8Mnv9M7GV2G+2MD9qLZQvS5+yvwUSLKbXRgUNc3X6ajMRBUZkH
4yDTXyPLWN4/ZFVu/k4WO64wUU3wl4mrGcr13/4CiCl1tC2bMPavEnIQEyfYSo0hAWkokMsTZWrD
q0wbXQjNVwXOQtgQ9RCImsqGb3g0UQ4bVjLcseABjHxk2zMZCuCLvx4z+YKRx/ENhcwLtBahGwy0
nOXsvYBh+xrzC2CWseOSTWfECjoCpFI8JIwHIce3sFCCL8QluZk7PrqNniqbJgK/S0wKrGFspUcB
itmijWds8/GtjcwxQ+L7aIW+3VNowSNEc5VkpqncbCUu7fne/3RA6TTUtPf/unyjQO+aayi7x8VT
f1jSChy3Wmtp3/a+RnVqd5UztLK0fxCeGLLhEK5HNXrh5uo1gHalZ4gEzLFqVGx26A1lL3dH93CM
0bGNGayZcaA6xDz+oI44+cepu4bdhBjAjEKqi8880ORZnDrmTk3TvwiK+/ydqXSCHx7cNc+b4Hno
yGxhmfzOuOVwGeUa/5Xz5OmvoIylJJam/v4H6fbRXm3pY/SApXQy3dFCQYHW+uFB+pWkH7l9mlRs
4ggodLkNq0yCF+jfvTLA88DbloK0gKWts9IXcLJPyIRJLK9BfZ2GWWo4It30xwTYQYYuR2Ts1pT5
LWassrpU5JNrEXaHXW4IQ3ENlvkuw51EPd+llrClvPqM0UbgdBqKqPe93JV9DBCb+Nc7PIn63P99
oQaeMFhhi+0mr+n8FJbB8pSD+XD8Aooopunxcu3LUT6DBHFK6gwGEuiYM0R8T0ELXXUiddYH05XB
5QGAhLn30kz151waq1j87XIKxzoM2uxArX2EBeO4fljd1hoU36D4sw3KSb4uNjylGvSZVfMulJaQ
gYU6pnrY7Ar7RRcEFkt00ne+OzABpVKeXv8Ijti3xTLqa3dNMzToHIN2m3Pn57kEBOyqjxWYZWI/
N2us+pKuRcLTbO4AGSPN7lF0mVhFxf3C2SxEsSfNQLPH+8nCs6mg8kg8E4aKi68u9YFoOESEioyP
BoN5xDLlFCORC3jnOWU4zjtugpuRXUURKYg4+7RFMRVUXLo6YSLazBsj9rHez2svlp7XVPY9Opk9
99kyoDDROXsxbjpUfT3bhuusivni6Cvzek1XB95QlEvx4bqdL65OlqVNaVxSq+8604YG1VLs9jVh
Vb5GJpc87DssXw1S0bGUas0qpJGEde8Z5YHDwjkHbbVcTku/Hp0m0hsTAGCbLDvgsMut/QomGpVI
vBjq/ix2Wn6F9b0OZTedK5cF0Q3zZ+vyh+PPY1EEcNeZfkVyesQCIUK63ho5j371r7NkKetDfoLK
ghBtj/T0z0yUU719b+oAEWWcS6oIHkUuwSWwmIngpO4LzTuQxCl+Kujw7EELgVowb3M+52VTqwVL
UPsXThLH1Be7KRmPLVP3XfsygYi+JrnGXiLn+zGn8Y9phqQ/E5SRrSLGXO4Qi2otA3X067Xnnhow
nnh1jxwiXpgPzHMlV0sSmCq2CQDOyf/CxldgXm8RfraitF9qtBiL3OyXlzxr9H85AJUvF52WXAaV
zDdaOl6ZRMKzq3ovi+2nV+BPmpsGtUzfS8cGXOlKr8WkIQVJOZmNTEM1QH9mRKSTTA4z6gxb4SBe
WC00vjsZ/V/3TzkJtKFhSbExNb8nZNW2xt2W/OPysP93RNeg6PB0ZG7NJWnn/sEXdmfviwVq+FgU
yS3JY8o+ooDNcdyuBeRFUmuloPSKZPLlVv1pWAnqaTpKgqQylDREHpKmeJLNQOP5/eR4qVu4IYwC
5xtV2FAKxKa8nyFwBTOj5Dsx4WfMOycKThZWXZgsxZ6N8anMUoEvM4OrHJoN2IonvxBQcprAyyHX
LwkcmM5HNTIUZgof6IfTIsQ8f1/AiXT7n/Ew3kFrHYvEpNkvCu+45hfKEDaOknucMDEanrtDN2e0
JouQqLQ7eacPrM19803uBbZwYSf0onqsI/XLVTyCP01ouR+LQkiqxrWW0SvSqR9PvZpZp0oTVTo2
vNmuti1mbDKoTZHMm7hzrknD08UW5vtu8X781hOFYHjSGc7FrxyQbgWRrlX+VdOkUAA4Xg/HqTWd
2WBXDvfelPKOgpNGOZSHS+g5eRSfzbIsWXFr6/MOqwz1RqAVVAxUn8zF103A3h//xu3/rQ5rIbNj
IOpTl2+3YhEjLsQA3OZV4098CUskxXUX158hlFvVPF0+CC6Kffx/hsVDfNQdQ8V16jL6EySOHQw1
pos6lFL6mBTyKd3JNC6DsQ8u+81k7WWIw6d/0/aZxm7OJo8VNk8Y/O9GG6J5+kIP1qHRsynz83sd
jgl3wUJRiUD0roBBChI5+v3HzR36/80oJ7mNxSNas6Pr94CN2cFfQVj8Nv1yWPaFAk06qJxbGtX+
L32Ui15Cw7oBYGkGgUyzobbgFKmHvuSmXbdq6LBXurZSt6iKaU4DfnL+12KiCxyJywQGqCpkG+yU
3DuB5REX/9XZGPFSy7/P7eaZC8Vf/7ODLYRUEkdwOTKdGorfXtD2rYEfvVtWVGDeJn7sbXsFhOmV
VwZ9JjX6zo5ftQTCKA0xC1y9+0FzRghwzLfnthWzqIDls7Z3Su/oiRpEkE/lkUPGuyJvVW7+b6k9
YDMecCZEIpXizs2eW1uuOpfCqxZB+75CQtpni2zk6c74BWtH/daHxsCl294AY1s8KZmHvZXZqlaF
N98G/BvjeJs6P3rX6q++N1Mq4QAedTJ3zieMu5s0R7G4qEoggTdU811jes5pll52dsJskmNkBpUi
xVBsej04/e+cfr2tE4WFvhWwdSUpZQejdVokyGMMy6oPn8dmqPDtKXroWA6jNCmGHm2RgBrNrshZ
/NIkaesy0r7hlhOeA6idAsReN8KSAkyT4dtyJFsvLfV4973rspHD4kNmMpxPRb+H/H/s7KPuogt6
8EbiCRmzxejwvHTr3XvqpBvsUGVFlv6DSanU5gn+8Z5jh6/6xknBGCayBJ/iN37cz2bo9u62tf9f
TWdSd8fSdODBKgerW+G807GoKoPvOuZ8oKCgXjjkdwH0Ho+xhAH2sfXKMlhxc1CBonv7wGbyEly2
j2xmS0JL9E4DzlPA53p3Nv1IdhJVK8D3azNbg9Pxl6iFRLrj235/LO5eBcERhXf8z5wQS3TiRUYh
v9zIPp+Ox+Fts4uDk+6t4bSIQxdO/neaDEmskNEEP7KUTEQWE3Xue7PXrwr6fcDBvFf/kHQ9rSAg
wCDRlkaPQNV+WyvfPXYMj89BMaeu+0V/QgBf1JKSPVZwuvQdarPpi1u+x1pK1mMQmSx9unsV76pH
vD4TZPFKLsC9dxceBd3GfcgzI1+q0Z78iX9phXjT3IgqvvF04PX10e9PTp4gYqNVhlzQEgWq2DkJ
XtTPai8ABs9fH6kPCIoquFJ0CUBT2vdvF76MChuEjzShCR7n7QP9qQW9TjRf4U6Jtpz/Hmit8GCv
wg+E0I/Xt9mOiVk/WtciWX88NmJgJ83ojh9B4fkzOu2QioTxB2xkDA/EUA4MlR9Da4xuCqJ4FnWZ
7Ug3IviQ1MXXcqQ8Y0qIjpufet21zRzqQA5x96WfzhicBqMjpXQyfqZ/ZIs+8JjDpZyMFq4sIiiQ
dtxrCyiDuzScjAS9GdJ8nPXT0EPi6hNQ8YR6a9uRvDjZLpmEV5NiRJzXNUJbSrfLrfT1Ez075NiA
y7gB0dImuhHJX3sC0p/jReWwX1KnUuiaUsyTsd2W1Jjc9mo8iDecbJs4zAwGYCtf6RtbbnVPGIJS
jGxB/6oSRBPRJ59+J7e5xFwq/hAD1XmjsYcol6DW8CKJbWJ2INZ0ek2pIkFHlqBgPwTu6dy2vLkc
AyinJ2aJQ0eqXc7dKdBxMdGbGFZfWtAVYKJ73Nk0Hgx1wdqmpv4IDd+cRPtJV31xrXsacPqK9gpj
/aMjuPwbljttT7m8w0nwVz1ORHj0QuQfnxXkOtVTQGx6si+0kewdtPbzzLEqWZRa+WQ0xgzwO0SL
QUJmxn50sxTE043VN2J5n9cEGnEEvdwUhh1L66/5edKCOy9xu5C4EWD5M0v1xKwPeNP4acpaO798
06ZDVaLAVQHHsty9bVFWVZwkz26IJjnlrUR3MKcDyTcu7dDNfTqp7rP6scXTWQxkQA8LFi/5P0Qo
rn32nBHID8XYy9aalIB4Cur1Eh8HKwNn+Fg0ydwfmDmGdQKJ1ftQDMzLSeAw2K3V1xnoasp3xD9E
F07eJ/VyjdIiCwGvEd55Fd2hTdANIKMX5NKl7dPiSiIjHBR2eciqP8UbXf1o57PIudt0if5TNLad
Y9Jg1MbUkgapB37q87LsUqWbwq4dDo0rmA+bppviZx1wjgQn3uhcdjJYc2zqBOeDKYHDmNfKNwQG
Zfg6oqCTrnLLxqrdoYxwq1fWvqLZM+0we/GeBXGxuTiGY/qpmhnOgu2HNtFNwV397mH/yFnNxI/P
Hx82UGPY8AT3asJoXuE+GOha9hOaxXroMo0JBWJMuwbSyex0kuq2sI95xwia73uXtLddAuxry2iX
H3MU9AhQ2vGRVYjRoTDDYtbN+ZOaQWYaB6wnzE7UnOE1JNaXJnsd9/8OH7UzPWPPEiLsauInzBZX
WaMpyEigsTscYi3R5Xi5pudzjPTWGKTFveUoiZosNBGL7mOpCtMDx8H8f8shmtjp/GGwSqAlomtx
za9IALzd4I7vH+SqWU5ELoVnRRskN8FVyqE5O+qsBYS/KE+R4VUyuZDVrl6V0iqKPoGTP0kanUse
lEg/rB1W+zqsXfXjvjxFYa7aPlgRmQCSvBXGNg+TbH5m4+/kCDJmovWP+4lSF0Kp/PeFkcyC8PSJ
yGyeCV0QIXfA3tTMBac5t/6lF+ZQ4UVjqRD3FXIOlaXn+FLkkxEF0u72IGUMJm3qmNFm5PiX0zeT
KTSGd4IqvLfjVPsEx/svj3Nl8mIRz8L8ramBlfuO2PC0U5nppgD+Z0LE+VXXkWYE8qSKlNck1M9t
XK3zQoOBpY3CCWQ89oijFkOk+3jLyord3HZP3bQfd/hxSu56zQj93gjv+3YNjL4xtssIQtEd4YMq
38WOAMp/yhTExdXFNPqHMxTTrhdrxGby9Ygpxu+hQyR6cYAajoibx4juM6CxmZUGnr5JWs2VthJt
JIDdZi/sha2MSzdUg6wc8whj7gyPQBmzz+OHXzCSTlm8IUUA5Mp+Q+/4Pm0TYIHsljC2S4WbhfVv
/Xqt//otemX9OjTbG0AyoybHKMzBwsxmojheJCrxJ8eRMLdekl05puJSn69PkZ8fAIRGz1sNEkTp
tHN5Hdps/xA7QviTSR7OyLrjuMt0fePZed8zKJeLfQvJwom/fq+P/4RCVOlN8/x6rxNnvLooW8wp
Xky0W9DxatYlWciFLSwwPsLTmlpmGadck5cQ24I97PMhc7rQpXyYSZISg/ktvaMqjAdrZwz4T9no
+afpkChpdothIX6hQB3MrQ/SFmm1EDj7Pc/+OA/kiWyPRI9o8IXaMjy2xtdLpWOJaquyc3FYFlwI
CGEL7lHIMVPT0FNPTJCadt6yKn/NFY08kPi/7TGUgRdwQ2GDphso0yx0wYW+UD3uVD+UTqMrQA0m
WuDP+8xHdIkZl7Msrk+oQtBJrbndFK/iVP/cxPaUE+1OlE7rKu5PaKzdQ/4HFIMAZpyu0PjhW31/
svd4Cmztk1049xFmuNAegssGmKeN6aX7saN1oe7fkVFZ7wuoUfQ1FxjeQKoLnZm4qS4nwPNjyKAk
j2Jf6hN6w26fXdg88enxY9KwkbuFTUwpmf+mScWmwAeI2XnGNdV6xnbXY+wyCzh1i0XNFLFzjhHW
fI+P1sfiO+akBC3zjFXEPJDqYTiSmZQtgMHymCwhc0C/IEhrl+CNAf/sM6RmgretPhQXY6guZcg6
It81aLzZT9NzRJHi8GA1FsZt9+cvtMPHA6UJW6MScHzwdJ/n+qiMb7iAz3OGhGUjSAgijJYyfuWM
6vga4U7zspt/pgU8AS5MfTyNpn2/Xv4N3HnsUvLnpJ5Ao0aoBgFNnbP4jeZb29DGquF01Levc/vt
GG0ZrTM22KxsryuBMy3bmMkdGtNGnU06nv5qKyNTQsVv9MFjp/tEYdTEVRclQjUeklAp7vnBYHW6
0UNUGy041HcglBGu4qa70dCgg0JQyPwbGnNzEjFBKS7abAIvBmQNdYQLVVdzv8CRgohCLxn18l1W
oDpnahsnC0xLcRpxGVbn4AOzYXvsB3fi8k8j/guhjEel96N5S7xVrsDnIrZFaHwToxyGK0E/PHg6
dF2zWQjfo+9WpIFsE5cOTbBvbioZqjTUvzEgdP3fTHU7wZDYQSFLU3JgYnCkiUPvvAVJU4F9AQQ3
zT2blJfLhhyxevADmdJVMWmpndeBsc11/pbYEjyGQTbUb6iztMu632Ta1B9BpVJzQeGmnBlrLmJP
8KyG6jfqSzNW3ibqtr/LPVV46NgwOkr4UYaz+GorRVimOagZ9IBlgR5bMhDgccVJrmOwle+c7zCO
a8qxJQhWsgVDeLIDMzUZMG4lN+ggd20hwLle4GkZH+ON2Hoc2zO/2ADwNkIYxmBkpKFReayfa29a
bI64MY8WKPLzcS5gussWaubVKaEAIMzh2oC05yjf/ZNAsfveJiNbHivKnS8DISGwaeTgFdJqruX0
7BsAJ4vXwh6AcxYK3hk06Gy5sN2VYH5NPP4Bd7tBy+xeRjX3fmnsyHBayf0i3SU3GxQM52H6pzP2
y8TdiX23xfJpQDKspUM7KbE+XXqGeNWTOOC5n9yjSyF1CMN17eD6+cJ3deEPJlQfzO+mZyGaR8Py
/N0nvTDJ25vrEZTUiyggvFby1CnNG6rU7UTbn0+5L3LyhzhIVCJdJmF4lvofFfk7GSHcvWJxKuW1
GlxFbfa8dKvXzGPK9UREwWpvEl4gnUAecjXvv53DOcLlo4k0lROJkIpT8g+RCtczDHAeaBO6Iy3E
sKEyOuW7qUbz7bFmZ7qBsXeG3YgfvuRHrQkp1y8D1N9ItAKtjtYBgQ5Uuz94DCiWPdZqhNkh3tm2
Fqq58HhH4mURWMFd030cSp7rFCvp4iq17GjJie29aRUVPiAwcYGj/WXdR6bKvxCNB5CRAId5iJuu
Vp+SQl3CmU2HtFzUkQU881HOgXG3x25Id9TH9cYf8nlmE992Vw0pi0fxhOr+5ykgvOazixdolI6p
EUJrzuUevJ3zgeahAtzCE3nFiIZViff6YoVAPuR5D6NZhDaJpYn8d8bYQBs/c8LNwVnnZJzVuVn7
TiIWCXypU/no8cdIsEfnBEvjgxSwKhP0rNbc7Hqt+DqTuuw/Bni0aktdJv99MO3o7vps//b9plnN
6yCyEDcExBDoPnyNU/oCePmkIE88E5DmQFiQZsFKGPGLBl5RYGgp8T+5je6IHz1sL6ci4U3H3SSI
Ub3x6cVkBElB1iA7PUWh/tg4RnG3BgIRfPHEn6hyByWbglfltTszEWzhNGQ1kTRE+w5IdonaYyyc
yPjuU32aYdaUwu6mRP/q8s//CEq97PAicu0qd9oRmFwaZMqukJE+XtnAjtOOTkkb142MTd1H+4+c
jkydtApZ2n6mgmywq5QWdpsoDmKUO+8ixPJ7+D2N3RHnAshVXXJqwM+TYM+4m97uRyskAGY2GebO
XLuUzAKbH3y+vUq2E67YYk+YMVOKmlONPYP5c/bTNJtycVTTkkLrO/PAHudRkeJGHBMwWG0cy9da
oZzXAj1FQU8aBHkwoEZOxh3G+9GlcmVSllX9ITkCJYunSRGtM5DakM31OVTh08+mLkNq26O10fpr
GA42P+q8lboCKS0e6SHivjL+ffeiz1ckMq3NRN5+HKpo8vX7x+1kc9lWL3Qqs6n+XfThdMsp8b/5
Vkg/4kWAINUEJR8fdGbQGFCU/GWeDZKzYKujmpShKMDUo42YBwhKLkkDCpbdWV3Wp4z5pJiJNsiG
5Km+e5fJxvx8+4/G7gqqs/1VFuy7Eb0/8ZLjxc1anqq1Abud6DM1eo/t2pbqKCd1na7q4DaXprs/
KeppKojUPBcLEbEZFKSKNB3bcVdl0ui7mBG065EBeUhUZZWjE/Xmva2HPSoQVwCzrDZ3oicUDrkY
t/j8c1QERVn9+SHLL/8RayvsmqUjppzCyYrylx2Secg5Hf+f9306Z8UjQtyThYMxOjqRmZEpfUzy
Jtc8noQEvskX1Uc8t7Ql7IbnzTfcpJxYM+NZj/+5MP4ntJXDdyDJuhZv9sZnrxLsJwS0USwEFT2M
D3coNFCmq86pJa0/ncs3zExpyLGpsDcNphjFZ4UVP68G/BYQJk/Xs/xCk3Rwoqe9hXjfKUB1yMVU
HsedT/PWJPBT9UYUGlvsjAwm8Z7FyB8lsS2teqkFR6pBHCS2jTctyBw5hT+FP87+kzth+j8tSOId
738P2tDHjolSogq9aEqtSpIIPy/37t4PkmW1ZKp6aMDACYCIX0m6wpAm8iv8wu64zXCYgiwxPrUS
rLDvxL7AkiMq8HjS1NyIWNGvTD+3bLlQ8pXWJOseTAIdXFY1NR/lUUc6pCidp97PXZ3RsSogOwqS
dPuXRCha9nerPJMWUDNGYWnRWf+qL0mg5wmgZlKtbqsumHYafohAcj/dO3mXMW1VNmOocCxxqT+l
h3FHtTwDnC2rr49P95d/YwDLB3BaZ5DNA87T9+Q2CqOt747xw49xQgvKf5dMcteU4ko0ZAME8rJn
zNtFhTkhaowFkqzagVGKZaWod7Vwg0c8x+8WtQg1CjhiD+ij0/YAYiKHfHxkkLTojqmIJ2FiUXpY
4Fml8YgGQH5/7Jw6lYkrHm/MBSM5nP2T6EWNyu3i3o1xsEES1ew2EAvEu4cbSDZjx7XclCge67vp
GU58aXYvnTPQC7gN2i0hD3+6ssmn9QBw9EeRA0vQyWy19LYKbre1ErZKilyiqDfdkpkeqQ7YJahK
7SK4gh/j+iSauU84X6n76H1wQWnVa2PgIf47oJavFt1hTMqacVw+tMvAtiSJPCyZJz82lfk+P1AK
kIzuyNmMYRmnp+iPBx9mfveP5jc6IA7L5sWjAzp76q+MmcxaQr9euE/i/p2vFwSsQxiqhgt96rmu
dLxQx0zUk9cWwgJ/UrJGbywb1jdIMSLrcLdd45SgGRIEcdYJiATdW33glqJDmUjToSR7kDZCu7aE
yc0pCo+gAZTotsabsODlDotnTjBh5Kt6FzOCKNwlaxrYp+hS8zxJEtr8q1GbDEgkMmwYv93KUQVK
q2IDw5mmHx9q4++hna+Gnuw3K1YEakvAEdCjEaM1/vFS8ilE0BnoPRYgY3uSi6A41QzhwLsnvMFK
BOukcnsVedgk0esi2hHdMJIErdxA5evg9/+ArcnG6+6hJeAWfh4fGQ1ruDdB4rnCxQ3/yDDYHZLe
BmEwxzt/8kFr+ipVlp+NWeW8QS/0ONzdBVfqb76Eyst8EcV8onVM9azPSd71N/frZKaljnQDD484
EP7aRyZHldKhQ4SNMGcYBJH4lO0fDOxchB4mz5aIKHELiaMXe6oNnMCtGQ77cjnT6iyJWl4mOu2s
+gOeWXuyJMGlzUjUD7Z04kEjJxLsNvBK82+ygM7kYnBrDU+8SZEAynLZLbpIqVVH9EHdgNcSyybz
2EiYvhf00zNPVVhMEeT9c1egXCtVX8rDx8jev11uo4ulm5kVW2pib32T1kL8BRCRL7gdBtehk8W6
bHihQQnsviR5UdPUgLD0wDO0mF2oIsD7JTJu2DG8is3QUvRXbj8xQ+i5IZYuuzhLHCKt85fyFz4C
b99QiqBhqIgRk9jvPhPbTAsJP44WBeP4UsjGNoRa0y1Tcs0/rqf83xIXN0ZP2Xeg/26a/AnR/FzT
LyiPTqVFrOc0fCqFVpFDLKbftQG7eA44d8DgyOX4/nMJ/857hJbd3v73C7aD/Nhku+N4VRKVjKC6
/exB6nyZSmHv3ABs+h6o000RW9D/+G5JcCW8UlHviP37iPfXD35ZjH1P+j5de5LDakv9Hefj4UYi
+65IDziQSFPQArn0DHeEVBoeZlE4H2b/uqIty4V5GZK9LExPzRMgVNuzRJgQ78WusmhXFXW0fuFv
oz/Csh2RRnd4aR8xqA5kQmAOZbFBRTXB0dG5ii5oA989iFbuGQOcZChtx/nWr93yk5Rncdrg3QYc
1RSmWyGVFeHFeHfgih8QNdS+8NGZP3mg3rHjanZUnAg/R6Vh9DExlvNytVze0eT2SHp/VPj/PsHq
i1IWRQdbG0hfb55AgKERKr15ezl8+y5D0kYsGhUdNbU0HT1qoDGRbxuKw1F1/t1irEMog9HqldnI
DRjeGSpGF3ID0nYwhfF+tApXaYzpm5t2IxYDMFuVD235YPk24pj5QHaC+V5KrFF8MbFfQTAVjv5K
mZ75L2GyLkQzx5DNDqcbvkP3xSTp3TGeAqMYdiMR76PlejZ7sKEkGvi5SQoKYCTVLbIvYaMcjK48
wQ2eHIg4Y3wnlCGMvUjr4d+QIcpYnR1Q5PzrHRYNBKUwmHhXsvKmVKELsK2rj9CXUIjpumKZ1Ffo
oMWxIeBc+qtC9gf6N9FDJ4oitG7x5EoILcLI/Y6VqxJ08hGWIwlN8KtoLhg1Q6NeZXOzwmcH6q5F
G/oW+FoqkNWRodtiHmQinSDsysyxpBADfFuubSjtrIYKjsHFYEoTgid4tshXqML2YLQzR4YPyHTS
8f/5diExYbpv+lyvG0sWRVg3em5q0s0vsoaH8L7KNa6Zs27avWTG7vDeQsit3Aha9DPVW5ys0c29
iZ9qP/wPNenPDIAaeyCdbGyna/8Zbr3MgYDwInXAIkA5w8K1wsM170K8s4z6gMq6IhHUwk6b1Qqn
qrH5jMGj4nggyq7wPoW4D1zqOYT9ujqH+PMFyyIX7SQwLd0YnPfavy6WCUXQ1RvI0DNKvj8dF/hg
3gi+SGbHxsSxdAc6wqKfz2jH9y5N0rt8PBuacFgeupxVqshfY56njrCM8WDAB/ERX692gLFOoIyw
BsRLmypr3oVXRRbaA1VIH5/TN5+jP/ZEIHZYYX0papRlSxgladgcuvc9Gqby0E4hMGVMvW0uOZZr
Anm3sUmb5ljazOjon8BK/k4NK+qCcw35Pw9ZEfzVxdwdoWSWCNzoGsmXI9exMV+lTbpA9xUMo3eG
94vrv7dcD1htVe5AjaXG2nfgqECJO97arndyjcvw8DI1MLf9jZvfbz9YVx8fYwxF6cfVIT3aTt9p
73EjHi15GTzD64N5Gg0czVd6raYFd+QaNLpDLPsVOQR8fPBGJK0L3NLYZaJEKTRyIu76oaO9MXU5
84tkMvqGgcOAdsFZztw1XQo0lPp0fe7vhNvW5XtwC+odVGFPgGHofvAPELSJhBfAJb2v52o5cjag
a4DxTbMhxWV8oH1pGSOArTDFTlkY/ZMMybh8sO7vqJSDrvIQRoiIexDPbp84KxVrLIaMqUxHXy/b
H4fdBcE2plZYXykRx7ZYeZEeRPaJXe1ZjYCOyojQu5o/qgaFIGAFIIBsWxQ9qxg0EQkPo+OvUU1o
MiAdZo+Y88l4LHQc3OiDjodITPLW7W8Nr+I9MRwZaTJ4S0W6jkh1Kvwxf+owzjRYEOkYyjOf7orw
XVRMUTyPJYsD8f5cheRP8aB7eaEH4gGIh5mF5gFZyKJA6gFjG/7N34kRrHoRIdKld8eu19291DMi
O0PQ+C4DJCuN3KSTes87VEbiTod3xz1BgpiCpNcfjPzWWqP99rIvGFkrWiwGJlC+mmT0voy5G1Ft
lLZC707hbO3PKSp7htsLiGlGDET+F+Jc+U3+V/Mn8qQxAU2gfnz3gKbSn26PA9lPJebkBolETTjs
iVz5KXEh1Of6uIDzbpswvCaOsliC1PYFXy/x9lgzjTikbikDayGVS079oNFCvDcOEsTqkBA2DaWH
oQbN/NpIXQd6mNrFb2xG/VpiaUfnBi42qHRdz37KjnkN3J3chGGAK+mNQKhQB5vtKHKIhpWUn19D
ZJKxXK5duL1tz2lPMPMnlvT54jELlpAS4i+gpVF/s8X9ZAmMripG6c8XoHRGmXzrEY76qrUSeAAM
n2EzcX4MHVrB5YXVEjQXkzbvAzrMvVJ23H6zlJ/gTZGUcbjGg1CVGkuLzTZfWrXO6s2pGtfkh7oR
W+LB9kgzzekqZyfJUqTcZPujqMu8ZSWfe34yxrBMigLsUSmzODYyijeRKOLhENV8YH/AWAm51e3m
kULxCQ5bKm4xEDhEHcYIONCT4FiebZ4f+tNge1WHuOzA+o/O92bIGofo4PiosLaw1u+hz/6yHg8L
quhc0cjteJSFpTRCa8tkW+dTnlPWIdkJi/+4Oy/RV4jbhcSBK/vF7rbrIbP9QTww+GeFtnXMtTgx
Zunt6MRxSg1WoPtWwSmzgGFE6XuAUMoAUMxwpz5ryIi7rOeyqni+3+jY37V6w8w3dxiQf4CUF6sy
foZcl5ZsLr80wzhgWTxEdAG9I7E+OgJdihSsAjplJloE/QYeVrWVOJVimLbrYKSXpQamvah5Q7Ic
1SPKUcm9lGZmUmf87lWqcAOjutXgYZ80AlYRNQGfGrb9rtXx6e+G4VR5z8Vz3ipDRp8DFEZ1w39C
yQH45gNT6N0nHJnWwuHN62hKlW2OdQjuazBEDgmnXPIFvbLGEvouES5ROWnCPcNDGlhVTSSN9ycO
bCYK9ETxbfQwyhiIU0zz/dRO1x3cKX56KnGchN607+Oo96VtMA+gG5UM2ylKKOh4Y5DBvPezyC8K
VGtAJBb9rvbDO+oy7TRzoNi4M6CQ72QsVSvWTIhUKCG8type1b3Ou5/2kUanRqHy9JAsGBIm0Ua5
PdkYcKZpVWuzkPU3auNXvDhNyjSWhtlUCNWveE2giq1ADxvxYGBq4xMoj12o1H/ayl/t4tkID2HG
lqLh0kvefPJZNk+BzPstyf9zPNJpecoGU9FztgpAWIbT1RgOxoBiPnTljpnrHu3KMVfkbGwPdxV0
I1ocBUWX705I0CZDCfcHumVHgGLHMo+L2njV3uJCjRu1tyMKTjDvw1souN8hG1VmszLiu7tKcSas
QcqrcC4m/VL/WaodVbTQ3xIwt8AFDwIq00VTvcN7a0qWXNwr1u0YYgUxXBvKKkI3k0hH4gtN+6Ou
t4Mx5N7zLMeL2x1zAo1AnSgkkeSE6JkKn1WAjMwHoitqYpy15mw213Qe0pe3rrN4t/CxvHiKaC4P
ThG5I6gn+muLXGIktgrdKH3tjrGJi5jLKJQCqAmQXiBIE/lPnEGC6Ft7cz49Z3csBSvYVyX1E3r7
MWS+r/r9NPs4vgBKUZ2AggbQN60X35wKv3ouzjID6b/GR71BW/HVDs3aVYKxfZgTQhmQAt/b84u5
K+qWjCvkqdH6heqtuoAmKs/RJSDNXM9U0soxhhRMJzeZXvBbYL9FaY6eetiG5YghkjPa5jbT0sZQ
OFb7ZGNjAYl8FdPkteoIHx4gG7uO4Kw8EbF/hgBELjlTH0s4oiJehzF6kXG7CNyEbGXM6zqWrUuP
NuBOv4DZS5mYxdp76dUYVqYpYcQB8BR58nDlzFBrLyPXEjgqLHOlJTU7GDljuwsV9cTxV0UIp+yi
x9wYQXe7iAt+J6Fr3qP8Irznxr1QoLulOFpr6gbd//Ji/oskZFt7wn3iTqzaoHfi6sAxVaLIcJqR
GCHYlf4tn6c4AqMhTXCRgQ9CzjhfLN6sjwcTqGKK0MD1AP2KzS/MHUOt40XIfnMTz/luM3B2ku2K
UtFrVdVXMr0wwZJkfia0uT2ECmwtVHZPSpvuCCc0lZky4kdUfsj1/YoVOwXbFg4/RHNIlSMcJ2TS
NBY30Symd1kpcG4+4Crk25pMxHLJFPFaiGr8rSB52ldMoS0QHFx4hkV/sHLG7PIzVJphFr9tRCx4
3MLeSjnc1h0PVUw5POM0Bs+kmBFoKMAy3kLexJKMHEvKKcZ4Dj2P2uFmx4zqrU4u73WYj9snaw9k
mFNajc2usNs2a4B0M33dpr8SbpKU7apMPx3HUtZT9oCPVJZ4DRGvq4/Hrz7v1mj5/L7QCF1kvq5x
hFv3sJpcJXpYXy0SDVravzpJuG8H0KdDTTvRAEAd2e/eQarInLzGLtxWJmxb3Nzy9F1BkjeON42t
KAyzmrh/Dw3XHi5dRHzdwvZqhKrgcoaVraCuxmV1vIcFSN/5H1jneM4m/W3pnlh1fLSX0oOaX+gK
cq3KJd5g646y9bJux3vYNaCiklF2zGtGy5bsFTl41IYli1+ejRHfpTP9EaN0AEl23OGUucs71tz2
pfcrhYtly/rLUnanYoJw7xBbmXLnYZueZASqN4SkCopVEhwtez/E2Crz/rK5sSg017GDnTn0OufB
XEQr20ZtSN0TZDKoyY2ArHwXItCQufZy/VenrMS0DxhyjGgUCghx9eGYrSftSamzX6DNbFLv9MbF
usIn6euNW6wRuYxHmaTdADJ4lPEgrZxnH3+pztL3axnxf8H/qJAtotBWbmZnH1xQ14OOJxCFl0Ms
QGYqidN77ZZLxy0eRTPpDZcoRJPzpwhmDPNdrAX32cZqq8AU60ipyBTuXsFZEi3QnVjdHDu1zoeY
1HYGgKT3MUpaTZlBaVgmKAacdlKHiZAmbZ54EcWrUKCwWDRLjv4IJEVB7YcNl27EuEb2mkyxGOMD
m5o34Y9KOM1GeymGapp2vCGl7UcUCaWv4zUeZioucfQx2/JgJE8i+gJx6wyevKKQXfuwcaHZ1gzq
Cx9+qBT370Et9YabYQelfullklTCFEpT5RKkgchP+wJGqabedLKbOonPAH/NjUVqelrnUq5vGi8c
J1xsms3XYuT3/5fzs6JTVnjpS793HKWAdsRzTm7aOH6RClYkuoT6c6wPkpVnBvrbKSvWUKJlgbjY
w/AaJvzm5xoxR/ZFfsipSmccrIOO7vI0gxOt/v5GD6mfB96L/2HtRlGBFgiAioxueFLbU4WcN1eV
cj5War6GihMwRANXszJMPxnqsmCLDG5Rn7RupNW+wlaxsUjzyOiLaZZMOMMS+k0djtbhmR4BTN82
NrAdruGBaAGE7viCzYgBeBZI2V/oaNjq83G904rQtHRtZcSQtBeYPmz2tpjnUsEZjrK+7dLPUeaC
KGtEELPW8JKpb2FKCPJ5PvQo16djFaDckK26oZ+A0nINmjuOcRcJjokvCuq8qrZySgQvlyVZ3HCI
98JFqQQC4vFNBqr34PlJiQcdgS/sR1dUF4dvZyoRN/zVwEcO492IShJQ1fWs9GeZu4iWJwJpOreR
/ei6e9CUlBpPQcjesfCFx3U+sqNauQw8GjW1tpD0gHAlLmncG2Y3FJ1Ng6sNI8cSW04qGCYdX20o
fQq3i31VRGXtYpQDJSgTHYsxNNy+h1raqMWq7tMboBR8oUbkKJHyfRUycb883sJc7rcUKzLreCNc
D7siWZn8ILC3ZssCNvB3go+Ry17ikdRLNF4eoBoAIh4PtdbLEHH/zB688EZ9gYmbAa5ohIr9P/2u
GpEeTmstkmS68Hs8veclo9mVhF6IzelvGqj/kAXu2F0e8id1DJEq7BJpM16IZALbC0Gc5QLSWjJ8
eejghOAroLNGYz6wyn3r+gOQotmZfMGVjLpvxouLsH8CdhN/BCBIaopeIrGk4hXB8SrKzuujYt05
LyHxcn4ErIUAoQ54Kgwg62JWouq0plYtFzY8SYKMTuuAwoxrQCmHP57FYwOrSfeUe47ArG5dSXpW
oe5SxafWwJfendzrMJGLzdUEfRTF50f5L3o9RJcJcABC/CWtSwQ0PaqTm0wDS51uivEKQE3jYrRu
t5uuNgGsV9Bkr4X/20DCuPQgbXQG4B8RV5qlrbSe9nhuPCuREBnEYNGnTU4cxZLB3n59CuCdQC4T
utoG1wC3CQ662V9R55YnxfgYn64Ymk9EYa8GIfDlc8eiAIrM12usgl6dsS7Tc1CUP/fly/RY4uRM
23bJuMvkfowv+2j8eCfh/UhKaA3H+rhziNoFNcz9Vx7RlcIG79gMbMcoNmoyvg5jU8kHvjVUpbuA
oU88Qk+UKRyQrO+HeY2em0PV99INJMaQGFhmvQ7q33iPg73bK9ODbtxuBqsw8oTDes/hj+1zCpb5
Hav/Xa3TO2TsTxA+jmuK8GMea6qaOsDJgLYu29Ko6If6hgk2162mc0nv9hJkRwfv8Dz8rkQX2bU9
aJkv09jO0qXFRQPKNUbCsIiY3Ed3cO+mi4Sh407hQCF+CES8b0I+6+mqFV5HphB1T7ktXytuvtR+
MwbXVC+V+baiLh+Dbd0GymdCYVe6MWr2cbRpXbu0WgH8B5F7oFHMClBijZGMSuDUEIPDmbK2xjuK
jjHp50J5BWUJa7ivNFZhLqeIbJsdG67O8a9RyHmiaNpmlmsCDzA0in+Xvx2CQfs+HLr+ZT6ClZkQ
FNLjVlXmAIQxNHY8//84ZkfOq0sX5EJ+h/23b0HCLMFztmYZFSfEpbp1nAH0k8rgBY3fB+I4X5t7
JqUbHUULwUrSCYNdbN/V7apy+JVqHAYp81Bngzd5h3GgkZlCOdZg2UJaWxnwXsZpWz3ivv82Z2g7
xVFgSs9/22J5MB48etyEwc2LwVqPO7rDyOQAhNURYhW+KqAxfRMWP/FnRUrd9SCspI2uTYRwm+Il
si564mzs4fSG+qYVDp+Jp5XfO7RNWvU3r9zrM5Jq4gyUh/FWMeMe0OQkcsvFLXwiUdSFIUjFBtNr
H/A+avSKbdbFyGZns4kr6RoJtXX+WEeWadOX0d6/aoP8quer0CC4N9R7bR43UJWCkSzimGU4XPHZ
lqrUteyMH2CbcGn/zoiU9F93te4SwbcQae7ND7ecqGvPi3HHbRwW0RFfLarCEM3b7N+w9gKIKDIA
MKhhZK52OSGVlWabfTEWr9H5w4ZoU8aOpPlSoW76mmsx2PN8XyYJ3rARPxdBlnp4cEIxZQj7Av/E
e3ic+Cj6b0F9GunWEiqkzsJV1ubM9dhSoJaiZanJ+FG6lzEQrJy4eRcZzsvfm8FVH7bgU5bUkzNB
COYokS4L51FxGkjVV10HtqIyjZ9flBFeax8yg+k4dCwKedrTXDSiQ4xyfV6k3QSP3rzW2gsYLpoI
kwlxF0iEHEPQgBYAky00iEjHNvcb7yZCXvNfI5cwIQIDg9Qv009Sc6W5KZXG45xgC72ubXSMJf0C
GtXqj/VcYzjHmTucZXSX67nbB5qwTE7hBxFpv039zHq4S0vkRDp6Gi5IlgAw5sqG27SXO+Wvhbnv
Ytdr+oMiaqGbMgxPftfifnPbYir4veXztHZ8rHAXYf4riHsmhDmhbDvEoguO5PwO4AaUSej03rl1
dgZtP1t8YKzItes8YJtWdC2JiIC2dAD1RjVsGNulBAoX2MNftTRW+xXtzlNbAw6iSmU4LO+7m3KX
XOhtM1Z0rZzm7czvZviaazINaqMExSDngQVVzTajcSz4pECE5Nrs6WOSYSJJm9jc1cet3YRP3sXk
r4qdPGXprdgm7d/eq7o5Lt5zwTibRWsm5qhY/br2NmbOaDP79oS2Aezwl2SzmthsDvqt5Uh8uxUi
89+VwQjFd/y+i0VZfMOP/yhXQMPj2MHVC+VaZJ/+msvsUseUfb7rwmMqo3Y/IA91IHs5/NtRQEGy
+1gUXlXKXqLTcOSppLF/XpuLrSzXKqbaLQANrZo7WpuP1AC2UMQnvZW8AJ0sizDdfwZ/GbVsZHYJ
n8z8+HSpuh4u/U8fJtF0c2jyLwvzFpR4HFzR5jACEtn3Ag5oPfcarnWr/gDJCubWW7ln4gXEC3Br
wiGurWXHC2RGX/IUPupjaPxTcDePFwEKytOWpmocYK+pUYam/UPOh11DYTJDZJccFnGxvsU9Ot4h
dAIV1EkEi/YlRfXYXLy7UtxS6FsbeKi6RWjXJdeRB70B5Xa58uKkUVD3+WBa6OeJ9EAlAEzrAHyE
m0j0klCE7g2HTEts1b+rnZRsi0UKcM2lhl/ZeegfDGX1gPg/KUaVu7JIGx5u5zbTHNYtFNnAI0Gd
iFIwCjyx5kOwe8mtGv4xf9ow6qfh10qtu5g2toWIREGn0uzxMt9gZXZuWwQYezc5jo072e6y3afj
a8YVJFT9trAUV9xe8OOmMUDYOIz+NZCRpu6KB8dLVLX1cmpJesQMP8TFRv0kFBu0x2W1AAmK939v
gJT7UDNo35k61BeO6i7N8sh9oHfTJO/TrN43UMPw96bwrlyREqBwgxyeXu66DfYlJzqk53J6y2fK
UewKYdywo0xrXBRAh6kclUtYGNADKjf6KhdcwRPp+t6uXjmP8oFTLguIekYs+bl86Ir+IuduVCsc
MLnPeBC8djf6Pu1rpw9y7TIl45cEnq37VklfjNLDIYFVAL6qfTA5Ccv8qEG/zPKIWwCVlRSmWWUx
lNzAZjkNG82OOTs2hIYbv7+9BR8K3DG8qWUoIde1vf5Wfj8Fy3UawOUz1cjDfCawekzR5vPq5eja
g2deSPj6niuoxFq0bR0eF03dXMBpJIBf5LfKdZlCprfRampV8WAm9lMUzCsQ9GAT8J8vbiQPL4Zv
II5X864kFVbUAl9xA81i2tf5sz6c5q95MxFzTH3R29D5vl+xVL8oXkTp+MqseRvFtYkkAVIK8RGS
KMbSyMTJnOQucsoAZEBJblADemhVL2eQAj4xdD3hUPLPzfHI3p1h8/vVbxVJrflKTm8aIVFzZ9U0
qu8dehTjujBpxhfdb3D0pRAW0b7/kfvbjFsT2/KpH5xublzOzmZLXSKNjpkMv2EbQe5RVqCLppn9
mAHpENh3AYO4Y+JnMdHioTgP3teOJsQYoPkUKaSa5mNtcFC76pSkLPUlP4SitdjXO63pSd9lWtAp
NbP8PYtDHMIEs70Qyr/dd4KLKo5kUvJSy+yYvUlpUvlcVQk0CBlEAqpnUfqaDImJCWEF3jL9jQ3a
baPME6LgDnsma4cZ99oiFXGm/5GC2aizJDal7Pn6saxHPFdAIsx83R9KW1pQ92pvfX3qxLHarkPh
A9dNFEIfjOpy7pxjXjaPNSAJDXLdMgoFM+QwM8kCemGuXLWr7KnwyYsZkSc4Ra68GYDDz0G7lVoF
3NOMh0C2hHAeuy4BS7V6q6vDoDziW54HlPLtzDyUa+qPH9uBlXmoNT10sF/AX0kX/xR8o/ziej5p
zPvHctH4A0KHQQ0pn1+ltB7gFNYwX13B0V7ixhhSYXDhchhYPCarK72qRL0UBGJ3blfI4/VN2lX0
/x7Jhgll4wxIpNKOSihY3giOxLFsQ0+KZaolKnvAeDgta51JFYhBeTTaKeEaBm3pa0i46lXBu4pv
AEwxQ3rG04PkoaI1RJ+34IY/Z7XQWtnJSvhUcopvU6UPnRLXJgyi/zq+ZNHOgDq47KC2w5/6bDfI
xb0UAIthltbWq6GVdaQdLo1T9Wau3SfoP4DeWCa1DoroKSu734VR/FKtFc/94sBKn7AfNV4dtIbz
y+EqtQF8lTVJPdGxU5EmMl8zFJJJCu3uMBgwUVF34+d7Cyg4F4FDXBvZofv7wGNrIP2QuRuQ+shm
9HYJhFbwf+gDsuIkDGhQSCkh4rnJ8hN8JcSLVN7zgsxj6kSsw+k9FQnBTFkoxkrVYwyNop6Bh0bE
+e4dyggE0U3kkMY7bo/StQREC04ZP5WNa0iq5HP0eJ5gzsxUbiPoqr04/yfe/PuQzS8lRU6BrzYu
JeHh7meqT7Z8yU1hzlNT5tPKVtLhCKT2ENB5gUahel7Jxsx2n4hj2PuAoM19uFt0cT/FfVTw1Rhc
D9AtLZx7vH8qj1mzjQBz4V9jZk+Hur/Z4rCRtyuSMBXqLhJN+q6+3kBFeCE+v9M7kMEEJ6PMei06
YKeSCgcGn5IDqtiQQPI+GzyvKgAWvUlJmBlcw01h8UrWNi1wrocVsiXryUmmcNdTA0W8Rsens6gm
wQznbWdw0XVTuRHktxseZ4Rl6LdOND9E1hMhXGPEeT8IHWsvOtqBGiua3UJ7I8LB/nhNg+PPCTyA
Qql7LOp9kArSL7Q9CDqDvuW+RFC7ycxJVs5vrtGZAqCnLhgvjauJJrMb9KtP5EOPSdmb7O0h2tov
hcPYSWSn1pZ6L4/7ggTb193URCrHWkqx0KewUGeOFd/heiQX4MsG6PhppZxwKBJCswtRUHp1hn9u
m9xGNFCzTKDiDo1RFj0c5JpYPLlbpqyQ++SINvA59M6acjU/XmcPmM/VLOAyNAckk+75aK5Ik6rY
Yc+8ogSf2MDvXFZafU76H3PDr992CCZ3byrL20vfWsQX1KjL5wjXG1CwCdA2rJuMm0I34peY1A1V
boc/mK1xgG+8/xzuSM5sSJMikyTyY5tZPPQt77LeMXe8A8SOI7cZJiSSl0luypB+RYjrpWElT7Xu
qkM8oQRIIdI3Rfj8xOHK7GOcTNwMxbZ8X5MQ9BLkX/BWzlZsYm1b57NwRXFc/swHBEdVBh2ok3Lt
7GNopFpxsNw9a6cbBhRYgUqHqQgJ09w88b4BYafBcWu7j8kinYSbs21pnpi6yNJlShMV4pEjm49e
yUOiPQLAU4/GexuctVAfwa49JT7s1Of2J030kb3yi+ATSRefpjm5/suucw/dj0G8H34ruHZJUEB5
X68uF46VjIqXhkUZu9RQHNNiO2j1IaWJUMqlLungh9UInPVH5BWpmcJccuxJQD2APFMZiAkpJ+OP
PRNPaTyWL1fetpa0uvTSGpP52peEdUN1jatZYTkSt9l3gcmXVTdVc18Ag2oVs8sZ1kAL5tW+lfWl
6gLw3mlK9az957tAqf3gYAVGP6E/CXzzfIl1HB8BcGsTTKSIRB8ZI8A/yVSbtGES4gYfgDpV/Pzc
mFh5DOwj+CFxQF8xEh6Hm3k+t07fuvHqwmgiKiMmFb6su+GLdvlPrw8PsYosF5LIKZ+QJN9NNRV/
lqgVle77zbJigt+x4YB53XGBRjx2xFr5eTkomgrZZTiAknAXls/XFrrqfXWVgJVIIGEjAE6KidhP
csOwu7SFfVH0ihr1HJkruqkAQ4VQdgz8YoQzoYoNpKcQm8Il9+3cT7zE2d64dr7TinaC7VK9Mqqp
gm3v94rcArN1hDagAel84SyDfcwPkEtDGDwai45kI7gYIGDGmQF9QbqE2nP23AMv1iwZkzYhdXrY
HGAX+hekcj45T30hHlaWAkCQlba4JkWOJFPBZ5azXYKXCEHjAR+crKQxC7IS7OhyjvNaXYpg9PqF
J2wgKAGr5Z9hIxMP9/oEG9rMyEgHtq4Ao+5SCO3G2uzWpTKIF4Tqnuzz9nN5tjr4Sg8fjgOoNjEW
X4ZVVKcM3iEyFfEkiU8P+Np7mDYlLm7G0s48JmjxeHq2qOKLqBCt5EvVHCXZUKyqqlYxBtf/NK4l
MwNe2L4CchaKL7sk12jiymUxWgPLwg1U/1sRzxo4pe6uNTDqIMMQ1ptZsfgUoR9pmhBAFdULOnOj
RLYi2MW6MrLy9pWLawtxkRuDT2djWr/V27Apd0MOIHL68sZBjvqjusVB9mrhPRNW4XmXyIAWI2OX
/zktas6sKrKEYOA58xVxr24niK0XpkCeTuPU7xWd7My6QXvKQQqFobBd4Rj3AgAroo50joLdqYjO
VA0KsyT+bvSzJ8XsDDNVLcoUZoQOMv0IjXidfPdowyruA5Pv6hrWOvwl39nqEhsU9TB0cPqlqpSM
fSD8Val8Jz7N4/Y51QZ1vLXDdCC/ulrp7Mu089CTNzxctZC8Vj47bR7GWQRx2of6keLbjkhi/8C3
B4JppgmO7aaAzZWlnuww7Ob0LTXR/uE3NkP+Mzloa4d2GEr6eovC43BlsUAkgdy9Cjd5ipGrBJpP
kjTyTf+BeYapVOFKCJMO2vhKn8/A1ukthZjKs94Mrfu4ze/Ra7VFiVjZi1p1ymoZ5S5ApksAVdg0
Xe8p6U5qTuJU3gFaa2Nlzeckn0Mvka3IG5HlNhpTaGwZ4yoNv8tegrvt/1eWuNOky//b6qO6HopL
pVO2n6RCe5FjryNck+lpEt/td7qdpPokA3t32Gyu3JC/zV5wCisQMecgy+Js+8MjZt0sfoJyv/Ov
yvZ8u/2nMi36JA+VDwChe3svodFPdqaHy6RmJpVsMQZB6EQth6iaruoBGVRSw/gjpW03UlD7TkoD
F9x+jvMzgnWjGbrjskh/Vbwg1zHW+aJdjgDQeeNe56pRbMyZjxbeQ3g1HYsbaY966wBqNSWqRXUR
tLTKGLt1bdEsigwO7QeEP81k2HOaaD0zAzzfp0Dl/x429gumOUXVo6+JIUrIHLdjgTDoZjEnItzj
8DZbDuazJvuKL25E2KZo2YTvpZBNhduR25UbHbsp2O23e9C0GjHQwmjYUkO0PPhJTYDXRcJ8a5JK
05M5rMTmHRdVn9nrDAsoFSGegykMw1OCTAlUhN6PbtnsSetiBHCKud68D1fXGDyzfaU2gEgZKNnu
zFrxd6QG8U/iBqflsRi9S1ggsL8t5Hrz3/sMw/4epfDyKt8TneTGlMGLQAEmGbFRlPr0EK/ZJuP9
M2CVReZsygu/FNMne67FTADXTxkMgofypXVd6UPHKmWAg2vEIbcyLipHBsfIMGUgk8/Hr8Z4EM3E
N3F+OqbW+zIPkO5rVgcx0/EHfcmK3F8pI2qX6etYP4iGrvfj5/dfl/5GnlT1fj1OHjSHsh9u0Vxc
yHdM9iLGRv4JmvAwWq64QDFX7RzLretUYY/ONPyNrPUSatt862CefuWrR4NCurZ30b7yRKau5k+u
RI0bPtToB/vg45Ul+vmpx+PkOOggHXWaRSRb2m0jj1wvBfrVJ7fayh5ta1WS651vecq+yzwwdFOn
MR4Myf0rjoZyJdItL3yStDj8dxdWkx1xG1PDWdpnhPPo8tWjMRIHn93sQ0Aqy/9Op2auMfkYVExG
gX5jpKB2KokqgaCr3y0X38YAT7Hso4w8hTwSh4owsQaEWlkwIUCKE6cbJcDjBICleZJD8C4594Pu
aJfhIwN6aoJBeDjDI2c/XL8AgMm1xHsmC9qyX6eFpji+x90wSXQVCvo2rrSjHZ2Pk2Er7WXnkMLo
VMyHRWWkOndnfPWLnZEEuHGbkLX6X3H97nfufamE558LH5MBumWpvK9EswKn6LJqqkFjpyiJ4OCL
q5PbHs/a+9oN4w10XixlZ4xkhVxWuP0PEHKMkPOQhpgfJOAeo+QvOdKs0lh0xA8U3cy8E7Xel999
13anDDKM+UG+3cYcSSVjBZ8xFt3jOcFEXEsQBmLz6wxxaHZnrxak7n5Lhp0fU1ueaOkP4iE/FmSS
PQ9JiTTKn9ps+2N2AtNk7/ENfI549rmi/P22BS+muPR6/kKEmK9AxyfwMhW8RtbI4mpQYnlI/wcL
0kTBM7ZRTfCJoOglINZEmK0mRRFBKGcwalMgckU6eyI7E067RYYqx3bt5FDtUP0jjOiG4VHbOTJQ
dxSfX0WSSuDu8DYyotsTWT5wwd3EkMDJBkygeoC87n8bLIZ+J/O7xzKvhuYE3ODUF7g5LC0mvmph
hYKftmpp2i3rMBpY4l8vyHX1H42I3d4RYb2mc2ptGS0o59JFC2+pmZyzTwZoItm920zwqTzeBdEu
KF4FdwbvgSgWEJsVJrK11avdeF0m1LjS0wkLv3BG2wkI7hCm7QglhR6WYyQ2yixnEJpIhSqhe86M
YAB0iar2bLLwCBgijW2kDDRlCilKPjfB/rNn3l+fQyHhl/6ib8Biuo8gadQybU05OiwwtMQC9bv2
HgFPp3J7yRtevpqdNn/EzPBRMjweYX0BfAL/6QkjWrs/ijsXT5xboRunnpi9Xwf55jjQvNagX8zh
Aw26NAqm5XP8+h0pBTSWh5vtKtFO0lPPPbFnxqd/FMcijUF0sykUH5RWeyacbzbCxf4qX99jZxZr
Cy6XVReljcHEiVkNA2XOLyOfmzv6ToZbL70NigDKtiFN71x5sZiA57FGIzGe2Swteqpbdp0BHNsq
PyYsg4p32avynoyXLLc8bRI2saU6CTMfmxGFUATwVMwfEtlUUj7Wgp5TBiqbFC62rHuUoX2DoL7T
rsMqIsF35uH6BUmbvQBWRqypl+iCGziYm/QpOsVa6GFT9/DwtIilCrXRlCkPpDb10A1a+qe7HMd2
OFxdpBm2z3dQe/18YTEYtgWVkkOkcMh8qL3Fe/QJiBvztSlGh1yKRQxixxC1AocV/Ms7FZiY3L8d
OxUoldZK0NJYSz+R/e1w5FkV+9rS/guor9WYDQ8Ksu/c5jr9a6xKTzsRDMyrtD/mkpRpDqe0FVQa
3X6ElJjwaauWBeU3E0vVqxXD1t9no6xJP8/WSLiKQJSD3R0v4LJXfx4a4h4x+REjOA4RbgqXga7o
Bla8Gy3ndG3pwi1QPoj9ZIxYit5Fad0xjdNuEt/MY9mu+6ZXY5QR11dQGKaWveB6ukwMgRusXaCk
Bh6x9qAa2/sdR7QiMsiMCsfyPDc7bF2x6EWWtzEKcYftVKmi5dUgpzkKjcWC3PJSeQ/ELW1g1Mnq
+XhjJtDJYLdPBmjk4td/SwrjO9KkxLFs2xvb+Vz54U3KLTEgRo8I34240huNWkzkHXH31kXEFY8L
yyxkRGNl67XxUBD4z8dc9DsGVaUVdb7fm/2qsuu0sCip0r+XSIT9cgZ7HkLT0rRvxGosdA5c9zoJ
uOGPhez/fcfZGkvrf9TOkZ09DCMNXGghDisz8ApHChQ6wBkQ+PydtPLWarfjtm29+l2361rr6Cdj
BiKHX2qPegpEdTImIzDWbssy5zJ/405GLrepLuI3FsqQTo9ZqCSFaCziMbR5WeC7FQkep1Id8/Ve
qKTOEG3OIil5nI9bl5fjHEXsQwnfgkemQP5j10Nh58DSFGxn3d1JjiCOxwY3zMFOHgD4vC1WdLoU
6sNxObIJvDbC8kY5TvKxounDdDOZkSEV8215m6uja4mkbMHy/muo2cKR58C+dDObht0/Gn8ayIVp
+7JzAxo+KXClCqWu02si6FkDF5N9ygSq5shu+/o/wEfZNzE2gfS3O8XrvWZyiWQqXGfcXvCFnbYY
vFyElf5IJ+6tTzDB/2YhnoRGAKOq1Y/+B5/c1+N4WAQsT3B5O/0P2Do8USvMkRMR5nyWv/Re7asY
5HiikqVyoC32eiH884CFiByQuAM2kLLOyvNOINAGXY5G7lEFm8y7vx+lc0A9mibKI7XZ9Z2FRT+q
1cnGKKN45HD+nx5ay2xowefdlCkBwN6wD43q9goKuSlW3vNMUtSUvaBdhqDcjr24GsYpTbBSlpZS
xGqmRe/NnIlMfI6YnqZWtjOjPdUTigRG3dK19QdO9dNvZhDfEYr9H/egTEQXgj3bUnW7FhH5slNI
hF6Nfv4pE/xfLjqCwKicmr/Kwpx+7j4qva2hm1vP3zN55eWBOMjCFnn7DR9ttTBry5WzAcXgoP4B
B0Og+K5QdACxyGs5ScfClAGdxlTKy+tShDa6b+lVLRO0vEkMIyiZOPwY2AV8qLeoAoMBcbcLsByD
wU6WkThcN7wF16ohnCCxgtFSXM0qclGKKtZI95LK4rFWGl638Sc7pk8GicC8qgNeMuUtlu5Jt5Ux
YiXBtBZ47cNQK9Om0ij6V/IaWHuxr20TN9p4xvPtX5e87XjM/ZZdsWstK0+CAxxoq+g5BtQZYBFN
zJSUCZg1racmuPAgZ2kBlC1RRYarywOB1LuTpZzXLKastC/AvCLBJlLAUQ6ty9xr5tX8DnJhkLB6
IryOdZYoT5VseKVCYyleT5LP3I671U4uQzBMVwXTjTBM1swc1ryy2Jr948PGYFS15xqfR9/Fz8Og
WJSwmdSesReA1thCwIQvxgvVmGJp8ya/GbY/dmNGnKz36FFWHwCsTr0gYro9RH+hZGO+XwqMFgJ9
R8A0HNo87FyCfWeBqZvCOX/7qa40CFa7OnJDTugAlYK1k6k1guw0FMGiDVuST553iPhMBoPbXccl
kECmGCbmw9BdJzJ+3XPC0C6N8AIlXgB7K/J53dRojJRzUUcT7uDk/XZhoHwDmUv2gUKR3H30FDBO
VBEqyptaKQ2Z35ozplM/qH7XNBnf0Pf4KaUBHh0YgDmKBKe0sqFwZWOkxl8KOfJFARIJwiMDuMGj
04oGSruBhSb8dwxub1aaQ1U5aBK2zd4lez2TAq3+r+PW0r2be/8m14RmtvS4B8hd5jYl1D/XvlD4
exrllQ57Zq4NTYAuayQx87NV8y8S8KdldCvj/WiLl+v9Oiz2PuiG9AIutBFwaiSMP9ssGGnlZZ/V
02PBd3iEPFxClQXFmZlmNWh9sonAn0yXokh4/h/2LPiEDetEk0A8m/sGh+2UaBldXK5bn2CD/Hv4
9W4hiOHGpQM7lMR39cf9eDgGFaLwjLRWsW0FbwPHzLuRUpM+pI2Z35FNchlapJiWE6XTY3XmbtXj
o2eKwa9B8Te59Re/GCEwtX06aoUf/ixT4zPK1DAoj3Aa4DW7SRbhRVfjD8bloX3ng7aOc1PSL656
f536NrAS68I8WYmzhEnAqtFq4+/5pAvf7CoXmUi6suhSFKLod6yUCjuaQ79geQO6ahpkApOTTu0p
m9USIkbH7MnOIAh4kkjoUc4pawNinYlDJqSrcGaCgFcqbDJZhL9gi7Da7tW9QwQNDjm0/DPWNtJf
+gUBK2ReDDNx60w7mLSlov/+4bRbNLdiRXltMBXRkvxPs12+OlCSO+s0hqMH+Vb82NHSuGrH+X1v
fEfdFe+XQEhN2Vqj4b5XZctIuBi7uRb+XMm0mBTdysNt7/D01EZf5CFot5VkZrkbxGCLywG6h/eY
przI0a6WWUFn4/SW3PqNnxgxWtODjzoop1j1iCEgdWj+ydIhRO0nffK6gwEqb/ta6C9W5/YCkuYJ
J3btgMBqGrgL/NkhdU1MA+iSA+TkocQ8jQFr1HzKV3aXihH/drOiDF6RAY+AL7b3KH+DciO53EUx
Qls5ahI5vMUw1PdGR+Ks7OiVPta5CfMCzpt59g++LV9b6sR3ei/lcAlanA9uQJeRKRJ9/MTznoKn
IggARmKUrwB7O3jAEHam+WGXQ8Up45JZiIlcacEVx8wH7MHJUWki6DxZrlUTylJOy3UPu25m9W8K
VbJ0NAAttAtrBeRbdbBUj1GmNtg7LFPRlsE4D0MgXH2vwy/d5X+bo6PDMTVUCtPm7NmF+rjHRmDv
5IY3I2CpmHJkbriGcQU9M3Gnz+IRwtM0+mmkquaQb+yEoijEY0TB073sATr1sO1jlHKgzan0aygE
2KZ6I666USegOQ/7lniNQ7bCX9d/EcV2QJTRqfS0rTVhnRmbEoLjRcSLN4OTv4y4C7oUwVr+/om6
8cSYtlhYSpYFtG2XRwtEiHxXxo/BL3rW6V5bCnkNTMNpY8YQfAbJqKdT+qh9Y6Jh5IxCYLWpmWKj
GnQaHwbjhygMqkcfcaPW2J9al9dzWORKLNIQgHHFoMoFXX33JBYGhf9WnM+RuV7X+b2SYbKlC4Vb
UJYw1lSKyjFuOm7VS9JDhKOkrAIJ6ssr7KPSEGLYqRlFaISsajgwMWTHaGiz7Kia1SULb/T4F4NY
mymmxqkoejHuX38l6CGFxQdhYuDwcLDi1E38O/PYseIqYMOioQpjRO0CqGgtOYZu5jfq3yGRyRYY
aGw856eOYHVPGzuSVXm0GMHj84KoP19AsINf2uKk5HX0IqzKEhTQdDPUowFy3Z5Fnv8ieuqg33Rn
WOAKDxkx5HivPAtDPh4GmjPehj/IkCTc1tjd2jd3xX65IDc1Phh0cIG7xR+22/6Ux/Sur/McycnB
svqSeAeWdiU6eMF5W1TV5/FzjYUkLVqzBneiULyadONsDM63yvniwkK17sQeDEGHdnHzDeKy+YG3
88HPFDaTyeHbv9n4G2kZxDiDLZST+IPlVH+vKY4lW+d5ppr1VJ0mGV8cRILTmu2vexAnAhaiG3xY
perEkg2wpV/Oocf6ev9LygIVO87g+45XpPp5gma9Lk1tF/X0536XwUTNrUj053rzwHQMTEe4hsP1
BNoXCDKtJ/6K3QjsZJnOwoz3cudttYpNZFJkfv9q0FolV+TWH9F2IdlZg8TJOlW8ermkCOr1R680
WHT+kKPkEnfnnB+caY+1kpRSkUTmPmbP1CbcCCIlWczXfHeIrLxDdfWfiCkKPZ7rhuAUZmECI9P8
52bGAKNU5HvBcB9JZg2K/9Xow4deBDy2AOZ/FoHK2arm935+7lDIIHYgm2kqemFWHgScNVxqaqRi
4glex/PSXAOr2xJlx/EcIKGyL8XscdmzSSvrz9Ghxyf2O/pXnQDi8UhEYGZ8hpHP+1Qcy6xudz7/
HJ5b6/oPnWbLauuhZBxNI/xXoCPx6UnbIPr9MrMupEATJ9a2n3sXyurg1TD8JUrdzJcyAMKePyGV
5AoO3fkk3Be5vFwn+k5Fot/g7Re0DaZ6tBz9d/Bb+xxvmsz1TIcf64cnUsyIIsn+4uBrockMrX4V
hjRopedb+Ljr1l1iLWingcMClTo1qJDtA74DeAz+XeTbNssi2wh1crgv30RzkMEQnZXFinUsIREI
nG+EdShzKphrkw/4Nwc92sm3gPrTHXylEVaD7U7kJeFrLSpushhiyrwL5ByLVNdVTIb7ZCapV6JU
sxCW/sHIf2+uiQ2R6Vp9hLrYvQdk3+Nkef451Nt+2OJ1IpYRl9zyshkL/cPpiWmImlTAHg2apMlE
JkYkowppbO/s4H9FCCz/0cUmb8T42NrDOfyRKtGn6+PNtuVis7cFLgan0pW/lwcKLt27O7uVCL4w
dzy71Gt8CGTfaAsqSKovik1bLoGbTzrxmWVf1Bcg4jYwq4fzEuqObtpm8WlgM9LyvpxtDQLYWnuZ
ApXO72ZB/+SjlOway7mKIyfURbOsE/Auc5XGnPMu1eeZe/Sm1YjYXi3Hh60dPWg805YzfeNCt0eW
59OU0KcfhLEI71+LPYXptdkoARkrBJBaagSTXMbqojEuVYBvULJsVlSQZvbYs5lH3DDqDRQ4DG5b
QQiqIpQBUj9wFl/hivMcF3cWmbrcwH05VVBVFLWWMnQBkVruA8+/PAoxW+p//n1eU9LjNHbEvBYZ
liv9CRIrT79sEUYn8Z5u3Xji2T+A0Xzmr2Fcl9dUeriB0pTtZNvpF3nTqpZ8e6LWTytVQOoq2F9G
T6E7Na4e+rNvgztFNvOK6zGre1ViYESjgSAhKOrSM5BVhTxqDwZktAoS/aM92fOxeAM3AxlTsu5D
pRjj3pHJGRvbWbWVKs8Erh1NIF7h7h3nHNuEk6+I96uZFOTughvCPgZPS2Vm8RHQe3MfOSEj6JD+
AS0ZdIQh53kqmIZyP9KppyqOCJRDhYVBuTKluuSQlESBpsG1mmvZKMMEtca3j2kkJ5oL+ObCZ6S0
0wmP3w/4PPNxKq059dVMjIoHwDN9ehGx19aJysCrv7q0AQ+Mj13sLLBez7sLIDeSkMmgNtx7yX5g
ayLBrRH3NpSGyGZntXOfpdv7rKJhe2eNO73cJYTl2i9jsNoxnQGwQfM+lQZGDabOH0Jb+AkGTb8S
+bT9Xse4jscmjww1F4gmBTtGgnaR/3pn9i2TD/jDwgBRxFLb7di8a8N54wiRZQE2lym/CWtimLWr
oPYcKFE6A+8mDNMGMXvscZHNEsghrw5Rd8GS8pQi26DVjvZ5i9anaBTP7OCmJgR7s6y9+cQMCC5v
WrsKSjaFtcQPu/gjVDFesJEXvHTspQaUqN7ugKdcc3VFuoT5tgBD7o1SiQrdxo7TGmwXafhUgDjM
WsFHMpoVo6RQJW1swTExtgs7O2JIaTAr/QQrDl7BOKlYRXAkxAtpI+8nwL4S4HSatr0w1lrh3L3c
IXJk63iKBZ4dq27WjJzZCVXZ+zt0UHfoRkLelvNF3Bx8Q+fQem/c8wwM0NFnsJodaRXZjvBwkCH0
HJxFZAQIl3g/46hdYKg/pbbdSYqrFoafQAJXS0Xcy2WpnMz+E66NbrZmhz28DxeEW+g7G3QnfC03
cpHhAAZqqplc/UysAlImf0KfcqNHnZNB0SDBmmq58JVmiLKM53PgjHqQQAyBHHCrp+PbVLPKB7lm
UAzsABzT2svK/tXOH/+LrSQQSmRpuhdLYfZnmQseRIfNC77DIjVNHyESm0QE/3yNhMm/UL6RZylB
/2w/Aird1qL965WGi1ktdQuoHLtlMBNZmpjmOK/LsfbVzMapVqYcsMeBZn3LE9gPmyZXZ+HNrqaY
MRnRKe06Hz9gOvS6N0n1KzxKYWdZdZXIGcoGjrft06wUK+8T8eI1aI4NMXoLrYYrJRmEIigusSbN
7RNX+VDsy/hAx2WMKgz/cPFlSEJZstXFZ/4NEvEMlwlS+WZ5NREfU7KgvJ/ThlJNi5vJ0uV+8K5R
bMiQLso4oiJ41QN1+tSPm56Imsp4fXA5ifyhPqpcQE1dVlyGVtnLfSPHGHhrB1dm38tMtZSiMU0V
HGWG2SfqepTHXrVK6Y/72Ei4+gfodUVJS3PRvljWuZqysOV/51gBbSGTExCwBBOln+oH8SKG7/PS
S032SvdeCR0Ua2bd/VI6agXCjNw/JKOuZDudsFNnCoClzJUDSqI5z3Vh/l0/qixiW/n6DpH1mHMg
FjhxcyOGGo0UsbomZ58McQXxejk5/c5cacOSMTCb19ZiDy4sY7Rszln1o2UxylJqC5qCCA0YZi9L
eP6SiO8peYuYug5w4AVKTMNr326fxHe+Bztry5on0GhsuQGNgmz8NWiLO2v3RycK2fRiVVfsn1AK
2plGzZjHQZ4tnhervzS3bTH2/fVeaWUteY2LQVdJR2ezYfCnvnj83Jd0FdGKVpI3pX9avHyTdTDA
MCPwFS4xAjeGJaRWlUHljWa+6Rw08jNeoKGk59rpP/1VgzEv70iMxJaDiP8lvrcJh+ELU96K2bti
hA65npxfVUNJibq761zgULWpofTRAILu6OgqXShZgc7uKpweOn4MR/vsXp/FgNdayhF1rlTC/01j
GLC+oZAgkYgajz2CVsy9gzK87F/KHy1b2FFprDQe9ctcheUwabR3Rk2fi193BpI6xRXR7Cl57dA7
WUR9Pa+kM0tLTksVTP76yAS4EyzuHRiW8Jv3V9hZiy83cp17B0F/1Ctpcvw4BYFoH81yhtraqOpF
qWcS6JO4emoZnNSPMKdRRJgavRwzHoR0t1QYeh3gGgyLVrCOpUmw9ia6x9qTrczjAuIAiDDgbWPv
mieMq9pcHAyGkbAoeakvVY6tgEpSwbV48GNzNsAFoqHipOtLuFRt1Ra47no23g7uo70VP2grC6B3
eUyM44UGlp+KYQWHW5WVPwz42J9DCUX+LsbDnXCnkkcpsL8mE1N0Vhw+T2HfJPgNwbfjuUy0d+Ci
QLzi5v/p3aJZTHOIQTi7gwTAWZUWdrOrH5UkgFzTHbVmH65RZBm91H74OX+Fu/HXI5ayKDFlPJVN
aYf9XYf1eYtP5XXdM93i4xr+pP/8nyKD34WLGNYeA4lTfRVwA44ojhBolE4PZ1bKBL/L5L3Qnl0d
QQh4JchKTFlVX0BDRkysCm8BiaMhcPkHIAHcbY6McIhnZYHLhjoZU1SVwTwIJ2booIG0RQxU8hNI
Px9zUb1jMuVCFOa4GlDOGaexkvDwxz4TvEI6D31TIkzRpI9zOGQitgmGGXXKZclDQGIfkmvYQnK/
ebpWi4V9iJ5IayqKtzyMOqXTxpkX8IiH2Zu+h3wgW3964XdSfLdSxSG4dDmMPmfW9YutMCuU9sWT
bjIoc5azACUs9/kX/TpD8E3Fu5xJP7l3bOyWoEbw9hWo9d+CBIHFtGPPndoLIFxg9Ts5UCPAbNfB
KriS3Iy6b8URQv2wScpBypuLp31dZL4aHKpvQqR5xeAM1XpXHVhARpZKA486achHKK6aK9g1sWE8
dfo3UQADc8N4QDhqw2HpvON8m6Xap+k+KB7JJhhjP9Q2zu3xjLbvF6urw4qJFiPstNmgS6cHQajN
u4Us8MSAaQ2eqIgSec2hEuGWpld7nD4w3YB/ZRP696Rg1uIhswM74O8W7Lu4rirQ8zZ8Q+2bdHOw
YG8bd6G4oj1BakJm/J1BB+zuJIa9ADYbAqP74xaCI1YcsSeEV2wqcl4QCNn56ZYwH6ZO/Xqokltp
yM7+2mulfSwIAOrDUEZaOXd9iyWyKQ38G4D4O8PyOiHZ8Eb9JMPasRSO7Vo//QwvFeN77LKSBQB+
cJ1nt9gYobwVZG99sMAjnc8zvc4uF84r/SudmYKC0CYgWzG1un/BCZZkXp9SSmvsgmHbwA9ngB+d
Oux91tevki37j8IlblnUyasvt7TcCyr9X7Vnn/lonZaBItdqTCY5NlzAfVENgTA0lY6X7zY+1Jqt
pOJsEVowUx28CIKj+KDPRrZnGrz1gtGm+29XHPrRXHGsdhLTroLvlWTqQzWrLB2GDm+RDJbqmrs0
ybZtcBG4fUFwUQkZ6YgO/LNooqOEjaB4hlUa9P2VyUlm+VNXM6rtnDZHvEdURMGTbBOhAvJwG3TD
HR4qBa+yj6ug/cVxij5HDXplRhmuqfmKkL8pJSrmKAcB9RXLsrzOtdhvE8Pm4RjQEMZqDpD7SwYW
fx0eCJBhDonfg5dfvF7VKSMMqUu+RIJnKxwjX9MPEOSqAOKvbY8ZjSToHaCsZjdTGsXSM4xgpc6H
Ifmt+T+gSljsnRn85hBI2nKwLL0PueHq+OHb+sjUBtsdjAWJSHp4wafl3LQmfyW1wz8hDuCkAvVE
F+JfPmcXzSppmpgVP9MwcKFPxomoeKvvoq6M1jpAN2t9hqxFmo1xGFW6drInv/TLk8YLTq9tnjqb
PS6bJjeuAK/+MDeHdQA7+SZSpvYUgl0oP/vGyZRXZQqOxLsktG7FavnfSlppUdDtqhIVmP3UyKeR
zJthXaQgXFyNw+MbqReI/RL7Rucb9nKoSFloOve6JWBZEqeIGpKRTFtwYQfVNq43s5M74TXhj3pH
upvpdpUPcxhpWK7wEXz6Enc+4+aUNw7xVIC231YUHEvmwuSvPtDqXfpe0V680/6r450uX7em+foy
3baXqJTOEGsudJvXXF8WT+UKrju54/oJiq9Z5MycGqjqPAyhb7hziGw+oDsNdoFpPjElqWaXfIgO
u5tMba2EGCb4QXD7iaUU/453+xxhNmsd143oOoVLd9Ymlq3N+V0w5g5/fdlaw0vZ6DrOWMlUrHW0
QKT1iAsdUERcdtLI5snTTmZbcs9NmXstv0HF6dxairYFv8GLfouXPVqe1wkBPnwxnN2dFyfONrHV
9AuvmZPG8+P0HkJzUH0mkneSgq9C/s20p0D/KrmjXYtnu2FJ05vs+Oamde+kGBGsh7cXGbQszWWh
fhWOx6WBDN+lSyHLzxAq08j3mUTC4xGVO18M8qhjPB+XUXUSHNJxQrGqi7P7w5aZ/5un7NVID9um
i22+qNbB8HX+z7s595hoLF4cCXourOyIQ+HQZ7VbhETUtML/tqHxOcO0kQ1R2vPrbgQRhWWp6zOG
rXuM06jAMusiEx9zQ92ap7dthGcKZbqlyrir3hycC5xY84ZSZBsvYeofCL2mP/8NqkiQsT/I6eTF
4ZlDvMsSjdxexVdTNQTmCfVPMwoWu+FEXxIi+i5L+0/PkzVIH3s0Uzk5EebmFIv+G+c0KvO5ZeLm
41Jqt8Vhig9cf5eD7vuG7Wkh4eAd9dET62D7BGh3fP0h5yJZR1KwB/VEuQkYJpAt4fxI7IqE05B4
poXo1pgt7FVVRRi3eD/M6AQ1qMdwLF5ppt2P8iuZsZqjxFsDC6PBprDLbUW70eWtWjasg6FVlAgD
KyJaHN1nDG7BcSL7yoo2gtBSS5YdiLBsCQPfmCT25QfYeN0PprtYKxskWjC6xsL28YGiDKVTYaqk
bM71vcPb45pgsFyid+Cow7013w1j7zITdDnyb9Ngb4PsZdyeijLNuu7V9etey5WntTPN2FOrIKNr
079pzaTVb+wEahoZfSMrX4A0DbYn+pprFTErbuxMkh2t4kt5ii8JWstszln25f7VB9k7qFA9RzGw
sLcv7dNFGu/vYfHFt/qd9VJtkWSLplJ1b8t3Tsx2ke2DHSgfjwPf1hYj6Sc0nVPn7XmP5NKisF8H
HoW0rONTTMuIsYcEGaLX7PrgUv295WNDwysRKFhqGsEfLGl1vyrI/zI6FcRbvpfYt4+aPK8N+S4m
ffHXinex5xur5O/aj1juez9yg43fmaqu3V32L9P6NJU1FiPuSNE9iUpvy9KaCOFw4TUqhSwIlaS3
P4tvalnqv19WqO0lPuNwy90cHw6MboJkEfDle6uFMq4mFDp7WE/gcGU5IMnYD/xokoIIN4c5dPEe
zx+tI4S6668edbWvPXxPvqVlPNTVHGTsk/giypiKeVjXqcVdvv/if/hZ4JyIzKmbkX4q9Lztawiv
xzkmwX1SRETKt1KyNXOKZKyacNEPKJzPcOxRAAPVtApWAPHd/XPGGO/WAZc+J7jXWDXLJVMeXfMi
PNq9VebIqUFFsrLppYqqu5W+iDGfFbMVfv6tnVkmE/KP906lKqTZxDLyr1asu9ivM5jj1dOdv2+U
f5tjvYc/xJlXXY9B4k97ygSBRti8Cz43x0D9m6hO7V1mn6PGC0qmQlBNR+owqzFxtgxRjpmcxC7v
5ginMly7L+glrmW9zntRIlPTuHqkVTB12so3DzYbbBoaSL8CWSIhZj7Xud26aEYDpd0lColFr/V+
IDSM6/P+uTPMxSJeNIDPszkHxr4zCyKjXMcbbaq3Me0HzbLp16PgwEdV4D2BnxnVxYmn2hYj1Pkk
g2MoaiJgUrZ2Vlp5Yw9vCPdP/bUwX7TVSFLMV5v+Buv/chiyThQ9MGPyzb60dTENp4WRafFYcEoG
VfpGRfsYnT7vrhzMpaMgJaxUX6pKxlNYvFleVBXt1FacDdKUpBkE1JMH939QXRrnV7CE8dyMoQVj
U4DMOPtxR4irALX/R9vREXmxQjjBiTuRTa0Xda6FgiSm25mcPqBRLh904MG/HGXgjz1klqOebdi0
UyiJpWn8TGk7/ajwq8Cnci+HL6i+jvKRwtU580l+gdraAfzzQbjlFwfiBeUkENH4JIyssnChK1wt
igQ4LuvJlQgdurYlmmT8wtyq1DydSfmSyZeUbdwcg/XmTubaam71/fbi0hCMcG0p7MLMS0nQ6GyF
7DuqsdFAOmsh1E/Gxx9YZITsd+gVd5+BqWJEDqQsSLQH6OIghF7HvHTMUcUeCMj2wY1UFJL1S9K4
nQU9DpXMe1d+8UPQTGL+niF5Bf2kgRzmVlHMusIJVLIajClqJXbXYej2xe/6OrunCVV7cbrxUl3S
cmA0Gzvgpj+ydozEH5B6lWcI9cV8z6u7M7o1G/rsIjlggchq3PriNr8+WZVH75Etq1h3+38AP5kW
yWbtwiMZxoSNFVcFD6ff5OKNkntI97vEsGG9OvGjfRAUp/QOCmbvysVKuMOLn6j/WxKi28JPHSdX
7VKPPQ9IDQAoKusn9mqEbE4w3Fx0VHvH6MBR5M4nEBk05grXjM5OIZLnu0Fj4gCN31OW2gCmTrFe
rLF4A+HxW82Xk1QP9soJG1ruYhaYwJEslXvk57LaGcNlvtoD4BDDgAdrUTa8jVFJg77s01YjMxus
k2WwjKhe1hQFNiDqQ9DEvucYnbTS+2djSq6DiSH7fGom6V1fjS1tdPkIo3g0TVanPHZHBpjfB6Jk
cVy/yYBXKf9lo1+yMG3NHUs5w0seFdQYVy6rzuaXI23il3hpe9R4BUallBFCh8+xVQnFaKQinE2z
on4hRpdCVz8+OeSYdwF8cJNAvtDTNiCulBEFQq6iaoIkRtMoatseap930gV8pKlMFZasWaKsTjg3
+smcKShpTa9vysid+fPPOYmMu9F8iEbQrHR9ceYbN+04y6M1xIaNY45p69JVKjvuEA+P/6Grxylg
yP/dB1ePEoylgqsxA/JsU91j4f2u0jq+p6TzR2fRz7c2MOuu/ccwDaRINcv13aqWcBSxdlka+P/2
S4DTTWHKPaZUw1ZGqwTg80Z65H/N/lhc54xaPHEDD2jDk1gI0uBGITo6LVIPC/QcGKJ6nWj8x/8r
85DTZRUR8IruyYtrVt7qHvVSEEgyTA6MPf40Es5RRbVQ37jG7br37wZp7l4CESoPGO6oQp1GaQ1W
Y6GHUrQL3qJZdtzzV5Nfp4szoSSLctk7KfLvnRV6uB8We0hwXV72wrP0xa2K9G/8bP8Q1cEKxokZ
vbbdQhVZ+tcAGf1wzU/RKzbmCYwkYcnM90B+RLn3yDC/ce+usja6/bEcfN2WF49obqvUYbJTFf9f
ErRFz/YaDbBu4TlKKjHtiuy4cLoHFuXcOoisPbxq4uXO4R7zyG0PsCQInrRgBH+nlqBgEzLV3RoG
KHF27+YDGE3ftE5LzZ0cFx0BvdoTaEV03LkdApFXOLkhUhiw4Oq3OuiC44A8vy0Z7/LIc9k9OXFu
9b6EDKTenDDgmaMvt1smdlV6c1xYVizPzZ6MnkwVOpOUyEj8+c2SDe/V0JhIc5Q+TGvZWxnygbXL
aVM2vrLGXy5fQqiR3YR1nLT1DNxRsBVLoMDeJV207XCvk8w/sW3bj3ENphvX4u0ERKk+ziACNiJv
zeO59arsoG7OIUE/1yDZZ/4aTdw8MWXNapdsjx+4vyHva++aB/bfCN+zRpu01fH2Cgk7YJi1r567
Bh15VHADhGjXE3lxGrKBIIogtMKEAlt3Ah8XCfj2gsxU9e7/Mfh1uwqMwyRR5WReuL1QZdNcsmnO
JQVSJQQpJr2vR5Z6BRaXqHpxUnSfREWhHRdHkT07xubT08QxufXiLm/n0jSpKlIjRxQddFqVKZVJ
VB+SFdj8u4g9ldw2L2V7gCwBi1nt0D2bQEn8MzhjNrJ7WpCRfw8PK50kOW6Y+B5pAQfYYE1b3/JD
xW8CsqQJ0zrXojG1XcemUj3pHZDuF25tC8SezC5DwOG9fj6fne3yUV7lxbzhAW1EGT2xVwVUq0d2
nXcSvCpZ00bf996nJhreJD5gFN49/0szmQpirgPEesji3Lge1TpJBYHcvKKUMryp5Ln8fNNJ3kvz
ApbrxS5qq0A/s3yL3cmGwPKkQChbAk57YWnYKrvLDzTkAI/d/CkQNT90hC5T8wyGOD0gXLNWUPz1
whR/NSnJUnaNHjta+vLdTyMJKddwirSa10smcRm7kq6JTCsBEsfhipSkbflDtgcqwT8hHwjk26JH
UtD6pohNXsRAxPDLffQQDCl3b9e1B75BS4okUeMBOC1U2sgOWkLISGdr7NyQ+LmiI5wxrIGZIuPR
HM5p0JpsJVILUKh2kPlwy+JlhLWM+jVbqizfyCnW1+LmBzig3RzEWA0eQ79u2xQ/vWg2+nN/5stF
HUIFSwc0K/kVRzrCMrUdTIHO6nrr6GxT94l1MkO8KPBakXdQqa/IJIoQl5c9xHOc7uBx4En3Q9H/
B6DqK5B+tKp+9FDigGBTnYcQuTlqiuY9Wruxbh1vet5nwdlD11BjFUrfPmi4V1sNYiZH0Vbo4OfD
zolFiN9Tkwzz/EX6Facl7PAd4pu0WxGyv+fPO3mb39ey+D5g6G14CZVYuR4W0uY32jLnysEmJX+o
m1VuUO+hj1aXnJ3LmkdnSH9fsgc5bPTBZPWWM3dO5KnPLZ/bcUkUS/8xZs5b2xmmAEK3Ixggach4
VKcfvabLrg9KxlKVTehMWf9rBvDTQzKOaQeDPbQs9LVua49SQcRSo+TKNof0fbeaaXDGUd1fXcs0
cGnAmc9+/VZUlRi6p+rVLHujAMJPk/8Ld074msAiwZ9UeREr1C6aPdraihB7ho/tRkwBJ8HsMmng
2QLfwE49SictbslMKzjg4GIDfwdXgxiShynHaW7Z2hEd6yP5thWEw45sOeUPdR+7ubBSE4i8DrhL
hXaqcOIfYS3L1uHsh5aQI/2mFGRVtfovglJyPZzNNoY6LzSkTeVxs12bmndwMj+noJQBgP6ZWPYA
J7+qlkKkTRX6U8Fduv0UO9MgngRWoUQgSrqqpa+O/IRxDKxHV94o8NkgTu4Bzy3UnI343Z8kWO6c
eXqZfJeuYGCGH2JftraI3vGwHQQO+3K8k1RhChuv74eapg69MxumyTtTre4ocxeoRw9lqtJfRyON
A5Phvh2WDBdkuE0TZmaN8HBH3VFhyQgwa2fSjZVKtfuzb4bIwzsbO0jFbeKiklPiAJ1QF1gFSvoP
NibSvySvavMxY7blBOoUhp2z5UwiRR+n7z8fBHplMkXGrtiM5RRnAtPQU66Y4/P4cYbMTwpkNuu5
qGOyYv7D+1NH8/uNSQFzjRAwQF1uUbkOMSngV69GeIAT7nvpPDgjtkFA0b6zQNlSsmMEtCwQKb4u
nbtVsGSBzBP8wiuKhwBCfrEeh0I+WUF29DbOnLs8JEhS0UHQlyy/CahGZXcRPb2gRPckUxnEnJPz
BiD2bp9L2b4p9LH7bu33LuVZzP45VOdFdgnvxrCFEeCRGFJe2ZWI0hg8J95IzdheGzAm+1L6W5ff
B7UmdMNKOEcKlizCMhAtXFY5pIYyiY2kZxTZCrE48VXstEt3Vjc6ntUii84suPSFB+vjgicFohsT
V/m+X6MAlutrD0WuaBQcYrf789m8NTXswOSTTOeypH2lFQNvEQESOdT3vxsmM4TwJZarGAwUS4/4
HT9T2YwSZ74EC6CwJ2Y23eDVfpRXlaFB/5frPH/IsUOH/zTO5503hLwJuY5gRf3RHaRVCSCFJrg1
f5SCpngcrgjr1PuDkoWS744JTIXmEPfWA9Tr5hjHDPHKOOoqLaXF0vrZX9m6F5HOrD17WLy/Wtim
Byl1jgA7czGYk4MjhN+F5Fbg45VTrpBJExBs4Kj4TDeNwWcCxff14ZwduXnelpUZWtjSi3GYRU2i
IlZlZeWoo4+3gBC/8ABo5lBZJ+LoU/DYIns2i9kF8BTtR8TTOmys2EdoQqyDdJYeaayMl5yeCnDm
ygZVA7hCsg+fREA5AiSa9dy1Q8j7mktFRrzUyg9YKIAL4t3oTUfbRsKtPG81vHYTYZWH3DvXnpo/
VA5W9yulH/dK6TliEPZ7ClWNtE8uoGJOwbdIubSKKbgHGEte46XJeM8nclYyvBxVJasDB199WX5o
TojqgqliGb00rriD2MvsnaoDBtjL133oZiav9zxetGR8BCdw7PFj6fKCjU7pQ6GeTPSg0GYMNxRS
mbHdDA/V+XTk6cVOC3RN42QQ2exJAd6uexWcZEsBGtISUss9J4FtcfvrZZsDpO/00+Iu9r0mW1yK
AvYNupRuHIoNm2RZvDfjI8INuPxMTUFa1+T0aJEiaIN8MkdzhtG/t87fW6c8JFSJaY/TJ4Gd+vyz
5h5rALBJucdHabXY1MpTcYieZaxt/Jk0nFRWMKLO3QqVm2MzJTVnipDUBOPfDe9T8wXH/1D0L5Jq
Flype+iy1j0fpr3V2fy/ckcPJc/Cd9tzA1JNOWsH+tTtkpqsLaQLcmXf3mGTPJpNPftViH3vTxcH
q3Q1cao1b8rNk2oGsy8ey2DEWQLjLzJRF2zr25CkCxc36xdyoMxFCQQObXtMwVLedQ3Op7Ao0i2j
ul4m7WQZpJPkndC0t40DtMyxPtpdcrZyLx7PBWbRewDTdMS6ngnxBOJCQgPf+5/fiwITulW9z0rs
MITBYV0ebDrWCsG7gxYSEJdnJGg/7etUQRg0etR5aTIXPXuVeZa9Qge0Ewt9wpU3i4sj3L4TrKUt
98UJ4DyufOuKE4NTP/Y44WP3NttTtJ4N/Uf694271u/o1RuOVI+vWOLL8jN3uSYU4dYi19U2CVEi
n7PYvnDmRTaZWPSzY1bzhb31vcQIPgboxddPQq5smfulh3rtTP+s4AcO3fZhuudp1sNIN3e6Trb3
pO6Xj4RYHZEjmxPGAC/IRkgbnm8UA/yyvgN7aeWezaryPehkX2gjHbFzxUFceTVP5BbB6kdHAVpv
weW8PR07tKA8aJ6+wSig9WMUU+WWERsnkvhNGslW8SGn+J+R8klvL3CbllMI/3IJDKaRus2He4fT
TtecLyNjjWSN701ITHLZbvcmiDwqCGkkw9gxte5STjmMVspWvJUIjkCry732ufeCuA4YrDlYDYjz
93cvitlWwXFzGbrzrJG1lawoVu+EwQDY11px67e50YyjEhKGI5sK2M+T+1CfKl3HYnzmp9YMmd66
25rrQ7CN67Oj5Hz0jn9kFa1Z0/rwK2CaghTShwUYy2GTinO5lqvjcCoYj1LvaSFZZRixzkK+yvA3
m7b4DJ94i+ER4QBkB8x8aI947eJUq6dHBiNKstkaBFnCxqduwaSW1beZrKAaMeYQNyKfkNVOfN67
TQ7wH3HeftpovURSPP/wMFJIpnvxIrSjvjxrQX4pYHxCKsNUlykNW1V/Wjf1yqIjlC2FM6cBrxh3
oFzJNVkGoWyp1ShohZ711BvXn50YuS1i/bLMY5X8klLMu+bU5DLPzzYUINAQCx89ZI+BgrgdauHr
eDLf8UpN0+zjISkWbkifwOijKqTQQkqKUeENfF0FDlKH63Taca8d9mZalKED4BlBzVuzJDiN7/3Y
Zu6gxq+40X0eTIEb0vhR1TZjbg+jyxNBcVHK87oRXQvl2EkLbifv1Qdlm0M7kQBI23FWkCR83iEg
jOhFU7irxmothI0Jp/xYqQBHpfaZz0rQP5uDM0qz6OcMAtQQZ7GBj8EEDrbkourO/SfRmt99rDHf
HcOqNBq2g+3DyqCRws4B9DZGurhEAi2VCHy0o9kvXDwu/q3VN+KOPsExTSW16Twrb8JwDV49d11l
ynsuZBg3uon/KKpdytNtl54LCKav4ev1Jnph8oSt5AE6g7IgPoljfUpF8TmEL6EoTs6cSLDnB/b5
mlP5pFKe98fgUFx51Htq0/sbx1FXDncwdN5C7q6VtOSBr58EdvNHUtEqq3veNxth13I578euBzp5
/E7Sj6STfpayG2L6IFEGSiz0ORl7wrtCO3r2hspnG0SeXo4+KH3xgdWgHw6gg0yrEhwnKDvpPpTT
Pxs5O6XZTKyTQ0JFW44N1HMe0ILhs2cE1pAzYZDeQ2vM8hAQgErXQR2hO68dXaa62zPapG8HACQa
/y3mOGMNKZAVj9YjaN0PaV50gBJibIlquHKKfTSe9Zd3IoASUH8pKK2EciMHdvBGsjNFHx3EqXRc
mDbXG05nYLL2q+cJJ3SB7HSKtHyDhLlJSaihpBpD47r5r++g4Dyxu3vGMjQuQsjI1zHOEh3BPoDw
VtbkJX1EHsIfodWWbzF/q5GdWDLhAsf5Niu2YSO0wQrNtxeYCDE5hG81TT1SCx+vTbstfeUrLt+H
IpVo3mEYAcU2K4jyr4FHYIFK2v1nsdoimmqXOnjmw2KH7S1CTAaxUbmTsDWy6tobWZ/oPWmNiILc
2y0UwOQHw+6vn82ovrOm53BTcrSf+1cLlCwvDyNUVFKtunrLXtzNpWp+jReE4ypfNGRSWWTUiAGt
pU+R3oHI0qMsgi2G580FDJKVFjuxGeTG7uyuUfBdf0JFy/HYkz0Vh7LMlyDDWrH4rSbWzO+WPvof
G0AfMOboHXLUnfvt/wTJwrX5eaXHBvGs6r/el0MaXGWn0DOiOKEaokmXl0DqyBITUUBoY72G1jcr
1E8a71wl4KrQSvpeCNjfjjVGXyCZw1XQmTyoQM2QR1pG9vyJVAPFUr553iJdkllOhuSEa7qPqu94
fbUj9ZBCWEuYUrVJqwZxDTwQN+3lQfNgD/YMaUAMjHGA0D5dAfM8Ev3UiL4ULMZG2wNg7zmlfik4
MhRUM5Al9oAOsmJz5e0ej4Gnc89Cqibwtdn1jkDNMQP9ZL+wQPqmWoC/mF0CNgBLxeB0u/9qSo12
9xJvTfPEfVdMLAX4OSK+0DX3pm8KyzXujOEzssEkDI4SFRvRB7JhtjMz0RpJ9p7TuxAfNMz9Xs/5
20hL4eKMKl7AWn4Jk96IEoBr+jnZoL7CW/IY+yy2EpnBgbPQSJMWCsKEpT3zghf6bK8TGvAuVV7R
/b9SqvBuIvwJvqnTxlaFxGEZ+K0t1bNHv/exfOLHBqu1PFAwpeIUW8URkFQm9+WmHKsiuCJ7PJyX
kZ+S4lT6N2mw8yIEldAkwaUPz5vD5zLutD9eB8O0gvo1zJ2LGYK9fbcLKDxSbv+ErsZXhui+kcDn
VrKLrWmqmHVAH2+BDxp1u58g80rgSajJ4C5nWzQUpR9PZlYWDbyHyo3s+ku+40ORl4s+dU+UogJC
DRq14II9TEs8yY6W6YTU+OweO5oabygP1ff7RWlQ6yQzC0xSmgg41vfo91FMKXqEqRp3h7u9Wp51
ldP2QzlTVEaRGpgkyR+QIUU0/+nN4EC/PAIX/k1RnHRB7sven4wZq2JeC/O8Llf/a+RKRqZbbxXl
ERXhwc0cWh26301Z8XZbMZRqVRQUa8tYfqJTgNyqjPBxF5h2ucDcXBF1LypSGVr4Y7Qex0hw3RXu
libJXyoSpLDipRBv+r7kEuy7j//O/u5jZvCxga4Vzy8MOXRffFYayPyRA+Mieu3Y8DDcoMHDIv9x
HRWiVrB0kkjH9gCJwjbsd7bpQdVU/U55lWgx5LCimF6wmUAypKWhuNrTFtqaFOfW0aKhSMtlLAZo
4ryWXlDx074B1y7J5Yjrl7Z19cVaE2uKTEOkuleEmSQhcvG9py7FTQFc9TpkrEsGRCH/rL6GEkfP
wFGxyh4lbQXYyb9oNqCiH56dtZvJG3002ozJwwNVybHU9hnFCeOGIt21OX/93LSjxG4mSe4eGtrl
B0zVm9jPvZ806VVe5WmLXvMO2O2ondA23sfFuVQRhMe/Lfsx0VamQWbPwJWp/EQv2WZNnOXTybQe
myTatAMXFRSGQZ2iBT71KaDEjfnbLWqdPkMvJF1TG1YO+FnVdVNKphET7rmRj8p1sThq7WqS981c
zLEsQS3o3RhpWiPmkhxj13w/QqSwjjnnoC+6HLxwtfStYOJvQgvH1aBOC372WtoALXKDig24PWoD
bdPRXd3I7gkgqftkiuiJvwZUO61Zs4Cy765BXDS4+lxB23HLiQlrVySSOSzvgvwDvj6RbUcTGo2o
WrWp552oeNWgJZsmSsoQzspeciIg9p37A5f9nfPa4eilmHoZ9ErJqZZXfeA2Pz3vuIUKpfXguS21
y5oprFCyPnKVilHNhUpcwptyi7uA4IYwdRFUN6yGHKXCWaiIXesVt250wqBkbB3E1pLjqD226F9E
PqTUzH/q0zbrHNoeYc3zTusx7nY67lCzjUYXKDob8lQiry7hf6DYC0vXvgejTN47k7Z1T1++GbLg
8IHCi+hD7KRWAj09rBjHCDJAJoFrm51lw4JZ3EUBYCEItsJtobr/9te6eTBk1nNoVcY2TQvy07VK
0347lZ9YmEDzpj6qlr4po+uoYrd8GMkptf8RVEAN21iyuW9VFXAyYLDP5RpjrK8K30AUtJYlbgY7
FMqDMZ1emAOVbsiXrsrsFnw5X4KhiLY3tCHzCUu91paZDMqUT832NhiVBAdP4yP86wBgimq/aUmk
kRyHbf/SdpH+LKOOmpgmkBf+ipZXqJJCyCc0H8LxVbXtpjGP5TVQKlgEmjWkMqrLbyCAg9kPrRFq
e+tnW9GHMl/2DiGncCvj2n9wf8WuHHb+RWbQTfCOfnXsJPwQgYldzfpwV+pYdqFyrgQMnI4Kd1Nh
OWBhqC4sqaGLZTEYPymE00/GIm3QUFLLvoD3s1G9HTiX6oSoEnqnqrnag4/koAArx+YHopApp7s2
MlvbASnH5VrUehtYzz6mOsjhhcablGUyDZ2/+ZZrFxwMFZqQMa94tUTB2ZHqQmAWXTHpyvhk44lh
Z+UrNYWhnAJXHZ9AUtP24HhS/fmzL9uFxOwdmNxfOgPkKoSdkd3CX+mc0c5WQ5ctuSYamETVi2Jg
U5P4aYEjRSdMa5pSg4H7mbdOrd9Nc5BfLDASEUeQq47GGoJV0cKHsWM6pC53i72E4aY8PE6Nay/7
ckfUewHqQckW5DhV6VYUcuBZXKd0ddpdq3YCtzqQbMLUoQBAvd2JNd2ccvd9NF9ZBh3r5XTH5Qk2
JtQhUcRvVvnOta5o9LviY+xKKR+YSspOUtvDIriyMBl3Qy2ikDPglyVBDDab1CtI3kDqZ5pA67Aq
rzewi4P7uwm5RrAyn4HXxSwYueosazePyYmcN3UJX01T5GzyCZvrsqyQwa/IARPQYcB9ipjlvxbu
/TnyZtbaBf+mcV7Kw9AdPT1n2l8owDD8QcvBNAyodFNlF1Tl7w5JtNq2xmd0Av1nMkwieqr1AW56
cYO9VX2qgxyNQP2b+5uqAlwv863G3GI1ZsX8iLLvhEHR50jVcwuvvvH2FHBoHJ+6+Ecqp6JCXGN1
GeUBLL6y1ZplQ3mJXwB+YDlgKrefx/4Q5GgO8S1b847wC8kf/UbAWWZfkscC+bymTu9Kl6bPnLuf
25e4aQYzQzgXnnYdRyFBNGD2YUwrYaUUwM33S1Pkkuk5DKmsYggV4RxMNmI4NRaFTn+0ROqGXiLv
zNaicvERKBZR5gCpliA0Ruq4HxFa39RfJZ5KvKebOH2wTovSfl3FHt1+tTG6tUKWOnZWNKME88AB
3FfHREJ7v1Sxrx5WCYLGfbsivs6U9IR6opSFaMBSX0LrbJKTG7NfoZfoU1w6ozLhm2n/vQBwCb7P
0TgkN8gsdcRdCPRZ7agZ6caIzA4uC3Mdwp7g4M2M5owso42onQX1PZEwU4ftRKJmbGid+uAt9fVP
2Axl3LkilkttOAQY0KGU9MLRNwwej0tI1TugIfgop08eh+YVSWKx3YM55gkIOX34Mh7p7Qn3GoZ/
oIpgGCix9B5bxT4ZzxdSCvKsNO+5Di/ID585dDKVlIA/1Q8Z6kPpvdG8kAlmwRZpORbnOkmS/rJi
97LU93+8rHavaljrc9FqARl/9p8Qoi9//0LYTrlkdB8CwNQSH+EHxANHWxfI7mF4UZALYj4ghrur
2Y260lWuBLJ70yIHowgHc8dMB9k0G6gj5wKN6Jb1U7eoSbqW8CJuByCG2pmjaCFG8hW5Bx/NOBaE
pv/qEZpwMB4OxWvIkcwwdkDMnE79/eaqB/mrRLjnfJrjcKH0emgWPiYwk2BhSgazzgj1fM8nDHV6
6/RPq3UCUuZLeuYpqhMZtHWR/OyQqrbB+aa4Wq8Xn3ViNSND/fgvhRW+fKtAfytLqz0JQ/P/Oxau
xiPemnHRtiYMMxgpdth5DlMVnv3I66SOYx5oVW0uHYlwBpr323KBD+XWAZJ7p+uPMsPtyXnLVdi9
mNqC8HMrjd1N+Vtb8jLJnIkfHWUTptIIybFYto7PnDzZemCCHH7Ygnrc1Aaz4oLgvg9Dm/aKV3MA
MPEETQW+OQP6IrdOLiEvufpNCUeu1t3m9Vqi3xlhSw3lIU2QQXMU5exhE5dKTVVo6N14SNylOA7C
Zp+p8H0v8Ki4QeyPWRQAHAiRM3Kvnbh67vTtZvRsMvU7iflcNyPGwqVcd+09l/99Qs+SAISxkwst
I09L4gFM9vIJ/29AqOWKfO5K7q9RI8sC7QqcLnskqDnYQPCwTnoKDiN5jLfYGKWiFE+Eze0B4ktb
ZhK6/+WEzf+PyQyYtrVuVTluXu1Sk2xeBKdOwWZqsRDD21c9UGiu4Nuqw90ig3PaKn/ZJnwoWX+4
hPSTyGkiVeNZgSXEWlvVOsnUuyL89WDQrTXjWqWe8vXE0McUGi26z6cSZ8tDOfraeEHtohpQYRFw
QHJxcoNyx/jKjQKB9mYo467efKgVXH8v3AHrtJc6OyIt50eWrwsEYi6wufGAB2D3O3OT0lZezOje
5avxUe41ihq1s8Npzz2UYQHzX4D6NnBmoY0EqzMCDlU8ioEECo14bdpv4U8wpfiWPIXlXmf7NXFy
gfu2Tm/nnA4qcA0/JiQvdBuApq/Lrj+dgjbBrnI5aZtLi/HLY5m4e/ukOmVze/Vhy2OjiiW69ey3
OXtI1Sfs8SmpBTaYJiXVYr9d0BugaTQKay/71EchW5A18nNaNu/GTBuMTiyHciHFT8rN02lUW9If
pQJZxFt7QaRmGOmZ8B6hfYv+MeBFh9CtZa+VarlYAqhAfuoaUB/3CVOX27m6yWBxyFoLMwLCX3y5
zDu3dW4IMNIDNMGeC4NhqzEDmqiwzObCmbAO9XQVLafxMIHsC47cQ/eCg1xktJAtMP+/cOemplnd
tAjWErdmafPuz9KsTpKa9MVUQpGJQxlThKKDYBV0lw+QompclBRtHBViEJVtdrblyoBNH7XjN8Xr
Rtkc5bBSSJslLmZJINdhFmyZ5hPUCvapO7Wd55LMGm1iCVj7KqQU/nclXFhhUJ+HKLsOAMWUEbVO
nkfnFjdadshZ2i9BCsM/5yzSImsyloQhkyEVgWKN96SVNlZCiI4KvBqyHYK1QL8vwL/4vRiTB3Zu
h3IVws8/FFls28gTa567bljcz6IOdo2aziHaW7b5Urjs5cnlPOSQ5FAX9hnu5pNjD+P1GmyAzt67
tiWxJXBtw/IBL/pwSSXrfBlfPJ2WQiYQC9yvUdg/kDrPUCn7/+10AIXwtWY3aCKTFi0UGWpIyF2W
HkkNvr4xGPKD5Vc0AWLfVB/dii3WOS+XHjUOAWxzCbcPpYpje/GNJl3IRfnDsCnR3RbIQMuYboM/
DUSoo1SzSKRLmwFGFPOXIgslkn4NdpAbyiryXkLbnN74nY2aYexniBP1ANPTsa3U5IMA5Zuh9vBB
JWX2TgaYPGUlhrzz7woCgycJc95Lj6rXIyhIaL17P7ZAOQvo7GCk0qs2y85XyuQwl1IHpYcru0Fr
ajyCJIrAbEKasbiO9U/CnNMsHUhJbEL7lGoMwHrfJmaTZmpxCVpKkSGK5A++w6Px7EVCb+V14ZAE
iHQ1sOdSimRzFpitrA8uyDwE3QvWK46Wj33BOPpAZosxWk9vnu0dEdJUnuJmNv71hbvq71CwoF4g
c05HqE6YyrYHAqWQoN9STjnFH0Ai+YsbFCnEyCBnHuYs4iinoLvk6UI+4ad/B8LOzx8koGFmwG3r
2Dt4ZQwEwzmjmSUptlpK3okwvoNDQK2OCRVW8cAZw4/+m1upaKBRUHbD6oFz8ZzQC/Crx9DZQMBu
WzWfj87e7iXSAnnEbA7Kdj4H6wfYfjMithUAp9kX4VvTa+oNOAE2Cu65CWMM0eZuKIWmlq/cTjZR
8uwttDNjvSu6VdVK1OiHCoqe+k3Khj/v6KE4MLY9BY6A4pHgLoLIoxoZhZTpM2JGccqxwF9HLeZj
ilCVlmeDAdaZPpVZ20YxYsbMz8vxTbj2YHBZlV4kWXELZjYhIvcnjNZm0/Y31mOjHYL5D2eRaGfF
gadbsOtxeEUrpXkfQM149hAp1QO1RukHbbmXwJ7ObTC363bWkq95TKtiu+hpIE1NCUnynuhQITpi
nA9cXGv163CXUIXklBMr3OeEGN1JOGonKJjrJJLXIrcwlzYDeBJT5wHnBzT9k0qU8wBn4PbFJk1V
ZtheuI9vrsVJ2gChTOYM0TvGQgxpRnH+rReiIgYzJYOZXBs88HgPMB8M5ubOU/9L/z+1qR+OUS7u
rU0baEp9aGpvqeWP/ZTeoWUHJhRfqPpe0O0rxCD0VSjhzan//K+LlUA4LHd9KhkWyq8X+kEVdGj6
B9uKuw9dan7OCtavVPi6lxzdYtWPrzkKYF7e+APErkB8rEaxdbfIuPs9Dgg5Az+YYX8tlMy0XdoY
lVKPC2SXfAkC3XrKz5z8vhn46JfAr4KM0CAitqnsU8e5wccoDDp0CHX89NAynoRjkE+S+vo3pdcc
W6ZWF0O2fmdYmiw+ZtNGp0qh88CMm2EsaBPSp67QxDI8v8nf4qB96Dv9iGR3QFjHgVwvU+tro6QZ
niJpazUuGg8UddPvvopnM2DuYmiCUJBsmmqQVuZQyRuwVGwSrkIbCR6nGGaJIUbkYQO9YE9Bz6Aw
I2PA0crkbslMsAAlbllkmu3TV4rWG1BL/trS9+3Y55GM1CqT3bE0bSzUsYNL4aNrJy5OBYIslsJ9
5NRlzquvg79UHUkSU5kclWs4bbagM4XssIIdzQHMt/Bb+H6VjhNsBm9yMkeCRu4gODRL3biSEkR1
Ev0cm7nHZafudxq3koadP6rUnAPS/QVOof8/d1n62W4bH5FS1havdg2+8SV+XgNQbzT45PCxdMB8
zKHfzoHYKU5Qkl9N3KJjviNLVF1enGA1/bKBLYuwPUtn6vpUVZs+QSlCAfRbvAajPN4DVYd9jUtx
wFNkmXiSXsdoVveoCMqz2wizA0GTztJ86FAfRmSzFmAKQB+XAIU01m5kL6l7RwLYhmeQCbDwypNr
ZSRHC/90EhvlcN+/IgeZP2tApdDenMCBlLx2H2jCZuDLtdoc3zpoyNc0aPLxP9jGPGkmjmQw4bMy
SyZwCsrPK8t2yUwHW+Q50BT/6UgVNrGbjirs8sBixz8/3zPrhBA8qIAyYeSp6cqypGXWKP7s+HjV
RpelA99H6BYWlBw7OQNv5Koaa31nrT5jM352msYB/4q2xP3WwZcmIbzYCKMqPR/yukbLPXEaRR04
QLH44tVbVlO+y1+P3Sv7a1ozlufMlID3IW2oVEP7DeXXC/ATyAWwyWriMPFm4R6NkObVwgrZmT95
nzw2/UHEz9bgeFVSzLUTF/wAvb2k0IOcAXeitfMD4oi6y0OKcQtSizcSNo226uYtrXpNNTLS0qMZ
Ecc7Rayc6eh9lQvOsEjffJFhC5yP4JMEAepdNyOZSvLX3weBEJJyBJUaDN1/9wrqEvpRzIz4HtzC
dEQmTiz2ae9EL3UyNOtp7WaYGwI/NXKpUO+6WdEctw/O8ly6ra1BNgMli9gaK5qETNMsr4sSyc7a
fWMOS6bG4V+8bp9mIIsUlmgNIPceexYhw6zJrIoCotsHr6fsL3zRH0MN+OaHZ9tjywnnIPOXRRTZ
d1tmLISswWP0BWjcU4Bxtdn2NFz5d8IvvjA1PTGcT7Pp4yrm0Ua+suiCBcVXhG55TSzp5saHoIEt
KlYjiWqZnRK1VOc5YIZTJd/UnTrgkqsIfXNIa9p9erhHLEl2VfFep9TlRzR0MLKC4f/PULHu17sM
+AMxx/0i7mCDM9PI15L3ypHLIKo1BEPCIkvKXzkF0cAA43Ub0OR8zHr1eoo+B7ntKlD4lPBvqknB
hB5fqy/eYDLENMqHov2Tqh6b7j8YSuUV7CfTTptvOlwS5yWHl+aoY5o+ReMNT8K+glg8ticP9Co6
NITdpzl6VH05PYJhf3YB5FNEI4gIhSAOBBdQFKuCLuBGXbATCOWqGJYeXyf9I7bmLhIbTxBadh22
oQNoARq5/7Z1LzzjP4KHV59xZiko9gIQ0DR1TXHpsWqUKSz8yZsRVb6cyHZ0csihAFfR+7dscGrp
lv8aT50BlsAo6T9VpIOGjx+14gdCTEjNqVuEweo7K3bKShy/m1jwcB0py5V6ySVHY9yZGouQ7vGa
E1peA/Ihc9p+1Kp02uYNVxXz5L7Ixr4AYUQNboSfp/8VOcCD+FOlXXPz0PjIvgZUAfCV7CHgMico
T2ndQrr/JSWQBZsWbSCW6JTRkYJPIGO38M0tbpRPaj1xWnhlE+geBWjbwJ3K/jAgLZxrSRwHYNFt
mir9ufA1MxUnbuTtMFvjU+5EMwyfOQMfKQxB4iEFK76q2lSuQoWcoVM6fUNaHLpaGZy6nMxWYI+g
Ri16xLSaDvW/yEgtAZKRYDYVv4XS2of2hQcpG6LO/x4hdyRfGu4RPGDqL1FsJvly2fbUgqmVGoCy
HEiaS8E6zruIrx5KCXNjRn21XCDtiHdtgdeR1FKzRN4reei6AbpLG/l0rOvkrWzYug794dT7MUCb
psssYy2AoCSyRkXHdySmD74a2Jjk0pJcSDMydInMIn1tmmNErNz7Lq1e0gokDR+INFcQnr3ggUFm
Ema0/ccUKW4yiJyOyRdBziFzSkNMVVOz7PACXpoXPxDz4vCT9JXQJ82vkcWoSM4UtXRRkSUIjN3s
RSTGZGxrRC/OK7jcBsumwHEvv7tR2P/SKtaoN2OytWJOu3nB+2vxoXm9MKCrV0NupOJlDiKlAJi5
ikrv8eSc/lsNzOrvosY6YlX2LJHpWWnjrtQXZQawYMGIyfHxLLY246PLFnw32vvHKdaNf1b4uOxJ
Fj/z+Gsav5YqukWFIFl3EYm2NTYZ3rybI2jq6JBiiP/bTbNl9oYcUR75tV6uFAbXoWElEfBmYeh6
XspnAuTcOufx0wS3L7D2O3ao3noeDOgyh4jW24NUOcrV3EVY9x2UsDG5JfIjU0KPFJibYhVnvUYA
imc7Xz6uy8ib4hI/xnfsEyGuJNbypaDRXJ23Z/cfNsWy9JO2kpPrtRPuns9sf/XGdl8FZlfaQJdV
VupYiKbnwvDobuZxfepc4Q+9kpiQDdYmZzBshkZfpOGiR8JbZlr5ofLO9fffYi01c5jfAvtxnWMr
Y8b3frIyAgLGj8ZuWGsu3hSgnZIVtpi3KB/uHn9W02vth6YkSFTqeOveRuMbVyRoIknOKSljV9RD
niT/N3jCzpmsecwY50Qknj8DjdMEhIqcPJVzfzq7fUUne5WS5uM+nlWV2qR2PEcZUCu5a5N2mCD3
0MqZO+k+3vMkK3kQohhto3OpZAZLb4y8THGTj90mmcpvq+UFxCfRqVKEqlhCOwRycX2cdm/NZyum
qN4mHXzGMUrMQwgf7RSNQLCj6dApfiVVcDVKckgkPRTbqyLtKumKirletC7Zzif94PgsgXpxW8bc
05maKZqPAUd4aoVAHA+tSRa2PMHnEOGmKpicV0emTVgHpEs2FJ1OPVNqX0/ZG/iBXxBnKsIKPNx5
zjJAoL2y5tsTO0vtk0J+k8PnsdA8gfvW1YTKsCMfDvQ6++ccViaVqNaZqmC8Z+rLdc3ykb0H6ZPz
G1aKNj9wSRDRFWTPpmpJjKe3nlBw8zoIeKhE5TGKVylkhf7n37QiUS7YJOz3Rm84pU+Qolhi21OQ
sFebdslDnIlglRuC9RBlbuTuW+Rz06yJ4koSNXI2XKy/h9NQ0R8+6CAXwFEqVXO4/ypAmSAhDUeV
cq8pp9J+tcqFnQ0BQDA1PxWkqHDsUHbGvjLnhqfKIwobx1mvHETRGsMhXkEPoXjsFi42T2xz3Sx/
ZqMswK9vIp4MIC6JzT9EYhSc7tEB6muX/14MdNdu79KX5W14xiAR/cyKP2yScIgo5040WS3Qep3R
p95K2vbUKWmzsQQajj0WeHO0ZpBMV8mBxNUyhv7P7b6i+903aB/P6ZyaY9ZKUXX9beDWfsR+ByJg
UEe2jGxFbxauYpWCziQp6ttKgc3gr68yaqF+8lmTJsbQZnAOCZCy5g/BgP0R7CAW6V31oF+jUJG9
yzi4yBeNmCiaq8Oh3p4osiWCTc9PWqJoY2d2qJkFEC5aPyWNU9QcfB7+Bm3JsLHuTUa6qDppUSQz
Zy5cPUWO0IQOhsO3la/6Nl7H5FpF+00tDwOqHu3IZB/T1xobUqCYQ/UolBZ6NTFej1zgIkCuu3+D
oO1p3VlxTuylJf010hjA5XEtQvHQXPVp0R3AatBvZbMZYRoz/UWX88a20c4pjpzKQ6hVQ8gkVDAO
wkLN28ry891efpGvxU9f7CKAzF6d+zsA3oP6ttQbJo6j6i3tgy1JcCTE+BVlivQXlh4ohmf9YcH7
INMqo3CRIlnRS3zQnBY9oK1JBQX8HYT8VK6Wg228K6Av6c/qSGL3gSq+RgTCOIS9VgM3WscvcVyT
GKdxPxwRaNrDnpZ6AcZkmOpmVYSylBsMjCfS/jSMpUa2y3Udvvf3pNNqoPzOFjnKwkZS2JUPSjGv
qXwIqNKPbOEyUxiUtFpp0tBMNu/ulwEsLdu1WT082zQJSu/l2ggdkW8Kpk7w/OhWLawQlxct+DbE
7dJgiCXNn31MOP8ov87BwmV7l7mi35e68h9ovsY5AzMzJXJlVkmwV+RrJhDP7vKxh1A2b8mxVFFl
a1Y3G+uSax0BpLZAM9tSk9Tr2NYlfOR9kCiVJOaAKjbvFPP3bZ4iNj+HRVz0Jt3NNHQD2BZrBRuM
1JJ7Pn/tGPganp4EBn1/bWPnPpamzeVZ0WkGoryTGfhSt6IFd6bO7ya8FGspkazRUnHE9NaFKliq
s7jDjT2xwKIaibxROwu3hD7WYp20MpbvipzWDYoBlB+l5BZ8clNeFCveaFs2InmL7Ai/ZckV4G4b
KYkQ8x0qB1KCDavau2IZ/SummCSxbMHFE+NfxgxmIUk5DBpuKPruOyTPalyg0AdMGXx/FmFOMPmF
nVy7gY+nb4Hfd1+CI87IbYQYR44WluzRsozT6c7tcN4pTrjG1g5+s9R9SUNjU/sgHHSLMJEdXQem
QPQ19YweB7u4bCtsP2e7ayf+C3vuIFTAkC7JkEjMd1eppz1agDbRaWmGXl7nO/Vpnp/7cxvBda5j
BeCHM0sPw+Ea5nhRTN2fNBZ5ZURiqBmVpsV2jvdb6JhSBiOSdjG5BZV9JxL/QLTvjMDCqUKUAGNR
FkJw0fL4d8wj2WULhy/axLazMm1tuHRbD6pOuGEcKRboQ1nue7LnkTIHmo5wOXrUIzIAsuDQ/81w
7jCWvdOqMzZdLA4rWG9/Zy+LIO5yvuBct5R+1obREnJFsdcrqKbnBeH820BgUz3yNW5tNKd9g0B3
cZIJsY3k51eBak8PgMi1JJXnFnEGlgZhTrdkHJ33oDRWBL+7ywzjJl67Cb6Blb2X/RF/MAPciivw
q3fEx7Kb3aWR0HQUSE3mYkeFeBfBnu2Wjmb0/uRHewgN8/ljuSanh62ClnghvDGqPrTWBCbyytaZ
7vOj/SW09IMU+Yp3kf6sqGIQxXjR/NQ2IHkH+3sa5Ae5DyY+4H6cGGGjpn+6GvL1a71CePXw48pt
1GAog0GTCDm/PlzIkzaHARIE4VI3KL5DeJu3jOIhZrO6q6r1TzJtwc60F2SCnkntiHmElcSLRuWW
BhA1ggx3HKQzpj7WZ2z3PgeS4zN4rSKR9aMwMwGJNnqj6iA7LPdeZXj/1UkNq+Oz5lykGJPdCFoO
YmcE0IcV8bQAksrdjRvVIslkjNfWMjdKpMTGtAZgxf9uJdU9RoFab4YREd/9CzqF1ZMLOeqsOrgn
eVp7bKqUN6jQCIgUrJJ+zfSEv9BZOj+iy6wM6092OB0ocGpfHCHApGjCrQ4Rx0+z6e8VZAjsnX25
jra1IoFJqC7Tko4DIMWvnIVAPXsI+th+eFTTCXYpXes/f6qGLOezTRIhvfwDRV19RLtQDKfLe8K/
jZtX0ztoILkY5Oazw4wyTrtBf3jXIKXc3N8NZH9RHdOo74oTsEdgmPy7pRyeARlQKN0lxeR5QLnp
/TDhCxHXHsVO57GEDzwNPFy9Juw4PcXsNe4GYyfcFQ6BjYf3C4scpSLEJjUJw8/1WkENpoadl9Xw
2+2kVHGEP9MSWFO9JLKJY/Ed2ZzcIRDjYfXSQ8XlEf7oReJws54bMqU+Yv7HdLIl/kzxmra6/f5V
uGR4OiU45rHvDOZ183MgZ09rywAhcDgWGLFfl5JxlBhG27r3CvfOtjJNTNFX0zG5VYN/XqTeLlw7
hp6NT9qvS5FlpIFNbtlKxKQZgH8Czk/cKO+T3UoD06MrWAcBqbAEOcfZ2TzqyD9NB1dk8VGWgRJo
mRCq+6tRphvpI3FcadKMV90eVyWIspo32aaeElgsMh5gIQqJdV7q4zEJC0iy0x3zklfCjNnsJWnr
RUGJe+AhAZB/vSBn+FeBegenhmrfjpHnte89yKMLi54vlwhcVbMgAvTonUNLYVzJzKuEy5m8N2Sz
wV4n1BHZRm/bdGUwVXzfAfzzbRNisw4poAVSvWZQys3mwZSKlNDbPLunJjFmnR+HxJcSWOrqO0JF
6drPXiuL6o3SAQHGdWDXyO4muLpLdcV7vTuvS3ZmAvszS03tEu4fujeq8zx85D7QROY3q0bGXsM0
qwULWBjzjH9lYkjxfbobmym0Lg7O2HZpTHfSp3+9uTxi44lfstZkX8LXbryqmzCFa2+qJP9mL5gw
pyxRfwOJITJb//TDLmmI7oe+zS/QcKO8aRpc0ahfnEdZk+1IWnJEHE1qGyECa1K3e9oAAILRnbgT
SX1kDQDX7416uMPy3TMYBWaByFX6vOz1Q9XfKmBXC/vfcKyaPIRETdG+bsaGnOjQB6pOJ6bgrEPx
w5/THvv2MGYvAKwtm6l4MGx4Z5dZyDCP7o41dh0VBcjcZ+sDVEmC/3Hj+VoOBf4ZRlQ5xGv2UKQi
/X8CdnAuch9f54l78BJ91zj7b51CuNRnR2Q3TVn/d5d5sNLTaXMXHAVXU/rf9c93Xvok/ZHJDXgj
oAWuV5V5W13S8toi5UfqH8sca+u9sU2JfxOwksjkN6gKJhamnNv4huzO3IGeOaA98oSLBB0ph7LC
4JSW60VEmnJ8aK8xAOM6P7EPJQuTEA6NIAONDtUld/VmzmE1UjZDRM+p456LxmpOyqHeOOVOOXWY
J1WEafeJKN5EtTnxLCOTvqyD0bbQDBM5Uq4F41mLf6syDZujcMTYWSebxXvaBmwgEDObpG83TBD0
Vumgpay+97+6XgVTVdshhH4q+Q9fwY1T0fvm9fy4yimM94iJxtIHGbmuz5y+QhzSNaKVw6dwrALT
BocASzIBX8FRvofuPlcyzt7JFVuANqF8Gxml4nixai3GuOmhqBfRp8F6al5q/81S+S+fBGTvUNyE
QkE0EHONuh9jxJcJQ5DnfLwXndhDYJkzxXy3ZbO3FcJxa5BQ57zOqpKIjftvJB1sH/QEYECBrxqp
nOjCK5M6LlOhD1v+kx/0LUUaMdAqiVMeyO4SyeNRC2yh46wCeJVgP5iAchp6diV6XOXxoUU7yuLT
7kihP6HvhABreeD+VvbBBNESzr240SYjVkJcptQSuvHFr2y4xiamu7jZMIc4HGNseBfBcEaibXN7
SJBOGUV4EGO4f/ma1oY7VTndn0lW2MpOMRndvBTt9gccsFLn72zwPz+d8CdLpHZhJiSW5Cbsu/vT
Ll6I6LzYpmln3DH0rVXUdY0/MIqrEaLpAvSRVH37o2pG0A6FDi/b0EaX5NvB7j/TIxeTCBTyCcbZ
uzH2gFwXCmwGzit7Q+5DodEgExZf7uQEzE6fKu1pqDNX661SfR1weUx4xaZktYN5o0504Qwj52wR
jlhb5ABoE9puNcieETirljS2+sCoVpq7w/o2evz560Dp5N54LVcN6gqQ7zaX3+WoFU1IKWI0hd/6
X+O1GKZ6fDf4Gr4D4BCXKt5jIEa4AKIqt55u5iNINR+mcFhJ97oVb3A47vJNnsvoJTZkyo4GxNGV
wCsUEZJhHP54F5ZVNq4jDc9OPQZAwM4q3bMQiTuK5s7UttULYOdmWsdPvR5k/dGpJp2iOqIm70XR
MLZ4gvC8aD3CehOTBq/k2Dui49ZEKXHqsGcgwX29wCepLZwHPv6v4xgzSjXGOhjZlZ1s1YPxX5og
hcE9yQrbI6dqHhDWbTmqrQGaDvHwcQa6q57IXU428RIrUdQEMmQlw1+6un1YyyGusvQi79MnRHos
1LUozOM4Swqpcossdr/UXAPSfgoCBIfJR7pCbyIkJl30kd67uforHws5lwwIoQb9Zk3PkoVpk7u1
yWom0GgaBiTfYSzgKU2RKC2flulqLfjUnJJlDHeYDoo/JPXXST4AO0eegXknnY41R7bo7PUqeSvc
jAEbY9j0byMhjg01ZSppyakZ/fVp+o3pzTjHmLcaljaNz7+5vY8gSFNj9GU7uM/WqHEaG0v6IOBF
tLFDEsyHacjUyq+Lc92UvZXHEyoCjFnlsMya2VNKilmsFU9ACzRgvcNteoa06Z/iTj3CYTY+fsI3
L6Gy8h04+gMbxMFz/ZBpFZWqWkqsoKVmp1b1zHRmvMzda+AzZYJ4IHZuNeCFmjGNSlDAK1NZtEla
7HvDi7Yl3Q+muxrLtrDXiPrwT4Vrsc3xucDOCyY5QppEMOb/DLr8TbXpaeat6Z90v1czfirH6Bh5
oPCQ/BXapd/5cYMiIZ9WBgLdNTk/U2D+nl9aMu+yjNQU6DdaRUxSK5AmYL/jZwy+AbinoKfRqI12
AfM6U4KkZwE+B+hCArgw1fcMp66mrxkstASJEL3Om9uTGIoufi1Hy8WP2+vJRjOv3F69GN3i+fja
nYdqgXcWqzezrYkEBGHayAFbkH8xvNnH5F5tXNNrh5NZlD/vWHRyXy4YjypPVbpGbqK7vD1wd8q7
EdmHacWzaAT2U1BbL8NYnSYUuQsIGeN3GxSNvm1oHzJba9/t3cIpvfiF7jU1cnY167HIMBoypaSW
TcKYcIisD6m6e91/p+988c9VgVFIc4zxZR9KK4gfgmwopYIRZ2wqdD9SSzFaABt+HeqECCM03DwI
aLgCRYvztdxo9gRza7A/iwnh//Hk7CeScgKGcycvl+3eZrEHwFQx1TRRXMRj1vHcHq+IUK3pJXX/
lnqBtet79WxE+Arso+XVK4Reyci430pqvhnYGkR2b0kaVUcgSIaSv59Gq3ToR2qYNdAMBhbHiwER
qorxMZKxO9u09LrQwVNJCgzDA0i33KkqqAG+gzTu4XwRXLKA4mEI16pyIjcf/HvyjiskK6BohI3P
9XSP+6t79Vbl4o8hh2QIA/oaC1L+AHqCG+sapDZ2wKuKQfQSIfymc+Pf0KTOWCZbH/EAsii6vLU0
v87wOpSEKA52jOPq8ie1f1vrBbqZOhgmOS0aEaDNysN/Mm3WVQMtuvFNTStHbFmvOHvk4ai2BO4i
TdIXMH3DUW1ltk7CPCBRBZtuWQVdLIXIfyuYAH56YPeauYNeD1IjwtZrjS1Ga2aVya7567rFq0O/
eINPY5hkWo+V6fZopcIJJl2SRco4F8v3fBmCmRyjrdJXo2kNGJcst+7xleYdY//aApTF1EuCXiVZ
FcdIRzAAdFV+5x15QFvI1JLWoqASmETW6KoVSVS10JgXWu/EZLk+NbgIJPPWE6WfrpVY6d+crCOs
AUZuVKTpK+olYzj6F9vHApv2JXHxVhlsYzbukAUtxGAe2AvCvjLRRr6G3dAQeMqDxyomB9oKN84Q
VvwwWm003uu5kZiY8bKkoAGuPqw4jDGz+x+yCC2UtqdO1EJMo3vDPfVwiTjnoQ0iyD99Tm+N4gET
VDh1IQBDL7CdXCNHQZFeFUU39wdsWn7+n9QYlVGxTgZdE+zZBUvGTzOZXGog323SMb+aMNjKwyvx
NKWTyuEhOyo3r79j2C5BUs7gtvCn+DmnPIckLT5MymzpTuXXigXCSnq7NY8F9SEnRoRfhUdwc9Rn
hZQ5nM2tjGbcSSrZ2wi73yBwvwjzuRhqrCj+Hx86ISOZGfuS3jlVzcGWHTZ7qWULNdPceTK/bpXV
9Amfk8z4pD6RXNIu0BbeDl2hakD2I9Yegy82Yt/uayYfh1iWalQxdz4Gn4aiKq5LlG0SNtG3Kv48
yvVp/3RBem2j1jIV2rUUrWsovBSCcw8sSU+8L3H/HrybLr5X4Tqkotqx1Td5/axjcO90npOfXYlY
Vy8/MwD+zLSTQWeUPHbwJwZDD5EkydVuWexO6uBJkJg6/NHqv3JsNDWotjlLKcTNPzROxo6cDp9r
Z5UFbzyJXQCoW/KesNfPyyKy2oNaBp23N83668sqv+DeBUWnvWYQnaOoB3XSn19SgTQOkeCxtvi5
9t78F5+/p+By7nOl8TqBWA/iV4eDEVg0aDEBWUxZQGDvSOv4lu0Li58OYDSRm0eXN2AWpJ+umcFh
tXAc7hj+C9UK3Ytx8HeUeJrw7KMfuvApZhOI7i2OAbAYqAIF0TSIZNRmiSAKLCFt9zeaIrVGsN91
v0dkf52Q7PLdkUsKHlqTWoPtWBZct1/THUI9zFDscdvUq3tVbBz08rGYXyChAilLtbsvOSeIXRQ8
0QtZFHhLLFgflTtWM9cKbIOhQJyNa/7JtdKC42SSwUjqtlq9N1i4LxNyi+rWCVV8jeQ0nH0AioLk
uaNfKHa6mAXkoieDaeakShglcutdmX5EiUphVlnhyeQB3R578YwdvQ/qnbxMU7OyUCCQU5gewhAC
18S4ofpASxtglKT71BTKTzIhipGBzAx2HLFTo7aQpJsfcfGR5mr5waaPrN1wp+iBKInHu3/WPoHI
VK8PAoYLVpJgJdAjSzk3JzLWybp1UljTArheRnLkuUu4OCVTJx79To0BqhM+2TYKeVoKUOSSUALs
nRSCr97F6GlimDRkvTCzLaBdf+ZG5OyaHOVWe+f6BpO+PU3UGEwLbf5popBQcgdlWw4sCDDFyf47
mAkS9Sac/GFIEq9EIhzk6WggffBHScIYCwwMpox/53olrm9CMbvdgmX5R5cKKLWhaAThT/GNJRk4
tWWNBdbQzMxYwnxr2RimG1AFMpOS2aG56305N7Ny87a644Wnepb8NlpQd4borVIqEHWhzkGso41W
SCJ5/gs1Oe0KaSCFiozaBEiCpYyFI+k3T+m6v3pGdSDzRW5eh52TUoRkLmuKbs8rnt7rpIe7uY81
xSWk+mm8OLzDN8UIozMeh7JmWoC0YmkmdYHtUkgoDj6Uqmdo0Lhux0ZL75peX/NnM9hY0+G0BMO+
0p+LVlJjXQqUTfqPa9YmPWQcWi5Xqkwlhbn+F02YVqvKX8do2zUpK0gZN0XWSgB8byAa5PUe4YOm
aYl4XpiaWJZtJfhYrQ1PXqvMT1dMf5/TNcSNQVPSYmlrQYdervjzQnPexb/3pU/BNW2kQXIk9M05
Dzsq5MgZ12Xp+tAx6Tnif9WJsNex+YhDAlS56Pqm8iTxr/9mPDjwr4z4kn/MGWnN+F0naFO0BFhw
fMc3n3SiTHC3FZ2OGhzZtMAx7Gku7dZX9zUFATyVONza4D134LJY/yC0PsWZOjgsX40in4rzUzrx
jM0sGVlfuQR6cMckcZ4EirqLZxnlQySFKMXiyRogZqzLhpL+D2IijuevTejVp897D//Fgs+JjF2c
Dq94VID+XcfddAH/zbR1ONFCWrNXNHCNMpBKyFftDzbyTUTtF6xkMeyFXKdxmQTPjAmJ7DBhQ0nv
ZsUYoGeTuG3LU+AXUtqv4rQzVpd6oCtsyhgPTT1e8Y1TV/+ZoEaoG5NxTUe5od3XkENBv92INns4
noe/jHeE3ATVgCXHXOeFbUEccR7G7SZ1Iw/5Or1/EtXjg3LPiUWVgXfq7y/TtHxI/LNuYgd4ygVt
wHHcoplp4K2p2P3bgYC7aQocM6WfdWb02nJgLKqp0lCttb30/xew9UIKWDt2s+OhnML5WbpjJBE2
4oqXvMmm31FjC6X4STxqhoI/+Ff4U4PE1iaeBBUeElu6k2IYbejI5BLetk7JTu03rDFNQfM1JugU
2R3qXnuJzFrJ4cJThps9vytaKW/JrXMUadKVOIXd1M7bZ0cDxRVHZpXuquKEa1jqUX0JiJHOk1Da
WPi94fWndn3L1N+xT4XOkNBnqAlolSIskm5vG4J03tmbxI3dQE3j+vuDtFmf6daj/eUUEUETBdO0
k+UCFBqzjnFD/mUarSMZl+MjwvMBHdixrq3V25xtaGJuVwvBT/9n+E6Uaj73rzUPdZCWsAw/l5sD
bXZjC4BLDHN/w8FUwel5uNsLan5/+buxBjSTB+1IBSd/PUEENCdWqmH48j/a/8f6cGJHRcmcZZma
gSpXnLVCol5IJQIbo1FL6EvKFaK38ttMwdelZwQv6Dd5ZdivLz+SjmoS9Bhvoh7qRywVzz6odWNs
Qvr44Cs0BTfG7l8CqBqgSN2GWoq1S/cTJi5W/j3fa5WDPuEK1wRUlOAIk3k8LpGlU294nZKEimG3
wynM/vi2ZP8oK2Ai7hBbBeJnOrq1v3wKvxE5n+IPId2BKcHPM1OqQwLD9XjjHcjQSUDIn28ajUs5
bLLTxLvWqgnL3ISqsrWRNgpjU9s6vkG1gXdKH3x0iVyW6dWndCUy587uPaS1cICoZ0nPxbGVjWPf
nWZLJoF8mrw1bJDG8XZ+JBIABNU6QLsntUd9zSeuyK47ODsxZ6eB5Cz2QCgMq85SzcDi0trPn0pm
kXLRR0LWgf6jTSw1LIUiIKsAcXMcZ8csef/heW5G19QQSagFz6lM6ef31m3dHGWyoAr4KxdWoc0s
h8KyRKBkS8Yi97L8OTHkk93meOcgKn6grgtD1i9FJ4R8++uCXcG9acKylfsux93rZ57QRc9E7iYd
3dDno/fEM0zwXtiQv0oG1GGJD/ivPkbvwuz7ygM1tAF589C3CDrfYFrN4SLts5kak3s+1N9viRJd
tkI5RS729SVuSMDxFOtAya54DMWUWOI2xyZKu5p9gZgcaBJ+3o1u+9KyT3HvDI0/cSg6HQ69i6Qq
tArZpdgnOXRcs/5gpa4NhfeiZVwIgSLsZanQc+SX8SUuTXGWqhnU8qKudZupcnqIZj23OzxeKfGo
ZXypPCqTpL4yWCa37M6AMA4kpGh/MyLzD3JDzYdyVUqD+eguyqI4nD5R8sd44wbeRbpZ8uI+mDw8
L8XaV4OIFiHiBPK7cxmW2WC2GhlxuSF6shEI/P7L2YZI5Greyif1clxJHFpvG2Ufwzak8qVUtO6/
fPtPABFVBkBOfE4cCgpCNB4JC3QcLSyPk/8XojxrmHJndTy3RUSdRj95Mbts0ALefs+Fq8ZwTVqE
50O/zowYcChY/GgLXT0d0q334Ikrdz+0OoU7MijHBD7KwQKa4KGNMmNNAeRJoIJjtvUX04G2XRId
XxrETKGyNcngKkd1Cek2XYBmytgERRibk6/yyuEvMEa5qELRO+QH2FpQ3Tt2WbBKuWUIFmif0N3a
RaI5aipdbqsw6x9kmSw/rUbjY3UF+j9ijAM93K087VxS/P5GdHUx4UFuuyOO7uAuzYbMJkPF7gSH
ijKOrNT2wHb+1LTmzX4CgoD0FaIcGYz3x6BOuvtexteq6VaKb4neoQiiDXT5kCkyJpI+a0t6XyDV
4VcJTwNQIHVs6mpU1YDhMH2QQDdf54dZDhk+A2N1ksJGTfJr1Qf9F9Ca5bsHwXCRR6ZwV7OTr5dt
/m4A9ndlUWpCT5ohKNRPy1ZnlGhmrcv6nAWeK2HgewQ2wY+xNKcSqipqm0OJfmh2GftpNqTHkLaK
UShKSkDkMIb39pB0J2FUKXQZLIRLGnGsjpwCzwwuSKsL3aMnpl87gmWCHO450oUu41ZD9IKTwqs9
jKO2Vq6JgFq+49YZ7PVzwbARMnswtrOy/lPTG92TKh2GMPhd5D38ydiIZyF43d/EHs2+dOcvfXfJ
fXYavMEeQGaj3TN2V15NEQDMr5fkZj0YmLYNStff2SK2Gxhr7B2Iyw1yJNMpc8bVt8hwVPxbBK03
iPTgcVx1nVsQzBYRiUVAYvEoXVuHixtnxttWEe5OQz0TGd5t1KrblwXf1dG2c7YhLoViRBnApWrr
Hk+cIwp8q+dbIFtDakTPOM3ni0mbUOwfPdVyavJhw3fyUCQfK3iUjkp/o+wYuhFer8zIU2Bf47hn
ZDGojxXkNgH+DSNWQw+MtKrtCtx4+atuaoMX2r7ncWhNIoTBZ/7WX5vsGTGcfijFmNecMPBXv2aD
jJ1nwaPg3CbgoK9t7exNXIImUNri+RHkTsr/XyXbAz3pbq0vT07D+y7nZRlyV0uA0l+sdR/JzIAs
1u2AIXOYuJXazzUSK6HIOn0qOXbZc7vkmiH4jPzkNgA9I03x/xKz+RI+7viZl0IeT677jc2zWV7r
Oq6BPgXLH95aJmrpNaRN18DrtNonK2157BKQP0cx1vxne6+9ypOK95b8M4Dp0M2MN617t4bCYLYR
/KKv+SyEMLpzdDkEBmwaJJchehaFMxwyUFUvs3Kkk02LwVYhbYfbvqOgkSiaT+rBwd+4hQ8sQpgq
vqmkZYwoWWPf2Ns/E2DGLnU1dASP7XChimaQzTiVcg4tFe67OPALF2zPt7VpIKEVaA+ORFVkMTo8
hxx0IB2wE5rE2ovE0K0iF5wUqexR7LSaxi36bUieuxm9SpI5pa2SaVpS3BMYjlLKR93cIPobvPJT
F7wM3HlNY3tLSHLk3JFszONoNefyXa8ywgZsNNms543cbr4EyjUPZC3Ng7ZKcULHrsaI6sKjTQET
KoLwPV9tDc1rR/ztzp1W3rCfifjKl3QRlzWYgyMh1UaZZLH1QvM1SxxwwH1atbOSQrzGjsJ4NenF
ezUQvq9XMGnSC4pNi3K8FlDRjd2PExnW52VeEKusKYDM5feYWmBqCbbIkPvgTFhQD5wZ/GXGNlmj
9RtZWuK+IOMm78cWf3CbNLjntIKipI0oSPM9v3+jUKwODkcFQ1YpFCResz9soxzENpDJmRqls5if
HMWQZSwxX7pyUnBN0BDvG06mbCPtstjp7ODkhLari+pRSWCOaCh7V61Filn7zDaIgotT+FCZAeMC
igAslBTuBdilWaONg+iFn/ouVGr/Y+Yjeqwj12VOqgIdw1uRMhYAkthOKzCf9KeIlyhRzyEAQKha
qV6bgcRviMFZ292fUG+YbzYXwwvWwkuybr7xpNIenRWpwZiF0Zx2yAGSJJva68lRFbnYYL9e/sqR
Gmxv/uWQcfUEQpHd+9fee4qiCBZn6fopAKHJiX35L7vwvJV5tlu9XCRhw6FT6IuWUOEC7Bu1gJE7
PR3txrGQfHc3YR7H6VmIBnfu1rMBVaQ4p+rN32VYVhuAQI/ivtvfEVX99jAZ6C0X8XXQPjI8qs8t
Q1b/qLFDuCOHGCnt7F8mR9bNq1UiaegfkbVw+syMpqkyu9axKihjNRZuCPiwiBMdj+SXSReWBFI8
rWew59mJnAaQs73l5mBPvqDHrGb8GpEpl7mnaw1ghmuccZ4afNS1wapBu4tRUdI7vpfsWUzjtAS/
9HrHkxBGbTB5xeWZF4XykTiIAo3gQ6QI7ovp4CG3nEzurpySSXoN73eVI+NuqlnLkoMREiHx3gFm
p+nr1win9Oh+uAEPDZMWDi5yve7v0gKRjFzgKdQ6py3hd0fBW1kQqI16i0Bj5zwEqXAttEsPtWo0
9bZeGfJFK9v6WWBIbghNSungQeiXTXWKtH3Xrs4sAgykBXg/Nyd1FJRaSnN7ZtgsDVbpn+s+/3Jf
oAgJik+/06mzWRR3mutrbVZcxzA9cO2cz3VQtcH6B6uTcAnwXII0ieapEAxIscgXDlZzvX462eaz
1MWPH8yrkXaEprtg1WtGjA6SlnYSxxYW54T2Bm4NDWhxsJWtdcZdpVkXeuQF/BsYGRwViQc5/nrO
BGrX0Ov3NlWJTvXrWVkxqY01GjinOp1kQq0Irt87XH3jKjFDljW7QsAw3+Ri/Ut6YRUiCYk6+qiu
+clzyuMQZXuUErgEWC0xq7lPcaQvvbVlafL6fGoLLUqeN1YCBFgGV7tjl7GTuGhlQZDKKg2porc6
23iJb7PcEf2M0nlvC9GuQDgBGH34QXlJgwLZH6rYlfLEgcL3SAoKZQd+tVD5JtUqQwXQKvx+RlYY
3gLjBhSv9mqpbkDz2EJv3fduJqsG+cfU03DOva2eSG68XPL1WLxWm/NmrOwOL4lMNhhDoWXdR+EV
XIySqGrHaM1iKxxtmM1MAVI4qZ82ITJOBo+VDN0Pc1oqD8VOcCYcWT0AULwYfYdNqQiMlNMKThM1
AUGaVdNDACC+DvaYU2rAI/iklyIIX/JYaJSbtNfe8eXaimZbc510Pk3odMrZveXBa2pLltQW9jAc
ASUBuZj7BVNwHqDHEXlUjGKZOsKNrpn2QDHQnVriT+ip4gjCKR29s53cmHS7rtemDhpSuispQthG
E7Abdcg3SkeeozNYuQ1hD3JYnaOm0L1U/xV9ik326+HORxBrnrMI2eifLYBU1RD3NWMnlxr5h7iE
HzjyqdZYX+Ur04k5S0NtVjatMqUOhNZaFDELs4talQfuSbcpVlI/KWaEy97NRBttD+Y+yTKo7oO6
DUFuzD2LulhS17SUACFBdXrpIfWBlpEl+7nlWCtyMIWBia+HmWAwKQnWIi3qCWG65cGzrbXgB8dM
EvzFt4R1jaGl4wIDIIqhy0mpsraQaWANwCO1/gViV8IL5ycWf5HO/D5bjH4VxVGvZ0xKGCca63/H
wftzUD4yZvw2kdQdulwa+lEl3+wedSVYY06R2uQ+dlnRjW6WpZje0gZK9G+WdhYi9WK9SJZqT4Na
xai6OL/2TW5R2MRo27PRqReYQjh3gV5do4t7gOmVOISn1TEF+jz10d0p8dKUWEMJbeAjNUA63x6h
aNXL6SmnKmF1uZvUsbfYqgDM8/6N+o++ydwSGG7809kty8wQhQ5BELTEW3FJ9lcnoYn5da6XdKkn
huJU9qTHbND3UQb1Bx4VE2G4P3NaDiCRE+wNPXljPfsJAzaHmgwCAmZeJComd0RfO2EjNKXFloA0
Mt/SYt8oV+K6RrTu0rhrI+1tXATAD/RCO51XB5xV8eQ37Izy855ZXgKjGLIVuJ7b6Gz5jbvRCKT6
EBNFrIqOgozGhj5Zpgfc7ORX2nrvh0b4QU9FF08paQb4OMyYmz2B/KwYSHQyFgoPacJKAN1X1UUz
tAFIXjNCBG6PAgKKBxm0GROq3IWVlHTTOj19V+rY5Vm0BnoLvUq9NsMtsjcpsHVecjN+3kvWu3So
mDz+JgbvNOQKPtGFCXDuFDx8jHIrRnn52idCgOvyaMMCQDD6fjdwD/lQbus7jJ/cNEEYYHuEcUwX
5+YnqAa4vatqWoO3j6RV9hlsAz2dVCyVqlQ7TIIic182XM0ONp3sFVtq8oONhw8GeX///6mGn1va
RNEjq27KdGmH5GbviNcBnFeYzIDPal3u58DL/SveMPXVXNSOkiKfZhFVXyumSnahFkoahJB+7lEI
TePebF4Q1dOkzGmJ6DyYiz2wdFCiS3uvBJqTJT6bPQW8COtPkOGjEh8d0tmZklgdxkYpb4iNlftv
mecuoVq1STd9C4UTFJ3tbnLfl07P5raTltCCqfrYxTq2M8hTGCJtvpGUIzGzkBYEeVCAmvyvYyjs
YqPwOORccPtaUPiWcB2eUOSPsOj3kOQFhk7nhV8NAZU2VUyglzfUzXE+kSQgI7G8sVAvmm/MDzeW
nyfqiTnHW5RQbku8iDfnkG24175vDrq5Lo/PQb4Ig974U7Ils9cgpCAS3dG2YM4XEohCLzDJtksF
FSlAD7OJAQuJbzDnTuVb4HwIMyfygNCtXfjzZk2A4O6yKFZdrkiPEzw9G90YzqEOlmiVqE6Sv9YC
5iYCsxSqmEMd38ysymojCx85LFaFwXzXGnhyXaI8nNm67v7updAWEt5DNvN4um/J8hQlpa1gY/Vp
kgCjiOC2cksOTTbpTBeWAgf37C6pVxuWzeBRIPiyeWzo2QAEMYaFbdgVC+8LIupq2DOezLf/ulXj
X80jbvD74U8RfX20Kug0XVjDAeNQ3DndbO2XNoKWV13t+mR9oU3aGukYcAjJuSmwncVjL+akIYZ6
WFpsl6J3xYkKMWs6T72hA57cRszAK2GF2DoSr3jkLcYujsJ4AEZzoAmIOy9BASEpDMiv0BBkPfh7
RrIgyFqz/laQ1Ot44q8dBqYg3AGFcb54q51n52LRyeMHNoZZOqsOQL4BCZ3N1cUNASJtdunC4zYw
g1wc2ZKB6vPihyDWx+Oy+HQ4S2YR3udgJpSLKnN/QGcpkZdGdLnHmwg6WhT1oYChWix+UdXVfqr0
Iz0IWc/hKyEbZmiQ5Ade2l4jtsDyGgwmPXVrMFeW83sp6XlnCcAr7xV3hemfKfmOTJxPCdsRb9P6
7aIXxDbQ7h19RLb/m5pusFTAr2TWgzF6tJydXO5S8XTrL0lBkoPqQc0S3P6+jjFJOvYfbhVNmhS8
9V7KtdN6Qlx8Rl7mCPJsQIj5N8XlzLMH3XeRBSC2YHHnVdjRkTxMqfPTtzOTCCx9/Ak49i2zEkS9
yjt/yjo51s3W0PVnFbYVgKbMokC71ORFSak7IEtdxS7lQFO2GVgat/OvAg7TePxG7C8c1+EGguWi
CamdeDtLA2UZwKGJPkx86jsSEByqlbt8beFHX4/24HvowZyDk428swBd9qwx7YzaPi09W1oUVEYC
UAYKhRXGhlNY+K+GmuUkhG6FIl3+z4Xoly1tQ+0+a5p9p/aRFVNuw+LEHL2ET5h0ZcIceVuR1opm
i7R+mD+yNZWLh+abRvw5hExo9lCbw13psB/gYuFNiflyUHbmzloA331woAXFmWKxKKGAkyOcYL4G
4phI4BFdvHoAoTrdky4dyz1sSmcZvPWgTzO7JutBMvbZo0jIRtmHA2rzTg68y6/rEbOviyg4WIrg
duZwx1G+0WRiqElhkl0wFgS2NWMhiTQB7qflaLQ/A8qH/ZB9ULr/lKuJ26aAqzv8/mO4J5yNU8y3
FeFPRpH5VLjTWjSU+cREgXqg73YVQrFvCoWF29unRSKqxRp3EfP076QkTwRGF6huPuFkYFbhiLSG
5hukBhYbPst8NqhzqiIryIDKsApFn8hVVdxXKr4Drqs1LI+Bi5sTJKC2uzx/MaxgTObG8JrWAtot
QnVy1HqTmvRqFCn48a+2nSpDZ+b9noXmtozsFOXOYeS9kLK2Ms4iYDNnIe4oc1s4yBP0skxgnXfy
/wlynl4CWKO5F/dApehAZGEKnHupZKWkvXYFLP3pWXwLUVhU2H7w/DvS9HuhyYHFoVtgYPeCjciI
au57VIpW2YSXAaowCdd4owEPK4OwccV2nAd1VUcMB0ZQhLqFEDh0vJs7v5V11oBVisU8fpiAsbC/
5rdw7ETY+/4kesPBJGiMMv9tl2eyaW/EFkKfmcCM+/VVQBcw96Lb4YFeg7hpxZUm6dSfGSjGaM1N
E8hqyXUrIXxQWhoNisQxBY2mhiAGOQdsybm5fzPONINhMOCSTdbhFKNSLaFMzRaQA462e8klDGCG
nPcnO3xjFihHm0TsZ47h0E34qfe3YoRmFQtO9DETtKgiYMn0N7c5ZH9fjqfQuwu6ipQ45vOI+86s
fQsrN1C6/SFm79yuKHDNV1lPqiLCrkhsQtJzUYIbQouAYZcsAmw5MZB04yc6fVq5hA9ZLBw4cqzl
C+vQxCJ7HqRYqEBgMyAaAo30EJjLWt9lLlo0I7HxJNeXlVxsBty6BnqBP0xax2SF1wimwnT1DSPk
F8PlGwBeJnMshZH8u81MDXENwC/0LhH1CyUUhAeoooSXN3hthye5VlKanHiuBja6KUCaX/TIAGb7
h3kwvllUMFKqLm6Tf2UjD3jk71iNvp9MXavDhgY854qXO8+3rEvtNZgcAo+sh/emEVv+8LY61Fem
FGliywWERsJuzz74FgZNtfuRhXv8v8rSdDrhC65nynnKWqrF3/3ZSgwMnbGWpnxLYKgzkVPosIPO
YOp+pMBDVSzMNYm9PmarHlB5BGNywpuwN0lHbFcXeOVR1Yb9UIDpGrMiEgsPUV12XZSN2AagSFKf
oSqGoni1WaUKFx3+F+Kq/JdYs0YMdFegPbie5YXox+Xkf5auusqE88ekY+iT50KF/5UhF0R2t9xt
/Mr20icfLbJIq61VxRduaeEFtnKDQImWOUQiVgJmXi44XvczmjTPVjpNmKCiUSI51udF6o/6tY/8
3De5XJKxHa1DDjwVamMrLDfGsCXAkb35eM94CptjCa5hGLHvciYrV490gGWAWS18++ojXxHw7bRR
98r0GEBSIwBwo1IJ/9YaIutqUJUuhmTgBfEcQibA9wwIqATk/SFnRA9kcptSyMLDMhB9cn/c31MU
B7r9fb0OoZO3cS2iCl9/wuc8NIW68UsrYZizk2UzYviU+F2xR4XHFpoV5aWfVfb7rodOxIwbprNx
Rw+6aZIKJ4mRrqn0UQyxIwOKnig0ahP/VsRJlqB6LG+UKtfoE/aHiWPxMMhpu26NQTqc7dmAIo6V
5XJHrKrJ7qITjmnKC0YsjdUig5322W+iaVtFcGdS15uvmpSk9pAGO2z+q1UCsx1rLPHc6IC+WSah
EZwVCyAKa3Q5n+mBkezwNdFpW8XDzAf48TBGKWaVBuP+fCpkmneO8PnLYTW54vrLFromyMPc7lhA
+vuojKam6Db4Pohne2P84/iXir0MAdl6BiomMNUD3RL87cAKwVaYXs92W33EjAUrJx10oaLwtjb9
XDWYPrXRV2TywJzKDWB5pgVv8m6Tx1r9IbpCoxLK3AlyUb2Nrnr9rrpPfp6S+VhgJlq173AupHk0
uduMaKxeHhwzTvRhRzgjY0N7t/vgydpc9fC0Vfq48BgVUUPU5vNHqMA7edqraru5YDmsTqC4y+R6
LxLx6hqejL7Ws2zmMS5zLrJZJ7rJh60OX+frFE2yyhKQBaFhisXJFagqyFT03fKWRRtF2EMpZTZM
OsuWgWwDaw4Jw4Z0gCgGk9ce+FDARP3cklsMetACM08tah18RfDnSIrI4xpe+mbinA8lnL5u12zZ
+4aRFTT4Nlm17A84mnLf7qRVRZT9g+V3FKRbMNL7IcBQy04iNJOxPSusOY2dt0uh1ytjUKfAvEEF
4qCJQQcpNv5ALFuGsbTRXh4whuuFXvkmZXnvCDIU/+9HFX7PDJ2XiAYMkoG6giIcpVZghsWN4Lsx
djkE0hGyr4/E6m0R+Bmy2ebnRL0Xy5XHCz7iS33W2LlrDwX34FJJq9gS7cHa/uESVrLQrABt548n
kgLWtshwlO1iE62l2LXihtDf1xdf56YZMwpKiXaEhide4p+XoZ3RWjQVpUvmWxBsU2YTV0AFOHpp
oMLiDrgc50Xp8R8RjIkcMn4j3dnpH+TdqeAal1PKZnoxv7dZrDYxDgIvrZnOayqkWOEBvtNdEffV
95nduVmWBk5yeHFvkwMkLg77SO7ZF6J5WdChNxvffRGmb+L0dRYykrWw9ozD+j1VvIj2RDqz9LgD
ivD60WNOVGgHBAgMSc/ao87tK+XC3CThHpzRQSu9Sa+rJhboAwBCdr6RLKbMQqDZHZaBm1Ke9JXt
V4Uf7InHDX+DOP9F0djr+Qa9BZ2ZkIW0A8LklYxmzJDcRY9csqO9KpxgBY9/qpZIMhKg+XI4GWkL
RsQoqwvounnSIgxbjWgbg/iABIbI0/Unmlh+Cp5XVWQyh8PnlLghGX9tr38/bWB0rU0MdIco3WEo
rHCDByjrRZuhdcPVdekYv+Btc3V4lFFiYy+AppWKxS2RmaBYo4w0QU3IcT4XVnwiMoRqdSmTgyjw
lopF2xZJ9CJZh4G2UJfOQj7xySvvp+joUq+OLx1ULC7Q7zPV7iBzrV1kHcGdleImDlhBrQPGTTnj
/htuYYYrfJT5RDhj/dM/HkYlbVlx4QnDFrARJFxU1jQsiBHbLvAMNxmJcOarDYCF3iSIO+bpEjxt
TuFoyS13xW4N5Ogf5ek8GQs2KR4Zy6It+fWFyYJCHSRL3dygQBH7sVMGzLXeQ0PmSYC9474OLYFX
kqtTI7trYdcJJTSBC0Q9j5GFcfA5NKoRAr1DmEUjmh6/P653ySwXzkrUCpJK4ad3nQfBsg7Pj+/j
fIJ4W5BelivZhsfPq/eBxqPTt2Otwn6d4x7qH86Mi2rnBxgFf68+E0+R5pidkVZ4VpH83mz4M3XE
A7IDDn1Aeae35gawsNtpTvUiMdSCTZ7vZyLZAfZOtCJFaJL6hXeD2YAXm399Yl0kvlDSKfxTRJLw
+mEkGiV3zv0J+/m4D59kPGaU3YNQKuV4JLkUlwbYN893gQTVUSZy/sD8k6ntYEDLeJnoXbtxMluO
N1MTYomWRjr8Y+gOuiJwhyHmN4ZMPsxzhfOoAALUp5uj23xxFPCxtPbhp6PRNp+oJOgWpop6jcrS
ZTC0EiGy2BVwQvtD4TzRxXVFx3GJD7UovEXX6PnXOR27+8VSWmSSgd/SiaSw7Ru4Z/gghK524+LT
m/dq7hFEi4GCR/sKIrzl+Z7oIMxgtr2tYUG7E4GmaGTXvjVZpB53p/6JEMN55gbf2PN4eh+vwvFa
H3GECQdAQfSuuKIuZX4WbuJTYBvQT8RbBGII4I5xXMLsjmJPyyGZqaFhe44c1m8+q3xsHyKIDzPg
jUCBVoyxJu6zIH/ij7L9ecaPaJ9QyOjPeViyFxXfM4wmFs1RHyEr8/bhm5WnaPo6sgueo4I+DUxb
Lfk5j9fq67UIy2S9zUvpyiq/e4q0f2LtwX387vdJIhJeF/HIqnQX9LWZuTCbk6PvAT55jVvOhueW
wfoiiF1kF7wBr3zvIkvhVF/R9d1GvtbyOqMIHbd1/m9wQoFwEeVkAzH0vbV4wnMX91drLD4Dgw6S
RtNy9A252ABdwe4HL8rGh5rmkXRB7uD1Y2wuXcSXYbr1zJ1TUrthqQHmC0M7Vw5d03nzM4r7IvNp
qYtRfCW9wQxGK8W50ugVSp+C/Qn05PC7saEdS2lFEGV9M6RJo7AiHubq/yayYouFRDT4Qi49z1F+
8PxiCDYFr7YljhAxDQPO1YqqUCFN+nXTQoUTaXU+Aftk8ZQqf0uEFpyj1XzFqlu+9Pe2u1g/4j9+
/7y7To2J22tL20rDtpA4V4Bu4/mWzShk0/Ox7V9pA1+kwR2ZFV9JIY4Ip4cZfnSESbR3TZauxzPP
MHsRSKwcU1jxNZIadEoMv6zflNjm3EzNpoCBC385FmauMjiRLppBvyvgeFd+gfbO3IzGbBF3Cdz/
ujZlZUuGO++lzYWkF4DO71fzsJLaiuY79ID9QnuaALEQ3qti493jyx7xeRLHHHnaIEEkk15FKHKu
rwZyrPyg69B341eRnx0/dDqYZg9/f5iByUvRwg4yc/FwzxBzQFvKArGci3CCccXaT90e7G88JEQ2
SINzzqzJsLjnVbeIu0T5/BGQUpXPTFELvUjdRMjG6AVDuS930lHfmZKP6HiUKo2nTGGvVNSW9LrC
nhO5KirFyNERlommNZk4WRwVkaoVW6tOG4tj4Y3tVitgoXhhQplrxzeHlzwIw7AaW4Cn7sGW+O0T
Bx9TOSwJNcY1uMjvzo0t5UqrbDA2zkDknI9AaOm9sVyZIahrbwIneZxkyHv0HOPv2i0DNPklSMzj
fFL5hAD6dfMXaxuThhIk8NkK52J9yGLwOASCDLx9WYscXHMOWSa1wpPGqTaKWa4U0BNcvNgqByev
GGdVXuUlHoXI4BygYC8tA1uctF2dmPIQFz8NLCKvBBvIuuKtTfdb+1ljJTTvwhEbQtzOrQ8uGdSW
kwZIj2HGHdbG/GDvBPffUYcPYIyVPkkghpwIVF4iI1rWRs8ZevOOc7wRFlSzzSOcg3Dli5nqiujX
28TmOpEdxx07KXEZXlpb+wAfvGxBTvAQX+N9h04wfFVBsOE6Of1oOaLh/4f39KF6/Yks+uKqBbLK
UoY0mShD8gGMZgkQ2Z6iPPBO+9WFJ0x0Lf98ynnCEQ6X+b5C+0+I4JL7PQtoXFc6mR9yv2ne4mNe
+Gn4mKXUluLVeDaCTB+cTPCW/Ma3VoLMsiw3aIF5mjO9MsfvC72b7os3Mh+iWuWcfTa5thz59V61
CNitqFfNjQwpnS1NVrhmY8f3oYoe6ZJHdXdh0onf9BEMSl/0oNhG7GHdcAZyaRSY2seFq8wA7KH1
751+wPMUh3ui/ZBMKrc7q3SDSAA5VDFQ15jNhblNhGA2oV05rjQgChHZoK0foojtcJ2D2a2vnUX1
YJ8jO1ClPUZx80i0KAtGdwtNS8WIDusFTE1Y6+L7WiV8r8GdH/2jRoh7iXEJQ8N/srgRp2mmb3zT
6Z+wtHR4ywJIlN4sVQqUU3EqggRQ6u5zKhm/kMXoNNEauo6IqzUC6RLZe8OfLlIeXRcBIMg7Xjck
uIL2GPqC+cpHzBk2ueAKNyfRyXHVLVXqQZvQUn3lz3AENb1+iPAc8DdNJT4gl8YmK++YaPsYZ3gC
CxQeKYh0jgpZz7PKQZw67VzAUa9YNj9qj25x948YlvS+8SIMd4nIfSw8HMV2TG4bBFyMuatW7cM/
1wWGUk5YhCbC05Jvei55tVsW0sQaE6+F/j86S4V55+5oAozpWQv+HpSgj582EZ2qNNEX5ly7Emxb
tmR7/Y4ABJwcknY0cBoM3JM0nWF2oByQOvxrc4n74d1qrh9YOvJhF8H/H20kte8W7qBU+RTRdRoT
WYMsnecbfOAUK9PIRGekUHC/pbavKXK299GkQ0TmA9zI0JRlc6SmHdBuSmuYUb6yqEQFUkpHkftY
5y1EDCx4t/3MV3Ke79hPLJx9YPDogGc//NrVkqWDBHDJPRuPWle/HtDkOVzR5A/dpJOsAvS3nwc5
qcyn9u47gOy+Z84rLwHvjSI9NoOyzktmeg6P+7cAO8bshXP+uhEOvFAZatw/3UUjscqCaHPLRoJa
YMt1cMm+Y2aNIW4EBquzWAp0IscrorJ0c3Q+vldEoWtbOnqpmuSNSXbzF05ig5imvo0oWXV50Rc1
KoE0NnBMNnM7dUtdRW8829u3XzKK/9NfrkHI3s4hzQKM5WxRNDy88zF7jS6pqt+QTmWiZe7VEXUM
aKqM7BSNy5C+ygX+INy2Urkd+sKPVsG1btwvSfY5vb118Yg5uJmc9utqLzXSyctZG/DpZcCmf1FI
UdAJ0Ks7WMKLZ77pWTTnlTOsOBCXywMuEFsSiEcAjlMcBkTC1t95ZJtOZMXv6UE1vuqQ7oz31h+c
qGI4IsavSVaDWTvoInuPeYUsSr56XxScTFGCBJqDfeIu7dnXxd4fcFO4o2bagOa/+JF7FVvTw4yD
rygAFc4GI3D5pfg4hCyktQtv2d82FjVh8kMfzGQ4OQ1VDQMhQvIRMMaH0lSRK3V0tPlH9WPde0lu
qEyh6uwPMM91sKlKF/D3srgM1bk0NIVjXdWU/1ZQM++MXigMG28PoZSPKatZq/nlQHmQg4lH7K0q
5qy2kVxhzqJvmXvecg0hzrJXROjkjyN290mauUVmkSVEJkNyj2S1Y5CUUZ07VM3V3onl1EY7caJM
zCm1VS0TT+SbaXKUwEweJNDUogO4X7LJlWvHS9HV1WpBWpxZy/MBrOzg42spJDz7a7jwiRyr42l+
rQzLN0D00X/hWNvrDBttGuF8+A0vPPFMwbFQA30R15lNgDN3uSNCAwWSZG+ycCOIv4Kwpqk0Vxw/
KEseJZzpJf1oEjfIQfi9ABk46+fILSTo3UX5V5cgaBv0Vfth9RtLcbxiibJdS3GGs2TcDYfkofId
nBeIapfUxECq4V4zaYvjzCOsp2VNGK94CxKS1YKFQLsGPtrcjvyXSijawGJ+JIaL9OHteIvQe9ty
9wkRbQS5154sFOdLDTKD0+IMuNI7+3vcev+k7Od8PDWV3W6bkq4C7MwNDBYH9Wyw9UbhaF6FIRsm
mneM8SSnK5JLkufy7vD18ju+FvhOirYO7USF2jurXhV7gJpP6fdR+AyDnTNlvJhErDsZQ8C9Al8W
BosbOYbI0UrQoR6jJK7zcNH9+xCCjoV9egkNZZZwrSdD6GVQtqWo0i7PWl6ENQdxNqAT2D5yvG7x
i+FUYHNRzHtuYMSDm53Yp5aTY9ejarXioxyRsvRj7nX1ydM1PD6Gq9GgEWInqR6Yg46gjn0SuVvw
06fE9zGevu7N7DNyQL9j63Voy3O3dQqE+LTQaARTlXq6rglRxdXAmb4mpS4hC68w+qke2rXGSlKT
Xam3DulVc+mWy6xkMOyyXPjpusNauhW1FEC6d6hZSPJ1AUVgG/WeaWTOo/MmVqGzJNRlxyTJ82fw
eu9fkI5QHz9Qpqh3o6hs654hLCbdrV5S6Cn4NfpJpPGmUdvcfeiVqFSx9yHwLdAJvQQUNf2ywqUo
Otat/caU1eJlVK6/MfsIzu0dixykFCqxGWnYI77VxYwevjvEnRTJO1NlRJ3EBovLD4wcQrViKx4Z
frcz07gAErpStztuK1mFYmHMbO+W2rdxpn3rKR+Xud7HMTEcOQvayFSv+roH1sbRhO0f7/mCbC33
ezwhCF+XWwRLyAw0+6EXpP+xLO2Sm7skPclD0QRTKhO39T0NACPAlkKeIKmJTas8x/EjEQHRgId8
uiFvKLiaFY85wEZy2IXpuZ32TqHDpgRP0EPCuoztrosrdlDSwhCZBtjM+S8Z8osjhjQe0WFBteDY
aErGPP8ZqX1njYH7yvWlzM9VDaepWt9eogOXhQAYKKkrA3kAFFOKH9Os9szYqX2l9siWNgmzLBex
DJbC5hsH3qtRFne2cBGLndFgJ22rkk5QQowxTwDaSCSTL/YCxPI4bjZbqc3ixrKqYGEXBsSYTWUO
31IRD5EB82ejtYF3USFLHidbu2oNCXJoPLM5OrL6Ctpi62G8jWgkqkcIlLUG4n7OxCngPs+M0Xl4
Jma0SOMq6FZV4OpMLfqZPsUTkSI5YeNnyv6pEZrbqvP/Mg1/NugkbzhnQuyk7X5aPoMPGToxWs1V
QRGSnAc2ZIrIZhPV58/L7hxq1w6GpGqODrmQMZmTVlAI1h1iBDscc8eMOBqqXkLw0xf5BUgEK2nY
gZTZDjLy1CuOIBYz05taqLAuBTFt1EuXxCVdAZoWPv5ikftHcXlj7m5pDy0eQ8P9pSN3PcHlJ9GD
K5J9zH8bAPuXMvG/McfhgsSl2c4MdtLxdmfp0wc79A/ZvT6s50sKnXxGjRuDSQGo3Yi2zdkyi62f
9hRbicM5IBgcs2VdPTpdDpP73uHDWbTl51hv+1uuzC1G0qt18gALeSKmhnWZcNNP6fyNj7ZiOan7
2agRe5/Hnn/MBSrl5PWHy3CPHpdxAinrj0NKUF+w8PIQph+s9fa9uO8RF1WnIt7GNc+bS0WpOaIW
Khd0K/8hEifmSBcEWXUEqiC7/mJMgAOfxd6rMC6ZLjpP2i/NGMn+38wS6O308PW4UzgKZqeY1Kh7
ue33MwWrQ+yp9FrL5aN2Zkqa3SDnC4N7EOvTuDggwot0abOUlLcpcPe6k97/fWCGY1WUJHDt0idh
syk5p/kotWoRV9dpU5TEyxD/gbPulAnYfoPY/Rh03IA6b6IJetIDtvZxWGrDFtO+ayi1TG/vWy5y
AvLjbgZl3Cq3MEKs3kGr1hEETHKfgEVy6ppB9xjjV4xZsEgMGFdR1SaU+T59XR9I/17s+e9CMIhu
lzx+JkiO7X2YJdLCIBFQaNvd8Y9nNlf/FgmQjSaTvCDlSh258oCp5BmT8LfpAKuMN/3ngMlCnyJW
gXysWmiS6Ev0npkFMLqSHnpp+ptEBSCaLO1gtsc35brNTbzgHJzDZvOzkbWCxrGtozk1pnRSyymD
fnNUwGyUNlmLc84nW2z1xAsfNrIt3OXwS9SHX0YEsM0r5ybzl9SFO4t3eMPdL2DHF6kRWgvv9liM
CMcpo7Pyf0uk32cE0rEFRzvvNVxCV8FjuQQ4TaS3aqxU0DCmiPFsb5QRFniRyjzBpz3epF/CcBl7
CKUuqhZkc96ijW08QjXCAbu9P6k9OT5eA0CXD3L2VjuXZMIw2A85SiPRBQ0vTUPgfGCzoUpLbD76
MnchwZ3b2pfUqjeGLBDd6WVrzL/dNStPyNs7K0ye4dyTZIQrK577KuUSa3EB7l/LnSXF/8SX5q29
0CbknQa5ozFIu3Hy7lqkSe9mseBzaPY92Cafhz5acZPUc50ZeVC4iuZ75+2b5cX+76nbXKXkPIN7
Uls8AU4eIpp+hIHZpdGnFCcSKYljSlQIzmnUPNJq1i03OaaChXH6vHJa6BRqEk17Qnbzz8pvb0xa
qSbgKQi2GxCZ6OpMNw9WrlZKdeQdwa2HF7IjqkA3dRTD4JcI7eOXZIsDfl0837Ybtr3lzkKMzpHr
rHQdPsA67sdghwK6p+TeHQk2JjEaoJnOKb2VWg1ieg/XGZi6q9DkauHEcNSQ8Pk9QiNVTFb/cge2
DsUHAGiQrRsDcyZfrd1H4lr6hi8WrVuqz3ZI5Rtv2nmnlN7wrVcbh6UizFp0zOJ07rD5AQxJS3xU
rmvVC6XjRlH9fdGmm5coyzxXPss3k2tYkhfMB1V3MwqvmmjQkgwFjF34A1NFVRaI/8kea/y0EjBR
g3cRl1bXuxEd7+AA85Zlf1EJpcPZtQTzNpX19/JA+v++pQw//SnX187kcuk5GiNOsaAUIy5Y262c
l3/a7TAhrdwzTGdhZEvplnfKVsn4hbM5sTYus+NcRlsdSIO2+iTx3oxrVidlRWGceO5uJtr5dVTA
OtB79ATGofyRiJMvYddmgE6+IVOCBorpfM6GRmPX8NJ3eBuuUnHDLdSoErEULLXgX2DE7iXIYdw5
/1dHSUtM0yrMstJuuy8yYo95d6IAV9HQ7agY28YphuK8Z6t+Ub0Es1T1noCQNrAVO9GUZjfN5Caa
1PbkJwbthZLqrH9mRR7tLmHh+dFgJ1uNJ1vRDVZBOc8puO9LNFOMA4AEwEByuw7rscpjG+7iAXWb
jPJKd1jtPl4pb8bjeHIaZ481Aeqd7YqNmkVEQrJqw0z/ZAFFmaM42c3I2ejKmy9DY32kpDWnytjO
GGT3tdHpkT6x707XcYBpoQFRvAoOFgWn6te1EIsiEj/CjAE8a/e+wzlPbPHG4il2VyBMLNo2CTe+
km8L7i4ZL3oYYX2M9SFnDdMbRh6K71Me3f3aXcRTaXkj1Tvs66pkBtTDcYq6Wc4E9cCClooNMa+d
5m0fro3i9sVsFq1DLjnojIllM/aZ8xQHad2JuaZnoSJM4S/q9sBSOGaCs7/Oe8bCycVSksw9AhMi
CnmE4lghGO63Ovllbh9WtRYwDNu26S9VNWx7p2C++K2Ns3l0lMPdjt3aaH8HVRxAMzF7UL6oievf
/WkCzmoCTGhS/Rob8XMjpvLPDx0eBk4krofIqPvBZ7yLh9x4XF6+fksllK5OO001NLyF8vEAQBIE
ReVWWbzHBeOE2uTUhxS1WXWCwSjef/xboREHl8TKHq/XdMkaFBpD7zIY5EroaalKdJY/WuO1md7W
z/E81oXj1ZmyIyiUqe+DxE03gKAbM1/U3Re111o0hIVpxoCT5sjPrBwZJjotvBoXDGbF+L9o97+V
E25ab+S+k7uT1/cEdizJkOB6ffwLdypAoD71W5af+4vzDeSP4oxz/GnGOa045s+ZIdBn6fkfYW1p
4FYAvQ5Fd7r07kj1z1G2Mnd+zSSkuwbvKZMU1ISw5ZTUiaoIbmWijmNdKjcFKa0e1ZZIbXN1rbqB
LmtUEsa6DsVeCZqrXr2yf3UWhOgrWS83JOT6Lq9nu4URBPlWlGL3CBKAYcWcMrHiKMFwhfkwAYhz
W0lP+4glHlZXT5m/Z/vu1c1ZO5wYtv+pdKje22HIoqTCXS/nxgrgpHu72ceX3gzEJZcy3bDXxKaG
NsfDezfyzVUTBLi9Ac0vt42Xwspy8oZ2B4UJlv83mK4HaK/jCsYFTn5nuey2EKG09k24+TFuvqvh
8AoH4xROi+D/pQtTL25TUlu8tLqoMx44Cq9PoB28aq9k4x7i310mQb7F5eYBMa0KXrE+MP1Afxhc
9MzoZayLP86PT5SHwlOh4tcx3vK3QMxF5iLC0Ktnl2j9TbGQqYUfb+IZ48AalTWLSoSpukefH2v7
3AJDBFWP7qjOclkFu/uJSEpt9V5fla8jTymZs4w26+hA2McWdwsghOsu77QBz7OeomBqcFYfMPpU
25OINZk2zKGQrukc9b3lhN0I0O/9v/UJbmEQ4vxqRNc6ya9Owooy3uJoCVPprwV+Rr169obRBkFm
Qfkc4NVExxRH3OeYo/7CgMcOHzVR+CS964j9NfyHfj+Ae6MmIXbVAFvVd2jMpvo3IH/6PjzaBElA
gbTrwmEo4BH8Ya6xW46Yhi43mRgDwaJkjGSNYdcdienpK5LMHSXMQtNiFqQ0rqNbSCgaXqjhy55+
AH2L8BYEw6i917PwfC0pvg7IzTdZfh/wmodBawmE0Ijf8WWkbKuq1Q5GM3kFewhrGwu1KJXjyZgo
V+UR3VMxqL5Eol4qVbxpI+4HfEpZZca4XxEVer5cQ3XHkNFz5gp6jlHmSt73zFTDLaho9s2//RGb
4PDAeSBH/4INUMzunSVrZFlx8PAlaaEUaVLUFiXa+MhpuYyP9urTO8439RdZRVeqAgnsEK/jfOUm
RqO07fQRRP5ZYN509/dTW3juPdfOEiTkVp4IOjW8SxfFr6Vjwi1YPxmHp/zAElsWPY6XOcpAyVTd
v8bPdKLYZmWh+iiv+/dP0h+BVhs3bbu5egpO5VQJ7ayPqYiZmrJ0YAXSWc+xkWOdaxiW1/iDMpZO
2oQ5BKV460G48MnNu1vXFqVGPWx+3VY9K3Ye//Vby9l82TmgpzuKyUEXplREffqQOWrtnWUgQOcU
9CsW3OTg0NOV2HXtl3Ibg1JkLjpQBJLUbl0bJTCV0OPL0X8vST2HlrcuB9VWC2amNqFXEmZkt84T
It2zHhhoq2p+16HFgdyx9Mk4E7l6nwLAwP6Pj3FNctfNpl+zKlhDq2oYYd1ChohQZPaJBigZmPDR
h+ozu4G5O3506UFqWeoNFInTZsd0wYs4sa3EdEqK6Ou1NGsPzph/t1xizz74paxy6qoxgiOLftSa
yhe6cxedQlesfdod23RzioxdMJ82M+kMaQFdYKQ1OModYwwY+EvDbkyaGWjzYKnpbMsYlmCY/fu8
9XDBKBOovD6DlPSxop8trE8EBcuu+dcobRQlBxc6dTNjJ5hswkM1b04AL/n9Um8ouhynQD+EUncC
CW9UdGcQymQ6yp9q/TkNqnsWeNsnpoWppUEioe0H8evBYGwnqst/Ymc9gFkbf74GIWRU+BgvhVhY
f8wCHes3ZvHPIy+84KwbjxuhyWRPudBTwp37W7DtiN1wEjAcbnGFK7BXg4kxzfxheZRESzKVBO9W
iQ5B3RIVKiCb/CLnNkTW8EVetltGTkt6dZyGuOFgV4BUm/lcq0YSTcu/gUmXaOQIAlnbrmwT0YBl
Tr4IEaZtwSKv8QPY0BUyCyr7Xa4OjLscYFw2jyKdfUTsgQUKmcz39iIQZrvI75Vh9AIvb3SMEJuk
6aAj6A9kFrPUKrLkr8fZS0Z9XE+wd213ygLaUbiKX0PF7ipwt5amJGuQ4RGh+/r1n1QF8qDPLAmL
iBHgUD0R0pDNu4mVmYIeOc5+U6fRi7EFB3Am4R4cMYCSdD6ItyT0tj0jSW7xvW6CH5d1EuU+n4Us
0jB9gl8iuE7Epyy3fE9Wn2Cdmvpxl9nh8XmT24yDUtZi4mQbD6DWjdS7YK2m9o3TjjEADwKHcb8a
vEftC8uxLFBBMVan4IUEXxwLOgFxhxETCOL3a/P1OGH954y26xR6nrvqFVcV8TeJkirBDsSka5qX
GNjXLAmreT8b2FV9e5TCmYn6r367uFHOAH13Kb6R8Y1xneg6r6NLDL/rhaZkjh2r69diCert+Se+
6+vrW5un4g0c9194Bh4q8F2gNKXdJ0Fl3sZj3RLCB8vs4Pix4zPHMMhyWRyImKsV9Y2kaLQGTn+E
AAeyj1wIxAvhhkLEIqEwCI6cyo7wNSAZKOkgP7UaqqeADmpo/ttmg7+aHJ9CPJNBSoeOjKba8hji
WyCRqsHyuSHuBoRIs+3X6HFfM8NPsQnDHRbg2y4BXsaHhI+ZU2DY7EFxHAhvQX2wg92x4h1PD7rQ
u6KQ+x0bpMMhvZNp4eWnPtRIyGyOw+Uut2OYMcKuNoxgBcpygFDMcXqEiqJp6Iwb2FUK2dwB/BfO
J04SFJNFiMpuJ8ARTEdF5UtVjmrBrAlX/Wi3SsSwe49DdxXE7OXzgs3NEOnXxiRWesnWOBOoJEKA
FM06JHxm10/T0BoUdaIe5dbLKph21nyYFSWkPPqdjiIC5qyHRNAWPX8NGQCXFCjG0JYwRtCL3VKS
XuHTG9G9IGMmqs3Bs84FiwreN+5xgEG7P8+BpjJLKoXebLfdDBediXi5QCBO3ng5JlhRXfqR4/W4
SdqE+2OW1h9sx+6AGO2Lo90PZYsHzo+05kF0iMnmbVxJwCFVIcuS5fKJXGcVggeWRlEEFjLax6MJ
MstE86dtnHGPBwEMtBT4Eu/WWDcXzyNpHzObzPxdfzEYeml7hk+KikLYVRvDasNqtDH0KAShl0cx
HYiJFq/uOiinhDjeTlUkuRngSSMcQCop5xFSAorTjyNV3zaA0w4fOecJgaVbpOBlTDdUZFbhUwrI
Urcoen+257WljGhu/wDndFdpVlxvbkMGq+AJSmxjUH5a9MWLf1IsCX3T+1NklvuxgynTV89pSCYN
TWcqNxcgWZzhmQuS4q0ZBBCuHZJs/5rT11t7zDNcb3Iu/jWKkBAbWbziuenenViFwiluLiD3eucP
g8zNHkxe0R2x/XDksQlOYoqaYeBS6ADSK17OJB/GZtUC9yzZoM0DE6v+jX5n09lEvqUMSjZyu/tZ
FL6paXUcyFzWe3eVVobM3IOK/pWHH2jFW9g9IMd5VY/wIagbVzE9YoWNYTWtx55bE12Eu7ZUUtXf
Om0WrSWecr26peryubNFdqdePAFPwg939Q1FWfPpAvSq/seFXxpRdTeDJjV6IM/IuP9CS0gfuHsz
4SXpiBQyDAZpUjn0SuuWbwh0xVBqUGJu85cBrmG7Ik2MwqSIU6stqfBAHdOU3vUNLvh34pIVj8b0
YrSyUQIceSpGtEvPP4Xpu+ZN/A4xNMG1C1+n34WjYiHM2GSoQ9FaUilc/Z1ZM8z5rPGwGw4l5LBO
FuNJzu3Y70moUv+5jS64VfZTD1+Wcflf+cgRMvJ3Fx4hHepyHUYb2B8Q4qfPRpCdPhLHgkR38T6E
p7muEWTsvTvKLcECHT2kywQKYOQI4FFhmx9N9Si/arLDR/c1Mep+L+jZRpED10zbj60mBQ4RxtAE
XPGfzhCr8GJrXniaURtYHj0cquSxY077kTqYaISDrxJsU5doG5m8EZRvAdrU1kDo42wCHaJhF8va
7vQA6hgu367cKIQM55elwxYm8LL+tVNLcv74n3nSM8u3ZGnreo0wgZMj4vnhOYKuDz7+6rSHu27I
foNA+9rAAILphZeYzVyX3UvkUEZuY4Vk03ZddyV/ellmqHaX+OUkTd3m2Tt1HuCb5xBq4ZYpug8y
/xZk68PTxxs/KBrVY/gNyyiOaT9V3netlQ/fZb0ATXIhWhdd+ThnkLI25pQGYcFP60R0dXi5K+a1
r/8EtzjOY/ZzPoDWE7iwR6KpvZkkBAe/rHkDDomz55gcRdX+8bULI2ZeI+vvyi5PWgRF4PXcWFho
dgMHvWGJdWcEi4+txSmAMb0KYTT4u4hnpZvhAyDPBJm7jqAgkPingQeaWD0eqPTABlmqHKUdwtwz
xK9/DM4j1vxOS2mC25/OriG+2vY9jNnqAAVehTz4n6ZWoo/yb5scyOOftRTjMQIU56N3NX5ZigT7
k/PEJdRHoYgLgN65WaFLY2DMuWM65qUgPFjeolEqI2rTViY09J4SNjLUtGuDFTG7HnsMYFZrKjb8
GvnoMWxmiWZk1PYuxe4Hv+j3Oqw6SZ05nruHBnjESK4rD5EdApZM+MXyuDvYgjhNn5TddJFCN4ay
rssbjw4BX1vc4NzfBVjbEvlcYzvO3cviO+r+seRlVvsVZckt6tHNphrD4/3TLnMkqnNXy+NE3tsf
s3otYOJwyhrjRgVGnPhDzJ0eKHUlrsJTwTgJeCivcVMKeD4Tb6CgFuBGfb7a+nbeUA3wbLLQG+v7
F6yjcqIGOHOv9F7NdbA5jh6/maEc39cLP3HUC07j2DQawlinQRVuF89hN/Pl3GLNkbawcEVDH2HL
6HSHt95rELfJguh+x3r8HaEX4ZFRiPcweAJaM1xczzkN/2pLEuZjZGrKh2PVTv4OXC5sXLgXgGnt
hxR1n6n7Lm/DGQi0HAxAzXmrwyWZgbruhKpVkzz0vx/lQllbM+v8Tn4QDM/d/EAdJAXRLM6PUL7p
THRc/Q8RijZQGyOM6qPMTWectfvNmhxWMEFXsaZbt/Mti3t12GffCyfAKhuFEdCu6fwjPyegKxll
NZFDmKHAJLVBd3+j+u8+Yc5E9TgRykLfuXbOPSQ7K/9EP1+9SbmdXisicxpmfBs8EKD/JlghNxx0
gDr2muu4Qq5F7fAOEZjDBZ26kuA9yBYSvtOpVNG06OKdoJ/ZCnLUz9Gsxm6E7AhXJJN2Eh/KmB3F
lX8QWZYJ/LMXwdwTx07O9E+kBXft52wcUtLHkwtMlTBC6kTjtTWknw8BIgKMW16p/1ph2P6Z+qDF
J40fSfpXuc/ABBMQvKXyZvl2Ww9lAWyKFB6ebcB7YSSbrOOf2KQiRs74AYK7NYm6f+rs8J5opwEY
XnJM8UbqPTv43HGZ7y54lKC3U+RsmnPAztxJR3HEjpZQy0gLjG4aUuzhhktdww+hy6LzHaayBK9c
tpiZ8dF7TABlBEzfeK6Lpw493zkk0VhHM/e/HMKYd1tmii3nzBMJ4S2ScvFGg9hHdZhjV/6yGtnD
eo03Qb78LHs5wha0uvaw5TJkrLEV4+jPxB8zVvYdG6YrTPtrGcyE3i1d4UPkljIld4GNRZk8YCp4
Rt2ngt0aEdTieCfnzKq4nodPlBsxEBsFPKBf9q+wRVZ56ZOs2J8d832otkw0xHe5MZZt/P6JHVLS
v9tOEgqw8cmN0lDaLwvAUi19Bl1TRTYh2QuYmiiLp1A0XbiujBwmUFt7UgR69FKN2l39ezEVxdiW
lXH34D1dPOVYCxA+27+zdPOwSOROYYnef2g4yAi3KhsweqFroY5qtKEDGcatdIfWHH9ZFme1sveN
ZiaUSBbH5Fe9HwgiaTEKlHJmlIL8noiV4JkgLIGjl9/qkG1U9G6Ibt+BJYzZ8CfrgagLR7gdP+Ta
lwdHeUN1TS2axc6Bz0XLZcgxjGIiJme5KGQwAQisfewVX7+yPaOywngEsecaVT82LDUDvB2QEbW2
GJN3KHhhnemBllQt4ADqSNt6q7o+Ux835Uly6lQiGVqRvSLMMLGQ7B3Tnf08NIskK8Y6kRVC0hcz
tt5Hz1yIz9aP2KbJ8ICPx5QSSZlhHllZzPcUUIC+9yEVRBfbCdqTV8iEdvDaZfSgZM3RR1GtIkT8
7NOsQI6OcWBsAHaKrBrH9QwDpAzgh/IwudxkbGAPCPvMC/GT5gVnCb/0sO6L4SnSTqPcK/kKOhNK
WVsVuMTlWlLfx5aqwCFdwqqON3VEx5aCgyoTktZaM25fQHlysWGYRGYmlTuqVAAyMKoBmKR+8ASH
ldeoEMZAxkY8z0E0F9aTIkNNtkcw7BVDja0+5/cHsKzNgNKbLvH9zjSEGvmnqm5UMTPsJIZgpPYt
clqN1E+FTGgtnuhk2vaBpSM/Wr1fSUsG2VMaIIfFqBzR8ieluv01QZPTJF+9QuRu0XpCIL85rh1Z
zkVYz6zQXWAh9hbyxCCFD7oUF9aUo9zgxzz31Evr5AGbTVxOqj1wpaR4wlkUmcDJf1EQbgBKw6lD
PmZq5+sPPBb6JuJlPWqTqXQ+jyJTAc6N5xAQZYhI050TO4KS3km5mE9Ok1+UWyloOzXlGBXYok1G
2axo8lomKngh1wt2BsveQMMhQzbhgrZktVUZKQzgSQ1/XGFWqlhS6fQdE5uyXT2pCIam/fxa56qs
hg8HYwNP0Icv/4HhXoJmIIUX/tLu61cCziluyCTGqlUWvOPJ+wSli+qKaVRFaP9nFlH/RDp4dW4+
CAh+Sz8SPlfYZl0wkGldvA/NIkYTq1wYuHQl0H4ofakeFWWA465z+tqYqUjqpy8EHThbJsJY4Cg/
rjchCsh7JO7Tx06AwyRL8erdoIfIfQiWr3BiyHA3r/vT2mvSpsr3NHHiFDiZ6uOSqprcyJaRqYE1
GXc2fLkvQGKUYKDSbB1uX/3RebM6Rx1IsMKzQDTn/r/zjV7FRbR8hzafjxtitTfZEY9bpZMCr0nA
9oWMXUVG+4/xQ3vW6aW93HLKBZ5nSZZbYzP+xbHLE/D9JTIgezb7K1bQ9PDHSd+Dr9dFjHsuzaD6
2FSwWr4dL+TRum1xktl7sllLwYzCHPVQV+wwhURQJ12OUACRlQVSPY6rjhqyrCLXZ3qHOnCWzd0h
c5U5J6HPXqmA8dlBnrwc0dc4ylHBpFaezUTThlmarO7/oskaoqrer1J2kraV3I9lx47I0DuvyW/H
fpnwDByUwq3nsFie7oZRJ5UeKtt+8NFnu76sd8avKLzXqYn+VrdTGt5e8B5TddRopEp/DVdrvQ+i
mbGpCRHMXKhnAxQkaOLHLNgR2a3ROsgjbvrzYbpBXCqQKI2ZG0nWXUn6uDdOeBCVPFvgqLlWjYmg
T/gO+TjWH1/nc3wm33bWWQPQHrFw1hjotYAU2ivzoCKXjtBagKK1ZIxi+f+HhZa4J+BhKbBykdPQ
qOs1xVLDmXcTQH38Q55ZfsNhPWZHgFw63MbUErft4BH1qJtDzauV+zP3rQAF2ym7NzNQsYytd+UZ
hEdtt4XhjcJ3VcGdzZyIlFwMchDk0J5+9t5iXwfTAOueiD9qzIZ7LGW1mUp8fL3mmOU22Jbmcqls
gkMsCvDUtd1ClfKRU5wOYjDH0pO20BlzO4K7D/FXh57FUp1TZM7uzSui7uEtMcqdrNMgmdphCCJz
IGOcGM3rJlZtwXnjkvtfDG/Fj7lmNahmoWGvAl3jizRWQlnWwv3heu52sT6hMRg+At17SpYWHhwA
nXweFrGzvrwIEPh+jgpxN0Z6BvzT6l9Agd9sK7vKw/jJB5T8qaaHh+nmeDcYYwycVGJKGxKIgdJD
qFDpTAM4LEKSgCmtMRgK1J+bNwf2MZOgnWZWsagxvlAxmUv8RQUpdBqm5jAGoUVJk7q/j9BmSgBb
zb0ICYD5wOnzNLW4NAu9bFMG0Z/r4mRPQ6puEdjvJaXTKe447E7lgtIeyUQO6cesdYZIqJJVN1EH
u5+dFOXGWZvUUowtkiLlCn+qnVYVyVxiBoLvE6mOyUpTF2UX4o2NHOuJtnsinktBPDGfqiHbD3nv
CSjkBZl0HCBcyvcQIdUw0PiAaqN+aFZgTAB73H7UDs5SEKTHEmJUOR8V1mnBRltx1eoIm/v1/Uya
J+JwhIS3fkA1D/L4DhH5H1dnMOV85K38Xqz6F2N7QAba+ysHRW+WihUl8jxdtKWF67gGTf9ne8BP
dv0mgYkOnuHezbd6E/wg/rjUX3M9O4uLKaJfKXtNoK1rfKVZ2jYnP3+71m5Vx/39HVTH5d+g0j7s
GQaX7LDgYTXhHdISchmcOdVfewWNztLuQjDZcdz15ta0OEHjvvq3orQ9ZBize1yYa9Sxma0ZTslX
yGGocSEtzq9+HJQRfOv5WVZDbE8iqrmsZnNvYqdpkIU20/oWv3j0UKeENai6jO9yzlwqDqw8NHSj
hbcHwlKn6Fx2bcBFRtjq4Hr4EhYH2cOYuAB1cW32NSH3sFZAsa1DOh0gUtwbKLL5SgynZ4KUAsWK
UOGlKiaoCc2IGis95pUKpeN1S/1ahQR8j3GSNV/KquIQ8sgiuqbzu8/oxDuAoPBSymMCFD94FsWC
hY7tvGZFmh/sSAshBY2vofIvtZTx6TY4vy9fddp6cii6CYPr9peoxPh8jAWtezPvk1mE0OCGSa4t
esVqYVjVIltMacXgU39UUK1aR/kznUPPCXb9AN40OOlhgtqhbX2NfvO61F7Dvfj/OZy4hwtSRHlZ
4407PLzr1K4mFhaNnr72WyKjhpqIkjTWXtQLj2CwKbpeeOjV8x1tCnLn2xB50nb92Zq9iFHhZf82
dqhT3xLZKSPipy1EF0Q4ZAXG6Y7ekWlFORohAOui5yuckdkp2e1OE6yzpCAMJYtubggzl9PEsuUt
9xemJrF/LPdEjBLg0UD4eZ/fWnlx6hhsZBcXsU66a5NMu3VImE2G9ZSeJKEmu4l46InHpwuCgvmW
AN0REyfzyE0v9GuLBj0WBNlnI6OWdbdZF2+vsNQsrWorcMnBfKI1vGF/QcaKDZXwSpT+u/tulSDI
u2+kHRpHcx0s6dpfeaLdqRVz2mkoxbdjFe7Tb6bUJQCPVUTO+Wy3YBQezqtkMRn/i6M0XBRLXt7q
9LRK+TUwmR7Tg5N6Mgz47q+OohSgmDOXkmGEcxJFEEXyFlea3PaOMFyVq4Etqrh1AKIToy6khYyC
3WWWwEnvsBlCwwjkLt3k3rLLpLypEIVIbuu3PFilFW2vooh54pOypNP7Mn/RXhluol2WwsJ5/C4p
vtUWN45hgEExIBf/EVeKxcaE+uZbwYef5T+QNoEgvAB1yg9FPJnTIUgKJuiIATTe5LutXmixPsNT
gVSeexC2bnBrrrDBqkZ5gQKhziR4KeizoxeXDupamk8w8hqtLph6Gge01iy+uCG5yEyDOe+JCpqD
Ybpm6Cr0FAoWm6+8iwDXIbDo2ZTYFOTpFvOl84yu3n5sZggyIqDSaV5sKwiHDSDxv+KDP18eEbRe
DZsY22OyEXgTk2yB9JC1aGgl5ZJaEy3GUpRF0ees1oOSmti73rs5mxlm13wtdJWp3jhkqqN8f4dv
Rd2y3Khps1FvoZLceTtqOIpTUg6PhOCmeVuIRlcTkWReT5sgBM57QVI7M0Gq+/23eysz+WmqY1iu
yyOhJICd0uIAZ73UsIZ7pjnX0FhidbDjBkuQ2Dg6sbmC6tC4KOPo5mIbgfmZRj2Vs13fYzu5Jksc
bW1y+Oc+XfJMNWRkM5uWwvYX9tajD4q7bz9ygwMajkIww7WqRhpugSw97XxcXrqWBXp41yqGmKCl
HnIv5Ux38P5/NxvQ0ERcvmx0XvHTvexD+34DShUWRuOnweJmFJyPD397DZMRUb6vDkhu6BSsNuwT
YEPY9YVqDwyV0UBHn79yU9y5LfN1AbKgF6AoPKpuyhZePeSeJM70yEdhxzzpo4oj54i22/CJs05/
GDGdGFMRNiaHjdjE0fXCgLpJpHBkFldRzU3EAMMfN4ds9fZ8hkkY1fixdTauIKCIMdnBTd3iNb4l
ltdS1Z59utp4bLedxZs+bMyts94Q/nLiOVwresmudj53oNsKvZp3C017ax3j85lC42Xuy5rchba2
v1MwGME8fWEcz4Tg4OEoAVO0JZuNiT844ntcbaldIuaKVEo9mbNwq/HPxV2kr2ZmUcQtI5/IOWfU
+5NIT9KCU+tXAFXJuCfBgWOYwpMn36yiJmSiMtlELZgTQpo8qS+CQo3rkYpZqbm9vT1cn21Ufr9p
+iEO3ewF62+YCrRypRtsQEecoecp3lrayrDdc/a1t2esqxquMyIwkRpahVaWxEgwCtSkfXjQ+xO9
qC63u7DF/xE6bnaDXUi/Qa7BCW2Z3bJkfLFwE7wu1IFRqGlUPGnjt0GUMXyAlLIqLBwBNxYIR/+I
g7kkV3TgmhRVAwrwxtNgdYMMkx6d3amgUFeCyj9yySb9bnihLSO2TPMQd/TycO3D8v7IkffBtDiN
xT3PNtmrSCx4vXMLMVm80mxZlILblHorcsqCwn4NW0eYk3R2miGvY3jrsrRT45odR1yM99kaNd8D
GzNI+YB4uwB7AnFRi97SqqXBhnNZ6PdeY9L3rbdxXCyybBCdEoKIGNBiWyqfX9L4O/9CbGA+SGVf
VydlxUJaFjPZOjO/zRDd7LPDaeV1/tMQBv+sgZTDZDPEpdjz9DsmmQ54kmILtLwMuchFUcLmGrmR
4zme0JMNTZnNkBe4fIXS12LB0aJ04Db6B39HYceQ5gCOcVsi3i0CM5/Qo2YWqyOEMnTuSTQifcj9
GogdNvS8cd8eeWo5pJb3FCfRivnbBBS6Ic2+kfxM0vyEosIZgOnaC0YunKzhZXPWwJgXtp/1u99M
YsLSTaiNMdDdtesn0iPUoH60/G8t6SvPOrP5xbqWL8QKQYuMBvq98G4ANEMBurXdGz3S78hwO6Pp
Qun/4yy4QW2g6gJu14c/cb+Gcuh24AdRQassGWiYzGmmAojHMkya/1RMB7yBYEjyxyZffklQssPZ
WuQD/uQuR1kY798S8ijY/DCW7zJxTPlGSommm+3Kw536X9Sc4ssENU2OUspEEkCbr6L+pufzDjyb
j3oCwExkZX3SOWe8S9ubQYgXueyDMpnvg0Hwe2Fabjj8UhgJIT+5//hX961c/JvEm5EUk4dKl39s
64Z05lwyVK4u9leedk7qpPafzCUuChaz2thp6hV0mnEXaDKXmeDCmyOLwPSSxdmISJtNkWAOim8g
rpqA8m82qLtQE4pM5roZ5MzfhYFCZHDx17h+YozQ1hBymG7Vi2g2kSL1ammmw4Wf6fENtFbJu0uM
5dIpy1I13BN9SVj3FQvLZobGDqYKCxhfzyCp9qIjMsrcToIEucL38kWwwRV5LPn0hfz3c1USXmit
FoxlomD7WPSD+UmyLqHE14gwoP4hkACxv2H6ZP6PI3Gk8VqY27mD4AKrncensZ0LxW9Fju+UlexV
Ari5C0YWGmjg5GS3eJEx08YNkBEktObk1UIPUXqJ858moQCN+a/8OMgsqNi/WT03i0Ji7UdV5Qvc
mFB6tPHA9n2dOfx99GmSHSzkzJFRdLdBNFDEFjJz94W6htu1M6txk9PY+hxZoDxmpgtGsqlC/iMR
+IN5aQdirEU2MRnw9c1uAoD3SSZWhbsSnBbbG9KELYxYET9s2B6iDw1n7xQLlzmZeYrDaurUcxuh
TJrO2K1pM23dVK/aL6/8ILm4rSQATqlJnSVvIdGFMx0DG5W2W303CFSuufjoVY53ASRTD1EwKPv7
QYKIBMLz3brszIk45rWRvTfyB+kMrFOV/OjT1PpPZdIl87XegzanwQ3wOW6nVxAaI4rrpXJbHJRc
3aZ+0jJL0Y9Y+xSeDQgKFj0G7IdDJFxUQXu+KYG4TpwHLCn0aPSXwhuCAB/nnmwqYwsuGS+4M8+y
FdH6vhbNsmf73kVwFmOg17xOjz+knV+u9oSgTLD2PoHpPiRhwXsU/W0/NNrzHE1kReE/nobZRd9/
4aq8I2f735t/mHkiQNAs0pE2aiqOhC4BKpl2cWjqooFHg+0whW+bNuA2HfXcPxdR5MUMjxt3XGOh
Iw3w0p7UgyGd1oRrE/zWrSJJO+FEZ0jwahf7OE7VPg83oeCLkCKjjZDpNdeVOTAyv1/LTttY45Im
N8fJYjtdroM4L8uh5rHNKKMpwCl3fN2LrL1Kus7Qlb99G/IE4CjpIpUewSNBXS9Wdszj/zPlGU2J
ar4/qVWirp0UXriCQhjjYcpaX1RZ40nZgbQAPWThWK+LqsDhCZwSzd844qD920X2gzeXjqwE0bLy
UHQQcOvvtPTOu+PGiBr8ky9+caKTA8Trb+/sltsgVzw9PeySpVDbV97XVGTCpasF64zipH1jHL8n
z0GbUimgjuYgUtU4JrM3eB9Rm58DOms6WQftEGuczun8D9QT1NXgJnB+VyfJ32PWUOHcB92C95Ar
sdvm7d7nbPv3ndddL6G7LlAF8UlvfEEKO4tvXESPfCmjmaqWgJe4ookNUjNe23dKzdhZtyOA41+B
z5eN3/XwXnn38jK5hdXiiIlMVN/Lwk9ypmXsSCsbyhGYaq9fd9gbKfHC77FptB8NE4ym00QA16uF
nhN4A5PehCb6k10us8uvpbIFiG1S990HI6z1PASqi3uehxPn7AXgX4jByLnh1/CKwj7JoQTSKHw9
wHC9xISOwHHJ6oS/MDNvGMNSASH2O2M4EJOLxVkQE5iQ6D4eDWTW6bbnHm73pkZQuk1I1jCtmHwY
Zl3p6uVtP5EVZnukYg6kPz/kLQhaAGJzFFOglB5bYLfJtfswPQ9j68OLbRoxibVYeqU/thRdG+tx
4xcp2e/lHyzWLo1jvJRCWJFDyYXKekxwi0PLXv5KCOejmZ8BHHU9OkN/0TpflrVCKmn77GNAPBT7
6f95eale2hFOwqIyuYGkXiR9EEs2l8oeYWH9yotYmiGvyDkAzMxKEFEgZv+uU2PVanzTqs+BpYYS
ZKA7GY37rTIoi9TBDGsYsfYu3UHDMfGQNQ/cjaVh23YvcKnjAmEFdlnuQKYwqExFKaxc/A9Zmfup
x7JsBQRzwj0H0z/+3klh0nQW41Oq4Z3JnZ2qTvOuT8s+3Ce53RdWrYqHdUcfJkYwqz31nAKyEeSm
S70r561jI36+sa/XokOJAEzJTyCDrPXsoKRdkLTdu2UjfqwF6ZAt9PXpKUFS8ak0V/XRnE0ejbwu
2Y4JvppRynZUUrasShlpCGvsFpvD5VgCIANuwlW+jNDM7/4K2x9vv465TQP4WFp/USfGRsxf2PQk
sEPkJJjm4tAEUp/qUMfsYMAgd6874wp5WA7DwNZCuxl6n3LVjcttBOWN7hbvE9iedkxBbrQQKuu9
kszsBRLL4O18wRyc2ijpHbIRluIVetwtxdl1QMjyuf5Yb9chL8wZECOqKTlMwW6uaK6Se02w31dn
Z5p288DT6qGpJROIrvwoYN0GO/WdMOgTYG5sZtYdQ/jkLk6GoQV8yMnnNWGrn8Juedp7rtiHoqhL
6jpE6e6jcs8dgI554b+B8pJCub8tjmMn0Ton/sGpfp5ptRNR5gLeiJhr+rZbXRNqXYkfRN13L7Ps
xmhZr21Ha7NaOMAzPJNRcHa80lLoOa9B7rYGJf04yaaoS5tfwQpRhcxTVFCh2zcZdOeuj4gbOtJ5
lP4b2/keg7Vj2RvcTqdp3f3bGaC0LATGTUUDTv4mrzjSPsICHJ5D/YJQvG3FCKpK4GQ/KkjPJqpY
tHE+iwiISh7LLZpjda9YBAN3eAMqkvl2ejn9QB/R0Tx5jmnnKjkCuimwzZKcWIGyZzH6PmGO/BOH
yQMY5nIi0OxAmspQyXecE+UrpvGE4kTowlXV5O1AMMZUrm9x7cjFrYC2sSO1vVl/32LdfG0CAHQq
Wxr6ANjAWBcnZEVnfDv/h84VI38RgGCil8QfPn1qyEO543l0O/7bDS3qE4Hp19zNnyNO5t+JKj/C
qjKIvkMiHJidndxaCzb3Ryc5zy2CY5ZXpJaItr4SJZbLIR+wiPiq0ZChv3KAUIwv4ICrHknb31bE
ibW2MU14ZJ8IQ4ISFu9TDaaz7SRlehRHSvcKpn+N7ZQv+PgPSz+mGcKBFdFwS7Pv74JMpyv77Yy8
g9YA9DAAjjZyFYzqHcVNXXwMffg1OzgJolDQNIbuAd5baB2Njq6geRksiACjy23lvJLOaHlaJVHo
hfgCYujNO8SQpDmxfxvXOTMxXJDw4GoLSHjq5QFc70o9sUFCMwW9+3MIHtdHtIj8hhahA/HJIsFK
YOrHrIBQVChoV1D+bfQjoYGcZyJTg20k7uk421iGVq1U/N+ZMv2rwB/dUDJzfiA5vwi5H8yy7SXO
aDSqwThabQwTcm8VH6TwpYdyjyxtHgiLzydHqJL4S7a5A3wwgTc6x1oF5rlCDLTjDQZuUhM2sm+H
iIEelpWFkEEogQxQyf36ztNqOPz0YgMvRmrmG7rHFPESRLE/e0m9XiocKIIOIViprUE7UGCHzHxb
ANEyv5CvUxlkZ9wLaMTyEATdqo4WgZBZ4J/qk0ozoj2EgBnkT+iOLdWIEMbys/jl5pM2Zef72UQ8
o/jaOsaPVEi3fs4eZxskGp0Oqrj39YMUi10mQ2mw9awXLdYtiLPWLzBJz2YTBWhz0TM3QNlCj3Pl
AmpmICicOPJAJIjBS8Uo9FDQlpiqz0owSCxjPARWbbjifCwsQKGgYWARSJFaHCdjAtsfVm0B9NLK
2VzGOqTGWPp4pfyNB7zr0ZWgUViFn1CpcifJTxhgzl7Idr4LPCUdzZfR+4KXbsLz7PN7+ttLbS1w
zrWOayR6ir31NUAsSIVAXpR1j7QbpgrV2H/WoUXhEPDSaVzLc+q4oquuy93+IETXjpCQyJWRh0x3
GO8W95VlEgcLbHCiIUslNXWUM90rD3yGvQGs3VRweSxlJWH2IUL1HJoxKNqYEVey3PvDFAuuwmRU
Qb8cN2s1BUFR4qDMhypRG5NfVn/tcdX9RaTAw+Hyv/Svy9lR3P5feY7Wiy+YGJ+eS7v6F8RGng/3
+Csc9NKHO+DTE/vNJ5K1vgirB8Chai+CgmF0AqJD/iRh9qScXYWlvuW+Hx0bxJ+1gZ78x1Yap834
TANf5u2/6uPKYA0Ipa1B2oc4/8Hx9F30dW/87KoOLvg98akm2eMJ5jGm3V7ggXM+VlqxZ1dpbZ35
7P+D9nYdcXesTlfXdRXw37ZFHZ8t95Vph28LOFjUhC7S7Dl7KWGRxS/FNDXFlIHC93gnTnWjqmpF
8cE+pOi9L//cwa9gM8zszQtRQmfCf99J0hWiwqpHF6mUZ/CaPHR0BZ0DV8RKAP8yBtnIGDlfSiAT
Hqfct2Z1m4Qbgx/LTCQHbBdQf1RizHfbJHLsut1s5q0RJsXiK+Jcb+jvXBondtzzQLPxYwzxGAuX
jDk/LGs9QvR+heDARGQFXpmY9h5iMaAjJormCPoyYWMN6niGXTaZkz1gxq0GNWxj04fAqzYuhbPU
UWs5EbfrmPmbF8ncMIDUha9zIu3HHs6Ypv2on12v9MYCosRfOB1LpmySnPyMaPFWQdDuXmRfl3vz
wAk/vMnt6o99nD7UwvnmJ/leB64+4f36BAdFicw8n6xSkCwkqa6bWtO77Gg7nWVfEkI9Y+FLnmWO
eql+WtCVvxy7u9vSj/JVDuBPa1otEEMtvXb9IQ9tokjyKIKLwuR4y1LP4ocOELIpPJT+KU6JS3Bh
dph7MoggIr0OpjuUSMyqPmo9grHBqKBAhDGJKylgsw2d46OF6vmc/s1q+OyersY2Jfsml/OjF6gj
39Idmo4S8gvDzrA4wR0uirXW+cNu2GiWTuGtfUirvKWtK4p+Rz0ozj7besQ/yQE3Eof50iI0fiNu
PQXpxg9Vt654QPfxxY70gnsG4qAd7GYymGppMqqyEdtqySYA2pxsPjkGidZqcljDcea5REmF30Qa
vMC5/Qs2mvj0TlCwXLft5LzhnnBYXzoHCv1FLMq+RJhfK4cSE2UrYaOllQ82og7JSIW+QV9c1DeX
LxrsEMyOzpEHez/0iix9zTDkExYO79TxMoql4mB2ce2vScD5SEndtrl0d/p1tvFhGodXiiCr08nZ
Jnv+BpAfKrVNugj5C5uwEiiAZ+JIzVW81qT+7f4Zv21D63Y9bonXzZXgp7m3U187oP+fGEYeNfB7
9RtY27evgjcCrAdSOFhTQaz+FFUOobR/tu61DY5/43Dt5VM2ZbHdBvb9JK1RILGikRLHUuACXedM
+w35wRXwmfvPFnZOnZe7OmICZqdhvPKDGEemJqFsih72/OZIM0CmZWR0rNrHzbUuUtojtYz7+Ztu
GMJ7URRXXplR9z6bRwBtenK4IRdDlM7BrC5i0JoFKR4UXWAEUUt9e1SifV0cy3dLM5151j7Mijkk
Qxo3LirCZNe4oU2QV2eJf3ijJap3B18BwCOdknao5cXX2W0Ri5nmbJJwwpV0kcL6/G/c2TN7/Kv+
AaCAHkMJ5KAzeuUtAWPEpl7xi4ijnNyHNDDV5+u+WbUqUqCwFowziIqhCFN9i8IvcVqqIxs7351Y
O26RtulrmPvffMf/wEvDit54ej9sT/ATptSsEBqzatSbd85G/7eS4e6LzlHh+bze4TNDthzuOrVM
5vzYcDzla2W5M05OOO9vlAr8XzoriiQhRGtKmMmNIEnawAIgl40BVGSv4VLGspVOoItz/awgxjHl
vG9NyOKBARCRa1UTieU7ALD11yICguvSdWWct2eqdIMi+jx9g8d/A83SuOIZkOJ1sKTsAe15p1dn
wBLC759+ak/zNuXzK9pK6Ext93gH6yP33FrQUT+xFSt/AqmMurDHyPXxk/bGwRKvpWZN4/IU6mdb
lbw2uX2lJU1z1vNLZ8AHC8SLSSSMOql+ra5Oro/7SjQW9xvwTAMA+0vJmFhtqUceqd/MhWWJUcSI
Fc0ihLH5rqTMgeQSefqvRyPhc6DskUZHpjUPPQgpNdmPPkIE6OSU/6ixXRf9U0DqyRwkVQaXvMo2
Bp3dbou0kQ4AKEcUrNjWp0NFJJFoTzlKfHapAnp69/oUp4zMonadFnG0g+EcN1cskYjIyI1k6XOi
mq20zesMxTHWaN814WFMn2PQgg8CBJiszJ9A1hBAth9OqUbMcqBY0LcLIHdyK9tP2LnQrFQObBds
Y3qIn/MUqm3F6mtTqP/a0wFFA/alBc/hhjvkmxXJZcFv+TgnsHOvujPgF7JA3gU+O2XJI1X/09my
k5H31Vqc8DyR6B/SX5Zt9XAhw0Jzbn8pBiOca1xXT87f+mf4CWIx4GVH3MK8oZCgg9hG4gM4+kt3
nZWF6UPNb9aZrAmF1XhdK/6AMEkfLInjH+5OPItzk/uTwHsCm/KLQkXVlOOjySsWTZI0lSwxtILj
27Cvt2Y0B85Pl1YJD3raT4lj9sWfMwkfCJsfDG3QmwOM5ZF5MOevGp+gheydsoEpvMUGH17TmGps
JZuUBDSraa+fXNzbwXESSPgQZWFCec6p9vI15brYl71JBBFwRMmeZ91IETjoi/P8Df45QuweYJkV
hZP3PsjJwn5yEPxvAztLCSWNJ1lN/Tog+qmSALjQdFp3EeQhlNXfGGtdhq6QinGy5VIKMxVQvsFG
XLM016u5htottbHGNBC+9rfGLdhStfjF7qgSNWjZi1SmMUhGiJ1AaT3hSvCRIzg3t9R4JQ14ktPZ
Qh57XNcrJcXmjzz6SPy/yd15ZNUzeA1qK+G52eNqy58BbJGLHiZ/VGGbimtVWIXDWPjgUrEwDytD
oMDfx1gFQW6DLyZcv60/0M9/D0eS7tmeHCUXHkAkNObgVz9VUONVd5ZgEbEJBUeyABFv8BtHWFnI
uHqJ3RIXKkFUj/bnGChb//vQS5EvFL8qDF7WIUaRAY9xgLQKlIkPnsEoEw7+YE2vVV6OP38Jx9ME
O+FDqHwgEEFOHvq0r1pBvVXEM3kfdlbEj5tvWZsUpdbVu8xZR5GpG+iWtU0AShTEUDpoFE/sM25N
TuHy5YosJKEwJUXXLTz7P/3FMbaOlZw/oH02OHt/taaSsSztbTj43TYn+ZfnP5sRow0bPHYYe8eP
iOzCh9txXO9Fzd+psanldmJRi8jsdgpXTBzAuuRDneUayGXNUh5ayEC1X2rBbsKiHeuIgqn/CCxR
SzuM7vVRXec0oxIOBM6SewPnGPS1TpfahHU1XwWNe7mBsHLJzuPtDPaJ/Wpk8iTVd7vqDWuFohik
GbYAgHrvOhi8p+gpLi55UZ1JM7n9u/WzR+4ZmHSqdgE7vbYELh4yQyyXcWj82NA2h9CAEntJe4eF
Hu1KVH103t0CV6rsrbLyLJVnOnCluL15YOhGhWN9aZ3gjRvTfKB4yzEzbfdiWRN8+sSyyCvIlzoK
DZQT4Bq9V4nJiPKHr5DmOtWDMQc+EnUW3EhdRSZyl/Itu+GbLlQ3fwTEpjiNen7WzWQQnJcuGADj
+huFKck0y5BA7b5cUmJ/eMh/nckF4dIbKQDFAhqMB9xoU6mGf5P0xlAkZOiRJEUdhWpI64wTNPsb
AOvVCVR7Fjcskntk3JXtbBn5NK8gJvXVwy/oFoeIuOpatj0wnUtvpODo0+jVW9lPaUqugkp40FKX
UUDM8nYu86X7kZLoQV4xbzecd1ZWvNpH8+Zl6Ag+RI9gumj6pfXrbNZ6yD/rLtB+PxxtqU5pvdB0
6ge+qTosZEXFxfYoIE/GQnb8bz+Ty43dQmjbTeI0hT9vqFB5bemRchh6Q3zBZWTlgHmULYRznYO9
kLuS/cReloVS9NiDkq6xwnTofeJE7AR4HbMOmxvhBBeqHu4+i1t84En8+2XenMDHmvXFHgIpl/z0
r6VALBNmULBO5SofNkexLhmIQILACAXaNSLHcxHx3MHBd7eD9fLn43rARH/N2awzj9WrQtWPhcRT
jlD/s23oTxYnt4GpDTQt8EdUZN8kXB2VLgJdQQKi84VhpkLUplrAtXoHBeVXyOqkWCnJHxuQQ7Fj
z0JBf1WV5TxinExXNzmayzkd4ao1rkUyOGp0dI4YeVQp8esp6LjHHuOa8rcFnEYowgfMOQlz/+NE
UTc5ftrO9xpgxXBsuZSMQcURZnOJxrrKQo7tn6Q01Kv/OeFcPXasjyhestrFhAHFZetjKpsxTtzZ
sFvMgaHLO33wnIMmBTC7g564hEduAsFG/6kcvBCSNsdGdMU86PBcmcL0bVAwX0UUXhK3amAJ6Mhc
pA5N9XCZ5fkpiE/0Qz5CLYVS+dDtkm6Y4W3NDOrYdmf3LJSAU/B+29Rsd4F7ekBHqCf2ojLRszw3
e51WnHcmn0/rWweH2YGxMoIPTvKV4zwnqG2nhOvSUZrRCpnUtg7g+961/W1dExOhph4foeJaWsFS
A1j29vQbXmJtyJjb2EZIEDzyqxzLjSn+5DX8ZLYppgJPaYE40AgIDKW8IYcFrMM4UC/C+2J8M1cN
x+y4cJVmD4ekUMqNU00vWNlK743z3Xqum4o3ElDwornaOHLKijQRefT57Ke4vX7x71r9owxn45q9
v2UtmfRNMcDOodNFBeOFHEn3fIZbLyH1ZwEcTP4i8eirunvxCZZiMkx6l2e6uBBkgaTnu7xgtaI5
YHe8xtFIUSZzSPBDTRhOSQG+zhoSnrzS2tLPL4BTbE2V67HrG44tx+gQ4k1GH1m1C4caCjcg7LrC
PE6DVoi1irQ2vcSi9pOvxcBv0XzjTKHp9PXIRj9JTNio8pRB6dHHRJqNP6dgUFC7a+MP5PI5A7o7
EdujrPM3uk2/pgb0CengtUM2q9qekDl0yRiDsNdnuhzmD6cq2A0H2UM4/PEAiDROsVUYX7M99Z15
Fxe+ZN/dOzDS067T9YYtBpS+vVx/Jb6AkKqk2mCfEJP19twFhmtdxAkFhhPQXD8C4wv+EBzJVCYm
OqMFkPZEzGaeic7PWXZIDgibote16KqaJMa1ImmsBBv/q48neHmeI70CA9HJb1c1/+nAdUk3r5LF
ADm6LMZ0dVQANbs3kdHgXuAe8i6F2gbQ9KWLYrO6gE5FwApWhWuyGYo3uEy94NUWdi80cm2B1klI
Ht0AFBiLfTykarjAtitGHfEbUUqdtxCL5oJsxQeKjNUekq9sBkey7z0klZU1hsXf9YUBV99By9gT
ijJH301fcYDbLJncGzN2xmJ5nt9EVRFxGTQAV0UmJwCLweG7y7gAOHpzKmWffCTDaSqsN2vZ2JN5
BVLFLjnoGTRfRC6lWEwtvpxpVR/WWXUwnCuOSlEFwcU7pBupeGFZj7n0Wf43rYkK7nRfX0UcGbsT
I/iULl94pkXVNBKaj0xzjEvf/G88gFLT9cPAGpBrC+8cZvqg5tXl/rlrC2nVW5Kmj9qCC80EbQYi
zlHkqUhsChefoDQI7xA3ZM0jsP8IxznhetZ9Ok/mRa5mXow7hc6gVT26awVvO3Z/lBYZmDe8TiC4
A1lX2O9XB1+CuxWMbdzQy8FxkjAo3VVqlDodyuQ3WKo2987L8ulgegaLfOfVLSuAG8uRzentNWUg
KlSPO/IxDU/UtPoiHHCNJSe2Uw33eI/PM5t4EirIRuOzd4ghvYsTisNN83kelz8pL5xmC78HyLuT
nxyJRODxXyC4Q+AaVL19YrPPqxLtsIlZXfxvNWfx+FRqsrosDnGqxPVA8bWYqrD5BAvsn0+juokr
Uua3q4Tj8n0PiRUIFL2Uus4pw+hoZYmt9aJOYNAV5MSY7kh5Tu30j5NMljIb4b/m12IEm0GRBt2K
3FciJwb6zLE6nLNAvfFSmkWWFw8j5sjKStliKL01AnGxnKsYRju4fd5L0Zm+qQQUEGNBMckUAksA
Sj+E1v1Co5Xjbc6XFnOdUxslw7upSiqlqIbjyuqRmi5K5vJlO+aV6kwLrptedK8vTRURGnw67Jtd
DzqtKwZr5iPxW0OuCQvRBW8ytc8Ic+R0iwo05uhSG1u0xZT0hdUfkKkniEgJS1hNHU6ri7z+5TEr
zcoiBWXPI0HEoSimtdN+9T4lN9VSsXr3E/tnZ33WpjjPeIweE26jK/auL2Sebyce78hp3oYolR+y
18NGWjoKta27fV9YVESQlughMQ7L6k+qrHzzDhXSErdmIfJomokTxKUE4hhq2bafhN6zMCHmoOLU
R4LVIrmJeIq7FjqCMx6xRMfKha80q15mKxQkMeuTTYWev7qK85SqLh1jNlYg1DzRdf/43qtrNifY
kBfKpu9U6tNLQeoxIaHO89hYh+bXBAOsiJxzWsvuiLcD9DRvDvUx9gGwEbZHn6BkXy9VNU/MzRwU
taY6o7dYZZbjnlZBDk/wVnmbHV7ipc3x2ZViatC6QyZP2tKll3KthljyGpSzu6c+RpZ5iJjrNrvt
lcwQlpd2gTcMqF6UZ1LaKsTATniyyBRUk0yAsbksM/1MyAA589N8OE0srJOwUW5lhMle4eXr1XR4
GBKFLuRCpUIWIPep19gH+RtlWdBnJHj1Lh4alWxsTEYonHyrs/Wh4viFYEMvcDZAXqQYr4G5GqDU
9FiwgCte5fBrVhRiwBncsc2feyaqLIs5ksA5II+xzQZHGzg33lfc/W9tkdNI8DtAJIGnOu285ps7
+4SVUww/bfTd46I8fgsUCtu+CCx1d6EINH5TLnjvvkoFTAe0xQT2PnJcMsylO0LvpQdRF/Ae/Iav
zetNz/z2QPp1tqdqMakcghkbCkE6JG8cW+EBBnRXc87icC09kB0EkTxva19Z65jPjPUgMil8JfiX
HnJAyRkIQ4c7FN480KkkQbpeIBBpIoAbZyRNxjMqcXBf945PNrkfWp8lbHx9tYQdCkUeqpD5TNoq
gPCwlZiARnL9HmMwWbE244npikesv5hUlt2566iFVp16S3iJXI0JQW7oPfUcvEt5pzJJ46k5rfQ1
4MwhpOhfHlXKAGALnOkUkTryOxr98xMw37wcMff0pmrobkJTy8UV8Hxt66Sjq1F985BuTqJY952F
DsTrNau40/axG6pcTgqVHbWQtQCWBLfC3Csh1r+z3A8sXTRKRebnUZpTImSa+yfm0PAnXqOG1ROj
1f7f1T9o+tEyGkyIPbWi07AxUf8ByPRiCq4h3URXBu4bUN5jWjvTW3TEfNBjPQt4EBZR3vd0GpqB
g+HWYAKlNolLi5wpbelDCLSGZ+M2ApiduzIcX+FZgKUkoKeQOSbkU51+jjN6BVPNl01XGliiipCI
ApHN9X0y0IFk2v8+vI1eYe2poAp2YggexPiOhmIdZmQh18OBJ1XpdTYQXpaTzvJ5WKAZeWfEdlJB
KK4B/ZIbDfzO5K1/27cjmlCZhtx7f+ED6SqAPNX0X2CRH5qfdsJKuYNZ9bc8tRO6WGGS6Tu22PIF
HtrWQaFitLwSXDd/M4+KeqJSprlZBn+foyn13bUzdwaM/qoFpw7L/+18G099sCKFDUNDx3H3b/8Z
CncBSNcIH8PkEGffJtnitGxUIq/tQFsLbtabqW8tHQkBsBb/SD0kYy8jrJIrNNbNngNiH3IDymSI
hTF88fGU+itGDgsXbuiQi1V+Ye1orict0GLV4FLGp2WUmoNXn0gcmiSn0xt1fd+y1ISut9YVnOrc
q1UPhCZiAYzcaslF19FQx5gARyUfv2uB4AX2qg6Kfh+07nzYsEFmIaJIK00fqdxbujnliXlDedml
CFIMTRvfCgYVAKf7yZVFHu9sGEfeSYRpN9MGB0V3hMy8ftgexKmMbLptEKO3kOLmELht9Ty2SvqI
LJ4KEyGuvRMOwz9cI7nX8ivzxu/aY9QAPFLzMqn+hJY328ZcXiHRrx/TAoE6CbqPh20Acg7sa8lX
4xaZh6JRUAGG1WT1iUAZ68nSZt5QMMGmsGYS8m8RCeewWiPFCx/z+jUl4ETaY/xfB+b/Lsyhp6nd
bFH9DJM32DzYYsOEJosXPzswVOni8DywBpbDH4oC5w2aStkMuFQ6BC9swFrg1QlxlXY8CdQUk0GJ
jai4wQxw/jLSsUelhrfXKngmZ5eHaLx3EUC/r7Cv1ft2BOugdfGrP94hzpOMsWqalwiJDr9I/yrI
J0f4kfyBzTYR8apa7rXMxi5Wb84hKBaeq5xjjsZfxi7mwuY75rn+Q75vCgfvRRtBeytvHDpTrX1K
/3PL2iaa4JuzCnpygLhreqpnSf9ngIF04R/hM3HaRyfCfnPLlpUwJ7ybdb8I0YW1cJHLO4MDgpob
90rWafP0EkxfpXcDTEEoGR8P0zgJFPe1+QTpixUxOQo8J5WmPQnjOVLSPFouFFfo3R9QbkIp24oF
K00a5XOVhC7synmRK1RrGvX+3tA+U4kmQGN2QrndCyAQSZNX1yd82q5JpfVDCtv0vm+Fguq1CJ+Y
pHD2skMZQwkur0zT/+fHFAm0cb/gFALsnxuXEnLaahu/IvuKEljrHvHPWaMdAx2coW3JVHUM/ZRz
OUwRwqXVnV+dsDzoTdmHhY0z1Q429Fql1k/MIcsu0D4MuqeRHMClpWEFWHamDEDMG8FsEQG/CNmt
PEYwg70UqKZSB5DXUYXZVetn2HVMTlpS6G7BRqTTWmw+E/7mLnMB6zza+TFj4b/oRFsfgIFb8f0+
PvKwUM5yL4CwrXkqPg0AqnDZkt3WvRudE7mYr38dvycqgzq6bS8J7gkx2glBKU9LF4yCqraVCzRc
Uyo4aqKIoNhUOVLkuiXc4CB6gnMnXWYEzk9phJV/fyW9BchNZyfCDjVFZzku8pFj94QhRn0d2e+F
9xPpCeQH1fPR7yZQTRGpJPvHbIlDL1+mH34SByhBWanu/aTcWsyaZtjK+KzqsNEA8QAtCzFq0mVP
mEOvmmCS+WcWy+opU9SsJ9DI/V+rZ/VFCMG0jMFPPTCUvztryRydUU/qwi3TKKEKZwxr4qZf3gyC
K+3pDVMcHc0dt6PwCnpE72jLxFZKjg4hVCEMgTvc7+yUln9oQkn8I5oDQ6Yj3FWZhyGTfwP/wG+r
9H7IK4Ia3dlxD98FILUEi8+V9qFHbJo6Wp4WGBbSx4bB0cRRYsZQA9VMCWWog195Y49g0xEcGdM4
+ngeWeJ1UzxB7WiqPpPkQV06EY/Kr6TmvLq2xCvKwO1iGUGfXUhhBDyrYbi9gRds+2sJSGnwemgn
L0i4iLCPQzUEEkGjYQJEThb78uT9fdAvrWDGoDb2DvADUztjXMXnqziGa+3BBhhfnQP2cI0raRNW
VsnpUw/BQ1jLOS9o3V1dNVDzLVPw0/XCO/RWmSf8h/5bdgsISz12L4oLdzRl9s+Np7gw35vUm4st
ko3f+WKQFo4XHkvSmYflbfsjfj7CQpw5ru+z4dJAqTMJwNjeb/uQf3ItjlE8EA337L0CqqFbzAxo
Fl2BGaq+fUh/UpFgNT2H8XalWPJEQn9T3GDhTxI728zEL4F2M0D1w3BiNNOwZWtZTB6DN5FAIXT/
ynUWUdO8bEd1fn/5LOe07tA66DwrWDX9H2Rh8AATGFxI6uI8E7/mRMJSjAVeW/+itYn4/5roVGNo
Go1+fw5Ww8xlJuyvq2TniLT6pKFwZR1d4h0kScg/pVbsSFpTrpPEXCL3BFfTjtpClwmOm83qch5p
YJFDff1YvmXwHq/ZFTeR1+JdjWBklavNPjPWxUy5OLwjR58abL7IWM/gTj7mfNt4AY1Uii/G44/X
prxFPRT03IwfpcNl8UYgpUqyratm7z733JNzywZqXzrl3bPZRu5zBmYXy8uRyZvfany9K5l5YQyp
N1gZMOpv7kwLA/wCT71TlYOz6EhJlPXBLVWmog5q73rPP1+D8f7LqiXoGYWMBRti3jboSeXQGNex
ibocCyzblA336inq8Ry3AD0kYgmPLpuC9ZtuFn36/vngoOr9qWUJhbulguPZE/ESvHxt5UfkmubD
LdhsO+jtwG4Tm9tns2kWQ2kRtAmDPDQ9vSZ07uyxGAs3zmRvRcYQaxUdcyUv81/61jsLlF24/4fY
FcE9S0caFUcSfthgjkWveer0fOptO/xaD9uz0Mps3BknoVzjgBeTpJDdqLu2nLC1CvI69hBiE6w3
TwMhWcldByI8EQGfsa8zsP/E1FxOjkuZdxEe7uhaWq16SFttGNBSZW1VyOGLO5b5k2Yi5kwFMfAo
Mo1natL/MqUraKuKfcmbC6msKyBeaqvn26Z0XZ50oNZrIM+r+1CUDDQ0pdBJJly6h4X7fMzCDwXZ
s9QwxCarpjX/ty9eby5sssKbinDsvy7Dd44TZWeMsQ1yFqqLHoIjhNOx6dDYhiJSBLQKo9+ZEOCr
Hl4RCtMBanYxA02mjXALrk4NV5p4w8Epg7nlbE/GvOMNN3CVsZMbMNQKMZBwAbUNLa8e6TzebDBi
BILlrfjn5KgbEhvqLSBCOGND996A0/DpTe3qQldtQk1jT4BOZERaRLiZR9MQdo6A3umnz9CF2Uml
YkQ09/w+duA4wCIkRrE/7y6QZ+r1yXUU0L6UKluaexESvXfYu+IoIxNuHNqjXaqOiYQ2KqpHzuHr
3uw4V5rEVcapgn/7qh7+3AO7HLXDmFaGKgNN+5S7Z7rGycxiD5hwhJcP9CsaLf6yu/JSGlGvctAl
dICWHE3iVyPE/ELx5JGmcqvXuRPRfPzXk+QU+848iZDP3CV34NTnkbk0iWTaYqad4kBUEEs4PRYL
0FWhnv9mCjdch/TJJNqW/GIKCNJQwGWf2WgElm8EdN0AHeHuboEp5bIZ6Hz824tnWAflG6P6DC2T
vAX8M1MU0tW0iR1X8HoccbKlTllQQxnYMM9oXE3eRAcdLlXCHUwhoZxC5vad2lH1pKFnv20V/XNQ
OK3n8Oa/zSAo6Czl+bWz4b4pw4Ql1CK6vbqyMXJZ0ZF3UqzX4z7blviW/VVfW10CtrEYylHfoTNM
PQeUWFWV8YMebWf5tvr0s1DPJUT9iBu3fn+RCWTdJI9JtwAKydhGn1FyIw33PPlLMwwWtPpZ4E9m
cho4vS4SQi1TSRvKc0W+Yltxl5KVqO3Jv2+ccDTWKbbjT13ZhNmNpV1f+FGkfeprGZ5raWGb0Sm8
l5iMAb5AJJNqgmnos30bQx+hkFKveSCe9rPfIRqecTvaH6YUFbQm8hqby0P0KRvoheRaGSt2v7bO
yP6TxLdRVN1XdW5xAcl7BuoKftTetgkqjrFulJj5JFGYMSWvuwHVj0gVrzgqu2e0gdHy8CYARgDU
L3MkFKS6fPTdskQh7KNUc3w5RZguUr3H1ZH1CRpNaVhYP8/oBlMapRj6ohzbFr8yKqZaYM5xMVvR
eaH7AFKu6TGHbZzE42/HP8M9iiIxsN+qJCb6AvIzrxQ6uBuWaaWyoleJzo9p78pbfeYv5asZ7wGX
lGu7xwwMeakgoBhau+ZzzAHYY5Dwn1g07c3mZET4YCDck4L2nc2vT0yfniSIqROLeYYqiZbfjdvU
6QXece9FcZln+oVD76jremJvguAsi/qYrbHjCUiu3qsi7PncEIwzusvMAdRCVwZaR/gGnjABZ1N6
lulxE48NXB9Nv13q1QJQ1H8U0AdriTwTbfqMIqfa/XR3blwvbzF4T153T0AECWC3LdUhAXPo7YYz
qoD5kpE4owqtx4CiFAJYlwRfwsJ9Rwv0Ke8g74ws+M7dMhmZpgcpN852AmOswNlO4l22nPkn7RAz
mvAJMPptiLy+pgzj0CBBhNGilQwQApvlf8phpqle8uVHyAW+BYnO18L2QFOsjH88YRsMelYP9Kwe
kUWxYrTht0QZemMFPGljfYumaDOGGAl86tjrBbDkE1py5wsRKnXjSPF4QVlQ2wqWMGPFmlDHxSyo
Ic5GCTyFrLD+rFKYSz8/v5JBHTka5b+/xaaAMa83xtFtcwb1V9Klw6mSJwVK9H9JsJy2+R6o8EAU
PjofUPieKqzTdE8Sgz7fKw1QbWECDbo0GlxzfH5lJwrjip/OJRzmcHZha9ZqaBvgjI7q5QLdWcs/
v+Med43uddxHOy0VbOqNTbd03XzDKYsDX7L6kZdAb6HpfcfRNz3vQykwyekZoO01JxlEBZ/N00fT
wqh793RB2QN4nqupBwf+KpLgZlh+664e9unJVM+iujSIA4q69DZ1bG2gH7LPDHqmXR6HytKc08X1
rfquoqieZFQSZeoe5Wo27x5Jw//A/L12a5e4OE50aKJDmus+LBkncQigbN9NQlDMbBy4tMwnpQ+X
CkPfD2ebM6L8ALj/VygL+EfShW631j10Kl1x5sWfFl6nipfY7WMLCsmH0AfHaj9w9lqTxqoaJDYe
bE5Swim1MFXi/UPs0mGkSvdYgeSAgdi/GR6lkHGaS4wuzycLgUxhu157y61YDcW68KvTayAHNX7O
TeC9rDUxe/ISxZ1uLrqK1H5YpbbizQf3CWyfR6a86PrKpe2a5hbWuIkoEcYDgemU89r2gbsjBt/h
Qm8nYeoUbVMZZEUwMFBPeno3jyqyWclG1E8wj/rLsfuMDxtLY+6TUqKxOWjbASyVpJKwdMCYMT5N
aH/CQc0O6zSP7l+KpcA9mGDEI5rwelJ/D7BDZNLgySlAPJFF4cUgrkUv+mA4zuhmnO3w0rG4JbXX
TEAQSu1Bu8uqxL8GfwUllqn6VBZGR6muwxRh+1mxiq82BUjUuQre8Sddpvhe4a3nWZ2Rccwy9gz5
DMZsjvRYQ3Cu8jXt6A04A7Pke7uUlMf7zjXVQz+sKkKiK5dXow1goczGnPhQIv114Hl4b1Pcy8J5
hDeGP70NG2azEpMWV9R2dGs/Ry99I/Q/rMYLGBg/u+7rrjubsFwCZWXJnPCPUK9HDRrrQmi2loa0
2TfWU7gzukAs2RD5xw8worQTodwGBstnu9E+2rSITfhQcja65GXsR2XUMb2Qea6bKTxmDm4mg+3W
faSjMHtzGtJkCaSLzCZIHGRnLYIk7ipUnh9aFJn9aoImEVuCEmaHkw/D2+8bZmPAHHrb9Fy4iDAQ
INSwaxCw/TSo5a6qz05kTBYn2McPVX58bBhlscsMALdqVZG1DvwXYEA4JVuGuoq3Gupo/teOVmJ0
MAjbrOeUL+HVyZd1Hy17HLRv7YZj9JTfnVdtyRZ5ztfx3zFJm/PDLD//NmMdUfMinnTDYc7BwhZb
u2aG9WgvS8vv1QDGz+Wcw3Cypw3yO7P6WJXp2hbF5iASiXX2yv72rkjoXrJym+UOPpGRT6Yffdmr
Q+YwtJJJKT+Acma7yDpbsthZjoDEuVfy9T3b2036TMUzGE30SxBV9s28fF2rwG0ewsV92CLvnpNE
eDbvVgUnQdtA43WmrEej34bCiw202JKPOXxjEK/wOr/KHkrsCHCqupTEPMhY6JQyH3vJXl1COp41
bnaqm7Q/sawr0kFHn9pscxBEXbiZnkvyfO6eez61TSYL/0/LxSi7O4p69jI9vFOQS90+KXRAcWmj
l9BMxveGrc605/Z6D5KCtPEFmNCU9THeohwCHNgX6SL20jjzR6tGCgydk8b4eESpZRIGP4qRtb33
JbOzfG1ZmCXudqaOavNKocjRrMUydgAff75V6G3cGuDRw9oh6Tb6QEjCVlZ5HDwfk8iVNBmxlkcl
S99+E71V+7HexNtwnXwhmQ9JjSAIkLJmuNNBOLDnTkpke2ArpoZBvMaV542leFPbaBvVoC/32qNK
9lgKmO2yQWAAXnRuN9YOWqnPswjg8ifrWejr6CBuxJi14E6DaCLn+So4FJ1OGr1fPnDDw5gziOg3
EG5zipNVk+hJszKsRMth2VhrG0zNcKzZcZ7Ho+33o41gG0J10gOlojFEu0YIYRs2i9W7aga0QXrG
VybrthWZe5RZvMXreNq7qHfejK2JZFYP9rrvau/bR79G262MHJ5qK/J0XvcxwdbEc20WXZiISZVJ
84Z5QeFjV6u53pnMJtcfvj0tcHUmerib3ZXsC1dk8Mf9jyoDW1yYORO/rVpQCrk6Np0/w/37ahRp
dtBGLnpKlQ6+9gJCw6DVV08AMcZAnAiYxXrhzxTXva9CjvhS6VeNYiG3ECnFHKP8adxyK9ksJM79
1aCSG0inciiJFHgYaYKKCeQnoR/IahKVgC3TPGWCyVl9xX0/d0A8ESNrSAhmoOOnhaCIp5MdvPbN
88SuyrWSaMdYO2l10P3Vn0FfK4vRmfWYKryyAqyySiswbYLd/2sQSwy5VtHgzqcZwC/HrYVaHque
WEli1pgl8SFqSMd6l9RMmy/BIfrZ4dXw6CKoORCXUBhMBOYVoIGYVUzqOUXgjB/eZIVLPXVO0h8a
PRqFd66765gl/jsHCKbTW7WZlmJ1x1RrHV1m19Zyws3aG3UFfw64ndgh/WH4xTM0A0Jpxrxw4R3R
nsordCJF7M0TAL0eaJPxY940HIj5jk9SQWKN0KqmtB4KfZ7+uLLU+lq3PAVPONPjfmld3vS0yev4
MV/MHdVr+l1HB6DrZSFQ61KxIyDUcek926Oq6cnWbGrLXMvYMhUst34iTO4N9+Xu2bV2Sb7Ksr9X
1qAfKzTa4FAGeVVaa/9cKtk00YH5jpnl33RhKDzr/oNYWXh9HosC4v7b3nPa8hPyKaOXkxSt1sAX
Re4hdmzFwHcJwmhn1y+NCkUVtBVGT8YXCBly0lL/CZ/YEUgvQhPs49iq/QILDLW4lYA/hvPE+DaP
NOtOWVspq8RZCpmb/Opn2toYFSV2s3ZmUUF/ODXWcZ2Y8j+cvXYe3hbHOZ9GCTHNyI1meNDUvMwa
dJXi64qW5iMMEKNmCZv+Qk0JdcWSnUdw3xr5TFCHHzbJo0l7aahcGhI792N5iCiXG0ybIXm8WAWb
MC9woKioEyqO8L2fvyFNOIMdQpTc0Yw1zlLENuw9kkNSXhUU0/mrKIBer17y1+Wg2zeHDeODvqJg
Cbo5o5P1TXqizvlfAHosT6ZinOtKR6BwtIQS/NLjSv/aVjD/NPAKYmSjOQUoew5fnKZrbrn00eEx
b+cAwvqTg6lTaL+tRaN4zTO085VII1KRmCAlqyoU680MoODxLkgS6QVfcX/Zb1WOAGy97CqFBwPp
k11aXrYAiCRdwcpysdTA6epvX9BGm6sjeYMpUF9pQ5lJ5dyKd5/n+fQ5S3eXmnb4eRgi2hUh5iyi
H9OnKNBE4kdh9uSXCr9x4v3Z2+o5JnrPw4xOBVrvbEJkAOGPO8QX0eFz2FSYL9E35aoY1vTmFZHE
MHDhN+XZp3ufASG3CWUjKFlONdJM1leM2fZXPkoyK+wP4GN2ygu8z+pzXC/sFNKkob4z12Zn9kUc
nIp+tuZn321RtNqIh4LZ6+N1XqmDba7498vXii34ZS9ynVpkx3kPJiKhUFu8OenlYMNa/QwT3147
G7cmQd3AXoS+inGoF7FK20Y7lijb7LkUBoLHG/YN+Agm+K8Ejdg0Jk4qkWlVsjObjmqcUxSO9EgN
8BXvSrkIFuUpDjknuAJuPfdfrvwhQT9WLbFLdSzBq44n4JxvE+JaX9YYBrw2MacwvQYyGxzqOXWy
VMdYG/ziQ72UObGlctcXLv8TCPqFyf/o9IJFIe6pnWpXi/vhZsEKje5ddDXblIamLPxuEdgxtB5g
3zhYwqChsSWK6QgKUTSf+BmOEFaddguJ0DKFMAipPaXzquq3JEAWymsUmLe7wTKwfFUw3/C69BFW
xgjDtQPSz+873L7YRRAKsU8l3xCGrWM0o2o2K/DZx4PRYTLp1AUxytiLE9Q4EriGflwSUn0JIw6s
G0f2eNdiBQ9ZCU/eYO6zPUQu7fbjOy3U2TlXxzp6s1zoI4R4AoJfeCQ2zGK88+2wy+90Rg4NO3Sg
ZDEFAMPV/mwiSHUQIGh/XcjpqKRKBXAdJS8c5SgUf8Nfy051cxCz/kuKr8lkLDFBy0ZnRtWlhucC
aXwUs9cdlm38yKTiJJ+Z8KMDuwCSsl0j5RAx61dmgc2VSGGA7OCZlcwE3GIGNcQ7sWCYAqEov+SF
S6Ybkzyk1Tbf8dHaXBr5nGd/ZJyH7/aj3xD8/PNDQtxFMhHovKtendGNR1hGLA2RBdh7VXxDh+ln
Q0OoHMMsj74iwIKV4p9p6qGkALO2V04lhNEX9VNRHOE+nwtTmGl6523NTcF1DByRlkF+dRNcbdNX
XccvlYZttTo+bbNrHRSgvHszK3VJEfQkQCalGwxsqFP0gLpdtLI7L8inKF3lN7cZo4uiVg7egHZY
4CSl7iAHQlg8pOMjGT/ZYr3ysPTKlzXtKL1W7+rs+YSqCmLV/b7LySr6PcO8x9x/Bpi5hKMD9Eib
F23Ig3ePDVjaSPMYkxiKBsSQcvpFepgx6hjTrZqNOS1SUKLX2z5L8wtneLOu9Qyh1xR0Ff2qJjww
I2U8aFotatSfRM7+3UoFvC3eHQkQSLERjmMSdRVXEe4Bpyrx9RftoueYsNj2hB6A/ktAHwJl25+4
WJkR6V4Ziu5FnXzzCd50W/2Zt9Y/8bvr3zt7u4b/fdJy6sPH80mCR8nSwwieKN4BXIm43anoFbUh
wYp79Ma5320wTFEUz1fceHNIL+2UH5x74ehLhOg2mMf8/+60xG2QkRe32hpr75VHoxmg4KmYhrjz
08ZjsfgC2XOEnyLWAYW9M1bXje7TEiLN+/n050xSsKyz52bM2+RpYC4vUn7qsC70oStEoOSoZQ4i
g9u7tBQQf3Rz77CqszWC+iB1Ng4m/Z66ecEt6RO+pUHRLOpLN/I/KQGwrUuwSkWCMOf0LpLiY3CB
8YBIYyQgTM674tO6RKZZhPUgBN9KBy3spA8HFPI+wtSyQgZPM2YU4F+dOOtItJ2k1Pd8zBYLHlIH
caY94psz2bJuhkpzLGt6ENogc0AyhuAlAhR+V8AY83JT1E8zvsQYlUHSTdlFQLgz9v+/2XRxt/zy
mebaFKEUY01uraHMZeJXncUQ9NW6RWokSsW2oq2KeQroe9WuuLpSmtnw+n5AGM3Lf+iJsdiy1VSf
Gz2f9PDIAyNnUJ3WavnJyzGzlJSeWPi8mL8O6I0k8i7+E6Ubbt501hUpXJv1NyMu+ajORUXq7hwv
dOXcha/NkGQ0FJRJalmdbfVWX1AZiosqvX1+TfnVItxA6Og1638jfDMJuTYF5N7yQs+HhP57S47M
dq3UHcucsngnBog8ZM4ckcrMxD4CuMc99Qd4fl8h6rxYzJO4XCynuf31JL7hP7ijtuet28WAURtR
xII4X7oGR3H2iiEvLNZPjr/MZ4ZtwmQiULvdUBdkPTxGOsXh6VcBMBBUEGp+IGvirf4VAHFkZ0Ph
ygpgvmHOfVY+OMhCnB369T8pS741ZXHXP26sHq1nwyNqyvTyocQkfN40enkhHCzrBiBfVOvGioFW
1MIJStpXQ6P6oxyImD28h+jPUJfLmkoUOs9pTNlQSnysTbkavEDhP7LuELPr5/qVQO1+FK7Fv3kB
HbTC5i416/nhmViRukcwmRxt50sj3mjT2j46yjRCgx45C8Ukgp6UwjK5gaqlUd1oOBXH+ZqiiUrC
hjdoG9nyxBmZ9UG1evXVJIvpCZKo/JdwRIAElxqagm4Z6p/BkkhK9DeyRZUqmbgEbaRsXjwrczCL
G9TR7hqp5xXxwycjTnycH11DXQnVK8w+tcU8jWeh713vjke77kfoy7brN0eBzppDPuJWfLiZC/RG
cJMkqMfXsHrLQpYS3/Dp3ySbZqAkeusKHuil2Wk+Aih4uvG0JTuSELTgebtLnbs1fSe9OSlX2YYn
XEXbu9ibOlnvQbq77PVX/veXjFJaPW437Tq9DkSCUwDKLsThA5XormKV61A1XBb4T+lJjG6XzM7o
zGF9Q2h1V2gbRX7N+uHjYODnqehWiZPYEGYaYy93P6WNKEi7c1jWmOgRF9t3RqYl9rr1HbjM0mGY
1KrcKjLhDha6+LMRkvx6XZFlfunggRbiOqa+4Jaw+T49DjjE8assSx9JzRVp/hyTMelBCylkCEkW
TSFp8F7+KSlT5RkMW7jF4HJuGsbhluf0bFRT6w6ZjNGYJH0o2IpIcdxkGHExCMC+icHV90TpyEta
O+xN8g+/LdDfGBv+annMnNvZ3+MGM23Hdmuo88TtTpIUZMXazwf8ihx2GJi8hwdgmxg8+NHCPmkE
zUljSx8kZMmR/a0/a08L4LD18/SX+3pMfhiMEmyx8VeFJVzivqPbo2aiwDqlvg/4kIzmUzGi0i8K
EX4H2yVpW8sGeouLOEk4m+K+jTCBJSbiVp64BZJDQtpSGrE/iM9vfpYtiF8IhsbgQNis8Sk8n8Fg
nqm7NuqPJX0TbIS3CKBcm9+ApNeslvx1i6OsetOmzRxbtWi37xxtNJ8CqoFH2cIW5oY+CEFRvxWg
5jFLiFJUD8h1JKmqegB+3/1t+gXbpqImU38rsOwRb9394kWxlJ/16j5OXiBcQz3hJZPiOS4ck3st
3+5tpGdQLHTpugLNZMQg9c7QTjK/bwfTvgrQyKNp8f8jjLfI6uDRHR875XK4HvMCjoMwN7Tm8svL
5eKYU6jN8QUD35LpzqU26X50bjc8FatY7mgVMyBbUskXrXaHxjO7WNWncLHnXbrAIfPF179VDN8l
vPR0RmqKasXWU33xAv/Wi1HZdy1nJXztMzdYkc1DbvC+cPgVH15zqKuhpwJSybRJhoFZJxlt19Uw
dFZuql8b1/xG2IT2TV6hzotLzPElcN9vSfL7g3ACCv8NvuR0FxKvaH9nVYRpPggvaaQn8zVwV+OB
8wqsM+1B6XReijLG545HZVr9sUYiEKhIuotjCbIXRl80sYD3nwRCQPNhNSY4fzbH7TzS7ie580Qo
cczm0KCTf6F5N1qQ580IvD7SiQKsbbbWaY9bb+pysQ8lt7qdy6VNuFIIeEWi+2Ph4ZCFKIgixjHu
YJbQmURa5zhupVX9gjylBFh71602zhh6BunSjXuNUvT4D0FmTsP8MeSpMypMEWH3L51a5tFkR+v9
1GdLHb/fHfHwayQGHpZSq/gmL+TCuZUS8871zzC+eWTShLOb2gb5TNkj2AEu+WskoERdUy+vF4sq
EselKxZQZAKNo5ePhT8AhCocHASL5Y139clGAq4RM5Aql9a0q3Wdw2+nN8WN1hn/a9k+AXgM76jP
B6FmiXUMGF7ZNW1cbEdNFqtqeNjO1m9iDShXW0g9Fz7RCFHVZ2VwI5JMK4/pbjEw4WDocCh2unYI
9ffPjPYmjGSFWk5dyGMhXyBBocDEncXoutRb4inVTzKK1GmnFnqRErsl4DVa8fMeFfZmeFXXKhKE
Gfa0PIU2T626cYmSzCSOFc9hho3GueHslzorSe7L4N1hpKsKZ/gLCLXQFCbLVV7H3uUmN9lwad7R
x+RpswEjR6VQNK9Zd/BhBUWeKw1Aa00/QHbX3jPNGIJag+vj4uIVEcS5dZoWCAOAc++/rgu0cGEn
nJoqRZc5dATQwFFXaFJZsFKAD8aLQYwnu8SInhEJxwZC8lm7CWD7EGSP7kb5+EDwLSbEQdC7ZniU
FGmGJsCpXKp1oDch2G5BflX1Jo9HW/WMx1fm2k1H8qtexoksSUkFskppXwwX1TjoTxzmj2GXXoGj
5O/S8ygDnMKjNaZTIFaFyCZeA3F6veve/R33Z9qsjwHRNgqFAlNyF0tgCzT3jgWik/qMUVdgX+4G
Vo8SKcpRsh57n1I6oqxseXdc/S5NRnW/mDfRZrYHhlkw03N2YkbGw2gOTGN1glKuYifY9KsFwvLa
zeWUHYenP6KFvp4bJ/jpnXMIyRCI0TRmuJIihXiDRkExLYZBMaPtlrg3SochxR1tQvx/0N6MYaDl
Zjbmg42duATIDvIL7gKcfJYmaPe1VrmcRtW6mhS75N7uOpG78wz+7YsbmxzwK5nPk7ioweD8yz1z
labvmMDvOaPwMwbrYZZYdtsQFfVMMppUR48g9QmIJYj13e0+0Gtj7nAOvj1zxRlXyV4yqtqM0QrJ
C7OyVaTO7vi8trBT6/nixDZIUREQZxPTmBf27G8EaNkyKHeMrpRiCiGOlRSi5qbi0glYVHtG82Vm
S7WHUYeCqv18DQENDHD6kwEmFFn2eEAlHiG1TSVi7Q8HZBIeRdf/GWjVm+op83TcISWxt/jXf6DJ
i0k/TED6FAv9hjXOnvCTcH1TOrcm/FFDhFPJVJpJ1IMt3K0XjV5lFboOimTDK+tDJeYtMcqJEsIt
jXmB5QMh0ZQh+/VZWf5o+7dT+vRM6m1Dvdbeyb34PRfCAV6T8O2cAjOJcYIE5oGCf2DABARSab8U
Cqv2nEjbZUK0h/aBAHbEhQTw/xJhZ9fXyTiyKJ64IUjv9R4++0+3RWro390LsuxbPgGpbOdDwBTj
/sX+kfqqt4j5j/mS1LSo1JZqhHOpER94rLHrP1eXUoW1dWOPqOzdboKQ4Q6AFGp29D8uR3uT4JWv
XOXYOgz8sP3Y2efVy8MZ9NOMhgRFu45+OsXTJUmIpoLM/4c+w/K+khPkjaDsuoCXDcJoxEiyHZCG
XBj3hSZ9xoGJnAcuYd0ZiApK5XtLoQN2Lrc7cAvaalZ3gfJGl3QkAAOZh6vG2FRTZJ7v8RU54hlS
nhj3q7xuHbfmbG/PQaDB8jBps/h3cY9VbnVL1YSsRY3rFViNfUi93BHc1TfcIDksyMzWLF1D+n/r
swMM/QPliLoWeXSqAg4MtPMDyHw2jvFYVx58m1WhnlADezFc7gYGze/3MbREf9aYrUu+ahPRPmG3
O40G6YIM7wocujbNZqubh0j46LPupQaxp36Pjdgs+HLJgkFNAwPQE+3S72M2hAY3kf5ShyjpGqsT
WPxcKcZqntvn0PGXgnxi91nt23ukMoW3FWxfiAOQlW7RgzWQviVsW51yuODoC4gwluef0OQd814h
eOvMufic7q43ehwC3yZhEpJbAhFdJowp9sHSXFaSdVRzYGnIX9uEZAEhN3AJqeNkFsbSSWivmE6q
5XFo5nQFj7d3YHv76dFqjC/4nVk9YvJUUPGEJ3ShlxVLD+V611foEz6ZkNznDIVxWe+fmbv/XCPp
9PzfJh5FJEISAUA35IW2+qyHMWtxpIcwAgfl5HL45nAJMXmDbuiciFP1NEQ+T4LxA49XUKmqbsF+
yUVjicbXFuzBmYJ+Bg8KqBoHX+l4sjT4xhCaU6t53SerWaabguGToNtvtLl1Zlwn8zKtU/LoYoF9
4udZslTqbW1f8JNJAfXCxN3wLebh1XralSS2JOBj4DlfDrkNmlJexF8mHANZhpv0NOCtSbR7tfD7
f//RmJd/LN9w+FgyCNgbFSZweMCh31lBmTGiltu+zKHRDfjMQypwX27X0+T1D8ZXcCT+qDO8SwR2
y1CGb5oBER+zkaUxwqBKYf1xrGEbFsno9ZMNnRKlKks+ptETstN/dSrzL/Zijp7b6kCwHbiL1cpq
5tjtilAZub7456pF6uwzCD0DngLDJurgbtyUnh5uZDmSqHSR02INA3luR9yvpHIS/53hwDimgRzr
nw3upFqeP3IWwPGwXnrR2l6U9udVJJ3wfoNAo0Pop6/NAeWckUA79mbDRYraZLJIH98yY+pDtvLJ
uitcsrQEJbjDDVo4SVhwbsXwOc4w9iu+Kf0WVX3KOTxALIZZicbTEP5XSeScMRJlhsqWrh4W636a
RGrHAeN43QBZMlhKNkoqTJUoxMmAUPfqa+oIe6/lBDWZrupkO8jZnfNkjtp4mPY2A7H9C70FQ8so
qD9zRc5Ul1IXLsPnvVNcAZDJNdZrISFassqNH9ZTMNjvMf8kV5uScOm3NjByETnv5Rn30hmeTOXN
+hY+nrA5Fc5xtV9vbtcyPhd0WMB7y0Spkb30Fyi6CCdQci9Gre54DHKNQuO2k9vmtXfOGrDW1v5s
zccf1Yy4wJOdIV5e3mcxHkPGkAVPjkmFgY8Gbsu2bjKo8jT0pbih6cOVnN3Pmd6kB/h4GBeHZhpT
ZOFwAUvintgcboqQ7NKNerd14pLH5Pwd5hCaSv7QVvYP9sSXDXZZs4MKbAyqVrKrDrrbwFBpY+g5
trI9DgLS20SFWy5PYlRmMrUSXOblYWAIQazICdRw10g6o9hP80iXgM0nQex/OPSECEog05Xc87DB
1uytH4ydiEpXDipiPS1xOokfeLLuLNSF2CqqL78e/sKEwPrJLBmAiJIQadjBllA/tgHdCyfRMc8K
dU5294glVq4yDRlYTxBS1jY6iZzJkuCBLU/g/W+oc0yfj1X8b2H3FoJNa8qpBjy+71r47ELXQ7lx
WJxCqHl9sFoZjY4NjY2eNu1w2CrD2VsOabJzYPf0Nuv0xxJq5H5T0qs/sBGt3bqP6YShG/Hp9DTR
PtifhvbJO7300Ua+whWtrvttcIPz13OZysRS4dU5BKx50AUdLQBAjw+7j3kT0C2FY4mcFplW6N/K
tcQaWqyhzkT7GsRqS3IVaxf+ZIVDPAIi+mc6YbzduryBr979gNyJKgRQW6C5gsldlTc/okxH+Io4
vf2l7hzLu7M3D9L7CjqDRJa34c0GHZ3z0imnrlUSJmewxj2NKzUece5L0HzNW9X86a/DVdodGBDS
Gj1yUbQcaC+7W7wGWRl/gkFlC3fbYUzv7TM2d7dg3XxHRIVPd9IJoya/uAHPVxhhrNb7gObysAIH
7GXcbdH2H/Z3uUZnZpYAAbR28W0av4D/f2jlGC3Fh/urZFyITDOfEvdkHcsWmtATuiIEKEdxEEWF
H7W3XfZ+hY28T5Y4V+TSzwnU1jpUdSeUUL0LKL79Ra8Uj/9SOpJyWfpF6pOMoQSjNyhOl+bYfswt
0yKvw3aybl53JXs/L2n14ECZ86CAFgMCyzhXGuosKfsvD/Jw2O1/ovgre247uAdfDb4VsUPVfgTN
UV96bLoV4ZOi9mt8F1A8E3GmCtEEsINwbFtnZeZBcUzbjRiVhEIvUAWbEITd9VSuAd6oRcvTobEM
NWgqZlGvhT+S+3f38WY0ZweOKx0p4n8gj+XtMUNZwClT6rydcXjcfIFSGK4m7836gTTA0e+ey7ZA
WuGpleHMHzLMyCSBQAbUEk/OE6NMvrVBqB+yGDuCRzAaAKQVtcA2ElOgEnjhyBT3nK3dJGENc+AM
ZQ4qDgbgRgaCjwTK28Aee1CGh1DL8Xjx3zbkReCBLSFeugZC3ypN5hyD6uPMl/KZyni9Ed5wdnCY
RIigc8Ks6f4Fh2/5BIkqqvPOqNudHQYXUSUp1/2wyID+dSVkeYun3Z1PjG9NeJ+iA8M+Y+hX8ISm
tgdr+Iuy1FYsw2tsw0lOsnz6ZSaIh+92eD55qEtGvE02FtmIzbFjtdZwMHmeDCd6uMZnQn2ruTB6
nPTwqm2jJmaeVSMVgkIZftvZYYJZ307t2M5vozOgsI0Zc/bebCX3G0n41WW4IunsoOxuC7WwHYUf
LXIVmnjC4TSbx2yBMx9HczKPwWEdXsoe8fXj7+2g+3mgeQe3cR1XPzRb5YntmOH7s9eJZK9b2FlB
r6I5TwsrwwxQYXimFlqYZewNiiokU1ak+jyLIXa5HqgPirNq8va4dH168dC8uu59tfzJdM1NUUxX
rTCap3J8ouGzqLC2WXUcun1VIFStHHfF6b1/NfdP3eMb58xF2dU23nHEl/Rpq9HoOtNSruB4mxUG
GfgQdwfWqp5IgZAhk+Mn8YhfVtt+71ulMOy+lMQ65g3ons1a9/FRkQCQtI/j67b8BlHQTdBqHr2u
fc3VWv0gQ1/b+szd4n3UhsFrE23z6+SsqRGWqKW8ZLXVMfSA7/bxNscYIgOP9sDpY/UcyndpWrX+
IzT/idkSt2ygf+X8eWeid3FLUxKWhdD2WsKUl1vd5QhzRUZgOu9rU9qi6vXmEBZJxcQj7eNfRq3N
6wnbrBx5kNlTMilvU2H6Uiq7roer/yX/v2YcmPYY/btHfq/Q4EejMDcFljShs/lbsmr1uGp5nYZP
DqxhD5p49Kkj5TMJ/kHye6u/gHCxBtnkDIPb4SOiW8KLh7vmMvTpnSHNWiEcdVCFe+76OBPNEVTt
oVf65bF99OoHGfdsJEc/OuFuihAu644LtY+P4Lg6ey+DCq/K4QdS9rjdHsaz9eGtOxVlliiO/ida
IKgC1KoUIeQJCP6hXlGr73pAZQGGHKqPlx42qA/OzkefPjzVdoE2IPdHQ4ddJ2WX/e+ZByf98S64
RGm+BWicMUBMxkzr3gR+IEfrHEEqbEAzqX1ymDjl6p7rUd6L6QJ/mC+Y/oq1iu+wgVb9oFZRR+AP
YvfjDQWGxiq+EmBdulYlnE1vYWZR4jJk/cLO+gWQD4yta+aQqL8CiJr+vU3/NrrBmEiIzb/X2fYf
BVZyDegZwEDdV5YrPYPAf03A+cTsKwBcSZB2MoRYh+ZNwd4hfYVfX900m1CxmgAa5G+7Y68dYPlO
Q0WJr/kEGkIeu2JkIvEJdPnK/GxSQGlehaNgwzO3y8V7iXRt7DB80bIBpHSXSEHtzBV1Q9xFnEer
1Ji+g27K/j78oY4+molaoHC/Tk85Hg3FLUSmRthlkuZkiKajfOelT+dmVKHRTxcPT1NdP9HImtxz
woCOdwx5hBaV65vTY02shrUB731bhDA06x3/s/xawi9sakx66PtC9IHWeHxyxYV+1rjm7NmgT0Dp
IiCvSMxw2iPX7CwoTjQmKyjYIk9LWeHXufjoxTEdbfeSk/IACptp7SbVD7lxH58Q0QSfLTKoViXQ
hA69+MSc9ZfbTN7bdg3bi1C62N+vMJrvjppaQvjXu2kmSuErnE7/du4/kpLPXc6F99To+7dUrX72
kwHfkU7tKbDDRNaqJImAJpNEbpj+2DTjFNwTOJXmwczqOrAimYF6MbDCx6PPW5GMKjIu4Il3rw3a
8At03FcXA26sE/gaIMhEm6VcDBIBdO8u8qaYbbzNhyJBB3Ld9jtWeSrNjtKC0+rGmBgoPD1RxNBT
hlzc1rIDk1Du1iNet9OT8RntnCqrX+DoZrFFGn5SXKFOZNw2zECAHSVqTdq0gumR59oVtCMd0V2t
gDP1hy2PR6Ov5wIMkD7WI28S92glvrpNb45gll5AbA80GXrTbTT0V5iMCnGMAO7dSEPuHaGOQSR7
wBt7ybUCxznF+S8XNCv7Zxuqz+HlUFlKp4nrgiiTuBy3P6u4VOFHkRhJIGSJYFu4TQlBY6svqgQd
JyBHeNNLfnxl2wBh5UMdbXDEjh/lgR2c4s2j/bxR4KD3HY6rYDluG2IfmRIhkAFxPdTV8Jx09OmC
tKKqUo1y8UVC4ygLeD/AroaWfVEZ9Ldt84xXZz0EsEDrXlmbNE8lj/G/QcdSukehwMKSCp56frkf
cx8aLpqbggqXd8cIBjZFxJt8GSRGJtpwW+5WAP1GwqOiw9oi12Zn8pV5wcUfCwP6nA7BwgNmcx6o
iyj5XVgCzsWo5KntkY0VvjI0MWJWTzqr0bDkwfscaW0q8Au4vJxCSX+MdLhz4G1MrrC4iCzC5EyM
psGjWRnDiIirXlnpbz2b3iDGYQJk77dAXPEMiIgRNUpUXB8YvRXQMjhYBOpIieiU7Ralu8WFEsex
/DvwGXMaldzgpAOD7raHsZpgAQCKqMcqi11lK+ABsEc/XGbMhDHKWY6yOoYn3MYxCkaNAPo3TF32
ILZq+vzQhPIOoeec072gXZjaF2JErY85p/xuKcR86FnczX0B64qgNFQCCpjkhWYtWwe3fUQT9xZu
tGRm+xUPwotBmUxThnjC8/h+LFHMmFYa1mAH+2SP/RbjsXPlSXSjOX0Tdtj+u+JI37gb8RxHxM3X
DzEnPOnH+dlmihDgwZNS6wgRmq53vw59OZtcUanL2UcbNmzA6uFm4lfl2qTyDBXJquCiwjSedbcB
4byc1/YC2OSYfp4epmnX46/rgycf7kSQ9s4NNkF3ombwWDEMpfRWhkJrRgHe6cEncovhEcHB2EDF
czmswWxlO5OtsgZzWBeGEmLi4nic8baJU8lB4N95iWuBLko8V64bnFv53eKigfQc6slwOKcwSDOk
gOSpIBqvuJyZpTGWVDuunywmmUj1hQV0cNmc9PbexFowSBVevu4b7mq3jpeaivTN/+y8EccZ8I4N
qA68Aq/DAiWvjkncF5M+0GtlvAtuCo8OYlpmr+19wsDxssLLxDlkU0KAGkbsVrfi4yOW/q2Al1AY
kinTmZ1HN94mioucSV0nLfaXgKVKJgOw7ycWWHR56nSfOHSwkl7B5dMgnx9RgYdw8F9qjop+TBS3
B/3b/2nTNsSqdbSCpUtjohqfjcFOteJdDEscEgsbXgscRxsHCzsyIdfUfLfX5PEA6Ac7BGewtchl
nrRikf+H1j83PBatF27zPd6qDYo/bIB/OIm4nT74aGikRw2/9Q6F/CJDf7B7yJ6QVd+U+HTK4yWb
Uw4XZk0pG+wKWVkKdXS8Lb4FcHKgKi4MbiKbagAd3T40YUoCoYnrufnmTXatTdJqYZ6fLbD4giRO
LgpdDA99Wqc1H+LFlCdmITF4jCChoKkBq4xWKdORunLwZ0L/CC5mho0K7feujgpW5nsq5XtLqeln
eHugmqBaPeqVUHSr55xyhZl1W0e7rKGGDwR7wAfyW7ckdJvtLtdy15C+/rjRoM1RFSwaVsQALgib
a3zTCpI5sAEOToVQ9AmC+ss8159GxgLMQK86ph6d7DfzC6ZF9VBukB6C4nV9Y4YLAQrXkomY7jCL
dLA2LG972v1KeSopW9eGZPpStAz/rfjqlojNlwSTl3K+Jcq9mENh41yl+HWYtET1IIgQmPZmEizs
1eB61goeF3wgXQlMSIDOylOkwdoWuozwah7/7yDIo0Rvm9Nv0zsMPJnHk2hoXOnXdNpDJNHfqrxs
Fg6JADmPcT3XKwS8BTzrU6m8tVzECz1+6evrQEPLN4ohzzUVWKimgI79nKbwCs0UPUhE9uDOqYoC
R/ztHpne1n7KtEyqOJvj7BHW5dkB6x8+M5+cJlHTXt26Hben4C5zuYR0Wehd27u7V6ubTQMsXxmG
+f04SVNsqeJLTHXTZBWT4f9jeLo1Xupe8H+VqhfUiK0TbViSy5JU6IuiHb78gTVM0WFDz22m2/Iq
matyWrbxncld7QKV8wWK6hK4tHMLjnKJvh//VcySXzQzBlKwXDefq+Ij872WWE9Gusbuhw6kXBqU
L5ytq0qIFrgfZ5xLDRk2+NkGqHbhG7xIt/NDc5KsLHimr0LcQBSQbKNCHjr/Zgziw+u7gL0jA1a5
XStnksanjPfcJDSAswmjuOsl6OvELXNE2iz6xahTQdFOiI5UJjVQaRUfEtimFkTacO+vfzxBN1iq
dLWhBB2rmi+a283gIQgIQVRSoGdFcbE0seQHlviB+jW5I83hcQvRwH6b6FQHfFnD57ahluJE7NFI
/yuiybSX+d1KrzXhaV+DEIrZVqlecJKSc23sI+0wnn28C8mzUR0DlGcP7z3F1rHDR0OpJX0KmcOx
d80NVE9bBIFdEz8x6tMHKoMJOZVSqM/gCth+AqKYl6V5ZEwXm7XNg+REmV8i6SgkXp9H4h7PFATB
cDndEQSahucJF34nRh7BT9GI2hmuckKp+yTVO3llbqFPmqnm4GRlawvPJPZ7kIhIimJ8G57mQiGN
ja46hVF/CCwbz4SBLefTQy4sZcPTi2IOh7LRlgBp4BYbVAi/YLbdLYRqy1/y+txJY8alQNgbZtme
XHMKNTlDdl8/ejDqpO0Ai3xQbz95LB6TM2eDRN/N9HxpAEUF1n0xQbqSV2wUUO1sxdRIAK/Pd5+d
Ff8mLzu0kUi9FuS+izXE0cul3nxp2u/joYs5aJzsjPrxVtXbBetdF3F+DCNMMoO8Vloc/4mPU07E
vTyOw1zXeAb6zPPjv2BO3+BVfrhLs0NDlNPCC4FwGCVyWhHook/+Uj959VImzCVg4bdEXWKomfHH
6/8Mxc0bMx6JHdux4gK1VbC90Gg93Svg8T6HdBJA+dY3L2DyB0CePukn+Xby3PTkebyUBRw1KQS5
90Hw8MGwKuy43BdBHX0DDE7FnnfOsEdio7p1MjWHJDzt1SFM9FVaQjn9yNngrhXlkpkQXdMV9h4U
2+YtrOGHytMpyMg82huYFEnjCdgcb5mUrEmth0UgU3gvKgMli96UwvnLX+REbCVzooKD1grntSbh
273dHQvw0bHIpX4rw4j2NP3iHs392plvxB7PbMxYbEJPrIYWtL92aaZlD1AsDyi4uQS5RFUAuPPa
cPINQT39J0Y34CSiOeYEIGDfcspq2j5M430dIiyZVomVd0qW1w1qpCWWOK3shH4a4sJtQ3hc46dK
P5DOopJU09qESb38XcF8Af5hnWH2R7N40pAJEf9PujEEPhx69jM8hk9Cqm5fbYXVM5w82HCCuQ0D
xfZfS66dZCKyrjoDVpjG5acbNE5Xld9u90BqjuOjcFElXbq2cdydD/oYz3YPUjFkfe0Bm04Wu2xQ
Fr7WgSdM3+PbHeLLTQquHiGFX6deAifxkO4yvxBSCGKB4/XdSw9TqUcrwLD3onFmzyvEN+LS0T2S
chks3MD7ZxyVszWRp9v6Y4QtooXsqM3he8N7uwoZ+j3lCePPOBjeDRLDUW7KMibd2nPPZ5p1doGY
+8g/teHn4aYz3KGPE0DBxIw8lA4ZmbWOfXKRwK+Hv1cXui6u1JvBg4EJvuuKNYRXEMcOcY4AubSy
d0+KUXRIIiKUHLw1Sn5Ef3GimfybI9JKzpPcLQsPy+tKo33QQmZt0qIw9Va+JCyYhDiBMnmTwUw6
LOriCCsiE1vr6itIX54RUkdKFnckMGgW05jnaoOvU6lYJB77PyaoM5UWUrLyEj0KvEcN/BDsSeAY
+i0rUyfaxMpTgbfYl02GLz7UHRxZpXpkEMbMtTBjpHw34e+dcEbpBiAAp1GVczEVUD+qu1akxryD
FQ16y01UNH/00MF4fSXrMb07rlRJjgUriWjhjlm5xMWtvGTeigXCHtv0EXiXqmlEoQvshte0Vyq2
I8HlhQehAjDArFCO8HwHL9BH9377jEBfMXKhvWHQ/szDHz9KARYJ7/KOqVmAvqmrsSTTRRdo8vvg
9a4E4bEmV5EtSaAFG+7LgdEbDrZVViIJedQCzVKus8MU5ezD/+AjayCg63PIj3jbvpy8NZWWv6Ze
AAFbfgJq3SHop8R94noCLba0ShXL7yxaAmii0juqrHfopEcBnH3r3gS5/HTsmopGbdsZtY80TOXU
MfBby073CO/eER/unMCzKGqK727vCTuqpGtmMFrePzfilt9v+MlmL3gGMQB2ijh3s145bUsUaMsg
ju0cKJ6e6sb+Kxqrm/WRUu2c6iYedFSyBTN+HAhcbKqCDyViGbyyQTjOWLgTgR+eQVpRZAIyRgSF
zr0oTCUk+B9/D2w3UKsCAS8DCGLRDPw0HHZ7jTMnh451sdKl3gK6wRUkAto129Z7dSEdXiNwI+SI
QbGnUqh2P4agq50ecGonXlenolXSH4loSD9DcWjdTciCZMaap3jP4RdLgy565AOBNbh1bpMc7qne
OjxkxaRjL1/d+wIp+sKX6776L1LpjmYt2O8piVKrtGG1o7Ijrmxd7HWKG15DTthos1pQmz8b9ht2
KTC4mj+RMU7T3YIp9n/GwRrdHgw6Xq6gmV4/XBQF3CN3R112mu6gZRcAbATZDw1n7G/2wt8pj0bC
YC6nXoMO4lHY5mhvBFf6KvafpqfFsPgyuHgTs4HohP//gMG1Vm7xDQQ0jB1LzPnSgkE6fBXnxiDl
7bmmD6MBxUZRm+2sv4KOn1arVyhdE3dSQ7ccDgn/a4LS7BJdGntfK9oC/cKJqBNxgF4eJZqJ3VCj
kSlQXfRFp9cnGsnszIkQUqEGu9bujKVbQ1wNXTVwOALL6rsZk7n72XRmW2H8UoDN914LzUIPJVgE
zw0DOD3xW04aV08UqBScwTfcvJ0RC7jpmd0gWTKTdtsF5CELDfUz8tfnRIjhaGh7IuujtwhElgj0
OBrnJRyMRdo+sxcMS5J5sKjwjO6CZL96PrCln+U7oX235jc0czWdP9ruKJnFnd+lFXz85dtlF4x+
wvjwiexdIEpv01l7C75Naew3wruLmPZBRMRs97TL9K90BrmreqsLSV24KF9umosYReqLRIYU13Dm
U7r8NhhnJpGxa8WfxtxHuVMKrKxqOp9aHS7caWd4CJpYR8lylI9CULQFPP7FF422frQ1rJIumGCL
IT9AjzGTw9BXYJFWl6lpy5lcGsE0zKfWzY+B2kp4y4zjWdVeYX9b6yAD0EEL0i11pKGRD1kjKH6R
8XXrzUwC9+Myk2eCb5tgB1c6NqAYn98V5a2/hH3uCLSQj6/vGWUgsKkqUHBtdYVV4LaK+qKwrBUf
tZNGPkQSkGeK2yGUzqhwqNNAthWsic7V60islEwB69LJWTt7omcugQbKP0FV6c636eq9pKDZT7Vj
zFft1+Ef1hIYsGzxCzeqlAM7Gy1BlaiaqJmeUeC3MlV6T/LabCJgvLoLqhnFbkKcZT2S8KXiZZCc
HEwf3ZJ6SFSp4HnR8fxJpczVPA0lHj/fw/1etYC7a8aqQsV66iwYBJI/RoSG17F2ckIRvSF9OeXJ
l/iuM4eIhlCK3BVXQh/6LBdaxjgU0bSIR7RBFIqiJwUQ6Gx+GbyL4z0sTG7fyqmiVdSutYQISP54
s8vO/xbLOi133aDXJGfUBmck8tJ+DOeEZfgMW/Em0XZKoiv7g+B7QdgG5IPQs6LLE+Nd6CFaqw+A
ZpvftMd5vWXCPvomsVr6EksQfTO3a8w/8dNPL6wwe19J4cQjm//zZTVj+Sv77+X6O3AW4BlNgGgE
8D986tPxC5QUzQtrhioBCbcZXynIghnpsvtn1W2fmUMPI4EyZoB2oVAzuxFPsv+VuAQ9+0oG2Ngc
tonrDNObRm81IYeK3WirFgzzyWus7+CMCGKV4j3BB8TMda4B5E+Tm8JWOb5YZ5YT6A4HrdD2rec0
LMW6d6s6DSd5Qlxago4i18dziBK9aBjWi7WSz/RgZlz5oaUqlFMLhOXEveZsQvN4D8Pp+J0pTe6Z
/dzfqJ3ugmwHCjqoGEI7a02J52E6zxR+wUivJMi+ulqet/IclVZov5f+nW4tRGNX9ERaCvswVmB7
o5HC7BLTNMTiuM4VTyeGaWkKNJ6KoPU3jP1ZagaPO7TCYbNpa2Ucm0d/jhyZf+a/Zf6VJSH7xVQw
eXzF3EEIH5RKrvC+xxK66+o+na+VSiBc2sS/lcelMFnH7M59GcKJox7PvelaApplYGmu1HhYuQPh
V7ntMkAq+iHAZzSoDP0H+oJ8/aS+Rl/WJI+QliqPl4ryYsBgqJ4YIRrCrT3yeG77cb+tqH3ZphFl
X013DgdFVf9Onbt7YGbe1xJ6OB2oIwVFF03m+Dlu2EPUAWYPxDqsQviyvvgJMkvRjVf4/F1F9brk
Kaqzr0kf1zx+WZ4HgN20U5NfnGDJXX0ElnZEcQNtquKh4vVtca6ZK2hM8/2niRhRo+q6DEGVdicR
f/R70OTW1F17C+COVw8HvZZDy1NrjyNZN78q+MliX+IDGaVmXpIOohyKJJ0IEvO3NR8ypNi7/5Mu
8hB9z4z8hcjuNI0H2C0lt85iZQr+0z6/xbX6cWKPMDwg3OmFTLKsTcRAb6j5Yb/Vghr/Kcl7iIRk
ghPCA8YZIAtc9QJ3Q7Wp5Oho3IijXl58MGPgeSGc5fTYpUmzraQC6WH4l/A2XqYsUnxxJv/Q6Eun
T6nmxz7VRnm+qqeYjMIqoC5aJT8x8EA2V0d87E99+35s3+cg2qgDjdf7DjqC0pLjAx4ZmpAR3V0V
TB6CpqQ1ib14cQc44hehjJtnsh6b3X+AkEV6tnx/hHQCYQyKrRl+4GMr7ZDXoGxp99oj/Smea1VR
y6QlifWzExTwediQ5bw6cFWon1aJxYkzBjP4F9OpX+bWh0f2H5vG4lvomfq6aL3fs0KO69+Ahn/V
WJvjShX4j14va3qyMokHSO+pZD0gnug5JxIX17RBb858vippxAu3S4sq0Dv5ukqqdDOGwxcXVIL8
E4aX0B5hbvQCQXsuhLDm3nxKx8rS4RY2PEtr1O3vjXpXmT0Njlh/aWAkT0ixQjgcLiiwLlS0RMNz
N+h36df00ecRfQnIj699ivEr2okPSoybj2Uek4Vvts/RzqFQIm8Xx2IBlxMpRCm5x/f342jh4flc
DUQYvDA/BPZJxv9w5FMfarFSGpGEfy/1E+iwfwo/gBEM0Ja+Dsb40xRKp5BH0wPhrKU41BF49WkW
DdeXIsZh8mgYUqOQOPdKtIJF0KbLwyau7/3+GBSYWY6lR3UcHpQUouqX785TF5gzi42Pl6VK1S2/
jcxlN+DF/0LtHurq6vjnHmYPZd9hwsCT0eG6CnDWSXKGp2KkJOKHG6VKYxFXtNfYWusUK/TXLAEj
Hs1BV7y/01bO+fQ7+mYzMyblymC4Cx93hdK43dUizfum4SyHFzO2iz+vSOZcSj3yjZ7X7olGWqQS
ovCnW6uMmt4BBLm9RF6WzWiv4ooWSUOiObzXpB1c44z21J5ZEZYLzGbUaDjCjpnA8P2cmzb/SgLM
9Z3ni7AHilgR5tOPa0WT4il1G1Fm3CuOPbHn7aSNj3fVkIzAkzuHUofcf7O+xN8q3sHJ/N2x1y18
AFc1zgyil0PqlUa8Uktk9xwKcRjke4RtmQdRvx3SDDOrF63M4w/fAB2ahPOKxJmpnO6z6tV/Ummd
BX3NQFJM7eik/aemxWqKTQgF8g3O3WCATU3jKz9ca9NQEEdlNG105IUMaHR7zgpt3p4Goxz+poN3
G7sP0KtfU0dNGuwhxsNIFT+6ggtZEAifIRWwqyZfj3uruv8HaxEGYSiY4UpiRxiYhA8wUoJCxqIp
8VIzIuje/7rlZIFlK6uHMMzLGbRo7Awi8A836pINVt5+W9A+S8HFj8Niid+aRM8+cAsoT9aSpcBE
dImXdD41I6D6mBVLktMV/SvI2dPsBvX/zbMqJJzuj+YEJcp17IaxB+nwXjI4O08yYpXtd9zL6AJt
J9mBg/UELr2SKRPC/OfoAne4H97XpsLeYN42FugjOgx+H6lavijJ4v9XbskQ44GuJ1vBK3aIH68+
RmeLfhjkDnTI1nvhN22ZY9K7K33Nau/jFn5qtey11AExvUxsEaZ8t4EeK12jC9owu+X5k9hmGRHt
ff+fWsON2CSa6EXJa6CMt+qVjFRlGuDLqu79IhLHcu9VgVU4bAYAK4k3GtcaEWoM5kP4MOJGBXtm
WsM4ek9E+4K3XJGkxjfzKEY+zgXLikylv6rKJ5uLBSF7udE/jbL6hUGr65jfhM+9IvZOSC4u3zBd
9vF0vCordUJ57LjjQvNadgsXy9IJyXF5bfOgyEFc6f6C1Wks8l403dxJ525+I9mW4xQ2rnwNGS9z
dkmlQO/6rmSV7QKoPQXOk+o8wyYESQNN+SA7/hp+803etparNJMNhG5MPO8tEVDF/nq6t4rs/5Q7
AXc3jChE08mbdfJx6Ls3lY9pMzlU4+1W45H/A+ZvFFqhUjWCTs55HjTg7jHYek4pcsFfDfG/vwfN
47LEkoBkY8ZqovqSiQYc0NG8oSvMp6U6fzAjflUm5Bp60Ic4b9HbaiN7szzY/oVn0J4P/iBctiE1
i0seCXahQTknNZeFY7N6Shm0CK9QIwkak3bGtMsiySpyshscQ65JoGuIfDekZIfHx2VfCfgb1oWy
ikC1SBowqBPHtLzhwsMdJd2ZV7biLskNtZXI/X2PbUTKgtp7ovS+A7BxWyNAnPk+Svifc4sp0Q1s
AKPeXypklQEsu25GWnBSGzfjvUeF0FMXPFBmZBtyQOVOtvSMprUNyVNy6XcvDjzQf7irCBD8blQY
yWcBe5A5KNupxx3sYu3PylKx0mQnLEq+N+ux9JGO5Vhd5RJjaHEoqsuLXlKecSeT6ICupwYedFFa
fcVrH8/bA1ChNtHokhSKywQNpjTXucfeUy7+mLguDwhV/B+LLKUKcjA1iLc7XflMeKtmxCAv5V9k
qefx04M2S02v8jfApx/U3cqC6WLffJahtdN05wSegNGDrQjMNzgbSoLt518V8SwGugFWjjd4XBIY
TamWq/dUj6490nHuzqfYbHIEzusoz6m6RzIAwPExTtIkbi8gO6SmLf22TNw/AACur2TPdqPr9pb5
W/G1URApurxFVdBrk3C8Rr1/jdZ8Y5L7RmocxiVT9lMr58h6NuypAu7KdPMWRguB7msALgN3GqXw
Nvj4KbTl6rCZbUfsFqmUlncp4qRp43W9z+ikOI3sKPKbaGfkSmDmJk0Twr01GStepUfY+im0B3cI
0gpf0eTCzWrjckrvZk9x21t+fXWM4ffMnTo2VF6yJxgfvilm7QfMqd6IeQtiRykADHvIw+jYh8ry
OxT1OXsB3LQ0CBQWRAfwnvZgZQy6Mw8bHzKX/3mejCXIXvZLDQmrihSDzdNK9iUkA2FeDUqUzcl4
kK/oPpg+te2Pd0czIH0H2X7/3Re3EcUyKa/Hnu/UhyTC4gLBSOab2vrY+9+Y4fE2JczIh4a1B2e4
QtaTPbnjqx2OyqYdIDwsKrhhNi2fxfjeA/UUVJ8AeuiEhndabZH6guegeN9Lp8ErY5L6i2AOYuOi
sbqYek5YN2vdqLeoAyczhjvhlKPwYApZnR5ii/L23daMd1rxKm6mILhkkuWguWAXiKhLSkJzyRtN
ZXZvWWL7B/RsnVAmsISWBnwe4v60RU7eJDx7aD8lHRJyFZLlpHkN6rZNhnCfCEO+d8iyDj9CRr0B
dksdls/eZ5XPltDdt58vZPcT5Ig4pvhkPoy3D7WroO8a53TXv89IYwOhJsK4ejsCJkMGsRzGBurU
Xm0h7ZmcVdAm+xH9OBznpf1Lcz22Tu1HtLOJgFTqrAuM5RXukRNq90C/BXhbchvir2pp7SIktxGF
K1BpCOtITFLvdUteepyLCT4uiCQX+kU86weSi9gAq/UhJQuMP6tJDlljtLA2HXMk3HbQqBQeu+Mt
h2Scf5QlN43E/9HPWtJ2g6qhHL1Nya9uF9/+mP179588c0zVrF4/WBKj63ARtxTndP9vIgOEi/W7
P3yR+xUQAlNYyXhbhhRwcePs8yA3SZyqhQr4rAcjSddbUE2zc0CqVPrPEeNREcLjCQUwQVNMJP9s
94Br4xmCmnZiR3R81kgDO2rCznEXusLp1ef32HaXZZzCMJu5C4xKFiNb3FynPn+h1b4i2Ogr7VaD
SlTSq5Y3bV7kG6OIbXInQs2v0xzJEED0EBieQLnC8Le8BeFz0on9o+N03qL7IEd1XDyPD9Sv21ZS
U/xWM9mC5L7GZQ65Bivdewk2++wC1VbOpkXqVTPjyvYKpyqg1/Pt/wnUgHYXHcesAQfJQXzy4vw6
Zz6iNTrYsIR8o9uwRiVQoN9eZVdvx25fHVtjYyV56IxQSWYHBYONjqrr6dwFM3pXVsMrMY3Q2Gmh
4nESUPOzR6F/QyvRmpYy6FOwpbRd5yuLkn+8TREmeJD7fkleD7XH72eX3ZHqYRoX6eCedjIejPgO
mu4oYyozaRXBrN4vzNQJMxswRp3CMplH154v3Mq1Gtg4WRQaFT9ryzcIMNJBwp5M+wOKTvGpBqDs
UQ6DBInTNhItCELEs4S3hgizgX+sQFpV0wj4opXgT4UdN9k0aI/HkukjjLKZSG/JRxQjnaIc/+T+
SYfF+C5lIsMBnSLsGXgujLK0Io2uq1GqkJamSftb6r3UsO2YXTVf1pwh0wDa7dMthCp5Kmbwx7Mq
HGZaoVDFL43iMYiwE1gDDTsMszJTArI8giXkkr4W+Dwcb80DxDEDa9wrXeL3zLZwlsmtoMUypI21
fCyN0UhlZfwnk2ymXJxD2mDV/njLl34+xP2VQ1YNQtOGMLjlxoXrQlMyqiFjGJT1O5yrNq+bLoNN
zxTd+AS120l5GUXwjV+IXanvxAz1Nx1uVz0dWShJvynOfH+3ELKStN/OQ3XY2WE12LV+I7nraU/A
u7UUf8+AmII6txT6mt3P5BdMeaidi7cekFhTCl7uFSkDkGHV+3FWZIOxA35VA4033XyGGIbAsNc+
+t5XUtEwlE325fQJPRuQ5Kq3HQOQI2ToFVIT/7FkSurfpzxoArIby/uIINf6Vqtid1TQ5VM8khvk
kICapBGCJPTxntOQJd8xvp0IxWneOl6t9UjTzQCljQ4JqvBGOxjJYDDsRAKcepY0EPTFcqSa7Mjg
305AOJwQOq3yQGZQb+V4zFHaRcrl/mhaOfKVObGSCqooMS7nnds9Ky7FbznZQkHGIj93n9eYeMMj
IiSYIF/3g4not/vMeQnHCznVFOC8+c0vwx5hRURIwKUT3GidcmNPzCUVa7wgbYMpWCR9GiV023/t
EZEmrmUyBBdOL5pTv0TxjX84S+PnzTkcY5qNPmjKd1hKIMWE93GOzjBrX6yfmWtL+vV3QRtA2n0Y
wX+PqzYZuqVMqaU5NzQ4xeuC8++VGLoeMtkB34yFYr0ya7GGtpnJN5nLPxlvKMIzAvO9eg0qRVw1
avJwkCzuCb2V43eFVGgaLyHE4AtQv2/wsKt9YEOeO4zVk39vL3xRIiztzF9lHnvDqaA39ZRITIna
lDgMNG8Kl0Z2/Rt+gM3rIDF/h4ihA7npVQy+IAAi33jbRMZ0PWFqAn2adt39RWZFbWnc89P8F6UI
RLdIJguEOVTV6DqPcVZmeog63g4UF14h7QV8uKy/N8WesETIpLW/PQc84zRXYC/IDewCEVNbkBkl
Sj8EVxE7Nsd093r7JEJQRiLoi79XkNRG02gsABrUYjLkPGC55+pJIxF816qAZVHH98Taa8bcYv/V
BQiCpmhYDz2vY4ULFXzk4UsMS93CtAztT8M8VlwV36X95b6Id6vJrUCS4mu0a8SVMcBbZW6VngZ1
ADdw0F67DMKmkAD+ANQsfwKymtEbSgwxgqmn+4KvRD3iIXepfcAIZSu7rpkhKkH6vaBM1s1hR2D5
UbBoYoMh/il15IulWmtKSkUV+AMnwoYBcZbXI5nFU7Z7f+RPuHLCXUFQFBBD5qgyb7t4H7cBrZ7Q
E65VV+Lk/leFHvp4xlZCCCHnse626SjVaF9YwudAZRGPzrlw0JcFan4e8Z69xN9amVC77TadH8Iy
NsPGvkuJsJ2vkR1TVfbDvTiQBCQJ1QyGhvFanCu/bd3tsz6CK86UW1+OVsNkrJtpNXbdZjnujDb/
YkfUNfGNZWKbWZHvpbx6Zi99YRDnPONqJkf/VpvYh+qgIeOqDB31OKL4BF/eEWMxVtd12TOHUbyK
AcWlOrzWXjt/sgdH+o50BQEy0CwvbLzg7yif6yF7Oe1WkHLpEpvDncnnCuT7VbKIzvxORfj6dIpF
xTqiJgtW/yDtxk1TxMea1ueXnJgycupMPL7tlMjP5Elk5l9AHPNqPe03LeuZ+y7amHIuuSxkuouH
GpzVOz1haQY1Zub9c7cOrkJew+HtiiUYT1yPGB6Fml+EtEczYexkQ7TM0rNCfMz2VRuuhN8pgnsT
pVUW9Sd24tYD3JZAKQwpztCHSB+14yJy/USxr7c/AqUW1pDwHutCx2vyUdIEGEhXTvfVx3dMSPJR
4SBsVI6jnZXKjUKDshzLk5lvGwZFyWsr7YMTUuaaVVK7p13ceJOYTzbCijWZaBTWir5Ckuei8FOH
MDg4XwRVhhnzCO/1N83oUvXpna/1pFqli3ojqVui8TvHqe5OMrqXtu5Cv2xHuQ/sFW6JVxz8gUyi
g4FkKwdQXe9XaV5rRyFZdz4+bhevQYsNMPsfsz5+DTL1P97PdojRYgMxQvVG+EAP5mPTZONRTTJq
ukj8wkfPoHtmEV9CdJQ9xittlHGP/jzlf0hrf4o66wIeMfBKbalHmXPXg2twbTv4SRGsMt5o4XXg
G9VS502WCgKWkReK91lsB+hBJkUyPGV0DzOF+DkgqD6KxgFTM+WX3qRcreaH1pjTI+91nQbfX67s
4Y3zGnYWvv2Jtvbdms1oIZATvw/c7lk0uzScUPBpWBJo87HYTK5Zs5XzsDesz04Ty3FEAsksxDPu
zlneELuer3o3Re3X3gCQbRoUSLGZ+wfySM8T39dtl6cHc5abPVEpb9kSZM+qMUyARkJJYYzJcgEU
jxoeMyW3WZbpasjxQbJl/0tVWBn4w+2BuTIKhSeukkcH4Bn+37k0m2ZIvL/GZyNMuDsOtVFau/gn
GPs6xYUr/RRBcC4U/YT9dWiZeO5Ksi/HFPqlsFP99LY3NBrxaF47UdwcWSXS+OSgnDBTwdjljg7z
62qO/JngqL+Y8MPY6/Isi3Oxr3vIfbfh3ee84R9PvNe15xLS0eDVXLsWqfzrEeD3FOlsYPiIHWfQ
OzP11A1q4xj2wpRGOS31gHxI5VM2p+kOtFUhJu0u2F7119SF2g79VsrFzUIvh/aZdByVj7nz/svV
8xIOIsXxsdwLHJZ8TlgTwwVqQXrdIR77OTiw3E4On5yHv3GMsidQzLq+G8E/yuGofFTI6wlWLXWI
1WhrIv3rbhFtifrnZYXFCgZsLR6++rBasuCwEFR4w7Slhml0lmAFS76cXiPlbG0wxxaYXkAbqkNd
aR6tF3JLWfRRfneObzynnQta18cB+9Uw2+vLJPfZQL4Rqsl1Vt4qukkoPEQBxQjTAprgrKA4urYG
+d+RA82Erh0oy3cR8tn/Y62L9WTKkknbxSJw355NjNvpT+iBLckmIr1qy4xNiu7O9KxUvWj0Q41s
Cqh2xFroeeeIsMPLQSmjGd85Y0NkOm4jnJVDQ2SEeO3OWY6HlHruuEi9NzGGcHZc/f2CNHBMuBqr
4UTUheuE0hbxkCCwhEvInj8UfEHNjed/o3o5+Euf8LqzZaLWyarhqOf1Zdc695Lzp6uWrj3T0D16
sslFDz8BykhAEJ71k7P5w44Xq/DPk134fYYvJhoa46vt3+nOdSJQ6WjDkcR98hHf+OPr/tHAYQ2/
gShi+jzS2K8f7xd1iA/ZOxfnX2EQw+Xh0e5e+yc+d+bdzgIG56K8WZ1DP9PSl00BF2REUaRdRQN4
eHBuNR/MkXFpL4MvquMF/J3jAgUQP41VSFMHmMiz/EA5skQvstYeI/aX9miD5CKJVc1pWzv42gm9
7sE9HyvGPpmdB1Bi675Ng6GabnU8iZb+WLzGjsAo4ob3dJ5tW4GgCMMi5w7HFSu06MWgGLzU+T+E
bdhpYj+xg06CM4YGVrEyy23wWbzAgLOAeSjqK2yTYkzx9kpHZje8z6/ZPxOKN4I7yGYPbXWHiZaF
5+CNVBALddenKrxFK1W7w4CA6r3XgGVW8bdjl/c3cxz1/kG5BpZl1NttOTuPUTjBhirOX4ysYlO9
GZrWXe/j+Dq0358ifFzpzPyUsNa6Va9NJmtrVFci8SbWjT/Sr0kJuaxsCFyW2wtVmoNUK2V2QD63
x/enNQk8HJSK7DNrCgJaH3ClXUy3DVQbwO4rT8HU2O3LTi1FcGskWbbASD8y3CnpbJl7tb8TrW6m
I67IAx5lSOPK6MfpDmxb3yM1ICrWKNMGlIdnTvE104iHAeAwX9Vx5G7+dulkMBKP4r+vaNwkmNAH
6ddib1hLAqt7JD7GaHfKIoyk9Fqmt9bEh2MVg3InxFtmSQdGsfV+cxQpUqQo0vOIDT53y/1pkfmH
UR6MMYX4Zk9MiHob7CCh4+QVlSS+Jd+MUaEYfaDn6WnA1bowUq/09+4pMNy51Q4UM2hMNcpsHGJh
TxwKEBabQx0afewYPxRx8YW0JsRpGhcPKrKkLR0loltru5kpzzPTti1ET+fPvXyiXY3pt/eTB8ef
I6A7ManMpdxuHxskcYqwEvpcFCpda1da3DSgchFsmIg6xh5jPEuJhPrESe8qyE8RjalGXGWBsmAR
DSiyjwFxjSVBcvFHrV0T7Sp48/7PnVGhi4rQ4QElDDOPWs20inpYXGwIyf6BoE2BviTjfE9D9izj
fGhSig9aM1VzMIbqAjQTaHgjPrSP5lTDuNAhejj7+CsfEObqGFPXvLAjvD/ow2/PIjAe0TNhXdTN
Yq1MG4HAu7YoPemtJUQgE2xApKaQ3UG9yTekc/yqgnQgt+LiPzJZmwxuJCY/ZEjdTozkW80UvI5Q
qjjCzR3bz2/8WjWrU1KbtNxf0eCDrCQwwhrLwHrgE22Q3vOtgvzqr/Qi5t7S8ebZhpMSkC6rAvIB
4qDKT0O3L40nYJoF5MdKyFQPWvVoaLi8r9eRj4P9TDkbdV8RF4sIfiT+4Lx67WhugoHQAXJV7Elt
/bTAUSVTH2Zk1rE1ZHH9yaEiVPAZGHG9RbrUgDVSmU9ncN2sjEhjkv9I1YaVmDXcrH2vRgOHkKFV
itJ6NA1YhlbRG1Qd1RNzwW0oW8U/Nwh1Lrn/Cr8ewYpzf0BgPHo3MjdctsIvTJa1TXsm+y7MVUOY
XL9F3iuPyTnaGtr7pB905fXXlGryUrKjIomc9dtd2Xo1Ot+T8Qiu8sF8tpRMjbpR6Cq0UYw6Z7Cf
2YIAD8O7KZJfEv9rI3k4n6t56/ef4ZFu52jd/57Hh1tAKcCPY7lhkd5yj3MAM2P1XntdSCbBBU6D
SyuKDdi0nxShXxNa2E6SxIznuBt+jFmoqIt4beLMj6H7WH8LsI2iPK4QpV6hBiNbV9FrIh9p9JVf
TyfIgv7JUFVh2C6YBI/Ca2r3Kt/FUm5d8ZhdA5vHTfj7LcNASNOm+UThujjyqL2GtfDu/485m9LM
cN/5K6yklmcggVUgMoB5kn0I518x1P5cJDMfT+KCa031qhsTQf/JaiVXyRgMn1EOHKuvDcDOI+wP
Ndb5xtlo+v4g+gTUanLxXmh+kMF1vhTvzP/1qFeqssCjmqGIQw0DPY20fTBo/FiFU7yfwAQMCh1v
HcWwucIPoC4DM+gknPvqzzFUFtdil3kg/gkqX15FGcWpIxncBzq9F0aOtDeKbT0Hfn7laDij3U3M
ntceidEf33PTtczar2l87baaMcESJkvgH2UaYcsdyA9uk8wrFRNa0wpmDxMEZzsJVc5KYimjHJdv
xA93MdHneiB+Io4rpndAy5U+RMORTb0y9zRVKq6HDJEOVNxw8aq+XExqPgdnyvqhPK/KJVWmjd14
JyAQX7RvvH8GAT3DYFBjQIeZ4jTAxEtl8UUmTtJwNb9ihHZ3onoyBhdxhvJwdSuWoDN9LufkzHex
iuzAz72TjIfkVO9FQWc/XE3y7R9Xd4PIkKM3wrMjXjtt8Zjf19zEb51PKy0uxyaUidyYkl8fx59l
qRkYWa3p78bcJffhToUnT0khX8Hk5HloZaDSlFN+F4G7y5hcGevxu6Zo43lCfc9HKp1Ecjz5LqbW
33xAJqsju92Wp+NmjI65TKs2WsuIAfFoBhH/ei/IuHV1gnMkXigNwDYa/eqoT1YA0sZ4PfsYDlev
Cxr/dmPqFXgbIXZUCN9vm5batC8xCMK2vdri7zX6/FYHms1eMlgGY8rGPDQ0jAyf5LsGLdmmPbQ9
j7OFtPWhKzrFf+G893TsSBrSLSUPe9+QX0jtUdxDlDt5fLNVjaDPpFEnX5Xx7mGu17IUQX1Koarz
v5SXFwSC7M28KLY5/3G3okTuBr+C5LO4NSz/Q+pTveh8sJRu6zLYQdjFpspQoi9nnRrgjWKahOd5
jVrxr6KLzS+3MF16NygROXeYwUY9ufwsWH0C5zK9p5WyZlNUC7iGNviY8FoUZGzdHW+jkEtBEY/V
01ma5cThHWOZSzwLHNtD5weuxEaO7q11dMZudu6waqbfLO/SBIg263Umn+d24+P5saUNrliF4w9C
ZQwCfUO7FfRiD3232NJhNn5R7Dz6YL8fOxmSnQ4iz38+2a9VeX187APNZvqbFs4nyH7uqZGyyH7W
1sQyNrg/PDCqP4OwRf0HJWM5EhadfSGa8aOgsD5X83l9kQbNydJxnRy7STeNsA6sLlRBdZYBAoWr
0DK1KrJHLBWacTDnYmAaJO4BUrt/8DS+2L11Ksz1iGAbET7IeCHPw3+raiD+wk71iOGkKorifIK7
fzLJP0HzQ/54rhWQIUto01BjshJfJ0AVDeEG37rSo9FHXky5zLL63/LOUHQSmc6hekUpXDu3Jz30
ICmqbyaCBTUouXoBWcSD8rXs3H6U8uYvaAjsEZMIc9KIhtWy9S4ad5/HkWQG/4XSmJSZlflCZCEo
qNdE86CSUuj9yXLS8KOAWjiZlz9FY8UvGOoiXJkDZCjEzWkpXTC8TJ84soa8VbzH509KhnZaLLz8
puDCrbm8ZUfd17bi/XzfOYf3JOpzQID1qb+0wr2gKZjvaM1Q0vXbwQRH3sftbuoOnDgWZLwgn225
MtlZn6lzkpujx6j3v4A3TmOyptjEk8dIsHj1J3BbmbqO4oiO0eZCUrBu5U3iYpN07ee1S5ipePl4
XbOlN3d7TCa/+PFwdSr3OSuNoPK8tDAuikT3UHIkjPQ2x7V3VROO9KhCaQGD3dU7mfZgn9XM2/X8
v2E3zgJORDqdQR5GiQc5NQB/BrQTvHXUH4TinlPMTZPTJW8hwqzDE7J5vVuo3X/q3hRtBwPB3JZU
9fwpZ+GcgxIL75Up/h2x96C+CP9LXJmg97U2QJPjnFFfq14SPg8o98yz90bHFv9Yfenrs7zgV8Fd
/dW0hMxsKcm1MJKQn+qW2vtckDsOyLrvKLfARMpQ+7geMx7aQTPCGL5rlK+FRBANzQ3BK2t0nv2h
SjZwMQ8CF+rrKHusjXnBYpz65Z0cINrSvEsnpZ5Zc+rEX12hvoKsFNs7H/8sWt/hTbRcun1JFkit
/x5C95V0Y0HXLN5poPwhv4aAVKw3W/F2+Iye8dpM9LMqjpQQcldE3tqydYbgcUg2a74loL0l7DRj
K8i16ULk6o2QZMdgyIuxg30FHa5Z5mBKdrMPoQ1o754ya4e3MsxxNJKC4sbxvPGtiz+tp46+nb+O
HjMCrSz0iBUX2D3GBQL05D/ZcChFnJLjuovBVjEBDVvxSo3zi1TaWj+Wgh3U8iweTtWN33sAvain
D/fnrp5OKC46OXyO6VaFLu+fzao/1wWR3FU7YTOJJVIJ8trCiUaZZyyr1lJ08s+iMiKafvjL6JEC
JTTFooxsN8W3xcnCO1AbyoUiMHA/wGmdUeoNdhhdEXbcgo7dtfnrTIyYf89es5C3Npt2Cqh6W0hI
hhvCd/EVS9/uC1GiHOJFcx1KbuOpBTDVaeEgA7IKrcXY/6mWroSYtywngDYNLxAEywjkzwxML/Ga
EB4wlZ7yhjWUbudnHNI6i7SbaMY10Z1S9ZWOw8K52Kgd5vLt9fsd+/eNREvRJX725zVE9DIUo269
UxKWVqwv9ismsaasLsILKJV/74xeRkHtN6Nru2Hkp3cgHHr3ewl/uyPHForUEx69knU1FMEHRHKn
R7p1FKmmt+pa4Wb7Q4XufXo3+bXd+wPrMIqsyZD0Bg8CHHUyXmXBzBlTAI43/qY6TpwumIlq34BJ
Rf0KVXxUeRPOmeBxEkMJhyHs80OCQ3Fki7NtSDwFhpzZ963LaguRkUPHd4vl2DDQx8x9hBuVVF4N
UN6NG2nhTg8U+KH9ttUUV4La/qxJmfEcrq4mQqO4SvnPzTEVYli+GV9pejn9kc5L3ZzaUJDqCfXg
HTy2KNLj5lDVQlTzMvEwepbsX4bk5InYIoR12SkAfLbfd1ai6ZXurkx8B/DlOvbNcoXq6zPtjYcO
lUxQWyG4ynpR38UT0lWKXItYaVngQdljj09vrifcdZrJCwFyKY98JqB1rnc8lJwMI9c3j0TEPLjH
qI+nJu+BLL7S/ZBW+8P8JkCcEYH0FlSwKSAQn25GNnTKqvzLqHIynMqcdU7VVohG17fZR2m+1r8x
tx6pKzPTb1DClP+cki79pVx4eCB/4aOqHG0jH3J4n8vqZbEmSL9TWfrAX4qtwwNWDgs8dbP2psam
8uf8EZGY7qrVcQBx143R3pAjvls01dVMg3d1Qt8J7JYKW5JCxLPF29ZSv5rwm24uK7CtecTS1aaF
wbmCS9YGAVZPUI9sDBe6Z3VZtImRnr8/fZowEZype3iKaQhW3mU4izAHKOEOE/QQYtktEs94P0KL
hETMs52QnqZLxV52J4A0mBqNKNDAYZIdm0BebahHUUklNhPHUb6Tfq1MG7PVpMMXtMhNLrVNbjWH
FXJ5sPWc9ON8BdZq2NUaZKcxqUxAExAG3yvuK4CfQrLBnKR64QXDRazZETJTK9tgtvNzMm/36N9M
2J3Kd3fschJgUFwETCfWabs0YjBZz2H/FmCirC5Bju2phgKTILs7QJPi2tPjuj1yhp1vvXoQ3AV5
4Dw2tWaP3iSRPWb9X69RGmkxvcJn/CiF/50SBwfbfGDx9D7GVgpRHCbY++uT230GedR/p3H2k+51
ef1A/c2C1HmBkLh+FIlf/I/VzEX9sR/YiKmiUawymD4QPOia8ulvM09l0ni8PujIOBWpVTniBbWO
CQCumOgmOEgI9SxMT/sWkcmNX6dn/0f7CGRdjTIKNGyITGaTW/qeUvSh+s0TE6bbv8Ekb7Lqd5FK
VGh4wnR5gkZSbxPowR6VRUECjoU4lp8v6nekXnKEfzV/TOQc7/48of8xB6f1/MIaFtNq2QXX6sty
FCLQmyMpjPQM0Gu+1J9B0p7T7Sg+XSjgTI4fkPrS1jmgDn+5pniCnLwEFLMLw9DvFbdRL/b63KNu
P8SNgS3X7rhXE9/cmvsBKZc/METkx7oprgO9YgsBZ+9qmRcXjzyEpD22PBFa7lulLVAMWAfA7KtK
EDqbQAWlQwwSE+1oR/dAVud/EdIrIguqzRR7OUS5B/mbryMUTKjYPcu2+7VSg7EuRo7c+UxLM33I
vs+w1FshNqwVYZQQqLyyE8FQiijaWAvHKsn0EdZb3rV8auM0sWjjYH4HUHOCQT6jkXcSnofM5GHZ
hEZnOGdmcj8vTmNIqA0g+ACWeYrS2ui7oWxUsI+BjSpN+LqNH7zT6XN2Y9ZvRKtYdXBNjvdALIXt
6Jv5mUFPGD7lBsMQFsHXWGZDbTPu5ww2JyeKbWIIklmefam6EBJU6VV1d6XM9oGV9FHQrwbbdF/f
Ux5fiX+CezOxKL+aNEMxM0ikJi7MIQvB7yAFtb8T6rcB34lZ6PA0zH8bJYyhNl8YGlMGdG55yxkK
yYxrLFIPEtehzMeYS33FzgQ2thZPT2hSkPd+ePwh1OaX9MUXcEJ/0ZJcgRhmPwut2FJuQWou5l17
ktFjphqUKpL5oz8z+3pExTgS6ShVBee3+yczLl58FBAMJOR0WBk28kC+0leL6X8gYItuNWdmiqW+
QYf/8C00rj3FOQaypxUbQm1QCmg8lRmaxbySPEdx/3ivD/Ypf22hOqMceV34SmymcH+gqAWb/u5D
48sXNvsJ/mzCd/lRsbPHWkQfZTg/MJN/rlZe2GOocMEq1u/edp4/WHS8r9Jh9iu6wuLB5kHKz+3+
bfyuGmhgzWaDT10DVCCd6DxCeSScUVSAx7KsIIRQH3JufGz0wnPQ8jdKQ6PvKwztqlsqkFc4HTuN
VO+rbgErLRWulzGJN6Ku/WYielhFPmTtdLCDdEDQxy8E3Sc6whccMdhs31pXbnsdygY/b3htHzT5
ub3RRadXqKINujwEl1rqjWmaUPNGNIL0zEF59EAkCAH38i0SocD0MrV2eAedFK5x22fNHly52TPu
9pbKFUof/GasMWZwp/jkbK8m25G6U5v3kqG0D2Z0fjgMTWSEoslfmw1KE6l2QMla1hFinqTepfOF
Q/u+aSAPeZs09FgniDp9MuydKMHUfETySkBwy8kCS7Yuao2Kp3U7qFKGRAxVIS1mxZNudypC2MNB
gbV7PlRDFL9o3Jw4nmxsWSRYB8jFnd1dVEvfLpHVjSZ/i+wjAxB7YKfnaAVNf9odrBlFyiEzkmd/
7tmoAcYJPuQo/WnS27fvE+m2bujqMHjo1L+YUZ1ZAhBkVEugJ4Ekr3E6Lx4VykIOSoxB38OyEd77
jUhzvWtGgY80EjaCOKqhToJyp9KcmUdTEKPfozL2zb9SY+afYAG3M2DmYM8A68dxH1C92BJFNtnm
d/RwMOGEK6UAF9jfHEAHKrHNMXmKMEPCXKTfmLBxEV51ML3ZgxjEyEhsNLiutjyr0D0L8QeGKqLm
RTMq1kccTkECnzek/Ibt6G46P8L29IBwOk/DNF+ivcPrZ33nHXysCZaX+OWwsjF2o1rkVdzpaKVr
XGN3ZlY1zbLJJGdpuk/3LD60xj26GjQQxGFRiL3ZwAHNAa2+h8uPirl7Bt3R69M/aWR4PxbDlcvg
2wnpe9o/ou64a595GkmmPyn1/6B12mrZnVN22qaRQj9anmdrvWCpjdF1gedoFNu7NcWHEGDycgld
QYVZGqgedFt6D2HXcofHcFNMG/DzG49MobgKhZSjnTIom/u6Vxf2iikLmRJUSBNivyxm021sLwnn
Nd092zp/bGnWLm3sxCvr4UDv7MTIdjYVtfn4B17gWWivQDGwmeqkjGs8iV6Jn1eQY5SGTl+FUNSM
00nvbbpZb8aRWOh+PMsk249uGeClDCDLdfTKxptNvmxHfk1LZkHHpVrrHRzsN1yAWJkoDoHqqgIX
ck/SJgEgFzXlgFui4HFOES/2/KSVPYNel6kNSXZZ5iXK2n7vrrC7ftHptJZogK/NZwQMPOkDpSeb
/m3JNNGO8Pa/bTVvIXu0useilrxkuR0Erz4UhfHw7cGU4dSx3MtjEcVIyCWAOgzLwhvSfNYPyLbu
N7R+iEZHyM6omUAepsidp5V7urGVFIMUnotoN1H+hfxNOBA6SbsE0AfVq4Xhh/ameJk78l5jl1r2
IBo3gr5Bk/hbbtYFkBd6S0NpWBISPfUifr1vjJjUCaWMz3n19h6Q4jjCr3st887uwQANU8KQSWwa
de3Yi7VjgHtQ52ob+NlztkWw2hR+A9W1tKP4aXj6FSE+TmVDzUrDYHY8LcSZUX3zb0MQDIMlnGp7
EiwuV4Cu8+lFrWYhETTguI27xVIv2P1IqQCwFHe1f8ma8vqN7AeNJpK2QugfVAtAeNHUFQKiMoT3
P5eLTIeq+kz/NNk29FffjKX63oEMSVfatp0XXzwS6m2P94ANoQFKGEDZV9q/FmpmthMbWiVfV16z
vFiFaqideqwd+AR8sfgEsbSIyRpgYDmnFCaV4eafSnsnOjFwPhkHL4cxwkG0EbzE59jILQgzXKvd
TeMmmPkBc7xKl4w5ZpVCO+newDRx4owO0P5w6zhKW4+/dvM4m2cyYNB9j8p6BSN/ZULmNT2zS6Ro
uVvbkIO48wWAqj2kQ61/AITCpcj9uFDa/DW69XHHR+fIqpXUG0SUQk9G816iFxP4HrY/GL23E/Sh
uOnSs8D5BXrXMk4mRuVqZMgvY21sex3X9pkeC7B93BIxNYFWh5kwMkDDCqDLWvjdIrZN1LcxwuiD
DzZuEk/44SdobtB0cMo+GT/AmifHow4PsfjEFjRWTvmdX0Bh/UelXXQD0PT1aLZjFmy3R2JXzTpm
g84PQ/DfzMIef34APVsJIZHlr05teVAFNMoiAHoYRGZKrfdRGFbcs4imWMhl7r5/deiuYFiy4pL2
JkNuUrERGbrHPiLW5oW12C9Px4egqOWxXmD6XwBlZJNP/JqLqkqirSNZF8/yXRfqN5RuHwAT/wsv
gTM+EfJgRMSevTFR36uOa8MGhUrBqHM4UStp6FSwJLltIZ0qZpoHI7Z3Lj458mQcZF3d3Gvl+yWw
8CcQd8g7uVTvdT2VynRPOrpOnwocZ5pv1ZMv68XC+acJQ5VyE79UBM1GS/AdXNYIiu0MVPSWkJ26
X/FIFiy2D1KfTcUxjNmNJe79GqER3kY00ZLy3DKlEHo3+qxiqcCJFw0aufQKaDkxrLTTGP5FanNg
TWrBmnbct1zpaWDpk+vNH3EfAyM7gnbSof7MwxTSVmvxmJMpzyZdgwMKel12bKa7psCBDDRfgkc5
sOIJ3rqQqV3Nyisuf+B56ZY3zhU7gB9xlqip2jkJuONvpbiiL5ciGW4uWMWZcnhp00LkoisKVti6
dKV1FjGfN7UQ2+CflMYgUplxU+rnOcZ8bj9m4ytpqQ2rLVZ234jl0Qp5aIfRbTqpICr5ZFwEAWKR
NVWQWp9ytyh/QnY/3Wu8RKbFqcaWCn9OQE5mlZv8NvbkYLolzgr/Kq/H0kRf9WlUsyk1Ra7qgp9c
UZ1LAoUotE4kfwh3hdsO2a92SB5WKlqbIEmZ0idVlS9/w1NhinAYMIL0Unq+C8xWFYX6+OwsbuDh
0A4tT57VW5WDBF6leUY2NLuYPPYTqxrkmSP2Yn2XNggO4WozWrwonC3c5qDz2dOK+aWC+hzkbHu+
VyXuosduU/WZjvoxOUJMzAcTultdPYKHEtqtojaRhwjQ5/Sd2RE9lF35VO+PzQyXpG+FNCKDWCDi
9L+RX06hOLUUBK9t4M+fPGR73W1SuqVhcoUKsprhMeSFPhzTM4dqq7CUIsDzKuDf1YY3HpOI8o5x
bRZYXu6tNScNla5WmdDJYoErkWha5OjEZ1pDrof0uW7jPhv+cDzLJ+C+uwK/8/5fg7552pGyLiem
LHz4AU0SMrLwhqeNbfGMz8dOXQQ2hVFER5nHVZK2pYoLX1q163jHo3QotKytmPLcdyar7VP/I6/o
LX+wKhkgcK5vRYVUDLb4J21jYccFn3yJGDygrFE0pm81A3JTicHE44NXQqQTPmhAfEaZiHj2yysm
nRsBDzzzKik9soM4/9hVU0tLC0ckLYj64AGIIZeSHg1hEdBYFQ1VJA0uZa7oXWaZmJtpRghBtAJS
kJzLICkHdGCFwFCzO+jUDXyLqqpUaFyQhwAhgOMiSBjVUFtUK5xZ43hA4pR8aMeIb0B/rBvbvYFp
ussyhIXLhjNalLlrFYOKOddETOK5I4sg7285u/3OKsKUHMYHd2U+6beRBNpwp06voCQT7gXx2uA3
OjNFFckV9cxWVi93luEa1pMKHGAtzgp+1UGXEVFNyrWCmo6t/SIZ3Nj89o7VNv4OFyW6x7wXDNML
Fj6Vad4smBj+s3SlSe/GJ/btItLe9Sz+xWYmQk80Oj6YpE0MNovUqROyHPbKCr3tGJ8tlPbgdJZT
QQkVaVM+9CIpJXjEHsWr62J1BtZXoqnJk33o/VHMyNqqBKOOVcqW66HgopR4fn3XKlNxjNlQvYkS
UQmMSMhC5+Y7JP29HmINbsIo2MmLOiy5/dMAF8+ms1Kfi29Dc+O1WCxfGM8hstHJeY0NgaY5mOIp
pdYyijE3IURBc02a1HITu8LyRAM0qgqlWzNzHUkdQoF/Ssha7fhXnH3yT0FzfElqOUjjqjwA8VEi
/N/Cl/AMzaCfJDYUqcVZyznJSXskt+cxcujoIGkuxaJLwyxKpPy4iwuMwOrUY1T6jRiQbrb5fstw
fyIm2+Tlb/pAGKaGm1ts8l0WazImcnrBEO60Oo7P61aSIaKwe72zTqUU+RP3uZaCjoJHB3sFaBkV
6zrH+9zAoEg87dFmuddZSPUvHmQQg7xhXp6HMfi1wC3ug/Mpl7LvqC1hsySeTk2bXWWhuSBmAKRj
pbOgPTTg2EXJ0tvXRPHOCixV/M7katLgsyJbpfNUnCcmiWVaDgR/BaMCZljmZk89RZoVJ7J0tWRc
ABfuty0uo5KdxJ+ibIl4O3KUQqB33H3zQ36gW5sn6Rd8p/ToyCggggOJDzT6LWFrGNH4tKpHxXe0
Arvz92dD4jUdoTT+1vxKe3sJwvsRSArE/sPftqEDZxAnXTU+xQerUm8HJVVhZ2gBw1C/bGWtCTUU
XDIeC44Am4hQ4gG+l9F5JajTsvVxr59efvIYs6y1MFyVkJwXmnJNMioKTVOAciDqYCOmhvmSfmTK
ZEtHaNP1ZuRB85unMN8n2fASQLJny1YCLW/XbX6vYdarirTRa+tJIGul1j1bqjuOqTr13alCvZON
xYlxfiRbqdSP6E2m5onaJeV27Umu2hp2imDJkNwfP1/lLWvcnNImBadanlyNe397y39NjjbdgbYm
A9EsJvxMqQJip3IuDSWYyVC4OQxv7lXvLuSHPexFvQo3CAfFf+h2/zoYQqbsroJEBR+A+jPcsfco
5X/1nok85sCllDsrNKw4uXYNTWUSZ81Vl0zJtBDX1ET63xMLC69jaaDlfQ9QA59flaftce+MDbx9
pWgaXJV6de2zkjKehiG+/Y+sW9riRRfWPrCRVSumBZ59kyVeLWRvuAoHkt09rYjOkjaRA8+sHegR
UclE4lRJVuRIrxtKItBMe5w7ppsqp7cSH6ZTysZug31gasGDHKJfumHxuO+x/q2F3xVvyoZXggXd
Uj1oMnrGCZUKIPFUAZin3CpOz30BBxg/Exwp65QgFoVA04+LYpQLtyr6GBPbt7ZL9gpF8HbfKA7g
aaOpkqjoVZZ+I9MaxVxQ0xvSTQtm4SPyS8wpyvrz+ffGVs+kSepT+G5ILXQ2nPMFc16U5pdv/L3B
mJ2mo61jqS2C1Em8NWcBiN7EhLDq/WbqHhTwQ8WQfHPLqHhnywQkpcqlQpW4dzXD/s9BpuGAl+Et
uiwWC8PxBeIFQJ5MgdTz6+6pN0sg8FSu9oANtIB79YD7nM5RC3OfIUa3/uS1Km7jHRhyMzCWTc2X
WhJlB2/wDX4Rae53267EMzzdKoMqWOliIredQBjEqMZls0fdm0D1n/gwmXvw1qMk3NDoN06kd/2h
9XJoYyUWrTQwDNKcFBT3UoMhMKQpwOFyfzs51hlJJNepKV0NfQAUnYv5akvg6FHxPa/8s9b/M6Bs
JMYibiuvh2ec3hOusHpKujuQPv6EMp0vzMpZPxpySsmEXeRb6vX7J/KUxMTQXgdIMP7s2UbhPRab
odc2OynC8sCDQ7EDdrtXNxK4YapkIZzM18z2ZNr/uqfnTBzjKf1OyQSg9A4aFruWp44Chu6VHk12
d3uWrOwiqrOPAj2++r+iMNmRUe6g9l82jsrdE28Ufgt+HDkgTOGE1XMe4YJyBmeCKnZ4Kp1pwcfe
660NXjfth7xKZKcHlAWx7a4NPCYgXBUIYc2F0/se7uthb+LCi5d0EJ/02l2p59maVu0JY6ktJcwB
XD9dOyZVdEMa/kJOnP1ZLYGGQQHxKS+Qss2KtyxBpPX5o/Fj6QzxkI8ekEnpN8iWy2qD7gFV02V/
t6nHTG2papVc9Wj2YuJ9LppLTW0A7x/cnlCRm+fAHmHnn4rjOd8bXg3YIXlmS6aeQA+zYejFXsc3
7Ha0aJJTWesGkC7jQiiKNWxxzwS/zCcsYpzmry0HagoNCpOAeOvGQH+IwxwQB2yyCzftNz32JOEM
nA2XvceTNqhQXoFglDer+pG32a5RqYiDpCOxCeSfP5CpgSD1KEC7casv92/Fzf5NX2lRThhNljwW
6tgmtdUxVfmDVYOXtg+Hcc4rpAmdaOgj1/Nh+SDpAmC3LoeQJ8l7RuL2B4W6DPvXno60xhR2pACa
Jr2M1cc1x8lxnbO4QWkb53FOvNB4X25vet8EhTjiCFVn6CQ5JWkm0jdsl2fRpw+0XJSnnHP1v650
rGpe0dhpVruK/k6q5AGW+uPRyAQlWUUDv+B8kTJQadQnqKYGtkvRe7cvz0gk6s73amI5oD+rBMEZ
PJozQECNrQ3v/ilo7yLeFHxSibwsW9a5VpCUfj4XBHhkth7c/OnLq7bb5CiEz5kj8zbg9b5lYhv9
tQ8pyL1Gxwpc5tfO7b9QZobdBH2P6ONfL9+n7snQvrWcBAvtBktUgSvg1yxouy8kDvTAL80d10BL
RVUMWXRcm333H0f+MGaEWYr+A5n1OMqo6imSMWjACgTwtoPjIvX4IELDkaKUqMCDIcqr+hBIutAU
l2DxYL5RrIN7fY95WtYZ1TW4exPFhowNoXcsc9gfk/mKJY2f2I0JLhNm1L8aDLCyWDsrlmBOBGs3
/cyoJH/Hz0L6+MT8Jt5wQS4omInYIV6X+lxUgEG6wZ89HrhN2IlpYEGBCc4XI+iPtItT8UCC9ZBf
h6IOaWeVCxOg8hx7ZRo6E4daiVIoTwjo/SG7rNitIF6TwcZa+JQOmsROSuXH1zJsQsBOEjbTx39Z
+m7/xOVVW2JZX1DNr2kf/5IerhGjdhKmY3WtJlIAnyFUQQ0SuN4Q5IukvPnpyVy33SHGyWiUh4uq
9rTe6ONVwhf/r+K7kZ+Jvm/7ZYGzOlNcoVGH++27DAfs8V3iRLLAy7ZHAxQhk00yyUxzldRFd6s5
joL7cH5HboyS/DlU4eFPek0sKNm/Lg7nnOJp77aA5OhCUP/UhPZPrAyZfR3ZRs4jC2PVLZXfa9Wf
38YNrL+kAfH9MRi49/rgX9nxAO3E6z/rg+o7Z8LoSh7+Bj7y7MQMSWrk1qQ5ijTD7S4dCNYrSdel
FaTt/h4ct8A9m06c7UVnpL+SZjWFroknrhxwYI//i0Ssm9ICvdsIZXlrZYkLjdBMkzhjvNAjKjhQ
HfA7k7QmO3mwLlStuC13cZ0y7/eMFZyHLc+dM0PwT4q82GNdE8MLGCJIuGthYDv6JqdYwWlzYqHd
vAzJD71MQDH3AacTun7Dl4/eTnhvkNcZKFf0EBjn+4df3BP0iZK/3UmLq0QpPkEWqlEa+qo4vGvt
lTSoXGCAdcZUgr8wMal/cGxUFqG3cgR6kRDcS2c8gsyol5OlVzYPmw8LEr+RPaMhCDNGI5SlgeEH
bP1Em1IAuhAOTeo4YmFeSGyI/JXE5+SexLDt3egos/jVkUueCMhlScavgyaZJ/JLqNsODTYkQHe0
3b1H65mWAgJScpm1EB3gqY6iRr4jaDTCPXJNdCvld0yuTiXS8+nuLslww3Ugiy4kyHdM7iOtBqCl
Owc+ZE8FthT4/egqt9eo91mCfLpr4ENK5znFYnLjo0UzodhuaSiGkhsfNaa76z5FHRJwsU6aDS/h
PLvPOAhoMZ+M0QQzGwkHTyxweBS42imd4GGpeQlmpWP+pteCSkV42/aZ9lFTo2TuUIy0DI2gyedi
4gWKyoBFkPaw2mp5yB+aa4+EQhEYwXoEb+mj21OZckEZ69rxDDEu7Urud+EbceS7yUPsunN9I/80
pHMM1NMFA0eXUFTw0H9vHtd6l2TsQ3sfpBf3ky60oXsJcwxKCbfCafW5Is+Ynu/7BexSBpZHD/oF
3nkg5/cOuOukt1FoDgmTf5f3tSswDOPO7gYxY7KZR8vlvqz6KYPtA8K5fKtAr2Jz3In21TWvI+Dw
pT4gb3/0mawfQJGc6vakNPtXgB8+FMce+ZygG93iIBW4CECWS1Llsi03Nh655fVlDiWUBYXSe9Pi
muK/3lDOb31+PeDPTiA9DYV/InIOoElLoAKNosAmOFmcoN3Ryth4Rosgg5wNMeKKVYZOnKbkCcsT
+X9JQN+oreA/MBtI7r8AksQWdF7GadRqOmo8bB9Syw7/CwZZmsq4DukX3Wewws3ogQSvUOkHhQ7D
MqaMt3kDb8vL8cordnPZKeDEpnRFS8O1dh7YBPn1zNnxoVHRmuKPoSSfBs7pP5/pid4JJcxTdI9A
xTF5BxxXuGo1bt1VkAsVYkvDTIbgLf2deDAtwPMUDoOdHUpf67MenQyJohGQG1d1c8uO6IiQwxVi
+qzG12l+lpIaaq7PF55//3xeHzcuJn0hzEYP1IiMRyXeTQi2zUDxpF6hGpfkLDkcqLqDcc84uqyL
HtdFuxt3+incngxySjPOsuyK7r8jxf5QhUUgy82Gu4heiBq19Ujlzlj5UnV0rSUeIYiPmQNCqtaS
710f0VSd/bvIN5Fxrv68jv7uRHBOzlaJQ5/SZMeAMqsJytB+MYQjMCjxqcCxgxJEXSq6n8VlHg/m
Fcsr7WB+90wjNhwphPE+LQKF2PwBrjvCfvsOz5/lLsC4Y4CPYEx3ca3iZncA+o8xFbC3ug7jwQub
ixOsBC8NiRQ6Yb+bWUQkRcx9y/kT/kXJTQSdk3SaEbgg9ZgSmdXiW/Ll1IHNBJ9x/hT0SId3CITl
N94p8KMURZ3AIxBCZ1yBAw1qTH2l2ikFcK8MhLvHpPnl/B+rMPBMFPYZRHYHqYZ9/Y4OJDp4IiJ3
YTMqbGi7kkLzF8TVZi/55u72pnZLp0rF8ZfizK1oBwMJduAX0AkbkOqhTi02mQN9/boaETXcsH3a
wyt/Hot7FmJ02Fi38G/OQIeP2cMCcN/HW3d/7Tbw6JRoXEQIXv9EVIfVZ+CfvdnwqQqJ0n2bprnx
8AjMOyIsVvzEGF1j0FrCE3JlmEmoVv6z+iEnWXexyjva7rL0PEYBWP18JO35l2XygTbWByTxvqZN
+fTZnIVze8VZZWLYuFzfmlTzKPDsopTtaO5whj9C9JiKujXxnVvFzPncsDj62lE9FExI1t+20NTG
7ATu90ep+j4fmBS/Ls+/Y43mYPvhKUKqKCRg+Cp1sDnCX2Quv6n+M5/+gBuyn/wNu8JwXF6xcyn0
PSy+ZdO0fkQAcSHAKJ3e2nXHfuypi4UJmSmwwDEM3d3qc65h+lk2IUMbKGZ1+Dz1QYGMuSTb/S/7
fkq22KgwKMUJR1fmO8IHT4Ms0mYmiQi/PpCNecjhZk863Ac34RYrKD7ui8x8Lfryhc+UT50bFF5t
CGw3By4cdE7LJPGaRtSqG+dI2syaaAbWdJRecvaNxOsva5y2iBYr/ATp+lcMHtZe/YidgTpIVSk9
ZOcWgeLsjIrpv91bwh8iR0fp7HAGvCl8tWGsuu+75sgmLcnNpDBipgn5v3vtOPpM895z4fECoIZK
+4tg/B+SFRzA5lrbryYanV8Po3OrktFVVpkqvCJY+Tpu5rCzpW3Vdgv5+GeYH/hnjAQWDzGRumH+
W1ps/oSLpAzse4PGYg2TxPJqclGuIqocYSUosvZEJpoCHPwPk7a+iYGcw+YMeNwxXYVUsGuaK0Qn
CTSam7RW7Uc7WDzSoFHAxdi9/OvUuSQ11MSjxqEeD2s6i5WAO3ajK1LATkAFDse7Q4uh8E49azUp
gbhAc0rD0eL+aavN9oSTZOnV6UkvlDNTnQ73EQgXLsFMz9TykP7PE8SrVKEyvO/CEDXRyXB4pkf8
raEBqNgtUNbAhNis+vzXPP/QvoTTlm51p3kPvzGM2SbLx4omF9dHu+PuaQb9YTSzIQk5DQgwzj88
bCIuYnkjPuNeOwvK+ADdC/6X8Jq+TLpTa8S1wu2sQfphFdzGbh3jfR2Abq/rGmpXOtzPiV7lHsv0
aW7fKF09osZomDkE0gI5ujlDGVU7u8NVYUwFHhnnO2zd9zwt5E/uMgM3Bg2i0GN9LXQ+lWPH/cgb
FvXXhVSCP9XArSGmj1WPIuXqTXRdyZNaOOsXz15poBd1oAj1S6P2jJStnRR1+3cdnELYn0C4fVSU
YO2G5laUclolXhSTedbTYnfRckd4GFl0ufDDljuXeLTFhYDebiDMwVylxq0XFzKhjySss1n/2AAF
qC0awrxSWoF7QNmdZa37IW3UL5y52cdiPIwWW7wX0U6qSzXpxhNFfAnUDBpJPZimX1OvfxdffpPi
7ecZkYGwjgLwD6ABRxoJZw1l+3Z5CMWkd7O+ZZyV8yFqWZRwLsqlFSX9FHhnp9QKlddPu0XaYmOO
yyso5OnzjJOrt7H8VZqnUfFsL8KUst2KXtcLMKpVQgzbURM6K16cVWmN75hKbK+TGWFaAFmjeQaD
r06pKWlJjECPslwPss26JFGgARGf029ubBnKTuyUL0kHzh7ArJjC4SweYnsRO9XHV7SDbUMsNt/M
lRkcMgfbaTluJba4Y4s4PsiF/5+MXJuoc4Xtf/lp9SQSOmElJMa0ucjGK4I9ujLay2ElVFDshQss
PEGz1kPFjIoV8CHJjA4vUlm/3yVpMy02puhl7YVMv/fgaRa6jaRzQBfMRw7JICyu6TcKtXrwPW1E
rSJbp7COo4WeRAHZPyDz2O4kTZhfrkYwLf31SXmGVBzszTEKjNrw9V44NjPvfmNmQGPjgFKewp50
cwLAQHf7QzWI5r0SqG1noGt+S2QJFr2GXerMYDugKZQ5CkA/08MUDL6YnfE6DVxjv4XvVTbKjfFl
UOGP1AfKT40x3j978FitEXSNCaCim29F4YeOrsBLcsno5gEBl2KW0JnH+cjv13jzSmZ6T58HqCwU
Vw/nxLSZKhkTzwFKi2u5+8zLueFi3p1hfu7mkBut5zOwIsOt8Zd5HWLW31lJUJDldxr/1JR6HCHd
1xQKKHGH5XwFPn6nPvOKgkxzd7oyz0D2qB0Ayywjw008xp89QaT1uZxRVyXakehXHx7WZSjhpuz7
9c0Md+BFAf0RlGf+jlwF2yajYn9K64xE25ytHYFnGfXuD2LpYPNHWISGQm9pY7o1XL/mbaAo1RYE
E2LF9/6CqAvLpQsxcip9eULt5kvdFyVxVS+SqlAuhGqBQsA5OR8l29G30vKndB8jtdW3I3K5Xv4+
ME6Gf6WKbu41RugOBQKZodkelzETuotsr7vTA/oKvXJysYo9RLoIu/9T9kKiAA0g9RWkDMg5fuGC
/yHGOhzNHXpF0UgWTA8PIg90mxNNQhO538ceaQ/B3mLPtIBsjxE1uCx3TjqVtXzNCK9VW5ynmrQi
N1P3UJeK6JBUlOkv7/kICCCjtSWU0s0esXJcwY8llGbJ9XkiNvSdJ9VZjh/XgvQ5ku0i5NgV8Vwy
SG6j4aJ0TgqvuSppl8/KJPHe0No0Oa5BlragiMSvzKVzSDvUgmihVa/D83M4FsfBl82sZaHoaB87
IzN2tDGxpmCNO3hXP6FO9nYHN1PRMR8bceECxi8i6VQY2K2c3P7Nyi58cGoa7vR4rurPS7QKWjz3
21Fb9CVuIi81rVTxBB3TwXhkoY9+T7rkDIHg2ONx1GZkD/35aTolySszLzB2ADPdEFlEH/ZTll4r
nZZrRmoQDzXFewKehPYofW0AK49Cm7Q8p/2egvGI03j+kmARaQWqEDm2ioY1W1xEnz7yfti/1ok3
Dvbi5xhvA5R1Tzgo0OfEiAeV0/cqHpr4Ky5Dv0sHqlVLU41RFppGmgUvNUBKBb2oB1f4VafZE+w5
Kzspt/lqmuWdnGL9eWhpeGQRB52/8hddOLYNnJNR/8Y1gv6VU+ys5IRXVGCEVOnvOFF2AjMNMPq+
53h98LzG5z4aBs4lv2IdhBHZeYlCsReieccMcwTTf1g4snAgSz3CGDlf0alxkhOigGOxyfEksSVJ
vIlFZOagN/K9iJuORaOND2y26p3+7/n7NQ2QVhYZCgH27Jw7BLwmjtr5yInBPu370aKHQPFCNXvY
83Zyqhvx6AJTftOZD/7V+eGBUM5ZzB5j2X3m4UyDijidHXI7JwjABccy+VVztoznMnyi8u04Vhnp
5JVP9gYLIHWxIY3v389bjkTDrqUvv9y8UcKgOO/7zcxGP7YDOU7UyeU2wTJnsJ75VRqLYahx4e4S
kRfdTemU78an48uqUNcVzwYstfVIbZYipIIKrL5rV6WnNjvYonQSwHdNs18QhPNqETAuhk6bm/ho
B50MqclMigM+aoHLk/2IW7xnz1XyAEHaBrHLDuFPXFwFv/w1Jql51phsZOvTNdf7xGxpY7bgn1NQ
rcQvsKjuurkZC6b8HVzaEprWsBcQXqoWnF5NxQHNtkZ0/F8W57c18cE3RGM94AI/Hca0zeYBxco6
/QD3K6mnN317JSWOKKrxZgRVKhrXaupjT6rnkKoQJjvZ69w3Kvpi4Xm4xR8LckW0YnUZdrIlNu6Q
hu6OJkRPY26k+LZ/7+7r7+6dgEE5yluESY9rsvst98WTXQwCDEk8VIcNYYmKfqdgWsFEI9yCuoPT
sHjCG6QEWsqjrIqbPNHoZ3JjE7y2ehGTT/H1ZC6+OAQ51+art2GmRWwl0UVGGh9iufqbyJLrulLs
2w2ps5MVV4OaVgWEGFbg1FdYcncKGTd7kT/fkUwlqcipmliW2MAqT9x+ScvcBhaXJ9ExAb8f6eTz
ObCdw5wPaVaF4Cv9iicaOAPFtOaJJZZqTTRWm3ZU6vpUPj4KiejA6CGr2mhM9hNPZcqbZ5nrFxqH
rZohR3K/R/ggSHc719n45ZcT/vRIDrWAUtRrUJI9P88yMv+JevvDtrN+HUqvzuPSD6sfOhlATc5d
FlmSiHHModALQSwExRSgfD4hHaF1d6BKBV8tNp6mo7bM0Uqypo9GGZbrVicG7OMrTo1hwY9/omQd
c6s8nxDmPZdLn/sr4EZ6QouRAJhir44lX+K2woCh5yu+4InQa1me7h5uwwh3bMZYb8PaLcw7YluN
Z7u0OIsF9IP9LQe68yDE7YaGO0OuFy9AE+artyFu0v1X+1xkoUApwOnl+/zXN8hoULHaRaVID+/d
1r/CVDo+wJ2uC3yGg71QezK1L+gLL6VF86Q68CZ1SirS52iKxwfaZhdel6kU/3aKSY5AOQgBZf4q
Mv+c7Dk9zovNLMIPX+F9EZn5IKxdpYBG3OAyAKoFwgpa6ZKzpPFG7ayeqlt3EWBLLq4T7MkK2sQK
YeeW69ZXlZ4MbATWlUiJB16L3tndonS70fGu2ThPkZiOW7QWD7+wwhFn+Xb149zTIATACtDEfC/f
e2eMUcm9U1ltpo+YpAFiZGBNsOQoS2jCdwwNGVDN5k0Vw4suqtwfWsBJVH81ycuxxzIRs6i6dYR1
ntp++R1liRSfjqGZiJdekY7OQ5RBmPSD2j1+xjuRvW0Pkh0PbaJzOuBWChlOonRfozr0gP4gvnWq
7PJQ9TQA977UzJhJTNETLs9D5xb7yi7LMBWUA9R2pzWUl0/VAluUDYST475kPPuzcn7fk0+tgCVq
Zgx2tdnJAo7viKjqAUgploYg4RS5GFra0JPlzYnH2+QDLKpveHL/gWCH4eD2EgZJW2D7gxo8E/cL
52iCZE+OCYZroCWRb10/ERcuiDIQhB0VzfJC2O+PQhlTKh/R3zCI2mRfEawzH+x591MQ6jS5KYSd
cTw+jm9umM7bA7GE5X3N1/M06R5IfD/pyu+CUfhOv1E7QYHB37mA9vZQ6ycDEj7PoigiOzxJQeON
JPi0cujaWXAe6qWh1gLWUapmoTxB0npaIvQaYo7PWFu/HdbHnRXVzaEwky7/Y3kCaF+HqpwAAS9n
4WAJDDzCBwLdisJfr9vvpFI5alksIBPHGaw3KweTdFwhUSerwFaRgCE1Xr9MYqOSQ99s1W4D/WIw
pHh54HjtJmXf6rzeltQGCzNw6C1IxVsDnCMr/EKEUIEMVQxuCSS8GPxqBcxobstRUK+O8qkwcZ6Z
WitgCPWn/027k7VaT8QfjQDsXgXJbxIqhJCA9jQk4c11LYoNgpWIKEP178qxc/IgeDxSbs5Daue8
QhovdQuU7yA3PnntnqfsaTQqTcczd+qMJwaR/xZY6q1GwsafmbQHySEcauBLn5eggAMCWf4nAIfu
HdJ3rdEeHvEkHGubnr5VKaRGYJPGK6by1tTCYJZxMuNHtktHwrHR2cQlhVT9IsVPpaoJE1PiKcBK
7sk/BR56B0N7eRDlktr/zFuDKfyqKis3PmH4GOjq+GTbRSbnXjDiG2EwcBE+6z8tU2DcLfWcpXnb
HSByjALikZl6fLim3aMXIxl53izU8T2El1ncK24aTRwo6D1K4HEWMUfIs8krD5u83e+JxUHrx8nT
zgaTSCyYDxpKgITNrhhg2aqyJVJeJIqMS5MG8c84Bc0BqKHoSK4PnxjzuLg/J1mZQsBK2/6t4s5H
NO3EcF7zaX57HiKv1beh60ruwwsvwba3J2gMQxS/wvJuYiGos5/R1/wXR7BHsg7aHjw7Id52+xUH
H6eNYmmhbBasneIO7MefNnZr7xjSc/OOq0gBNGxGeTV1qBcqWq1SAz+BWOtTcA3L5j6QqcK8CDay
YAJEY2EzVVdnkZQ5O3AThf0I0NWgbOBpLL0/wAbL3nBUbpmPnZcfkNi2POp01o3+bjyKs5A7Npww
U6GAOG+7Qs+nayqwgWqAGhf8NDLeSkiTVzxuJvMYTgvwoNQb7Uomb5ivskrhLNn0bYdlnO5CFl0a
4iwxE0s5d89tYuEnXM9QFfBQJpc5VkA4D/KKA5I1BdTHQa6n4xQafApxdl6jYMSGfI2G8jJUjNeB
0tPq9QooB9tlNWdzQLyQeP67BR8sCby60Vk2TqLydslY4hvp6yG6bzgSnhYJ/hSV+gcdR+XTjpc+
c0TASiFyrisanljrClc3bNGhoVzFNcANjgBMkaCJgr7FSWhk6rkA/OYJWOJSllkrqPbWy+t2NlPS
V9lzj0n+gMk8tj0k9IBTa8Ad9iHSZQPnozKjQAZA1Nmbh0iiLTAKkAZsYvyAf8SzKDGyqwbvkQMt
wg78E3aKTLiaXLKa2vLx24L0X/IFHnC5ziSaxWl5CgLR09xev09qc8jOQGyGIRxSZu7rUoPrRWuh
Tx1XnHl+QXsd87ytFgHgcEynyt5SvB9sl4803HvtHMDWCv0PU+syAxjouoebIZAlVY/ttBusWFbE
qSx4EiCxmfcTOGbqHm2y7pzZE0Rb10MXm4mF7TYvk5Cl5nXiJjCRg0L+rK+TNIPkGNEk7kdEcUTZ
lKuZPZpTDEEdIXDb0kPgx0erfbCCBZTu4Gb5NImfcKVwM5KNdKomo99mizxXPe8XhQqSm7Vi9i2o
wUA/gbtJU7HIyq4+4Z9rb96V4YrKKrBi/j46QP70PI5XzIt1aK3YFTqC2m+PjmeuAHp5uEvGAYSo
LoILcKgZkOlZHBS4p06ZT5nsoXNPR2fiD7edxKcg2njTGjlSPIXNKvdncqq66uytEk/5v8a2PxHt
Tyyox8yvp7lOvyCqrCXVZBom8ukQRYA/z3pOxiuL6ygtBZvPMhA6EZa1SUEje9NHX66f1Sb0Tu0K
Nz3pASg9MJC0qDIkMOzNdbMLW5lXlx8OOXImRxYNWY8hxeCmLGw+OdV7A9kRICIejkeZD31mmmld
oUq8oXTEHEuGc7tNdX1wEV9G40p8sGQ4Tu2gBnYWWoBtEI/6OUwS098F/o2OoPSw+dOjglb9Itja
nKG+mnOxKeJrda2V5I3bo9B3Wcl/ZpHCGaaaXY2iu0IbKTvXhmfx40CwY+QufpiBJ60qVFL2caBY
70Opm0Dauqc4J2P+WZRG51K0lKlpO1EQlpS7Sul7369cByNbVUjR30IRQMqhNN7YoyMvTX3Hug61
UbSPM5RlUrCGQdBQ2IjxuFFeaDclLwwbuyCKyE8ykMTGWWdMPXjMLYOy8nF8WKQHchCnkbFE/hFe
d/tEQUGezTc94o/E48AeKmYQQ3s43XrqHD7G+smhao8ueSCfVhzMCF+jF8QdaZ646kUIekFBI+du
6H5LsxfHI/IFqDWLedV/9jYfmvKcDJWcedGxXTA0J2kiwGIb1qf3RHcN/r2ehwxzhA9vc8VGDy2k
JEZyvUA5C8Ams6bSBNr4PIF06BGIMOpRl/gd2PnkwHHzMXdQcdu3+pmvH5XhY+dE3vU8dk7gVu3r
ahuqRjJu9LSpMPoaWvzWLMuy8N0hbeH3xrhJZCCbN9NfX6t4Genb5mFmJU77jHRa/HC+myPZn2qK
R25QjOTO2TfFt0SYFR6XxB9dqd/x63Vm96nw76GLgHPh/Er5Crp0b05uNXRJq6p+YCdmPD1dU/+S
iMDV5LKjyDUJUV90OcENkBr4fJzWetwWAjLAKEbFI65OZIK6ImXZY4hJaie3JaR9YQkOyCWL5U2E
VCnyGorNMlqk6/uVQKyjvdLO6Ke88us6BaZW3zGP5M4DPpq3JKzXWfHO4do1ysHEpPVutNH6nD9y
Rv0whp78HaqN0COXMAozi72rh4mT8nbPmzoPo+H0N8K6/NH7JLDk/cJYx95zyD2kXgvUd1P0AkFP
eXIrbmjyGu8ReIuSFRV84q2qjtCd8mzmvITl4bwKoTXXfolWpYa+u6yNGKXsD28xvoBbScWCFWod
qvzhGmIfhXls8W0R1xYY/N+WtYmsqCWMhvx8qq2+z7UJy4oURlRlkoKTu4J/f8yKIM9y0ai4aTgO
N5vn8tM2vsbDo8EfQZ+VGogvW8GsymoXaA6QZ9ALV9WT44CBKdG59Hijy/wxp7EbcaSLVns4mcW7
y0ty/5uZaGuhp5PlgAc22UuGNOATybK6YJHcTmxAHQFy6GwPbgrVw/4r6L2i1U4t7DO8OqJaAD4X
CnsYlsU8AtNAntlgrCQwWKRyNAzH95IFN7bPdN9rhqzgYv+TyX31a6GbC/3VM64KJzco+8GVH2Bc
gCwYxxQRSkGqICSraTidaYXU+rsbJly4vexFRRMN0o+9qfaO5owspPD3Rh5kIwY0QDdQLs/iQbpJ
jucVYIFP8lCc58MMr/BflbnsFCerlDT+XD2pBc7n7YE2TIzxXx0JioTMV9X/
`protect end_protected
|
apache-2.0
|
52749dd6789c76a0d7428cfe597d6546
| 0.954501 | 1.829762 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/uart.vhd
| 1 | 13,505 |
-------------------------------------------------------------------------------
-- UART
-- Implements a universal asynchronous receiver transmitter
-------------------------------------------------------------------------------
-- clock
-- Input clock, must match frequency value given on clock_frequency
-- generic input.
-- reset
-- Synchronous reset.
-- data_stream_in
-- Input data bus for bytes to transmit.
-- data_stream_in_stb
-- Input strobe to qualify the input data bus.
-- data_stream_in_ack
-- Output acknowledge to indicate the UART has begun sending the byte
-- provided on the data_stream_in port.
-- data_stream_out
-- Data output port for received bytes.
-- data_stream_out_stb
-- Output strobe to qualify the received byte. Will be valid for one clock
-- cycle only.
-- tx
-- Serial transmit.
-- rx
-- Serial receive
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_uart_pack.all;
entity uart is
generic (
baud : positive := 115200;
clock_frequency : positive := 50000000
);
port (
clock : in std_logic;
nreset : in std_logic;
data_stream_in : in std_logic_vector(7 downto 0);
data_stream_in_stb : in std_logic;
data_stream_in_ack : out std_logic;
data_stream_out : out std_logic_vector(7 downto 0);
data_stream_out_stb : out std_logic;
tx : out std_logic;
rx : in std_logic
);
end uart;
architecture rtl of uart is
---------------------------------------------------------------------------
-- Baud generation constants
---------------------------------------------------------------------------
constant c_tx_div : integer := clock_frequency / baud;
constant c_rx_div : integer := clock_frequency / (baud * 16);
constant c_tx_div_width : integer
:= clogb2(c_tx_div)+1;
constant c_rx_div_width : integer
:= clogb2(c_rx_div)+1;
---------------------------------------------------------------------------
-- Baud generation signals
---------------------------------------------------------------------------
signal tx_baud_counter : unsigned(c_tx_div_width - 1 downto 0)
:= (others => '0');
signal tx_baud_tick : std_logic := '0';
signal rx_baud_counter : unsigned(c_rx_div_width - 1 downto 0)
:= (others => '0');
signal rx_baud_tick : std_logic := '0';
---------------------------------------------------------------------------
-- Transmitter signals
---------------------------------------------------------------------------
type uart_tx_states is (
tx_send_start_bit,
tx_send_data,
tx_send_stop_bit
);
signal uart_tx_state : uart_tx_states := tx_send_start_bit;
signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
signal uart_tx_data : std_logic := '1';
signal uart_tx_count : unsigned(2 downto 0) := (others => '0');
signal uart_rx_data_in_ack : std_logic := '0';
---------------------------------------------------------------------------
-- Receiver signals
---------------------------------------------------------------------------
type uart_rx_states is (
rx_get_start_bit,
rx_get_data,
rx_get_stop_bit
);
signal uart_rx_state : uart_rx_states := rx_get_start_bit;
signal uart_rx_bit : std_logic := '1';
signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1');
signal uart_rx_filter : unsigned(1 downto 0) := (others => '1');
signal uart_rx_count : unsigned(2 downto 0) := (others => '0');
signal uart_rx_data_out_stb : std_logic := '0';
signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0');
signal uart_rx_bit_tick : std_logic := '0';
begin
-- Connect IO
data_stream_in_ack <= uart_rx_data_in_ack;
data_stream_out <= uart_rx_data_vec;
data_stream_out_stb <= uart_rx_data_out_stb;
tx <= uart_tx_data;
---------------------------------------------------------------------------
-- OVERSAMPLE_CLOCK_DIVIDER
-- generate an oversampled tick (baud * 16)
---------------------------------------------------------------------------
oversample_clock_divider : process (clock)
begin
if rising_edge (clock) then
if nreset = '0' then
rx_baud_counter <= (others => '0');
rx_baud_tick <= '0';
else
if rx_baud_counter = c_rx_div then
rx_baud_counter <= (others => '0');
rx_baud_tick <= '1';
else
rx_baud_counter <= rx_baud_counter + 1;
rx_baud_tick <= '0';
end if;
end if;
end if;
end process oversample_clock_divider;
---------------------------------------------------------------------------
-- RXD_SYNCHRONISE
-- Synchronise rxd to the oversampled baud
---------------------------------------------------------------------------
rxd_synchronise : process(clock)
begin
if rising_edge(clock) then
if nreset = '0' then
uart_rx_data_sr <= (others => '1');
else
if rx_baud_tick = '1' then
uart_rx_data_sr(0) <= rx;
uart_rx_data_sr(1) <= uart_rx_data_sr(0);
end if;
end if;
end if;
end process rxd_synchronise;
---------------------------------------------------------------------------
-- RXD_FILTER
-- Filter rxd with a 2 bit counter.
---------------------------------------------------------------------------
rxd_filter : process(clock)
begin
if rising_edge(clock) then
if nreset = '0' then
uart_rx_filter <= (others => '1');
uart_rx_bit <= '1';
else
if rx_baud_tick = '1' then
-- filter rxd.
if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then
uart_rx_filter <= uart_rx_filter + 1;
elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then
uart_rx_filter <= uart_rx_filter - 1;
end if;
-- set the rx bit.
if uart_rx_filter = 3 then
uart_rx_bit <= '1';
elsif uart_rx_filter = 0 then
uart_rx_bit <= '0';
end if;
end if;
end if;
end if;
end process rxd_filter;
---------------------------------------------------------------------------
-- RX_BIT_SPACING
---------------------------------------------------------------------------
rx_bit_spacing : process (clock)
begin
if rising_edge(clock) then
uart_rx_bit_tick <= '0';
if rx_baud_tick = '1' then
if uart_rx_bit_spacing = 15 then
uart_rx_bit_tick <= '1';
uart_rx_bit_spacing <= (others => '0');
else
uart_rx_bit_spacing <= uart_rx_bit_spacing + 1;
end if;
if uart_rx_state = rx_get_start_bit then
uart_rx_bit_spacing <= (others => '0');
end if;
end if;
end if;
end process rx_bit_spacing;
---------------------------------------------------------------------------
-- UART_RECEIVE_DATA
---------------------------------------------------------------------------
uart_receive_data : process(clock)
begin
if rising_edge(clock) then
if nreset = '0' then
uart_rx_state <= rx_get_start_bit;
uart_rx_data_vec <= (others => '0');
uart_rx_count <= (others => '0');
uart_rx_data_out_stb <= '0';
else
uart_rx_data_out_stb <= '0';
case uart_rx_state is
when rx_get_start_bit =>
if rx_baud_tick = '1' and uart_rx_bit = '0' then
uart_rx_state <= rx_get_data;
end if;
when rx_get_data =>
if uart_rx_bit_tick = '1' then
uart_rx_data_vec(uart_rx_data_vec'high)
<= uart_rx_bit;
uart_rx_data_vec(
uart_rx_data_vec'high-1 downto 0
) <= uart_rx_data_vec(
uart_rx_data_vec'high downto 1
);
if uart_rx_count < 7 then
uart_rx_count <= uart_rx_count + 1;
else
uart_rx_count <= (others => '0');
uart_rx_state <= rx_get_stop_bit;
end if;
end if;
when rx_get_stop_bit =>
if uart_rx_bit_tick = '1' then
if uart_rx_bit = '1' then
uart_rx_state <= rx_get_start_bit;
uart_rx_data_out_stb <= '1';
end if;
end if;
when others =>
uart_rx_state <= rx_get_start_bit;
end case;
end if;
end if;
end process uart_receive_data;
---------------------------------------------------------------------------
-- TX_CLOCK_DIVIDER
-- Generate baud ticks at the required rate based on the input clock
-- frequency and baud rate
---------------------------------------------------------------------------
tx_clock_divider : process (clock)
begin
if rising_edge (clock) then
if nreset = '0' then
tx_baud_counter <= (others => '0');
tx_baud_tick <= '0';
else
if tx_baud_counter = c_tx_div then
tx_baud_counter <= (others => '0');
tx_baud_tick <= '1';
else
tx_baud_counter <= tx_baud_counter + 1;
tx_baud_tick <= '0';
end if;
end if;
end if;
end process tx_clock_divider;
---------------------------------------------------------------------------
-- UART_SEND_DATA
-- Get data from data_stream_in and send it one bit at a time upon each
-- baud tick. Send data lsb first.
-- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1)
---------------------------------------------------------------------------
uart_send_data : process(clock)
begin
if rising_edge(clock) then
if nreset = '0' then
uart_tx_data <= '1';
uart_tx_data_vec <= (others => '0');
uart_tx_count <= (others => '0');
uart_tx_state <= tx_send_start_bit;
uart_rx_data_in_ack <= '0';
else
uart_rx_data_in_ack <= '0';
case uart_tx_state is
when tx_send_start_bit =>
if tx_baud_tick = '1' and data_stream_in_stb = '1' then
uart_tx_data <= '0';
uart_tx_state <= tx_send_data;
uart_tx_count <= (others => '0');
uart_rx_data_in_ack <= '1';
uart_tx_data_vec <= data_stream_in;
end if;
when tx_send_data =>
if tx_baud_tick = '1' then
uart_tx_data <= uart_tx_data_vec(0);
uart_tx_data_vec(
uart_tx_data_vec'high-1 downto 0
) <= uart_tx_data_vec(
uart_tx_data_vec'high downto 1
);
if uart_tx_count < 7 then
uart_tx_count <= uart_tx_count + 1;
else
uart_tx_count <= (others => '0');
uart_tx_state <= tx_send_stop_bit;
end if;
end if;
when tx_send_stop_bit =>
if tx_baud_tick = '1' then
uart_tx_data <= '1';
uart_tx_state <= tx_send_start_bit;
end if;
when others =>
uart_tx_data <= '1';
uart_tx_state <= tx_send_start_bit;
end case;
end if;
end if;
end process uart_send_data;
end rtl;
|
mit
|
33855387d43e6738922885c5952b20b3
| 0.379711 | 4.623417 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vactcapdashofkplusone.vhd
| 1 | 1,855 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vactcapdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Wofmofzero : in std_logic_vector(31 downto 0);
Wofmofone : in std_logic_vector(31 downto 0);
Wofmoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vactcapdashofkplusone;
architecture struct of k_ukf_Vactcapdashofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2,Z3,Z4 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofzero,
datab => Vsigactofkofzero,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofone,
datab => Vsigactofkofone,
result => Z2);
M3 : k_ukf_mult port map
( clock => clock,
dataa => Wofmoftwo,
datab => Vsigactofkoftwo,
result => Z3);
M4 : k_ukf_add port map
( clock => clock,
dataa => Z1,
datab => Z2,
result => Z4);
M5 : k_ukf_add port map
( clock => clock,
dataa => Z3,
datab => Z4,
result => Vactcapdashofkplusone);
end struct;
|
gpl-2.0
|
47785f52d84d44cfdf955cdbb393070d
| 0.599461 | 3.289007 | false | false | false | false |
Ttl/pic16f84
|
testbenches/cpu_core_portb_int_tb.vhd
| 1 | 2,194 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cpu_core_portb_int IS
END cpu_core_portb_int;
ARCHITECTURE behavior OF cpu_core_portb_int IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cpu_core
GENERIC( instruction_file : string);
PORT(
clk : IN std_logic;
reset : IN std_logic;
porta : INOUT std_logic_vector(4 downto 0);
portb : INOUT std_logic_vector(7 downto 0);
pc_out : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal porta : std_logic_vector(4 downto 0);
signal portb : std_logic_vector(7 downto 0);
signal pc_out : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cpu_core
Generic map(instruction_file => "scripts/instructions_portb_int.mif")
PORT MAP (
clk => clk,
reset => reset,
porta => porta,
portb => portb,
pc_out => pc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
portb <= "00000000";
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*20;
portb <= "10000000";
wait for clk_period;
portb <= "00000000";
wait for clk_period*2;
-- Check that RBI interrupt has been caught, e.g. PC is 0x04 (interrupt vector)
assert pc_out = std_logic_vector(to_unsigned(4,13)) report "RB interrupt not caught" severity failure;
wait for clk_period*3;
portb <= "00000001";
wait for clk_period*3;
-- Check that RB0/INT interrupt has been caught, e.g. PC is 0x04 (interrupt vector)
assert pc_out = std_logic_vector(to_unsigned(4,13)) report "RB0/INT interrupt not caught" severity failure;
wait;
end process;
END;
|
lgpl-3.0
|
28e8d62f4dda5efcf8fb8a0a9672ab08
| 0.604376 | 3.63245 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_cntrl_reg.vhd
| 2 | 18,476 |
-------------------------------------------------------------------------------
-- qspi_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi. This module decides the
-- behavior of the core in master/slave, CPOL/CPHA etc modes.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_SPICR_data -- Data written from the PLB bus
-- Bus2IP_SPICR_WrCE -- Write CE for control register
-- Bus2IP_SPICR_RdCE -- Read CE for control register
-- IP2Bus_SPICR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register, 10 for control reg - to match old version
C_SPI_NUM_BITS_REG : integer;
----------------------------
C_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Wr_ce_reduce_ack_gen : in std_logic;
Bus2IP_SPICR_WrCE : in std_logic;
Bus2IP_SPICR_RdCE : in std_logic;
Bus2IP_SPICR_data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- SPI module ports
SPICR_0_LOOP : out std_logic;
SPICR_1_SPE : out std_logic;
SPICR_2_MASTER_N_SLV : out std_logic;
SPICR_3_CPOL : out std_logic;
SPICR_4_CPHA : out std_logic;
SPICR_5_TXFIFO_RST : out std_logic;
SPICR_6_RXFIFO_RST : out std_logic;
SPICR_7_SS : out std_logic;
SPICR_8_TR_INHIBIT : out std_logic;
SPICR_9_LSB : out std_logic;
--------------------------
-- to Status Register
SPISR_1_LOOP_Back_Error : out std_logic;
SPISR_2_MSB_Error : out std_logic;
SPISR_3_Slave_Mode_Error : out std_logic;
-- SPISR_4_XIP_Mode_On : out std_logic;
SPISR_4_CPOL_CPHA_Error : out std_logic;
IP2Bus_SPICR_Data : out std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
Control_bit_7_8 : out std_logic_vector(0 to 1) --(7 to 8)
);
end qspi_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of qspi_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal SPICR_data_int : std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal SPICR_3_4_Reset : std_logic;
signal Control_bit_7_8_int : std_logic_vector(7 to 8);
signal temp_wr_ce : std_logic;
-----
begin
-----
----------------------------
-- Combinatorial operations
----------------------------
-- Control_Register_Data <= SPICR_data_int;
-------------------------------------------------------
SPICR_0_LOOP <= SPICR_data_int(C_SPICR_REG_WIDTH-1); -- as per the SPICR Fig 3 in DS this bit is @ 0th position
SPICR_1_SPE <= SPICR_data_int(C_SPICR_REG_WIDTH-2); -- as per the SPICR Fig 3 in DS this bit is @ 1st position
SPICR_2_MASTER_N_SLV <= SPICR_data_int(C_SPICR_REG_WIDTH-3); -- as per the SPICR Fig 3 in DS this bit is @ 2nd position
SPICR_3_CPOL <= SPICR_data_int(C_SPICR_REG_WIDTH-4); -- as per the SPICR Fig 3 in DS this bit is @ 3rd position
SPICR_4_CPHA <= SPICR_data_int(C_SPICR_REG_WIDTH-5); -- as per the SPICR Fig 3 in DS this bit is @ 4th position
SPICR_5_TXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-6); -- as per the SPICR Fig 3 in DS this bit is @ 5th position
SPICR_6_RXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-7); -- as per the SPICR Fig 3 in DS this bit is @ 6th position
SPICR_7_SS <= SPICR_data_int(C_SPICR_REG_WIDTH-8); -- as per the SPICR Fig 3 in DS this bit is @ 7th position
SPICR_8_TR_INHIBIT <= SPICR_data_int(C_SPICR_REG_WIDTH-9); -- as per the SPICR Fig 3 in DS this bit is @ 8th position
SPICR_9_LSB <= SPICR_data_int(C_SPICR_REG_WIDTH-10);-- as per the SPICR Fig 3 in DS this bit is @ 9th position
-------------------------------------------------------
SPISR_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
----------------------------
--signal ored_SPICR_7_12 : std_logic;
begin
-----
--ored_SPICR_7_12 <= or_reduce(SPICR_data_int(7 to 12));
-- C_SPICR_REG_WIDTH is of 10 bit wide
SPISR_1_LOOP_Back_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-1);-- 9th bit in present SPICR
SPISR_2_MSB_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-C_SPICR_REG_WIDTH); -- 0th LSB bit in present SPICR
SPISR_3_Slave_Mode_Error <= not SPICR_data_int(C_SPICR_REG_WIDTH-3); -- Mst_n_Slv 7th bit in control register - default is slave mode of operation
SPISR_4_CPOL_CPHA_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-5) xor -- bit 5-CPHA and 6-CPOL in present SPICR
SPICR_data_int(C_SPICR_REG_WIDTH-4);-- CPOL-CPHA = 01 or 10 in control register
end generate SPISR_DUAL_MODE_STATUS_GEN;
----------------------------------------
SPISR_NO_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 0 generate
-------------------------------
begin
-----
SPISR_1_LOOP_Back_Error <= '0';
SPISR_2_MSB_Error <= '0';
SPISR_3_Slave_Mode_Error <= '0';
SPISR_4_CPOL_CPHA_Error <= '0';
end generate SPISR_NO_DUAL_MODE_STATUS_GEN;
-------------------------------------------
SPICR_REG_RD_GENERATE: for i in 0 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
IP2Bus_SPICR_Data(i) <= SPICR_data_int(i) and Bus2IP_SPICR_RdCE;
end generate SPICR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------
-- Bus2IP Data bit mapping - 0 to 21 - NA
-- 22 23 24 25 26 27 28 29 30 31
--
-- Control Register - 0 to 22 bit mapping
-- 0 1 2 3 4 5 6 7 8 9
-- LSB TRAN MANUAL RX FIFO TX FIFO CPHA CPOL MASTER SPE LOOP
-- INHI SLAVE RST RST
-- '0' '1' '1' '0' '0' '0' '0' '0' '0' '0'
-----------------------------------------------------
-- AXI Data 31 downto 0 |
-- valid bits in AXI start from LSB i.e. 0 |
-- Bus2IP_Data 0 to 31 |
-- **** IMP Starts **** |
-- This is 1 is to 1 mapping with reverse bit order.|
-- **** IMP Ends **** |
-- Bus2IP_Data 0 1 2 3 4 5 6 7 21 22--->31 |
-- Control Bits<-------NA--------> 0---->9 |
-----------------------------------------------------
--SPICR_NO_DUAL_MODE_WR_GEN: if C_SPI_MODE = 0 generate
---------------------------------
--begin
-----
-- SPICR_data_int(0 to 12) <= (others => '0');
--end generate SPICR_NO_DUAL_MODE_WR_GEN;
----------------------------------------------
temp_wr_ce <= wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE;
-- -- SPICR_REG_0_PROCESS : Control Register Write Operation for bit 0 - LSB
-- -----------------------------
-- Behavioral Code **
SPICR_REG_0_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(0) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(0) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH);-- after 100 ps;
end if;
end if;
end process SPICR_REG_0_PROCESS;
--------------------------------
CONTROL_REG_1_2_GENERATE: for i in 1 to 2 generate
------------------------
begin
-----
-- SPICR_REG_1_2_PROCESS : Control Register Write Operation for bit 1_2 - TRAN_INHI and MANUAL_SLAVE
-----------------------------
SPICR_REG_1_2_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '1';
elsif((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_1_2_PROCESS;
----------------------------------
end generate CONTROL_REG_1_2_GENERATE;
--------------------------------------
-- the below reset signal is needed to de-assert the Tx/Rx FIFO reset signals.
SPICR_3_4_Reset <= (not Bus2IP_SPICR_WrCE) or Soft_Reset_op;
-- CONTROL_REG_3_4_GENERATE : Control Register Write Operation for bit 3_4 - Receive FIFO Reset and Transmit FIFO Reset
-----------------------------
CONTROL_REG_3_4_GENERATE: for i in 3 to 4 generate
-----
begin
-----
SPICR_REG_3_4_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (SPICR_3_4_Reset = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_3_4_PROCESS;
----------------------------------
end generate CONTROL_REG_3_4_GENERATE;
--------------------------------------
-- CONTROL_REG_5_9_GENERATE : Control Register Write Operation for bit 5:9 - CPHA, CPOL, MASTER, SPE, LOOP
-----------------------------
CONTROL_REG_5_9_GENERATE: for i in 5 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
SPICR_REG_5_9_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_5_9_PROCESS;
----------------------------------
end generate CONTROL_REG_5_9_GENERATE;
--------------------------------------
--
-- SPICR_REG_78_GENERATE: This logic is newly added to register _T signals
-- ------------------------ in IOB. This logic simplifies the register method
-- for _T in IOB, without affecting functionality.
SPICR_REG_78_GENERATE: for i in 7 to 8 generate
-----
begin
-----
SPI_TRISTATE_CONTROL_I: component FDRE
port map
(
Q => Control_bit_7_8_int(i) ,-- out:
C => Bus2IP_Clk ,--: in
CE => Bus2IP_SPICR_WrCE ,--: in
R => Soft_Reset_op ,-- : in
D => Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i) --: in
);
end generate SPICR_REG_78_GENERATE;
-----------------------------------
Control_bit_7_8 <= Control_bit_7_8_int;
---------------------------------------
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
307143ed2bc7200013fb5c2c38126e3f
| 0.450693 | 4.283793 | false | false | false | false |
tmeissner/cryptocores
|
cbctdes/rtl/vhdl/des_pkg.vhd
| 1 | 15,986 |
-- ======================================================================
-- DES encryption/decryption
-- package file with functions
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
-- Revision 1.0 2007/02/04
-- Initial release
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
PACKAGE des_pkg IS
FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector;
FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector;
TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63;
constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7,
56, 48, 40, 32, 24, 16, 8, 0,
58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6);
constant ipn_table : ip_matrix := (39, 7, 47, 15, 55, 23, 63, 31,
38, 6, 46, 14, 54, 22, 62, 30,
37, 5, 45, 13, 53, 21, 61, 29,
36, 4, 44, 12, 52, 20, 60, 28,
35, 3, 43, 11, 51, 19, 59, 27,
34, 2, 42, 10, 50, 18, 58, 26,
33, 1, 41, 9, 49, 17, 57, 25,
32, 0, 40, 8, 48, 16, 56, 24);
TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31;
constant e_table : e_matrix := (31, 0, 1, 2, 3, 4,
3, 4, 5, 6, 7, 8,
7, 8, 9, 10, 11, 12,
11, 12, 13, 14, 15, 16,
15, 16, 17, 18, 19, 20,
19, 20, 21, 22, 23, 24,
23, 24, 25, 26, 27, 28,
27, 28, 29, 30, 31, 0);
TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15;
constant s1_table : s_matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7),
1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8),
2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0),
3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13));
constant s2_table : s_matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10),
1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5),
2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15),
3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9));
constant s3_table : s_matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8),
1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1),
2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7),
3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12));
constant s4_table : s_matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15),
1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9),
2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4),
3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14));
constant s5_table : s_matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9),
1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6),
2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14),
3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3));
constant s6_table : s_matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11),
1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8),
2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6),
3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13));
constant s7_table : s_matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1),
1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6),
2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2),
3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12));
constant s8_table : s_matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7),
1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2),
2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8),
3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11));
type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63;
constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16, 8,
0, 57, 49, 41, 33, 25, 17,
9, 1, 58, 50, 42, 34, 26,
18, 10, 2, 59, 51, 43, 35);
constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
6, 61, 53, 45, 37, 29, 21,
13, 5, 60, 52, 44, 36, 28,
20, 12, 4, 27, 19, 11, 3);
type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31;
constant p_table : p_matrix := (15, 6, 19, 20,
28, 11, 27, 16,
0, 14, 22, 25,
4, 17, 30, 9,
1, 7, 23, 13,
31, 26, 2, 8,
18, 12, 29, 5,
21, 10, 3, 24);
type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63;
constant pc2_table : pc2_matrix := (13, 16, 10, 23, 0, 4,
2, 27, 14, 5, 20, 9,
22, 18, 11, 3, 25, 7,
15, 6, 26, 19, 12, 1,
40, 51, 30, 36, 46, 54,
29, 39, 50, 44, 32, 47,
43, 48, 38, 55, 33, 52,
45, 41, 49, 35, 28, 31);
END PACKAGE des_pkg;
PACKAGE BODY des_pkg IS
FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 63);
BEGIN
FOR index IN 0 TO 63 LOOP
result( index ) := input_vector( ip_table( index ) );
END LOOP;
RETURN result;
END FUNCTION ip;
FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 63);
BEGIN
FOR index IN 0 TO 63 LOOP
result( index ) := input_vector( ipn_table( index ) );
END LOOP;
RETURN result;
END FUNCTION ipn;
FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 47);
BEGIN
FOR index IN 0 TO 47 LOOP
result( index ) := input_vector( e_table( index ) );
END LOOP;
RETURN result;
END FUNCTION e;
FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s1;
FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s2;
FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s3;
FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s4;
FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s5;
FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s6;
FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s7;
FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
VARIABLE int : std_logic_vector(0 TO 1);
VARIABLE i : integer RANGE 0 TO 3;
VARIABLE j : integer RANGE 0 TO 15;
VARIABLE result : std_logic_vector(0 TO 3);
BEGIN
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 TO 4) ) );
result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) );
RETURN result;
END FUNCTION s8;
FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 31);
BEGIN
FOR index IN 0 TO 31 LOOP
result( index ) := input_vector( p_table( index ) );
END LOOP;
RETURN result;
END FUNCTION p;
FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS
VARIABLE intern : std_logic_vector(0 TO 47);
VARIABLE result : std_logic_vector(0 TO 31);
BEGIN
intern := e( input_r ) xor input_key;
result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) &
s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) );
RETURN result;
END FUNCTION f;
FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 27);
BEGIN
FOR index IN 0 TO 27 LOOP
result( index ) := input_vector( pc1c_table( index ) );
END LOOP;
RETURN result;
END FUNCTION pc1_c;
FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 27);
BEGIN
FOR index IN 0 TO 27 LOOP
result( index ) := input_vector( pc1d_table( index ) );
END LOOP;
RETURN result;
END FUNCTION pc1_d;
FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(0 TO 47);
BEGIN
FOR index IN 0 TO 47 LOOP
result( index ) := input_vector( pc2_table( index ) );
END LOOP;
RETURN result;
END FUNCTION pc2;
END PACKAGE BODY des_pkg;
|
gpl-2.0
|
fd8fce6a6248348a00f77dd85039fb91
| 0.491743 | 3.064213 | false | false | false | false |
Apollinaire/GameOfLife_FPGA
|
sources/ClockManager.vhd
| 1 | 1,165 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10.02.2017 11:21:03
-- Design Name:
-- Module Name: ClockManager - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ClockManager is
Port ( CLK : in STD_LOGIC;
CLK_btn_fast : in STD_LOGIC;
CLK_btn_once : in STD_LOGIC;
V_sync : in STD_LOGIC;
CLK_gol : out STD_LOGIC);
end ClockManager;
architecture Behavioral of ClockManager is
signal A : integer := 0;
begin
process(V_sync, CLK_btn_fast, CLK_btn_once, CLK, A)
begin
if V_sync = '1' then
if CLK_btn_fast = '1' then
A <= A + 1;
-- elsif CLK_btn_once = '1' then
-- A<=11;
end if;
elsif CLK'event and CLK = '1' then
if A>10 then
A <= 0;
CLK_gol <= '1';
else
CLK_gol <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
c7ff6ce0efceb955c4faa408143db705
| 0.506438 | 3.446746 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/Gscale.vhd
| 1 | 5,025 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 01/30/2017 10:24:00 AM
-- Design Name: Gray Scale Filter 2
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter creates a gray scale version of the image. It takes the
-- sum of the pixel values and divides the value by 3.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Grayscale architecture design
architecture Behavioral of Video_Box is
--Define a Divide function for use in the grayscale
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
--Variables used in the divide algorithm
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
--Begin Divide Algorithm
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
--End Divide
--Grayscale signal (contains the average value of all three pixels)
signal grayscale : std_logic_vector(7 downto 0);
--Const of a three
signal three_const : unsigned(7 downto 0):= "00000011";
--Sum signal
signal sum : unsigned(9 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--Add the value of Red, Green, and Blue together
sum <= unsigned("00" & RGB_IN_reg(23 downto 16)) + unsigned("00" & RGB_IN_reg(15 downto 8)) + unsigned("00" & RGB_IN_reg(7 downto 0));
--Divide by 3 to get the average RGB value for the pixel
grayscale <= std_logic_vector(divide ( sum, three_const )(6 downto 0))&'0';
--Concatenate the grayscale average together and place on the RGB output
USER_LOGIC <= grayscale & grayscale & grayscale;
--Pass all the other signals through the region
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
end Behavioral;
--End Grayscale
|
bsd-3-clause
|
9a75841d694772fc09017f9d3592497a
| 0.620896 | 3.22322 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd
| 4 | 11,867 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
bsd-3-clause
|
8dcec0c208d8661f817d283ca3019f5a
| 0.447965 | 4.459602 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_command/synth/fifo_generator_command.vhd
| 1 | 38,970 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_command IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_command;
ARCHITECTURE fifo_generator_command_arch OF fifo_generator_command IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_command_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_command_arch: ARCHITECTURE IS "fifo_generator_v13_0_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_command_arch : ARCHITECTURE IS "fifo_generator_command,fifo_generator_v13_0_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_command_arch: ARCHITECTURE IS "fifo_generator_command,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=24,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=24,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 24,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 24,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_command_arch;
|
bsd-3-clause
|
3ed9c3173fbfa5c9be0e2441c7c2876e
| 0.629356 | 2.922604 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/xip_cntrl_reg.vhd
| 2 | 9,960 |
-------------------------------------------------------------------------------
-- xip_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi in XIP mode.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
--library unisim;
-- use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_XIP_SPICR_REG_WIDTH -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_XIPCR_data -- Data written from the PLB bus
-- Bus2IP_XIPCR_WrCE -- Write CE for control register
-- Bus2IP_XIPCR_RdCE -- Read CE for control register
-- IP2Bus_XIPCR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register,10 for control reg - 8 for cmd + 2 CPOL/CPHA
C_XIP_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_XIPCR_WrCE : in std_logic;
Bus2IP_XIPCR_RdCE : in std_logic;
Bus2IP_XIPCR_data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
ip2Bus_RdAck_core : in std_logic;
ip2Bus_WrAck_core : in std_logic;
XIPCR_1_CPOL : out std_logic;
XIPCR_0_CPHA : out std_logic;
--------------------------
IP2Bus_XIPCR_Data : out std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
--------------------------
TO_XIPSR_CPHA_CPOL_ERR : out std_logic
);
end xip_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of xip_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPCR_data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
-----
begin
-----
---------------------------------------
XIPCR_CPHA_CPOL_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH))
<= "00";
elsif(ip2Bus_WrAck_core = '1') and (Bus2IP_XIPCR_WrCE = '1')then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (0))
<= Bus2IP_XIPCR_data
((C_XIP_SPICR_REG_WIDTH-1) downto (0));
end if;
end if;
end process XIPCR_CPHA_CPOL_STORE_P;
------------------------------------
XIPCR_1_CPOL <= XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1);
XIPCR_0_CPHA <= XIPCR_data_int(0);
XIPCR_REG_RD_GENERATE: for i in C_XIP_SPICR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPCR_Data(i) <= XIPCR_data_int(i) and Bus2IP_XIPCR_RdCE;
end generate XIPCR_REG_RD_GENERATE;
-----------------------------------
TO_XIPSR_CPHA_CPOL_ERR <= (XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1)) xor
(XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH));
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
9ef3a7aa2564b893c7f3ac5ab4a2345f
| 0.433735 | 4.851437 | false | false | false | false |
makestuff/vga_test
|
vhdl/top_level.vhdl
| 1 | 3,305 |
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port (
sysClk_in : in std_logic;
hSync_out : out std_logic;
vSync_out : out std_logic;
rgb_out : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of top_level is
signal locked : std_logic; -- goes high when pixClk DLL locks
signal reset : std_logic; -- remains high until pixClk DLL locks
signal pixClk : std_logic := '0'; -- 25MHz pixel clock
signal pixX : unsigned(9 downto 0); -- current pixel's X coordinate
signal pixY : unsigned(9 downto 0); -- current pixel's Y coordinate
constant HRES : integer := 640; -- horizontal resolution
constant VRES : integer := 480; -- vertical resolution
--constant VRES : integer := 512;
begin
-- Instantiate VGA sync circuit, driven with the 25MHz pixel clock
vga_sync: entity work.vga_sync
generic map (
-- Horizontal parameters (numbers are pixClk counts)
HORIZ_DISP => HRES,
HORIZ_FP => 16,
HORIZ_RT => 96,
HORIZ_BP => 48,
-- Vertical parameters (in line counts)
VERT_DISP => VRES,
VERT_FP => 10, -- 640x480 @ 60Hz
VERT_RT => 2,
VERT_BP => 29
--VERT_FP => 45, -- 640x512 @ 50Hz
--VERT_RT => 2,
--VERT_BP => 66
)
port map(
clk_in => pixClk,
reset_in => reset,
hSync_out => hSync_out,
vSync_out => vSync_out,
pixX_out => pixX,
pixY_out => pixY
);
-- Generate the 25MHz pixel clock from the input clock
clk_gen: entity work.clk_gen_wrapper
port map(
clk_in => sysClk_in,
clk_out => pixClk,
locked_out => locked
);
-- We're in reset until the DLL locks on
reset <= not(locked);
-- Set the visible area to eight vertical colour bars
rgb_out <=
"100" when pixX >= 3*HRES/8 and pixX < 4*HRES/8 and pixY < VRES else -- 4: blue
"011" when pixX >= 2*HRES/8 and pixX < 3*HRES/8 and pixY < VRES else -- 3: yellow
"010" when pixX >= 1*HRES/8 and pixX < 2*HRES/8 and pixY < VRES else -- 2: green
"001" when pixX >= 0*HRES/8 and pixX < 1*HRES/8 and pixY < VRES else -- 1: red
"111" when pixX >= 7*HRES/8 and pixX < 8*HRES/8 and pixY < VRES else -- 8: white
"110" when pixX >= 6*HRES/8 and pixX < 7*HRES/8 and pixY < VRES else -- 7: cyan
"101" when pixX >= 5*HRES/8 and pixX < 6*HRES/8 and pixY < VRES else -- 6: magenta
"000"; -- 5: black
end architecture;
|
gpl-3.0
|
f033223b29325c570d29f33c6e35f425
| 0.6118 | 3.285288 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_uart_pack.vhd
| 1 | 3,656 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's UART Core. Please refer to the documentation
--! in plasoc_uart.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package plasoc_uart_pack is
constant default_uart_fifo_depth : integer := 8;
constant default_uart_axi_control_offset : integer := 0;
constant default_uart_axi_control_status_in_avail_bit_loc : integer := 0;
constant default_uart_axi_control_status_out_avail_bit_loc : integer := 1;
constant default_uart_axi_in_fifo_offset : integer := 4;
constant default_uart_axi_out_fifo_offset : integer := 8;
constant default_uart_baud : positive := 9600;
constant default_uart_clock_frequency : positive := 50000000;
constant axi_resp_okay : std_logic_vector := "00";
component plasoc_uart is
generic (
fifo_depth : integer := default_uart_fifo_depth;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_control_offset : integer := default_uart_axi_control_offset;
axi_control_status_in_avail_bit_loc : integer := default_uart_axi_control_status_in_avail_bit_loc;
axi_control_status_out_avail_bit_loc : integer := default_uart_axi_control_status_out_avail_bit_loc;
axi_in_fifo_offset : integer := default_uart_axi_in_fifo_offset;
axi_out_fifo_offset : integer := default_uart_axi_out_fifo_offset;
baud : positive := default_uart_baud;
clock_frequency : positive := default_uart_clock_frequency);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
tx : out std_logic;
rx : in std_logic;
status_in_avail : out std_logic);
end component;
function clogb2(bit_depth : in integer ) return integer;
end package;
package body plasoc_uart_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
8a33a0204d183c0aa465fe4398081e63
| 0.606674 | 3.696663 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/reg_bank.vhd
| 1 | 16,195 |
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0);
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
tri_port_mem:
if memory_type = "TRI_PORT_X" generate
ram_proc: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable tri_port_ram : ram_type := (others => ZERO);
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
dual_port_mem:
if memory_type = "DUAL_PORT_" generate
ram_proc2: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable dual_port_ram1 : ram_type := (others => ZERO);
variable dual_port_ram2 : ram_type := (others => ZERO);
begin
data_out1 <= dual_port_ram1(conv_integer(addr_read1));
data_out2 <= dual_port_ram2(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --dual_port_mem
-- Option #3
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
-- From library UNISIM; use UNISIM.vcomponents.all;
xilinx_16x1d:
if memory_type = "XILINX_16X" generate
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
signal weA, weB : std_logic;
signal no_connect : std_logic_vector(127 downto 0);
begin
weA <= write_enable and not addr_write(4); --lower 16 registers
weB <= write_enable and addr_write(4); --upper 16 registers
reg_loop: for i in 0 to 31 generate
begin
--Read port 1 lower 16 registers
reg_bit1a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1A(i), -- Port B 1-bit data output
SPO => no_connect(i) -- Port A 1-bit data output
);
--Read port 1 upper 16 registers
reg_bit1b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1B(i), -- Port B 1-bit data output
SPO => no_connect(32+i) -- Port A 1-bit data output
);
--Read port 2 lower 16 registers
reg_bit2a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2A(i), -- Port B 1-bit data output
SPO => no_connect(64+i) -- Port A 1-bit data output
);
--Read port 2 upper 16 registers
reg_bit2b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2B(i), -- Port B 1-bit data output
SPO => no_connect(96+i) -- Port A 1-bit data output
);
end generate; --reg_loop
data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
end generate; --xilinx_16x1d
-- Option #4
-- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for 5-LUT Xilinx FPGAs such as Virtex-5
-- From library UNISIM; use UNISIM.vcomponents.all;
xilinx_32x1d:
if memory_type = "XILINX_32X" generate
signal no_connect : std_logic_vector(63 downto 0);
begin
reg_loop: for i in 0 to 31 generate
begin
--Read port 1
reg_bit1 : RAM32X1D
port map (
WCLK => clk, -- Port A write clock input
WE => write_enable, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
A4 => addr_write(4), -- Port A address[4] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPRA4 => addr_read1(4), -- Port B address[4] input bit
DPO => data_out1(i), -- Port B 1-bit data output
SPO => no_connect(i) -- Port A 1-bit data output
);
--Read port 2
reg_bit2 : RAM32X1D
port map (
WCLK => clk, -- Port A write clock input
WE => write_enable, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
A4 => addr_write(4), -- Port A address[4] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPRA4 => addr_read2(4), -- Port B address[4] input bit
DPO => data_out2(i), -- Port B 1-bit data output
SPO => no_connect(32+i) -- Port A 1-bit data output
);
end generate; --reg_loop
end generate; --xilinx_32x1d
-- Option #5
-- Altera LPM_RAM_DP
altera_mem:
if memory_type = "ALTERA_LPM" generate
signal clk_delayed : std_logic;
signal addr_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(31 downto 0);
signal q1 : std_logic_vector(31 downto 0);
signal q2 : std_logic_vector(31 downto 0);
begin
-- Altera dual port RAMs must have the addresses registered (sampled
-- at the rising edge). This is very unfortunate.
-- Therefore, the dual port RAM read clock must delayed so that
-- the read address signal can be sent from the mem_ctrl block.
-- This solution also delays the how fast the registers are read so the
-- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
dpram_bypass: process(clk, addr_write, reg_dest_new, write_enable)
begin
if rising_edge(clk) and write_enable = '1' then
addr_reg <= addr_write;
data_reg <= reg_dest_new;
end if;
end process; --dpram_bypass
-- Bypass dpram if reading what was just written (Altera limitation)
data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;
data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;
lpm_ram_dp_component1 : lpm_ram_dp
generic map (
LPM_WIDTH => 32,
LPM_WIDTHAD => 5,
--LPM_NUMWORDS => 0,
LPM_INDATA => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_RDADDRESS_CONTROL => "REGISTERED",
LPM_WRADDRESS_CONTROL => "REGISTERED",
LPM_FILE => "UNUSED",
LPM_TYPE => "LPM_RAM_DP",
USE_EAB => "ON",
INTENDED_DEVICE_FAMILY => "UNUSED",
RDEN_USED => "FALSE",
LPM_HINT => "UNUSED")
port map (
RDCLOCK => clk_delayed,
RDCLKEN => '1',
RDADDRESS => addr_read1,
RDEN => '1',
DATA => reg_dest_new,
WRADDRESS => addr_write,
WREN => write_enable,
WRCLOCK => clk,
WRCLKEN => '1',
Q => q1);
lpm_ram_dp_component2 : lpm_ram_dp
generic map (
LPM_WIDTH => 32,
LPM_WIDTHAD => 5,
--LPM_NUMWORDS => 0,
LPM_INDATA => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_RDADDRESS_CONTROL => "REGISTERED",
LPM_WRADDRESS_CONTROL => "REGISTERED",
LPM_FILE => "UNUSED",
LPM_TYPE => "LPM_RAM_DP",
USE_EAB => "ON",
INTENDED_DEVICE_FAMILY => "UNUSED",
RDEN_USED => "FALSE",
LPM_HINT => "UNUSED")
port map (
RDCLOCK => clk_delayed,
RDCLKEN => '1',
RDADDRESS => addr_read2,
RDEN => '1',
DATA => reg_dest_new,
WRADDRESS => addr_write,
WREN => write_enable,
WRCLOCK => clk,
WRCLKEN => '1',
Q => q2);
end generate; --altera_mem
end; --architecture ram_block
|
mit
|
00187b9da1e3a8108269b11c66076137
| 0.531275 | 3.627912 | false | false | false | false |
tmeissner/cryptocores
|
cbctdes/rtl/vhdl/tdes.vhd
| 1 | 5,085 |
-- ======================================================================
-- TDES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity tdes is
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 TO 63); -- key input
key2_i : in std_logic_vector(0 TO 63); -- key input
key3_i : in std_logic_vector(0 TO 63); -- key input
data_i : in std_logic_vector(0 TO 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
data_o : out std_logic_vector(0 TO 63); -- data output
valid_o : out std_logic; -- output data valid flag
ready_o : out std_logic
);
end entity tdes;
architecture rtl of tdes is
component des is
port (
reset_i : in std_logic;
clk_i : IN std_logic; -- clock
mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : IN std_logic_vector(0 TO 63); -- key input
data_i : IN std_logic_vector(0 TO 63); -- data input
valid_i : IN std_logic; -- input key/data valid flag
data_o : OUT std_logic_vector(0 TO 63); -- data output
valid_o : OUT std_logic -- output data valid flag
);
end component des;
signal s_ready : std_logic;
signal s_mode : std_logic;
signal s_des2_mode : std_logic;
signal s_des1_validin : std_logic := '0';
signal s_des1_validout : std_logic;
signal s_des2_validout : std_logic;
signal s_des3_validout : std_logic;
signal s_key1 : std_logic_vector(0 to 63);
signal s_key2 : std_logic_vector(0 to 63);
signal s_key3 : std_logic_vector(0 to 63);
signal s_des1_key : std_logic_vector(0 to 63);
signal s_des3_key : std_logic_vector(0 to 63);
signal s_des1_dataout : std_logic_vector(0 to 63);
signal s_des2_dataout : std_logic_vector(0 to 63);
begin
ready_o <= s_ready;
valid_o <= s_des3_validout;
s_des2_mode <= not(s_mode);
s_des1_validin <= valid_i and s_ready;
s_des1_key <= key1_i when mode_i = '0' else key3_i;
s_des3_key <= s_key3 when s_mode = '0' else s_key1;
inputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_mode <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1') then
s_mode <= mode_i;
s_key1 <= key1_i;
s_key2 <= key2_i;
s_key3 <= key3_i;
end if;
end if;
end process inputregister;
outputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_ready <= '1';
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1') then
s_ready <= '0';
end if;
if(s_des3_validout = '1') then
s_ready <= '1';
end if;
end if;
end process outputregister;
i1_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => mode_i,
key_i => s_des1_key,
data_i => data_i,
valid_i => s_des1_validin,
data_o => s_des1_dataout,
valid_o => s_des1_validout
);
i2_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_des2_mode,
key_i => s_key2,
data_i => s_des1_dataout,
valid_i => s_des1_validout,
data_o => s_des2_dataout,
valid_o => s_des2_validout
);
i3_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_mode,
key_i => s_des3_key,
data_i => s_des2_dataout,
valid_i => s_des2_validout,
data_o => data_o,
valid_o => s_des3_validout
);
end architecture rtl;
|
gpl-2.0
|
54ee5cc6246169a6c03b201260a70243
| 0.53294 | 3.259615 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0.vhd
| 1 | 10,163 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EQDqRTFU2v0Yr4ayqnCPWtZtOvmwqvkP0Xi9isxy2JtVyIKS9L7Wvrrkjz2Vu63BA55BfHAKE5x5
Pb0s5EPqQg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OifBT6nHozgZcDQWxGkfvVvQ+jUft0Pli2Dww9olhkPpIC0ivjVW/s7JR+L+P8WMJWv5lLBYUO8o
IUtJDeIGjm9xpDxku707rwzpukUbcH0v6tLSaFP/8WA0uG5uaM0OlJik1KcNpf4GnhWdWrljuLtM
/Xw/fmPusBCAjypI7W8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
q/HCqeI7pjLZP7dTRc9Wsm0ELyKVRBTbBIQceFsa7XBrwSB/Hxn+c9ZemJdK3ZQqnTgalYuqvGzT
rgezwqTc8fC0IfJykmk+kJ7Tt1HAD2DU8plht5HEfgDVlW5NYt0S3EMFjihMwfFjRhF5Y23oRq10
ipBrbE4rlQ+tx6yRDbm/BTbIycVZYZWY1+5eTN2a0ZzlBJkL/MUGtaar97hacQaH8EnTtMrB6hxe
R8qCgPnes/+Eas1kurVGcpZW7nGEIBHgz9x8A3Fu5+gXZxTz008tRVrD08TwMaArg3Y0yUxxr9FC
5GsyZ5fS8fCECjX6zWuv/hbEbAYwMw5FsbVNLw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
qUbKCxMXw/nnIulYkN5pe93HmQQ5N3ma/VsYjdHh6IzsScZTOE91XnA/FIXOznDfdlDJ7l56wCrD
OV1RIEQjOyYByz/RfMl8YpwiQzF4Adq3BP97T3g2FgZyywAaw2p+pP3NJxGHTUf1PPSaJQB52pVV
j8YlkVnGzaHwXMVAkuQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Fd3OnEDpF37ORSCftR3VqfnsY5rDUuZleCcIBB3zorEz5/eeLtCPdzFI7aHMmcin75j4X8b5NBmg
pLcIB4yDkzRxSB0GZVzH6dGQ6To8T2UW860zTu6AzG8W2MAVgJ//Q4wrelF68iPpuCeM+JSgRG20
OtFkOHqBaOeJW0uxYxh3SLZFPi+4zJHZaH2s8uz6e34hLVoCCocd3xqdV4SaH9ohsctwglEkjAws
eUFgVHofyA0obqa19+4glTSKH000l5y5Y/FBdNidKD9OaAbSu6KYQe2iKAQF+rG+I8i1ORu4ME1Q
UG+FTLWF3eQptYgGPO1l+wDJ6LNKgIdZWc712w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YqBAcMlmStICdrufAXi53kftO4qBclLx/B/0rL3TZvNv+N6RXZSOQF3NcRIeIoKDOUEsasbr3Q1F
4R9e8bPfliUoKsPERwqTQNShWSXBHMJHZl42+yT1D49+x7ALuyegtFJvE5i4MeAGXLtu5E1jdDye
MhratXvJnnhtLO6ix7Hu9jJ6pCV8hlfKB6UxVkgy1ELdJuw5K/B4ddltYde0eJnwyZE0ApH5HSc2
oIHfQAgbMIFf7h6+0OlFYVf+yYPvfwQoRFvJ/5WsLcyEIzzYs+gRLoYx0qhh+kwL4nOQk348TWpz
lKi9OSHc+sAGQLf46joESuhuInipfrkgBi+Sbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
Yatxwr91DdPkx4SMx9Ly008UMryJ68SA1mef9n6dBdtY5I2N3DvROSySe6c/Tb9jP0qW30kmesel
5Rv7Yleoj80g31yRjslJOCowGW+nlBIq12Djrfv6ktFdZU3naQlIqj0IlrhbtPe/1E1XyBmMAPx1
rpIuo06mjdq+tjqAaJv8j4uNiE7NHypfU8/0F+Zb7rvrBtr4gdLD5J0IvuaPK8+HdSrkUVxJri4b
nSDY8Cjg1Kyd+7+elBpQqo14gfte0nUcK5eyCMQ0EQVdr1xzPxtaXyC78StEqc6xQ4oGnEnQ51Tt
7irOnrmb5AOPpPy3ZiLXbAxKBzepz7U1ffxFy6Kg6yK0L8YQx7aUm3hDLp+Vw77SJNrbk8nR8kTp
NTWdkjNaqK+4qRBgaP8SEGQwBqPRcVPw6CSXnu4nobhihE0H0dmAFKE3HAmCKYpUeVUk61ClEDxP
v3cR3f0a8W7juUf4VNygGN2yAXdRR9lUzIWHf+aCkBRgh2TxVObtSpHyPJZlWaZ3RiA2GqB7ddpA
l0ubMD80HEuWBRn3he1GDx7PYYLgEqY50ITkLXGYjYghBop81WxaAdUhvjVb7jsYfNWAFeuo6+2F
X5aKGC/mq+uA39Wg7wOzTSOB49oV75ISIJP1Ys1iuR2Qmgys6KcFq+46wFis26OIVNUz7MrBfVlx
WZm2N4mTsV8cNjxBT3f+7R/a7uCkcAsQg4uWxcbTKz2IMxUi7VbaSiPdrSIcFk6putexDM0OWHpP
DCTLMnM1I5S6qFO3K3IIxlYGqk1jJc1/8Bs5PAnEkny5tgmnuJ+VYGFm77DeDCM6tDabIasSiHzk
5ijXjC3WnCFMXHIYNvkE5gR/PKO5jZ6ocL7ywGR3QLFH8XWb38gK80BLYSKUe/4t5Qh1Y05i1ohQ
AxnlmVxfykkJSGGi1x339i+QeO6qx5anz4oiq+gg/4gRFRlgoi1d55sagxLL2cCGSpa+qP898llO
BMnEPeUZXY/0Sazmzz0gEH+N6c+iOBM2VGiMSD1PIiO8DilOfDcTJZFtOCHo+4OP/tHXnFnHRY5Z
z9k4Q6YPbgw/9BBhw53U1t/oFl4ouqqdXk169b1vYPdKeBgnigFgvZF0/2iE2Fs5iVinGZdvMFBc
cytEDDvzchDPc/H1Z1QvuNIYgafuhD3/9JcWKiuf0KgMAi8AXxaxH0C0LQUcxwgiERSvrQ8JQGw6
0enS+TRCop6fObdgiXq35uqk75pUhoZ46j13I0dXr47LTMEYpRu+Fip0dg+HTiWkNh7iImlHEzgk
DrlW1NVcFB1GhhZPWcsNpc09zBWPU9aIsq9IvDvmzWiAQfrGA+d5S+5eGMjZ4RYupWLrujwuVJsf
mLbk0lAg2+3d6w8k4SG4fQrFWfysXjeP5gF+VBRYZBdrACPVINOU3PJqXNUnu3SY1c+MMotPBhnI
T4Pu0ffMubcwgn0x6co/2irnedrft27po5pdWHy59RGw0SPw53X8UeChpZCv8oTuBv60WQnT9Gt+
GBVZGC+FJfxkZd7a3t6bV+iHUTCDdKu0YbJSb3ZGy+bhJCqO3NI5/VQlXqs7J/mohM9eShRoRY2+
Ad1nUsrQDhyIqhz/rn5kqZvrWB8Dnrug38LJahVcaPe+2U8/g5y068OGwncnfM309TxzodSFEHJ7
mXDRSIeYkp4CmYgvK74xbRv/3+Alx2gPzfaeHmfCaucefmENN//681G3NA8o0i1TBi364ngGIDrn
yRQ4yGHChpI+sX7YzsWSOfm8uYqzh/yz+CRdDyAOICAgGZZ7fjg2RXfZ0qpQP7XvCh8rZERcx8wy
X0LZbPs0eTepqDPltedbb6bH37jAJv3XwPYlKlTvnVX0sQ0k3QSXTUvjmUWMuaB+hvXD22CGkKmv
5tMdrW5YkKerCt7/wJEKKzL9YOGiJcIIWsyBPpKNRoaoJzljmbClgcgtPjMYMycqgfkcI+42h4AM
F+HZ6N+Bca0z0r6ypmj/l4XqxwyUggds2p2V7f5ZkEenohSnldI6TZAvY6wX+CSbggJfYRHPampK
1AXcUDHJ4MrGA1m3hKUqVC6Qoe4/Qt8+N6WdW3kzi60eknGHEuoy/YblFAFKnBxB2I5jlj/gkPLv
+8IQvwOBfnRB4jjUEnjDaqe+dcvCzGdoAIGIl/3kdCqj3A6/1z0p9l9S11tEMSF1KCIQfhuxaq/k
kBGPUnfHsCyANgUPtTHbyc2U3meYo5bNHtsfrekWQZHC9Q/R7+Kpy3gc1V66OJLjU8ji0M2GvUyo
F8f3nDJDhdT5W9MEFBzqdgL7aISTMY71jisri+01vfrNZNecj3xtq5VD5TM+SksUy0VMVsmWMgtO
Uf29zbAu+Or8xJmxQ3QCsfF5pIem1HTLR9Y/4REWT8/TuZwpt8+k39YcSUyNNKrxMV9sa6xBrf2s
z1XAWDerH0RxLIXtmkbst+sRVp6vQhG8P/KVH4ZyMTkatzAw141syDzBwOVglWd7jb3jUxWiRFDK
wrTOMsbUfywOpvCS+vDdKTp943jMon2jHb601EAKIkQNvkbaHMFxPAhAf6YPWZMZyGkNs34950/K
miCgIHWiKjxTmFRTTTTIfzSrnPYwnPA5fGM1Vl/L+W2sLO8JzA95gI3WIqX+7TzdIB4G3Cy/1diu
YRlloXqseTLvVZwpLOqF8/0PNWqtYPGGb40c/Lof3JfZYNNrj6MYe1LOuL0UScqdkiDRTd7ISuGd
N5FQXlqFWoz8p6gAUmwykp/t0dohKuaK9iKpiRXHnMKb/KDvnhyHuM+2iDEYagq8YJEgFLeLcyAw
UbBLVwAzI7iJUsXysxfTKiprd32VjqIYxZ3CqgAQDuv0I85lGSVasN/j3/ULJN1vudJUM6XAmESZ
lWvJMdGTOSG+6YPxr28WLZMZmw6J7MznJteXdmn11H7tHY3sSYSwV1522DY447DNJ8xZ0LPMHmXb
ybz6HCalKozxkePsACAZJ+fKmhnyVr46/HdjdiVUIFdvmFPtblK9NHg4vG2kN9N06qKzMHpWOl8i
nNZZsNDhq6XArhJLln+db4o6ZbaTFWj98adsxuLyDzJEWXBmfspy7Q/b8ufCveRD2shkWbPDH0ra
9za2ryLluKSdfYDn3oRbXfapzLrJdyYVzDyLkBHrXrLsJydkVf2hm389jXr+i1nlv2OMgmdNXKjh
cALClqLv9G/TLzBTTTnoQiObeD6tjPqbkiJz65vihJk8EQ82TwAtpTzQRyKUgoWvRo5wHc90/pFt
7bxnd/EG3Pt3jZlrlqb/V2xtBiKNRG/WsaJjFy1IKyUtfPKuGl5StkhoTNK5N+WzjvPbMGzxeacP
RGzAV8gGM2l+oBOScOwXOn8m+hWq5vwa+OZGkVNUDe78gmQS//oqZshh7xf07yZHNj+SSS463pq+
OiaV9FD1BurZ2ZU3kiL7yQ+OkAAK3EKE1w6OLR/Z8u3Dv0TCenvaGyusCTEGZy5SpMijEDMoOgz9
muNJXrN9FgXX3oaiME+q/7ZjMsLy9acnp99IrZ2y9LBrOjeTLaekh08nS71koCojTzluEkxmqSnB
edSFtKeFFZ2r5bvOy12ilYnX343ZOUUyC0HquAtOHDUZO1PWxSYbz5C7yFX4NP9hrnoR2yZTYR39
H6Ea8fZ6xkBnanA6r+1VH3bDARCNTOGRMkLUN0Ia22oJzxCuP40kpoKXzG+tTYbGe1E/oRg+zOky
RdEJtCTBzfZ/OXQjKqgjJBqsbMB1ge2EQW5HfO+90ACSOtqo3tVHlFOa5HO/U6MnB4g7+uGwnr8x
qfNEhge9axXbiwHKFB49sRh6vS5tod/V2Cx6rwRw42W1CCbx2ZJehgk+P9sKihbgJi5XD2Cddd/c
+nHZluOogW0meL93iKX2PBEabnpDPwiCueU8G/uqKpWgMOJVfEYqMfQXfu+Gf8IwnwI7h4OgNaXL
HKzDcrJYwBIcsJQaWmLCz1VI8QrSscm9gXSexir+evO9ExVcUC7FrQQIg98rne1yGWlx1vG3TZ0u
ozu1ItHinR9dwCqXjzgB1CD20PovEylJPkURYr5lVEjGItmRkLtrV/ajjvGLda73rAVk6+hH+g0y
GuNGAQ7burGd+VSrp7xZv/rSarHiGzbYr/GStkrMwsKKrMwea8mzLFJDJEbHdWdGnyifajEvYnDG
uC43hprMIxBla4pUtdSnFFGs1qv9qxVwcfXV296M5wpwcLIFVplL1c19AsLe6AfAQKlmi6IjcD9u
YxfTW7G/wET78j9HF7ddDS4sTBp1K+1jTic2EBVR01/B6TYVQHwc3tVwJKt8RGMjT/2y3LS+T9/U
wKGz3MZbqxMrahlfh+L8Vd2NEm0kZH8bTOns2sqjndBt4cNPYaiW9YMuvcq1Q3cxF+edb87i2PWl
mGyrkzpVN+5h0ycgzBGRy7oPIrmdYxbJSD1FR+TtLYZ3t01P2yOKjpYd26KJLH5tuRAF0BkopsPq
a+xiZ7mmZdtGVo7VziIwOMv6e5wKq6ffTgzOUAS8nOTsiEpk/AJLwzpagazV8j9g0kC2oZYmqXXB
HilNtz5t4xUxNeIHZbWfZ+IwVO5w8qBWxEy568F8n22+6WcsiF7ysa6UpXRBxK2/9iXFlY5hKiJm
5jbQTuSUqcp4GjSxP0ANz46/EHsODUbUra3IIiJ5ugcHh9bKUY2rAFfFcNoAKl/6xVASajQwKI8c
fSKXmZqw0506YuManR8WhGSqd+SAWw6iZbrDRdtGMUoUG8ZZhb4oEDgUklAQPEfhqj/K/qBP0TMp
g+p2mpt4pwuTxkBMQigfWF9KL8gGxdGCtF7Dx20kc9xXbxNDJAQ2kUfgtKURaxUmmE2DhNLKDl4x
DA8qX0LnBxdhAdOXuLKpUvPnE1jE4m+onUytSpnE56iw1cXNyuvo1jApmtJp1LGP7hDUBJZ/Bgbc
BpZ+dWOvSsogMsPLJlCaTntQn0kxUIRYbqxLwmeKQtcwOYtsHaTeULloeMVYEmLuUS1YC1VeMQcw
5CjzPynEgR/4RGbU4MGwuzGSL6MXJqE/uNQcAVx+mAp8vZbCWCwyciUW/7h29A2vPRruUMOj0TET
AHxrB042QEX2RjxX7sHQSCKvghpfZGSGWojUWqRh9saVsacChrnPVnu2K8R6xZqjolfMqOYINTVs
D76fc91HxaWJzHTjdEiKWS3Vx2EGhJ/uHWwLCggLEW33ZsSTt7yM7kZJ6xin/xK2QmUDpj5KCC4k
1gXf2VVqZ2Q8oLJgiZyyYF6ORC1WEuddvtL/SCbC0aFwso2XUyLkYkZOdC8SaTIEp0IdbkLSNgUn
u28hyJiJgFmcdWmGmzIEBbIeyIdyYRcURlIDESr4F4xcG3Tug1N62Qb/rtN908jbu8hYSFZyQDY6
xlz31nKeMptLAqhbF9NVnnQ9zsOIZtxVxYnHbi2n1tUlpPHNm8i0yDmrwu6FQHF+7SeV23Or/CK+
dPbH/mhL1uemOWQ2j8Og5v1DiJR2g6L3+dOK8WOHkMis52zsxeT5NYshcVlFtLa5RcAZiAOfCC1t
SlbirGT3XubAg2CYtVIaG0efdVxCpjaRg2CUmUSQC8LGWxEtetTm5Q0qiMFWRy90a2dExh6E9ZQL
sKOnREnetiiVFhP7zBUhLXAXwOApon7HGTSC/9+ZLUeO6W7tkzXmIR1iPkDmwMMWqKFC9Sr54Tyy
BelKZWNJPilvjLfDXSvjZLTAP5muWWg1YpUd/05fw1hKHNJsGDwaydC8eiIn5lw9EaWUm0CNf+iP
TplZZC+Dj2V+1LLKTnOETJIUNOwMkWFIZc+px+8crFfq94qlT9M2bsv9bqLuAtW/ywijZA/0NP5i
rIxZn+tzVmSJUoFhLcYELPFvGNpzk2/aUZCHRE+nHmv7e9OOcxr8phRqrjh5biz5sWgwRjvREQKN
u53J4t8GwGiPwor2YrrR1rqX+Oa288gtfXNMM4VBgcqmUlMya3sxBBRlusgUF3WEeW3HRNQXZW8Y
EY0XcDGz6f8XKY+nSPh4qkLhKn+COlEif2Qz454fMLwfNUYBUfL5l/iP/AWi/OqX7TSN7tFTJOR5
4+4BC9BIv+/RUniBAV/MqLYUEHq56TIKYk0Zjg2GZicRJvZDMwPwSp7iyuUtMBWIjLP1ghoGv914
J5D/P3yOGN7ZyEeITlPF7XyN0+GpjD6HZQazo6XVtMe143YHWsM1rI7K2QiPjfoFZxJvATRjGmTQ
9b8Q80wBWWVCZ9OgpvVv3oO5xGtisenC0RPleSQ6JnXiIe6zQabzL64uW8xBxgcd7bXNpaemov8x
VhJloEPTlqP1ZOYr0/8L87Pk0kCHUGDbqLBSMZp3g3AOp31hFyErF3HpHAyphXAjVjl5rV23A9q1
2doGrZVM27CKX8YMidFtUjlatgkCj9etvy+Gwgloz2yGi2T34IAFA9f7mEOJj8d01AEWhmizlVnI
uEbC6+HgoXLKCNJtC5VKbGbkznh5mdE8U+5rGh/Hylr/BdfX9+P4URqh6Kn9pHjmT98NKfY99FpJ
IMH6Xh2MQBBx8fdLdGWMw7/vQsX+nLByIQLT+qF/vCS6r7dlhU44z/nYvDbWzzBxb4LiaS7ASIXx
Rw7lfX8EcXERz179lijTHIUbLtFRtKiEO6oIk9olE7Ul5Ll1ntP6Esd/7HELUL2NDgC/bT7P52VS
R5Ue4Ne3HFpTyv3w0LnvMagr+bBZ4v4pl7laq7/4oUUhQfzdirCPSIf0eE0MeEYw/Bv93Zdnkx8t
G7a4hCBj+zw/Mio0p7owozMOJpoO8veARKsEcQAGbbIczl1V2yQUqch2q7BNsqxzSs2suUPJAPy5
fer1xGp7Oo77ttZbJZE2iOksEGKNv9NSRM50yo2A4zOY8WE4Y7wiEhCT6RbpuFLjSBTycN+AHC/Z
lqXVHu+akeVmXPt6A6or+p6B2hOUmdjB9yJFgTBeh5fbe8qluysP5Drx7FNudSv5NKneN2OzHP4K
S0Frh4+lFJoNwaDB8rhq9RUZEEwSya/8e/WqSnCgF5f3pBjhnl23+/C8qvwdppdcbCuNNmz0EtOw
2TZQw80AS0Ms6vclUpyiUkNQqDV2B+HK1gWpL0JjHXbtrMlgCBFFVVsVo4kaQfq1tjfZf2XV20Hw
7Bdee9rxSbXQMzrJbfrHKg+IM2BzX+OWfMQsMh4Gjd16eQ==
`protect end_protected
|
apache-2.0
|
f395574361e55dc26c1264fb3e41a8f7
| 0.91843 | 1.925175 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Pofkplusone.vhd
| 1 | 1,393 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Pofkplusone is
port (
clock : in std_logic;
Kofkplusone : in std_logic_vector(31 downto 0);
PofVrefofVref : in std_logic_vector(31 downto 0);
Pdashofkplusone : in std_logic_vector(31 downto 0);
Pofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Pofkplusone;
architecture struct of k_ukf_Pofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => Kofkplusone,
datab => Kofkplusone,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => Z1,
datab => PofVrefofVref,
result => Z2);
M3 : k_ukf_sub port map
( clock => clock,
dataa => Pdashofkplusone,
datab => Z2,
result => Pofkplusone);
end struct;
|
gpl-2.0
|
ba05d695cc53fa6fbb77efa3ac0d2ad7
| 0.596554 | 3.15873 | false | false | false | false |
tmeissner/cryptocores
|
cbctdes/rtl/vhdl/des.vhd
| 1 | 13,401 |
-- ======================================================================
-- DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
USE work.des_pkg.ALL;
ENTITY des IS
PORT (
reset_i : in std_logic; -- async reset
clk_i : IN std_logic; -- clock
mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : IN std_logic_vector(0 TO 63); -- key input
data_i : IN std_logic_vector(0 TO 63); -- data input
valid_i : IN std_logic; -- input key/data valid flag
data_o : OUT std_logic_vector(0 TO 63); -- data output
valid_o : OUT std_logic -- output data valid flag
);
END ENTITY des;
ARCHITECTURE rtl OF des IS
BEGIN
crypt : PROCESS ( clk_i ) IS
-- variables for key calculation
VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0');
VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0');
-- key variables
VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0');
VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0');
-- variables for left & right data blocks
VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0');
VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0');
-- variables for mode & valid shift registers
VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0');
VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0');
BEGIN
if(reset_i = '0') then
data_o <= (others => '0');
valid_o <= '0';
elsif rising_edge( clk_i ) THEN
-- shift registers
valid(1 TO 17) := valid(0 TO 16);
valid(0) := valid_i;
mode(1 TO 16) := mode(0 TO 15);
mode(0) := mode_i;
-- output stage
valid_o <= valid(17);
data_o <= ipn( ( r16 & l16 ) );
-- 16. stage
IF mode(16) = '0' THEN
c16 := c15(1 TO 27) & c15(0);
d16 := d15(1 TO 27) & d15(0);
ELSE
c16 := c15(27) & c15(0 TO 26);
d16 := d15(27) & d15(0 TO 26);
END IF;
key16 := pc2( ( c16 & d16 ) );
l16 := r15;
r16 := l15 xor ( f( r15, key16 ) );
-- 15. stage
IF mode(15) = '0' THEN
c15 := c14(2 TO 27) & c14(0 TO 1);
d15 := d14(2 TO 27) & d14(0 TO 1);
ELSE
c15 := c14(26 TO 27) & c14(0 TO 25);
d15 := d14(26 TO 27) & d14(0 TO 25);
END IF;
key15 := pc2( ( c15 & d15 ) );
l15 := r14;
r15 := l14 xor ( f( r14, key15 ) );
-- 14. stage
IF mode(14) = '0' THEN
c14 := c13(2 TO 27) & c13(0 TO 1);
d14 := d13(2 TO 27) & d13(0 TO 1);
ELSE
c14 := c13(26 TO 27) & c13(0 TO 25);
d14 := d13(26 TO 27) & d13(0 TO 25);
END IF;
key14 := pc2( ( c14 & d14 ) );
l14 := r13;
r14 := l13 xor ( f( r13, key14 ) );
-- 13. stage
IF mode(13) = '0' THEN
c13 := c12(2 TO 27) & c12(0 TO 1);
d13 := d12(2 TO 27) & d12(0 TO 1);
ELSE
c13 := c12(26 TO 27) & c12(0 TO 25);
d13 := d12(26 TO 27) & d12(0 TO 25);
END IF;
key13 := pc2( ( c13 & d13 ) );
l13 := r12;
r13 := l12 xor ( f( r12, key13 ) );
-- 12. stage
IF mode(12) = '0' THEN
c12 := c11(2 TO 27) & c11(0 TO 1);
d12 := d11(2 TO 27) & d11(0 TO 1);
ELSE
c12 := c11(26 TO 27) & c11(0 TO 25);
d12 := d11(26 TO 27) & d11(0 TO 25);
END IF;
key12 := pc2( ( c12 & d12 ) );
l12 := r11;
r12 := l11 xor ( f( r11, key12 ) );
-- 11. stage
IF mode(11) = '0' THEN
c11 := c10(2 TO 27) & c10(0 TO 1);
d11 := d10(2 TO 27) & d10(0 TO 1);
ELSE
c11 := c10(26 TO 27) & c10(0 TO 25);
d11 := d10(26 TO 27) & d10(0 TO 25);
END IF;
key11 := pc2( ( c11 & d11 ) );
l11 := r10;
r11 := l10 xor ( f( r10, key11 ) );
-- 10. stage
IF mode(10) = '0' THEN
c10 := c9(2 TO 27) & c9(0 TO 1);
d10 := d9(2 TO 27) & d9(0 TO 1);
ELSE
c10 := c9(26 TO 27) & c9(0 TO 25);
d10 := d9(26 TO 27) & d9(0 TO 25);
END IF;
key10 := pc2( ( c10 & d10 ) );
l10 := r9;
r10 := l9 xor ( f( r9, key10 ) );
-- 9. stage
IF mode(9) = '0' THEN
c9 := c8(1 TO 27) & c8(0);
d9 := d8(1 TO 27) & d8(0);
ELSE
c9 := c8(27) & c8(0 TO 26);
d9 := d8(27) & d8(0 TO 26);
END IF;
key9 := pc2( ( c9 & d9 ) );
l9 := r8;
r9 := l8 xor ( f( r8, key9 ) );
-- 8. stage
IF mode(8) = '0' THEN
c8 := c7(2 TO 27) & c7(0 TO 1);
d8 := d7(2 TO 27) & d7(0 TO 1);
ELSE
c8 := c7(26 TO 27) & c7(0 TO 25);
d8 := d7(26 TO 27) & d7(0 TO 25);
END IF;
key8 := pc2( ( c8 & d8 ) );
l8 := r7;
r8 := l7 xor ( f( r7, key8 ) );
-- 7. stage
IF mode(7) = '0' THEN
c7 := c6(2 TO 27) & c6(0 TO 1);
d7 := d6(2 TO 27) & d6(0 TO 1);
ELSE
c7 := c6(26 TO 27) & c6(0 TO 25);
d7 := d6(26 TO 27) & d6(0 TO 25);
END IF;
key7 := pc2( ( c7 & d7 ) );
l7 := r6;
r7 := l6 xor ( f( r6, key7 ) );
-- 6. stage
IF mode(6) = '0' THEN
c6 := c5(2 TO 27) & c5(0 TO 1);
d6 := d5(2 TO 27) & d5(0 TO 1);
ELSE
c6 := c5(26 TO 27) & c5(0 TO 25);
d6 := d5(26 TO 27) & d5(0 TO 25);
END IF;
key6 := pc2( ( c6 & d6 ) );
l6 := r5;
r6 := l5 xor ( f( r5, key6 ) );
-- 5. stage
IF mode(5) = '0' THEN
c5 := c4(2 TO 27) & c4(0 TO 1);
d5 := d4(2 TO 27) & d4(0 TO 1);
ELSE
c5 := c4(26 TO 27) & c4(0 TO 25);
d5 := d4(26 TO 27) & d4(0 TO 25);
END IF;
key5 := pc2( ( c5 & d5 ) );
l5 := r4;
r5 := l4 xor ( f( r4, key5 ) );
-- 4. stage
IF mode(4) = '0' THEN
c4 := c3(2 TO 27) & c3(0 TO 1);
d4 := d3(2 TO 27) & d3(0 TO 1);
ELSE
c4 := c3(26 TO 27) & c3(0 TO 25);
d4 := d3(26 TO 27) & d3(0 TO 25);
END IF;
key4 := pc2( ( c4 & d4 ) );
l4 := r3;
r4 := l3 xor ( f( r3, key4 ) );
-- 3. stage
IF mode(3) = '0' THEN
c3 := c2(2 TO 27) & c2(0 TO 1);
d3 := d2(2 TO 27) & d2(0 TO 1);
ELSE
c3 := c2(26 TO 27) & c2(0 TO 25);
d3 := d2(26 TO 27) & d2(0 TO 25);
END IF;
key3 := pc2( ( c3 & d3 ) );
l3 := r2;
r3 := l2 xor ( f( r2, key3 ) );
-- 2. stage
IF mode(2) = '0' THEN
c2 := c1(1 TO 27) & c1(0);
d2 := d1(1 TO 27) & d1(0);
ELSE
c2 := c1(27) & c1(0 TO 26);
d2 := d1(27) & d1(0 TO 26);
END IF;
key2 := pc2( ( c2 & d2 ) );
l2 := r1;
r2 := l1 xor ( f( r1, key2 ) );
-- 1. stage
IF mode(1) = '0' THEN
c1 := c0(1 TO 27) & c0(0);
d1 := d0(1 TO 27) & d0(0);
ELSE
c1 := c0;
d1 := d0;
END IF;
key1 := pc2( ( c1 & d1 ) );
l1 := r0;
r1 := l0 xor ( f( r0, key1 ) );
-- input stage
l0 := ip( data_i )(0 TO 31);
r0 := ip( data_i )(32 TO 63);
c0 := pc1_c( key_i );
d0 := pc1_d( key_i );
END IF;
END PROCESS crypt;
END ARCHITECTURE rtl;
|
gpl-2.0
|
a140ca63e5fcab1752fe759a6335f38f
| 0.490337 | 2.833192 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_wrdata_cntl.vhd
| 4 | 90,840 |
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
bsd-3-clause
|
9f3d3c89fac054f32ffb37a94b8a8707
| 0.419177 | 5.084803 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Video_PR_1.0/hdl/Pixel_Counter.vhd
| 1 | 1,906 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity pixel_counter is
port(
clk : in std_logic;
hs : in std_logic;
vs : in std_logic;
vde : in std_logic;
pixel_x : out std_logic_vector(15 downto 0);
pixel_y : out std_logic_vector(15 downto 0)
);
end pixel_counter;
architecture Behavioral of pixel_counter is
signal x : unsigned(15 downto 0);
signal y : unsigned(15 downto 0);
signal hs_prev : std_logic;
signal vs_prev : std_logic;
signal hs_rising : std_logic;
signal vs_rising : std_logic;
signal visible_row : std_logic;
begin
process(clk) is
begin
if (rising_edge(clk)) then
hs_prev <= hs;
vs_prev <= vs;
if (vs_rising = '1') then
-- Clear Y count on vsync
y <= (others => '0');
elsif (hs_rising = '1') then
-- Clear X count on hsync
x <= (others => '0');
-- Clear visible row flag on hsync
visible_row <= '0';
if (visible_row = '1') then
-- Increment Y count on hsync only if a row was shown
y <= y + 1;
end if;
elsif (vde = '1') then
-- Increment the X count on visible video
x <= x + 1;
-- Raise visible row flag
visible_row <= '1';
end if;
end if;
end process;
-- Edge Detection
hs_rising <= '1' when (hs_prev = '0' and HS = '1') else '0';
vs_rising <= '1' when (vs_prev = '0' and VS = '1') else '0';
-- Pixel Output
pixel_x <= std_logic_vector(x);
pixel_y <= std_logic_vector(y);
end Behavioral;
|
bsd-3-clause
|
4545c83bca8be42c30c173038b917d87
| 0.511018 | 3.897751 | false | false | false | false |
Ttl/pic16f84
|
timer.vhd
| 1 | 2,306 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.picpkg.all;
entity timer is
Port ( clk, reset : in STD_LOGIC;
option : in STD_LOGIC_VECTOR(7 downto 0);
porta4 : in STD_LOGIC;
tmr0_overflow : out STD_LOGIC);
end timer;
architecture Behavioral of timer is
alias prescale is option(2 downto 0);
-- 1 transition on porta4 edge, 0 internal clock
alias clk_source is option(5);
-- 1 high-to-low, 0 low-to-high increment of RA4;
alias source_edge is option(4);
-- Prescaler assignment
alias psa is option(3);
signal prescaler_out : std_logic;
-- Input signal to TMR0
signal tmr_clk : std_logic;
signal porta4_delayed : std_logic;
signal porta4_rising, porta4_falling : std_logic;
begin
porta4_delay: process(clk, porta4)
begin
if rising_edge(clk) then
porta4_delayed <= porta4;
end if;
end process;
porta4_rising <= not porta4_delayed and porta4;
porta4_falling <= porta4_delayed and not porta4;
prescaler:process(clk, reset, prescale, clk_source, porta4, porta4_delayed)
variable count : unsigned(7 downto 0);
begin
if reset = '1' then
prescaler_out <= '0';
count := to_unsigned(0,8);
elsif rising_edge(clk) then
prescaler_out <= '0';
-- Rising falling edge and transition source logic
if (clk_source = '0') or
((not source_edge and porta4_rising) = '1')
or ((source_edge and porta4_falling) = '1') then
count := count + 1;
if count(to_integer(unsigned(prescale))) = '1' then
-- Overflow
count := to_unsigned(0,8);
prescaler_out <= '1';
end if;
end if;
end if;
end process;
tmr_clk <= porta4_rising when clk_source = '1' and source_edge = '0' else
porta4_falling when clk_source = '1' and source_edge = '1' else
prescaler_out when psa = '0'
else '-';
process(clk, tmr_clk, reset)
variable count : unsigned(8 downto 0);
begin
if reset = '1' then
count := to_unsigned(0,9);
elsif rising_edge(clk) then
tmr0_overflow <= count(8);
if (psa = '1' or tmr_clk = '1') then
count := count + 1;
if count(8) = '1' then
-- Overflow
count := to_unsigned(0,9);
tmr0_overflow <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
0807fbf87e4ddc97e99701835b299c2c
| 0.628794 | 3.270922 | false | false | false | false |
makestuff/dvr-connectors
|
fifo/vhdl/fifo_rtl.vhdl
| 1 | 4,248 |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of fifo is
-- Register file for storing FIFO contents
constant DEPTH_UBOUND : natural := 2**DEPTH-1;
constant WIDTH_UBOUND : natural := WIDTH-1;
type RegFileType is array(DEPTH_UBOUND downto 0) of std_logic_vector(WIDTH_UBOUND downto 0);
signal fifoData : RegFileType; -- := (others => (others => '0'));
signal fifoData_next : RegFileType;
-- Read & write pointers, with auto-wrap incremented versions
signal rdPtr : unsigned(DEPTH-1 downto 0) := (others => '0');
signal rdPtr_next : unsigned(DEPTH-1 downto 0);
signal rdPtr_inc : unsigned(DEPTH-1 downto 0);
signal wrPtr : unsigned(DEPTH-1 downto 0) := (others => '0');
signal wrPtr_next : unsigned(DEPTH-1 downto 0);
signal wrPtr_inc : unsigned(DEPTH-1 downto 0);
-- Full flag
signal isFull : std_logic := '0';
signal isFull_next : std_logic;
-- Signals to drive inputReady_out & outputValid_out
signal inputReady : std_logic;
signal outputValid : std_logic;
-- Signals that are asserted during the cycle before a write or read, respectively
signal isWriting : std_logic;
signal isReading : std_logic;
-- FIFO depth stuff
constant DEPTH_ZEROS : std_logic_vector(DEPTH-1 downto 0) := (others => '0');
constant FULL_DEPTH : std_logic_vector(DEPTH downto 0) := '1' & DEPTH_ZEROS;
constant EMPTY_DEPTH : std_logic_vector(DEPTH downto 0) := '0' & DEPTH_ZEROS;
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
fifoData <= (others => (others => '0'));
rdPtr <= (others => '0');
wrPtr <= (others => '0');
isFull <= '0';
else
fifoData <= fifoData_next;
rdPtr <= rdPtr_next;
wrPtr <= wrPtr_next;
isFull <= isFull_next;
end if;
end if;
end process;
-- Update reg file, write pointer & isFull flag
process(fifoData, wrPtr, inputData_in, isWriting)
begin
fifoData_next <= fifoData;
if ( isWriting = '1' ) then
fifoData_next(to_integer(wrPtr)) <= inputData_in;
end if;
end process;
-- The FIFO only has three outputs, inputReady_out, outputData_out and outputValid_out:
inputReady_out <= inputReady;
inputReady <=
'0' when isFull = '1' else
'1';
outputData_out <=
fifoData(to_integer(rdPtr)) when outputValid = '1'
else (others => 'X');
outputValid_out <= outputValid;
outputValid <=
'0' when rdPtr = wrPtr and isFull = '0' else
'1';
-- The isReading and isWriting signals make it easier to check whether we're in a cycle that
-- ends in a read and/or a write, respectively
isReading <=
'1' when outputValid = '1' and outputReady_in = '1' else
'0';
isWriting <=
'1' when inputValid_in = '1' and inputReady = '1' else
'0';
-- Infer pointer-increment adders:
rdPtr_inc <= rdPtr + 1;
wrPtr_inc <= wrPtr + 1;
-- Full when a write makes the two pointers coincide, without a read to balance it
isFull_next <=
'0' when isReading = '1' and rdPtr_inc /= wrPtr else
'1' when isWriting = '1' and wrPtr_inc = rdPtr else
isFull;
-- Pointer increments
rdPtr_next <=
rdPtr_inc when isReading = '1'
else rdPtr;
wrPtr_next <=
wrPtr_inc when isWriting = '1'
else wrPtr;
-- FIFO depth
depth_out <=
EMPTY_DEPTH when wrPtr = rdPtr and isFull = '0' else
FULL_DEPTH when wrPtr = rdPtr and isFull = '1' else
'0' & std_logic_vector(wrPtr - rdPtr) when wrPtr > rdPtr else
std_logic_vector(('1' & wrPtr) - ('0' & rdPtr));
end architecture;
|
gpl-3.0
|
3120d6494373635fac896bdf3792b1b6
| 0.671375 | 3.329154 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_timer_pack.vhd
| 1 | 4,062 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Timer Core. Please refer to the documentation
--! in plasoc_timer.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_timer_pack is
-- Default Interrupt Controller parameters. These values are modifiable. If these parameters are
-- modified, though, modifications will also be necessary for the corresponding header file.
constant default_timer_width : integer := 32; --! Defines the width of the timer's Trigger and Tick Value registers.
constant default_timer_axi_control_offset : integer := 0; --! For the Control register, defines the default offset from the instantiation's base address
constant default_timer_axi_control_start_bit_loc : integer := 0; --! For the Start bit, defines the bit location in the Control register.
constant default_timer_axi_control_reload_bit_loc : integer := 1; --! For the Reload bit, defines the bit location in the Control register.
constant default_timer_axi_control_ack_bit_loc : integer := 2; --! For the Ack bit, defines the bit location in the Control register.
constant default_timer_axi_control_done_bit_loc : integer := 3; --! For the Done bit, defines the bit location in the Control register.
constant default_timer_axi_trig_value_offset : integer := 4; --! For the Trigger Value register, defines the default offset from the instantiation's base address.
constant default_timer_axi_tick_value_offset : integer := 8; --! For the Tick Value register, defines the default offset from the instantiation's base address.
constant axi_resp_okay : std_logic_vector := "00";
component plasoc_timer is
generic (
timer_width : integer := default_timer_width;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_control_offset : integer := default_timer_axi_control_offset;
axi_control_start_bit_loc : integer := default_timer_axi_control_start_bit_loc;
axi_control_reload_bit_loc : integer := default_timer_axi_control_reload_bit_loc;
axi_control_ack_bit_loc : integer := default_timer_axi_control_ack_bit_loc;
axi_control_done_bit_loc : integer := default_timer_axi_control_done_bit_loc;
axi_trig_value_offset : integer := default_timer_axi_trig_value_offset;
axi_tick_value_offset : integer := default_timer_axi_tick_value_offset);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
done : out std_logic);
end component;
end;
|
mit
|
b057bc43abdf066cbb9ed269f3ccccb4
| 0.608567 | 4.196281 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/sobel_filter/sobel_filter.vhd
| 1 | 5,844 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/07/2017 02:26:58 PM
-- Design Name:
-- Module Name: blur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library work;
use work.filter_lib.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sobel_filter is
port (
vid_i : in rgb_interface_t;
vid_o : out rgb_interface_t;
x_position : in std_logic_vector(15 downto 0);
threshold : in std_logic_vector(7 downto 0);
sensitivity : in std_logic_vector(3 downto 0);
invert : in std_logic;
split_line : in std_logic_vector(15 downto 0);
rotoscope : in std_logic;
PIXEL_CLK : in std_logic
);
end sobel_filter;
architecture Behavioral of sobel_filter is
-- We need to convert the image to grayscale before processing it.
signal pixel_in : pixel_t;
-- Size of the filter
constant FILTER_WIDTH : natural := 3;
constant FILTER_HEIGHT : natural := 3;
-- Output of the linebuffer / Input to the filters
signal window : pixel2d_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0);
-- Kernels for our filters
constant sobel_x_kernel : kernel_matrix_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0) := (
(-1, 0, 1),
(-2, 0, 2),
(-1, 0, 1)
);
constant sobel_y_kernel : kernel_matrix_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0) := (
(-1,-2,-1),
( 0, 0, 0),
( 1, 2, 1)
);
-- Results of the two filter kernels
signal sobel_x, sobel_y : signed(21 downto 0) := (others => '0');
-- Post-filter computations and results (thresholding, truncation, saturation, inversion, etc.)
signal sobel_mag, sobel_shift : signed(21 downto 0);
signal sobel_trunc, sobel_sat, sobel_inv : std_logic_vector(7 downto 0);
signal roto_rgb, roto_combined, rgb_buf, rgb_buf_reg : std_logic_vector(23 downto 0);
-- Buffered output
signal vid_buf, vid_buf_reg, vid_out : rgb_interface_t;
begin
-- Convert input to grayscale
pixel_in <=
std_logic_vector(
resize(unsigned( vid_i.RGB(23 downto 16) ), 10) +
resize(unsigned( vid_i.RGB(15 downto 8) ), 10) +
resize(unsigned( vid_i.RGB( 7 downto 0) ), 10)
);
-- Parameterizable pixel buffer
pixel_buf: entity work.pixel_buffer(Behavioral)
generic map (
WIDTH => FILTER_WIDTH,
HEIGHT => FILTER_HEIGHT,
LINE_LENGTH => 2048
)
port map (
-- Clock
CLK => PIXEL_CLK,
-- Inputs
data_in => pixel_in,
vde_in => vid_i.vde,
hs_in => vid_i.hs,
vs_in => vid_i.vs,
-- Outputs
data_out => window,
vde_out => vid_buf.vde,
hs_out => vid_buf.hs,
vs_out => vid_buf.vs
);
vid_buf.rgb <= vid_i.rgb;
-- Filter kernels
sobel_x_filter : entity work.filter_kernel(Combinational)
generic map (
WIDTH => FILTER_WIDTH,
HEIGHT => FILTER_HEIGHT,
kernel => sobel_x_kernel
)
port map (
data_in => window,
data_out => sobel_x
);
sobel_y_filter : entity work.filter_kernel(Combinational)
generic map (
WIDTH => FILTER_WIDTH,
HEIGHT => FILTER_HEIGHT,
kernel => sobel_y_kernel
)
port map (
data_in => window,
data_out => sobel_y
);
-- Process the outputs of the filters
-- Approximate magnitude
sobel_mag <= abs(sobel_x) + abs(sobel_y);
-- Move the radix point
sobel_shift <= sobel_mag srl to_integer(unsigned(sensitivity));
-- Truncate
sobel_trunc <= std_logic_vector(sobel_shift(7 downto 0));
-- Threshold and Saturate
sobel_sat <= (others=>'0') when unsigned(sobel_shift) < unsigned(threshold) else
(others=>'1') when unsigned(sobel_shift) > 255 else
sobel_trunc;
-- Invert
sobel_inv <= sobel_sat when invert = '0' else
not(sobel_sat);
-- Rotoscoping Logic
-- Give the color a nice "palettized" look
roto_rgb <= vid_i.RGB(23 downto 20) & vid_i.RGB(23 downto 20) -- R
& vid_i.RGB(15 downto 12) & vid_i.RGB(15 downto 12) -- G
& vid_i.RGB(7 downto 4) & vid_i.RGB(7 downto 4); -- B
roto_combined <= (sobel_inv & sobel_inv & sobel_inv) when unsigned(sobel_shift) > 255 else
roto_rgb;
-- Select Rotoscope
rgb_buf <= roto_combined when (rotoscope = '1') else
(sobel_inv & sobel_inv & sobel_inv);
-- Buffer stage
process(PIXEL_CLK)
begin
if (rising_edge(PIXEL_CLK)) then
-- Buffer stage
rgb_buf_reg <= rgb_buf;
vid_buf_reg <= vid_buf;
-- Do splitscreen and buffer the output
if (unsigned(x_position) < unsigned(split_line)) then
vid_out.rgb <= rgb_buf_reg;
else
vid_out.rgb <= vid_buf_reg.rgb;
end if;
vid_out.vde <= vid_buf_reg.vde;
vid_out.hs <= vid_buf_reg.hs;
vid_out.vs <= vid_buf_reg.vs;
end if;
end process;
-- Output
vid_o <= vid_out;
end Behavioral;
|
bsd-3-clause
|
81125fc1cc95f65eac8ce15974285035
| 0.540041 | 3.722293 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/main_pack.vhd
| 1 | 18,383 |
library ieee;
use ieee.std_logic_1164.all;
package main_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 530;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body main_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C1C0101";
ram_buffer(1) := X"279C8840";
ram_buffer(2) := X"3C050100";
ram_buffer(3) := X"24A50848";
ram_buffer(4) := X"3C040100";
ram_buffer(5) := X"24840AA4";
ram_buffer(6) := X"3C1D0100";
ram_buffer(7) := X"27BD0A48";
ram_buffer(8) := X"ACA00000";
ram_buffer(9) := X"00A4182A";
ram_buffer(10) := X"1460FFFD";
ram_buffer(11) := X"24A50004";
ram_buffer(12) := X"0C40007C";
ram_buffer(13) := X"00000000";
ram_buffer(14) := X"0840000E";
ram_buffer(15) := X"23BDFF98";
ram_buffer(16) := X"AFA10010";
ram_buffer(17) := X"AFA20014";
ram_buffer(18) := X"AFA30018";
ram_buffer(19) := X"AFA4001C";
ram_buffer(20) := X"AFA50020";
ram_buffer(21) := X"AFA60024";
ram_buffer(22) := X"AFA70028";
ram_buffer(23) := X"AFA8002C";
ram_buffer(24) := X"AFA90030";
ram_buffer(25) := X"AFAA0034";
ram_buffer(26) := X"AFAB0038";
ram_buffer(27) := X"AFAC003C";
ram_buffer(28) := X"AFAD0040";
ram_buffer(29) := X"AFAE0044";
ram_buffer(30) := X"AFAF0048";
ram_buffer(31) := X"AFB8004C";
ram_buffer(32) := X"AFB90050";
ram_buffer(33) := X"AFBF0054";
ram_buffer(34) := X"401A7000";
ram_buffer(35) := X"235AFFFC";
ram_buffer(36) := X"AFBA0058";
ram_buffer(37) := X"0000D810";
ram_buffer(38) := X"AFBB005C";
ram_buffer(39) := X"0000D812";
ram_buffer(40) := X"AFBB0060";
ram_buffer(41) := X"0C4000BE";
ram_buffer(42) := X"23A50000";
ram_buffer(43) := X"8FA10010";
ram_buffer(44) := X"8FA20014";
ram_buffer(45) := X"8FA30018";
ram_buffer(46) := X"8FA4001C";
ram_buffer(47) := X"8FA50020";
ram_buffer(48) := X"8FA60024";
ram_buffer(49) := X"8FA70028";
ram_buffer(50) := X"8FA8002C";
ram_buffer(51) := X"8FA90030";
ram_buffer(52) := X"8FAA0034";
ram_buffer(53) := X"8FAB0038";
ram_buffer(54) := X"8FAC003C";
ram_buffer(55) := X"8FAD0040";
ram_buffer(56) := X"8FAE0044";
ram_buffer(57) := X"8FAF0048";
ram_buffer(58) := X"8FB8004C";
ram_buffer(59) := X"8FB90050";
ram_buffer(60) := X"8FBF0054";
ram_buffer(61) := X"8FBA0058";
ram_buffer(62) := X"8FBB005C";
ram_buffer(63) := X"03600011";
ram_buffer(64) := X"8FBB0060";
ram_buffer(65) := X"03600013";
ram_buffer(66) := X"23BD0068";
ram_buffer(67) := X"341B0001";
ram_buffer(68) := X"03400008";
ram_buffer(69) := X"409B6000";
ram_buffer(70) := X"40026000";
ram_buffer(71) := X"03E00008";
ram_buffer(72) := X"40846000";
ram_buffer(73) := X"3C050100";
ram_buffer(74) := X"24A50150";
ram_buffer(75) := X"8CA60000";
ram_buffer(76) := X"AC06003C";
ram_buffer(77) := X"8CA60004";
ram_buffer(78) := X"AC060040";
ram_buffer(79) := X"8CA60008";
ram_buffer(80) := X"AC060044";
ram_buffer(81) := X"8CA6000C";
ram_buffer(82) := X"03E00008";
ram_buffer(83) := X"AC060048";
ram_buffer(84) := X"3C1A0100";
ram_buffer(85) := X"375A003C";
ram_buffer(86) := X"03400008";
ram_buffer(87) := X"00000000";
ram_buffer(88) := X"AC900000";
ram_buffer(89) := X"AC910004";
ram_buffer(90) := X"AC920008";
ram_buffer(91) := X"AC93000C";
ram_buffer(92) := X"AC940010";
ram_buffer(93) := X"AC950014";
ram_buffer(94) := X"AC960018";
ram_buffer(95) := X"AC97001C";
ram_buffer(96) := X"AC9E0020";
ram_buffer(97) := X"AC9C0024";
ram_buffer(98) := X"AC9D0028";
ram_buffer(99) := X"AC9F002C";
ram_buffer(100) := X"03E00008";
ram_buffer(101) := X"34020000";
ram_buffer(102) := X"8C900000";
ram_buffer(103) := X"8C910004";
ram_buffer(104) := X"8C920008";
ram_buffer(105) := X"8C93000C";
ram_buffer(106) := X"8C940010";
ram_buffer(107) := X"8C950014";
ram_buffer(108) := X"8C960018";
ram_buffer(109) := X"8C97001C";
ram_buffer(110) := X"8C9E0020";
ram_buffer(111) := X"8C9C0024";
ram_buffer(112) := X"8C9D0028";
ram_buffer(113) := X"8C9F002C";
ram_buffer(114) := X"03E00008";
ram_buffer(115) := X"34A20000";
ram_buffer(116) := X"00850019";
ram_buffer(117) := X"00001012";
ram_buffer(118) := X"00002010";
ram_buffer(119) := X"03E00008";
ram_buffer(120) := X"ACC40000";
ram_buffer(121) := X"0000000C";
ram_buffer(122) := X"03E00008";
ram_buffer(123) := X"00000000";
ram_buffer(124) := X"27BDFFE0";
ram_buffer(125) := X"3C0244A0";
ram_buffer(126) := X"AFB00014";
ram_buffer(127) := X"3C100100";
ram_buffer(128) := X"AE020A60";
ram_buffer(129) := X"3C030100";
ram_buffer(130) := X"3C020100";
ram_buffer(131) := X"AFBF001C";
ram_buffer(132) := X"AFB10018";
ram_buffer(133) := X"24420A64";
ram_buffer(134) := X"24630AA4";
ram_buffer(135) := X"24420008";
ram_buffer(136) := X"1443FFFE";
ram_buffer(137) := X"AC40FFF8";
ram_buffer(138) := X"3C0244A2";
ram_buffer(139) := X"AF828010";
ram_buffer(140) := X"3C020100";
ram_buffer(141) := X"26110A60";
ram_buffer(142) := X"244202A4";
ram_buffer(143) := X"3C050100";
ram_buffer(144) := X"24A502B4";
ram_buffer(145) := X"AE22000C";
ram_buffer(146) := X"00002025";
ram_buffer(147) := X"3C0244A4";
ram_buffer(148) := X"AF828014";
ram_buffer(149) := X"0C4001DF";
ram_buffer(150) := X"AE200010";
ram_buffer(151) := X"3C020100";
ram_buffer(152) := X"244202DC";
ram_buffer(153) := X"AE22001C";
ram_buffer(154) := X"0C400049";
ram_buffer(155) := X"AE200020";
ram_buffer(156) := X"0C400046";
ram_buffer(157) := X"24040001";
ram_buffer(158) := X"8E020A60";
ram_buffer(159) := X"240300FF";
ram_buffer(160) := X"AC430000";
ram_buffer(161) := X"8F838010";
ram_buffer(162) := X"24020001";
ram_buffer(163) := X"AC620000";
ram_buffer(164) := X"8F838010";
ram_buffer(165) := X"00000000";
ram_buffer(166) := X"AC620008";
ram_buffer(167) := X"1000FFFF";
ram_buffer(168) := X"00000000";
ram_buffer(169) := X"8F828010";
ram_buffer(170) := X"24030003";
ram_buffer(171) := X"03E00008";
ram_buffer(172) := X"AC430000";
ram_buffer(173) := X"8F838014";
ram_buffer(174) := X"00000000";
ram_buffer(175) := X"8C620000";
ram_buffer(176) := X"00000000";
ram_buffer(177) := X"30420002";
ram_buffer(178) := X"1040FFFC";
ram_buffer(179) := X"00000000";
ram_buffer(180) := X"AC650008";
ram_buffer(181) := X"03E00008";
ram_buffer(182) := X"00000000";
ram_buffer(183) := X"8F828014";
ram_buffer(184) := X"3C040100";
ram_buffer(185) := X"8C450004";
ram_buffer(186) := X"24840810";
ram_buffer(187) := X"00052E00";
ram_buffer(188) := X"084001E2";
ram_buffer(189) := X"00052E03";
ram_buffer(190) := X"3C030100";
ram_buffer(191) := X"8C620A60";
ram_buffer(192) := X"27BDFFE0";
ram_buffer(193) := X"8C420004";
ram_buffer(194) := X"AFB10018";
ram_buffer(195) := X"3C110100";
ram_buffer(196) := X"AFB00014";
ram_buffer(197) := X"AFBF001C";
ram_buffer(198) := X"00608025";
ram_buffer(199) := X"26310A64";
ram_buffer(200) := X"2C430008";
ram_buffer(201) := X"14600006";
ram_buffer(202) := X"00000000";
ram_buffer(203) := X"8FBF001C";
ram_buffer(204) := X"8FB10018";
ram_buffer(205) := X"8FB00014";
ram_buffer(206) := X"03E00008";
ram_buffer(207) := X"27BD0020";
ram_buffer(208) := X"000210C0";
ram_buffer(209) := X"02221021";
ram_buffer(210) := X"8C430000";
ram_buffer(211) := X"8C440004";
ram_buffer(212) := X"0060F809";
ram_buffer(213) := X"00000000";
ram_buffer(214) := X"8E020A60";
ram_buffer(215) := X"00000000";
ram_buffer(216) := X"8C420004";
ram_buffer(217) := X"1000FFEF";
ram_buffer(218) := X"2C430008";
ram_buffer(219) := X"10C0000D";
ram_buffer(220) := X"00C53021";
ram_buffer(221) := X"2402FFF0";
ram_buffer(222) := X"00C21824";
ram_buffer(223) := X"0066302B";
ram_buffer(224) := X"00A22824";
ram_buffer(225) := X"00063100";
ram_buffer(226) := X"24620010";
ram_buffer(227) := X"00463021";
ram_buffer(228) := X"3C022000";
ram_buffer(229) := X"00822021";
ram_buffer(230) := X"2402FFF0";
ram_buffer(231) := X"14C50003";
ram_buffer(232) := X"00A21824";
ram_buffer(233) := X"03E00008";
ram_buffer(234) := X"00000000";
ram_buffer(235) := X"AC830000";
ram_buffer(236) := X"AC600000";
ram_buffer(237) := X"1000FFF9";
ram_buffer(238) := X"24A50010";
ram_buffer(239) := X"24020001";
ram_buffer(240) := X"14400002";
ram_buffer(241) := X"0082001B";
ram_buffer(242) := X"0007000D";
ram_buffer(243) := X"00001812";
ram_buffer(244) := X"0065182B";
ram_buffer(245) := X"10600006";
ram_buffer(246) := X"00450018";
ram_buffer(247) := X"00004025";
ram_buffer(248) := X"14400006";
ram_buffer(249) := X"00000000";
ram_buffer(250) := X"03E00008";
ram_buffer(251) := X"A0E00000";
ram_buffer(252) := X"00001012";
ram_buffer(253) := X"1000FFF2";
ram_buffer(254) := X"00000000";
ram_buffer(255) := X"14400002";
ram_buffer(256) := X"0082001B";
ram_buffer(257) := X"0007000D";
ram_buffer(258) := X"00002010";
ram_buffer(259) := X"00004812";
ram_buffer(260) := X"00000000";
ram_buffer(261) := X"00000000";
ram_buffer(262) := X"14A00002";
ram_buffer(263) := X"0045001B";
ram_buffer(264) := X"0007000D";
ram_buffer(265) := X"00001012";
ram_buffer(266) := X"15000005";
ram_buffer(267) := X"292A000A";
ram_buffer(268) := X"1D200004";
ram_buffer(269) := X"24EB0001";
ram_buffer(270) := X"1440FFE9";
ram_buffer(271) := X"00000000";
ram_buffer(272) := X"24EB0001";
ram_buffer(273) := X"15400004";
ram_buffer(274) := X"24030030";
ram_buffer(275) := X"14C00002";
ram_buffer(276) := X"24030037";
ram_buffer(277) := X"24030057";
ram_buffer(278) := X"00691821";
ram_buffer(279) := X"A0E30000";
ram_buffer(280) := X"25080001";
ram_buffer(281) := X"1000FFDE";
ram_buffer(282) := X"01603825";
ram_buffer(283) := X"27BDFFD8";
ram_buffer(284) := X"AFB40020";
ram_buffer(285) := X"AFB3001C";
ram_buffer(286) := X"AFB20018";
ram_buffer(287) := X"AFB10014";
ram_buffer(288) := X"AFBF0024";
ram_buffer(289) := X"AFB00010";
ram_buffer(290) := X"00809025";
ram_buffer(291) := X"00A09825";
ram_buffer(292) := X"8FB10038";
ram_buffer(293) := X"10E00002";
ram_buffer(294) := X"24140020";
ram_buffer(295) := X"24140030";
ram_buffer(296) := X"02201025";
ram_buffer(297) := X"24420001";
ram_buffer(298) := X"8043FFFF";
ram_buffer(299) := X"00000000";
ram_buffer(300) := X"14600009";
ram_buffer(301) := X"00C08025";
ram_buffer(302) := X"1A000009";
ram_buffer(303) := X"02802825";
ram_buffer(304) := X"0260F809";
ram_buffer(305) := X"02402025";
ram_buffer(306) := X"1000FFFB";
ram_buffer(307) := X"2610FFFF";
ram_buffer(308) := X"1000FFF4";
ram_buffer(309) := X"24C6FFFF";
ram_buffer(310) := X"1CC0FFFD";
ram_buffer(311) := X"00000000";
ram_buffer(312) := X"26310001";
ram_buffer(313) := X"8225FFFF";
ram_buffer(314) := X"00000000";
ram_buffer(315) := X"14A00009";
ram_buffer(316) := X"00000000";
ram_buffer(317) := X"8FBF0024";
ram_buffer(318) := X"8FB40020";
ram_buffer(319) := X"8FB3001C";
ram_buffer(320) := X"8FB20018";
ram_buffer(321) := X"8FB10014";
ram_buffer(322) := X"8FB00010";
ram_buffer(323) := X"03E00008";
ram_buffer(324) := X"27BD0028";
ram_buffer(325) := X"0260F809";
ram_buffer(326) := X"02402025";
ram_buffer(327) := X"1000FFF1";
ram_buffer(328) := X"26310001";
ram_buffer(329) := X"8C820000";
ram_buffer(330) := X"00000000";
ram_buffer(331) := X"24430001";
ram_buffer(332) := X"AC830000";
ram_buffer(333) := X"03E00008";
ram_buffer(334) := X"A0450000";
ram_buffer(335) := X"27BDFFB8";
ram_buffer(336) := X"AFB5003C";
ram_buffer(337) := X"AFB40038";
ram_buffer(338) := X"AFB30034";
ram_buffer(339) := X"AFB20030";
ram_buffer(340) := X"AFB1002C";
ram_buffer(341) := X"AFB00028";
ram_buffer(342) := X"AFBF0044";
ram_buffer(343) := X"AFB60040";
ram_buffer(344) := X"00809025";
ram_buffer(345) := X"00A09825";
ram_buffer(346) := X"00C08825";
ram_buffer(347) := X"00E08025";
ram_buffer(348) := X"24140025";
ram_buffer(349) := X"24150030";
ram_buffer(350) := X"82250000";
ram_buffer(351) := X"00000000";
ram_buffer(352) := X"10A00035";
ram_buffer(353) := X"00000000";
ram_buffer(354) := X"10B40006";
ram_buffer(355) := X"00000000";
ram_buffer(356) := X"26310001";
ram_buffer(357) := X"0260F809";
ram_buffer(358) := X"02402025";
ram_buffer(359) := X"1000FFF6";
ram_buffer(360) := X"00000000";
ram_buffer(361) := X"82260001";
ram_buffer(362) := X"00000000";
ram_buffer(363) := X"10D50015";
ram_buffer(364) := X"240D0001";
ram_buffer(365) := X"26310002";
ram_buffer(366) := X"00006825";
ram_buffer(367) := X"24C2FFD0";
ram_buffer(368) := X"304200FF";
ram_buffer(369) := X"2C42000A";
ram_buffer(370) := X"10400018";
ram_buffer(371) := X"00006025";
ram_buffer(372) := X"30C200FF";
ram_buffer(373) := X"2443FFD0";
ram_buffer(374) := X"2C63000A";
ram_buffer(375) := X"1060000C";
ram_buffer(376) := X"2443FF9F";
ram_buffer(377) := X"24C3FFD0";
ram_buffer(378) := X"000C1080";
ram_buffer(379) := X"004C6021";
ram_buffer(380) := X"000C6040";
ram_buffer(381) := X"26310001";
ram_buffer(382) := X"8226FFFF";
ram_buffer(383) := X"1000FFF4";
ram_buffer(384) := X"01836021";
ram_buffer(385) := X"82260002";
ram_buffer(386) := X"1000FFEC";
ram_buffer(387) := X"26310003";
ram_buffer(388) := X"2C630006";
ram_buffer(389) := X"1060001A";
ram_buffer(390) := X"2442FFBF";
ram_buffer(391) := X"24C3FFA9";
ram_buffer(392) := X"2862000B";
ram_buffer(393) := X"1440FFF1";
ram_buffer(394) := X"000C1080";
ram_buffer(395) := X"24020063";
ram_buffer(396) := X"10C20045";
ram_buffer(397) := X"28C20064";
ram_buffer(398) := X"10400016";
ram_buffer(399) := X"24020073";
ram_buffer(400) := X"10D4004C";
ram_buffer(401) := X"24020058";
ram_buffer(402) := X"10C20033";
ram_buffer(403) := X"00000000";
ram_buffer(404) := X"14C0FFC9";
ram_buffer(405) := X"00000000";
ram_buffer(406) := X"8FBF0044";
ram_buffer(407) := X"8FB60040";
ram_buffer(408) := X"8FB5003C";
ram_buffer(409) := X"8FB40038";
ram_buffer(410) := X"8FB30034";
ram_buffer(411) := X"8FB20030";
ram_buffer(412) := X"8FB1002C";
ram_buffer(413) := X"8FB00028";
ram_buffer(414) := X"03E00008";
ram_buffer(415) := X"27BD0048";
ram_buffer(416) := X"2C420006";
ram_buffer(417) := X"1040FFEA";
ram_buffer(418) := X"24020063";
ram_buffer(419) := X"1000FFE4";
ram_buffer(420) := X"24C3FFC9";
ram_buffer(421) := X"10C20032";
ram_buffer(422) := X"28C20074";
ram_buffer(423) := X"10400019";
ram_buffer(424) := X"24020075";
ram_buffer(425) := X"24020064";
ram_buffer(426) := X"14C2FFB3";
ram_buffer(427) := X"26160004";
ram_buffer(428) := X"8E040000";
ram_buffer(429) := X"00000000";
ram_buffer(430) := X"04810005";
ram_buffer(431) := X"27A70018";
ram_buffer(432) := X"2402002D";
ram_buffer(433) := X"00042023";
ram_buffer(434) := X"A3A20018";
ram_buffer(435) := X"27A70019";
ram_buffer(436) := X"00003025";
ram_buffer(437) := X"2405000A";
ram_buffer(438) := X"0C4000EF";
ram_buffer(439) := X"00000000";
ram_buffer(440) := X"27A20018";
ram_buffer(441) := X"AFA20010";
ram_buffer(442) := X"01A03825";
ram_buffer(443) := X"01803025";
ram_buffer(444) := X"02602825";
ram_buffer(445) := X"0C40011B";
ram_buffer(446) := X"02402025";
ram_buffer(447) := X"1000FF9E";
ram_buffer(448) := X"02C08025";
ram_buffer(449) := X"10C2000A";
ram_buffer(450) := X"26160004";
ram_buffer(451) := X"24020078";
ram_buffer(452) := X"14C2FF99";
ram_buffer(453) := X"00000000";
ram_buffer(454) := X"38C60058";
ram_buffer(455) := X"26160004";
ram_buffer(456) := X"27A70018";
ram_buffer(457) := X"2CC60001";
ram_buffer(458) := X"10000004";
ram_buffer(459) := X"24050010";
ram_buffer(460) := X"27A70018";
ram_buffer(461) := X"00003025";
ram_buffer(462) := X"2405000A";
ram_buffer(463) := X"8E040000";
ram_buffer(464) := X"1000FFE5";
ram_buffer(465) := X"00000000";
ram_buffer(466) := X"82050003";
ram_buffer(467) := X"02402025";
ram_buffer(468) := X"0260F809";
ram_buffer(469) := X"26160004";
ram_buffer(470) := X"1000FF87";
ram_buffer(471) := X"02C08025";
ram_buffer(472) := X"8E020000";
ram_buffer(473) := X"26160004";
ram_buffer(474) := X"AFA20010";
ram_buffer(475) := X"1000FFDF";
ram_buffer(476) := X"00003825";
ram_buffer(477) := X"1000FF87";
ram_buffer(478) := X"24050025";
ram_buffer(479) := X"AF85800C";
ram_buffer(480) := X"03E00008";
ram_buffer(481) := X"AF848008";
ram_buffer(482) := X"27BDFFE0";
ram_buffer(483) := X"AFA50024";
ram_buffer(484) := X"AFA60028";
ram_buffer(485) := X"8F85800C";
ram_buffer(486) := X"00803025";
ram_buffer(487) := X"8F848008";
ram_buffer(488) := X"AFA7002C";
ram_buffer(489) := X"27A70024";
ram_buffer(490) := X"AFBF001C";
ram_buffer(491) := X"0C40014F";
ram_buffer(492) := X"AFA70010";
ram_buffer(493) := X"8FBF001C";
ram_buffer(494) := X"00000000";
ram_buffer(495) := X"03E00008";
ram_buffer(496) := X"27BD0020";
ram_buffer(497) := X"27BDFFE0";
ram_buffer(498) := X"AFA60028";
ram_buffer(499) := X"00A03025";
ram_buffer(500) := X"3C050100";
ram_buffer(501) := X"AFA40020";
ram_buffer(502) := X"AFA7002C";
ram_buffer(503) := X"27A40020";
ram_buffer(504) := X"27A70028";
ram_buffer(505) := X"24A50524";
ram_buffer(506) := X"AFBF001C";
ram_buffer(507) := X"0C40014F";
ram_buffer(508) := X"AFA70010";
ram_buffer(509) := X"8FA20020";
ram_buffer(510) := X"00000000";
ram_buffer(511) := X"A0400000";
ram_buffer(512) := X"8FBF001C";
ram_buffer(513) := X"00000000";
ram_buffer(514) := X"03E00008";
ram_buffer(515) := X"27BD0020";
ram_buffer(516) := X"54686520";
ram_buffer(517) := X"6C657474";
ram_buffer(518) := X"65722074";
ram_buffer(519) := X"79706564";
ram_buffer(520) := X"20776173";
ram_buffer(521) := X"3A202563";
ram_buffer(522) := X"0A0D0000";
ram_buffer(523) := X"00000000";
ram_buffer(524) := X"00000100";
ram_buffer(525) := X"01010001";
ram_buffer(526) := X"00000000";
ram_buffer(527) := X"00000000";
ram_buffer(528) := X"00000000";
ram_buffer(529) := X"00000000";
return ram_buffer;
end;
end;
|
mit
|
aba9006c9955d806a6efff74e794647b
| 0.617853 | 2.305657 | false | false | false | false |
makestuff/dvr-connectors
|
conv-32to8/vhdl/conv_32to8.vhdl
| 1 | 3,042 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_32to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 32-bit data coming in
data32_in : in std_logic_vector(31 downto 0);
valid32_in : in std_logic;
ready32_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_32to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(23 downto 0) := (others => '0');
signal wip_next : std_logic_vector(23 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data32_in, valid32_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready32_out <= '0'; -- not ready for data from 32-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready32_out <= '0'; -- not ready for data from 32-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE3;
end if;
-- Write byte 3 (LSB)
when S_WRITE3 =>
ready32_out <= '0'; -- not ready for data from 32-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready32_out <= ready8_in; -- ready for data from 32-bit side
data8_out <= data32_in(31 downto 24);
valid8_out <= valid32_in;
if ( valid32_in = '1' and ready8_in = '1' ) then
wip_next <= data32_in(23 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
a0c29830a368d8d7ab4803fd062f4a9a
| 0.622945 | 2.944821 | false | false | false | false |
makestuff/vga_test
|
vhdl/clk_gen/ep2c5/clk_gen_50MHz.vhdl
| 1 | 15,269 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_gen.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_gen IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END clk_gen;
ARCHITECTURE SYN OF clk_gen IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=clk_gen",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
7d5a277a8ae49eaa300d33a4c612ee5c
| 0.699849 | 3.358038 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_smple_sm.vhd
| 4 | 16,881 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
|
bsd-3-clause
|
fb11cec3de166b834d51a35c81fe4069
| 0.382264 | 5.447241 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/sim/axi_dma_0.vhd
| 1 | 24,747 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY axi_dma_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END axi_dma_0;
ARCHITECTURE axi_dma_0_arch OF axi_dma_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_dma_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "kintex7"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END axi_dma_0_arch;
|
bsd-3-clause
|
25ea18d78e653ab9de5cb484b90228fe
| 0.673698 | 2.784316 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/RegCaster_tb.vhdl
| 1 | 3,829 |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use ieee.numeric_std.all;
use work.utils.all;
use work.txt_utils.all;
-- A testbench has no ports.
entity RegCaster_tb is
end RegCaster_tb;
architecture test of RegCaster_tb is
-- Declaration of the component that will be instantiated.
component RegCaster
port (input : in word_t;
SignExtend : in ctrl_t;
size : in ctrl_memwidth_t;
extended : out word_t
);
end component;
-- Specifies which entity is bound with the component.
for instance: RegCaster use entity work.RegCaster;
signal input : word_t;
signal SignExtend : ctrl_t;
signal size : ctrl_memwidth_t;
signal extended : word_t;
begin
-- Component instantiation.
instance: RegCaster port map (
input => input,
SignExtend => SignExtend,
size => size,
extended => extended
);
-- This process does the real job.
process
variable error : boolean := false;
variable error_count : integer := 0;
type load_t is record
SignExtend : ctrl_t;
size : ctrl_memwidth_t;
end record;
type load_table_t is array (natural range <>) of load_t;
constant loads : load_table_t := (
('0', WIDTH_BYTE),
('1', WIDTH_BYTE),
('0', WIDTH_HALF),
('1', WIDTH_HALF),
('0', WIDTH_WORD),
('1', WIDTH_WORD)
);
constant lbu : natural := 0;
constant lb : natural := 1;
constant lhu : natural := 2;
constant lh : natural := 3;
constant lwu : natural := 4;
constant lw : natural := 5; -- Won't happend
type testcase_t is record
input : word_t;
op : natural;
extended : word_t;
end record;
type testcase_table_t is array (natural range <>) of testcase_t;
constant testcases : testcase_table_t := (
(X"0000_0000", lb, X"0000_0000"),
(X"0000_0000", lw, X"0000_0000"),
(X"0000_ffff", lwu, X"0000_ffff"),
(X"0000_ffff", lw, X"0000_ffff"),
(X"0000_00ff", lb, X"ffff_ffff"),
(X"ffff_f00d", lh, X"ffff_f00d"),
(X"0000_f00d", lh, X"ffff_f00d"),
(X"0000_0bad", lhu, X"0000_0bad")
);
begin
for i in testcases'range loop
-- Set the inputs.
input <= testcases(i).input;
SignExtend <= loads(testcases(i).op).SignExtend;
size <= loads(testcases(i).op).size;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
error := extended /= testcases(i).extended;
if error then
error_count := error_count + 1;
end if;
assert not error report
ANSI_RED & "Failure in testcase " & integer'image(i) & ANSI_NONE severity note;
assert not error report ANSI_RED &
"Got: " & integer'image(vtou(extended)) &
", Expected: " & integer'image(vtou(testcases(i).extended))
& ANSI_NONE severity note;
end loop;
assert error_count /= 0 report
ANSI_GREEN & "Test's over." & ANSI_NONE
severity note;
assert error_count = 0 report
-- ANSI escape characters for green text
ANSI_RED & integer'image(error_count) & " testcase(s) failed." & ANSI_NONE
severity failure;
-- Wait forever; this will finish the simulation.
wait;
end process;
end test;
|
gpl-3.0
|
24c0c843dfa1a2b0365348a2e75d2c3a
| 0.51345 | 4.143939 | false | true | false | false |
a3f/r3k.vhdl
|
vhdl/arch/clkdivider.vhdl
| 1 | 774 |
-- A DCM block would be more accurate, right?
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity clkdivider is
port (
ticks : in natural;
bigclk : in std_logic;
rst : in std_logic;
smallclk : out std_logic
);
end;
architecture behav of clkdivider is
begin
clkdivider: process(bigclk, rst, ticks)
variable i : natural := 0;
variable pulse : std_logic := '0';
begin
if rst = '1' then
i := 0;
pulse := '0';
elsif rising_edge(bigclk) then
i := i + 1;
if i >= ticks then
pulse := not pulse;
i := 0;
end if;
end if;
smallclk <= pulse;
end process;
end behav;
|
gpl-3.0
|
5e4a876c257d48e176472187e5d21225
| 0.511628 | 3.889447 | false | false | false | false |
tmeissner/cryptocores
|
aes/rtl/vhdl/aes_dec.vhd
| 1 | 5,471 |
-- ======================================================================
-- AES encryption/decryption
-- Copyright (C) 2019 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity aes_dec is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity aes_dec;
architecture rtl of aes_dec is
begin
IterG : if design_type = "ITER" generate
signal s_round : t_dec_rounds;
begin
DeCryptP : process (reset_i, clk_i) is
variable v_state : t_datatable2d;
type t_key_array is array (0 to 10) of t_key;
variable v_round_keys : t_key_array;
begin
if (reset_i = '0') then
v_state := (others => (others => (others => '0')));
s_round <= 0;
accept_o <= '0';
data_o <= (others => '0');
valid_o <= '0';
elsif (rising_edge(clk_i)) then
case s_round is
when 0 =>
accept_o <= '1';
if (accept_o = '1' and valid_i = '1') then
accept_o <= '0';
v_state := set_state(data_i);
v_round_keys(0) := set_key(key_i);
for i in t_key_rounds'low to t_key_rounds'high loop
v_round_keys(i+1) := key_round(v_round_keys(i), i);
end loop;
s_round <= s_round + 1;
end if;
when 1 =>
v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
s_round <= s_round + 1;
when t_dec_rounds'high-1 =>
v_state := invshiftrow(v_state);
v_state := invsubbytes(v_state);
v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
s_round <= s_round + 1;
-- set data & valid to save one cycle
valid_o <= '1';
data_o <= get_state(v_state);
when t_dec_rounds'high =>
if (valid_o = '1' and accept_i = '1') then
valid_o <= '0';
data_o <= (others => '0');
s_round <= 0;
-- Set accept to save one cycle
accept_o <= '1';
end if;
when others =>
v_state := invshiftrow(v_state);
v_state := invsubbytes(v_state);
v_state := addroundkey(v_state, v_round_keys(v_round_keys'length-s_round));
v_state := invmixcolumns(v_state);
s_round <= s_round + 1;
end case;
end if;
end process DeCryptP;
psl : block is
signal s_key , s_din, s_dout : std_logic_vector(0 to 127) := (others => '0');
begin
process (clk_i) is
begin
if (rising_edge(clk_i)) then
s_key <= key_i;
s_din <= data_i;
s_dout <= data_o;
end if;
end process;
default clock is rising_edge(clk_i);
-- initial reset
restrict {not reset_i; reset_i[+]}[*1];
-- constraints
assume always (valid_i and not accept_o -> next valid_i);
assume always (valid_i and not accept_o -> next key_i = s_key);
assume always (valid_i and not accept_o -> next data_i = s_din);
ACCEPTO_c : cover {accept_o};
ACCEPT_IN_ROUND_0_ONLY_a : assert always (accept_o -> s_round = 0);
VALIDI_AND_ACCEPTO_c : cover {valid_i and accept_o};
ACCEPT_OFF_WHEN_VALID_a : assert always (valid_i and accept_o -> next not accept_o);
VALIDO_c : cover {valid_o};
VALID_IN_LAST_ROUND_ONLY_a : assert always (valid_o -> s_round = t_enc_rounds'high);
VALIDO_AND_ACCEPTI_c : cover {valid_o and accept_i};
VALID_OFF_WHEN_ACCEPTED_a : assert always (valid_o and accept_i -> next not valid_o);
VALIDO_AND_NOT_ACCEPTI_c : cover {valid_o and not accept_i};
VALID_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next valid_o);
DATA_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next data_o = s_dout);
end block psl;
end generate IterG;
end architecture rtl;
|
gpl-2.0
|
447bfe43ae62db8bd4d4206cb05628d6
| 0.534637 | 3.543394 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_PofVrefofVref.vhd
| 1 | 1,943 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_PofVrefofVref is
port (
clock : in std_logic;
R : in std_logic_vector(31 downto 0);
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : in std_logic_vector(31 downto 0);
Vsigrefofkofone : in std_logic_vector(31 downto 0);
Vsigrefofkoftwo : in std_logic_vector(31 downto 0);
PofVrefofVref : out std_logic_vector(31 downto 0)
);
end k_ukf_PofVrefofVref;
architecture struct of k_ukf_PofVrefofVref is
component k_ukf_Pdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Wofcofzero : in std_logic_vector(31 downto 0);
Wofcofone : in std_logic_vector(31 downto 0);
Wofcoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Q : in std_logic_vector(31 downto 0);
Pdashofkplusone : out std_logic_vector(31 downto 0)
);
end component;
begin
M1 : k_ukf_Pdashofkplusone port map
( clock => clock,
Vsigactofkofzero => Vsigrefofkofzero,
Vsigactofkofone => Vsigrefofkofone,
Vsigactofkoftwo => Vsigrefofkoftwo,
Wofcofzero => Wofcofzero,
Wofcofone => Wofcofone,
Wofcoftwo => Wofcoftwo,
Vactcapdashofkplusone => Vrefcapofkplusone,
Q => R,
Pdashofkplusone => PofVrefofVref);
end struct;
|
gpl-2.0
|
08cd597769771d923e9d56addbf79154
| 0.594956 | 4.151709 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_dma_v7_1_8/hdl/src/vhdl/axi_dma_sofeof_gen.vhd
| 4 | 19,880 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_sofeof_gen.vhd
-- Description: This entity manages
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_sofeof_gen is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
axis_tready : in std_logic ; --
axis_tvalid : in std_logic ; --
axis_tlast : in std_logic ; --
--
packet_sof : out std_logic ; --
packet_eof : out std_logic --
--
);
end axi_dma_sofeof_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_sofeof_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_ready : std_logic := '0';
signal p_valid : std_logic := '0';
signal p_valid_d1 : std_logic := '0';
signal p_valid_re : std_logic := '0';
signal p_last : std_logic := '0';
signal p_last_d1 : std_logic := '0';
signal p_last_re : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_valid : std_logic := '0';
signal s_valid_d1 : std_logic := '0';
signal s_valid_re : std_logic := '0';
signal s_last : std_logic := '0';
signal s_last_d1 : std_logic := '0';
signal s_last_re : std_logic := '0';
signal s_sof_d1_cdc_tig : std_logic := '0';
signal s_sof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_sof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_sof_d2 : SIGNAL IS "true";
signal s_sof_d3 : std_logic := '0';
signal s_sof_re : std_logic := '0';
signal s_sof : std_logic := '0';
signal p_sof : std_logic := '0';
signal s_eof_d1_cdc_tig : std_logic := '0';
signal s_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_eof_d2 : SIGNAL IS "true";
signal s_eof_d3 : std_logic := '0';
signal s_eof_re : std_logic := '0';
signal p_eof : std_logic := '0';
signal p_eof_d1_cdc_tig : std_logic := '0';
signal p_eof_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_eof_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_eof_d2 : SIGNAL IS "true";
signal p_eof_d3 : std_logic := '0';
signal p_eof_clr : std_logic := '0';
signal s_sof_generated : std_logic := '0';
signal sof_generated_fe : std_logic := '0';
signal s_eof_re_latch : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- pass internal version out
packet_sof <= s_sof_re;
packet_eof <= s_eof_re;
-- Generate for when primary clock is asynchronous
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---------------------------------------------------------------------------
-- Generate Packet SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid <= '0';
p_last <= '0';
p_ready <= '0';
else
p_valid <= axis_tvalid;
p_last <= axis_tlast ;
p_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_valid_d1 <= '0';
p_last_d1 <= '0';
p_last_re <= '0';
else
p_valid_d1 <= p_valid and p_ready;
p_last_d1 <= p_last and p_valid and p_ready;
-- register to aligne with setting of p_sof
p_last_re <= p_ready and p_valid and p_last and not p_last_d1;
end if;
end if;
end process REG_FOR_RE;
p_valid_re <= p_ready and p_valid and not p_valid_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- clear at end of packet
if(p_reset_n = '0' or p_eof_clr = '1')then
p_sof <= '0';
-- assert at beginning of packet hold to allow
-- clock crossing to slower secondary clk
elsif(p_valid_re = '1')then
p_sof <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_sof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_sof_d2,
scndry_vect_out => open
);
SOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_sof_d1_cdc_tig <= '0';
-- s_sof_d2 <= '0';
s_sof_d3 <= '0';
else
-- s_sof_d1_cdc_tig <= p_sof;
-- s_sof_d2 <= s_sof_d1_cdc_tig;
s_sof_d3 <= s_sof_d2;
end if;
end if;
end process SOF_REG2SCNDRY1;
s_sof_re <= s_sof_d2 and not s_sof_d3;
---------------------------------------------------------------------------
-- Generate Packet EOF
---------------------------------------------------------------------------
-- Sample and hold valid re to create sof
EOF_SMPL_N_HOLD : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0' or p_eof_clr = '1')then
p_eof <= '0';
-- if p_last but p_sof not set then it means between pkt
-- gap was too small to catch new sof. therefor do not
-- generate eof
elsif(p_last_re = '1' and p_sof = '0')then
p_eof <= '0';
elsif(p_last_re = '1')then
p_eof <= '1';
end if;
end if;
end process EOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
-- CDC register has to be a pure flop
EOF_REG2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_eof,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_eof_d2,
scndry_vect_out => open
);
EOF_REG2SCNDRY1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
-- s_eof_d1_cdc_tig <= '0';
-- s_eof_d2 <= '0';
s_eof_d3 <= '0'; -- CR605883
else
-- s_eof_d1_cdc_tig <= p_eof;
-- s_eof_d2 <= s_eof_d1_cdc_tig;
s_eof_d3 <= s_eof_d2; -- CR605883
end if;
end if;
end process EOF_REG2SCNDRY1;
s_eof_re <= s_eof_d2 and not s_eof_d3;
EOF_latch : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_eof_re_latch <= '0';
elsif (s_eof_re = '1') then
s_eof_re_latch <= not s_eof_re_latch;
end if;
end if;
end process EOF_latch;
-- Register s_sof_re back into primary clock domain to use
-- as clear of p_sof.
EOF_REG2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_eof_re_latch,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_eof_d2,
scndry_vect_out => open
);
EOF_REG2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_eof_d1_cdc_tig <= '0';
-- p_eof_d2 <= '0';
p_eof_d3 <= '0';
else
-- p_eof_d1_cdc_tig <= s_eof_re_latch;
-- p_eof_d2 <= p_eof_d1_cdc_tig;
p_eof_d3 <= p_eof_d2;
end if;
end if;
end process EOF_REG2PRMRY1;
-- p_eof_clr <= p_eof_d2 and not p_eof_d3;-- CR565366
-- drive eof clear for minimum of 2 scndry clocks
-- to guarentee secondary capture. this allows
-- new valid assertions to not be missed in
-- creating next sof.
p_eof_clr <= p_eof_d2 xor p_eof_d3;
end generate GEN_FOR_ASYNC;
-- Generate for when primary clock is synchronous
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
---------------------------------------------------------------------------
-- Generate Packet EOF and SOF
---------------------------------------------------------------------------
-- Register stream control in to isolate wrt clock
-- for timing closure
REG_STRM_IN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid <= '0';
s_last <= '0';
s_ready <= '0';
else
s_valid <= axis_tvalid;
s_last <= axis_tlast ;
s_ready <= axis_tready;
end if;
end if;
end process REG_STRM_IN;
-- Generate rising edge pulse on valid to use for
-- smaple and hold register
REG_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_valid_d1 <= '0';
s_last_d1 <= '0';
else
s_valid_d1 <= s_valid and s_ready;
s_last_d1 <= s_last and s_valid and s_ready;
end if;
end if;
end process REG_FOR_RE;
-- CR565366 investigating delay interurpt issue discovered
-- this coding issue.
-- s_valid_re <= s_ready and s_valid and not s_last_d1;
s_valid_re <= s_ready and s_valid and not s_valid_d1;
s_last_re <= s_ready and s_valid and s_last and not s_last_d1;
-- Sample and hold valid re to create sof
SOF_SMPL_N_HOLD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(p_reset_n = '0' or s_eof_re = '1')then
s_sof_generated <= '0';
-- new
elsif((s_valid_re = '1')
or (sof_generated_fe = '1' and s_ready = '1' and s_valid = '1'))then
s_sof_generated <= '1';
end if;
end if;
end process SOF_SMPL_N_HOLD;
-- Register p_sof into secondary clock domain to
-- generate packet_sof and also to clear sample and held p_sof
SOF_REG2SCNDRY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_sof_d1_cdc_tig <= '0';
else
s_sof_d1_cdc_tig <= s_sof_generated;
end if;
end if;
end process SOF_REG2SCNDRY;
-- generate falling edge pulse on end of packet for use if
-- need to generate an immediate sof.
sof_generated_fe <= not s_sof_generated and s_sof_d1_cdc_tig;
-- generate SOF on rising edge of valid if not already in a packet OR...
s_sof_re <= '1' when (s_valid_re = '1' and s_sof_generated = '0')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1') -- and valid asserted
else '0';
-- generate eof on rising edge of valid last assertion OR...
s_eof_re <= '1' when (s_last_re = '1')
or (sof_generated_fe = '1' -- If end of previous packet
and s_ready = '1' -- and ready asserted
and s_valid = '1' -- and valid asserted
and s_last = '1') -- and last asserted
else '0';
end generate GEN_FOR_SYNC;
end implementation;
|
bsd-3-clause
|
b1fe2d324df81b50b9bce2783dafd2c8
| 0.443511 | 4.08046 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_int.vhd
| 1 | 11,367 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 28, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Interrupt Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_int_pack.all;
--! The Interrupt Controller is developed to extend
--! the single external interrupt of the Plasma-SoC's CPU to
--! support multiple interrupts. The only goals behind the
--! development of the Interrupt Controller are simplicity and
--! having a Slave AXI4-Lite interface.
--!
--! The operation of the Interrupt Controller is as follows. Each
--! device interrupt, which are the interrupts associated with the
--! devices connecting to the Interrupt Controller, is enabled by
--! writing to the corresponding bit at the Interrupt Enables register
--! located at axi_int_enables_offset. A device can trigger its respective
--! interrupt by setting it high. At this point, the device interrupt is
--! considered active if it is both enabled in the Interrupt Enables register
--! and set high by the respective device.
--!
--! If there is at least one active device interrupt, the Interrupt Controller
--! will set the CPU interrupt, which is the single interrupt associated with the
--! CPU, high and set the Interrupt Identifier register at axi_int_id_offset
--! as the identifier (IRQ) of the active device interrupt.
--! If there are multiple active device interrupts, the lowest identifier will
--! always have priority over the Interrupt Identifier register. The CPU
--! interrupt will remain high until there are no active device interrupts.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_int is
generic(
-- Slave AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
axi_int_id_offset : integer := 4; --! Defines the offset from axi_base_address for the Interrupt Identifier register.
axi_int_enables_offset : integer := 0; --! Defines the offset from axi_base_address for the Interrupt Enables register.
axi_int_active_offset : integer := 8; --! Defines the offset from axi_base_address for the Interrupt Active register.
-- Interrupt Controller parameters.
interrupt_total : integer := 8 --! Defines the number of available device interrupts.
);
port(
-- Global Interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- CPU interface.
cpu_int : out std_logic; --! CPU interrupt.
-- Device interface.
dev_ints : in std_logic_vector(interrupt_total-1 downto 0)); --! Device interrupts.
end plasoc_int;
architecture Behavioral of plasoc_int is
component plasoc_int_cntrl is
generic (
interrupt_total : integer := 8 );
port (
clock : in std_logic;
nreset : in std_logic;
cpu_int : out std_logic := '0';
cpu_int_id : out std_logic_vector(clogb2(interrupt_total) downto 0) := (others=>'0');
cpu_int_enables : in std_logic_vector(interrupt_total-1 downto 0);
cpu_int_active : out std_logic_vector(interrupt_total-1 downto 0);
dev_ints : in std_logic_vector(interrupt_total-1 downto 0));
end component;
component plasoc_int_axi4_read_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
int_id_address : std_logic_vector := X"0004";
int_enables_address : std_logic_vector := X"0000";
int_active_address : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
int_id : in std_logic_vector(axi_data_width-1 downto 0);
int_enables : in std_logic_vector(axi_data_width-1 downto 0);
int_active : in std_logic_vector(axi_data_width-1 downto 0));
end component;
component plasoc_int_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
int_enables_address : std_logic_vector := X"0000");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
int_enables : out std_logic_vector(axi_data_width-1 downto 0));
end component;
constant axi_int_id_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_int_id_offset,axi_address_width));
constant axi_int_enables_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_int_enables_offset,axi_address_width));
constant axi_int_active_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_int_active_offset,axi_address_width));
signal int_id : std_logic_vector(axi_data_width-1 downto 0);
signal int_enables : std_logic_vector(axi_data_width-1 downto 0);
signal int_active : std_logic_vector(axi_data_width-1 downto 0);
begin
int_id(axi_data_width-1 downto clogb2(interrupt_total)+1) <= (others=>'0');
int_active(axi_data_width-1 downto interrupt_total) <= (others=>'0');
plasoc_int_cntrl_inst :
plasoc_int_cntrl
generic map (
interrupt_total => interrupt_total )
port map (
clock => aclk,
nreset => aresetn,
cpu_int => cpu_int,
cpu_int_id => int_id(clogb2(interrupt_total) downto 0),
cpu_int_enables => int_enables(interrupt_total-1 downto 0),
cpu_int_active => int_active(interrupt_total-1 downto 0),
dev_ints => dev_ints);
plasoc_int_axi4_read_cntrl_inst :
plasoc_int_axi4_read_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
int_id_address => axi_int_id_offset_slv,
int_enables_address => axi_int_enables_offset_slv,
int_active_address => axi_int_active_offset_slv )
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
int_id => int_id,
int_enables => int_enables,
int_active => int_active);
plasoc_int_axi4_write_cntrl_inst :
plasoc_int_axi4_write_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
int_enables_address => axi_int_enables_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
int_enables => int_enables);
end Behavioral;
|
mit
|
27bc3bc3aaa02bc58c65f0d09777a7a4
| 0.556083 | 4.274915 | false | false | false | false |
tmeissner/cryptocores
|
cbcmac_des/rtl/vhdl/cbcmac_des.vhd
| 1 | 4,087 |
-- ======================================================================
-- CBC-MAC-DES
-- Copyright (C) 2015 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity cbcmac_des is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
key_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 tO 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end entity cbcmac_des;
architecture rtl of cbcmac_des is
component des is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic;
clk_i : in std_logic;
mode_i : in std_logic;
key_i : in std_logic_vector(0 to 63);
data_i : in std_logic_vector(0 to 63);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 63);
valid_o : out std_logic;
accept_i : in std_logic
);
end component des;
-- CBCMAC must have fix IV for security reasons
constant C_IV : std_logic_vector(0 to 63) := (others => '0');
signal s_des_datain : std_logic_vector(0 to 63);
signal s_des_dataout : std_logic_vector(0 to 63);
signal s_des_dataout_d : std_logic_vector(0 to 63);
signal s_des_key : std_logic_vector(0 to 63);
signal s_key : std_logic_vector(0 to 63);
signal s_des_accept : std_logic;
signal s_des_validout : std_logic;
begin
s_des_datain <= C_IV xor data_i when start_i = '1' else
s_des_dataout_d xor data_i;
data_o <= s_des_dataout;
s_des_key <= key_i when start_i = '1' else s_key;
accept_o <= s_des_accept;
valid_o <= s_des_validout;
inputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_key <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_des_accept = '1' and start_i = '1') then
s_key <= key_i;
end if;
end if;
end process inputregister;
outputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_des_dataout_d <= (others => '0');
elsif(rising_edge(clk_i)) then
if(s_des_validout = '1') then
s_des_dataout_d <= s_des_dataout;
end if;
end if;
end process outputregister;
i_des : des
generic map (
design_type => "ITER"
)
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => '0',
key_i => s_des_key,
data_i => s_des_datain,
valid_i => valid_i,
accept_o => s_des_accept,
data_o => s_des_dataout,
valid_o => s_des_validout,
accept_i => accept_i
);
end architecture rtl;
|
gpl-2.0
|
4fb2b5cda60351c651f79e5cc9e6eee7
| 0.545388 | 3.466497 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/AXI_DPTI_1.0/src/AXI_S_To_DPTI_Converter.vhd
| 1 | 9,740 |
------------------------------------------------------------------------------
--
-- File: AXI_S_to_DPTI_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module reads data from the AXI STREAM interface and sends it to the DPTI
-- interface. It will require a 32 bit TDATA bus, 4 bit TKEEP, TVALID and TLAST
-- as inputs and it will output the TREADY signal. It uses the DPTI clock of 60 MHz
-- to perform all the operations and it will use the maximum bandwidth of the DPTI
-- interface which is 480 mbps as long as valid data is received from the AXI STREAM
-- interface. In order to achieve this, FOR loops have been used which will generate
-- combinational logic that allows the simultaneous verification of all of the 4 TKEEP
-- bits received. Along with the DPTI clock, the module also reads the PROG_TXEN
-- signal and it will generate the PROG_D bus and PROG_WRN signal. In order to control
-- the module, two AXI Lite registers are used, one for direction/control and one for
-- the lenght of the transfer, which are synchronized in the top module.
-- The module also uses a reset signal aResetTx which is generated in the top module.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;
entity AXI_S_to_DPTI_converter is
Port (
-- clock, reset and DPTI signals
pResetTx : in std_logic;
PROG_CLK : in std_logic;
pTxe : in std_logic;
pWr : out std_logic;
pDataOut : out std_logic_vector (7 downto 0);
-- AXI Stream signals
pOutTready : out std_logic;
pInTdata : in std_logic_vector (31 downto 0);
pInTvalid : in std_logic;
pInTlast : in std_logic;
pInTkeep : in std_logic_vector (3 downto 0);
-- AXI Lite registers
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pTxLengthEmpty : out std_logic
);
end AXI_S_to_DPTI_converter;
architecture Behavioral of AXI_S_to_DPTI_converter is
--------------------------------------------------------------------------------------------------------------------------
signal pTxEnDir : std_logic := '0';
signal pLengthTxCnt : std_logic_vector (22 downto 0) := (others => '0');
signal Index : integer range 0 to 3;
signal pCtlOutTready : std_logic := '0';
signal pCtlWr : std_logic := '1';
signal pTransferInvalidFlag : std_logic := '1';
signal pAuxTdata : std_logic_vector(31 downto 0);
signal pAuxTkeep : std_logic_vector(3 downto 0) := (others => '0');
--------------------------------------------------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------------------------------------------------
pWr <= pCtlWr;
pOutTready <= pCtlOutTready;
--------------------------------------------------------------------------------------------------------------------------
pTxLengthEmpty <= '1' when pLengthTxCnt = 0 else '0'; -- we check to see if we are currently doing a tranfer. this will be a part of the AXI Lite status register
-- Generating TREADY signal which will request data from the AXI STREAM interface
pCtlOutTready <= '1' when (pAuxTkeep = "0001" or pAuxTkeep = "0010" or pAuxTkeep = "0100" or pAuxTkeep = "1000" or (pAuxTkeep = "0000" )) and pTxe = '0' and pLengthTxCnt > 0 else '0';
-- new data will be requested when we have at most one valid data byte in the current TDATA bus. other conditions are that a transfer must be in progress and the DPTI interface can accept more data
pTransferInvalidFlag <= '1' when pTxe = '1' and pCtlWr = '0' else '0'; -- detecting if a transfer has failed because the FT_TXE signal from FTDI was '1'
--------------------------------------------------------------------------------------------------------------------------
generate_WR: process (PROG_CLK, pLengthTxCnt, pResetTx) -- PROG_WRN is generated
begin
if rising_edge (PROG_CLK) then
if pResetTx = '0' then
pCtlWr <= '1';
else
if pAuxTkeep /= 0 and pLengthTxCnt > 0 then -- check if the transfer is not finnished and there is at least one valid data byte
pCtlWr <= '0'; -- when the signal is 0 then the byte currently on the PROG_D bus is valid
else -- if valid data is not available or the transfer is completed
pCtlWr <= '1'; -- PROG_WRN is '1'
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
read_Tkeep_and_Tdata: process (PROG_CLK, pResetTx)
variable aux_tkindex : integer;
begin
if rising_edge(PROG_CLK) then
if pResetTx = '0' then
aux_tkindex := 0;
pAuxTkeep <= (others => '0');
pAuxTdata <= (others => '0');
else
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- check to see if a transfer is in progress
if (pAuxTkeep = 0 or pAuxTkeep = 1 or pAuxTkeep = 2 or pAuxTkeep = 4 or pAuxTkeep = 8) and pInTvalid = '1' then -- check if the current set of TDATA and TKEEP contains at most one valid byte of data
pAuxTkeep <= pInTkeep; --new tkeep is read
pAuxTdata <= pInTdata; --new data is read
-- TDATA and TKEEP are used in the "generate_pDataOut" process below
else -- if more than one valid bytes exist
for Index in 3 downto 0 loop -- we use a FOR loop to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- each valid byte is identified by checking TKEEP
aux_tkindex := Index;
end if;
end loop;
pAuxTkeep(aux_tkindex) <= '0'; --reset one bit at a time after sending the corresponding valid byte to the DPTI interface
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pDataOut: process (PROG_CLK, pResetTx)
begin
if rising_edge(PROG_CLK) then
if pResetTx = '0' then
pDataOut <= (others => '0');
else
if pOvalidControl = '1' and pLengthTxCnt = 0 then -- the control bit (and the direction) can only be changed when the module is idle
pTxEnDir <= pAXI_L_Control(0); -- Reading control byte from AXI LITE register. Bit (0) sets the transfer's direction.
end if;
if pOvalidLength = '1' and pTxEnDir = '1' then -- checking if the module was enabled and if valid value is present in register
pLengthTxCnt (22 downto 0) <= pAXI_L_Length(22 downto 0); -- LENGTH register is read
end if;
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- conditions for starting transfer
for Index in 3 downto 0 loop -- the FOR loop allows us to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- we identify the valid byte's position
pDataOut(7 downto 0) <= pAuxTdata((8 * (Index + 1)) -1 downto (8 * (Index))); -- the valid byte is extracted and sent to the DPTI interface
pLengthTxCnt <= pLengthTxCnt - '1'; -- since one valid byte was transferred, length is decremented
end if;
end loop;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
end Behavioral;
|
bsd-3-clause
|
50064ff5ff4a1acb23ef9b53b0a28d5e
| 0.586242 | 4.669223 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vactcapofkplusone.vhd
| 1 | 1,748 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vactcapofkplusone is
port (
clock : in std_logic;
Vrefofkplusone : in std_logic_vector(31 downto 0);
Vrefcapofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vactcapofkplusone;
architecture struct of k_ukf_Vactcapofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_sub port map
( clock => clock,
dataa => Vrefofkplusone,
datab => Vrefcapofkplusone,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => Kofkplusone,
datab => Z1,
result => Z2);
M3 : k_ukf_add port map
( clock => clock,
dataa => Vactcapdashofkplusone,
datab =>Z2,
result => Vactcapofkplusone);
end struct;
|
gpl-2.0
|
eab2329fbfac8b2474227b87d007e003
| 0.608124 | 3.249071 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_cpu.vhd
| 1 | 26,726 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 17, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's CPU.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.plasoc_cpu_pack.all;
--! The 32-bit CPU of the Plasma-SoC comprises only the original
--! Plasma Mlite CPU developed by Steve Rhoads, configurable cache,
--! and AXI controllers to implement the AXI4-Full interface needed to
--! communicate with peripherals in the Plasma-SoC and those external.
--!
--! In a later revision on this documentation, more information will be
--! added to describe the features implemented in the AXI4-Full interface
--! and the capabilities of the cache. Information specific to the AXI4-Full
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_cpu is
generic(
-- CPU parameters.
cpu_mult_type : string := default_cpu_mult_type; --! Defines the Plasma Mlite multiplier type. The possible options are "DEFAULT" and "AREA_OPTIMIZED".
cpu_shifter_type : string := default_cpu_shifter_type; --! Defines the Plasma Mlite shifter type. The possible options are "DEFAULT" and "AREA_OPTIMIZED".
cpu_alu_type : string := default_cpu_alu_type; --! Defines the Plasma Mlite ALU type. The possible options are "DEFAULT" and "AREA_OPTIMIZED".
-- Cache parameters.
cache_address_width : integer := default_cache_address_width; --! Defines the address width of the cacheable addresses.
cache_way_width : integer := default_cache_way_width; --! Associativity = 2^cache_way_width.
cache_index_width : integer := default_cache_index_width; --! Cache Size (rows) = 2^cache_index_width.
cache_offset_width : integer := default_cache_offset_width; --! Line Size (bytes) = 2^cache_offset_width.
cache_replace_strat : string := default_cache_replace_strat; --! Defines the replacement strategy in case of miss. Only "plru" is available.
cache_enable : boolean := default_cache_enable; --! Defines whether or not the cache is enabled.
oper_base : std_logic_vector := default_oper_base; --! Defines the base address of the cache flush and invalidate operations. Based address is this case is only defined by its most significant bits.
oper_invalidate_offset : integer := default_oper_invalidate_offset; --! Defines the offset from the base address of the invalidation operation.
oper_flush_offset : integer := default_oper_flush_offset --! Defines the offset from the base address of the flush operation.
);
port(
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Master AXI4-Full Write interface.
axi_awid : out std_logic_vector(-1 downto 0); --! AXI4-Full Address Write signal.
axi_awaddr : out std_logic_vector(31 downto 0); --! AXI4-Full Address Write signal.
axi_awlen : out std_logic_vector(7 downto 0); --! AXI4-Full Address Write signal.
axi_awsize : out std_logic_vector(2 downto 0); --! AXI4-Full Address Write signal.
axi_awburst : out std_logic_vector(1 downto 0); --! AXI4-Full Address Write signal.
axi_awlock : out std_logic; --! AXI4-Full Address Write signal.
axi_awcache : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awprot : out std_logic_vector(2 downto 0); --! AXI4-Full Address Write signal.
axi_awqos : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awregion : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awvalid : out std_logic; --! AXI4-Full Address Write signal.
axi_awready : in std_logic; --! AXI4-Full Address Write signal.
axi_wdata : out std_logic_vector(31 downto 0); --! AXI4-Full Write Data signal.
axi_wstrb : out std_logic_vector(3 downto 0); --! AXI4-Full Write Data signal.
axi_wlast : out std_logic; --! AXI4-Full Write Data signal.
axi_wvalid : out std_logic; --! AXI4-Full Write Data signal.
axi_wready : in std_logic; --! AXI4-Full Write Data signal.
axi_bid : in std_logic_vector(-1 downto 0); --! AXI4-Full Write Response signal.
axi_bresp : in std_logic_vector(1 downto 0); --! AXI4-Full Write Response signal.
axi_bvalid : in std_logic; --! AXI4-Full Write Response signal.
axi_bready : out std_logic; --! AXI4-Full Write Response signal.
-- Master AXI4-Full Read interface.
axi_arid : out std_logic_vector(-1 downto 0); --! AXI4-Full Address Read signal.
axi_araddr : out std_logic_vector(31 downto 0); --! AXI4-Full Address Read signal.
axi_arlen : out std_logic_vector(7 downto 0); --! AXI4-Full Address Read signal.
axi_arsize : out std_logic_vector(2 downto 0); --! AXI4-Full Address Read signal.
axi_arburst : out std_logic_vector(1 downto 0); --! AXI4-Full Address Read signal.
axi_arlock : out std_logic; --! AXI4-Full Address Read signal.
axi_arcache : out std_logic_vector(3 downto 0); --! AXI4-Full Address Read signal.
axi_arprot : out std_logic_vector(2 downto 0); --! AXI4-Full Address Read signal.
axi_arqos : out std_logic_vector(3 downto 0); --! AXI4-Full Address Read signal.
axi_arregion : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_arvalid : out std_logic; --! AXI4-Full Address Read signal.
axi_arready : in std_logic; --! AXI4-Full Address Read signal.
axi_rid : in std_logic_vector(-1 downto 0); --! AXI4-Full Read Data signal.
axi_rdata : in std_logic_vector(31 downto 0); --! AXI4-Full Read Data signal.
axi_rresp : in std_logic_vector(1 downto 0); --! AXI4-Full Read Data signal.
axi_rlast : in std_logic; --! AXI4-Full Read Data signal.
axi_rvalid : in std_logic; --! AXI4-Full Read Data signal.
axi_rready : out std_logic; --! AXI4-Full Read Data signal.
-- CPU signals.
intr_in : in std_logic --! External interrupt.
);
end plasoc_cpu;
architecture Behavioral of plasoc_cpu is
-- Component declarations.
component plasoc_cpu_l1_cache_cntrl is
generic (
cpu_address_width : integer := 32;
cpu_data_width : integer := 32;
cache_cacheable_width : integer := 16;
cache_way_width : integer := 1;
cache_index_width : integer := 4;
cache_offset_width : integer := 5;
cache_policy : string := "plru";
oper_base : std_logic_vector := X"200000"; -- msb
oper_invalidate_offset : std_logic_vector := X"00";
oper_flush_offset : std_logic_vector := X"04");
port (
clock : in std_logic;
resetn : in std_logic;
cpu_next_address : in std_logic_vector(cpu_address_width-1 downto 0);
cpu_write_data : in std_logic_vector(cpu_data_width-1 downto 0);
cpu_write_enables : in std_logic_vector(cpu_data_width/8-1 downto 0);
cpu_read_data : out std_logic_vector(cpu_data_width-1 downto 0);
cpu_pause : out std_logic;
memory_write_address : out std_logic_vector(cpu_address_width-1 downto 0);
memory_write_data : out std_logic_vector(cpu_data_width-1 downto 0);
memory_write_enable : out std_logic;
memory_write_enables : out std_logic_vector(cpu_data_width/8-1 downto 0);
memory_write_valid : out std_logic;
memory_write_ready : in std_logic;
memory_read_address : out std_logic_vector(cpu_address_width-1 downto 0);
memory_read_enable : out std_logic;
memory_read_data: in std_logic_vector(cpu_data_width-1 downto 0);
memory_read_valid : in std_logic;
memory_read_ready : out std_logic;
memory_cacheable : out std_logic);
end component;
component plasoc_cpu_mem_cntrl is
generic (
cpu_address_width : integer := 16;
cpu_data_width : integer := 32);
port (
clock : in std_logic;
resetn : in std_logic;
cpu_address : in std_logic_vector(cpu_address_width-1 downto 0);
cpu_in_data : in std_logic_vector(cpu_data_width-1 downto 0);
cpu_out_data : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0');
cpu_strobe : in std_logic_vector(cpu_data_width/8-1 downto 0);
cpu_pause : out std_logic;
cache_cacheable : out std_logic;
mem_in_address : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0');
mem_in_data : in std_logic_vector(cpu_data_width-1 downto 0);
mem_in_enable : out std_logic;
mem_in_valid : in std_logic;
mem_in_ready : out std_logic;
mem_out_address : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0');
mem_out_data : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0');
mem_out_strobe : out std_logic_vector(cpu_data_width/8-1 downto 0) := (others=>'0');
mem_out_enable : out std_logic := '0';
mem_out_valid : out std_logic;
mem_out_ready : in std_logic);
end component;
component plasoc_cpu_axi4_read_cntrl is
generic (
cpu_address_width : integer := 16;
cpu_data_width : integer := 32;
cache_offset_width : integer := 5;
axi_aruser_width : integer := 0;
axi_ruser_width : integer := 0);
port(
clock : in std_logic;
nreset : in std_logic;
mem_read_address : in std_logic_vector(cpu_address_width-1 downto 0);
mem_read_data : out std_logic_vector(cpu_data_width-1 downto 0);
mem_read_enable : in std_logic;
mem_read_valid : out std_logic;
mem_read_ready : in std_logic;
cache_cacheable : in std_logic;
axi_arid : out std_logic_vector(-1 downto 0);
axi_araddr : out std_logic_vector(cpu_address_width-1 downto 0);
axi_arlen : out std_logic_vector(7 downto 0);
axi_arsize : out std_logic_vector(2 downto 0);
axi_arburst : out std_logic_vector(1 downto 0);
axi_arlock : out std_logic;
axi_arcache : out std_logic_vector(3 downto 0);
axi_arprot : out std_logic_vector(2 downto 0);
axi_arqos : out std_logic_vector(3 downto 0);
axi_arregion : out std_logic_vector(3 downto 0);
axi_aruser : out std_logic_vector(axi_aruser_width-1 downto 0);
axi_arvalid : out std_logic;
axi_arready : in std_logic;
axi_rid : in std_logic_vector(-1 downto 0);
axi_rdata : in std_logic_vector(cpu_data_width-1 downto 0);
axi_rresp : in std_logic_vector(1 downto 0);
axi_rlast : in std_logic;
axi_ruser : in std_logic_vector(axi_ruser_width-1 downto 0);
axi_rvalid : in std_logic;
axi_rready : out std_logic;
error_data : out std_logic_vector(3 downto 0) := (others=>'0') );
end component;
component plasoc_cpu_axi4_write_cntrl is
generic(
cpu_address_width : integer := 16;
cpu_data_width : integer := 32;
cache_offset_width : integer := 5;
axi_awuser_width : integer := 0;
axi_wuser_width : integer := 0;
axi_buser_width : integer := 0);
port(
clock : in std_logic;
nreset : in std_logic;
mem_write_address : in std_logic_vector(cpu_address_width-1 downto 0);
mem_write_data : in std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0');
mem_write_strobe : in std_logic_vector(cpu_data_width/8-1 downto 0);
mem_write_enable : in std_logic;
mem_write_valid : in std_logic;
mem_write_ready : out std_logic;
cache_cacheable : in std_logic;
axi_awid : out std_logic_vector(-1 downto 0);
axi_awaddr : out std_logic_vector(cpu_address_width-1 downto 0);
axi_awlen : out std_logic_vector(7 downto 0);
axi_awsize : out std_logic_vector(2 downto 0);
axi_awburst : out std_logic_vector(1 downto 0);
axi_awlock : out std_logic;
axi_awcache : out std_logic_vector(3 downto 0);
axi_awprot : out std_logic_vector(2 downto 0);
axi_awqos : out std_logic_vector(3 downto 0);
axi_awregion : out std_logic_vector(3 downto 0);
axi_awuser : out std_logic_vector(axi_awuser_width-1 downto 0);
axi_awvalid : out std_logic;
axi_awready : in std_logic;
axi_wdata : out std_logic_vector(cpu_data_width-1 downto 0);
axi_wstrb : out std_logic_vector(cpu_data_width/8-1 downto 0);
axi_wlast : out std_logic;
axi_wuser : out std_logic_vector(axi_wuser_width-1 downto 0);
axi_wvalid : out std_logic;
axi_wready : in std_logic;
axi_bid : in std_logic_vector(-1 downto 0);
axi_bresp : in std_logic_vector(1 downto 0);
axi_buser : in std_logic_vector(axi_buser_width-1 downto 0);
axi_bvalid : in std_logic;
axi_bready : out std_logic;
error_data : out std_logic_vector(2 downto 0) := (others=>'0'));
end component;
-- Constants and type definitions.
constant cpu_width : integer := 32;
constant cpu_memory_type : string := "DUAL_PORT_";
constant cpu_pipeline_stages : natural := 3;
constant cache_tag_width : integer := cache_address_width-cache_index_width-cache_offset_width;
constant cache_word_offset_width : integer := cache_offset_width-clogb2(cpu_width/8);
constant cache_line_width : integer := (cache_tag_width+8*2**cache_offset_width);
constant oper_offset_width : integer := cpu_width-oper_base'length;
constant oper_invalidate_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(oper_invalidate_offset,oper_offset_width));
constant oper_flush_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(oper_flush_offset,oper_offset_width));
constant axi_user_width : integer := 1;
subtype cache_index_type is std_logic_vector(cache_index_width-1 downto 0);
subtype cache_data_type is std_logic_vector(cache_line_width*2**cache_way_width-1 downto 0);
subtype cache_write_block_enable_type is std_logic_vector(2**(cache_way_width+cache_word_offset_width)-1 downto 0);
-- CPU interface signals.
signal cpu_write_data : std_logic_vector(cpu_width-1 downto 0);
signal cpu_read_data : std_logic_vector(cpu_width-1 downto 0);
signal cpu_address_next : std_logic_vector(cpu_width-1 downto 0);
signal cpu_strobe_next : std_logic_vector(cpu_width/8-1 downto 0);
signal cpu_pause : std_logic;
-- Cache interface signals.
signal cache_write_index : cache_index_type;
signal cache_write_data : cache_data_type := (others=>'0');
signal cache_write_tag_enable : std_logic_vector(2**cache_way_width-1 downto 0);
signal cache_write_block_enable : cache_write_block_enable_type;
signal cache_read_index : cache_index_type;
signal cache_read_data :cache_data_type := (others=>'0');
signal cache_cacheable : std_logic;
-- Memory interface signals
signal mem_in_address : std_logic_vector(cpu_width-1 downto 0);
signal mem_in_data : std_logic_vector(cpu_width-1 downto 0);
signal mem_in_enable : std_logic;
signal mem_in_valid : std_logic;
signal mem_in_ready : std_logic;
signal mem_out_address : std_logic_vector(cpu_width-1 downto 0);
signal mem_out_data : std_logic_vector(cpu_width-1 downto 0);
signal mem_out_strobe : std_logic_vector(cpu_width/8-1 downto 0);
signal mem_out_enable : std_logic;
signal mem_out_valid : std_logic;
signal mem_out_ready : std_logic;
-- Attributes.
-- attribute keep : boolean;
-- attribute keep of cpu_write_data : signal is true;
-- attribute keep of cpu_read_data : signal is true;
-- attribute keep of cpu_address_next : signal is true;
-- attribute keep of cpu_strobe_next : signal is true;
-- attribute keep of cpu_pause : signal is true;
-- attribute keep of cache_cacheable : signal is true;
-- attribute keep of mem_in_address : signal is true;
-- attribute keep of mem_in_data : signal is true;
-- attribute keep of mem_in_enable : signal is true;
-- attribute keep of mem_in_valid : signal is true;
-- attribute keep of mem_in_ready : signal is true;
-- attribute keep of mem_out_address : signal is true;
-- attribute keep of mem_out_data : signal is true;
-- attribute keep of mem_out_strobe : signal is true;
-- attribute keep of mem_out_enable : signal is true;
-- attribute keep of mem_out_valid : signal is true;
-- attribute keep of mem_out_ready : signal is true;
-- -- debug
-- signal debug_task_main_code : Boolean;
-- signal debug_task_input_code : Boolean;
-- signal debug_task_time_code : Boolean;
-- signal debug_interrupt : Boolean;
-- signal debug_write : Boolean;
-- attribute mark_debug : boolean;
-- attribute mark_debug of aclk : signal is true;
-- attribute mark_debug of aresetn : signal is true;
-- attribute mark_debug of cpu_write_data : signal is true;
-- attribute mark_debug of cpu_read_data : signal is true;
-- attribute mark_debug of cpu_address_next : signal is true;
-- attribute mark_debug of cpu_strobe_next : signal is true;
-- attribute mark_debug of intr_in : signal is true;
begin
cpu_address_next(1 downto 0) <= "00";
-- CPU instantiation.
mlite_cpu_inst:
mlite_cpu
generic map (
memory_type => cpu_memory_type,
mult_type => cpu_mult_type,
shifter_type => cpu_shifter_type,
alu_type => cpu_alu_type,
pipeline_stages => cpu_pipeline_stages )
port map (
clk => aclk,
reset_in => "not" (aresetn),
intr_in => intr_in,
address_next => cpu_address_next(cpu_width-1 downto 2),
byte_we_next => cpu_strobe_next,
address => open,
byte_we => open,
data_w => cpu_write_data,
data_r => cpu_read_data,
mem_pause => cpu_pause );
-- If cache is enabled, instantiate controller and buffer.
gen_cache :
if cache_enable=True generate
-- Cache controller instantiation.
plasoc_cpu_l1_cache_cntrl_inst :
plasoc_cpu_l1_cache_cntrl
generic map (
cpu_address_width => cpu_width,
cpu_data_width => cpu_width,
cache_cacheable_width => cache_address_width,
cache_way_width => cache_way_width,
cache_index_width => cache_index_width,
cache_offset_width => cache_offset_width,
cache_policy => cache_replace_strat,
oper_base => oper_base,
oper_invalidate_offset => oper_invalidate_offset_slv,
oper_flush_offset => oper_flush_offset_slv)
port map (
clock => aclk,
resetn => aresetn,
cpu_next_address => cpu_address_next,
cpu_write_data => cpu_write_data,
cpu_write_enables => cpu_strobe_next,
cpu_read_data => cpu_read_data,
cpu_pause => cpu_pause,
memory_write_address => mem_out_address,
memory_write_data => mem_out_data,
memory_write_enable => mem_out_enable,
memory_write_enables => mem_out_strobe,
memory_write_valid => mem_out_valid,
memory_write_ready => mem_out_ready,
memory_read_address => mem_in_address,
memory_read_enable => mem_in_enable,
memory_read_data => mem_in_data,
memory_read_valid => mem_in_valid,
memory_read_ready => mem_in_ready,
memory_cacheable => cache_cacheable);
end generate;
-- If cache is disabled, instantiate memory controller.
gen_no_cache :
if cache_enable=False generate
-- Memory controller instantiation.
plasoc_cpu_mem_cntrl_inst :
plasoc_cpu_mem_cntrl
generic map (
cpu_address_width => cpu_width,
cpu_data_width => cpu_width )
port map (
clock => aclk,
resetn => aresetn,
cpu_address => cpu_address_next,
cpu_in_data => cpu_write_data,
cpu_out_data => cpu_read_data,
cpu_strobe => cpu_strobe_next,
cpu_pause => cpu_pause,
cache_cacheable => cache_cacheable,
mem_in_address => mem_in_address,
mem_in_data => mem_in_data,
mem_in_enable => mem_in_enable,
mem_in_valid => mem_in_valid,
mem_in_ready => mem_in_ready,
mem_out_address => mem_out_address,
mem_out_data => mem_out_data,
mem_out_strobe => mem_out_strobe,
mem_out_enable => mem_out_enable,
mem_out_valid => mem_out_valid,
mem_out_ready => mem_out_ready);
end generate;
-- axi write controller.
plasoc_cpu_axi4_write_cntrl_inst :
plasoc_cpu_axi4_write_cntrl
generic map (
cpu_address_width => cpu_width,
cpu_data_width => cpu_width,
cache_offset_width => cache_offset_width,
axi_awuser_width => axi_user_width,
axi_wuser_width => axi_user_width,
axi_buser_width => axi_user_width)
port map (
clock => aclk,
nreset => aresetn,
mem_write_address => mem_out_address,
mem_write_data => mem_out_data,
mem_write_strobe => mem_out_strobe,
mem_write_enable => mem_out_enable,
mem_write_valid => mem_out_valid,
mem_write_ready => mem_out_ready,
cache_cacheable => cache_cacheable,
axi_awid => axi_awid,
axi_awaddr => axi_awaddr,
axi_awlen => axi_awlen,
axi_awsize => axi_awsize,
axi_awburst => axi_awburst,
axi_awlock => axi_awlock,
axi_awcache => axi_awcache,
axi_awprot => axi_awprot,
axi_awqos => axi_awqos,
axi_awregion => axi_awregion,
axi_awuser => open,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_wlast => axi_wlast,
axi_wuser => open,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_bid => axi_bid,
axi_bresp => axi_bresp,
axi_buser => (others=>'0'),
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
error_data => open);
-- axi read controller.
plasoc_cpu_axi4_read_cntrl_inst :
plasoc_cpu_axi4_read_cntrl
generic map (
cpu_address_width => cpu_width,
cpu_data_width => cpu_width,
cache_offset_width => cache_offset_width,
axi_aruser_width => axi_user_width,
axi_ruser_width => axi_user_width)
port map (
clock => aclk,
nreset => aresetn,
mem_read_address => mem_in_address,
mem_read_data => mem_in_data,
mem_read_enable => mem_in_enable,
mem_read_valid => mem_in_valid,
mem_read_ready => mem_in_ready,
cache_cacheable => cache_cacheable,
axi_arid => axi_arid,
axi_araddr => axi_araddr,
axi_arlen => axi_arlen,
axi_arsize => axi_arsize,
axi_arburst => axi_arburst,
axi_arlock => axi_arlock,
axi_arcache => axi_arcache,
axi_arprot => axi_arprot,
axi_arqos => axi_arqos,
axi_arregion => axi_arregion,
axi_aruser => open,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rid => axi_rid,
axi_rdata => axi_rdata,
axi_rresp => axi_rresp,
axi_rlast => axi_rlast,
axi_ruser => (others=>'0'),
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
error_data => open);
end Behavioral;
|
mit
|
9bba690cca743072b0a6f7ece563a558
| 0.556125 | 3.998504 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/io/mem.vhdl
| 1 | 6,542 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.memory_map.all;
use work.txt_utils.all;
use work.utils.all;
entity mem is
generic (ROM : string := ""; RAMSIZE : positive := 32);
port(
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic;
-- VGA I/O
vgaclk, rst : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic;
-- LEDs
leds : out std_logic_vector(7 downto 0);
-- Push buttons
buttons : in std_logic_vector(3 downto 0);
-- DIP Switch IO
switch : in std_logic_vector(7 downto 0)
);
end mem;
architecture struct of mem is
component addrdec is
port( A : in addr_t;
cs : out memchipsel_t);
end component;
component rom_default is port (a: in addr_t; z: out word_t; en: in ctrl_t); end component;
component rom_vga is port (a: in addr_t; z: out word_t; en: in ctrl_t); end component;
signal cs : memchipsel_t;
signal instr : instruction_t;
component async_ram is
generic (
MEMSIZE :integer := RAMSIZE
);
port (
address : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
en : in std_logic
);
end component;
component mmio_vga is
port(
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
memclk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- VGA I/O
vgaclk, rst : in std_logic;
r, g, b : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic
);
end component;
component mmio_leds is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- leds
leds : out std_logic_vector(7 downto 0)
);
end component;
component mmio_buttons is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- push buttons
buttons : in std_logic_vector(3 downto 0)
);
end component;
component mmio_tsc is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE
);
end component;
component mmio_dipswitch is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- dip switch
switch : in std_logic_vector(7 downto 0)
);
end component;
signal vga_en : ctrl_t := '0';
begin
addrdec_instance : addrdec port map(addr, cs);
vga_rom_selector: if ROM = "VGA" or ROM = "vga" generate
begin
instruction_mem : rom_vga
port map(addr, dout, cs(mmap_rom));
end generate;
default_rom_selector: if ROM = "" generate
begin
instruction_mem : rom_default
port map(addr, dout, cs(mmap_rom));
end generate;
-- It's possible that this isn't interferrable. If so, maybe use synchronous RAM instead?
working_ram : async_ram
port map(address => addr,
din => din,
dout => dout,
size => size,
wr => wr,
en => cs(mmap_ram)
);
vga_en <= cs(mmap_vram) or cs(mmap_videocfg);
vga : mmio_vga
port map(addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
en => vga_en,
memclk => clk,
trap => open,
vgaclk => vgaclk,
rst => rst,
r => r, g => g, b => b,
hsync => hsync, vsync => vsync
);
ledbank: mmio_leds
port map(addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
en => cs(mmap_led),
clk => clk,
trap => open,
leds => leds
);
pushbuttons : mmio_buttons
port map(addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
en => cs(mmap_push),
clk => clk,
trap => open,
buttons => buttons
);
timestamp_counter : mmio_tsc
port map(addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
en => cs(mmap_tsc),
clk => clk,
trap => open
);
dipswitch: mmio_dipswitch
port map(addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
en => cs(mmap_dipswitch),
clk => clk,
trap => open,
switch => switch
);
end struct;
|
gpl-3.0
|
f6a5e78fc4de8179144e8c8b6e323fcd
| 0.436564 | 4.076012 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_afifo_autord.vhd
| 4 | 16,838 |
-------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_Rd_clk or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
bsd-3-clause
|
c2909f67d24f7a9e9d20ef5d0e2d390c
| 0.441739 | 4.517843 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd
| 1 | 8,323 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
M8m8SbudzV/u5DcxeEdhEDdsLYqwaBIIJiezrfYIfFLCt0ZI62S6lZK7iuU9o7lX8obgf+U/1XjH
Au1G5FmtUQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pgNHFX7E6PTDvduKUXwYlAz9/y1Lz2z0rrcw6YT4ZUQb9QXMmvjLv4TbL2hl5It7ir1N5nwOlAfn
tiRuYOo8buApBa4LpQqzwSUxr2vAaA3yX3pZvvqrvO1yo1yTfBwkAbkq3Ojgu2z1aFK79DEWWV8n
DjwJegBabRFpqsyL7g8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qVvVtz+Rbj/eRtvQwigKyYx5Z5TCACaVOi/Ff3hhEdY7ZZ2QVc2j0VdqpIA24Dw3DxP8hlu7dJ9x
e0UroiVB+z25/Tghmspnp0jFEo1J7WYVzcV6/5m3vi05zVEmW0ErhD9X4soFn6c+MTqlvpqJmMJL
gr2wm3EHhgdTsvk2L9WUDB/Rszgwfo7ZlWLrJEQoQl6Qky0ATgsCHREj9JOKdXzNBhrneURO/UEb
l3Tcuoez7giBDjTpbXlHWln834LH1zsoo2yYeI7R9aKcij95dSRH+H+x/rkXoE9+VaoTp1Tuaa39
cg1mJdSZi2zuUlH0C64+CVndO6I0nMsQ4E6vkQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sEdi5PdnDKq4BOTdbtFe1j8Tre/9uSBdd4r1Sk1qq7Zi15j/EYoSq/FdHn99EGBzq3Kxob1wSSi+
a8/qH8QArTcs89YDcezxvbMvtT2UD/2aQWSWjbJ02VY0QpbsRq1/lhG8KSIGTsYjlJMqDsRFnF/2
21bXdThcSfpG01yJcsw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HDWJppRUBA3kguo2Waqdo0VGANwSyok6Mo1GPJ6eXWHISYETQMA5GCZ1TxdWMJQetBGtOHbaynMZ
mnttDSv+53qOOmzPmXX+D62PfHKcn73nDljliaElKvEe/CDvPX5EzLCPIXQdXADRVOFfeV27LXLv
nhhWkqDN1/0tgFC60wLMAK5FF+FPZZhVyp/1malSCLksiU/qZST4MSWtkuWwtEny1qlaUKAfqxMz
Sfxgoz8z5/0l0twVyaAB8OyspRaLQAYbaDIaCSJGOZSp1qNsx5NVFYPeWl2T0G3LYUmOAa2r+bS4
QPGdwUVkOmxHG7adhzY9sPKoSj9HO8kJtyAq+g==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
HCkru9FaRpb6s7B4t5YO4lUvoDtt1FDt69fVea4UPRZiKCzHzzkWlxc6lDYC6SaRafQrkDwhXPLl
vrWIqZfI8Ovcncor0tnIZSfmU6huZ6FC+/xljLH7aZjx4Rc/QMkvJRxfXKxUjesYAsiB0VLtVab+
SDd5uAIwPA9hRtGacu/c/BuZwkwmcM5YSVDnDzkLDrQnO3+SvI4XFNoUVVvWNt7Eh7yt1/56rj6D
xTzMZN5ABYRaIXR9W8IbJ/PKVPTIoCSWrL94Vj6qHuKFGqVIJgz0nhoKJHhZxubs7aJsBFmlcCLj
DydemH8lSn0hdAVeyutLcElxPBqWIQ0npZl0sw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
OTk1W6UzwUQkX83ieGsl2wk2NoNV9A7KlCSwLwDCBn7uLE/JiWOFovyLBF6Z+TftVJRepdx60Wl0
9G4Jdzw4pp4iKIcA80O1IqEPrKtJ0KhPQKJXRLZvDYgEGKcYkwSwZikxEHjqNxPbOwxrA7eRqQPo
GoZw/pdbh+5zp/Gf54LfYTHt75tb7w4xEiFy/p9aIJX5QlVtd2tfMv3uTdbFUfyvxcc05ZHvd0SV
O2TXppppLpGAp5MX8Vda333m0Wb+xxDqX3sDd+yuljQLYH6HLdT1oMNPasjrvcU3UQ4zfPTTMMpS
21bpjYAWRLTzQC99QQLPrMSoOZhKxBQSJQqX8SbGpRlqyfxL4ulNARf6gUmGKf0rI9cDirIjAUgo
DGW2fSCNuZ9QL/DsBnHTAp2Aar3nPfUufpXDstmTZ6bTrtjW2bsP4wX/sa2LVCdbT85dosMHS5Fk
DRl+f0kQ30WlfT/d7+cE/EXuMLIKPhKQO/AP8lD3mEbGeAZf9oy0o42xXSU8Kz6jJ33e5qpnIXqD
WGksH8fH5loinWCswppEVDvFSswx5X9LAXERwiWDwMYm3N/fNir3xhsVRc2iYwqo7j5QSBITUmV7
Kp3UHwyOG9gPgxbe8M36OeQguw1muspZUFaejILxFGED3v65JyDVbr4WhjLjpHD73cdVT/Jg1VpX
8LCF0/o82IOt+NX914PgFwYplrVGGX+Snjlc5xSbb6H7GUdJD44nf/j5yp/LaAaMcV5vZFg2wZpE
vlK8EBgBdkm3h9UPhOC0fNUI5prFv499212qQpqSChcKSqtOGy1VflJkmz5zPK4S9KR0dCpJG2zo
Xk3vpYHxcKJ1mqLmsW1c0DMYy2UQk55ZmQS4/Iy3PLkJo2gdwib4yVQRK+e7pgC9rcKCXni03eAT
r3YkOmdMGI8J9V9VS6MVsjTz54a5K7R/bE4Nvn/wUz21EMY4lszqqui5SigBBA1Wo3y7Qe+kDNnV
1GCS1MiwwSjury14qrB8y71dukOgHwlxoMHaYUk7mvS344uLeErhQs/1LpUlL5E9Fam0vYhl8ciS
B7Y37S74WCVuv7rNi3V5weRFXNDqO2iyI6wexAFvTEjatZQMZpM2IhgtxNnlzqcxstFz89urPjle
HmTL1JEPhJ+vnVZOWRrhFzaqZdjC8N1NdXYwvcUW3c4xUmkgbMPonwmTTN0YJbiiToxJZqK/EOqo
/tBF+DxLntqXgzoFrRjTp/AcN7beKDExEBRLsg97s9qP2oDuWFGJG7UPfCMsla+uds5cv8pj4wwi
k0UiRnawuSKVOxOiV7XF2NOw2Aq6u5ylJM0jKqwpb2RLoRWhLbOsDDaxIiSDTBPOkIXvHQ2nXUli
GnaRYwnKBdNe2PVOdL/YAwcvT+YZ35PE/Ibs/4pAv0Ge1cQkkmw3qoP944xHAS6GzxCcIJ2lCQ46
HDUOet+SMuRPAxgETTnGiC/ZhuLhAqiyGW1OHlU8dTq155Nu5bdqtTyGxQr7tkEV158bWMBeaRZQ
HufiEEDa0uuRgA3NImTJegI+pm4BJaiMx7lygR/ZX99fp+MKES7zG30ALUXVRHnn0QQnlRhFHwve
5v0Y/yzKcCvJYYRB4cQ76NtLIFEA9ItVtU0crnYzVNjIXm/VQzWTILrswYRjESaL7muMQAgeEQ6b
fDtC7E4XO9OQ5a4DKfwdQqePoCO4BGQKYFFDdqsvw8ACtZrHKhkHBwsOKcRTjGJXdk6T3f0Dd7cD
oZx+6MXAzy/g2trZ/C7d/tkZTx+d+F7Cu/2UNsAw4XajmEJOD0vecmIZfFHBn08A+RBs9wHx2tqC
sE+dIgWhwzDSaEorkzx1SKFf1sg2gxqzYYknIht8W1vfgz8tGJ16X/G4bpAKqVgSbTKU7yW5PvEn
wdcwXDTjBn0h2qpRyfCAhVd6kpB5FIaynZ9WVkwOdmSV7V9nWzdqFaly6qJWzlYHANIvvqGQWud3
yxp0Ug3LtLtV/9e0MvAApGTLRCgkkqCQtHlI9Kk524Aj0jd+TsdJuGDuXc8uOGmiC167NpNMWfVD
/pjmx1xh5pbXQQPtFBP/LnsIY1bVHsJ/GIh4qakJYPZk5A+TKmAon6T6T6hM/XcoBTEl9a27FdOT
Xm907OCfx9IBwfF+gGw2fXycqf9LqfsUr78cpkmGrw2ESWoBJKMVhPuvbIlX5//yVqlHHXtJZg98
1zH0zMn2IYQyOUEFYPDszNSdp1Xff8hC8l90SkYpYd/yO1l7yUVWKVGU4fV9rxAbTyxuW8Y/s2Be
vmvaG5TuI//L4E/DuYctOFIk1yak66oFzntIDu7trF0nl0tCtvsHUHgIpzU3Mh+cNO53TpRnyVpQ
GleNCDx48+wJ+vkoGtH9A4hiL5A/wrG5pl+Mvu/qjtZHMLbj/DD8c2McMooJHWqxEyXAUdgr3o2c
KX95czRbDLHXQsCZQsINJWJX88lRr9DSz5pyu11PlKms12ZiDUwc7y7fXEKPNkUgguZ94icXcztg
ed1l6c9JPwHQ1N8K2+kQ8jhmIip8rmwnHbBUWyRiAGZqSBzbhVHaYXtYAI15RAQEIw6N8HbyjK8i
i8yy+vRGntvj0XIOptKNIwYPE7K5IaeeuPKf+KxnrlOeKK3MjtdO3idrrPUbn2lpcOW/lpgsK/8b
k9UZf/gt0f+3KSR7FBbqb/EfGY0R+lCqAUGwi9BQClfb94iWM7niyChjLzvUOlTLr6G1018L+UuU
MncABot9h8/71jvD4X4WCOZBErIcS4c7XrzFgn5I7Cvp/ZhLSTbCmf0N2e8gdKpb6twVZ/KSxq08
MInYvhn4+jK4YYnfB58zGAzh4KTMdzFAGSO77pAtNRC8HkeD36KqZxB/prteXpa8aKgqNSxUtxgg
uJcPcsofs8S/s5X3eQh3g2LxVRGdrbKpYY2mVyjx9qEwadV+f9+BNfmYt/3FGgOVjTzeTxHQtXzV
hE60tNDgsD4pHXknLzvaJbQs9z/YIKg1xkjKhhmhhab43QCEqbde1hBY6s6s/5dZqZ3r3y0c+YAC
4+qp7Hn5FfMbv/jGulN6fC7kYKovA/64Op7AgqUABuHL4fmlS1xwUkP4Aj3+OUXr/UVcbPaQAKAI
+7lXAC3wyt5RNLsxGl0Hj6UaRDX++Ie9jcotUHFOgZ9LYNjyNk5l7nsrdySKwI3qyC9e3xrD266+
//E01+BGL5u8s6OzeZpOC1WaUq7dfhi4Eseyw8E0MwjmgiorsrNhc0+lZShNgL8s1Uac5g7MKB7M
qNfzO405Rj2jUKx6PSFlxJfMFiExUOSGfDWC3ITe70NMS2QqNLw7MTe/KodWVcwPVbqjppvpd0ww
CvoXphRCuZ3zFHpaMAjWihSryC1KcnTPohu/hA+wokrsW4BEP0HpeH+AfBE+pPhyBMXFmLnyCYKS
LDcZNGHXe/t4oqr5XBzv45dtuWZ803Iy6GsDX+CtVWX5RnAjpXTNzi4BnuO7C+qHH7TAxJmhYYjD
iXMVDXGUCLKBbmQtfqA7EkrcGICTSFL30bRPUDEAeoCHyklkgU9rpbquQhuR+VLErt6Q3z2EjuUY
zW4BrJirmP7+84Lb7Vix9Ag1NHk2UaWeb/kWl9UHpIgtTpSd1eeqLhZclSjg18gipF2/NeDf7phH
XfYmOrk/a8Y6p+N49csdibj85H7s37thXLQJLI75I577WKDr6aDAjAq1Dkk9jLc5dUgaj+xLAk2Y
xxZdGkUtvB8xvCS0NNU5tqbFkOWlRX9RSg+iPtgBJIu9f8z6ZEMZobZxzoFAUdY5uVaAd5S5GdMh
VTtIb9nkGQMwuaF3H9RZMq5M0DqECVDrXM32UaRvH2YNkh09DG7o/RxSGhDJbNNhEohaQYoOuweQ
7RjwtfQBfw16bBmjniaqMqzJlM9YNlzEvVaH+v/9cJZVKaO/X6QyAOupKzBntEV6UPP6Z2WGMGaV
2nyS57ifbQaMtr2qt05LUpsLm7k7XHZFM3/i38zJTkzX1YY4C3r+THCnzyxknsxkVMl+p6oknsT9
8oOPTK4Pz9jyaD3Gp56vlW4+85IYPWRhxQ7wrIHq3/K3PbKzwMa9WCfQD3qnoQKXFE4ol4pQXf0Q
ZYYWYxzKHXe5wUwE4QEhO2PlXcT8rg6mlvR4K9/FoYabdLoId1SfU91fOiGAeUqDbq73Ah0C26rk
9zjfqxbRjbaxG0eaFoG1CCFB6slMz601LkHbs+NuDF5aYVhD9bPVWxtyv74uv4nzRhJ8lPb+VsPo
On+iXwX3DDdLSAqdKv5ekbFa/VsJGWPNwbDByUh04vN1nFOG4cQ34vPTZrmmne2U7UB20TApVtOh
yuAtLKRoE8sszckQ5QcCFYuthkaDOCzSw2jOB7vlW/uM9wiV8JsTWmnJBOcC3zE2TtpuAeosMxwA
78Z4uCu14MMQRtkSxG2mMbb+WeSTIItStAEjbfhK5PeM72e8A1cKAG+uQxSlGDMdrRb1K/mbEzmo
1HDfb8AXMsCPLa+sgPp3M+gP07rqPTqymbH1KHZ3i9Czk05X9z+//Kb1YogziATXlIXDNqRbjUDf
WVR+BE27ItmTjiv8jJgH1SqH27Ys8PFC0mBF1eX3jDnENNX8gLr7GWzxy4HcuSpjwEPkTPQVL/0F
4efPbcOqID/zbWz/CjKvevMKlr0TCa93UctTtGBenMJPVPXU9+PCDca4AV8oiJbLt6ZU8l8oHK5Y
q3U4VMvH4MT5OydSpkd9Us2DmAUcs4fIg7ZLM+47B+Ejc3cEBI4xzNQTOHBdG1zreH9dMf0e5JHB
i5e1re2L2doKnuSc2WLuWmAd1aQdsMIp+ryEi9uiZkQS2BjJKcWH1s1mYg7mffGLKo7Eeq3Yoa/H
EwsKFH7X5mJfxMRJkVDQE8rgHSDwxCl6J92UKnkq6td6GNRsfooY1Bm/jLm1d1mBYbMytH8q1of6
lc2PE1UH8tEqQ6SwBPZGkbfAOJ2l5A3J/wnPvUe3aME+DENwzbfl55VCKn4LBsrbROEZLknOOI7O
TewaGcqbOBlWV0UBIqrOHy3XKZn5qMvSBA6G1C5DVb9hr9ZJ7UKV5Be3GyXAuqL9H1gdm61GVXZj
onCclHIdLpimrEO7O8sPM/PGB5S2jIUeetK6tytclEm8Bhe0G0TlHFENVPhB5dej9g7+dSpzt1No
IS7GmivIqztfjmU5cTD49AJSChnR5iJBy/x2mY4XOSxlWKqEXxZAKCETtW0qupVgHmXGwYbkzy52
VanqsZvJqFST184jILIttD6o84OThViApdIlHFzJeeUc1IwwyqsqVlDyQmtijjDwJ8TQr6g6ig2j
ZC02qCi6Curp28kyGaUq8kFgDynYz28jfHhJJ/ljH+k9NYPGkpnrOux6
`protect end_protected
|
apache-2.0
|
422c9f18718d9bcf69beb247f0923f1b
| 0.912291 | 1.966682 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_mssai_skid_buf.vhd
| 4 | 24,686 |
-------------------------------------------------------------------------------
-- axi_datamover_mssai_skid_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mssai_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode that
-- also incorporates the MS Strobe Asserted detection function needed by the
-- module. This provides a register isolation of the MS asserted strobe index
-- Scatter needed to improve Fmax.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
Use axi_datamover_v5_1_9.axi_datamover_ms_strb_set;
-------------------------------------------------------------------------------
entity axi_datamover_mssai_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_INDEX_WIDTH : Integer range 1 to 8 := 2
-- Sets the width of the MS asserted strobe index output value
);
port (
-- Clock and Reset Ports -----------------------
aclk : In std_logic ; --
arst : In std_logic ; --
------------------------------------------------
-- Shutdown control (assert for 1 clk pulse) ---
skid_stop : In std_logic ; --
------------------------------------------------
-- Slave Side (Stream Data Input) ------------------------------------
s_valid : In std_logic ; --
s_ready : Out std_logic ; --
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
s_last : In std_logic ; --
----------------------------------------------------------------------
-- Master Side (Stream Data Output -----------------------------------
m_valid : Out std_logic ; --
m_ready : In std_logic ; --
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
m_last : Out std_logic ; --
--
m_mssa_index : Out std_logic_vector(C_INDEX_WIDTH-1 downto 0); --
m_strb_error : Out std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_mssai_skid_buf;
architecture implementation of axi_datamover_mssai_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant declarations -------------------------
Constant STROBE_WIDTH : integer := C_WDATA_WIDTH/8;
-- Signals declarations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_mssa_index_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_mssa_index_reg_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_error : std_logic := '0';
signal sig_strb_error_reg_out : std_logic := '0';
-- Fmax improvements
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_dup2 : std_logic := '0';
signal sig_s_ready_dup3 : std_logic := '0';
signal sig_s_ready_dup4 : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_skid_mux_sel2 : std_logic := '0';
signal sig_skid_mux_sel3 : std_logic := '0';
signal sig_skid_mux_sel4 : std_logic := '0';
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup2 : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup3 : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup4 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup2 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup3 : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup4 : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
m_mssa_index <= sig_mssa_index_reg_out;
m_strb_error <= sig_strb_error_reg_out;
-- Special shutdown logic version of Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel2 <= not(sig_s_ready_dup2);
sig_skid_mux_sel3 <= not(sig_s_ready_dup3);
sig_skid_mux_sel4 <= not(sig_s_ready_dup4);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel2 = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel3 = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel4 = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (aclk)
begin
if (aclk'event and aclk = '1') then
sig_reset_reg <= arst;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
sig_s_ready_dup2 <= '0';
sig_s_ready_dup3 <= '0';
sig_s_ready_dup4 <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
sig_s_ready_dup2 <= '1';
sig_s_ready_dup3 <= '1';
sig_s_ready_dup4 <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
sig_s_ready_dup2 <= sig_s_ready_comb;
sig_s_ready_dup3 <= sig_s_ready_comb;
sig_s_ready_dup4 <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the skid register for the
-- Skid Buffer Data signals. Note that reset has been removed
-- to reduce route of resets for very wide data buses.
--
-------------------------------------------------------------
SKID_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the skid registers for the
-- Skid Buffer control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the output register for the
-- Skid Buffer Data signals. Note that reset has been removed
-- to reduce route of resets for very wide data buses.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_mvalid_stop_reg = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
----------------------------------------------------------------------------
-- Logic for the detection of the most significant asserted strobe bit and
-- the formulation of the index of that strobe bit.
----------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_DETECTION
--
-- Description:
-- This module detects the most significant asserted strobe
-- and outputs the bit index of the strobe.
--
------------------------------------------------------------
I_MSSAI_DETECTION : entity axi_datamover_v5_1_9.axi_datamover_ms_strb_set
generic map (
C_STRB_WIDTH => STROBE_WIDTH ,
C_INDEX_WIDTH => C_INDEX_WIDTH
)
port map (
-- Input Stream Strobes
strbs_in => sig_strb_skid_mux_out ,
-- Index of the most significant strobe asserted
ms_strb_index => sig_mssa_index_out ,
-- Output flag for a detected error associated Strobe assertions
strb_error => sig_strb_error
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MSSAI_REG
--
-- Process Description:
-- This process implements the output register for the
-- Skid Buffer's MSSAI value and the strobe error bit
-- that is needed by the Scatter module.
--
-------------------------------------------------------------
IMP_MSSAI_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_mvalid_stop_reg = '1') then
sig_mssa_index_reg_out <= (others => '0');
sig_strb_error_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_mssa_index_reg_out <= sig_mssa_index_out;
sig_strb_error_reg_out <= sig_strb_error;
else
null; -- hold current state
end if;
end if;
end process IMP_MSSAI_REG;
end implementation;
|
bsd-3-clause
|
6957d179297c64a99e5af8271c116cd6
| 0.464433 | 4.455957 | false | false | false | false |
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_dsp48_wrapper_v3_0_4/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
| 1 | 142,613 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Qf0h8c9FF5hFJr2j6DhlMuNnBIIbTUJEqExkPrlzdp1piOTzS8TftyD1wDYKo+YI5Nm4qIQK1Syv
fTy+AigmHA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HU+Mc0EdOO/vnFGZ68ekYBaROHQqXDKKbPDIr1sMVekDIcSIyieDJvRD+Bx1ft5SBK2MyOhU63yg
NjxFlxbpNNi6Dud3G23kgVhQ+cGbmJRpBskIidVnTkexU4mfjdaR65LGrvMeEgkaJcpkROqywKEd
Dffm+pDPP74dXoeXjg4=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ojZ+gJGu2Zranv4JRlazhMljXb1cqCUaNRPAJ1J8B/b8OC04eeCIko5HQlck3OAGfGSg4/Drzwb+
kfdDEBoc3aWA/OOO4BsJqyeKFU8idR4QS1HCF3hg+1/ePxWkgyvIVnZ7twcIm7N2WG4vpTWpCz/L
UUX6p3Z6AqssW3ahEmLbeWBcxu3S1UM+5d1kJw2vrY3V2cBJg9aSK29otab/vNZQ2Nr7rYc+IG8i
11sUi3iGkJFK5G4b+p2pi69ICGRhhW+vdLazpeZdSIuYK+NhNyvelOko4J+XRgUVefpjECwbqWLx
cAcZQFLjqkq/3HJ0H6SbJ1Wd9GFW3WFyqQXscg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
lCdVZ+DYqHE/8wFL+dQ7s9BDH0LQ6D9MBn7kDXwCCWCYRVU0M3pqqRcWG1JpCT1gDgJ7/C5Fp9cG
ufatjCsJ2eQNRUZ1J/9MH6bI6FF+nUc1bK0FE9uAZ2KPrdoxyGER+7glBcBgvWhdaFvrYNM88IoM
MS0pozdNFNmGzD6NX0o=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
lpTShCItLeHhp/sFiyBYk/MyKTN2f+cC+Rko/GdbNE9g9B2GJKf/lgnRLOZYbfICzDDJH5mCfxRx
Ct9GH6/hLe7p3FjJG7d/3JgAh4Ezq3N0vOFKZ3RcbzSFP2NndLKp6IiYNeaVh8EL11KztmKTRQL5
u4ngR1/uR/mAZzUa5OQNtiGrj4phMPemDW+dUSHzxTDma5bIfg5J6Ien/UM7rlBpRDFXhM+dSAAv
tqVCyChLWplLjdJBDnnbq9ZciWrAvp8eIZFGE/wkTiCV1t8rX2gJGFndkh9AQsxKZruIAXwopDPu
rj71nd55tB+jymCpVuDozAfEe2vNhv3Cm9qOaw==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DAy+cFjjI7X2IhXhJ/4IcMU+MYlkA4VPlWTmbnG+XzBJ/6HKM4GtFCF4dEoMrRp17qCoDXJ6IXBn
woqEvX5bzt5VBFHPqb8MFKGMIy24cG2K6KcCPgNkWmjdMANA2sLOPJY76qDX96CPvJnhUSQzmWKo
kgJoi6HwKh6EnQ6Cj8YTBrYER1ZeyNRWbynRPoioGT9oc4VwwzpzC5TYEB6uPvxwu60T0J4r3Ju6
fGIeIVud+8D8dRN4Nq5rBkGZyBpNv7rfz2ZNxzLrWv1irUPmvfhCDgTBYx3syxHrhxHhiV6TaZgs
KtpBRGXZDCQQgzy22JHVxDP2baVXVCCzN712tw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103440)
`protect data_block
8jeClXo4XTVFR4wW+ypP2vsspAiy8YbjiHVQmBPNGS8fHRClf4fdoFIrnnP5R1eWmBMXgm3WKYWH
y5IFg6MsHnfmL7Q858+dUYOhBz5ll3OjEbQ45IMJlXlYWkoW53ukMRkNp8cWUbP0DH+Bw6FGMv2C
+EfgP0XVPvxx+QRUt9GR/GMkVO97sgNdmU2gzg0M0nUl6WlqlLHBgYldIgL0/Jw0uZYBOME1nvdP
hre2Nx9U5c6INQEKAYHtn5FEXzAECOnp4+dytROPJtFqlaGw9PWuQA4W1Sa8+JxT+63kKwcuL6Zf
EDtp7LQNHEyxAJGYNXx4fy5oBzAp6FYuzDxL0QSf1b/tCrNduEKb+YgnJJPialu9Blybv3SlaIb1
iIiC8d/TnFPUIMtS7jV2Bjhq5eHqKr/zOx3bAyrfRELJ6SL6wSmovCVlC7Hs/kvtYxuev03ZaGCP
kCECyRCnB1Lp0KSHkOjcV4yMd+qQ2OhetFBonVBvHoLBNg4DZP9PhuRevvCaSnhraDqvUTUbOMr3
QUoH6KY4PUirbIZM216HvKTdIbE6mDXTUPHsAxe0A97TqDimvRHcx4ebh0AshwZlQOH2XsajLv2S
fJScfIoOSLq2h/WCtdjmkxGuu2eh0z7PCM/DN6bCl24eKcEWdIvmHVCIVsFKDJv5CPR21pTlPRCp
g+Xchv7RJQgW9fzuz1IO4+n2HKKfL3vytplPKzvbP+hLJOtOgJmkMpHEHIb+XY5pFW+BxdjdnZnQ
qkNjUnSYrJouKFz/Kp2STcQLzBerxP+i0xWWpXB/w8/KZEeQMim7qtYJsYUZddX2k4SO2aTeVSpa
3yeffgCO/HX+kZXxf03cLia00DhW+sm356Q9JV6Y7IMYT0uAHMAojB2+/57R1JyYdKkOEkBJa+8c
CEJGjKBuZDxltyAEOog1u02B4hLxN9sK7sjMge2sJIaj2O5jk/2v4oYX8uQjZW2kjqrIPnGO+9ZA
VzVNWQvaJcgOqQgVn2O3seJhKzDFAo40gfwpkKPwHD7ydsh5CSnTee8f4rqJWNH0fXfwRXT5heM7
noxFlpM4DF4E2sZ5nb8y3S7fisHNEkXePTZODIbIEywoMHe9ChUc2r/Iglm0vbxHNKCKEB2WI+tg
kSJDB6ytlAPfXhgZFccj5KjYLEVwus9THRgnFcsDbwi5PVtAK+3zCn9M+ddqV6cfHcWk6q4f0tuT
BdseKzp9WyGv/TcmCOzL5pegcakGYU0zetBehnyPfW8hNggQVwJ3D6BeCVL7juoAEk9rPVUEMCNE
aaAHscgo5S1K+vpo6VdKJVhdTzvzXhvjmwz8EChhtLXw9ZKa6Zk7GF+rg+ZzcVAHHYbTIAeDZt/I
DrfiADEtZBwbt5sCKySNxt2qdQifWNU8RZ1QB9qLdmrYwwkH4ZehjCZwF4FQlbH4ayNprqR5pnfC
d5vsY1K6Z8dVGrzwqPC97QHZI01dgyZbecQKxc7vCvuTzE43lToF09QP0k3WtxLMUWIjQ6w5nMwb
MWCBcJGReqbnat6CTR819Aaby8nkHo53HHfU/isrutACk3YS7i+PWGMy7QYK0tT44ZE2Qwya65Uy
VeLv75rOLfC02BuzQ7h3X4UtrFb4Wc6h9DkzRMY/t8qtHsNnCtLwWuX3duh8Yir2szc2KnxFcHh8
0YFRbrGEcbKbyyyBOr2MrmSitwBFpRF4AFFhvPy+wKfFagpB2/FN3ssld/7m1HO74JNNWF+8dnRU
38X267476w7QT1syMCYOkuVvm8Gf+UGxOkUqLqArdTTcufMO0YVCT7ZpIpJiwBXrqQqTkBTWEhJm
fR3oX7ea92EficCPO8AZWMW0qKfujxTesuGAzGkRSE1raQorWw0LkivLW2BGnlSDar4LZGOBBj19
iLCGVcP+TBanc7vHMFMy+viiybxJZwcgrf09mIq8RSh5RU/kUSZhPEfcBcUBUO8OVc2gZC7MsB8j
vqVvpym1pTUuut8Iaffge4TiCrzYwRu9J7B+48FdGXMf0dYb12WDTbnnXVn6lSf/eXJ95HXhbSgt
nxTmUjwrfXHEO8JAyWg3kFTVZnK6CxSyExRRF/m6OXRPZnROQMmyD3zTXdfBsFeSu7s4anNGTmt5
W4CMQcbtIzFqs0n5PpVlvk/sf9JvAFfph323022hHftmfeTDhi44c43VuBnvl/Yt4dl4+wl1Xu1j
bEBubH7X8CWVYsoaduJdsNF3VNhglNJSBspEPrWirZ11dJ5doVDO6DEhlS0OG4mtsPjewJM+bdXV
vbA/kSpZbrgDTnsmhVgFHJBhqMo1vQMP91lXjH7kEFmPbe3cykyz+U5QFSa/+MGYK438BbxWqB0y
PBejXygY3C9/BU3Lnk0JjDuUiDGaCnOoNh6zekVHr1OV4M/PP+dBHb/DZzPkJ169caV82WJCLG8g
ZSIKmxSnWs5xLBVLuYpLLZcYOV8n/rUFJwZaKLGpDO0qMxHpf/njYcUqwumkF6l/1T8PGqGjVxup
RtQTecClYXumpoGxjiTdkTAnOs5E0mVMTkEz9hv/A2Lv6PPQcZ/BfVdkFfGZaY346EzOkLJUhDyF
eZ9ztVVZ6xNAoE3cSqNyt8FOMgHo/UUH3VeH4hSxGtQbOwm2HrW55H2jaTgcmrT+Vl3Q/sbJfa0G
dUWjxguSibyr6z5cjGxM14Opxh1NkJWY2v2AY0QBLEkstCsjPdaPPesx7xxtQ6/w568nL29JEsy7
2J2YcA+tgDqmpBv6dTbYmBtZqpNJU+BnpJcmDSeRzO83+mSw8BbByWYMvOTBrgD7l+zm09vjNjGO
MWOzCejgbXYKz6ZEaMFWF6FzEyoYXvqC7wMk9K4eEZCPJSOPD+HbrjQNHYYUvP+sXIxj4dzPwYLd
T+8wXVfb2dFNMd7AmNLAFM86uDEQ8F1LSo1wpGrDNGIjNCGatXIjl83LiqmQjApgSQ9IsLZLl6mZ
BMEscYbcjxyUiOjx+v8oObfwiUzqaJuxNs5ZVdUWNxCyiucoSZyAam9AFQfZjRwYydBvupTUZN0R
Awk/1AhbiVLk/z5//t/idfFwbb84d8DVYmmmk4fnbgBEt4d2vWotNyvguGHWs2SUszMBt7xTtcba
6eI4o30ruNR2x9n5NsPAu1UqD33P6iiY59r99Za/uR8Cjr+SpIP+mupBnOkhEkj2K48i4kflAw8E
3id9H6Max2zYOEQ9ECIL5KHups2n2FS0v+fNueeNWnVHqN5jJ7do19KijOBcLjF7S6q/YzwGUZFU
NnmEjNRAUEq+Oq0AHqJzvHm25eBgm2yZ4xsHeyLDuWIyuDZEoCR4emaQvoQcMJ0fX4mPl97oh2Bt
0nlA0om/HF/VKYx02iCFXxHMZkl6iwP6R7vhPEt4AaLfcE+AXRGnAABPShUdulCWtDSM1CHz2eJr
NuhdvcXJVpCPQcXdpYMbFQpo3yl54ctVsiCm4kbTPIfeE1wHhIRj4VavAVAT2kwIZLkcQRcvlD25
z3vprrMeVU3Ie+iPNua7so2ljam+VAIIh4MpJouj5g2p91m/YSoDdGcFz5Ambsm/Qr5ZqFgx2F0g
QH1h1ewhrxBaCwqGnTKVyMTF/kBJP7fpJHgQ30gIXuSKEl+TN4D4zn1syj1QvfRS5853ST04Ga66
v0FOphZxPoFLV8OOC6tP+WduMFRvkHmwofj33JLkVBF9/PNwonEdODeOTiRsxtUy5QTbYN1uwyRs
CQ9fL9A3AQalLyFyET8SONnU6ZJpESPBwkXZGf+K5SiwK4Whigf8c+xHRT2Gs8ULMEzUSwRwl4h5
NBBzhumz1AYQEixzdkWbwyCz85yBlBgQY+jyywYa97B5SSghbqK4YA1jK0AIg3W1jPspUXMWEuhB
ROwcG7m1PRC9XfuxjEqYttY1q5H51KEPFSFtx3n7FW9zEajuB26nJchfS2e0P/Tf1Rt+UtBH8Yvr
kmjbRlIaT1xqsdfxbSgMosr25SpoBLMeM1THNnLStRzPqe27ypjMbxgS78gsl80cUuTWD8npHfKQ
297fc+zJupdaG5LYvhtN1NRj4Mhxpz5szcaeGibWbUf8aXE2Ysi2ZLUXsVHRWQZrsiD/7aei3lmU
OaAS4LWW+A+ZuBjnlvlmrT4+B0o1qbZLNeT1ns6PG76XRLiHKscHQZSRktDvgXor4gmawu0JNDLn
9wM4RGOAcq/A6UXN6WhzHXB67O58KODjJdcwVM5m5L0iM00BzVdvM6B05aWc4XlNa9EFRV6whU/R
dLXpMdRN/VS1keJj+fRG/PuBP4MaIRKtYTsyM/c/rmyonLua2htgKr9VEIb7jH/s2hj5qRAbtvSv
ZYilSmFzZiZjffkDwOfdAZNPqnMyfNsNpNoTFWefPS6NB3cQWqfgMmz1jAIu0yOnuQtzkCaAcmNO
qhVpHPo4oqizyrhcqXazPS7fbRZs3RtrxWIzvgl/JEIvmbyumQmkQvjc8wWzrSH3EOqv4PjDh6WP
+m6+LIGLZPS+bulXXXuURs87xL5Pt+v9qFzhAA5Tj01Kqwp3JnvtvZNopUTKIuoI0mmAArQ5JWFW
zsQj+mA+vE7F4Lk1H1zQ8lagBoJdwTY5XhR/fo1iMl+lzQC+4U/l4Hrov3kxCtNBYNnAgRt3c4Qj
DwQs0vLfk+3ydYzpcw9c7ueJm4SISV2sdOaHxa+pyEx5BESW/FCxM076/yKD3tGZ06NBrKLLxFLU
w8uHGZTdjN7Rq9q70SjS0TazBy8bgbFRA/9RSM4/0PZQ4P6HYOzFDuzAHRyd97ytMrx9bEh2I594
fRkmIJChyXf9KljAA3QeduoMIXyPsY+pGD6hdhGIG+qvf1x9UeVNRC+ZAQiKiD7gGX8/2FTbigBP
KJkjMeqrRLZo/874eo0KnlKExIPVrH3v9o7oXn2u6dtZ+7egq9xetzwgVNn/DeZ6q61W+eRU2346
srwGCwz+ih9pyR3WZAPzioeK/BQlTwlf6KegQ9AaUxBfhtJG2SSe9yH2GHu21NueWF6vN4jiXAne
i2nz5+n6tEunY+UP7ABDPkScDelirZYGQzyfUc+Jfm6EEk6s634rq1tK0cmps0d5t6DXBc7m7OC6
CXFZvGFjrVYQ+yapi8hNp/Z6t9wuwkdd9jMBM+54Uv1ugJmbY4AD0bPZUk0jhGWDAu+Uo/t3joFK
eaihHGsoVaapAHm09mcTZUnpi883I/PW6D+HcoLNCsZ4AhvI+cT2wR9lcQRQFhkkweYwlOaPyqEP
eE8H+5JLtfEB4DScLu5wI1+v2zn/77VrmabTVSxftw/Av2eY0oAv9JQqzQ62HYOcFYzAlL/aRY9s
UhFwo9n+YshxvAWpN0B7eMChxFfvRb3r/Hp9R8RinffFk2dqrLPwekZnXJXHw8/+WEvcwtANO6vk
MjooVYAqtdcuAm97mFAgcynM3R7HAaTleDGUeNzkCVVcDeJHHDfT9ALPAEogpJSwW6kx9EHfm+GW
JXc6h7tn++EZA2wZ/i7g71RFdO6zoQxdEW95zqqwmTRc3xRUQmq0Ll6fF/0L7LBI3l3ycQZbzUgL
D+6L/2qJCVOgSlbT73dqtTpvkd4q3inLWFIC48RTQHMjNfsGfyP+UlZZtc6y8SK0cinVmLNwai2Y
GkEyqzZVbu8bj3XMHH4h2MAWZo1bzzad2trpPpTuGfSgA4eNIXvFXVhMliEj/NfPUbylpGUQlM/a
PxxzoO2//2iWtIgqW6tALZzSBXfnOvm6stMxLW+Dyqhtg1sGUB90OJkJhWo5kF2YQnrUeKZ4HZmu
k71lWkovqGBWKY9UP8Yy2vfgquHXtezHYWyDVltJWxSH1coHBgCbG9U8nPVlL1c2Bx2oAw8SIfl9
7XDHs9H0M22XA3SO0QZm2HH+zyxL17LUOGp2NyG0BMJq3Xq9CzZIZaw3eXprBItxi8eGPl7CeXlf
x/afeZYqelsvnwu6FQmAlUh3mpFQRHhUWQb0hka4AAelOPs9MxTIXN674BXmNOVG2K/SGRnsMfbv
LG3FS8fHBxbMF7/yK2h2MgWEqI9iFyjINWXv2EfiK6itqNpjCSNhGPFmcEEOkhXFF4C4o6BtQ4dU
h5muHswJwMNYaLgNIFFTApd+1Tupi2bsncwJMOPTsoqJkSkrO8zqZXN10X5Mpr2IuNCS+V4KCm1Z
UGzbz5pfh2cn1MQgWJ5KP0JQmVUop8kpeH3mbvqeBnU6m/f6g5ZzN+/U+JTf4WbnkFQmGX0ygkvY
+fI2/oj8JL9QG8Npjt7snnqK6LUwFM7YzKRBFS9TOW3AmE+/ISEP2eL3agxEPur4tFRYbgux0qoV
4txSWdf2k0FFEd1Mjkjo+mPdSjKsCFI7jMiYfH7vNNVQGb9ss5hvfEhJD9E27pSKZIJkjquSJBSi
sKYB/HjKDTH0qP15fZKNztz88p7Q841jRDM86iGb+N7AYMr/QBumviggZcERBTT/L04/G5HDvKML
mxkmEG58owPAV2FvEf53kux3OmSbwkKXsNs6mvUTafMYdYmX2LgSNgsPkzlzSAziout5U0701hEb
dzFBhWmYw79YsNdtWT1egtUxx7PftVjdRc0SRjlu/AWhvs+N3JHSE5GkrH32IQz4c5fCaKnfsUMf
R09OVmCoNRrP1Kz+PU0RQ1+vAvV4SnuPlV14Phv9mCbC//TBoVtJ1QsQWKiEbuJuZII52dq2EFwC
MzbcLM3Q4Ksc0X3TFTZa+1KAFdWVC31UY7JrIrIn1vHxBiFA96tYQX6oO22JXcLn1UrDRqHs7UdH
8+amNtw5N9n87yBgr3avCpDvNEcl1IXHxv5m5ZXv0nvT/ak4gUOJNCtRkeSF24PNbZ4jdnCQWpB0
oY+IBBw69sdmgCuwAA34gOzkzYFOaob9iS5oghfbK7HYWZ3rbhXFZycnwyiKdbhkgahclfZyKqL7
wZjQniGCZ/A0QIHPKRpG3IUycQPQhzhCyff7Ly0duexAbHMCdkEHhqzx4BlUjZroymYu+pkEGuQa
QCEWGcTuUcsGnNvKUOjAE/+atxQ5rpnFvmmiQdngLhid8BV2y+Iu9yRS0R+ncj1/gXqzAQ4k4PWO
Vi7XFhSP4X8TEk/8Kp2J8Mr6WyUn6mE+H4+7CvAdCergHSBwywF5hHtquL6iDRxl38Fz7uKF7pVD
kYH+RGkkyxCqG3peDLZ0e02qLx+SeHmLF/rRsrFjTUVCKhKGKCaD7vtzb8EbxBWIt9fXv4FsDIxT
1D+KjYsDYzuaRTrw4oZ9OfgIEE2FSXyFnGxNPY5yG1dLtiNDGkAq0FB4qOTciWPeYBZRCj8ZxoBg
Co+A9+6IsLg8ce+0uhlQchhnaUzRCLMkukKlVLXV559sn+jWqRmpRrfU2P7v8inay6YKEQASEQ13
IGitGOMeoIwfaJp8RSqB4rjMCvTVjpBx2PEDYbLtqcgN3f6tbS8eucUM4A/dkoYX9Yw/COowMmlJ
A2BCLTq1MIg0j9G0isl0dGCN5nBo4GLhBxi/bNJp+YW+qQsYNW2uRJYN1W+k70j2v5ASPsPZpVFF
bmWITliWJ5D2G5u3Z5DnlhSjSTFM5GCK1IthgEFDQ3zqrCBZ6Yp+BhnkJ6VA26tAqkzi0QCWmNRg
uL0IJ/lTkgjpf9XaxsqTbOvP3hn+39uW1ZskFdb8EFNdJNBOTS7wSu7M5KsY2DjTRHJ0++Z9bTZJ
xHeVg692/oNm5KHjgFiLl9DoPDdo4slRhy28LskqgIJJChGh+JkDIHWbmRPeILrHzLpdpkJz+W+Q
vZmC4hpTKQGbp/UMx+iB62+nbBybmpZgxl8AjcxO7JDj8M3ueKe8vsas83Fh7TBfEZgQf3nCyYYW
vLqz0NWNMVKoTaEc/AhN51n7oO/JbmL9mghrvaXIVq034MC+S9ftlbHH7dSJmfB/jPweMOwNWC8+
ep8hteVegeSSOHpNc4pgJGCxsN6CXGqSmj4wPAJc8S60Mn82uXCo4qf29S19USEoB9iN0irz+n3a
dpnC+B3XgTZ94AM1JI/Eev3niYrx1SWMF1yqKAs1JNwWU4uNWAdh6quxDleYU/5h1B0bJLGBReE6
M5BJFuIgRu+Qc7gyPk2hW/t9QnDMN19oVbcNfOGgo3sTp5LXa/D1Lt4JIOBIzWmw4GJIk96aD+TI
CtAK2pIbP6i35H1JEdGKGsf2YTHwxq+ww+1QPZ8h8v7uZjMelzIFDliKNOnuALpPSte8uhSapUiF
bMSSCZmvtEKJD57azhs50L9wfjUNmYY+hkCpPtRG+JvmDasDMDPbPaCwZmf333hzLisr63j19CHa
XO7g8mIzTC2ZBj1z0PAbFbkOEScHtOObkA7zKvHHg/wd5TiUA+146zGDjk8Mt/61I6E1aZolOQB8
RdJejtmPKCwlk3t30E9p0J6wAuG0gtp9qGCMNympRTPRT1gocar/czdRso3knYMH+NprWq/oF7c5
+vpv2euyq1iVz9OOXBA7NaRelQcdKo5n4pEJ2kca82KzxevmTp+eZERaDNy8skkGBAt4rGpFh3tz
5nm2/UMgxPcgtAIxL8cOHXDRDLAYheStRIVOr5FXweeM9ZabmETz7s7lpv+R1/yu5lCWYm1ybgYt
3wifTUhwItwCLknr5Bq6n+tzU/W4dE+IloQEKNdIEUsJ6gE0YzxfoSoBRuBVyGvXr5TUK7GSgdH/
/zg79+1CKSxc8OFgt1i79XykRtb1vcP9/DP8X/4aWzvJSFud+BRBXNl3KNyNJjg8DPpWwlCJnfHT
C/HXPqpMjQ8+c+qX5OAFJBi0wOTpieGCkAouoae1/8bQTbsUPl7tzJqBeIu/+rHLRb/sh4IRqtEN
cUSjEZbHiP9UK6pGqIZyIv/PyhjACjXlPCaItxC46agR4mbarVfOQsYekc7/EVKJWBExxwaxV29o
/uERQ70rEPBy8G+rB8aUsDTobsifMwD+GYZM54ozgLqKoW1BOgtD9ImJTTctryVEXXIZ7RXKW8d/
Bv2J55DxFQigKXYIZ3+Pde7a0y1Z+HrPGv2e1YQCQTjQ5162hwge1JLe5bGbPMwgy7SnO0pgs44G
u6I75qalINGlMlbIh8Al7DcObeCDxIItmRDYzMXtRjlNeH70Wp6c8QJ8Sw/fgtC99FVi5IonXlg2
HiFggEMpwEIMKtLqawlbJRIiB0D4Ep0/Dkg5DCRumpxMFgfgXzYx1a567hYcGV26pGupl+0ClT/D
/ZnMsnWA4XWX0o3Pn+WLhc77fn7nWeGO19pudyIWELYXFSfRfFwDTuJEL02X9ZRVMXdiYCeIpPOz
Zzak3tUCvwlXeJOdiCDxgWuS/orhQ+/XVu45vazpbH9knJwmOrFsg9kaeDXGAjKqt6caNoNFJIHG
MwLa+ouMPlnSN9VDQF99xTBJSRD+kk96woMbiiunJok9DND2jreaSpNc//4becXDXRMixkQbhq5T
ZrBgnv+znmIueUkyPFk50vqzRZzPkTlh2Th4MunQ0QXjO1iGUtP82XQP+KjMx6G/lIUssFBxxecI
+fUn5gQQKc2Bi3wmuOUHEvABy8pWsofPF4sNBFDLBtRXWarVP2LO8mV5wIJ0fNSdnLex6BKDQ1GL
zFH0AHxDX9WlZkr0B+GKnRhViOCDhtoNlM5KE349HoQgM6vqwTxzzhwb9t2n/ZLDkCbeGqC9/bmT
iP4ih/bYY+S0Bri8Nv+ppwSODUdNVnvijOPod0BGjoFdeTlDSopmx3SRkceGsy58CdtXb/N5miW0
GgNkm5ujQfNlxOjef6Q1BCOXAfPgt1zB/xX94Ih8hVmVcPhPuOAt5EzN8M88xZ0v6zXedNystzHE
77TNIEiDeBkUq/tLOyEqKd2jM4QrY5+4/p7VZxZH2H6OLmaLOvYoS5bS7CJjdnIqWENzp5yvlZu2
P31plQ1ONtXlzJzc/HmyPVpRdAa1KIb/DRq6lJUxtT8KVLIjboAe1l4iqs+cmob08/0c71ogFXmt
Y8uDzD9aTMIOinuVCyB8Qjz/nK9zyVHZ/ckwANOcUuj9GfyXZx1bjnfnX01QMfZG3hq1g/nBObNZ
d9Sw65MhocyV72UYercTOq0eEwmvkurY0n5rGyZnjDCmMB6hxWDEIvdjY3hvQWsd6hzWkIR/5oOA
dvV62uTBa4nLWCn9vajNXvBfsk4xAhnN8lgqM2k1RhBqSim4LI2JBur4HhDfCMQ+rGD1qjqjpCap
1gInKityWRbEilVA/E+LoXKPtZGJu9NtJGRFrGlu68g+NY9e8AruEX3HcZl2rvMDllpg1AfgcsDH
i7qnVlZJUL/fKzT9tDeYuLaTajYgjRP2qtIjrYjz3Fus38utYY5emOibaPX7dh2620bz+dDRE+48
77ye1amYclRhVGritndPRcE50zoJaBkGwM1QlHYpuHy9Zc+KPnG1HluXeuU433O5ygs8c++QNc9x
QKkPugUACIPf/9Pv8jmEBWSKCKcpp4tMxQwd/GdfFjbJSnULMTLi09oWVsxHkIg2G1aP3Tef/UB2
g4egl3gDyA9ULScB3UxXrtc5L76A3ENnlePoPc6R2LeDIvmljOEmGHpItGMW16+bxhLdTzuRT9SM
xnbiVakPSEwgUleB6Rk897/6hmBxqPxkTBFkmUVteVZ+iHzlg4yNiC4h8iK94kS8NcAhSNl0f2oZ
qloXFpwOjCS9D7PbTVTLphe1jZQNa0GnHG7rtUeCJ5emM/vzwIyOJ2xchMJbcnZ54qFdgoxS3xeh
8BUnEmgimEddQ0XpY98G916s47dHd/Annju4cCQ0g3ql5b7BbmBjXgddXm73aaYwLPeOBVZAsNQR
qksxQmfo27iI4rFq+7SbdnhcmLF9hnJ6/kopYmkjXDoF4Y1UpEd6DPwWWHx2PPyYeHgQCYUevkIx
lFjUWe/9frGLuQY3jufr6p/yTG6QmdyLiQPgbitoNjMz+nWJSMTDlD3S3JOjxAAXoJNWXaIlGJCs
KvLJyhIEjPXlX5U6ASTPRfTO0Tyup2jqXj2qkHHGeZNAx1/Is7z3hxtdA4E4OayxzysaaRMxkYYI
vXJPkMnrr+MJ1eQ1PxmUlWgHi9W0ywgKKGNVS5LE87xklFRMmT6MHPbdOI22hLFnSzbe1hTIxZ2u
vXw2ihQ1w7Qz/IfpqISaZPnzvTjgvjzKcHBozJR5IYZI29rgzcxwStQiHkXtVB73NtLoWMq4HBHn
reaD58w8Y+dBUIGFeoKvo/etZbF3wi+f1pBcGF8SxtzRf9U7Fkc+uE2t6A8qKiFXSy58X/ABekkl
NhxujIiJwevZFTYyZz7THe5jbxsZjC2OBygdXDqmDLIGuII2he8NMzxJW/deAhsc/S6Qv1nA4xvn
GcQDOjv1bOfj6BvSdMiy/6+zglcZHIqmGvoruP1rvRxGaGGhEswOnCuz9Ta4GJb0JPGvjMGnjRy2
HEZOZsui/m/ZjBBzZR0ULNQSzULMx0cqHVYNMDjYUN87VlCuqM7Yhq9KYjy3lFxuWyZL5iOxdZmN
arnePCyTrekgFOkOCR7RqhXpgJEngNYBv9bd0Nz4YRLdFdAsk0CCc/R4d9f/c2RpvK6RlQ1tNVwe
tif3Tg+D7uQCbX/i2TXsFpdroVSRtQeluxItux72CjoTYQxF0IR95vu8to74V8qBKxsbK5krzISQ
RV7mvRAEhnwpsOhrRvr/IHgx+O9/aV35nT+BtU9x20hFryUVTCU5aqBovpJ8fhGNKq40hxzgoUHP
+DsXw6Y+yqBD4kb6AwqSlrJ1nqavdUuN72JXhf6vqPH3J/9Wq1d13qwEdUpBZAhP3WPIjKZZ2swU
xV34GV5QbyQktfeC1AgGpNj0uZIR7v1fOXQO/TgPABUS1RbAdByvYoPLrJPyNgm9/Sr7f37F0pi/
tlRxymPTBFztC3d5to20JlBDTS8FuTmfi31rjn/GzWc4fX0nYKfeBCqZsIMN9DBlZgaspJ5PyJSQ
mfUDIm90+AyBLfrguggXbKP3lmyEEEATwWb9VAKGaTXPLNbl3v4YoC355oTEt0Mg6nzJmYcyoKwt
P/lrtgZBRR4C5PL/eYmRvXA1lG4D+b+eNKisxV8Pb3yli2CaXSvQLQ/omuZeKzZHQNMQpfYgRSBT
oF6N1il2yWRR8ZpCvaKoK1kKTid/S96O+ukeFbdtIydxz03SXQVtunA4KPg890lwMX4qJtcQlXOI
egKdoKDUccFLdgVDeXkpqQ7IaFPi3JeFxy0w28mci5xeCa3kbD9zcR92jjjPP10drFYpVLANFnO7
cKmAWHmzUDCIHAxnTnvAyDXRtpCeKn2OuQGyOaI3jEH95ax5sAhqYhg4H/rrpnoWNgfGS8ISsDDv
8VFfyEAG/BseMv5UyokpBa6FKItjrINb3XLeDyXia3pLt52awwf0zSsKIJyxw2MBfevAYwg/3CZU
7PKbXolzRsdrLkNbZF+oVxfSDc2c05MZOVop56TwmohjrIz8XBz/QiO36eYtS6/fuONVzNdqCeb3
QE7D+1PME72LiW0nKfnFvQzZZv4VrCxPik8oDH6BBAkZ5gGUc41U/1w2NfSqdSbQsm9zAfGenn8L
CTKKIxzJP5rpLQZXXn8cL7a46/rbT6blNHI7mazATBP/dcgCushD82PDMVOkH/DArNgaDzHP4St1
SR2OsK15qaZCoZ+n2EQ+equCse/AvA5X2U1hFCbrn6WRoV1lI5wZabsJMkUBqdfznFcsSKXBQ+xl
R353QNlVZ0ugrzfWdxXSFcsz+b4rJrHTu5LwpVCZfVd5ng4gyZSsvLqTf/9Vb1xuacsILz7FKsX5
ClM0rKaFM+DCN+q6bAW82OdUyOv9HG7tnabYy+R2PxiNdGO7+jB2+aPWUZ3af2AmWcD3VA9qdoWG
QJtzuSsjIn2hvf4Qkni7I7XYlQI+G8oW6AzDcs31Fb9hVfUwgPBTCXptvYx7u8Rrf2rbnVr3acCS
P6ALSXbW7RLTmSugYXp28ctO2O3s53hEk3CeG3Enw9IoVQZ703r2CmJMTx8vcbUgj2W3vENqnZW+
Py3krj3FRBvSLRlFWpxqCVmN/1l5QTVVUlbgcdyKnJEnDCi2KRmDzpyFkfzlLexxCQqIf1IedeYm
GeDNnKv5XedZq17Ah6oz9RlC7HSvnS0jCLG0LNUY21WeMHrMAheA5KiZdTe5g2pph06fu9N8jjC8
HX9u4qvFD8ybBHzzGRB9SLcpiNJUtTuuwgXr2A9iWfb6O9r41MVMcZIQyDofFffxzSHkQaNXwdpI
ShHHUomqA2lutvPvWmHZIHUUIwD3WpHuJVyADTWJfsV3ZgjiIaAt1CUO41ipf56KcEfXTzdPvfTe
0Re6IjzO+lo1HlvB7uyJIaOAuOZGUG1kEbafAyCgD0lkxr/BzQKbPaO/Nk7fVxZ1g6LhdEMXnrJG
PBlvP5DPc8cW/4s4VStABDME2b4tZwgK7g+VQpYOdBwXx7ixajyZqjkYoTwfe9dt+iqojsaaRq9Y
sRGh6mIYfOy3h4NoDuZlHzzJSsKtdoo2oOI5xpaqVEAjLirX3kixJ0ByfohbQ3uQy0fhvX5RS5ss
bWyWUXIURBzqhL6L1fDYOZ/U5Efg7fZrfaoqhDT2qTUr31qHTpX3USzGH1lZocrDJ0GJWNrFpNtu
WHK9a6lsLLN4cg0D/ij0uuMexwNzJgFSaRozqzJBKUwyMItb7xDQVygsSQ1lnhPXECssueSZPvQt
Xx3yFBX/8vkLZmq3aM3hDWcAxk0IYgfmh+ejOTJA67eF0+YI5dwZ6MPhLgsv8Nou5gzl3+/JEuX8
+niof3i3vE1ZUfajXRGGA92YI61F3RRQvLv2TnOF7fsJRwSPjHPX3Uub1UFZc+p854uTekxB/Ey2
i6QNEXkq3KsXzb3AdIWm98d/ERqkIQeNKHrLgLjpY1K8/kP2eI5321PGd5Sl3HUunIyatfQV+oeg
VXlqFHMNjz2i5RO2hEZjiuRX9QOhgfbeCdAY7Q3+I6P+OqXTUUBYCqEf631MyOOTXm5f8nHlDykB
anuKEnnrY73qV4txts/egQVPSDfNgHI9u55wPzT5MQL7mVzr9gcv8BiuwO0Ny+2uZC8KJzl0Kyvx
yT08rlc65QXStvBC1pcSBeLW35HZpV5aXEr0PP63SmOi/29fBdIHfoYUoHIlz65iiPMYH9pPYC/y
vz65MckO5iayDP5OFe9jnyxEsTx6tZFwPoTPi+tC5iWt/LFs4IAYDBwZnYzVtluioFv0nRRvUlEK
QvQqUjW6cxigrwd7rSwlY1z4UOFDkncBB53Fd3hyNFn4gZwdo/iYJOo0TSm/5uZ3b5l4WnkpSHTE
E8hxSkT3jTRzdRZGeRQavPuCnK/YgCrSQvCgoFm8P/pTPkaSlBQHsbOxnCzGq6SrwlGrpK76Zcnf
yKqdoI3ubQtGhy7oOkl2D2RfKMo53nBBDHHQkaqdlM+1gBwbq1HebF5V3v844gDuR/o5CBnrLMy6
63ncVtWxN8FHhpVosKEaBgvICVLGeoiszY3tH8IeqDcnD4igCKeHn6EFXxaiUrGmqtrdh5Zmiezo
2WKS/1zRmz+rlLijc9Uk1Wx3SLY1hkSQZXhow2IPsyx9Unnt8TChTXDgvISxDVmrjHOUX+p/Gtup
mQUfJgc7oMjPz7igR53xLlIo6knahbC0/nrsLNq/gv1VoVc9OmBVYx/U5zyNS5IL7DEfUxcWj4FZ
oPUc8/MjHCvBuIxD/9L4C3nq8LC8U5XbLj4HE36zXsHOPKqeDAbmZSoCUOh4e+Sx+PhMOkvFt8fu
2+jKWfbjhkAY02uHULwPxhYPq8RhX+HMCnQhva2CviVauSIL+83tYO+0rdtKSO3aiVvZ8ZHib7Lx
umv5G1Pbexf/L7XPxPvm8WcQmFVpTydWshOAmcplciBphxJFNQLbq7/Fd87DoVw49Ly46BWafUqQ
kPGJdnqN+ttPalLNaqXi636RZwajFGr5lzYwyDaslZCvgYgtEKip8XRBD6xsFRWZDB4od9qOIjYU
89f/eCWLKjgisjJg2ztwO6TCbfdk/QD50MhNk9vnrKKs7doFUarlpkquEAf/I1wkoRb9OvO6CRPn
Puhm8cBiQN3i8x+Pp2aP+MR0AbjTB7WprbedJm49EUp2QEpWq234iYCEvq7h1/JE+MOveKAzjmdi
UdUMLh2r6Zd5mVD9/tKY3viKO8Uzn4f8VgZfB2ut0QcAi4++MUk0ZKQuUEhFXB3ULuLQHdse/yDi
RqAQvTBXTiEoQYWMNpe4mxYOFR3cNUrLQco8GAbwk/PJML1bxhP+OaBQlJoNNjiVwygAv3Y/k85k
/L4O3Iax1q32I6vwj+SWlMVtvNYLXAL/GTLo3dBazBqJ9YW8pciHSiSbxvsG8jbuZZH0YqKzLBlk
cbox72yyGHaTvj7rX8s2LJul94pgfzpD40KZzm5uSv1UlmPAyao4T595VwtRGi09eY78Ao81GamP
pKX0qvVIj+x1kfR0knt0h8ugORA4doiyjl5hxKzJG60Z6u4B6z2feZ4vKNV6i/1v0sNbPnty0SCs
OVevLitW2l8zSyLSEUA1A7jLfvoxloFmmnuBEWLqMXriiEjrLb70XaszfCIfrpxJ09C5L6vDonD9
p55iJzUye4BTcWWnRq2Kd5NPfpGxEebQbvqSP+NS4P4Kmlrt5d683Z9KfB6aiENym3UG2zFwgpqi
9fdTPcGlXCHgAzWURLs+MmecVSqYMl9xG8wZQEkLvY+nzdUyeuso0T8hJUb3dkjTi5Qa5uDNAFX3
c1nL/on2GDNnhVepppEbYFa3oXaKw2MExwgXdCEZULHxG6syJ8hLebySZwETI86piYC8vqB3Rei6
DB04Geayq99SiNtqmM6ngdyv2fSLQtwuqBqlFFULqQrXWb8uPaX+ntZklxLnfAqwlU8pxJ0eoP3s
vT+vWnHlfTSOYbqUAOeiaqK3jnZWp8UT/BgYS/HmCDWhLBHxIUISH/WvN/35UMQO/+rB9PTj1INH
PsBBVF/GYUUSgcMTJCHolOQ9o5dxx8uIXh7x1AbWXDi1D97zmh5eCoEZvNaIHqEAwvmbLHwR7mYD
+Ss4XdqsPANelz2/KZRQ9u4Wnvuql85/RrnoME4c87rl9H8CV9EAOFMUTZkT2B6zXs8Y5dr3OM2C
YF+p5neuXtwJqXmKBUBNuqBSo8EARRCezn0kbp9qWas24LnCyZTC/4I+ocq6nYOyAj3IJVLxNkDd
g2RbXhAU/eWR3etyzaoHl13lxg7FOke/EeDtosRZfOiWUsC9/zAYisW/bjXXySRKrevm7Z2xuao2
M4QerOLm5kFo9+ELLLVmNwS3DeGxsyoS7dOGd9xZldwElSf3SA1C4SIcvOP3IKX5tqDpQVrRwO48
UDbGkwZTUBJ3ixS1+tRjHkXY/LwxI/cc/YZaeAaJqaX4y4S/flvWWAHWqTZXXBQ04O3msDecHcIl
bAmph8LGqvVAPabVUDDZtnABahoEOk7SLo9hwXtK3SJh3IOhR/+9LC2SKQUkVOTT3y/7wXDIVqcb
sn/wE5/3WjqlyJJenx05GimhlI8XtIrM3VeS3gv4NruATZyG/Qyyc/3s2Vx/TPctsmzHlD2BrXlq
MDgYU1GTENDO+A5g+S7No8WyvYruip53wE4ZhLSVXz5Oo+vYIZ1U5d0zti8Fcnsh2ZIMjWNXXZLh
uMtVlZ9T+kj+A0gOnaVPyww1xtDDA/g1rm1ztGgwmt+f0LpuDyuK11M275Z/OwcRi0cFpKqlda5n
+MmnPe3ggMnZW6VncY1vfr9C43Ijfqfr4fqXkw1GCUghYzvIul4zfx9iSj+XbGXU9YccsF8XAnht
dGDwMdeR8PAW1H4WUc061gPCSYmPDCbfYkXzmz8fSGXGTniMfEZk855qs9CqS/Bh37MhjJhdJNnb
5tH5NqSF9N1PPGrPxHUUuasiNk9tWk7iF6B0AIZO+BbuNUv4Jw82JJETAdPOiwdGZacTCVPSU632
iLaT1I1iPcRcg0FEAl0P979w38mGtYBi0WJ0I6jfOmBduQAYk2quDoF2cf6I5f9ZtNt5JX/SIO+S
PHgasR2i7yYlBs1XBXhwAOTEXX9HOzC2VlCH80eVfbnkXxZ7OBAC18ozj5drfnFAe7mt6eBuOPRR
1XqwCDAAzTaBIQTrVmIfU1Mynp/454nuBR+iUF/9pomB7Bd020PvsiJQGBWdBtChTWt/CEaXb1Xt
yWwvnLzmgOWwapSeJ50gRbG5RLNkzi1nStRuG1f99VJOWJgApXddMc1fZmns+M5Gbr5CbQlKTW/w
WQlDkIfryKOgPfcShtl5qtuN3yXb4iiGjrbWnwRRvWbsISaG/JAq8b0RlVirsoihcdcXZrAP+i0v
iNycLcY0JGmZiPrjSKW7XnfsAuyZFurYJ6X+FroM6LhB/RRKVcRMks+f2Z6bcWk5sUjOontMRNlE
TAvhL9HBWzSTqzmgNSmWvwoCI16oVoM2s+04cjp6iYOzZ3WSTdHlPIzkTpkg2EcwGMX+o/unTlGq
i2Uy9l3YUVjHMtkTL8RKyqpMtcaHCadmCiCIYloSfAlhhUq0zVFLfqajeS/HCyI4YG9YkppvwlvG
aG6IAKpNIPpKni8e5tXJZ5wtHnZTNLKasf9PWrIUd5wgllZbekWT4fmYJYCkfzO/xXBD+ZKUIMP7
Cfso8SDQQLwSZPuN8DMFy8X+wTQyR2Elaq0nPFYVe3iFFolX+3dYE6E0c0tZEYG43aJIjoe7Gs/b
YNFwit6oPXXF0VaZ2gd9Cn55LA8Ss04bbxCoGQFVtJCoDuxwHAx96rEXgYjPsa4pmvrNWL5SWjpR
sNicvJSYYh0dA1LaU6yfs6xf5Guak4ttPt3dWMPgWvKBz3kvjrcJosXS8/t93GIciqE0DkA12U1P
VOPKUDbpI1A7RPLTxGSJWYovr9nmwAoPvjIUE+ZLCSxjAalJ44EsHHpXJ/Bgj3vcJzh5ecS//YVM
qk5oZdLMUlQG0NQEkyCIjiAtmhzTbDZsGvHHYBY3VtsjvkOH3WhmTSktgC5v5jhgI1G1hJ9zTLo6
aF54DQ4rssGNXiypCn29S+TXfJSv0obXXR+2CmBfhU/AEPKyoh0979a9ESeqMQeSWrpEbWVuvSBW
RrHN3+YNTkKKpVm3DR/dr7A6/VC2+Sg72aw3VK1v6n3UU2kwfusPW7I8AE+2KeTKNL/66fZE92Lh
T5nReKzp4ZVGXXPseEMzdXjREEeN+XHrCGjDMUrU9XI0mUWcmI8/xUjOnMCu8+JbvSo2R053j4rO
TyIFhe5EZ0bsYecsj5PrV0FjoazbIzulyEjgTl95SPZDiMqN5a3qoP2tTC8j+sXNhSsQJDtAouco
l0nRo5cO0ARBUBad+LVHLfc9W6f4BiOR1yHzDynIwj3EzXjryudd+g5SIkyME2P5b3y/J/K2FKuS
yTxjfiz42sdLz0VNPi6HEon5Z82ChPhHJlaWa6CDnLuSQFVW1JC7DleelBiIbfFCkpj4JUnJPYfD
1FW5PQ9dZg+9GRtLldWbfpPAIP4JfmKuYyby4b15hXNww4NEHRpad0n/aSXLhn47BkKrJ/kJzfES
xo8AgVd1krMcEFOqKPGyGiOzmriY0s8PfWQy7eQro7lDnkAqipcBBd5ao3GE1uGyPqWdqfX18D/9
qV8xTO+89Nzs0GIT18fUnirTUOwHG19mQWZE9hKQKN89XoHMRmVrtWv09bLlWsdTw6pXEnj8yDkJ
J+AlGY+7bQ0j9byUgu4/OAQK28OgGWs/olzFFnSchtqf7xOL6y14vSoZyNB61AE/21KhQglHi2W7
cKmyC191QY47khbvfqDcczXYmaVac4PAAB9SSabwpZGViSdhcfCiSBX9VORihTVOs3uZe6RycWQS
8O+UdjeeqoBsJKnAgqgessKlhK6HotsF2fK7MzLRjpelL0VCWU0Cy2ne9y2U/FkJldIu36ObEQ9a
WF6NebEDEF0SmklBbbdiyI28xppCUKZH8my6AxpBx/WTfG5b0pDCQD50CYpm9J6oU77oRDYaKMSZ
gndUxjieIlj1k9Y/wZMHWgNOtf+jkUJcgBnjBIYGGGmjZkDNtglOb5a7A4bEQbm6IKhLJB4kdPle
1IHxixsO0AoV/s4Z6b2ue2rSMkJgn3kD0R4SrDCILGUarl3wfw14d8D9c3Eij/ygr2DeZAneUENP
gq7ez+mC6zjMTTQ9U6BeNcDh6dcYNXdNf7BmYSMdb+csfsFDcYIVd8uZLCX1a+CD+X9h2zykC5Xk
jYEGpLbE1rbf7LMUCn2+JKPaAltg8v1ArX+GIQ0s90wiE6KPbXcfmXOyse7u+mE24I+PpS0aeqmc
5uZ3f2fZ3aIDysuG2t8gcKHd+CI5IEHGmy0Yp+3y9HCQv/zsL/evq4zXGg6e/VSn87RP+nEEHEuP
1U4WUvz/Ws57GzpMgAoZk5PovteXey/P1CEWO6xALNySlhFkxeUOsQHvdDRtJizPh+GIkpkQot+Q
8PUt8JYQkJmE5FirfkySWjbvBDv8ANwoTHC6bM/ofq6sZjqDHpl5lz2JjNlNwsEz8MzywBChEEbM
8KzkNbURUQvAGhCE+J/hztNnyU9OgiRfHrYfTX7Vwx72IfyGQVJ9wh6JPQikzG+Gx+2aO7YEB/mx
TfdCr5LccCI6zlioNUdlEvKwVjFFq1fmj+gqHPPg83o3dqyHBlUhhqyQzDMKR3BRLu6ltZeAhggU
go7LkMefU1pgDCHpyObhhFCNX+o7qk1gOkCZdfi5kRhjBXJdN9rRIO1mY51wNQPA67EpCVkaI7wr
VfqAtsPli196VOGsb0YvMBNt97kqxWhnuX3lNnALpRV+A2g2UxPt7KnUXyW+RuRYF79uo/YEzyUg
LVKFukY62r/HffGiCJLWKiX+/ITuXifhkr+E0XoaN/qy9h9YD5cbkOVxcLSLMfmZl/hsKivuV7Dn
RFV1kmYErhae5VqmQ2BnfT85EH/pluV2lXAF8O+TZ/7Zbufx6iRYXkjGSXOzJB+m4TW56udAQE62
ga2aJ6Sor3w+x9s7DM/EiPxani4tmoclDt8JTdPBeeLfdGPP8GlUy9uJ8oKgjhDzcba124m7L5tv
mDDsTRiHRBSH6DysOAqzIayb36ps/aUFbuqE0Hb4h2OENxsqZaz+y63ByPpldliadu/qYQ2qz7Om
YZEAcbTRbMAR136/Z9cVyu+WmaWozBxPJxt5Sx10Iz6HOyMcSTri9KEPcjYCmgCakis3aGiyLxxd
1gw6kqW6wsJ6HUe6GvvMhfu0H92/m5TVyqgiRlS8PVGVISzS8jyeYy3tlVQkYxgGWQlRu8QOYUaw
UMtTipKQOc5VdbMDyGXtwEqMe7BS6jY30NUxAXGm6CdW81w/CeXlWh2nGxg8g9zSNbuMdhiSQ5Vk
WdxgTOZ0ewwiat4FgZ+cxXleq9Sr1zb77+Eq+387PUslhKCYaOjhgzOdK6yd+pRF40WHb1ruCfvM
M2YHhDP+7hOi7esaXJ2yIP4Rq3KU1cRSBZa3fdZUJtrlQSi88TTn6hRKn7VC6IMcBgV3iDtYGsta
h/+G3dJxcHJryQ2iNN4oZbi8lojxK1rQ+bckHbVeaOEgHqDTUFFDJQJswKjUQiaKlL54Jz17qtQA
q2diWknV6VUio4vhFjI4dpOoEWZxniEBwbGrVONwEnn1i6y76QTMHsWfLfVsWj7M9ycJ6HSzVEe8
b3gLkSPU8UPCAKcHYFw1dYt31aLl4H2+U+Fdn/t/94q4iaCTpKkLWZENN9g3FLDwOtLtx6D1slXW
+jC2z7Rn6z5HR7e+StduJYIowUsiM8A0sw+DzTMDJlu5s/7Q5e4+Kso7eP9rd9kf2g3u+5nYb3m1
gGk0KmV9jLWV39VXISTN9BpeyZ1qoN4wAsR4IoIHBYkkGg/1HILlyZ6LoPOrbt2Kj05/+vShAkfO
gDeQclitx77BRuXzZpU33R1mERA5LMH5nlfde+g2VwWU3hPmcIskk/2z1YWKipQOmf5n75lgA+LG
wnUFxcnhRdVdi+fFNuu2yeN8acqxUPHxC5yex0ue7FJ8FBrcKbfLchzrkhf5Evf2+k3+cbTDRKC+
V1MttaJrmy8LamNIAek5deFpD8v2F5D8HEeTMSeFtRLatLi3yFfC5+F3ryz5F5tceF7ADMxHqbWv
S2UQQJmfCNJNWmytCUB2Cm9O654mG/wPJjeQltHB0LIB484BF4bPWjzCNnyhO62ycRXrdsEOIqhr
zb4Ao1V0ZnWeFqx6OpaykzGmViRdecI21KepFrD/7G3OlCtiWghZlrAe9fydPzlnFGPakfRnQMlN
15DCQPzKlaIB+zbTemE6bU/qs7T6DHuSpsybN3C/in2i1lb4ovXSJze2qxRcVbvUPJNvcNCO2ybq
RUsHGkDItUZoRSnzTXWdX5v7dLF3iZ1EmoGZJ5u+bf8r4bxa7sCvkyMEJPAqA3n6gFkfN4nfgnHS
5bAd4ErBvbxY7AZrnIz4KlMuuYL8UFDOaMWi1GDntu6DRFpmTgGGiWgvTZFZRmYhZ4MaLEW41X80
pR82kLigTFHSh+1enZBGu1kYbbia/9vfTc5IV61ZXoV7PvzGDDuHtdj5VWJ09iNctSYRPpOUCizo
WNLEAVbHhtpdeRXvm/6Hoo8muDvjJ9pFD4t/aq/zT4D/hcxau+EbXM9B0OzMnqW+n6Xa8nsLSELN
jeAjEiAuGJCKs1hUp3enJVICNmRbQwUjLSYlAkGFNZ7VA/Tyi6SfRIFnpxRnPDohuy90xxlZLkjL
6XgI55rLRwRliU89jnb/vWgzHmwwq6JvAqCaOk4NnldYCGDtqz5d1/7ppGWpMVwmH5htT4d1Oedw
xaYkLc74GKA9+U3NLwB0nWwyHPsFcNpuMP8Mr3nS7EtsU5p18TCHsxy553otlePUzW9pFFOIWcwd
0UD3VIJFkpK9FvPVtH2ZllM3APkmrylPxLqrxIQJePFr/HfrRwQlNHuZ9jG+Bulzcy33UtQeBlcL
JUa/H+Rbb3C19s9xTbMAWu18+rIGo2VNrgnDOTPyGQDS/jMEkmfmuNHbpDbHH/VEYYLXWhTnkf/t
WKbAEKezJgSl14nKq7/f9esgWHqUSFOGQLYRHq3Y1bpBd1oDDDsseI+YeXAFybeDu1v4jYjKxIRi
0opBPgmhenuR/hEBAyWtDG8VLIgFEAUzbrXQzVO2v9A3EvyBOL16FFRdBwXquoquXViR24voY6S9
I36jSpW7mIOdubeIdLBstA0FP8t8hh/sDjuR7pQP+XVZHCVPS3Iny2gko4McI4URrkkQ/VZX0vBP
/+AOvh051bXLOLkQTNC+ck6oYB7aipDwEUif1b2v0z8v2cIQ9EK8DDbViR+uSCC8rXj3/Oz+TJ08
7xwc7KcRVsAfTJSr7A4nPEcNMr9OEkVIFbhbEGyMJqkPvehFGporllOq/DE5a4PkPFA4bRonF+gO
SqfUCWHLV7yNeDVAjR8dLpy1J9yUkmd/5fl8naHfVKDcURRpOpKN3u9GfhAekU48kozEa3BZLpJA
FSyCDNs7gonBlaa1urwoz43EzkAHDlK3Qc3C67/iKmaiM+yPydt88vI4qmnkr9rmdta/bNrH4ZWz
GjZnGzPmMfgbOoyKRNgsiQgpeSIzx9A7NL4X6dJCyV0Z/cJ0qGcaDV72FNUD+kpsU/u8gJry68Bt
vrNAbYfmJ+htuvZwV+1xtRm1gaw9ySPEEuVHSkSHJIKhSW2eDnQp6PdWSAdR0gWoYjjXTHNTTpaJ
aLCXiVLe2oaqoyZIPvaCnlDQLmJ/hOnWihjEmlAb6EjJVbW7KTsRk2mADkZUU/NyY/W+Sh4burC4
trZMq4zv0uhPkFwZBGn55sjF+D7QHroKP4pF/mN4w/Xa6rU9Wu8mnp2EmSP+/BLADHtDtRvbYh/l
hKtZjeu7fcMotPM1fDGVV036OeOzBaiL28eFw3cd8KAI4SmHF06ZgL5MNtC7IHt3XPf0Zg+XtwYE
nUaKyVTYny5VpnQG3dNQejLDyVqG7BUpY9j3mYMbo1jfY9WyaXl8G1PULWrr+5hq5yNzVqAihdN6
tXTS+V5wSXOhqmhkHbuTSR3aoYZP2P3W4Zx4YA7kQHjOuAtvipodjkSM690pIT594sEZ5MEXNefC
zF4eKw1We+b30GobBp2HHjqeZiMdtYGn1PFeKYiWUq+dRo3s3cplmB3BhEUCkT2WQFAimStogpn4
Lc4IqbCd12tXzOYsa6WlMp1Dj8Str4MSoMn1/h1s6yOc4/5oowFsxZnaRltQfrov1HHqkDqfluZZ
6H45YGUaFrRHONH2RCkX+MUFqeVdoKo9COyvROUEYjDdk+MlD3t2PhwhDSQYlMOvNw1ejYp+RxLL
0nvB3C3olIkLtWLsHmvlaAZtwHzA2cv8vtWXgQGQ6OozEdKk7JmkzsEAB5U0bWKRnYyQebC3QNHm
waYY4i/3m8t9Cs2HITB8FCJw3x6R8NI2gqyLXGj9j2L2jj+LktUVq/xfHghHU/LEW8Bi8ibDTojx
kS7CTX4XeB+G+aj6H08t1c/BYVA/6cQytgjGoevZm/VX9QxGRB1Qn3cwoeCW1drHaS/4nGZh2zbQ
inKs4DHHo/71KsJpSGsmEb4/Ptkt2bnxvpvQisYYHSpeSXEXON0VJrMB8BPLNQRhBDAMcTbJFdYb
z2JhaoXQvbtRvMbHTF5a4790p3t9MmDsjlUieEGPZJim1AJMEm5dPupzKvqHAn7NEywOLgJchbcH
BfKDW6DXOMH8D6KSm14DhW60poimoXb+zfsADB+auo8rKdZ1VHZT0docC+RLItSAP8UDqie8u+Jc
OlYY/rPsfcuMdUXzeaqCKSSKfhNpAxKUrsUVY0/NlOlkkFkCvnRLFzmraV2oDDpuGyhQs5SlML4S
f33b4u5sy7OyGOdxudTeHiECubL+OUMD5Bz2zN3MzI3o1V1krTqAGEDmVslM+uugYYcdAbM2HU0b
ZZ2g83Jilx8eprWRN4bbWzdFzudwtkedt9ckLi7mYkVLa3ceo3QEStg2fU/B25qOYHI8rxOt4WRa
WovtaEpqDRuuWMv/BSbHANiMJlRgJu9rRylJxyn733YWDZcyFqo84VH1gC3PliLAvvvoUeB1mMUX
z7dMkBCkFWTUC99kgMuZsxIyq2ApMTDDMkcRCAalHMG3EJ9lZxmmoub9hI0YiDarilq8HrYNL9Pt
zmjCWFw8Ot1n0kCk+09StPIMvcu7fg+j6M1SqpQkkOyJrbkHK7hXa4cYdaJvFRyYLy++a10P7eZ6
oM0pIMn2SquSOiyMTlF8JycMUpasNsdJQrIhNWU49Xu0hRd50912i8ucDNfopqFW2ZZTpWkhx6GH
leLaySFgC/+Z+QdzUDLsYaovIXYyjSWokcse7osNyoeWeX8WN3Lng779wHgqR/oFk9uXCngYoX1z
k5aeVV0mu1z26Wf8DdjZ9CsOB+wdyINqbzsbnJ+FjObw941Ort7vqE9/rhHOGOxjklkStI6+eo7K
sMLpJiWmQXy0kbC+aYvv3dK84meA1tDGwdZ7/w/9fEITh6S8ebnc/jMGxjrurzfSu9Cm9XYAs2U7
yw84M0DLA8JeMqkzMmGdPqOap8Bq4n1rJtvsWvcpWwDHFzdFj+znhG/AJpEwMpj9Xf2CjR5dlAY8
c+zEBK5IGJInEx3IIFGnyTNku3t9rwNMt3dww2WHE56t3tX9TUwQ6t/DFp1KfEFMr1kp5WFnzXdz
Zvgq1L/nS1aZfhBpkYqwSWnZM+nxvxVvX/3mEqufQ+33iij2F98RD8hVAHakaZPiIBtccVGK2XRu
E+kXy+hxirqDpEzd6RfqPmX1T4FeXnjS9cDtqO9y/LuEMKoe+NfBNDGonuUdBmd7ayt6upqTLcnF
p8jPbshyMcERg1g23MKcxVRXlyMMgeLQJHFIznBqLqKIwlqVbGrA7qnOP0E74c5s7p5fILcbf4aV
ZzdzkNYi6b9d9SConslt7pcx+u2ZHKzKyemiN8axysknUX6X6xhTTNA723Y3epgHkZfVBPmCPjlT
5+yVK4qKBPe4DHRKZD15QEpzuz0sGJsyWy4GqxdehGoxorELCYToaIiTfhXAmzDwurygvWLePvyO
LEsoaLBo0eZVzinIznCh3d7RGQ5zeYnVk2hL6lx4EQRy8O1wMfJQ/WJI7UKJx/02QpxkV5MO/WO3
+Zc68AVnQT3N0m/4OdpNqmWypBK9HAvPvrFi4l8f0+n0jD91Xh/pXvOIiBuQ4I7NrHSB6ccgmjmS
Eg3KlOaDYLDAKOcnhhTXakxuBOItACOVolfCKUP0/nA067asN3lDooGXuL1LXGjJXdbvCzRGmOVM
S0IDTxrCoI4/uKWqjMafCiXj2p0jefcJE4TPpCuEjdHRutv3zxI2M2zmjI5cFlQEHtgnHNup1Jt2
mDx4DIG14hgTJtd6S+xAFLvpLNZJ7q+m0Fa1biigetfxcwMmE4X9B/8GV1l+i9msx+Q8QdaZ+Czv
43GHlqONtsA5cO9zhIhq+nKg+ktHsNYKSsRp5g6Vf3NkISHwiolJg7/y0xZL4t6WJOx9DBAX8JQi
PLxBIGWBVCRw6WtpzKae8fRFLcwdT2gRN1a6mKdQZzAT4gcKNx92OV63NOjFNOEYWBfQfZpERz3w
2PiZkFG1EgcJH/Cn+IAqZ3VW91Cw5//dK5XcfpkPmKvghfoED0fB8LFzfu4YxTpKYErdYFN5MkQX
AnTzSk5sGLllkBK+wBMl6BJchLq664TgGmbSNbCD8ugaXSMFGhz2RCXEMxTHr7sxcGWdd6fudw+v
oH6WixgtPkL0fNooRgzzy2H858eu6ToYf4mIICWqdNwjyIqVCA1vCzRRShZtvrLOi0T/L5wcN4tT
hfe3y3jPWZB1b5RGRTLdRKGnYuzcWaTQAqyw0BSoUuvUx6E8piYftPkoZXJ7ZqQxqe/q+q2LLLne
QnRXL+N+6b0fLOkoW8HgQxb+KORKQQ8RfzVRCO1k8djX3bX+guvufXUIBMCmef46AaQaJURzuDAc
J9fEM2XB6hYJWF9IN3++hrlRyHYhAegVl58s2d9QIi6RSugzmFR2w5ItSKCb1aph2hX7s9cPkB1v
seAQQcZ5PE9+wBONuEr8cCs8648SE4NrIscNSeHgWnfzJKNhpTr2+rr/HQm43GsPcIXCq030sx7O
YQ5JVdUM56Kqb0DEx7o8kVSk8Cby8Vtx+hXANpwDC1cs5rR4LSXflMtnezg+NwnRYSWllCRmYLv9
3YxOnZB9WwxTKbkQN/V+Z0tp83HOng4HkNpuAGUH0BpoqpOoKJtPtcHYpa7uEO0Lp+BTANsBQ9sk
nmZhWqrYskvjALBMBP5y3MZG9yV2ya2Dq4vzfI0HtDdwPFJ81Lkf+wOTa+Glu7cXI27qPIm8zeEq
yyzU/kqTM+KQ8fNj3dG5e0Q9TJ5SffDnaF+2PGXCl76FsqaYxmMKSeQynjslJO5zwJZ3PaGyAqpy
tyDLRPR++n3eRO1mTj+pVTr6SivTtOq4KRqtobkU+jMhEkd3a6tWLIQw8twgHqQ7iEVgq8unGypH
QxK5RKMYYT+hRhXUPwt3CgeNR1YQ3UUBfM+pd0HjCaewfs71LT86T8adhX5JREscVKqGiOZHN5er
gXXkgMer70s5g00HVSPP4TByrZEm0YQG04naqwjWihO0sUhEvZUdu/P9C+Vrqx4sFKFzzJw5O9OY
2WOPfKcADbO0pW5aciHG0Qgm5WRXw2l6f3hp3DNuwEEplWW1Mj14sqIQUyy7E1vitKF0hfYHDYgm
GK+y740YXY4LK8vMkCYz5q80VOZ6E4eULuXu1eFNXzfB+3xg6B04ZZYmHKakkUlaJ/NoVOBaA5b0
AA132hXpRgjbumb57u6p0dGizrr2i+4OCccJUY+kCezbb8KVv1l5Suzr67b1F4Sz/5pXfxKEnDt8
bCUA0pP+12sbMy4YfrDymYlY7OnthVvjubU08p3NSSRpmvYyxRfpJc/U/FgfQ2DyFXuzNjom6+Ic
x+mzqVOkZ783T8YLFiDnZP/b0GbL2x3loaSYcAPUnb6TZvYWdIirefL1H1jn79VBccOULBBqZALd
FoXdV4AAoP9h0wzwzXK6wCD4DGCeG2rFsoDftu0kMLlWRYHybok2N82b59v9i3FNLNXKH4EQHjS8
hGKlMsHXcFy8yz9AKy1zkj7gSChQO9lGSLqgn0Qqlr7Tj4hWILSoDYvRYcJz7+oxc2Sn0G0jDuoR
yWICfIlotau7ctZ7AJiD23n917ku6Kg/+lEWp8NtL/UlHv+LsgsoOigrgCPJ48bo9qJ9CxVDy9zq
YS2H6NR3vtwLRVEBdkf1jXyL+efQbQ4upTXjzUeE9Wr1vE8dniocSIQQ6NRoviIo/6T2b943ULlO
Ke+Vh5HVwvQpHLG9zutwRsHzx/5+7Af0S8ddgyPksmzM/fmmwy/rCPgqm7bKyFDigamMKzQMNGtJ
kcsQkSbzaG0x+ehrRZtNKxfryCGpRgEJiXjpqsXCUX7IgFCuEsHBAZAgD2F3KAKL/9n6Im1jJzZj
WIu5aOXNestVDbNy8dhc78DqTyt33e5EZyQyg2MPSddeC137ElQMcwYtJspUvVeNhDZ2EZM7Smfg
y+Ugj+WqQImrLf/4ZmeQI/2YIZImTKa9YZCO011Ac6Uv/fMX0KY3XA3modoH6g8mVIO47vDfc1sP
kpw5TEamCzMcIL8cw7qLRYNST9NpBdhNKi8U2IdqnbnidJLLHpsPMIPgj7Sf2LCCB0W3rfcrJ/jQ
duxGFyR7fvbA04xOVVjcryZMbwi2K6Sq6U2vKaTgfPLd+PsFGFJcmXSVit1Dsfrs8VZ2/8sG6tm0
SxYUGuZlSu/sn1QX211Ef/D3XDUS5q5KVlsvfocxoggqZzmz334oa8jotjUpUp3G1LT1Dc61d1v+
UUM3jeqsaVXoHb7Zrz7N9WdgsY1IHeyttTYceZ2GuTZO3LrzifM8yOwpIYKgOCgnD1jvKchV13R3
V53I4elMX6RD2N08UL0H12Vn+swD5zsfdu7sVppczjtygoFfeTEnxryKpyoxJDzeuX1Dv8iziw4G
B7caO1Bt//nEjyiNHOU6IjS4SXc/OQ3vwIiXGMnQKXhw04oTEmMJVkQBzDmwW1VatYyal2FN7OEh
pDrSNT5ea5276TszoM9+hddgJNZbXu3fGRHy2XTKrF8pVa0o21PvTXxxZZ+KOVbyDOK2X7cz587t
2gvNXboqn273WQ70OKlfzX3VriFaGPoaViTz54P0lM/+bdH830uvcWHMWqZlcnzmuu5qI+BwktXi
v3mG9mR8AysEs5XRzwr9xTeiNWYbn7g/G6PBt9KPao2wUo7WzE4M7IGyj/LByInwZ/YYuUCRUrCi
kI3NyImgAyxykCNFRKAqqZutp8n0FaEU5Zl5KqtB9Qv/MGEqAHyqAurBaaQ7HZNqRgbkksC/0+TW
A8YD2KVHaiGAweb+L/4MzNJgfgVOWqYfQIXhhrcPc636IJGeHd93cQPVDQUnYLlvkVl6xn3RdFly
PGk9NUIkV3L6WClHCj8eqJV5VT/lPLgEafZPyAVBP4VbGhilUxaOU+tW46QVI7shq11vIi6qBalg
zmtm+Vd7OsSD2fWcQm2aqUGL3oq94TW2FQEtbgQ6EolPatWe4F/W2Qrv/W/fc3SCQVLcCokGAur0
DJcKtRG2qKZnnO0BTrWP9NlIWT2cPua3G4g5h4RKhIqyc5lzq8xEz6KJUrt1QgB88KWCGMuoB+Vs
PTv1SD/Ro4a1CRiTG6f4Z7O6+9xyezQELPZufJbaAblf8pQWJfsD9d04npYNLaK+r+h5TE2ZD/ba
nUYRSG7NTJ34ccV1PL4wXEaVvjkLg4Hrw5wk+UjSubLQ3OPSqyKixsCBqKb550Up9sTkQqgTecka
HTfCBuJXYD+sL/WjmW60awm7VwjHug33Bq60OOv/BIuThnCIeRILK0JA7t1ssf5fTivgkbNsXq4n
ElmGiWFhUXqaesiWG1h17nhIfblzsn249sUlFPnSF3y3t/PfQJa5xV0V3Y4zDF2S4DHcXHQbNHsU
lz26z/v+dSB0apAdqxrVdN5ypQu8jJe5WB9VcUzvnmcJNfzI4xImRYyRumAwudZBDyOwXSCUJF+8
IcR8VasL9NoyOxXiMlEIFjAn3EuXFpaMfsZOUOCmdEikpe6m3ZLzzBjGlV/WT8GUeAM70l/W0bfO
R4lSvf5xBUYygdv+HGSfDxAwagwRDuOySPNxViH1C4LCPjYlsZ6OIAz0L2vuUc0huTx+Vt9o/WNh
/bZmoWmShweU+LJQ8CjChXmnydNwXKImjxCDvIdEEEjb5LnhPAktHtZQSnplwq0jaGu54VApcqce
r6z2jsjQR2Tp3+n9hMfZAoqjvbl9Vp8ZpwkCcX0J28jwHrcb9V0LBFeiZCyiWFvn5KVoMYMHf+/q
8ozkPBxe0r1xOwasVZpASOuyRuehtmbIPui6plHJUC9mDhcYcK0uyGE8beDb9wmSHTV+i0ANMnBd
Bkzg/5J7/dk+rVyAD8bFFD3yNdvEhFWVw++Y597kUGGs4wtspqCkH0b1QhdFqlPAbVzTHBQxCmv0
woieoOoWvOdC3FR6kiAgOyvsNXYPDsCEC0BiN1Z4pVvEgtoQmDPzs7K/iFWIBI6xhMnZp2ICLEKv
quc2Ovbls0XrSMZPjmaqFj5BIT6jpUU9uY+tf6Y6Yciyvw6f87wX4CwAyT0ceKYPhKuqTpozt9n2
VS4XAYtJeiY60MxClPmrHI/WPvdAo+TdyLigVIUkR0QaeyFGNCDfFpzHT8fqmo3fJzeJXs9PlhN7
2tnkmisCM2AXdW8j/cPcUcFFGu1JNqRNr+aDruf1gzNTCwNn5KzvIRKOSp+fZTtPDKoNjWVVEdyl
/TTjXk3llFHikqMmy2FeUYWSD8TkyBykwRCXZvzcQKNYrzbTeu31Z1pw65hR0k2GUBjGRsurrqfx
ulNEMM5C5F8OuyKvZQei9GykrQO5LAN2yjzt6MmqaM4BC92yU1xjwFRpNUE4KO2nXpfxTPpifhXm
unRDTCmFU7VMJK0wfGuwYQS6AhXzut76Xj5CeRk6eGwA3nxcr/jQ/kdH0z55rmWHOeic7RD++LYW
xv1oosuTTj6rC8/5kXj9JIdfq8B8Hxdg+g6YDAwhdoDwOIun5iQvDUGH0GhOpkXpgLgxWNytoCsk
N+p4Fz7k8rmddC63td+m9ShmeugKmgVUDrfC4isq12sIDXyoZDJGmPXARbLcQwJ6aCc3YCh5ASUv
3rmFcCAaCmetLpSLF2khoB0HmmSgzcnFoAuJ2IeYp+OS5eN52GPny8dTabB56RO0yqzZduZ7MHGE
8G3/hW+pf00/JOadS+98BqrfKkAm1MuMdukxhXMyeBL+a+XtyX+7dg7CtcE2p5zc4SBehRt6boGP
TpB/hukedYbd7sD2UpeqL2qVJdNJvjs3WeJyWI3RsE9zHxMqA3Fjq+bD3yfl7H5QMdJsfyZtrv6k
qLqSax7IEXwrRPC32tTdFifg5UZO9lVqV8dIUagLxEzdxF4hKPWGScdbF/nBeIHFwKvVPwTMypiF
kvaZv0v2gOjiLGjifAsaAxkshjpHRqpeEhWAOY7QQcRcIFtPD5y5wnMmqzxp6cUTfiu2T7Q4e1U0
aKrngUacQXF4sTvD+UX8MhJWptxvZpqcGISqrZVAtdtHbpXMt3jG08HtCF/As5pTza4/p0xE/0GY
Avu3hkVYTIMzKv7AGNBSZaX7c+iWrfyPRoIPTJ3fjb+4JoCO8Hil12E/fa8XzcewRvP/NrA4segl
mvG0gO/Y7I5gzjUBT9Ovz9v2+X8h7rJiMTKGKuaGjK89EeygnlGhIgqKUK7DIa+3Um0CnrckA+IM
thyCHpK5vU6WCa12ipZjzpVBLlbL8cNsy138+sv142s0kytHNVPGj7BCxVtD2BCuo/EYrpK9focK
LoT7m9hVxQJ48DrYXsPJR+hqRLEK0i3Wzy84AjTF/PjHGca6zPYVBymnQIZAz8ZfFPmPO6Jv340W
h04riRxKZDN0FLrgdrdZ5NPBzYhPw90H1uxfFqZOLwpGM/YO7Jej7XvT+IhoDfZn9m/er7c4tfjO
VhUekbgFxfHdobJvsw0wztIE9cRREjwoR4GDoXcGdeZQB8FnS95atpfbMzvdxLz+k4xEaWcVxJJK
iVoYb4L+0JT2ADqF5F6MEC+hkg2ceQPEQTRSyU4q+qycFDfWQgu2f9MR81vaLc8JEE5Q6EbBeT1J
sm8VB7Yc9nSygbTulDEbc+64QbKvoM//hJyhBCZJU9N0oWABYmNPO5IjZE7x0LBHYiqurHWEw1zJ
GEVgEpQ3n8A1fQAVaAMEkyF04dvH+ZoV9KCTuqBGDAmyZzQEbPPsrtIQjHZ4kBKgVTFD2xfRLgLe
eWxl4FYQ4x8b5WT4nSy6MrDAJRXfoIWGXxwWsvGxdy0SVdfKgX7aCY/rbNJrE/+wZ08sC7sNQhcY
Oaa1taRbrliK+bLgDdIH8REg/QOixHT+OVpfFF9R3m3/VpBBERBLuOvQRR8hTZ469avkrxuZSaxo
QRS67TqhQB3/J678kOUGSt4cebXy2Pxoh8AHcF/H7xmRuhhaJe8ihEWocIKMGZJYZNopial+lXsy
za+RcGoWo7zWqqm+/zsjq36+kNfKqSc2DzGK87XGBuYYBc1RkPFflnwVTYeA4KjeEyyhU5rMA6m+
jCn2nSShXP6wPtRDcwnOzbJ6botYZkUoGTwEbDl5RUhCNvOJtl/OIYMLX5wg76V56LfmXGuaz3ON
JG3AcEQr0IRWSvDf8AxR8r/ROuUn5nH82zlJecMjQlly0aeMoKcJmdHahkh3dDyy7/GR76cN+q2I
L+v/zYQ4JWPJzLyLfjdV0XWmKXWkdjKfxQrD1xtZ5oRZTqHaeX2wW2zgTzuF9nXJfDVcLlmjt6um
KwFimUthABAwuIXCBjsrp48lRSm5gj2se+0S0Xof8CgWZg56a18KR/qy1zadmP8hkzF0goDJBBvO
nx0Y35sq1lBDrn7W9VKZI9by04HnjHYfMQyaEmw3C65yD6jpqIrZ10MIDrmYAoztlQuL/U6McNxL
gaUHdhxt0c1Bmpl1GvBQe1c4Pm75VV/OhoYeR9RqCJU4W1ffj3fAUVXsppIT0IQu0gb2JjfCu2LI
Q8J4vsoC7djY5Mezw20Uw2F3NozAlQA1aI8Lhp7kGNKdcv4KnxwqFscsKKlZKxVsKHGiT5885qLv
xAv7CVrtiVAeFYjIhnDgsh6wm/gzmntE3894lMbDOMu2E/TDs5VRi09M0MkqzYpLQg/9N54NTZJn
xLDWlPXfY8oBYMntsyk5b+TO72uG5thudOpBW2bpGDkuhzneCt1znbGCKur5SEsjWOpJHirJTn5t
mGdWPo8kPXiihEyUcKv9OWypDoiq+YdNrZgoXWk+ery4QqOJSUh9sKA81OFee9VTjllom4ZxMgX3
bkKM+DvCdNQs3eTQdo+vilVfrXBOfKdnIAYz4WMh8YCBx34YCPUSfHHZITUl7buVF3qSg7yXzBr0
G9+dJg63ZmX1NYVy+H1XqpWbJ4tkN3f4JrXV72mMOmxcURpqIpBfz2nFliPhd5NYsH/J9ilmwTIf
vTzEUNXAsZXWXepcRlqNSrizVDypfDrNgF+c0NQD0VG52mAqPq7EKkzFRF1aQg5hfZbkHkGm7p3R
ZAS1D99pxZwqRDtOAVx51QDOAoMA02JUbyhzToOyg9FAw0VuxWTFZB+AFdBMig+0b2VJIi6S0AK/
buNOmibSLK9cIAQXONvVxi23Bq8yc9CxNHNte5WjP3scmTMEcVLPykWUv6xqIM0MhsN7u9enfhhw
i/QUJUa5vQvaLMyBUi+zzOMML+DWtkGqnUtlq2ibzAwdQd/NfZNRQVYCZze7yiz0fPTsbT+K+c0o
G9x8uNhL/43FjArAHfexx2r5q3HNoMDLQNz4uGM2LMkO2+aU+jxTsbJjkao94pOY9sycsu0Gv+og
O3FuwYmZv0flT/M/vzFhRnEu9NgqgNGglW1cp3J5vhW26pflsi4ZjiskfnCKtqV6Ipqjp42fZzA7
gerv0Ll5SEtg5dDcmIGcfpZvNYrYdnALFuXLdKmKginqtiMx0pc1+LY2xl5CiSSFecFkPIKUPtKZ
5N1ZuzaMbdR+EApL6mCLmkKE1ORo/IjXI1Rm2/tPDlsoC88lAP5cQclkHW/LjLShvN3YPXqD6Ykb
K4ZCh/k1XvMDSQLkWu4ev+9VNeNSmDofrjVryp9q1zASXr5JxHE/WTvNWHYpNbcKYW/TUr0IyN0F
lyaarvZnW/mElzmWObCrObiKmVKcWU6wo975OSYENcW4luKQCRKXvmMUcKDKNvANcxW4bsfQgc5d
hx1e5xAryn9+MM6QKZaQOGaWwuf0ONCuIk03OHQqEaPKJQplPUYv+psmrqslIhjI8IK7UVI2lUMS
Wz0l/32HxnTvOHXHcJd+GYUher0OaxKB+LhxBwCpQeYU3PpvwTHSnvw8QDARJvgH/ndH0t4n5MMe
oIgjo6XsXwJHZPAWArNt/YhxZ/djl0hzGIUoXH66vRH4i/1CxaoTmj5EFld4Az7iE/1j12eHP4bq
uE2ov544OruNtKxHjWe/tysZQKD3Zq55DobyeC9XciQhuTA3INZI8bEBMV5iXLefkLQMu7abDyAq
m/ZV6k8n+dCCu7VGauz9s05qCwbg1+TcQnkx4qIoVSlt2ZymN8bhzXtpzdkTqAP8wY6rUuEv4Rv0
wdWOdda3fjbuomf9TaHTX2UumQTNpZEeBoHNWyqHyZVn2KT+C/rG+yKuBtPtl3d5S40Y6qaXQabm
3sTP3FDW5fQ8RRYQitW23WQga3VWLSK7SijJvWiQWQPn7b542bSVMLYE0PLcOaKGihUfC5UEftje
TCxtEWHHdGOGyqsetKS45oQHZF8PxuKGdiO30nR1nXO3U/8HNaaHTnUIoZJA8IQ59D+tOfF7AyH8
LHizBpQF5BvqL8CFhw8606uJ6QwMPlYgCZuejfJYkizDlhNbsPLchquUX2Adb06dVkFO8rvP6Un6
M1YPw9HaKpshfE7eII81sqHvSpbKQKbw04y/vqUq4oOAOWPk6FN+4NcUqwZT7vFXkpMVa1mVFPZi
GKKqZvn89k+mDzXHuW6zkU2EYoToCzV+J+fXkXL9wcp3Qr3Ym0nkhzKgOjdO3IvpfvxtQ32vvMnD
yMm3lQF4cISyMy5Zve3hk6ROPRFa9q3COlLfI5dKWhYcc9vvnF6rantWgxDLRvBZJ64tRWnGQciJ
goGRlTm0OzBO5CVtpWT9lh2zfpunapBbJxT0z3D6AZ1swtVHxDiVXaTs1KLpaDQ3dppkFiQ1pLR6
+se0azN+HDgyNpgE3wlrWyea0Uoj83pqCCWDAUwnhhBCocSzc5KpUqcZoyKKBEbiUp7MzQvsF+hJ
ffelIrhBlEA/Plz1noMjoBh9owsbqHQt1DWMMl8zAfAXeUH0Sf7Pe3/Me7MmmYs+RvraD0PQuGIW
+kUwSohplrtJGZsg2Kdvkzm3boaT+DT1ylkpzk7FSi+6HxZTC+w5CK4yy5bLs/8LAyTYuWlEcv10
Z9wXnzIJ1kKQs09ErlwuLKEdOSy+0xULg1lh1835bhGvEKdF5g1T2vEOLdRHwXNUrYb6ya8LwEPw
Uu+Sp+qvhxjY3z00x64kaNG7pJ68jHyI1dFY+a4shR+koeDxm/B6/yHtkDK+M7/khj+HrtlaTXmD
lbhPMWj9ppemxWPZuxeEU9naHaKZ9GT7bbAVZl8SGif2/mmtT2VUh/Bxyhz/aEVgrTZhpGRA4tyK
zcuBCnWv+I4oYiCPR8o7wXdtJW5VUP/3rQG48yv9FHL7jjGwhrobgK/kb4EIi6WxJWwMdGQNdmej
6ZqwGXogeu5978jK8H+3MnBFVJeGWIBIq8TyPBW2BobQR/K2KTdElxif/DcfXHjQkyqWgDVx15Hk
KijhcUX8vUcOyUG0t7NGFyhN+FS/aVr6g3igB5S0Rlcy3X+KBq/2ZOopj6MJRL/8yQb9Jg+CfgwX
KNrZqAH1DhxkOPFUWhfiC5zoB5UcC+LkU+mMw3TCB6MghoxzNXKKCd0dLd8bR83F7XLBZYcK5A0M
5fait+VYrHXrgcsrEjvzfuR9aWt+9ixsBThVQuPXoVGuOLyneWVK5ein2qM8KnUIzkxz2P//lixf
/W0McZ9IEX1U0J5weQnj/r8rtRi1tZu77LPR/Lqw5ZcOanyx2OFknA2NJ/sD2p4jLmgjaeQo4QyU
sTB/3GkHw3kCH/2yNkigfos97XY1PX6GauzqkqJrd9KrXJr5vnNnIGb50PEQv1EYJOflXpj2ipAf
lGZM/tyOIPVNMKlEZBxodbK0UmXX/jfyh+SJ9+5omaFMzMS83n1ZJNuAqgMiDnDZUBGmVJl0J5CG
ZF4uRiFDExKTH2ktKboO9HaVkx6mT39KOqzqBWXOqBrNp/0MIn7BKD/s1p9LgS1QeNIFtPelma4s
K0tnOxG4pAToOSYzNwcyTb9UuuJymT5FrT7pIKBGHMbmrDgDzQEVaMwqixs7yP+PwqyzFiX6v2S7
/jvi2NhOJVgM+1H8+lv6OSblaa9DbvgD7EFa2H+vJvODXGgWTYRqp+QQKMaeIJxRIX2Ahg5ft2FL
i3YDkavw24Xi0gZ0TbxpOAzEOZeYyxJTIPGuNDoH69yJyseo+l6XVNuKIWEQhW6vKa8n4zJbV6sq
q+TVK+tFvamsiFmQY9iBCfkA3ucBYw4/+4Mbv58A3hNoYLC6+a2xvsbJTaUqRbGTzBlDuqaa43Cu
OH4MGBoi+XXcbSWu1whqkE0UdEJ5euHOR+EPu9mxFmIYM1bImst543a96NIRD2TZqplQ3KKk+9Pu
6nlnWP2n91wdG4eV+1dpIlmOx2Pwc1kAkupIBE04xL8huvYrb8sA47pZqdVQDVu81k0IJBTLF/R0
2UFKikQl+hvESdspZJfxq28VNegLaylv6eDS9kpxs7DoB3rzo95xLTwsRGQB4YeVYYCj8om5/7Yi
W4m5Kd0/tB2htmHiE8K/NHU9KrkPBJOWZzNaxx7wWU7FegRSB30mZdLTI9EnlbUx9M7sigrXaZkh
FU6+EuE4kH71FDa8HooTrYj/N/BgKwl6mXaK8Q1RFEZCJJC5OMm/QV0P/i1dn7GeeB2daalg5Udu
Ved+OcWo9yV3VinRik5WxBREx4e/IusYjz1ULZ4RG+aQQAL/hZf/MA47x3Ws7QxETXIdeODjUeS0
utRoBq5gchQ1G9l/Mzwn00WDbWFtCf4GHlroFZVim0MW15n3d/xRye8xZxsNT91SEGR6dMEeCddP
k38VhWI+iqDsDKwSIY+VsVNwtC36nWLAs2KKs3FwISV7kgWW6X+2sd3T4xQzB5aUx5X/Cy6c1TfL
W+cY87LQRVNS4co7gnqaWup9F5zCyItmSSkO4V6Mvfmw0jcXOZZCtq7Vc/XrnUD10hsmBfcT9Wy5
hFq4lQFpo37YvzgowoaGPwD+fwQ2918+bYJiKmlmtIpslmOHxh7aXNuvY+TF+VFng5iQPOLqBpbk
m76wP7/qj/ndqIRw0MhtTS7DxfgDacSp2r4RokrLmIKHTcs1BuZ2ceae9xLcXasJ4b2iO8HRnjpR
afgKhxZlT4YwGOsosuLsw3BW0MjBXai/9Xc8kRRGIwZgatWVFHkzyf1J0K3yRA9cu07lfTz+g4ff
ouerB5efPRPPr9TyqalLPqGbyttUazDl+jxwhbU8/RxZco+x5HF7DwnIjbpT2fTsbQb5rg+UV5wa
JyHNKLMfKA//xjagnbsiHfwhrdXRfb2Ar0yR0sawdMhoXhWig+xITuwmqvsVMMABqfK4vLasM4Hc
PVNISz98qoqJhGzJcfqwRIHHvIEUcqiJyL+umdCIaDhadfEltmMHCMOEE8NWq3WDTK1V+cW+olBX
9/15MLMAQHlMZhcZtyCibtaoJo9cZx3fWXKb6oOeilXkvP9Pie0x1IkcHmcOKVXea+nFQAgUXPQP
tsiZXvuk9OEwgcQWohjd9jdcpIrvXNg0ALfsDtGswbHPg7Oz3/iHiNhPPR5ZJMsV3vM8dw7yYJrJ
lwocFfQNYklsbRVfON8Pe1597weCpHRvfyQ45wUS4bsCg36lzxXjLEigMp3+KUUIB8l9OHFxl+md
dWR2L5J70fJEXHcZsA3tC4BfsUVHF6qPLMJDLv+Bw8UMzsCZdS1cs/olrGqHPBO8EkeQPsnpBzvC
ZmCEwbxWLHYlEyvCP/cSMTYT91nywNIxS5XcU7kvZjj3lPp0aWfFLD7T7snFHvtF0W8IK+wRMMlh
wZger4qxOGNM2bzXH1skjPyy/kS8pS3RB6/Of9QHI9tdahf3PVzgRrILh6yWSuE+ebMxNHpoNgbE
Kv5iGjAAW98AAIOz8pYA4E2QtGgzfEf4qYzGhSmFBoCZ4loR75kDPQNkesg/VOXjKvSZBnra6pq0
gb0wFFW6tDJT8Kf55TNxUAMyhecgMvpTUJhdD3gF7z6c0AGktoX4u2bC4mtHra31kyuL5h9HDM3o
NonGSbbOAy+FzbV2bE47+MP2By/RA4M3iRfAW3eFitrTYfoehzTw6lQGhb++fPUPSG+uYg/r+3aB
BrZL8drgaeO316hnPLaEyMwr1wmHobzkM9EibndRlIXA9K5c4uuZJLk1MiK65ZTi7vNzCMVsL7Li
gOEZcuHN/5fwzLt8T82aVGFn7dqQC9weOdG0i30AFS0lZimZbzgmpLFyR5q+5QhOjCKM+yHBqP6D
eMDjBCUx5CTMlOhI8ZeCXUXHLBDqRG+tkrGMGp8xAWpVHXKlBZhkuWzIQUi146IAJakKtUAql1r9
lhPHvcAvWhLRR2rUWfhTUFlYX7mAkrmo9Xgz/4f+ltFlLRhJxLCgdngH3bpyERwNx94jtdQI5qr6
zGsQQcrxThgl+W6OosWmaKeet2PGCzkHqTkr+vERGgRGHs/GKQNqYZOzmEjdsgyf9p0+UiARKnsu
yolMtOGk62NyzOBnFYP2M1WpPy8Xmf6komPjMcVhRvOiz3yMBrHgG4CTszUDT5v0XKcrJH/IH8n6
r6026sanvCeviNqBd9DOnbboeoeiHG2s3vA8R6sSY1iWdXdtG69ADMnJfpq6Nk6vtd/UBnCMv7Xm
FM1oeKvyVnFLXqS/wHl/U1J622KxXm1jXFnqO7MP1Jy1phFS6aBeN1r5wvX0lqZb+dy3YCoQ3K+W
lp3/EkxBlZwlPTiYyI1wmzfckykmJFLW1V1dY4kSzHgRuiBxRcbr+6hAY7cO4TB9x2JGIO8EOUPu
kwpASqiyp4EHgn9mY+318KK8u1S1K+wWHHy1vC1HdlgTE/grV+u4EZU+Vi6pS2qLk8f6P2EjVVza
VPEYWUMj50fAnxNHZqW7QvujxJ8CcF7lbkm37RbS8Y45WArYEVZr3nsxwArGQyBpeDCnSdpOUjM6
fJIki2PZGdKouwceea+1S6lLis0Nf3p5CkBadFgbq8JCbmGnaZHUME5v5m+PprKap2Fy3jfi9uLb
SdNMyIIFsGtOObjQRaHwmmedtTZmvLc9WOE12dDSYBgIUUOy3bClNO3SKKurGm93OLbCzLfU2Abe
z3nR3Ytrkan2NMnnnFW7qkUapnVsbNfo1u7X7A3L1+LDBWcEfo8WJzpnsDBV1gB8tS5oSjcsRflb
MPWmwzkfPW3KuHybgaRkkgr4OoTCMSoN8wef0Nq4cmIxia0uo6fTeQzInIGQUPQdYoxa335ZhQW2
pHzo37ednj0+VG3eNEahmSzxW4iPzFIWPkgjy/tHnOmerGdg69i8YiQmoqkUZ2dg11nOWhPzulqW
Pl0WXekVmXvghdIBtI7IwAerGxCAJELHJoCZmfjw2PN7+DxhnF7vvMhiTKJXRt1gsD8YJznqtaJr
hEdTaBt8AqpNr0h+jpGMqSodksgPArR3GGOYYY/9wz05Am/4oqIwMq5ZRvHoVj6+i4Cxw1BbrIFt
hBmpF5hP1CgzR/n4bD9+w1hCKk+wXawDwivHoGHdyvq29kQv9g6aUK1RUENh//T9TeEDN8fiGI3L
p/fc5JPMMK5mZZ0s/YK2JAgSp3dQQHE9IO8jSF87HtbR1m5Sd9scnt0aCPHOIJPKHncJ/y+25sIW
XxeBZtzTP45GynWJdnbMJf/6bbzTkdMLz9/1bellkteVbOKLCRQc6+iO0YlGu48xvhEE06SoyLB+
92llKVUt8atMu2cnPQb30chG0PYqUy+4R20LJh614v3L1gP/kTay5515F6GTavEJ4TRVTlUAJ/uK
w9Iuhf3rqNocoSyDmgNQA1sMMyKuwHZwz+eYpoa0aBBz9UanGaN4/TMWOIkT5WOZWb34qgH0rIXN
GnD2JMc+ecHUANCFoOszpQawxgi/G3PjxIh1yoqY6Qsf7IrZn2NsnRdC43G/DavBG64HxtLYozAp
hoTzvSk98gZhezhePopUGdkNRPGwd+NxksrDS4fQkE6gratMY2tT14dAkCXrZ/zAHdUcqKng3/CY
KFCAll3q67mL3+xLzFzrXa7q55OInWALyUOIqmc3Y088KmlNiGE0p35wzmN7GulTpFgwBSAdf2nu
V3XoFbqvDQS/PhDQOslunRBE2kfUEQmcJ5NQ5UFXSIBwP0Qfbgz5+tDaA3cNQIDNWjZhnJUGlWeY
DEcXPrCZNUUbn+E7Ic6LUSx9ZyNFL0Ku5njd8hje8RVk+Nx4H+KhDzmOvC9Z8HJRXNaIo93NgImW
ltEnkWwldi5KVJZ/Xspdv9pUY5dsjDAkUZLMg7dgMKPr+ksqgHFaBe6odbtrBOnOiKRgZZspKPC9
/FqeMVagX7RoTR7GK65onFhI0RKvYxi0rDk5Yd+xY29PtQK9LDJpumMb06qGTU1qvyv0K2Wnr/yd
teYKEi7/qVHVRLtmC+7nc6txD67QCD+WaPNr75rLoth9mCDbz6UnbAHl5+xcsqkbJPHTlNZqmm8v
orpTEOI5B5OjcBdQBsh+jHEBBHzdmTrv4CXhS1VlEi8PI5LuT2qjlCdlsC1owdZaMb+ViIK234/0
7zOmv8NmVgTgJHxx3bdTTTSNfJiHnhQIBQGlt1EAVwR59ff+MsZmB08ycIbtoe9xjtTdOADG55Uk
Iox+ZvYeVfHQpHmQ8h1K0qvXyD6at7yEoRbaK0C0ILD5VB/f4o7fZ7bUBSS4uFwL90xVpEOpaH3k
lI1ytO7CetDq5+uuhRSKO3u88wf+TnvPwcbJUP8a2fFaVHCs8LLBPjb4Cpv6TTt27Ki4O5b7+Sag
plOzc5/h5nMPSgKi9xv3h5F/biH/O1X5OI44L/eM9a4V3aaUCt+gZJnzAjNuDktqCLrobnz5ium6
mvKHrDebKax7EICUZ/8686NzbW1R5jJB1Lv2ASwuYlgSEWdnOmvAxmfpId7kFBtT26iZeRD4aSZT
SNDGowqaX8716Im3D4W0E9yKVFvlZRjZqyLrruKncZ+YTnSj10yeKcKSxYMWXUyFEEM3+MwE3R0V
k7qLvwo8W7QtozXekbtKr8qpzHMUTR5tbxG97wbIK/PFENPkP1Tc8jzjBu8nIb0ng4P5OQSgw1n/
zg84ZuGM+sGgEYZJGkuY0xTWJ7uxE+Ezn6oLqzDlLewGb4sOzT+mdCQ1CTXbYBnxzYDBqmx7m97T
5HEI9auUod+sAdfkmwb5EurG+r0pMZw8Z+7nHvO9VT5ZlRdBP9oOCVAPd4CDyt96eDhj2wzArIW6
s6SkNhAp1edQJWwvgBE0ZWTJhdFgQ2gtOt8NtpfUMqqq/59z8BV44J6UcV97SW4tlspe1sDEAniH
MTkc1cltY73z8ELR2vEFvgtEmgI+D/UDjm09UMshznlZ6B2blbCuxfzOj7H9jObHBPY56KpuKa/K
iKxWKY465HtEhYKTvPAnDcNUUz3ATZLJ26WsAZBalrTfD4iqGfC2yL7Q40A4u4NzshBSFcZo/tq8
0J1+xPaLa3C0+Ltol25jh2Rr5mg5iPuHjjAcQUcDO2Z2T5F6pOtkhIuEMNwVpUG6tN+ak0UMdFX/
4BO2y7EA/Ij/HHPRrnkmy1jyXujQgDmBDqKW7zw0Daa+CBwSOleswlZvCxAz26/MqIRPntC52S0b
2t9TkrobhA8afc4RYFDARicruEWoq5guLNSE/Zez7Z6U0GEZqiF2a+snQw0Kibvvjd/79lTaxAtg
flPDzukjVhRsrb7MW+ul/KM7adW2EM335Xezdjv6yTCWxFqnfSDjwNwVaaM2lhy6Ved0npMfNL8R
ZAnR/ith3I5XTeYmyPf1eklrSjd6gmtmlmS4uEz+tlXk8aFLmFslSOpu8xaY3ck8DnvrxkeUFdra
WMwRWYP/vIsEqSWBRWNlEhxFRo7UXvVBQpGlB01x6rWsussuQ1HPIwLiWjvY5mfie6wBgbJrE0i4
/4A5qVp4fR5mZUkf3BAQxnXvdrMyvi3tgOg7NuK4dCqEEY7hzJSk/mYst7wwAWfummaqa7Crf5jC
9ggWsPSAbLu/K8UHKzb4cqOjAzUzJungU267rNHsEqNpjRxVtPzZguX/Rl7AmEz5fl0klV2JXjRc
oxats8o4ZTbLwq3xRA4vkca5tvIj5zsBEDXNgCdSFa9EI/C/Kyd+fkJwht4Rs5P3uCXSuJhrwFxt
FJDrosBgCPWEkoPF9byRBH+H1ecTArvn7FrPHAurSgC1VogFdAex+Min+Cg4Al5LOmZcC4a239G6
umaS0xClUP9z82xunRONiqKYOOdoMfxn5GpT+2qYH0oH15X/3nH2hz9SMtlkWL7xUcuaCTPz+zwD
nRoVCcpOBr+NRMfm1Wsrl45A6B84ac44ZG80nN5m2b+onqUg0m7GxKB8BS7xKBQJr1AlBO7h/sHQ
S0uP6yy1vXhmIiSU6cNi8xKZrzMJFGGXmq0lFJCw9iqFUv6NH4DOHg09xvR4QwjlYEKKjRUzWfDk
5vPPWBEA4HSwDOIXENblCtbl/DhrlXJiQa/yavEQQhv8XpUesvr1XT08MetjeqqOuxJk9Li+BX8Y
b0jXjY06sJixt+XOcyRGLiLcnVWAPsle7tAFKcBpbP1TKGr0haDKoNoZJtu8v4nhXkm0AaA+GAo1
KUEOiPKF0deobyne0LHkpXYPhKMBApDaxPDva+/0YOD8yszdXzwkAwmUJs6M/HykMlhR7s6GrgXS
LuydZbfOcIg0o5TImDDUKCSazileqaUOAZ2Gh/ONbRZzWIISAfJng8oHxSBZkO4LvGc2SWViJNNJ
tTPzGaFBwbJzTqG+Gg4wVcvaLQvEGIw6v7MBbex1WHYv7BqEPPJtX1d7gRbNjPeUiX/1y1A6VHK6
CzeqFvubjeDq27wJ6X2yfRswYUn4FIOa+LT2Kk5PfXtmnnnag/M19N2U4AGgbfrgdPCDFm3qDAHR
b+/OSA2JCE8+kyQJaej+Mr7eTxhQeT3o9lSMLlNyVEcBO0l8KxwNklJt4b4FvPmqV+P7/T4ZKrkz
Nb50iK41egiImSsam/2/IRQmMqqkYjvNyaKLUGE22Hmg+UGsqBrjNnX1/BSnTTNFtRT/1VrpeCGU
DxFBt41ZR+sIguf50ptY6DXzxEZr9gIi9YTxfVetsmDLBLU/B42o/EMsRv0LpYorc2MYkrz5j8yl
TRmag6HuXRfJ16Uyem3l3gIBYPjxg+I0w+J7s9WgweHyIkzX3lOehmfyGOOtszdsrJ1eg8me/X59
0OMg4ku7Y//Urc7M1dkzxiFZHJrofi9shyI+Fz1j0a/cLVUp2rI5cL/WVNAHXQ+QNK3b2FmZ10tg
gXG/3qJCohLhpa86HS4NQ4x1cUjEUi1oicXHQDc06cIh2ACJguBfjqd9+GOXQJRELDRlq2DyxR94
mwxV56+1H3lJ5rM9EIuDfMekfAeXAjoVvRHaNl9lwr8Cu+QHj7ga4dl6raiE+/g752kxfdKREQ3t
agaFgvXhtZbqhKoexsCNBDwS32Npx5MdbmJuf5avy+v5Axkmm4x2wvTuEO6dIZ5xP7vgcsjdbpUn
7Kj+NUFDenjgbcRw1u8ZK0UDfHQ03bb0Ul1Kqwpi7uBo7F4JHeHdws5W+VpzQ16MfNml+/bq4DoW
G+EKAEPMLXtulCDYevz69aVynwzpdp/kVPe5B6VJW75teYHSA8cR23YOyxXsDPozN2G1ibsFI021
3BKEhza5e0R/O1n/42uNEZWJ0oBT5o1t77/CV2m2aT0mt/CSGrVy7MKhmBUCsBJIuArOpTpyibzW
R581WCOLM5YWmv1IqzdHdNNKd0gAq5VgnQHjrCTO0YIryUXIWue1hJ/sulBTTY9elo5ktMIS6t61
uuGFvR9oJaTD8k39/6rUXMgPde9E0fGQuUgIRU0yjaOGTTL91IeJ4CWGP5oJrGEno+g/48DsOSpp
M1sOM6prJENOlnlLMh3gpsGmL5StBGGK47BrgtrpHtKHje+fSN1ZDLFJ5j5n7LHd3U3WKMdOAzic
F9dACr34LGf5gfjphMRf+t7zj+dSyGTJn+VT+SZLv+RPpw9uTa0Va/5fEjHS9qHOa9Rv8lhyzEbX
F6PPekXpGK6kK8oQUdQq3BdMXX88dpOenXR8rSBVBCvM7xb/t7PxhOnabIU4z+Z75fSavCdwi9Du
k3AIe7b7libZz8lRxoLr8X511Ul66j1+D1satB8X+6/7cbJZNAypJcGROByFcxezA0p4PcWWBJZG
W9zM7uX7fO4vNHwQ00FP2Ah1uJd/yPEGqW0YtyxMUWMZpgqZfbPu+icMTeyeQgbJ4uxGd/dTxND8
5V6eXyjn7hVHMfpBCpyHZQ8rfuOYlD4EwEPHjThMoSm7GuIRsVwCL3OYAA/GtRn0gmnPHNY9CiWT
2BR4LdZCOL38pfGJwh8/SgsNy+HPFJwBrRKQ3vzwvC0FxSqpZg3B7UYsQg3RGgcJJqbkqXPPg9fQ
yIFW2W27RqfAvgnnpiGCM4dtRcLws5UTAbzWmgX59mTo7z6DufXIWcj7LejATfnOCV7tsNEeGS1r
8+OCigthGIHoaCwzubt2eDE62wrY5WeML1DIVVuGoZVipe4Ic1Ht35aEjKa8hDbj5GO/Rx73vtZo
iOQuc9Cnn65cDF9xF0R6gRjbis5cgh+0bODyu08GG4UXeFfgfw0byDidjKBMhRRyB6yIjQZPyuWw
h9Y07o6H/z1cv7Qml2QOPaHUz9004fjIqd2L8F/ZJArfCUkp1pdRpth4iUuBfeSO8wEBkL8vZ6NX
NfuRepsXhQ/6U26QgdZMtG5FO+lHYqy2OZSuCDIJnZrBIfdbPtlzgT/QNfF0veVpUTlhlKOxCLUZ
tcA9NSwGUoookC4LKHkCuu+S7fDDAceGYeIfZvjr4fWs6iSHgAmuzX/la5rSOF+lB94LEts28WQ7
bTbSvzPyA7i3j9FPC2Nw35yFM9UlaKM5s/OP3BuCGedfTYAq4hSqPttUx4cV3dRhSOh61t5leQst
Lkivb8wmDypoFebar3+J+VDqPfJ2ef0fKwuk9kfa2RG6kB1QANZl4m1TsztTHF9PyKTMQYeIlhiL
ZPmWbavXyEhROEKPfZ+v3R9bdO/7QAKXdpUO4JYTSkpHztO55mlfvBi05eCD4Tdg3juPYUklWmjO
8MmAZ2CFOl34NL1yM3jy5NutgkdmsQX/W8uT0LvOgGnRYwgbAjdWIw5ksTesfF545Vt3lCgh4hqi
PBiqo9qKvgJmBRbGYEwO1ivVG2dSDmzaJUULQCTVLnQ+la93i667IthGb7hZHzS2BNauyiqal96d
VotexMTPph0sGz5xmlBBFmsryumJi4zZk3/AYKDqZl2EfL4xURaTBBzzXF2sL4TBCsVd5e/0Siif
teigPxVokHrJEfE5Y97uzd7H5T8U3EQbGearWfH8i4u/mGyu12yn+TMGOSf1iYMpAPrk7EaVrkT8
sfLxS2cId6JUJHvtXZRWgVeem7mis463NDE1S9UoeLjSAhLvrh9nd6zXd4MYsrz+Ep43a+0HnNkw
pkbdl60apBHnh9rf8FXGXSoyoXPcUzqoAepoBs9cRIxm3oLdHMU47Fh322uPcyNdowJoE6fVdiTD
OsY24THJ6N3mQ5MA6Bn6oT92sGk8uLFIcDoNczE8QSRr9qdEK2Wa7If/uAgvSSLL/zAUECt16K0u
dPYLG8G5DcNFJ8KN8lUGOjZ4hSBIunsd5Ldj856yRJ+loKJUdAPsZQ4TzaPKA++sm9e60vlsOdQm
TGlpmvWInwtc6UTvv23I4OKiMClmdKxMlS/HhwgROIRjq6AwDAyWremeaVOY59StnS1fucDVZ3dK
hwSnFai9jyvSe/a/zHY/ibBDb5TRSqgCokwfXj6T6lIU8U/nib3D9wJAdG7fQDNOTQm0+HcfbbAi
tSnMrrGiyKTDVsFJK104wjm7dHu6nA2YTNM++9j6EqexFmE+yCA+y94z2l5Ekt5UlA3OBVKr2Tf6
3UtZ5hoyjPu5gpHDZ2ILhJeEyNylVZQoHYnhxwTuEnwYM99gD+/YzMpE27W8DDl5ZLyBXdFLGSoB
Oj81irbf0hUdmmxjtF+EFmkHNw1aLFpn/i4ZbaxC5CjVAGzDc2nP3d/oK6mKY391dw+B2jqDoIk9
/73s4/y85R+xdU+eavm+Kh4a7uDl+JKMumw9muWFV0AR/hkZrBH8KtTWW/3YibI/xPW4S9cJOcYl
4IEzkTR6+1YkpLJTgmBWSO4oFj+JjY7pvWh5lGzSFlC1ol9rtNVEDdTKM+Z6usGYEgPWXsA0zXry
qS5ul3alySpIkNvkPfha4WuQto7Z6VLiHS9XKhuIlDTffesGY6Mye80yPD05Jco36tBRTh7e+62k
MXl3U2K5Pvq2FL8AF1xXqcZuiYmluavLVD66tgU9RbYFnBlmVVgKw8wW5mZmRnoX3ACrrT/eDlqB
nJ7PN4GH1yN28mRUZtNcD4xDelqs5/y/+CW0LfvfM9jOVRhEmN6q9WaIn4OrrDTtUMx8IyKUmixT
XWO6B6wcElI7jQ1LFLqIas3jq1tr48kItJnXpffFWgN6vs4RhhsT1G0PITWhVXCn9JfpodBeeDUM
NwtYI9GM4iZM1xm07o2kgYtmTHAM7hzUdck6ZQmsTSl5f/Q6zVCTZVNwtzTWCy125JIAjqZj3lTP
kcN33tAsepG1CPT1tgheqY3knZuH+6EwlQ3X4Vj045x174BYcQYHt1+1EwCTxTzlOeAjiwzjl0RY
SJp1j5fNYOcJhlPCByqk5HCenrJybR0wUeTYAEXrkbH4yKZJN+JrN7Gwx2SRnrtwTnJ7bi/Vahgw
t2HU/dtxUdZBCKRx50SGRQbJKoSIKAMy0xTnsKitL8xsqoky16NEWwmCbpcYXl+rT3x3GlVA4Xvr
TGPruXASXgX/KArwwQtBw7mgZN6npTOW5712gy1hejAfKWuKoFiiWGO84m3xGsqc84hPYmPbHbsP
Qqi/rCakTQt6/vX1feJc2NgWZOkvxnVos/J1kyAZTL4xJMT1CJRKHaJJZ1Kq7MpM3iFzxXDkUmv1
jcOwUB4bOl87tvEaf+/W29SibeD7GDf+x3GAN2vv32RfJbFfH37WEVLN0vTcMLk7b916xsulAnIu
qMQLXCR8zvo2votb9w7fi/5TWIBkr4d9Y3LlCOfSBXwKVSczb2uL7eMjPBzDwemmrnUxnUoWvcH8
HebPrBcw8dnVTl914pxrKlED3irp9a05t4TC5DE8rnnclK+m630iyhe7+iuWMjThPK8qU6aOfdpD
u+83HXrDm4i1qFtTlOk9U2ZKF9+xDc9zBA/i2Hg4w1wooFlBHB6lOkthv7Pz44RlPKqdovvucJCY
5yjHGmT1cS2+lyRD21GfcdyqPwu/Lgd2pUrTs22nmEwI1TWk/ZbXwVvlbKgyVerl1o1+HXVtgFjk
BoRKskSH1w73UF5AIgRvh6kmIPvT6W1vZTQHY2K24shPD3p0cKoWQERHZRN2Wq2TRqD/jU12hc/X
rmCgfAhO5ujxmXmG1ku8LNq2MBlzCNvY3Mk3XBbJ0rP39WbLLQmhCj3QP0TQKizoVlQ6jkaDytK9
QFWrsdyO6urKYuV9bXb+2FX4kF+D578+ouuk/4bEP1Ih0/HnYDtsT7ksFA2/4OXFi8sbZF/uW1xg
GdGyEyYCx8bC2yz68VcZKkK6cZCqVyw5HznJz6b0UsveASLAVU5Wg8rGN7IwDh3qZctBJdIkE2W/
FYVMkhWASrxLd6abWVnAsVQYvO2X6RXpDdZfCLoxc0pfR3rTaj3ffmtjxfg/JTqe2p81sNK1Lohp
q6GBi0SjmTu+gm9BYppLCbdMlzu3sN2uEHnsDhAd31AXM2/jBzfa3z5b/rGC3FnzSI1zvAhCHqyY
+vxA5+/Ton8LPEasBPJnZTlLha+pL4MNf3pOl7Z69Bjw8lY19KCgYduTpIXIwDTUl82gzaFtyI0Z
huvQchsnLzUtxIBzy7S4AYGdHaxaRfCQW/0VTq8CmSD/fr9Yu3Sgg8YROChDImHNVsdVbIZ5Lzt2
L8pCNfS927wjsvxmxdF7p5OXZaBFG3+O/MzmlbMaAbxDRWc9J7aoqaavX7597HWWrFFXfiJLuv5x
2i3RoRnhOW04yJ1Jz+fm99ylTq2hqXxh2rirHMKaGbOnqiJr5FAgNgWEIiN4wRvSbWm80baCcDrU
xkDDJX6QGX3TBAKloH1Vc/012qfsGMPLlBhuxb64ENb076LQucDBptq1ByZojUpudnhh7drPWuNa
QEfk+D7zRc4N51mHNKa2Mt/TlqkdiwPaBXLfW1+wIlT1eTf5l9gQet5dAdm28zd1dib3K95fKWUC
HThSYWrgVe7AMm+eeXj1MZUZ0VP/a3cAu8AFA0SHDnM4Of0kJNnbCq/C2SihMlb2gYLPPMUA/eFZ
it36o2FmpzkzLVEuHF7D8J1pJ2QjBHdjhiZMLW/pxc5Q8FFFzDQjAw5uwG6wobuQb3Y3dppdojEo
vJhVn/2mUAbM/oh8EnwT2COHrssggiL4dKWPSd8yvoL2qoZF0xkoQ7+ENsgYcRTNWT9tAJW1y7sy
ia1lz+6yiTx66q+o0PzTGC+n28uyYgnSfuthqVwUTnstCp2hw3qmY751mNzY9MTTXmulGZMGVVGj
nb/f3dEQrZcGqsac6y6Su0SOszeCoYxy8ppIDEKkN5j4o5pxWoyU+wsQKjhw39lHVB7OtP/Oqc8U
surWv3dbH0O77nVVXpstwLH9l+wZM+wziNSG+9UbKOT2eNnq1ZWqsT3rcF+Hs6SuNBDvzNQ7GZRF
Ta7Foeg6gRHjYc4t53iYGRYMUgSZoHQlDx/E32DI8BFuJm97MDCDYjwhfQcVKYe6Do3sU0CwrusD
SQrYqJL6E1+R+SL4+OYNgD+2jrPmeZtEFgdDtUKG1LIU7ugg7VSbfemaFXsMPSIg0rlH7YSzDXLw
louxw/Ddbwe+0TsRuizERaY9zKrLkHhFbGH6QPBwawLdmUhWGCb8QQ0s7OsHLlDiPdzdp77xWFU9
6ROA1R6IlzLhPqb6xlup/3IXA2NGpLuSeuO0mCdEo7LSFj9gr4GOkU8BDgauuaHFGSznvATzmbs7
Ns19WhgJHDgvQrrGK7DlA26lDyspa69KWbcRF0ZnASXgNxFAl4E3tbIGBfCxqL4W3p4AsCFwwjH1
P4WolFBV6fUtUqf2jl9d5hwbD13sCYtkz4T1O/+xb5+nwifld5oBi3q3kFPvY9tLb9YEWyYjEgtV
K5AP4Xs3EUkwX790xa+dgqbrWW/9gf0ZmBQVOLcPTnj7dSPV292dFB3qbRjW4yEF+Gx4N7iYNpr2
7WZ7Muuino3b++R+1eTb0U+LEKytE+3H1skTIPpHzkSzmRuILf9ZSgii8bnKU4agqH21jNrilZkI
cN7vPCkWeEP1LeDXehMaJ+D++ER1YPXMvlzrbrWVAXC7ZDUuc+18i7XuF0ly6n54lta6cEkz1sxb
gOlxYq0r+cGQEBCzTLVwF4C/TXJvLgdZKEgmZ194e+Djxrp6tre3umV4ssXe5Pr/QOjjDMvzDQiK
THyhPrQWyDxhcbyYYxdAtu4S7wURSM2+OE/OgLwp95x5oqveXx/wzb6QjdNiSx+UWoV+b4HjuIIQ
k+hzl2AsTWK9t/tl6S+O+ZHHXZagS8cvM+nKwodvVMEOZPO0wlRbJS4vCz6XLQwICF/rSHlcU72G
pm8YAxvKLQTUuggpnL9tyCtJFkI+H7a8g98WjpberfnbCig/1UeRynQzMCmZwxtPqiSbhUpGy3zK
cUaRcsA7+KYVLtvfyoelnNEk+LtYWFN/UC6zFOzgrw6UEQBt7IplllK7cZ86vm8vHyiIHMzsrkxB
LAuPu0OtrdgaBbuNRPg0vDlVRqsnKFdBC0OTNYfd8EYgk1vvGJbvkzK+J9kwejyZnyFoV9OHmfoh
9SCzGIbHD5QP+vZUN4fLi/SWX1t0mxfj5uXA0XmecGl5jxaNSqWudXjBAuACFCW9hwQt49FUXB+K
ma3dfX49Kp2BOKDELgYg9ZGG0ukNS4tWx72+KSYOdoei2uwcWyRplrID6Vf3CrBwJYx9D2osLBpQ
dY5YclTYSEPiCyrZiGAk8DDlba/TdKOuAltiWuLU2wgAVBbq500qfCVbCLH3yy8EOI9rb8znYXI9
yEfQ1cp7GS670Owx1hmRfrV6lbzcdL1K69p5VleYYli5l/8U0KG5IGIMI2UsES6LtCKjevt9UQ9Z
1wKRdG2Zz2AWjIU8GPlbAl9QKu9/RDMt6dpK1Vn2AxZPn3YkKU0twh4I4eVd7dahWzHWNi7UAc17
+wnVYpL40a7bIBClaqmz4wEzv4J+VsBa5ytomJOk4HXTkSBr0J4d3mdwR4UnwKNzua9YOadcRrxB
A81uIMOoyeUkHCTsY5+p7mGPlS7D/tc+diG3sXYSTUm+FaKLEN2H9TRq3Z67zkZ5A+JIJ8efc9cE
PG1iNX9qdGKsMWaJ9j1QQWYdBRuA/Uwp4s1L+PndAmUUMFWuUJvcDGnNgg00C1Q/gePNA+Ugpgx6
5OmxhJq1XbVk7Tc3z05ZEP8iPIVKCJreiZ5DJotfjxjQiuMhilxlJz79cmrPKYPrRFtxoAV8YDX9
+ZjeVWnTzgSv/GmJ8Mtlad8amrRxs46uCoCBCzy9wqP8LjGF5HhNLjkvGxYA2XX56iD+8amThIM7
c4jpEp2Bzege5huCXycKlzGaHgV13Ffy9TuoPFTU0GC67iik6UyWUQGM4ypK0/AcCjbqqHiX+VnA
93BPrmSI/JY8V9hbxoFXLBwf6471xUZXiQPIOF5rsv3nVp11yT7MQH4qSD/syQyHG18OM6TxgrPG
Dsa3D67fi5KETkonlEEvnTmazHqrsnB6McvQTIm14AA4JW6goPYi/6DGvXB2XUIkDR7ebNjPEeWV
rG2njaEoW5SDKl0Ogfw5zhJKC09rnpLggykTcN2mPct1At+Ugm3H3bPRkbECtRPITXNVnfe6PHco
+NOTXEvNWdT8QxL9k89JVi2/rpetT6faDFW/2X99kwjXqSgP+6mO3wc8E/D0ZllBFIngKZJlzVtg
XjHKzr02Qix1Eizl5mfB/Q33lx3YcpRLD82chhHH6cCDzghL9f3ehLmiC0/53Nie99A1x+dVm5CH
mogW9tcVP2DncKhLcoXC169zcj/sZX406KsoXRbpcbXrqHbhFL4iwefDj36zW5qu6OlhBLv11YMG
BPzvevchuh9b20C4hPySeRZcjLG5V69cglWpRYxBsR+MGZygiTjixcQJ5AlOJPhfr0709q1S8Y/y
/tucz4z7AAGN0GLoj+LU7U94UXwO9KnLLV8ifETcGpPy+DK0XYH8oGH2mbbJv6h4nTBL31sfJ9Eg
rMNASxlmJW/a51kTnSLccTfQMkLOQ5XuVu+1oV269wrDWGUj0mXSYpRIMSwYz8saGGnil9rMsUWG
6l7CBUn6cv7yhPlXWog74GPTu4WqMWjCfrddFBZrKPBcl1i9z9md7lncFcYiGrEGqvrb8EPPM38a
Yz+jGjUswajqIlv9vWr+34SSJ1i1kl8V/GXGEAfQlcq485GJ6cBVFVa3IebjSnymo8cr+vnJNwq9
niUg09Bsup9j5ttpEEKBVE1dv4xEpHJdP3pYFPn/r6Ac1C1/Y/OH7lWsidSh7jSUlZFg3N7kUO9P
dqkZWzIvdq984r/lpfNM/VnfbPRHq6mLuG3CRVhhlZlNDgv/BFektvhUiMbOBn+7cpytBp7hYNtc
DidgtLdq7SQfPZzGHMVATPeHKHr02GP72EUmuXd0EdoGSYYHskGUqk8JgzSV4fEtoPfcIDAcvzaW
B9ZylHaXKj4DLNcwwrI712n0UCheKxnAgKUidPZrN29THsLB64TzrmZFYvilYpyICn7+Fz9mxv0g
Oz3ACo98LV2DqXUpAhsQivsfZBYyrsxsXw1VIJNA8Nn2QuaaqL6u6K0u8Zly9QueoEsRNAdKIfpk
3JqQjgYvpKVJnLukJwnPvvRyNc48ipvWFfO77fIsZ2bKs0nOKga0GrGc4SmL50VyXWcNLAItTrOg
EE3cqgZL79ONoFKhfsRrIxiF6y8emuugMX1KtaaNYX4nz4z1WVG4b4VfIIhUJXjS4VsL0YAShSyM
20CNmGmEIu1qFRFh9Eo39VFuS94BZE5ILHBsCGdH4p0bPAWlEgphVVePJfZaTkpSPSW3Tcn7rhTz
4IiOR89/ruEovz386t+IlFfsLOzbKJRJZiye6NpWehzyA4+6HtvqOxWTCKDhb+f+p4mDpVwgZAnL
yffgDGUH82FiJESZJR18up6BkPQcEstpEfL60dGYvxmMFAUL5EFN0xdiUOM5Wk/zqrHj0S+7owZT
49XV40LsqdCoEWtOQwoviFxwQpjvcjtvVTWmux0yAc5zffYaVkVGnzPM0PHcl1kAlrXwNZxEJzPs
3PsfLiioDzRdFcw63suA8HtXL3t+hAnZJu4ylVWJoYa6y/KADqiHN9Jo5Gltys8uAwGj2b3J7pR3
kj+v5GaqAGGyL1lO4d4k5EpCjGq6t90M1Ham/6WpGeJ19ROX9PFaTjn9IVFgZEP3S9xiiiAowxe8
LTBj6Pac/RcoLPuYCeLlLTER54U4LItnmAXOVvurJvZRyltZgIVddh+Zrtc3C9FCUSwcQcSOCq9N
1EVanY6BfZYYnSgMzXXaMxUjBooqC0q8UeaVFDSAG7XKFh1AdPXOJcurrK45pTNZrRmavU4xLoE5
uzsJeFu39tJROUMOD0fJasmi/t5qI/HX/4k4p0rbjPej/GKmPynux85HnID2wrXRGqWGuP66ZxFX
Nydjcq05koKp0LnlEikaJWm9MeqINgp84hFEOpCkRKqbt71VjRWxEW4tRIKHbJNP+f8GEEQEXpVe
YPegrhhvN631JKwrXDM51GZ8cU6A00Y5v+TLErB/f02KODEHq/MTZ9CyZtu/LSNAFTsbgGhyqfBs
YuJ0ZpRDKRRiR6KXcngxJXN6Ow1cmM/yBlZ9cZl3W2kqOyAiVTSjZ5vcTWJ+WtWb5ykihYgIcJsU
Ulgs8SOKHjo5R+lYjE8e/lkC2LoHCgW3elmtQzkqUhUMIIxQXguJKkqHJBDwQCqGIifCqXDMzDWp
CxBcDUgS9yMYQR7q4Ldlqs8EybAwpD2wcV0bG1nuQJhytS3W4hr5pRBTqFhNId91Gq5422bODGIE
y6Pu0fqrIy2z6DgbGnvSgYRpl9hessk9ttjUNSjDHvX60rmXaR/FXkH9t8HOTVffnJlY9YhjqoDJ
vnWaLxCO7zXBMxrZpVmZV/UetibRptn909EJUod4LG81b1FsQkoh0/LF2X42sKpNsvCjUThOVPI6
PJz98RotzjgJi1XjHASW5t/a6RAyn950O8Mng0YLHMMiHy8xGLcTV8wI5b/x0piYADMwM4fp88QZ
y82fztqyAvP81E24XGq0hemWfVbPZ5bAF/uoySuD3fmbl+hLYiLzMoujrUZ/I5tNsqmQvw2LcRLu
3LWT1gsEomFWnp5t5JN9+TDGDVlLOZz8bjbxhcb6smnaSXHnnXwYkZwamPMA8oL1NfssF+rb8nct
X7udXXAwpWBOdrszZ78VG6s3z1BgLrfXJLzHNabJxZb0BjusDmmXVz5d43QNg1sbUkCqC8o2HQCt
k8qy4OtfLQi0WPJsFD3hXIRqL8wnpa9muWqrsTtJ8xZnoGHo21Rxo22RWmPi4Ti5mgpzB/P0Mk68
KOr2oLRfbOZF7ltIrKiOz+J6WPMaDOCEbH6gdlnqJMeLv+AIS70pfwfW3AXky6CSKMljx1tLKvb+
5sXoZkN5leMjs193YdWQUjFajTYoUIxA6mQoPMzGP6gtSG1Jbvb/lNpe3Z2moZDMgeo/bXZhPzrn
4j4RPjcTR8DFGI2M6c6Y722KalIXRMAsLz8E9cIXs+GdVgVmxqqtH5WCEgmmWJn6ItL3UBqxs3Mx
xtB02Y/sdEeZ/5JxWTXVVRlx32Ko94/ccmfuVXGErazoplnIfN4vBedccEY/5//AqCHNaoDXfKNB
cBZQFLvdwk97dcNzZcP8gqcQylzaxBHIBxWBKA253JPT1p1ztdYFMyMDtDV7R+q9P3CxKdKa5R0G
Umb/z/hKOt9Bm/B8/lc66GgjYclDggmzBGY+zoGnpBYUDyJG9DxAZoiQ7fVXuEVrm2U5L7/QsEz4
ackJjpLUJMfv0lyHoqNELynieEiSB0kramy8ts85UsxSaH/IqWLUQGLiTaGGUOj5uNxe1PcIv3Q0
tzEPC77MpTrLyonaOM5wl90yw6A/gshVKBrV8tf86wQLUYNYVObFCzU9qTQZd2PY+d5+27HnQ1XO
OY8dAw6y3hTSjjXLx8vFwMbrn+e+F3BYnNNDuNNeI79zuRN4p7W3KuJz/+1pyUaUmEFfR8G0ftG9
7Ar380CtJd8pn1ZrXQ4SAX7/Akg2fQQ6CHcKYviVCfAVc50Yshy5JWp5H0f59pzSjY2iyni5DsoN
lhfRP9TI41pMdoyxugCgG00hYwgmgnrFWXp10seBWpS87uFyQ/ctzSoJDvxm7xzYWyvETMOLhc5q
tPI82h4Mn5wF44bSUhzv3u+CxaxiwTuNQDnh94MHbj4XlP8UyAlsMPohQalGcQT3OLc4sl3a4N5k
qrHOLHwYdml3YepRKuktDKkJiwWw2dYPUTc9JHrbqSCi8cJYR50DynZUA3G3VZPEujnkSebjzBvy
cQ+tXreu0A5pTIxJutkF+N0zG7BdiGy9TRm52Jl0qSwcuw9VfKbc2c+lhvN9EYb6qKj795PzV1Xi
Aq7QdwYetiVnO+g5ycRMtq9K7TbiD6POTY5gNPs+VwlTnTGLRE5ADZAoRIiaCZOKWOHjfPhSSCqM
v8sdzDdJJXXBUXNJGV+50AsnCHf0CmNVVfAOfVPG0hmUJ4ZunxGK0Xg9eEBmk6l4EL5QnLAkLg9E
yBOngO113cgCH+0ob5EEXgZqR+kMrXCdxc5NqwKrvBiGyepOXwQbI273ONNNJ2EdbCzVgpcOWJlq
bBhERQBrCOvliryjtWI/KvF3Wb+t1jb+ozSic4nuq1Kk1DB6IowysCHfTBOL8h1vOENYxHZIqayT
Y+bS6vKSvq66qKy7KVDn0hdCb6IUKKj7z2HX7S1jYTJIjv59o4vRZF7qk8YG81LX0dyaRkzFbgLu
yYWDFJmQTzjW+5xkqt03/kqt4thmzmLC7C4sxlGafiQ1sj6Qk3K2UT8/sZoKjYPpdqWjcWyalrlB
qTNBQrFJekHOh/as3hglpsUaLeGEUwPdR/v6b+lIJ09UUHsJ1+0GoydwdoiM7g/cDLaH3Tl6HyEy
JW0zlhsmt5hT2gOurTsC3tXQDmpg9VbQte2vW/KlN1Qk6389IBoyYniE7bhNn3+udLF52pxRz8QF
4zqsUq9we9XJSop/eOj7ABEuczFJM+J2yO+vZBdEAD9H/+Il51WGeaSDwG1d7BIYZtdynGOYCX79
JRcwOjHjsjsFtnq2hpfwXKWKucN53TiB6cDIK9qxmbstUsVe04nTAQutMRnwo0YatzwuJ24F0VsQ
dgvVvxuHApTBZgpwC6R7kzcVa0jVJItxd/MD86i/ATw7neOvOpGumhPdYF8pNNYpY9pgRfySigIm
jHdRoP9XjEVO4una1o0LmOCCi6C7lanix3kA5CD05FTxlNZJHba2oREjrSI/61/uV0reyfyDuNOx
HdPIEaMa6NDYnbbj4VLj2pCsmZ/B87iWfMVrw8ybf0itXbTKKKdDdD4o1jp60wU1ljFq2zliuho7
uYdEtJrsWKFaohYDle1yeu1IsX4HUsgsT0isCDZco9LUJnfPeSxwjCCk/K26zzYTeO2LhpRIbtpA
e9ZyhRbGzPB8jwg4l6+lEn+NqiZ58/6R0qmtdTRYya9Lz9Fs7nF9T1qtNI+Bgt0UBB29KshRZNh0
xA0WbubU0f+/fFQuyjA0Gw5B8pRz9vnmVESX8KhDF4Z2lPx1HlF5aHYzIE07k3/L2rmhhW3xfJ3f
IW4A82wXawAnJEk5nDNAc6OUNOIXHK2mm0dxTlPQfw61jPU9MKjrBr3ERWSRZr+xenTMel7RQIrZ
FdHKE830kYa11aL8TJP9nBk41JDOiR+FP02+VSMGFw/pYk6JZKHK37/4cAw1WSVAiMW8T2YmqdEZ
Y8Q1CqEMLZQ0Od2UbzPWC14smClq7eaDkLwxmJUcC97h5bImlfLt4nMBcXIOQgCOJ2CIyrMokR+4
S9JwsNQNLTJnreJXPY8muD4/saamw+90KD3qsGOGFo0Onk9E9JmhS6g7hL3wwoBvxdeWE1x/Ji94
ZyxohJxeJPc/UY2VsZhmkNg1hUnJNLvQTE2mkrb9RzKTwXlAGo0l37rtuZa8R41jr4zQoc7Nesci
43BQjDQjqeWc9vw9q83hx0HjyC33DQGn1K7muNwvaU6Mmm0myDJqiz+KlIGkrwvRoAl5xnltSL45
xr1uyPy8AH3EzcNACzaTzOfQfUMyGE9WsNTNSWW52S37hzSM6Hjd7FFlwYVoeVzBplO3ZQ9r3LWq
HNhFL439NEGL3pIFEv0/2/1lvVTvwWEuTt1XJpicpT2i6/GAe6PGCcKkLTEsUwqg5kFH0PLrZKC7
x+Pi0tdt0wx5XGy9bewAw67fCbdnu27kMJtRl65N+tsk/Nl9pP3OZqi7u+K6BR+u+BxUtPdLIDqK
tbSLJ2VRm9TLDmklg1Qcmkz1GYyUTfojGGKXwBmCdo5NdPqp5FWm69TZsO1ZJRHkS1sEwg68dllN
lj6z91aiXR4CZe8iq8Vk2yrKlmQQXLOfKhtdnP39aAVvBQy7Nca9crscIhPRMj4YEGg/jyVBI5pe
JH89kT1ap3yWmudiupdOyxUq24lEJus+KG4jZ5bFKFt6L1XTN2PgIAiRStcDJKKHUYRVlpaC44jn
82l1yGNDWyZJ/AaiQWtNs+kV+94hMsU2mY3FUtS7nwu5LzB+m/bt378oGJRveDW403Q3M1wwjcuj
9FtA+k5UowJJWXwL+J9UouzmydKUCI5r0pGUvayNQunnHVBpGebTe8IHZIWFyOkUxgAUP5MBFwPU
wjEH0NkacyDJICbSYYwjEgUUMAz7K8FA3hMJzw+c8Rmr7J17+A5E6km+rgpLZL2bnlEqGT6mZahr
M+Quh4vD/XgOi2W3quQdJul8CCPoZ+weGe0ErdpIqScRHPqNqsBp2YWG5kKqdc4RuT6brG+6juXI
tFcPpoSVr70IGBiWo3FyHAEM5hWc4mst27HDRDf3Fpg2KPsq9vTmgTC5pEHYp329iAOnQotswj3/
pMNQ8VmIE9MR4BS13tGJAW59KaTIRNfmUG4QYDJDC2LBuUcXi2hBYtLR1jLD1QOmq1AB6Oisp+mb
caVtHMlSFBGwF2xYRDfQUngEEWbukXXdYmjKA8L4eNbtH3Ro0hL2WZ+DBot+lblKxnsc6+j4CRdg
eedR84v6B3+NX6FFz+M/GBFczlFQA8FHvCvdAIzG6j8oGe5AmvoMy05gG+60LkrZAjJulkIGgy+Z
r/FWeHd6UXqMdyo9a3s5EH+H6O4oRMc6A6zI8xWZWefab+36GBfIBRunzw77FrygxcZTmu5r3n01
VW18Q9lZE2pdPlj6A1NLJyMqYtP2QcWs2eOey86Xe8RWe+Qy3k9oZvvrACcpEfSnchxpO4wulIXf
vwK5mgk/uLpyZFmWrF7W6SWLJhT2LV6hY30aWlVWHirUuIDoJtfkF+KyvaFMzxHTn8q7vCtG+I+P
1rJAYXnP7Q4EbZPIlm5Tb0VablZPcftDE4KNFg5eiId6+XQF2A3AcS5LxwetrIWkUPqUq1Y44kzy
kXA7ToW4FG/zN1u2IUnbtiXQ3M/wYlKF3WXPJ5OwABdv9nK7MDkABwjVU162ReUkP8sned3Hfm0Z
Dkd61nXGEVfG7O+VhJs0ZJjYb2tl2oy+tKsWi3pQflaaOgrizRD04VmrwWEeocbCIk6CEFWMt/k2
KDf0fnMXqR2aLCf05X5qx51nauYz5UtWVJIqMEmxhUQ46p9YayxqSROADy2Al4j3Raw6pQWB/dNc
SpqkEneZDylMYXnRM+3NloWN3Njw1vvI+lEmbeMhglfwVa7Gm7jCgTkGDeTrZLvktSRkN7gqCWvD
e+SihsenkB7Ulf8yPzEAp/sShR8iig4oPiJ4ga7FY636l8EsFi9cVi3zituaZIhD9Wo0AOKvou4V
bhY6Joz9nPWpppieNdJ/+VvzoTEAXrmZ8QIeAY7p4stXoaKZ5O9R6v3ldm0NpAlglbrjYKs/oz11
aFpDdLW3ntiwFr+Bmc7Cj5ZrIrxgkEobF4lIbrid4Zup8mNh21HckhAS0gVf51NLB+nPwlsNXoRs
PgX0gotXb0tKBNh9ABNK/nD7bcBGenI12pAdKiGO61fUEc8Ud5d04JWVNRMmRbIUXLg3QqAt3Hhw
5Ody1OPf7oq73dAkAYrV3IrVDlqiwGyZHroj4ttY7ll/cCaPnIEVlGFU5/UaemURDQip6U2P41Go
o+hU+QdPIc760jjPWDghR3qlppdv1Bd6x0ZdoPfEOgtuYqHHfxzOH2EHuJ2oEMWtlTI7IXgxJMUd
QmTYzuvUMdT5ugG/EXQiMK9UubSjG3TiNvV+usABx79vJvPc1AalKYzPoDUnCh4ysPgj1rNtNOjR
IL+bPQKky9Sz2k6Nbil81h0P0oJm/d4YGY5fDolkAp9zsIdEQJ75FY5KHpeFLNYxEW9tNCuqkBI8
ZFe095Asv5tW1YYF+joqHbwjMJeU3+8KXryTqJqc1L61KwiUz/V7QPX9UgZtkoUXKoUq51YcwBWo
KVjVgfUNKSp3kiXOo+9jj+shvOGNT1mpWHOg+j7inONr5cJK1pU+eV9ad48nxlTSYdA5MVdBvbEJ
A/gVwzdfenXE3/4sKWeky8xR3ibd/Pf7e5wVE9hNt9X5vVlVn3ClhQ6kpVl4YPnznkfDRpFZNwH+
+ssBjIuV4fICOwIcrAnZE5BtWCKd93fv/uCb1Ev/pPAk9sN93tLQ3awQkcsOkRljnpB9SOHm3RyS
X1SMbiV5gvjXQbrKeWgChrPn7Bs/TlXO8IoKR4aHkio7Jg69utQjlhGAbILrv8obvlfiIu73qf2g
kOAJqt0iWkWpzJ7QQLp+dHfTiSleZ4p3lB1WHQkdqIuiH3YFUlxpnqvVXX945nZ3jlYNtv54uidG
UqEM0Xi1Kf8x7UWvjwrc47H72JK10tiMNOnIL4C8kTuOw8RvsZxsK0PJAKnw7dO31tTNtuo/LcFT
tN7h+lGP519S171zrVgLETv5ZFT6IWBBANph3/qR4Rpfo/Nc1vL52NMgNexzjyFZD4Dh4aJbM3RO
4yXnGVMT6EDVxrxchfMPEMJ23tpX8rZhh5AcX7SQsrzdpZ7D+DAikJW6Vaz4Gt3MU/Ed7DTJZijB
q+p5g5eYE75xfz8LjUsZbXAAiNGH3HvFLDpsBuADj4CtfX2l6+pFuxVai4P2AyyUnCgP3LHD8QRE
jL1FxVZ+i6aiCZ4PZ2mQ/NYsGN5mO+6CYlfWr84ESs6tXGUGaY4ATO6pdrPiefzAsSJzLQucxjCq
YxOqX8AC0s4H4p45984A10rB5Lsx/LOpttrKopT5i0nHzZgVoAgLl3k6cFcItxgkbQ2Rr118d3p0
K9/taKdIR3KBE5slJs+SV7NB/e/uhhbFzR4lkOAEHRdHO6u99Vf6DSuPzqk1aEE/12bp3/+AdL1y
e/UE43jA5O26Zr9C9Nq73UhBQEkRZPQtPa72uFDyeA5PzO5VenaRsmtgGXVBLRNR7cXOmpdRE98l
qejmFeuLS6i7GqyjSh1YwRIlYVVWsOPqyP/jPWGrSUauJGCwu2kKSLjsaQGgAblD09h2aERXkvu2
KHVY5vfM8T1rg/n3Ezei9wWFDM4YhMJN8tlIlaN0NLKycKBEw1jY6YFZJHTWXcidftQwi9X+5OpY
XG3SmnwykBv7UTpndgclwm4rDo623wSa1moMyz4TnZGJoCJxafbw7M5/RvyknYf5QjgyyRQHKHN7
fwvUis+YiYB2MBw3wB/bnedwvH1OxDQnyHBqcd7MRFLAgSv3qOE5zzvho73wFBbCzN/BFCignP5w
7r1Z0ReJ36i69ghLMCRCDqpnQg9N2JgRqH3m8vIGPdA6W3PCHoBVE1p+NeH2zEOtFZXPUoYs9W64
VfpBb0HMuFharHYPZUBS4Uk2S7rNqmcwE5tTiJeth81EsZxSysR2FxUnnZ3mJnvgUL/pto3trRAL
p97PaW7wyaJFXfqQov1Ic4JC1Vtyp3VZcpDO2grPUSssGaRK0/cCokTOO5GL6yIx77/cwQd1pswx
6gix58PllHxq+kReYzAlVxfXXqu/JEPXbj6ALtyauyr3657z4Yi2UB0H61Xrm6qJYShn1JZ7peqM
1X4Dq880ZLM5nNemTIXqQKC9czefmi7bcfomQDXbYPxx5LHPTbMyscpmo8kCR9MzarY4UlkTvKii
1+yPfOGl8qfusEGDB6VB7kbNQWvMcM+Btd6XhtxWdNcVLeQhPjxqw0d/p1JDfCFKBYEAJ1VMSSf/
eTflYuF9dN/XV7hEXd5mc3XRokWvpymXGeLD7ClGLCKYjTbDv3gku2XiYM3lIb2cSbjUeVNO1PcS
ani8PEhhKds1iat7lpBeMARPWRunV9Lg0zlP6mp/bB1lj6bjeMNJKv/FR/PeMc1ZIBDbyTfNAH71
iQ7KduNRgZ/a68E+CW947NpQGCLuFnbG7h0+VEFI3E7sJo+X9HsDymc/lMUa5X+LuAF+KIHx6Ocb
1ccOqDg5MIXOXW/+ExRTgQPxrP3/KcBhpizEdPgT+f7/frrfp5sVT84byQD5sOEt5N26A41idYq0
cCxBBUyMhCEHk/xHSBgnAeEHY/N4/vdbZnJLwc3KLnRiZp6BKTiXFzwx2aouKH1WhhbcoKjAkT/T
ltBZSIc9YFEZOdlQ8PgfsIa7XfVzQywR+VHHJa0rZ9+QY8F2Uh7dARQAlwcwb7WHE6DqPtKkMBF0
jkYSUkmTRPEumqD+FvCcyh5nvXXjJAA0/Qvnvh4YhexbubZecopEJnxWqUHZHny3f4JfP8ZO4xUR
weq06VgNQVR7ISFLvdaGVJKmRNlnuAvr+ua8ssCGN3wSA2B0kYJcBGcixlySK3vg851NNAwEhbgh
32/usRGUZVnCkxQ3Ah5NBqUZOU82RlqJzqTL1rbiHnHp2X+A9HG4GsPSicNRrdB6YsW/HNRxJmJN
Kp2uclBl+52ZyK0egtG1L9oGwXVtuTx4yf7EIpvVGfkA/pycSgRUo60ualpvkit75JUD9cFR8y2/
HLIPK0koISdLcbdn27RC0aJHloLtjlkEoBZ7djuK2ir+Evtj8DjyZNJlQmZckjoJIYtKUXIma94S
ls6rgW2Az8DD80m5YzO/fLf6S6hcVW1YSzIGE+Cc+ovR1OomAoBcnXQKEKQppffndl2aUF2c9qRX
1OhqQUc+xnq/9OJS2ZgRQPjeQ8yw77dMfaj33ldzeegNqAeiRufbwHU6mpi0HXDC3wzs/ICThul4
GBMLPE8S9nTYPLaSlQ3XGq9/7Ic7MEGiI7nKVEVY6s0t8aCB37yY0zVMXEvhFNnEaubgv9KOx8g8
dsC+KHYSLotpE2wnlaanUx3qJJDe03ixQtuKJ6ti5jvzsUF1qXSda7ciWZKbk/cNtV0aKMbWCcia
N7CT5WivGPhUj0AgbZeWAUl45+ZIaOGdFEwG5VI4nGLV0i5sgzcDNpZ1gBqS6HQ3wn+G2fEDu0xd
oW0N9HTGK2/Xew4eS6wtIjnP07+UJoEbsvliFkHdjkU6LEmbQ9vybaNLe7z4BKzs7RPePEeKvrUa
eUQ9Qit/pk78YDlmeqoM4VgoTS/du2qv3GgvQjoTpGtrRjB6JmK4Rm2cAUuGULOfpbH/yJfAxjQZ
7HJBU3C5hP7gFuVqs7GcHWF3qIwpNBazvy/Tc2yuNPEeqzOSM1JVZ7iWennsxBtuZL+PIKVwJQ+N
bsRMQyANm9cxZVkww6vKyhGBFRYfv7xQU5wOk3+XAddvgpb/YJrGr52y21IkupJS5Sl+/kcwAOJc
bIKF9Y598w1gTl2XWA5e0peiauYjxAeSTwHDLhtSvvmFLLII46c3usjh8+XqsEpQ+fMk3BrSQrRQ
cdxwovgnfOsEAEv/7t99f6RQb8WFTsEywTY2wGLb+Ob3UZ2FRamNCSnOqN6gE7vhh7wsGEObyMkn
9eZwy+NZiQ8ps9v+HYG4Kpe82olxDAaspiE8U9TS9ogM9s3QC0xwjQcZpHBkFdTDjjvXX34r53Os
oXTetYs0skGr78oJzcpg++zBB3ProLpcz6BHnqfPyqFZpUCKFy5IvY5WcXiLx3X6BOOJfFHT9x1q
U5R38ZVLaWYiJ8WryCZCW9LdQ5FO78ril0nbYDTxgCakBZcBo1y+PqJLCq0ulUFhm8ezop5XFMVU
D3d4OtmIsmBApZQMo+2HpWu5eLIDLZWEv7wFHBx/F/VJTQhP73WkbbYUM+scBLs352YJUOxnxpy1
Zt8bF09uBogJZjxKUCbHiaWbH5mo28hH9RiG56cRaadr4FduqQ57JEYB6f5a1v7dirDqoTY3pRft
KIddVLio2eLOruod8VuU3xlZejbQuUjEGGPzY7xP2T05kzUFQm71RAhM43/k8Y/DnqBAiuBLc0M+
NbXk+XRrYi7AR4UAyu2wQJByNhUgwm5Ok5+YgQjW94D6FHrIG3feCKMvREJymFHopJm8AyWKosvv
s+LQeuz1+h2kM1Av3cPYbHGxDmc1jNdzi0EIL2wQSZelV1jK3ubTiMApF0n+mnK/EzVPtEOwZRQ3
CNc0u74wmhPWjWSgY2EtKd8d4EPrg4xVDziiXUfED86YQzwiRTeRsEP65guUP6r9nOqnEZ8C2ob2
VBIZRFu4OXVcjvXRMbfd6gbaoeMH4WbJxsS0yI87leXkt1rSMybqusG9IL0MOifa+7ZMTjCzl0MS
0zP+hf/J/RWFG4sdMPbi8zNVmu/16D0/8DQh2X8LUfDqSNRSfe6jXD/Ksy0GBv/++MNs7jRJZK1m
cf12y+K22uokJwNdO+071W+aAmUyMBMkixUd7GF4ShBWMKKv1XYc+tWlZG1lmU6NC5+P1bDi5GKr
9IOR+Byqc73hDRNmPUur2YqZrKIoLkWq18q62tEpPSPjI9nb0ZO4PKcx4b7ZQu4dYgH3d0dyRwhd
JD7QhzslMc89CpAptyW5nSnwX2nwvh+mrL9Z5IcjTXUc1kOO68rpOJiynpncpue0dzJ4T56XHLZk
n8+0C7F5kCwK1W+z+lndXGY0h7q1qRNrzJmnMxVU3NZjY8PmbZRVSjWxW36+blHUfyzfkWZCD4je
teHMyn7C+BDk0ioiiUJLvFhvMJZiOXqERBw5quXZAirxK5FfzraiDhx9W8CtuMtPt+f9pNiQP87l
DL+Vj077qQOitjsPeHI63L+VOU77/nO46uyeIMtCtAky7eQQ3vwuOQJkLdXZVEGOvLGRvEOQ4SSe
Ighp/E7LRTIBSrjZR04yF98MYYuzAPBGmgojAAHasaEN4B9KBOgf1AbnEq556q8qWBwHyVQbrgRF
WucTeyIIIFDkEzk5ZEWZcQIV4D8ReIPmJfQGx2SeE94CWU2fvHpFW8q1CYAASYzwHz0a6Xb3tRPP
7IMGzIBjpM6Fxzu3+tlFwz4ohrkyS1sGWrPRSvxS3vXypC7WlAKzRcBfD8NRocjSvbgnCv/gZAoB
D7XtsB3m2ilZbuCvwiy+BxhzOHegctiytAgB7+sbRfSb16N5fru4DafM1dLbocE15GzluNovsOiB
JGb6CfefsdC7kIR2gVUoT7IaPyUpl6hm3dzHgXe4EHp9l5tazapPOF1gqbd5pilSN/m//6j/mEM2
kfOgeLVn20L3cdjUTAjpyvjzbIq5TSE5pyaeNSLQUSF2ApMia6raC146adOPi/N4bZEKiaUorBe7
jSKgdKbf9eCOvKekunR+MqlILKuyWFjDAwDJAj9Y2WiMNqKpwJJLpip0KoctLjIVSJSccSjaIf14
vZ8VQ/z5rkc+E27gFZie2unCxMEZeYNqo3Spxe3no1Z4H/4Sk9SqKzo/eNN62bvuAlYDbb+g2KT5
GLeqs3Sv3V87WAHTeKtaLjkbfpDROsiJ+81vg8x8GUYt1DvBXIPyml0AUjOyHhfT77dGdDPxs/mh
Qfkgcyj0cudK44gzW9YEX4o1dJzlnrRSSidoUwzMMjJy4jxCRdKEcz3Oi24VZ0ilXEjwTbOb0FAm
WYkx6WC0AHHWiTZpakDVbXcNhc4CpZr5dJRfdEfasJw6hD0PdCnjXoNSTXEZquV6VoAnh6a+I5Qq
mzxkvbYaIEsNLLNW1fJu4iBor4nKqZaF8UKbjkGAYdI9mAWkmeyY/6vhI6SSOxyzbbYjhGT0CJA9
0j+g4YdglfjBbmydDlJeO+uRbrGxEoiQHeTMHtQCskXYUE4cIyQVlGUupo6cI8wgHet9r6ZDxdyN
jbqPc/Y1hmZEGS6KHYeQ0hLQZ4eIG8z217+y/0uiJPWyo/j1Y8IQeeg4li2Mi/n3j7ThLcHgy3bA
VgUBiGDygWgKz1NhxQUIh75U3HkvAqD2sxXYIaLtvrM4uXvjyCRpbF9VR4xA37AylkI62Zkz9lR9
LPAZDMQu1XJlvTNwhDqXK6ezGLL3/KnxyX5lF9GOiSZkgZwIGqMzMLTDiAuanN4cxTlyecn175yO
j8zHwSnFe549fcAhQV8FN2YUOZ9VdXPaB6N7R8Vq6vUQOnFS2vJLCTcYmz47+8ivuQINsyAOyN/8
txjAjI8r70mcazw2jXVJqWXwsYlzEj/CnyvHRt/TWfZmjjojpOEQWhH2Z+oCB5gtBWiMqKhcIsqv
iG6JIYKc0U2LlNIkZxirIg1Hof4l6Yv/Erh99SeXfUuDdHI6Tnm5L0tElm2dmh2OmPjPM9IDbKXB
uBJO6K0pLLEytQkBv9pHQ2pVkaLyYRl446Oyxt9vaphG7kIOnkZfczGWDh5KpgZ3hGFnPBzIGDuI
z2v5T94wTerC21Y2FBaiKvQrBsk2+Us1RPf1E3SDL+FYDojy+XOSDcqUEB4UsFguqzjhNG/X+s59
KBTb10wNa8+G8Bh2EN7HdRO3mHjySUd8OjCR2Q+jI9jQRsk6cDS8gLP+Wq47vOjZrnlMsMY1gv+G
RbpjGRg0RDQlYCHnvBhftN+KjgVcnPdvQLLJ5o5vMtHla0tQ1wzUTTE25Cscbke1ADJxax+Dt5Ln
JHHaRqP2pYaf7xC6zQYePpFwYXb/3tsmnspyrv3ipHkrFJbE7G2kJqJvnC4/WhqPwYj9fWAuK/xa
oDkS/ZyjtT2qIKWNf7ElSlIRypmPnQVZhk59+BMGVAKI+ArjLuDYxe8vf5fincz8XSKngLw/3d3O
wTqGwftbXRliznpNreGH7BA2kAPLNBHz811xzagGHZOaTtKef9Bg24zNvVA8ejganhfle/k2gWfo
8zOVnSFVrw8NjdTGMSRiJys+sBDesus4sSMisxtW28m8n1W/CxdkjHoC585/XxvOCEaCOxHzuOAE
7x2oTV0LIlJtTf9rFYh7+nQZx9X56W3h87+1kx8zjzko94ydXE5xxafbyv+ADFmd7OAZLxgS5MXq
evSesztiDeiGaN/g2CZimabyF+JPGv8H5+HZgZIUKEyg6NStnH146pSSqNeZbt1qhgYoMJpvHxnd
vVYPLTa3zcr2P/SMA3aSO1D+3lazB465XhcFuC0JOwsHlJHJOMtNiC7TEC7yymTQOyY4XZEHPLVR
vMQGUz9keG1uCj0yg9S/5YW4JEESueWHq+8vAWscbHBZ0x0yRNvxcu45JEIAKQSMh5CCqygL3wou
TzN5wn6hd+tzHiJmqBv2ltScgNlqSuGa0mDjctKWdSym0tm4/6YzIUv/3CeSmF5ERnNuX13pTWCh
DEAY4U65XNpjbfWIXY8vM0Lkfln4wTSAT4s4Px8pTMaYVMoWs7Z/8UdOCqM2C38E1eeRazwsPqxk
9ZKo4Z/tP5sRMaRo57gwQw0MddURxtdiithK7QR0uWnI+DTW1Oq2ZEpR3ehLGFD9wc/RZ4QD3vww
eaelWVhC/EvL5DRZlIByBfQSt5bU4Z/+13ZKMq3nQgThSyJa0yTAr66E5UFkO8fgB5wSIFKKjdfd
4tdgcPOLZeKjOLp53n+qmNalMUDnYl45ijxzhBH8YEX8DllWliNv6hcNxWaIhGBONdZsQvraZekO
yWyfWTjpFmhNEd7/mQv1WpOF8+WiLQ9H3JDJbu+JYPmkvHVOW4WzzTjPfm+B3145HVAF/I0AfjS1
ZDhCbT/vmTmDqaDPO+NjPenTzlywzBuQ01WaWvxQSQIpP7/bMDgb3GLPCwjUw1NCeeGgbqclHscG
i03rvhxvTWqfg7H+tszkDP6HVoA0GpXmv/P88yQPkDFbUnB4dcpL70NtbF99bh2d+9yaJe7Md50S
eXEIPQ3Usiaej83NZTAY5qHr5XNlM41yLatsxzAeMh2ZWTvmrHistS/ChlAWIXvjWfu6/HM3j8lT
go7OT1vytJEo4lEL7483WbnhXPAIgsowEqvhi62DX5Fl2mWD0OaBSXAGfQlI1cxMWhFDKEQ/h02y
roKilOWwrH2txd+Upa3ehQ5BqJ70u2x3/glyoKRuc3Op53fJvDD+eI78oxiMDqVQ8/9Y451BWufj
2F9WMM5cDR9M4/TW1m2CJiTPvK8SIL5crjCk1zTNB5OUhlvMaR4sWUphyefSymIycrZ6BN+Mv5TN
9tCjcVuINtIFXRYw/6iUrpBzqZKv1KLAS87dK7xbxwez4QEletKMEIsez+pTcVM05vNB2hpb0iHU
J7mQVGf+cmXLGLQof2IelQRqiHGH27zL5OVxpPwPOHzlQ82Tj10Jftg30YCs/QqqaLTyb6kqxpS2
/HRleF0mzLIkXSjOxn6oj1mpWAmw9jP2dy4wFT3GDL+Q+EyCqicQZj36Tmgh4QsgiM7VOheKODjz
KWxZLCINF/jbXR3LdMXz5PVFDlWtoIys1AoJ2+6zBab8tSBD9+7BUNWU4qgGWKZA8jOL0fGo0XdQ
PlEEdFqDww/lC/BWempH8m+y2CqaIGuqK8YKX9sDJ1oZh8FUYyte6j/+Szix0u6b0H45AGAAz+Em
NoR9yFXho81Dlr2ctGjID0Fy652ZG8LWiAxsKtmeANJQrciwrMmI21aYOt4MDAK9MLESDKI5I7Fr
EXvqEi6dJO6SWZ2uaFsZ9D7XQoyZXUZFllNWNJAIJ9WtxcRVzzNHevOmHTMKWrozClYfZr1EPtEv
kQl8zh6InEmNcssVqUfYrGFuxd2ALtlEUdG8S2oC8qW2yMEUHPLm/sHPcO1LqWU/d8b6bDr+3l60
jHYjsRXGjHXoTsM10w4Am/cRlgxXQRoYFr7LKXGyC8NI+tTtGkc8/vZJFChRrmcBDxNgDPCTH+9c
DtIviYRehEPCwJQ2ouFWlIbZ0ADWSbqJKjYAhTR+axRA0+UUh3GHxEVd43YlivAyzwBrV6zQyDPc
hBWJJyLXhlptvJv0yRjY0fREsql24OiwApyZ5kREbPkjfGTEt48M0jkA7uaSVGeuTYXbOivbhHDO
0gGqnCRT3dk2a7fGgc46XUNZkp9RGNBdsAADmNNWZhQ+E2z9xp223VhS621HUYNvN+qwhTfnoX0n
zka7HUfzU9ZlrdYZyPgJ97WXPNuhyg5N75SUUh5QyFtGaTllWx2LoHSkK5cThpIFzWQ1yVPOQCjY
D1gyMd6iRQfW7LDiNgSDLIPDBy6mDvlWepyDk5AJiFTxs/93VRbiNiUbS7hWsi7HU+0kQ3QALF6s
wi6wa3cHVdfkczjKi64YeDyceiCb9AEgdDcq17FlHXmqfVo3yCZKUTB8wxvh5R5qV0BRXuA5SdrI
zNgFUx9T9gabkOM4jqoQ9LJo5e9uWdcRrtRrcRtW2iQKmMaw910Qfn20Q6wXSTo072WOOzjGCC28
lYjGSDWAnyP1r/ENHCyuO4hfSdLU+2MpW3H4kaRVrshKvwKEIBag3sRdoFnUUEIMy3tnMupXPfkM
x6auxkZX7gvslqDtzvkyBxu2g5ThSDQftwTBfuJXtrZ4EjEgDnWGoJ5CU+T3+OChLAtO2oXodZZR
NZhUsFCeKd7W7/3FpatmhrfoakYKEMydYtEWxgrVrgN/514Tl4x8MPwf8DwzpZdXE4LALi+xafVK
xZ8tchjWu2+a6g+TxzaGmTrmM4jSqNJwG7lXAf9gdj3V3p2GeAj2Od2iSdb1VYixtGFE4d6OUNCQ
ZMK88qgsysnqf1XqVkhEFlkaU7JKGQ8Z6Q9pQEvw+FBEdZccGbHH9iyJ2EhpvL3LPB/m2CelLD2Y
MiGmesbNHEQN0WAeBsilvShEhkawhIXDBOQdzpEdyW6yKzm7UyFKiOOVLqYPDQGaPXmBQolN5pA3
/xgyjcglqrrN6Q6XjC2MV5V3Axdd6fdrx/KRodGTDniKQTrbMKd9LCfCVtqamXoGukhEXnR/0JwS
WQ4sTXXl26ATPzlDVP/OvoFPYDJolAITZFsvKuCwW2gGftaVIm/CxTqa1Dnjc4lkTUxhjeTMlgI7
ivBpNAHO1KLIDHjzTxUlHHZ1U1mlp+zCElN/NR5EL5pNiGijJj6GKemmfcAPfshp2RKxh+l9f0h3
FG57WGUVWEJFfl3/2U52UPMXh41KzKJyHaC3eblQphk1O3Ng0dfozbl2VcDk9t5+JCs1q+DWPX2p
bFwxSJBweE3VkOOR7c+Y7bxzipWRcbwTgY1aWoCAd3WnVIAbdigWqCo5hBZ2ShdUyEetNgxKMHg7
WAMXzzUJB23hePwQ2TkdY3C2p5FMkxFXEAfN0iT4G5Ctkf7SJhPN0tD+gR+PSvbPbKpHlcDRmzfI
ZtM+Rl0jJ9WzUxrv/os6mZq4mx6gYnAdXAWIy3lz1XWeFpqc3N/XvPba+ibvmgWo1bSdfyxVqMgv
Sx7hohHnRLH37hhyAM9hrY9Mxcu+eNKKL3/Fg2Ef6qzOldhDPgT7u1Ly5nAdomvJpBYQwFu1MR+U
H/+stowioiuF2CAOr1qCcFTncxJ22+TMM+6PkqXQaBf+1qMYfF+GACRrn7s42/ROnyMq39PCW5K+
/Zc0NNngsnYIGntvihQLFYAVDe4UYjDaf8Z3dg8DBRJ8WyRRVvLUTDvmM/BEpBkeRMM5hT3MTG3E
7aro6aGSLokBiDv8pTVgYOxaQVZ+bBUYnssrTmjY43eDqRRHfJxs+UQILDLnpiQbcF+v2QTePAV2
6JRht0PmE3pltTsJb6oN9hKfYoyl+7YniXpgy7NJjcyGNnQkOEp3JvCRnx4CG5+uSeAPt46KYUnA
WHGo6NOl4WE6RXj0Vwwv1hUxax8rnH1E3lPRywNaATtPtvnpk9XtSZRMEp/uZHATgmPNqf0a3B/P
gIxRdqsxe7H32D/0GO+HzaAugR9sBhXxyue682SQgp3fWzDjTWtRxAJQ0UgmFynnIukLBVz8u+aG
qQtozqkD9Rej5I6ixSvyPmKx3VVXlcC1RI7oGoLA0YN8Do0OZh2Tn4qIkzW0dorEpJUlVpEQmRFY
AJUVnDUlxiFRSkHPGIaCxXl+YYodEREiXFzelQjz5Y5SX1iim6jlXF1Drb3vJKGkvVdMmBhXd9FU
52ggFx3mlmh65pWiTI2DPv8oDvgA5ZRET9rO9ocfj0WAL3uvcTYb9h0WPPJYX+21yxKq97eTtwiX
8vh87fKciDVHq4dRhRPmgOLFDizBfmZyo4wlDoMsrSLgmSbXntPM0NxVvqIM0oweR/P2jiXGvq+5
E+5c7GoFYCNvfqHGuxelu8ARaNx6U3YyvIFw5mhyC4chA7PR8q3EdjKM8cNkg+G1fHIOkoaMBUXm
jsmi1FdmXRFJ6E/SpfGxBGeMzijnxlnpociYZPHMGQEnhqN2mm+wN1fbQaW8Ln/V3LHi/pCnX5ac
4wYLEnCS5x3rg/pfNGY7CqIafgvskPJa+uL8u5fSMRLRtCWdBDbz5T8BupVP1d6FV6TryT3nbng9
gkKY5DGtfYXt6g09JJ7Pml6Glb8B56uHlTJM6FXwXQvhyARTmbMcCQHCECHjzBH28iOy8C7Ed3CK
fNueCUEadqBqCnIb3YvOErbLZQjoIktpXgmbWFmSMBaeMy81TxURSs/1CRPdvhY+NIIfnpoJWVxv
e7JbXvFlyM5qPRyDpiN3kVx135Jw4SF5hbsOLmKAMSJN8VJNJTvynRnn0RMWwQta7sQ79O45e2zX
JUdCZ59v6jyP0GbmODqqQu6FIzSHRJGLXdkj748SZd3QliZoUWMNa3DLHCMvn6JfGF4Q7gxEpAFo
cAaLjUqQT3SUYrXJ62y7hzKW212I26uppxfF50yCc21/VkMQN3TAdR7H11i2nYAqdQIu2ZNmhqnL
WLBqDigh7sW+4rSD1sqUvDEyF0VDbYW9IXU+iZ4pMArfysRP1McX02AM+b5X9NmrJ54fGcfe7JX4
CS1pUd/b/QVe/pNqzeBbnyIfuV+8Poge+FRO6dcvcv+h/X5CZ+73/Tp0i9AgyazolI9705D105U6
Asp5YJnfNzNU6RZKNy0RY2M+Kt+3sm4mNZjeEMMWTwbtFz79k1lTZdE47TvawQp7+ocuC2PLaCwm
p7b5Tv2Hm4Ju4Xxos27U1QkmIh1u7lUK/V47qU9ii8yRMyzxLtPO2+LE18JGD5kUhyCgE0sfUVZS
hztz8WNWXFzW2oPyvT5QorHK1AHTk0TAkGjeOrh9ry3Lt3djOmY3S34bmzMaOyAmii/1BtQD5kpM
jvLWalbvq4y6V68Pe+SGywXPB1gL53SgRV3miks4aVadYwOh6mSSzOMue0t1KXARtpj3JX2wi7LW
hOBYSsIz+4Qbj6z5kcdErm8bjfL7W3yJoPL5Cr4cPZJDQMD0L34UyB76PoXzXKB3NIRQiKZ6+//l
moy83Oe+2xItdaZNy9tvdC6ZElYzO/MN8DfI92l/aUJrExBR6u26DQfuUHPKmE4KXV9xVDMLXpgG
OkTaTrKHBI7BuMJoxrtpcG1HNA6sFx88ODHLUz1ZEVguMN6jFz0WppYO8BvvUJ8pn/a3Q21GWzZm
SQ0d6KkexV80jOxSzYMAIFSixh0Zum0AF2309g5hgm1Wnlk1CtKa7TFQy/Lz8q461QWdgFXsQCJz
eKw4EbrSYtwT4zZ1eTSVQmz5vcFdGEW9fM/r/1fbc8lnjoBXjJUHoNDvR0T1SOqTHRtRBa1ZTwqL
/a+6bbrQrxMw0sfd1nU0K1R34IzrWdK8F/Q5Qn+OpVvzdnhPFPDBiXuHcuOWzYs1psmggdEz2voE
sgoR2StxYiYExXXr6hh51v54+2IHE2uVT9PdUPc707H7Qfghcf+lojRxxYFdA1iPTMj1N2ScsO4X
mbjz5hKI85Nxr+rwig61mnKKsn+lDeSb2KnEWHtycNGE4oU0hrr2AFNZSVJH4ZT32KXTqVkal8IH
raRsdNfKFE6DkVWU6xoiClsJ7oYijoenS8eroN2XHBka94c5nzIdbroHI/fW/huikIHRJ3IWpXyM
qVwa8ln97DSLM2rHPCiK9zA/9AiPYgpFSSUsh0LHPDzgdXPjDEj/d3GuutcUXr9z/ocE5GB2o7rN
1X7svjHx499UmUADl7NZm0L+TGd+fkz8YEwlOMhaIht60QKaNk0/eQQCAUFiN+ZhhmnWavHK1OG7
ot54Poe9T/3J78/zU2/S4fCUVD5n9O7NGwJSzcV77O2epdB855kkdePhzBpfTgFqBKVwwAPsGbY4
OGl4xfiE460bLcI7upcbHEaGrSMxeoDDzAK6IECsuQC88fMSw8Pn2LuR2Zj3xtwtOYiC11Lk//hg
cA9SkREefy5zd1GVXa2xCFx4ymNzZdn889gxn5VvkvFhpYeT2heO4biacOphVji2jAX9Lx9Sodfk
NcsiXk/BKAtZihEc9BmlEyq0/P5vnm6rHoAubPuMwvFxyG3Dt7oLsvcpczb8qF3o3zazqftD3Pp2
WrnDTW5lD8EY3Z0fp0fYEs93gv/9lNjFAH4zOZ/7L6pbVmpGhsV7X0q+hleMsxvUIhBxSgkEc1FP
6rfmsF1lb38aswaSASfqabIfwJU5DwdJ/SmN9Kwp87knKkDkQc/Gs3rPOH4q1dtxY6PHKQ5jHT/M
WQrpvIZp+JOj1otgvxrA+51hzHsSyvDRpAcYHy+t6+8nH60TJsps1iwXHvHwEpm+fjYSUkVFnSbQ
BJEQlphDLZeFY4qitUNmh6kFMLxh9tiDKEiEV3Joj7a0k5I6Xkkd/4PAQqXrCMODNmITGB9y67Dc
pNPrXN3aUqqv0ZHRDIJyAkekJweIQXUgQ5VPAfcanMC/6JhXmxjcnKOGsbqwic3E9qJL5/yBEYi9
30Ux/er9QQtsWcKDV7t76Cw47pClYmVLfyQBE5VSMteifRc2Nqon+AKFXsewETqbnYJFYs7v9Fmo
6uYWC9qOZEm227WVoqj5zYRllIF1QbkhzIJt0eQiZD8SiO27x6N1bw0XjqrOUmjPx0SuLabAokw0
GVXrbgnaEbDpitrbqqy86w+3mCRSHygJWVYg1Ckare4o3B5wT1HWdzhGXPeFLYCN7Amo22fQSWYg
3G2H4pW919RZp7gXzgPXxcJXenlNISsEWNNedppLjZpy9Ujg7QyXGCpwne1wBQuJeV4gifKMPh90
FQcokwE+5vnsqDQ7/2EW0bS1KdEEm9nC470RSW+ybY0G9nBDr2ilK3SOd9R8nuaMtVcS4fsSETNN
wYAaGha1kK0ssSkYmmveE2+TTFycZu2E7J9UEwAw3/EAgoTfSGWgU+i3+iPAsPdTgKGiCOYtMhVu
xSYFgYQ/PVjLM/kipdbkRiFUrP8lwpTBLub4lMRDqrsNZ2GwDpGLcJbFSI2cbuOOrCYXRsJqNJcM
KoMkAXxCE8GoAfKLnaaKJ3jh8Hj/CW/eEybVe3XYz+aby8/pg8nSjj+WGvaSlyfYGeR9hliNY1QC
N6NkxpqCh7usG+iqnEcp2JJgjXGi3opnTopVlJ6vyIcat0E3Bp5Xq2hEMDi4FOfztqbx1PxbyKvs
BydZPSC72p6jabiXbkbyxbdK1DDJNMriio63bTgsJ6ng9wjHA0HF3U8Yf9ncqpDZnwlQjdcpXyMH
5xaA25lLMfzyGlPXBM1OSfsFUYd1nJsqh5Y5qTN8P/hD9l3NYk5XEpDMxl4Kovcjtw4ILfrVkWPA
Ke+mzU8QKSEMb/jqT0dJaU8o8ZtZ0ih0gSppi6xRTi+lAd0E7TumHiObBW0lFub5cqBeAZBdD6/A
Bxq411xgqABXyPUnaH7n2Ac13VcCkZymUtGl+sUlwZ3J1+4UvBKQ+cBpzGgQ0b2hChneDR9jJsOG
3SylmT9iWO7Y4+eg0KZqLcM119lLAONbj4gifzoHE2qmLEi5iT1gJhXcR7Rxu9hifD4JkY8jIpCt
44YaNSTJZPeS4QtRqsRlbZyvUtd8W2UX/xjOKpuV2d9/WD6+lUlnm2nVdhrVbZm+QIEQB04eRp+S
kCApcFyIXsrt5IikpFfXB8mLzcOMpkPRdJRVV+rIaEGlZGPp0jmwmzCs96uO7V1eedUdRxSFOoxQ
wt2YYK3Ff4av4NviyncyEL8YYAaZE0N4lANjwW/tkBY/cd8tRiwFsPllCQbpClFSzDZ2qo08XlJ1
bTQdwC+m/3R03tQp9uNwfhrF0kfagz2Xuidjhy3+5pIubBSBaeIsi1jtmFqYssCV8MNtxkBHsYwI
bdzsg/TWtPooK+GrgzgxLjDZaue2a4clbxRFhf4D2I9fgDYvdxFteeFfOWMlwqegOX3tf/ktjv+E
ZhHYIuhoSMvSrtGkD7g89saODf+rGDAkB3df3JLt7Prv0ouEhF0FOEhQ0um6nDXpksV+iSZpw7tI
NPhvB5xO5ENbZBuTYA6J4kUEfVZHB7uDo2v/nHaRGYY6SGW6CWKGXymipCdiKQRxYSgoFQh69tsr
9Tq2o9leStfhZYxSj1abKi8Qe46Urb0W1ue/B5jQxGugv3reQuCRoaONp75kVOSn3tTzeEnx3wmd
7DNpIAxAyy3cRSDuaf18UaEOdDwUMypvoN1rAXfgD1UbvC9yanWIeqK2ZQV4amjPeUOGMq1GD+tZ
ZZeI3EbLLAfd1lP0XLmo0Ka0sjHzK/m59Z4lYxgzhUF7BC+Ok5So5LEYGLJ4QBRz1pVZfruJj8Ni
vE2A7Or/Kq3l0F0+GAJm0Fy5V/2M2/UHBa3+aSbnKABi8+BimURgH89i3rwaYQLBc8Y2hdjIeDnc
Fozn0vRlG3AwdNoslg6EuO7u+hRqyLnNQCXxic8g/P3oKgq9o6I848cPcCROt2MZMe9rJGUd9Hjl
eGs+vk4IdUSV7hrineWE9zkeR0UY/q5iUZc8f8G+mrm2HpishUVBqN6SbPOr9BW9NCdv5H6yhQfC
MFsYM2+AcyjCK6KHXY4hL6a0XqFK8Mz4m7RX2rBsPfkk+pYSUjm/Tkz1Qy9zGtE7lVn2xW/fbCia
ebUQFB6LWDuPUiBI+/5AWjZucJ/ODKZXzMBNwZxF1wLlehyEUNB+nwQpBRulBcxvTfzNX2hcGwit
7C8Q/PJihV3htRhsbwJZt+bDRo2h77gNAouUmXTBcEs1RvJKkikcOwuMPj104n7r1zyeJJjLqsw4
RIZm9jObtkhMGi4BSgvbWWdfaFK29caa9tzOq0cQLf1Iijd96oRbykOPi2e1+Jf6ogP7XjPP3zYm
MstwfvsBkbeckEkIY1Ee/kVuGaam2Vb2DWV6fvkLfRXTQd+jIbv71FWHSR2Th2SAc7lwcfjXUAA/
NuRrcM7E/MqziWLtv39OUiQPQZe0Yp932aa7Hf+ZTPP+/7x3i1/hrnJc6EQWIySil4AkNm0IwtBC
cz1LspT/gkuK+JuPmJvKvi99JXguxeAu4N/EFx/xCF5KneOArEpnzxqZxcdizTQZbV8erCURuyhn
YCA8WcNIxqcA5/cTuJ822341jHp+TwNlqzO5c9FnFbiL1vYZdV+azIh5jgkJFW9P8mlOrDCiW6cc
MMm1LNZsLZjJu2DQSKN8gvPxVCiKDl0aTdc+DRUjN2d0yytxFvITynezFWDPKliuD0t6B285dBq1
GlY4qjqG2tl57U+fZY/rIogQEB14E+Q9+dNRmJbWFvf9ZS9/yqeLfZzoC8n3F528r/sE++/VQ4Kd
dKXnaP7b4OnuBR8Ma2Up3p4jhkboEYD40SVHMWzrKo+xxojsprDRr9gHUk8Cp93jlA7+kknpSg0e
1bZnRIbJh1t4c9o5bJWe4Vl2DuChGRiFwim8yD0PdvBhPw+KBF9ouLEfhdEDTMNLAT703CR8L+Za
3wnqDmLa3B2bGRb/RFyTaZ8aJFnOQ5GRfX59EFLCySv556mJ04826KksW+vxTjydTYIMlTQzQxtj
0Zyi2vbC7p2hyhMT5HwA5nJpp8z3C2jZnAcPSviFrLXoEa20ZVIbnc3x07qK+Ec4ucDCNr5kHfCC
bfRW6sIVpAE4K13xOtiIzjoLI5JGn38q4ARrDudjSwcfzkTADRslu8tNNI32jlxRVGFWGmzvxZNN
bM4VQaeYUJd36Lx8wYFFKFv5EzOEj73tUyAqw/mlVV+DlXvyqF99kvKG6h8x7pZw7sif4VhwurD6
rYSxe0dLLwl1EEqnLvL+twV4tuu1qqEQ9wX0T7CV6RLJqzVQdm/24XbODIps0bZXkW3Wxc89BVMv
efYTENnFSaGkhzHqa90AP+gmHrLmV84oqFq5XaiVfnDVVtNUAJ5ujWu73G3yobLEMac5IOH4tQez
htSyPSrl2eXncB5g76IPp9+/YImEiTkHTjImaNZoM+19W1fas3kRrq8OXIFh0WQaFhS2u6VhcVzk
qcb9KLU8iQlnddWcXNI5K+Fjwb0G7fmbt8d0zp9B+jOfTnoUVt0fUwRpeUxklkW9kEBXxSXaKod8
BdQ9Ap+LVoitBeWOVTW3LLD1absUDv81NWpU+TvyGE45F3PoHogYCN+heojfZ1J3T1ASkpVx9uem
oFTqtHasCLx2EXT4eedira0Ir/4puSPuPlLqlC4X8s9KsME8mz7ji2sMk+tALCTJwr1HTMoVcL5q
dHAueW7gO7aK+vDcpGbX4RxuiVi6jv9Gj27ptibCG3YT4Zj3LkU0FT8N474EC2ALDyjxBCKg28WE
fBVXvEdrPb/XJNqpWMP3OOqgfrXsPwwkFagVJpF4GRC5mZAlb9MqBWzJzIyAVuy+EYe4W3bNArKt
7rCBHD5OuwP1XGJtKH2sbQcvUjAnRKOMLP2wB1o3ZSEiERm/EMCpUZIPsS+pIcqzdcA/sbdVYHEc
/h24M17tAiNHIAt3UxZ4KbBmEKI0OHgWTkv5bniKvvKC2CpFh0c63ChKqTX9VMFuz6qoqcwv6Dye
k8dUyngp4sSC+IB5hTEc0Dg5ngP1ix+f+35xp/ppory+oOE2tSa+dWCI7CWnaZXVpn2LdLb4f3gw
LGxmkjBefgqg0lb2Hj12d4j9hKwo37mkzTAqk6CcqbU+KYyn8ZO9dQHF7zMUmemPHe2QmgGWa9pD
+XWfzPGYttgdXpYfWzxEXTY0lceL2Zsd74BkroW3kEKk9WCwnM9vEBNbGsyGSVK43IFedbM8b1dw
dS7q7vh4lZV7PHJX2cFz90kF3c8YbcO0mNyQM34/6pwaybzf8jmJ4uzg3w4X8xLpb/BBN2326Ll1
164czZfLoMF5S34YisMPELDX/bk4QT9MMnlH0hIUcDc4y+YJUrI3BPn2OCuQDwctqHGUpq3q9Xag
+Vli3b3WFKMXU5OFPVcKqWpKRoyawe/qSIsWKjp5o3DwiIXIoML5t+vZ5Y5XNFy/57VCMPe3vSz4
/oXBHM3B4dyFa2GZtTLQLB5S7TUBirKsNF2rH7fLrff39u0+d57dOCcxClyB7oeD6Bx8zcRtJ04t
4xiwJ39iAKcIGYHDMtAz4AqQ8Tn3jWkYiGtUCWjwd6rAsoNEswtTnVxTwuc1MbWxr7F9EvOUDsks
BYTOuNOIgUeVjOqOASPZh1s9cj5vn/oFo63E0JnMcgFlykmhVPqimZVvz0J19NX8pCnBheJ+3sE+
qQVUfoL/xBOQDiqEdaZavvgFyf5k6ALJflKn0LmcU6RMU3Wb1Sm75Hynjf3Gl3RdyMbb9mMQqf37
KvgKmZoR8eD9K7pGnl/P7+48N1Kxcm9VZ/7IKs/X08Vo99A4dIEUcnc1V9NfynP4lWzs2f5tvvdT
lL8eQJLUh7z+25m5tXBiZsPhSKSeFNelRU6RIULznod1D1unPb86/g08DQkbQE/9ZthPvZ+kmb3b
4Ev9AyvELHJTnXaaQCFqOtiXdJgMNBzCB6GIO9dTjXYtpdFyLf9xOyztUvyMTEgiMhZpSbrFbqBx
/4eWVwPNuDyN08aHGPC/SEu3SrsavVmbGf32UP+rFQIlN3NG7isKiVqRdTjoqxpXNTET79Ztv8ke
N3lu4RiPXl1YpwHUc6G+IaotBeT6obIgnzrsy2ROUbx6uZ3XDRNtL0B+ejyvwR+4hgzdQ1fFf72h
aDiiELw/Ojrs+sfHE4jBbUj2oHvW3soQi98O5ihf4viuEM4/Xs51fghJfj8GgG4hz+qMiZltYyQ7
obHsqhZ4gOEXUiQ3s2hHg/wZr9ttykvzF+EMWg37dnvqwSFexmxl/eaRntZXpOBwltz/z2BFjqTG
L5QmfUI9ggNHGHdwjiFZKMW4ZlFkqWn5f0LpOmlnu4Vw2j4fcDlcWUoXzqggVZwX6PJzbySRSu89
6dv22XQueoegDbegSoTjW3MlctD90kHQmZxEs0M2JgbVDD/Mr1V6tfhFLCYqkjVJfue+YjnXhGts
K3bN5f1KrlOeci9oOYebsnGB5Gsv29xi2TxU5uOJSIDPrxV47hgjfFzNo8mJitBTJMjozXUEvtcP
v1lA5Zz56gKz95cmH+LzhKll/SaxgLw7nP8Lm/Uip7CKVCduKN8NVJpjARgQdMnAfuHz7ErE0PIc
ZL9LC4fh9ZPznJdLAIYUWXVm4ZUgmWV1cMyZ1giT+1MmLeAoBTNmcU5VfVscS/ITkMnKHfftrDDQ
JT+v/Xu8yBM8RGQeZ+lRY6fDqOF1jdyK/d3iW0r5znFIXNGh7B2vJSYMq/7hm9H4SDmVJlPz1tEw
nca0+1cbxD0oDkVhNjyj6g3hnd2Ffd0EmU93mieAqAE1Hwcs1xlQ/L8/6Jprhbs2KBsjfw0r88zC
y6q/O+wA26M+MRaLpDssPuZ8KP2BjZcofY8KU+fjcKEHI0RHT95ZUZSnAGWcZXf5xbFD4pwaAG4G
Q+2W4OrfQSyE1rnRqapOD7Ub3UDr2OH4wqaSUphs34C/1f4tix4VlET5AlE5taPIC42CTu3qiWMk
laHUXzuXgVSO1P9w4fTCDN/N8VG3Rc2sa6r67XgSQg7AklNmUduVxwMCXk26+w06xQhfFbNBvgmd
I8rzNBFYMz1ndHD11JtftKB/6FMHhxgT/NccgUyvKD+zvND+wXu6nlNCbXvT26Pd9iIDXf2919nU
DlZyBZ+ju/Q7CUukyj0nZ89QVa3HEjcnKmIWyr354kPG/M26XA8+vdp7rm6IOXM+2mENtuJxQzhK
3x2F3Dc54u1JbkbFkJDWjdFOkUPpfIwzxdofBw8u9baT3PYjqdk3tTW7NQlWhncb+K3FyKYutZmt
2uhiXQYsjRrvm+S2jE63RMo2ftGyt5NGejqB3HZZNQKUhMNhLyWSEarjdE1mO8DIMAK9u/SAwnuy
T0RQzRKMybsw7ddW/6AsmzZeYB+rHSu8hP4HmvZ6wI+EEIcQjgrSCbzZGNBE6V0BL8jNSn7FLho9
NJ9+mpifm8Ydze0jWSVRv0Zwdq5q4EEbKlA8VecXYilIoKmsDx4hCyMQNAI7kgH7C2k//B6Qb7IM
q4q5eoB8PQba4LMaGB/xE8c2ddMEs4o8oG30xZ8ZP2Q0PClxXjrcxmh7ZRSDJ0V/wOUYLl2miK7g
RDXhEOpAzgaKrdxszu01/QNTsTF2LP/dE8l8z89Vu+dc1BRCRoLVrrVrcURJgQ4RPjESmDunnm7d
/JKo2G8GGmvWHA0thX6NFV1g2/vjrxHC5hhFrJGvpU+qxCB2XVTeEUCFNQVYsHgbP5uPCuUwldLn
wxHTQkMqO8xhB+1KBJEXTSa7+z3BbsFvEb3yZ6GAP5g0EmKSpBLVKv+DDEtEIGXbAqYtliw1aL+u
Wlm9tDD4lUvCzP2Y8D5nqgb2Bk25Tc/z3LeDYpJ5CsSyFIvLczECYvLr5g57Dw9mco4b/WMKOcx1
a6flMKLpFr790u52TSh1QYv1CiVJWDOouGp2SyqctUD+ZoozMfDgM4AMhCiGYbPxliulvWvkaa2/
clXmOrK1YVmFH9+np9+KV6tuftr8zbG7IN+vd+xBFrtVALPOvfJPvIQ+Xxy7zAgB/J3wrXYnxUHB
tdKOp72+06TB/+vlvakYt4zrSacz6/avJv+r1cBJcF8JoiHlwxJ3NaOPqDTyL+Zd/sP1qoxu2A8O
0t9embhG1pJLIxTgcozf6LV4hUUWZ2rs3NT4DUMxc4LDyUCvQhacxROpKViTFJr39uOo5/CMViFU
UqcMsjyf50NuG1IPdZUFOAEpJBCb4feR1YZz6FRsp6HMtibF43grKaAfik8jIyfL/gWgilBihrjb
JX0tEW1fb92ea1I5puF7C/RSAkTwWP6xnlKfntM3CGsCGTp5LAPKhbY7RbxqjmhgdEwEA9uUbtHN
N48WL/D+2fFWKRVcqiuWFgKvEXmyWXJoqI1itpUaPdJf4FtTVT9YrF94AiPUzIDzT3VdYqo1X6vc
m1U2O5OlaJ+wVpDdVAa+bDzhnikYhFHncICk7EjIGXSBH8XynFyhWzyFHd7eehis8yblP3IKWMTb
GBtDbgi47xdLArRxh2irfh/2cFbMzAZmTMDWCWNklWKyT72WnKTNeHaXdhlGKjGGRNgLMr/rAovU
pRQuuRTJQ1wDbBlLrnuUplhSox8GNRPUqNm3Afb95A/+jDb1Ptkp8Ejk1gc/3JUHOb1JHVmAlfbQ
tNJawnp6UZ9HwC907APw6TxOpm9q5hDgeltXPI+pFvQRhM0zSbWLBUzigx+o9C5+dMbTdG+SyXtf
qlqUIRdU71zAfOm7dTQ/35QKxgVbAlar4ssDwNIqucF+sAydr1/G6kD09PdENzxX3I20OAsulhAM
0n5oTurnToCu7iUjeJG2wdwo7jSul1S24SIob5K4riPdit7nXWMAJUHPRh5+8rln0BAJn9VngBi3
JLHsqoHOeHiGQiFntu/OzoEdtjCujGxEZxDJ+D+4OEl0lv0s/GbppVHfHkbEs4rhc77K5jj2Cune
KvFADt26YHJAresU2ELC4KKQk74ULCBkMhzO9nek3LXJ8R618iIE7Q8L41lLBI7tSrW4d3E7mIVj
F/4MVNebkeFZMj9lH67jZpj5tbSxut+DDPpjcgtuXcpVofef3krfqNjHMtzha29GhGlJ0MBvGCBm
eyFPZ8Vf1C5zhgpc6Sai6F8E9F4vsoxu7HaDKvUewxsBrc0zagbR5hpzwpVDgloIGV+BfDRf5nXm
xDdveq9b3XLOdkOCPUSYl/XjKid20wPM4ha24d/HTKJjpGrIlLBRb0d05lKZxtqq/3wDFyjH7d6y
vQjv6JIVEMG1sgwuBDZaaOeRpnA/vZWNRBHMgQuKuouzdCMQ9/LFfL52D6azvQKAQn0sMEs9zgA6
fZFaZ4pnEUTbW2UluesglzETh1s/zh76HbHA/M/vyNJJab8nI9XZ55LhnRfeNnhYlgIR7qbsktcC
NEnvykfKqDVMxS1tg9uiez0Ht3EfDNH9tVxaFYOrCcgXZwIuAHbPD+XYlRWua9a1tfUqFV5YPuX6
hWiHCEDLiFO9YyNYHIKMkBbxSNUWVrtA7lmcdBMC160UphmALtzbVdTdUjIIFzmj51gyFM6kAt06
AJd01TYDCQ0ntt2WuMkjg2xhNbQLPzIEp2sdl/KUOIipCbsca6ihIUQaw85Xhl23Nd8t4tFrY0bR
6k7f9p1nPozEwzVGucqlt2654sbDH90zRpnnGV/I838acOcDPBjxJ83whaznQES6n4R9pVdlCvh0
TxV7SjaCGUyiE/mwYHRRK9OaZADjYgJ+5fFSFZXaDAreCu2fsQYf8zhIJMNcMWWZVAQ42vkosW/q
022Yulax8aXDmdkcRizsNFnnzlpsaamqyE4f6O4HPoiZm5DZxelJQhXc9FyY9htN6o4OH85rkYCC
Ave+OAhE5ZWizPrgN8DGdTnvVor1SCWs70le7f89siWN9IUQqHLFMaPzRIrhebAvj2lw4NkF8czb
o8L6ALrInfUMEKQbdZWIXO1A58qEJTDZ5dBoCs44hLn1z4i/eXTkJ497VJOvbfOKbrF6kgEfx9bp
7HScg4ma+cySR2ijjQm/QVBjSGZnbYv97A2A0vrru19LU/05fKxXRCPwWZ8m2LALPbJHO8H1XYVV
WJjPHnO2adCoChtWKN0LQNZ3UQ6HpWzdlDCtGqYvDYF+mO6C0essbBvCKtW8+swLEu8OQZt+V0Nb
/dHMRRs7JG6KBDPZ1mlCkJ4sMDuQwmX266oNjB5Kqu04z6NN3AL1SS/ph4Dn77RxfrF/okx88rjE
Us7uKosgL6WvsCcQbvlV/tHZeT6peq4U+IufcwhiVl4drIUlSZcb0F2i/itqhhB44SGmKDK3MJFW
dvp38rS1dRyMMo8cD7di97qbrUBFLPnTsjFoAqnFY01ggpPks6JrSPpC8uRh+nSwy8nzt6mtAHFO
7smdcSeBrw7yvJq2xd9Crg02nSsqW5tzTNptQx9Mkbv2MlX3KX7uPDt5oSeokQEHtRrUvMpUDSlV
v9RDjY0dsESJOwLz4mQKAScPCebbtIbw54FWCWWoEvtX8lZRB2vFqXlFLHkQ8aPpExSqD+DykND8
eRXpHuvOQ7bzfxxTEBYt5G1Q/d3Q9JFIsfutt2dDARHWIz7G9Olktq9OtCToGmb0gd0/UC9Q8n1N
YowY3EIVVM/NBIyJyRgcEVSALJ1oavSo8OFLUW7+W2Bc/cK6/bdMV9+twKz/+00aPjQPJ6vvqD+j
f53Ruqaz5LC4mAayVWFhJFcQ6vnPlcoR7OuL6RuBLmV6YFJ2vlcw6YUemCIF5VYv1snM3IOjtN0D
3eSp0ZQoe4ZbIKEkZcFF1AvhXKJLEBomScHcdSY0qh7xs+Xw28yXWOIHVnOc7/HFX3safqPxv9Bo
9P1Drz5cLHBwCLpM7UQDygaalKBxJ7fJ2EaLSIEeAEwaOMURyzh/fhbXaJqBujUVWxXvm9xyE1L8
TLKbhnkMJMEynhJ7GvOQYya7bhATnve8K6EUBgmDOEPhDv5eGyUiSxptr0puF48lBih97D7plYqk
vAFgfLcVXC9BX1lqjpwOkPxL1AS+0hoW87T2/NiUrk8e6NZ+NFX/p8jPwFhjVwcKbif2QQzIrf0c
vTjgF1M6uplDsU0X53frmoYnrTeZR3h+aH10YEd+ciTphlhyHGlLItvEYERIEF6RmL0LJLYLq6QJ
Hk2BOIiwlCy39so0ts4KMz/eJ4kFGYvc9pFU7t0feUZETBF/wQrZV23JgOBxQcT4gNMZADB+esEV
wBGELhfAl440wrXkCdCo+VZD5StShAsO8DGBJrJcbLgoH5JAqIutSgnePshXdYVQmYJT5DBoWKt8
QyRFkxStKgn9l1sv91xI/J5BTS+9h1KX80f1WYwKmzu3rxoU/lnYPBShiFC6m50u9bJDxgtUWRv3
vOxoOx95to3YT4VmxBEUhurI5iKvGa5LwJNYzodnweAyDzu5NWasKyv7Bh+RkKqRGmpManwwy4xS
mt1CqbYnBYOwZHRyiZjdn4bz46FqLi/Hm8R5dVNx4YtIoqbIlpj4AInfZxxsw3gIaRrkl16BdXL1
fQA8tur6J1aLTH1WHBmgJC0cVjxoPGZ5EF8L+xfX2y21a6VYyTMsajII7TVCX3HuX00SanSCDx+y
ocFtp1k0nl0ylQyVLxD48xtqcbTD9GC7sSVxuOQ03hkGqXtStYTS2CvjDLeBZ+Tt0DsgD8VGYPym
V75r5Pnv66btJxxZXiKKICXt1YnQk8EhZFNb3D92I+i4wasxHFa+WGZ2j5BNRyN4S/RKxTPm+hn5
52KDkJ71JQoycZB0poGldK4IxEtHO1hR4sHVNGQGZy2dnFYkq99/aUfFZ6aCp/HSRek7dx0qfrc1
nMtYwaAH97XyYe9ZfrvCFzBxaYEF2aSdGPAP45zb5Esd7zlZLGkY/jLy6cZcsB0259+Z+4NbFYyl
IQMG65GESiyxAGeAMjFcoZuTZiVmTSMIDpXL6FeOtrUw5dFGRfjwFMbG7seHS4xF/VRms2VZnSrF
XDkfjYVavsl4y5PhUZAGbJitS67ETTnnMQ/inKmv2Dq676FZLouUX0Tpf68t/lPCDXxLhE86wLFR
baVrCowImRFYaB36IbeWVHgsG0WchEoamlo79FZmic8fOQQoP9QRUIHqB0kCqujBlfVowC6UfiIe
tdoobRR7UqTVhohLIY5aSIrrgNoBV+l4tezcjaztdagNbjYC/g4vTP66idGT7M62e9mw0wkqstCR
sz+BBQyqBI0Er5wQGIWI/HxzmhykJXaFY9p5/fLXqA7juWt73Ex3Dg+nRT+Ap2T6wcFUGjX6TgVJ
9dBUQVyX6dSvl6Q53gyddZ8jjGTKabAUofvMvJhu90wQYjn3fePvWWi/3cvyuflw/DCYAenJb5oV
I/aXT+EjylOXl+4ZRYRHNXD7RhITCY9WAqY9dt2Plpt6FcjdEl+VeuGaY6w3x0SxBkrorWPBnpgK
5S65Cg6eeJB7cS65kWOnM+yFDrK8MVj/PDOuo1Ye058iXUQ1L7WzXVGlsiADZGTffHh333pRZ6BO
wDN5/eEysBoQAoIEGqOO8R3dKwG1Cd7m4rigdqYxUihKeK/1lquUAflqlXrJZy5aa5moZXaU0mO4
vWkipkGNzSuwcDfEw2P+JmlZKLJNgYrSJr/WaCxLt2cx0AvXikmKUMqrwQGpXHfXQ+tnT3ktasy/
rVWEXdFNSj1zbzvd9baZqTeR9bLuuOvQONXoUzY8agVXNdE8zBVNCigrCRxwIFLgTiAEMscNtn9k
XWYMf2Ei9/sKXEWs4dNkPswy8SSFzRfSB0XTdhHKO7IuN/uQ7X+Dj5ToetAVHzK4i+/nhP+GbbsC
yURbq0ZL6YKIhQH84s73zfMMar0nCd0X8Bp6TuMthFYlTstsh3dGAutZZOpFBCciS1G0UQVSD5tI
o44KjqsttHr4fHjQ7JsZwxBb8a96W51CqFJu78YH8llLoIbpQNRXqfQFNEUCmEQm4RSVwOIDuuTf
vBTy3D9dvd+UiiA21JAAxufa/GB+LZDHPOQiZUWIE8M48i49etFIi/Nz0dDIrKlC8jhYrj/aS0fZ
tKp5AKveOBSgfGpjMwX2/BqNPofW7zAaRmWZBwV95zFQXoYVpx3DQJYb56pq4YcxpIz9sa2a8CUz
bCW9eWtom2ucGNBezR8d/bxe/spcn5qzbzMxSv6dzl2mAqMtvb1xaIPNbGnBlGkmnuwWNE6sofXC
gOIQ/RlHvQxCz/CZNJniTCjOUU03c8HCaA/MWYNnrQpVVN65WRG57JQlPbW9U14Ay2tLslybyMpZ
bZIP2TVpDxgzKb8JTxMlDoyqj1PdHXTMwD6Xhn5zEWiiJlKghyl6w0HW375FcJ8NJWR5p+uVDUqS
PMjbHT+8GLGfJ1R7GnkMgvLwz/HNsorLaNtzmgpHNdC/Vsw6YKQ9/7uE1s4xzlPmAuRNF6Dwfm9H
5u97D7M4Dzyua5lm2+k+Fl1y775XydxYuQz06YXxq4wIrJkQopNE5MV5ZD72Vbdt3jsfJaQNtVQH
xWBnLMLnl4kg9km29AJXjHWj7Ibj9q23I6OUTZM3LGcFHhOzLZX41OEMnygnd9yqx/kypTQFf61U
M0cn4dNEhuwlVcn9kjLH1gxCzb07b5PTAL5cwQ+Htbnx6gXi4WbkFMsjJyBQITqD4wr78rCFNPLD
kQpuyKeb3+RyHXHnC+2jzD1k1fsPRXQwyJn8SIyhK2sUU0Jbyxvh1sNu3WrSxyboNXbMTEw/5rfu
trEmQTy/hM5qeDDgVwj06wYsEyKuBbxikJXmmhkpl3DJWPkdZU9knpMyUDqoz6827c+xjoWeV3bS
evTzDW69WIlKsgSxIIEYnDHMt1lFujH86hyA/3DVoEUrI5kR1mP7fRlbJsd6/e29fcfnLyxpi+hI
nGiv0KBN49Rm7RvMLjZdfcOSmPCJKDeCDT58MDcgnEmmL7KtPo348mPUIrPNLd4KZHtlQDAPaZr6
bm/nWoZqws2ttuYNEgUHVt0L/G7rzHAhQM/c5lvebo6ihyNoBlqoEluxULihTouiQO/DXMkSnPZF
hY1bvjMfn1uIdpXNIvPBAjp40DJFEZlHgrfHEvOkKRrZcEAeP2rtknG7F8mbBDZCAeXzp/EAS56Y
4t6nAg/V0FtC6PghiYDEOlYa4S6C9IYMSz6aM4dOtdnaAl/1KWGB/y+lWhhlTa/gy6DrEB1StQPC
ORcF3dDxRZuIV+KdBqc2p+6+YbVwitz1h6dMAa7uLggnCq59U+UG3WJ6xW7SGkqWqzM9/BcSJEcR
JTG1GbYsOzCCXVUEFdN2YZExkGX6cI7bES7QqbmFmuiSAzz6HdeCaaXkDKz3yUuOqIWzGeejNmtD
hjNRTOC/kdtl4tWmzht9aG4+YATrBSXyEDsFK0B3kE3H1UHjNjqcvYDh1t0Rj4J2YUmmoU8ZDHzH
5R4Pvi3GWfQU6oyu7H4IA9ZNgs+B9G5anI/6W7jxxC5G6TG+uXGb39cLFJtuz3gCcXtB3Wlv2txo
vThhNtJZfsFpJArexKW7Iyq0BdoG1WaofKwUgbYgifW7VGu7157XNkyS0iZTwEfuG4Gsf8Tn+FAj
xn5V51ROeh8fCVgjhY6RxeBWyLM8iokLeryyzaf2egc+foHBueTsVpY9Dkq/siANkYJLgXoeRQaJ
iKoNI5RCwayZIN5+Lw9iJ/9F1Ri1AJwUv2VK6RklesZFuIy8odGNKVn/pA8ASPWqfc5Xnm2vVPDb
+YErqPmUz52dpjzpsuyx5HMTU78rRh0eGprTNoLZvHeHHkLOuTXoTxVKFuu3lilehcD7Sdm6p7ft
3BxybLbvhwgL9xGA/m/pCoiMgojGjllebv3nlfnHbGusjU7eFNciRFmbWpApaNsD8ArX2rlxYPuU
Ky00WXsndKE047j3pTKHOwiXPLXS2QnQ6vZvH94Kl2+0a7K3CtOANfwgxdmVonh0+oJlzIezA3ej
oiepXnlSNVVbNKVs/sa43uNiJXcmGzQnJR+7lwRXpHINHPZOcCg57nUhiWjMu/zfys03TT2MM9cF
JczsFdV5CAgas0MdLFUQv4TYWAu64WqC+N9QEEVsOl1Gy/mKDVxMBpibcMK/WpJJOhXAEcA2uDfu
jyj/UY+TUr4UEnUybYd6X8ySdYy/IUnJWShlxGAHALvt+WqQmbAVYs42nD20oQz4pFJ9vBz5u/VU
/apMUo3pzcqBuOA7epcn+3ZH3mwk0d6rbIeEPmGPmYaDWV1xUUhhBs/a72BcntQKjFe20Rk33DnB
KxlvVo8K6pbrt9ZTxl0YK8JoKYOVvC98x1gR7bQie1vI1fbvXvKJMBI1EH/7O5uzcrxtPd0+cO3N
nLk8AslzyXpRmdAQ2zCkdcIY+/wjc5Wd26ewnV5Z2/K3o7ooAedHzIRgVP3mIRtLE3MDpqyCDeDR
1Hu5X+rNH7t4JSupDvFrUQLwoZ20m8d2XROn78urEXMLei7iyPY9gQoWw3T3zD+4dCkUdS8qVKYO
4gQE30LVHEJKFRAgW/wJsCizejuvGTwZBjAuefgJwzel0MsZZD/2uG7yID1I0OL4jUJcK0y4W1X8
JuLeBGceAMPIS7IAmo4SXIbqyGXMaGvlqvO+KyWQwGYxbDjIlz925XW9+E4VjtkW8HVpwcV//R0C
0fxb54OqPGIyeRzBzIIHCLI8oJaJeYD56QA2f8xQ8Mom7UybmNbMymlRaZBsvVOmZmVPldmhjD5f
Y7pvc1eQFDT80fUNyRU51h36NDGKpCfB8Ks5/XDeiHTC101Xorb8wqdSdbC32U41F5n9dTyEtneb
G8Qx7RuqbH8ywQUDoW2DBdIYoGa2AxRbUHXq0QmqnPjgheGp7YIGcgpRdc/1iDriP3R4Lao0+vxl
pzWcVObP11i4JqEd9on0mSfatVP0Hao+oGOXMagO10FZsM7wWHkH3y0BFUmTsQ6NLs7YRwcXTmIZ
Tqw+P5L1BUPZgSDyA3WEWoTTDNeWKmgAPTwmhG/Fp2qQe+6g7zaGcy4lioAg2EjT79zyyz0WDWLe
LhR8Z77vyiRcToGQsF0oQ/CJkiseojwFv5yRjslExPpiCM/BLdmEdWfFhXABzIB9TLAvO0jiM9dz
3sSkbO5BRZVduRGGrsmWfeArHme4InXGUjARAxEavcU+il32+U/SvW1LhhaSuDcL6fRoz1BhYuH4
zp6V1CCC/6yvv1mFZS+yu4xoX3Yw6jbfcwQNwmNe9bg2bCRZgS9jKG4Nb5T3wJuv5JIGbyskg5pE
P91swKooaY+dDJwiJT0dnL5NoAsJgdoq8CENZfZyHXdDyI+riR2Jd+rNeA25n+ZBj6uuNlNz0dUP
b4XBhAOWB4iYA9DZnQV1cfTczoKfL7FUvUMhOsdiMaeR5HwpNMAqNOOIQ443RkAvIwr+pO1o8jPW
Jqge+AJcdi3h/lTcXZsCaWEzbQCxLz/szE4WKZ/SeFPQxzo+xn3th4oFuVPBrVoluZOukI6c1JGm
vg0+uVDlhBTa9DY9UdzgGWoQghE1KOnThxTmd6LeheKTIdQCWVEF4LCviJ4Vr2NDiCdOcFRf0MTF
flHaNJJpvDLXxER9M8O7rGrUZqketLrYhutqDP94+0Oc55nMhq6sHvC9rR6s+27gr+d8LyvoiU15
z7R4woDd6LK8/cp+gsbenZYBB+ynWqT/D14mEPgb8Gp86XEw82O9z5mNgSPKQ+l26zGUQ4DPN788
EP7fHvR1RBY1lyqnXIFoHOygbphA/f2QD8di7jkG2naXZG+sh4OUkHgc10jphXANvWR2LQPwWinC
xh8CuV5gGAFxrMFvU9fFtIXXSfLHSKpAUWyCYrScmIASdVKmdMmwImnUI2faUGsU9U9FU0yMik0B
jsXEQT1cg2bwpF9ug5nMrQLtm/S/MPh+EGsXQS8ncPP6nPvdwwWhQ969nAYZz58HxrowtMT/fXdJ
l9I58JxJRw2bSc0M7hSz9bBFg4B7/EEy9e1FhS10Vq0cH7wr7FMlbqMB4w/qdIYc+h2mP7k2KrXW
9qkT4XwNaNtA90NfRqe0hbnfZBzpG2bOTAXw81oAcgeN7MN0dj8ak61Psxxdp/2o1PQWXhDEQ/v/
Kcz2l8mSM0qCheiC8FNk1zFRLcpsZbQbtWKT/C0GdlW7f32GSdGtu7QgDiD0O90x91owusUzzwbE
jRrl5GCR8hfsY5EZmfrQcJeqiDekL/CYHS6mTfaz2Hje+3BlFUItGrraGNVsJl01XZnaXTUazlkO
LfuEeCOUnby66KYy+23ATgx3UzPoQUGFUx302IT/g93zpiggV0KEfdwzHMMi9Ux7ZaiXnPE4u8hf
rg29p5QLsG/sYnUfjzs/I3vk2Q3x19nhZk2BACNtiGGcLzPIsGk5tUTXzLcnWXa+nbhbOahiJ14w
ScMT1qx5hnWBYRrFmq0LhPoazuyj26c2UQcl5+Jx2RyuHXAEenz5RvJsmAc5CZoZFJYpIRfXlm/f
w7mLU86jqmeuveB3U0LmZL3EPMYnSYYImEKyL1znEGZ+4qUfc98vSjK8M6/HeJeRrxQ63rOWqYAu
U0ax7XVOLKJSZ91TwucLyfpLbbfnKP6gWOsqkB7aZYVKqP785yd6K0nwj2ABbH4WtnaoIuDWJIns
nEzOXBPF8auCF/TkyiiUWa/mBvuSZt6qIebkGH3Z+iDe3aFAPkEOAMcFnq/hUylaPs13LbBd3chz
CymqAKtc85WpdfKCUMhJnpyg782+g8F4tsYoAyC79pGWiuxceKZMIPnWsT+amNTbut95XM/AW6c+
6+DIYdEyi/4NPjXN5543KJcRu9z5Gp0SDYW5yVpUi4CfJhQkQxpwflslZZBrwPrv1b53jBYDkHVk
gRombONbRwZBl5faIy8HOwk1yPDZ2AUarq0e0S9oybXM2+c0JNAzubJc/UB4RI4zuVTL4NuM32Ii
a5Cmy+GuB5G/L3O8Hh5umoY2p6D9CxxKqnOrhtdL07CLmgnVrHa8Pl+idiUtjUMWTTBdO27Ldumq
sAd4KFAy+XFmILh38NDRg7bul4GaIdBb3NV/s2/JNP2j3IsASUT/Zy2mj+svbK3UxIDwYqKf1AR+
/lJ0XnAQYOcvVw8S+unpDTiOkO1lmARW+6fYwFI3oKkM162NPU5V5vfmLXqIRHgrSDrFVJ/be5y3
EO4huQ+6gADMdAsH9nU/VBIZQ1V4Rpmk+SLsKuwDG9R7jw+nt0/0iyas/rRPg5V8duXd2yXMw40n
2QuLFoClrEbLudY55uewsiybMSa+TNSPXkn8cK17iJ9d6D2s5ASanvPZ67LwrpuQc3x0xz3W0X9b
0rXUefEVNLVOrJiAAXEd1ZMDA3IZTUblu2I0ZI0giveMqrJ84wEpWC8keudvrNVULaL+HvwNpNo0
M8kAeOmj8wmtI33JgmT2gJVEs6olyV/TLIKFCqR7gYN1Rbq9Bh4+hLp0FV+Qwp3Ra+iVgGQeeU59
VnEhPY6nNQD8iiT9OnfimBkisQcchAnluCvQp+7dKToJ9v5EO7LSjBKsZqH3iXC3GIOn/kwyAADx
i5kAczmDOndjsh8pC+gvmn1qDKO9535J0+EqRvLM6j+jNWlRlNDWCumGHceQH+zkxBPRwvWFCtdV
yPo+qkGdPkZQF+M/9Z15LPEdxhTSvUxW5NOtTSuXKNmFu+DPsyBuyWM3qtKphIOgXEF7hvpeHRE8
IFPv5H4m2GVdfKy0mhpBhDZBAFW+9JGJEwYxJxCo9qxiygFkOqnxwL2UASIrMGyU/WTTqCWarBTi
cbjJnPZNBfuqDQpODEiuimJBdrPzlgNIwVdrEiWFVZThe2nHI2VvSL9kSOoVMgdl4epuwWBeZM1Q
ez2SGbqo2Lwf1ZgSSsK6h8KQsQA/5kAccPNPjQOsK31CwL0TxJtvh3i2KrVn3T9t0WXAdoAPjieI
de/RrLJ87SdGtjbn6ZP1ZyJldQHBxQHPxY/51NeIDM+vL774C78o7FXTNcPSKkM//KBqPlu+ViNG
k0oMO0HrcvF4ZXII87zqKBucs6U5n+2FctIic7R2iWAhhkDB+BdCwWQwXygIOBJGAUDLCViCbcQ2
xxQSV9g85GfoJwCwl9Tp7WKBLnZd6z46ph0fMg5JmPge4ifyO4VQJLcMF0ftgU91wdNVDxzo8Mgk
EDcDV4uieHlpHZKLKef9D7g2Nf5jQ9xtH2O0/U3L/SFfiIQS0rzEx6M/CGffRHi/VVDTXeT0y7Xh
T0LECvBbJlrC/dwF7m5iqOPLAuUDGZOkEN+Ena8SmPpLkhEaK7P4e1hlPKmJp2oWjLrMPav+tn/5
QKWJtlbNwZRsMdWs7u/eXsTrQr03MBbYNw1zZ95wP8HCPtpIBAS4ux0/1/EyfsKsltaATdDcNYzD
dbREoOEG/hABh74WdAbTLaF47e/T75ZoLgZH4a2DkL1Y3C3QCATEXcaTSnonUW9FMCQmpmQq+Nw4
8Nzo9arlrkEG/LPB9cJRp5V7ahT5jM1v7zKWxnSqSCIbjYwsFSjP//H9DaFhIEXrNDRIpfGcZkgb
zGMDU+QyhjWcRgsMArtBpZ79+StbC9VsgKfwUQ6Ked9QwVkvEp7uqM15IKZFNkluS7uWoc9omNNa
23MKPsnQZyvC2iV7VqeAC7Z8TadWGez35HP+fm/O53HjPadXd5uCEiu/qvdIz6FL7RudS6jneNYZ
YRIrbbi1UqBA8m6CirANawcwenPfvW8EElRpUTbye0HZ41bpTpSpjz1EqK2wTTBHa7fKt1AnjGWe
nhtTfVOfZuDciPTP/+DrqTyV4pFL4Wkae+0T04ngAnmq2qzIGFIoB9kerrnsMhQ3eFN1TB70yJ6e
Rx2Lx+QyD7EwN8NcWggPAiBpt8qsb8rEUL9FaNqz3zOgGrue0uhhKlOA2BRAh94+r29ZsoHm637i
bGXAWOvXuTqLru/HtXRWx4q1MepTbBVca0WAOXoagU2qQObgq5Wdz4ExlgG0fP6OLVt4RTgaTp1V
3ZHsF5IYcqYE68Ccl2KcLwRjwzrPyH/6U3oaTuAcKtRxGOVaTuw61Sx4KjCYgryjcYOFUzgugoSW
SctrsAIebw27VMa+hxtfJqS2kENJbzfL36eh2awpkIT+jzmivAkmDkTu6lyOVOBDqNIe+WKKzNFF
dzA2Ofn4jSgW9qFIz44FIreH/DuxuegUwrRy2ZR6gQpobziE6KfPC1qu2IYkmwnCkIkBUClZDtsj
ybr7fx3H0Dt3WrUahqdZpmXdU/ChJRQiy0YEjItY5r7fk8jjDe6mp+fqCUzHPz0Vu/dE//PZHIBQ
xGWjOmL+N2KFEpRXlbmVrXuvvdTccZ97H+Am/A87P0c9fOOC6LUEMUoPaM8kTexqc/AD+GT4b9Lh
xnVfTt9bgAdcckQ6Ysn1HlGwemc7pnHB/zRy2ga05JjNBJEd77HKEvQn/KFXP3K4SbX+aaYPT3qW
O2UJM1iPbaNckRKb7yNktSOvujWPvOUvqHaxJgIkdk5pJ+SHDgLYY+o5gv8FYWF2f/ccu9ILiK2/
FPK/o/z3jXgJfnVnhsdP2aaPrvxteZEDk/dH2VYYhRimOa7A+XkCtAGdETh7aOomcorVcVsiKOXM
8pxM8WCetxr1WHdQpmzjNt3Pb+T5E0P0snSOqgwAtZpoixFCo7EwyWU9mCveACZMWzvCYKovzgsS
OHjVwKKuI2NFyRMv7YeTXs2AJZIl1OoPavQ1ewAl0Y03Qdut0MxTNoE460FMOKJw35fPtggXts5U
uR5BHxn/s+ku9fOGcm9/HOjt3lOxJKtggUOb1U0KVjuV9cQTww2oVFf59Obzs233uJlGKaIA0s+q
islDmjZ854DS3IB23ZS/G8AkAwbn2TP/2kdS1GME6+G1o0yhxqjw8k31j1fI5bMJUzQ6sfd7Q0On
+HSsOcbx3DWZKQIegSAMfW2AFPOaoT36qc3ejziZ+pDTOx89Oe+J3pq4FQTn1yI2o0TqglqKS1uA
7eHOPcRYEmHCOO74vgin8tpNVL1VFVwXaH0ba6LzWK9cJORHKXtvLcmxKqdcwe4RyoXuNL2J4GBv
p+aMsapSXbvpDbCKkOz81RPNkut8Pw9lI5lIJOE+LIkztE4h72Ky8NSUmWx0BW1lnl22WmMpLUG/
xRoAiMxfJOKLyCNwJmWGjS6VBtK43tgfk3juQQkJupC61Hs+uXwkV29NN+k3WYU6k6raDVxA5Zp9
uOD/SpEgyruv/qGlZ8hHv/LNfdqFEGcUdiNhtJqQ34o04XTbjH5yE2XYJYkkFqAk3g2JjrbR3Wpz
dFPDbHWQuImuE1PvsJPgi79Tpdn0vXJS902dW0/B5AEi/aO4RVZWzF3V6gqvWgHqALL8uQ7KtgZp
m3a/Plc9ZofS/U92NvqNmWH5Y6Q0fVN5qiRCuvUKt4JJE+j486CffdYHMtHdVAdjuHvTS59LmAEd
DE//NcY1Yl6KXiIL6UtepMFS3PEcP+wGZXxGHheISHYOkwwHSm/2IbgxPNOPPRsewipSezmQHLxE
ZXyn7khiJJxAWFwje+koVirI8mfQqPu7h5mXFQR0TDJYEnNp8Z0Fqxo+Zqaxg1bas149TiUK38dk
DO7Q8k76smcEl/sTDjVGPeBwTzZzlQn+nwPdGqiYbZOlSGM0W0lRbjFi86oAR+4mTC+X3yOd/F0C
lgmZHxLtACEodRXo1DhqjVjlohd3LqqZW1xrJUJeMdVwtBwPeaeOKQxbpi1Ef6DljZWLVBJyiaXk
NTKAdMj41Qj3D0KHvXJVizUaDHVBF4qdR0MIWCPYbWxZGjVYu9Shi5/dyZgwWIgKsbGOzaPQkAQP
Pocur52OaTFDntrsan/KQjUP1nmpfQF9n4GaY9S7TmMCFPLq2kvUREmsOBvbRrQx2WgnDmXY2ZL2
zT5XVNPfC0z7bnbuvidH1Qei6a+Cm35nsY3rmLawC8KQzD28judQMPB2BK5pxdAMTLQh/JoTUgCk
BGY1/HgFFYnA0GN26R/Q/WaLQNTZVzZeTFYLWj2MSgfuBL/My/eNsBVkARo06pe6ZaSYLLkkzCod
SG0L2NA6bqQUYBc3GKGLro5OcLfZBRqdkOG/TPURX5ds/sm9nOCT83OcI/A0pH+upNowNfYeATYz
yFqsJs0G4obGam7ViHBq87hi5kKC1soI+dWkIUElDh59viYQn7lEnY3zkbYrtaVC88RlwjAopoN0
0CUSXAiIV2yG7WtRrtS6luOZwvLqQHUeXWMHSqaphdyHxaGRFJ959NUraN0RGE5ryD3oTo1PmwQL
euF8rmgiaBYSTTptH5GuHW+XYTwjERWYvQnZscnhP/IlATZuIm12DDg9ga1sbkqMZdtR+krx5gHD
owbmmFmsujJHMLC4iU58DtRbDJuzXxxHecp+cMPTMosPFatzUi+p366JJDc0qn41nO9l71D3PPPs
MkTwb4y2aoW/uepR5echQOhzzQCDtp2Ht8+zGHFTSKBt9Zbc+NggM+BzGqvlg43gbdj9ojQSeuet
hrj703X5NEadQAjDZoJFStrFaP2nPs9+YFTuJlqHhTaJjVTckLUPBaGB1zN34K9BkvhB14Q/YYui
CUzKoFWUe0fSi6oNdDN6pX4alKThTvQIEwU5lAcXilfNxIiGPZe29bUsbZfsEo5uEkihYFsYcoYt
lDYhZz4gqerGDGwPm13UtdPw2+fGcvCnET7JDnbYtEuYWVvkjGP30lwzJZphIUV3b6EiJkpprFt2
2cVLV2moL8eokqUGXyuXoODChdFRj3JFco3DFtjIzm5zVvv5gToh95NrZEV9waag0mTKL3xGIov2
t2vI3XXUqfY8fBtO0RA67S0QlIEuoGDY1kvvEDxrcPIVosKhkyyNkP2RYwqMtrPxY0g+zhWOi2LV
PYobF9Be8mRAjOUbf5c1USMByiBFTm4YyTu8829YeshWDf6Wo6Z4sCqwhF8nxSEr+4RCJqydURHX
6xTefFJaLhTc8SIt61p5IMyRfv5Y8BKNJ7gsowitb6vbSiK79bO/dRzmAvht6U3I9StiEaCWcze8
PrG/s6bJIHGjq970OREqZg6hy5h0Uc/KH4mKOmFzCSjH96H7aFYATE7jCCviwDJsTUhy9nGYMBad
Fm4qA6L9LqJ4UreFLzkaOaKVgJiGHmD98zPmigmP6OqjinNJ+mcQmNmS/riAme/W+XeL5VvIfemC
KbWua6xzXriXYsZyz96FDLdiXRps2xBb9EVLDEAFAEovJp6aAl6R9btBUasETHAButQ/XVlvfJFL
VeCHwNND2AiRSoGF/01NRcXvREkBdyMHPN7Hx8okzVvCevSpgbUzGXhVs4gT+zq0xI/YiQ7+A+dI
jHz2S/fKB+toIj8g1YCxD4jbZA1AcaKBFmiyXfjMENBvFvOE86n/WJ4lw74GBTszL2shIA1tbXvz
CxoR9D0Ld2coUcUre3NPehN8nOC+agicoogk34O8GnGo4UT3SoaKQ+01SGDDj8y1zNt1QXPGLRpn
z3irv5nOe8nV765CEwQbgOFuXai0a1e3QZnKh1XCrHk8x2CVhcHczBkjMCOgXGUFjHNJMhKG1TPu
fX6T6rwolZcfbTo1qUNvvpJaIhnSWN8hyL92i6fzOlK6HWty1DG6uxucl6ZBH6zXMJybWQPHWSBw
VsAzj5/yYKyWj9Z4WwjipBryJfvPXu4IrrfZfvrVby66cNOHixyGy0tywnp8lH/fy0+uMQcKqWu5
mKsZV0DveEv6vCRSaPI2ZNE60iInCfUE2+YIOmjZtmjPiHT+ABBHYEgjoxYb6NtcUw28jf1DWiPD
lQwNWew+ARE5KSiRM6s7cnLW9eaq+4DBDsyKUVo25U/R8sMFv6HMEXQ3EV3Qg3/cAEXQQe6SpmKs
ZLDNIfqWxbLy+4GwR7zPsJ2zWXxll7zfn+d9K+G0BEz8seFEF4M2tvy1NTe2LWIok4oarnQRGlYA
3hKrjMZIiJk/DDXH84cpzVwtm5f6jizb9I4vFvIIISmRi6oCN6qC0/DkcCWRxgitWVEIcPFWvmd3
q0GPFvaSOI73fPQaKlUX36VJDRi26MkfGMUu8xUUVC56/7Ve4TkcWHWOBKfOH/A4iG8tGZvy/JaD
FEMjf3h6bfDINLI6qgYXwjfN4MMgjF1f7A2szrNXWixSPjAbNmS6nEUTDs4xehR9hyJoowdsfpL6
UEhXeZ4yNMGoCfiNqJ2Bq79uKNGVpH29GXx5UEzbIEIlrlSqNDiApdqXahXtiYLXCZBh4KQXx/FS
uorLvj+ZgE8wd5t763Ev4x89e5ZOoNpZvfxBaFgjQX6y7wn6WzNSGgBXtFWfVq9/slROk9qhpAc0
6kYYVgW2Tq5b5EWLhS454LCWRWoU5YFkxHCapfGnWuax9N6vKoS2KPvs+lSs/K+JV9lQErf4OBEc
P7aHuSIW9H5jvEnhG4jhYsO93/80dvo5jQXVK+rn/GuROJHqeUO45o8rrurcqvbFpepHKaB85g+d
KZLO1ihZSrFbeSB0biSrJtJy+4r5YpYIvnS912FP59Q11UTCO+Z47lgCGhNXxfj/uedXLLZXjk8t
VhrrYSi4THyywZb3/yq3Gz7nQUqDFJjbRgoXPvJU2eSoKqwmBIwayFsCnKjhUNXu/cUxN50rqcMq
tmBomYwUAlKxUJ4+Narye385Kpa9pxoehg934Lis91t70bN2/ep7v901rTNKgdB6kUBBKT83kCFA
L7SE4jWfpHDP0/v/UqJX/4zuthV8O3S0o1tP6fAoycOAkpc2TZc8i1dP9gGGHIBTDyyNwt4Gk+EX
B/o+P8bCnpybkcknlSp3n2Au1xpUf745dggPFQ0pNUf8FYx9cCciAKI9M1g0Cg23GJYyaXYYLMAV
7CJ83mRbXyGkUTjIzexv9R5QMuJKk1Jc6FWTaJNb+XyltBRuJdKxGUwMrBmU0SdTO6eFGiAEaH+d
OR7RVAJQg3g1tqBSz7FJapm3vApwkcXSesFEMUWwl/BPD5GzJ/Q6EqxWDJl37tT9difEl17yqXax
hRqNXnxHwOIsNFWd4852qiMGO4wT9LA4zK8cc7NOhIgQk1pahej4LvTPVCyBOiCZ0fgZBpPOIPGV
qhUdS1vX8CAmagxLEVtvwDyJ7TCdFHWvQnunDH8x5hganWRbKbYf4Lrg5Sh7zIdUSXR6BXKrrukx
I5cB7oImRRMadSfvgnxgUoh60sdAz3SlGiH8ghZoV64rEPCNRgAONm64Da/7OIefXJMzkaKtIiCh
6brCtD1dR0IkhLAm6pfaOVzs0Cg2NV2HouQdoeOkWcJ+oU5tSDOSA1ODQYURvANisucF3YrvQrWk
ynxALFhCFUt+XsAWQVm+xPXp7HV0H9U2xiLXOeQhsRjmBf9gZP/jL8mvb2Rd1wTVOX6/Vw4i9TLu
LX5P74WY2nBbc34booM5Dj/PJo4H5EmC7RqTWK2RejfqbjsY3raLYNrERReAbK+xwkdchlXcyHOl
6pwlm3QeQhfVRxQIPWGb5Q8tAtOeXzCQEDLUzG0KEWoO8t+AGKGVooT1jfn9rB5S+0PgUVlmNRb3
t746VeCxy2AWlQm4PVuSIa3lJnZJin49uXNzOdxkSJPQYM+t6YlWPC4X+cAP4rm/29DTx/hUo0Qr
6tNv98T8wJS5doAS9NGLwsYEhx7+JYEB2wg3abDl5fIanZ+jydzCDvoKG9UrZG06LZLgqZcdmnx7
Fn9NqdEYsTWuRJ4HGscU3VZJE5AOecA2huMcOSi7v1ZwOqehKyjXt7nhDvL46f1h9vyuR1wYgN/9
fvqDUTcskrfxK1AhOZbpeRbxoyPnp1B+rmzcFlDfRgUpcf70qPK5VJFmpBTC23eqWlzyrZDReGbm
DnmBQ6KHgh39eqKr1b24tP62ahrDYQUGjd6CjxvfC+P0HiIlTjaRs/ErqDlkunl1boZBWsiJK//n
04YYsKPHGN1pD9O7G9gWTD1DahbTBGKJINsi++T7D9NjV9q3XI8foQ8LjXEJw9JjAov+LfjF04+J
/ZL7HZGDKSE9TozG1D4gZTFF6hZhrB9WIht5gct1DKPLotgzx9Md6zUaKh+2r3h605xzkGxlBc1S
XwlisvU42/I3ylRVBeaKq42PBGSoIpe6D0VljXXBMGA03LrKZXD56wSdaNp0xiM4zoWDdZTx1o55
pZMtY4yBCnmhLyvWHegCTQcGCcHzM4QQWGUn4ixJuBvJMBBs+DEBrY30ZEh6Km9Dmcr+YbsUl6Ir
Z+Goq/DZNTNwzooA0CFHgxm9ceDdxpjYKRUlVapyHQCpLSY+c40myhEANOz1NBOdtEwZ36HT/wlZ
OdGlUpYNiLMVXJ8c/B17VBXf8SA4u48WuG6va5ayREJhiHG9BVSJO94aluvZbwFt/88oxBfkY3q5
UH6OEU+3LpGDiP5qXhzhnJjBWgLgrmuQc0fDq1MW2KRzmg4pXIzlazdVEZTRL3hwCJS10QsxS6Sy
eBPB+bYNfn2qSnXvpFS7OmPBb74+HY6YtEP6/fMv8ffBCbFpNkRu8EskkVNgN0YdZHY6abYBK7JU
31iekwo5Nr8CExHbDpMvuw6opCj/kYAjQj88n6NFlDo4Prx6Ejsyzzuf50OqaLWAtAs3f99x/dV5
mtohub9xL8tz7Yn3+RPFM6i14v+gwuFMKiuHOquW4pfHWEDZL9s+/+c+LBtDzBP0lhFo1UqKa7kZ
bVX2/w/eRuugyolJHrFmWwc/G0oM/1WrtDg8zeAIab5zQpAMBDIHG9joXIbTjx7lKJiSrnAwuzOT
pfuZygEJkd7xECANT+B4tInQAyBJCBUba1pcN3fXwzNAiHSKUllFaGry3n6+CFrKF7IpWep7r6vo
Ja5+2dZ7Ip3ryU+6eWAgLYCIZLvujVRvA3G7xTymgcAg+OJEy/NE0/WitHFKv2uPn4dgj1wKcnr/
zDfGietwwyCQefT5XTJO7NnbzZ3u9O7vx2fNFY1v41xycdC4RQfFHStBDvw171zBTCCB2U5hVn1e
TguiC7zblAl76wUHkGwWhzDMRXjrqV/pQxxPdyqYkkeK8jY5SgAiSUh+XfVssz+6U+PykOes3+SS
tx0VSwpRFAmEuT66YJi8di6DD6D+s5s2pHAvt+CYaEr2WEWfnGhH6GDtuIa2BCcmd2FIUqHGSHFJ
oVAUu2dO403IPfPoi2bb3S5mb8rmBkbXj56rvUcVA6dkejGLdbDVj9HTHWLkAoIMjiR1yW4SKHaa
SpVyLrEwbZjHjJV3s8lNFgQjL662DpefPZWjxbj+RZsIl+V6KdO+9g1BG0xdqtrktwFhLz9JqBsR
cmgrs1uchH/S2oCu8XgMISJZBDGuKK/8oASXGp8h+1eKCP8Wtoa5/Hegjq823u2mXSje3jixYh55
T0eqmoA++S4a+8B2UqC506upWJKxNCHk6HfDbIgB9SK/XAC66GY0WgAiZaXBVkKrIf6GENDY/Lug
NL71r0lHEhDLf2cLcvWyPpYo+3pm7BIaCq49XDVX/VN1rYYarbe8ao0ywKIwZnbAmVfz0KQBgcrp
EVEtB8jisPQMviFHqmk+o71+FtImtrvWSuqoZb9qH9E5JAup4WYvvxQrqh04/BCxzHijV+mWADWX
JjIYUjzaRPqQmBi7hyo7F9+fj25LPRS0HNCN/i0BoQOMyTgRczS/9wzdTUyyz68ASZev+IRlpJPq
2gEwK//wPUYDlQRBeNzE6j9k9RhbJLK27uVOnBuhourKkOW8uHkjF42NM998pLwLJxD99l5yD/bY
Qtb/G/CihHzJf5+18Gqt2OJcZl4hM7NT+ZQWbdX/dd2cV/FsQiQzJDKMxvRL4yqKAfasXrPflCEp
qbbYRJn04NeRzpnmRMjkQZUlD5ykKDyHJgLGAeFFGz0sKfBr6X7MLGKIBtWK6at7HCSHZguZwgq0
geRbuLvmfy4yO6+l823vBJtMN3mgr/FDU9eL/VlsgZDqgnnZa4Jig23FcnsHo+Z7THtUe+jWLPrX
2tPsZSpU8BjOKVpAd6BHAIwUoQ1jNq90pZNiocLLI3tI+JoNvNsKRl+TxJsE5w2Oyjo6s8gRBFYw
34Xn4a8BNHKV1UNP8LtkFDKLrdwInhh2K//jGnTGbqkZUhUCsu3ttH2wYkhsRaQeHcucolEcK2pz
3/cV/+mACuGBInFl43mJFJ8Hn4vjBvG+Eyq0LMSQgj3NpCL0Hg0AnOu/lA0JSsRUuH37zFFpAcG0
pbPivA6S66gi0GcDfWyjzpgPA1yi0w7PSUFBnRk2TYqdq7k0D/onq1+ZTr2ojadexK0bz5da1x7N
113ANafQHFRPmbK1hj1K+DpKEv5G0ry+RNu+q4P+/aDaMoTueAUJ6t1flBbE2dbQbKImV8W4YXtq
1oZMYIGpI7xhTN9SkO+cY07FabDKhlCux9P/XzgOqxeixRsOqduzFW+EDkwi8qM6z7lnsWJMJHCR
snXrXUS0Kpr56gtOLQdXHEfEzbf6H4MaxMTWJOBv2qv2/1iPoVbkEfaDxxxKd0JWcUIOKaRZwZfg
nX0JZwHWhb9FdkwhXN+vQgsakBOmSGdX+aMHqRneJ6/UllOX6UWC8qpskjvlcUwgeEw9Fq0/OYsZ
pPPs096WJ4H/+Rk9E5zjiVDWR/T9i8o0J3TOxAfIRbyp+Qmxp+C/iWXeb3V2rBzvm5j+Lcj4cAhz
7eWkf1YV+VWoWt2EFpiGEiI2j2nnx0kJINjKEgbeJ82GUsxN0nh4DBvnHz7JxD/iWS/bhE/V3CoK
xIHIrvpHH89GKGvPKAdMrrvoJwKeHP0H/ltcvH7U7uXqHQj/VKuJbcmRihfk5hSsXO4zwyPOy2TZ
KmCarfs5kgw0we/5d0/VoktbXEM0Mwv9U2FsfD3G5kY+CC8zyyZ9S2PXVbP40Vy81P4UaQwSM82o
ChYcIADc4CjoUMTFUFl4YiV6cnX8mW5KK8q9u+DiO0Ej2XKvejDACcgPA78HN2B5DqGIbUAxDzT2
7Ny8FiVm5AYTyk3D9wSMiDlIiwmL0afBu4z/Fr9Y/MAZ0/xXXgEa1Txex7PyKm8qL3BZrGYaL4BH
UQokBjFK5EMcC2pOyigYGfHXEj9HjPp7h3NBjdudxxo4N+9KZvFsIfbio4NDqSo30gi4vhmKtAZZ
3JRutvK8j27u0llSqnXziZACPaLOQHuVZcLBNUlUQHc1VjaWh98AA2rTfBWRYaN/jOEWc5C4woXL
XZPWa6znWduMSy2ErkUbilVbC3l67k4i4Rl/hASj8QzX8+EWYYPYCytG+YKB0Go/YEsb6e8GQ+XQ
b1f9PTIRgeInjY5JGsP7qlf6u/aHcTr1RpynE00pgvBmw9ExKJuifvDPTF4It9l6Q+iBswpWx4JY
Tgo6N2v38mk6aoEFMpX3HjECjtXAwkrFbPOsM2uf+4pvUZe5y19F8eORf+cuzXQkrDX8HgJFYPM+
ZSvbH1j8qUUKE4NdX7idR/ky/zaURpUz9uaYBh2/hcNJjb2guIsuvYquBJcRwRddakeijpqkhxM5
Fsh/F6v5pGB6U0h8UBo9YHzbx3OV1/8IYku3Z/C2vtGneBxxcq1hUuUWxjFOScx60C6Rp4scrN+s
4fy1Dml2BEihuucYXiwqNJvtl3megMgfLNIUgkKNc45StqlzQRBTY2sQEKZRdDYMVBRX/KZkBL+z
7U96kLI/veZVgmkrqVi73fpYPYewKu+G/4Uxj/4N/hvR7LIyrNfoooe5fDEHMIf68ssjfSPh6qZF
pIr3Uks5WnBLcTrQuI1xrpN4pRMohixkUd6d8Ii8zZBYDVTv/qnGKMZcp81RJV1vwxLiw32C5Z4j
eCX9FV/TKxKpVCeHbhaYZ9reb2CXrUNQVLeaJgGPIj3TDKPVE86rKOlug5UHCvmKlMBMa+Z0taO0
flRMkxq3PGdrF8oc28GwE3aHmnwpm3FXt/nX9kPwmfKNjo64X+ihz8OwvlB5vOUKvV/GChh5ue/l
0Sm0hpJG6Z9IEnlHt6YWor7GyHxt+ppn/LtUdx7MZN5QP3O2pQlIgvBfg3PXLGS2IDbqAwDJjwW/
l+b4iqni5I6YV+RmtNNN4bAGc3bKsF156Al+raMKNe9BaFqvygbN3yvsr9F7yUlNqpIxtxeAqWw1
vbbsd6FiyX8cqwLUQwwco4BIUX5MLbWJ1EuA/AWwP12v+RNG4VneVV+5CVOHczAbRIowr3eop5ph
VbGcbSGaWivo9yMewX5ez8xKytqz/VOvhCZX5tJbSag9R3dCDKKoOUXmqLov5o+bmlaz7spjwrjz
HN36nNQxJNPsOTuWC0Ee9cKlX/1VJKMNktfWMFCWYTxBFtHXe+XFMPgMDWUVqoreq1JHPZMg4v3L
eYZlauT2mPRmtZsvTHtFzovp67ZMWB5IC61AHo9Vu7CaioEOuMkQFRD/wZzdQZv2k7THE2av+FZh
dt7EClA3aQZOYreanT6P6BnMRKVLaTUMGleK5JByH/pM8R8RmyMvzFAcweNXqUGc6bCMfFaCYoXz
y8UX0rPg5fMjVweHtYgYFwIDVaHhLQbAWTGz+eHLcPRoTEPjFczZprg7EDKPm0SPlGDXEbyQxt67
KXJMgJr9BO54Ey/TQEz3AkkHAH7Tc/BSWeMzLsh+YLwjuM2LaUnDAwR3U73gwHJKan6AGTzwbxMZ
ITMgz4grnS1DfTmx2DdtfyTCJIH1JwbN7PBbCfh6ibUt0zfvzjGsuPNqTnYVKNGSJPvtZKXS9iaU
4bpO45N+x5dvo3B5XUBlk5bY6HXQOe7V0kBix5H91qkJkqV4//QhpBZvvMggGgvLXm7rf5vzUwZC
1L0VtwGHlBFgIpnmetGd9r256/Nh5i9cuZ5U31avZp/KCbKylsQWfaVfoQ+UfKXfR6KGEiYckcwT
tHez+D3gC/pp54NhOeexqbiAtSNTUmNGSLUWmIRpGNDtMyn4h/93ln16OUZcXPFJozTph5BXzAMf
optoizaiG4aaxL7rWtZ+38Ts8fD6Q7lg5vUHk1Po8oPTVJvlzzZTNMIu5a/10mebRcF73q0M2BEt
ZWl1i7OBUqyNr8lsJQH5MB4Fe97Se1IG+OeLkgB3nAVM5qGZUCKo6pxg+PTpBgtIg7WS+KrKJf5q
2pGei0v6sh0XpxqWSgl9jO2Zo5TFh46Eg0LIuzyvgYH35+bDimSlqqm7Mcf50nQn9QL/Q13Bqx1q
5cvLszfMwR4q9EpTO9bhQYwqWWsX0mtcqpKKbtLPKbaA1Rc8iW1lyjHf8LdNJ3Q1he4CPBEVu/6c
L0dPiArA1yLCQFOb6+QZTQWS595pQcQHMn5XUUlnr5AAWuVoX2RWY6OFaiMN0mKi7WZKjiwaYCgF
J4oDdLumJ4Hq2GAd0g/+Ph/I+7alV8W1+jhj94vRQs1Qz4tt+UcemGmmzh6wjiJATcwwMfcUMvwm
25DgsRWH0FVEnUC4LsGXVMesNdFT/ShvUz2ubxkaHAtqzmnZbPribtQVH2YHE3fGH1yl94lJJr5N
F68Q+eKnuqPvVYp6DB3gDUNOtXVFH8Y4L8sfrg4PaNT84lKGruf6sqy+b2q0EJlxIDTlGCkodSTd
Q/55NAP8Gi6sc4reyviPKHGX747M3/8NIdfIr6TjVTAEUhD5VlJqbudAzKJs0kU+h+V+3xrIK76A
WT+7rUZXLjiDcmO1FFLUKYD60OX3FXZAWA6llIbbW/uJlSkr2edekOxUp3U1LjObNM752ulqZvKt
+3nYnAnnc1WWjgXtYt5OIw9LLojNRSC3/V9qvWypUpCGN0tt8vHEYJQWG3GS0iMoZN3hz+N2w2Wm
ICaqGgDhWRTFZM542cyOXPtcXdZ669vHDNZPwmPJ+wj57VCPFtO6k5eVgcpgmnm/AKJhh96CROob
9357XCab1A89Nwy8IvEfmP05Huj5CPJGLVrARh/Sd5vk3O2lsV3TAZmj/rv7JVlJYUT3zx9GTMDO
FcKEbv0jgut97Kx+PBl4kfdot6OLkGAnlldtpIPkFiyvgJ9pYhXzVjL3pjmuzJU5mGtJ69+dyBay
b9xGXGiqn14aML8y52xvGFwy1eVi2WyuRRUCXYlQWRFv2nbS+dk6XiN98oUkAIYfMt08sZRFkDBi
iaxuaAsC48DDTKIVXWHf0LqFmk2jEUO2OtJ+pfBSoRLt6cNGqf6O7gswnoD9sZX2WsHUOn9WM1/2
8bLcouvEcLWMyQdFZ/SoiKUNQWR4ZeHJCwxAa46etr/NCAvUOnm3+/fBw4kAIqhBUOCg/5I/1zs6
6RqNEFUlFuXuL3dq0bXR2NMfcPaBso0fTTO4WviopZLthNlPDgHEBS6MUMvmHdP2QOr8tvBHw+9T
/VFl0WXoESqaOlCFsaqvMw8959u1T/h2ITPeHepe5en2fQo+3XkwaOrsxVdzUyp9IUop7i/VBZrV
ouLKPoyUU6SpprsDUk+gg20ZSjrNjwzjhhUAfAmYEYeSv0yVAVAk6TUGT2nqVYfPVQ27GGmhNcBe
4e0Iblp7CezKbSN6co/nm363jV541vkdtT86sSfFZ8CCTbXSAQKi9lSbzvgNr/9pOnV9SlrUgVVC
eAG7so9XWd2Lv/rTzw02CQmU/XI10isv86wWR1WZPJZRsAttdUBYW4+PbdywvkL5zMR2FR+JjGOg
Tp0RRImqLkIM92YfQZQhANY2s/z9fiTqhvyqsuw2eAHon/gULBBPhvh89MuzUWLanCzjsbqlDYGz
mcbKutg0REowjCjIEA3307VjazomhBobqJ2z5Fk4iR5bgMOiNwYgzZ10vY0pADW7c4EkUVAbX5ln
AxGBSkZMsBYbcSeKshFVQCOoXE1HLZRLDhNEwpeGOOVDSB+R8uGYLB2gLYCzeHEnzgnKDiH0ktOz
J3inCWdXrq66iavf1wZcAv381UBnxiTH2nQNheHH58ys7FI7BUqPDVSs6iSco6FW6HSD2d031qCI
UHdUkc4Do0eCSgr4EreRhDbafkTAuMcuyBCrruMipVQhwxvUioZ/OvzentJX7VM8SKGu4LyKgHlL
3P2Jjgmemh6tekIGFkBcD7eeM1uP0Dt4nawgAfQiiheW9uG4mPlp8+unY2E0qjI+6OsiCOeQv7qN
0kw97DMUYmlSYjGM3ii057gJUALQ4tjPgLXBiesb0H5rCdP2UM7AY72PSA5wlOoMphEd/WYBGC72
9lsvXnLHj82X+gvEGKVIDms9DaAeJVxwGSFrgqinj7GojcPgIwjXsf1jpujiPD2Pom/d3Ulvo9y3
XnwcmzHMXpA7jWLxmBle8BHRE/WW4TPladx9anAd6Onm3/+G4uX+DUbc7mWJiF3f7aZwlfnUo2cA
xQOLF3V9LcGTE66xHLuswnbdqlqG6sxEUhPPtibA3XwNYrrHZ2uxCj9Ul7tQagslt2LOZ7fw8Kmx
5CeChn2z6tOI+XgCaE+gHwxP4DV/y1Ii267wb4CcStmBy8mXu2FWP+He/SKTp0eAlx7Uzl6kRnkZ
MCSAXAAHdF9e+Omtz0PHu9cfyUNweW//HdgfBMJOFDZdaPvZqydWdgqs6NHbraIUxJNXQZSGJze2
jG/CF2ywdwPZ/PiJX/KG/LWHEGpTf6b1RRIBMLHZSMfbxbNVDhCNpfRf1YyoTEQ2B+CpD5Zdfjtg
TQpjGo/JLKDgSb9oxs29Z9mAi5pD3rwjWYbznPPjj/YgZ/hLQ3Dr7m9iyPjSJpZWKSS35A5YKpn9
z/CB9dywx+1IWEDB5qIOXosT78xwB3TeBnjuPiTpa2cC1M5/OWm/h1m4udYqWY9/bcxSC7tCv2tJ
zdzVVb9seJFktv5pMhEj6uFONYKGnDgEJ5TNXpxXAeo7dgvmDzH0rsYhOZc69RKyNdFKPeUyfQzV
+8x2n6+dSJ+RhcaupPRL5YfWpj3PaDmMf5lG0A2g8iLPpU1y27K47aF8Tu1CUEV4qe70Yg6i3kIx
dD5Sm8/QlR8dD8RHczEF4DvBjzZhmsRBo4JpoEN0/R6Fp9ymKh4P6wUryd8C4NWHGvG1HmLUQbqE
oSt/8/POQn0SI+5BNz3AKBzOtGlx2fUpkhyHUrihtBKFKLhAo7LpV0UOnRvzvlHqM4VbaXcpQQdv
DSjuI8WPxuEAkBZI4LcSAiGMLMEYzy/gOTLZszc15uSEn3GpMArsTg5EG2U4sOpJF+LsUqM1my73
977oEnjWXdSJrv66PjMi2fzsZ1566yCuZD1wZWailHfjBsms0DUInfYz5eef/EKJtO8F35OTQrqI
gc7mTGy+Vz/+N6RzS3IeiqJFOvq+/ZNgYpudp84+gb5o39tN3J9LEzAFXv2Hrzjm2pG/RE96ZOfL
zB2Py6n205qfkCNjPMOSig1g0fPHRX1FYllkLPFXrs2fEWT7F7C4Mzkv6GhU0VgDNDG47EhLOfSu
D0+NK4RnNov7OJX4dGuMCITp6g/189S3jHhz9tW3x7QvXK2QtailytkFawQtaQWKjs8PJbxCieFx
0kW2Vx7kXpiBmRr57A5svnGjq91ruaysYE0uzhKX49uyyo6xE79GUw2yOgBdOSICJbtJTQhxrO/h
z7AN/b0bH9qbIA1ys3qL/RalFLnGtb5RMdX0qpKZ9H2T6goXBUg1CvjZVRleAmSqR4RyffE6u09J
Fx5o4pVXlL/mxBFVHTOO3M+a/rvJULFxPWLIMWYM3ZPp6EK86iBmPnAGcT9hniAHLFbZUpf/s8jL
aG05NDL1KHbTwrUTyF594Nzti5PJQ8rNKw12V32xMALSummw7AK2PF9GJe1yIlabhAZ3pr0QU6tC
nVLy2AQgKTL/wMRGTH7iDG3plGyqbTUOwpCQ0hMIFNtaaele3aUdOVxwRBvScvpqVNkEQtyfvfO8
Ud/3uv4mMck3OMKIcfJmdrypvAnIfUgDNYktDVyZ5WFAQZuyAUCF+fgfbk5zVdaK3cQJZLx4uZU8
ekp+PQUhc7wyRTlR0tDDLYm6vctzvUfAl35/cJSvXMbn6n42oaAw46tNw5by2P++GjQ3iKMk5DeR
u31Ezz7G4xVPQc1bVLJsXIokZQr9BmGXvRJloRlQhp83rd+brBB8odALkxFndcvxCmeeVHjrdhrA
MGVvtCtQWL23BNkkVXLSoC5dqm9josOcURJRDjumAbWttzvcxsBlJqr+oXx79sx+cpReZfl1kWAl
eS7ZQtjJSPY3B6Ymo5y1m+BUROui12+qfYV45dUVjEGCK+lpdKqd4MNAyUJfpTF6qAcuxu8pHGgV
yT0zZlhygaTHQcNXK2/mdUHfwwGIYfkYKedtum1ALPFn/MOgsmA2lgeL5DIv8AYc57En4LnWwc3V
4LDF+UF9YiUFxNacriuhT2GOEwn/krqg/TNiTlcUX2qQn296w3ZSPWyFl63AjWOEj8phvZrOUg60
ryMBMik4iXvK1+pKUHHcO0x6GfzHA63UBi5AywN8bIG++qOUuETJD7xJP3H6PDlIPp0Zl7BWsgqZ
82qmpA+GYVdeYhhKXahsNOKuhdTFEqZl1UHdh8QgihhpIq0kpH9w1dPPO623PO97+chNe05v281l
9NFfZwe/XCOZrge9xVA3GQLywR+egGft4Nqeo6q4JdXc85cSu6/KTrphGiBk6Ei5gHW7uSeSrQF6
RsZlTsKgNRWugSXkJyoXI1j4RobGKVmIHNVwGhYx/rtSGp3lnLN+GsOAEGuF4UPqnrgGMKKBwe9x
rUMxpWsXW4IuD4fHZ5DdwQ2OUs1HhPRUKFgTLjrK/1yIV7bu4kG10l9btnV9UA2QvRwhUaEaBlRY
neSaCbb6sCNvoDA0RSS0+9tC2Xkm9bgVb0URb8sRHggNm38LXEnBCN+hzrfz2t/hDjYhRLZHvDX1
6iwzBrtxxApFwDKRK3iLpaAoEXHvjc0XzOPDNMoqhthNiZukm9EkYttqNL9/o97nJJftllHWQ9a0
yp+lAJFMilhjKLX4wQkkz2nXKhg5li6Qjzuz1M/LJdt5pDG1cp4tqV1XzAYYB0Zc3YzEPECM4Chh
K0Cf9Dn1Ekg4DMRE6qCGMCqHzNnS2n1gjJ3fKMrWy2id1q6FsaCc3G/5VJA3LYTuAy6VMP+q1gCP
KLsUuI4ZEkjgy/WSPCrKMEsqqImeIlOiSkAEP+Kec2q2UtujmJ6HuCBA9//lzt16/DrEEBj3yJLA
MI4ZMnI8Pr7Lk1Z2qD6OB4oOGIMHx6H1vhmRlgCQwg+rh9av6prbnxmqQlDVyxw+MtGd7jciLlsf
TR2L6cCgVdy6uHVE0dk0hm7MQQZVjhcAmw5chR9dt0sEKFoIFvupckvCrWnaUI79PmL8smw0kFNn
o4w8i6asBUsTVKt8i0Fpj3pulFHONsmnyksquxJqi4k6eKsSjCCFcacOEp0OZuH5pAzQNpJyCBc4
HitM+89zo255su5ictEkPdpZLU/PEsKgPyz3HyeucR2CfxbHhL4M5rCpm3wb58l+YPWAGCkNT1VN
9ntQPMzPmRm7d2bblXUF47co5QgxKZm3t2zTzNnTND9mb5C8vLeVnJmbjFR/GTY5q2kWi8pfzEHS
whf2ee/5G4OQtBX8Q7VkpBOqE0cbEs0ayJTVIVawzYU50DVrUe5PZtAVFsSER+lALYTVvgu1uECE
9ds7LOgvNrcwmBypIYnGRhPTKExSXEe9CAOyIv3sX9pKN/+0ooXc9zKtHVSbzhwUJd5Z01bWv/LP
YrmtM6OVYq+HQE/aydZxZi+dFa4XwLkFbdHbUVPW/xs7vHhHumeEdjy4wUhNiD1vC1N2s9QGXcvY
BspdDCkqzJvWJ2+exunaKaXEZFa5TXrRe5Eo/yQP1X3CiYrijaotnnTraH44TukGvwL3N3JkojE5
NaKCHF0t3gCg8Ms7N3L79OThEateE1DIWmjR4mxFKlFjazGxb2KnUWjUSrQJ2ovhb8BjMze5Kc5E
JTJ5LavgqW/VLmaGC7SbBzo62u/tjzxKGTUOg56o8tgsyO82xFJi739dXupCLx9zCazDi7clomw1
n8SnRZBQzY5PG7lCf2D25HBUbxCnNtUUIqF65Aeeu/nY6RWMYJ4qDHkENSIxQtthGg0FvgX04OQl
qiDkRAheC8TKKwW9JbBty0evF7lbVD1TDrxWAXZqbDlnKUav1QZtEJxxIYOLk2PLEoKBiehXnTrj
T+CVk0OzVxDqiWlZEC1fhowmbKirRULqrfQLg15nKrcX0mF/LRO58C2YOy8mOGYo/ndiG2qwwfVm
9wObZ4v9JivfnTHys5NXlBUm6FxoMuFGIWyKvTcQEE1zF2ggIGPhdhviAmg4glGA3mOSmEMZKgBZ
X5Gu+4+KMxQieoLUgaVpg2W5MJmIA0hueHAO4UXKjaHu0AhP51RHb21S6QTF45JgZlvH8EiHLy5v
gqZP3aV+1vohS4ogaX/ZQ8z9XrwxLLr0htxg0o2avRRVbbh0bbzgdgm+riUwVvW4V4ZY8LBO62o5
+LNkKitS5iwteijNLPRc3/ZCTNOsye+vO+w5H3RFMKEROvsKMqTTtSt8Ie4wIkv8fjeh2SsLtqBV
Arg89eu16NImzMfOtXMTSr+jIBFRS4/cY/qV4foY3LzxQKZcbDqXgWtFE92A2CCVdS3fR3YQqVvf
GNvTGjX1DwheKKWj5+HR/Hu6zoppl+U09doHqpX1t3X6Q27K8x1Nl5xMyagblQA2Of7wExC9hZlB
50kxmHNCyuvDI3jUbhRGNzS6sbX459TNT5qgZhhzB/RhteO9LUSN9KV/rsQX0TTvkHVeXCXxu4eG
zyLzij/kFxWnTo8fe3JyRaSeOfNkzDu4DV1t1uaqFumFa7lRfB91puDHxxiz2/7f3KPgc2dTfxm5
HfqW3ilKAdK7RGKqlm7+hzhxFVpm0wb6vQZaiJvMoGWT5ACPony93e+J6Zqt9ceJmWmK0kmRp8f/
FWd6wFiON18B3pKvZZv9lwN6ln4HJTiF3A9oWFqsYtJxhr5TuowV6R9ZhUXM1zyjyFM3elBDEyTu
pPngRfsFCNg1UVVtCh+1VTaCS9CDhn9TT2TohHwiLmyuYdiHo9opd4GIlFyg0gP8Zj962U/59B4c
Ku7I0lnXvcd/pCVANJSHKSjZAKXztLYxUPvTcatbTcerWhyD+EjgPSMEGR4jMH1XB8rm9kkd8EbR
mveqX6dxgwKsX7bwkMtjKqHurUWs5AwzwPnJ4e6uzydocXNgmG+H6DfhOlNMhaoKPOzFJ0JtLDuf
/SS+eQbGikoOpxqGh1Og3DU5xW1fjYnIWc8ADknRPz9rz96zChmqQ5LO1F6x1exlYXQZnXBYKgU3
SWaD0WdLZWQgvtrTGKe1H8vmUMXG9cW3dg2Q6sQ6Sd2QvoP1AGefe0qcGEWokeTnQEArSr4ucd5L
qOh2ub7EN0Ii+u4fbcBG2a7eagp/8LmZeeJMfZdW8VhtArL/fahzxkxMF8pvKAKj9s0LC/vWuFbR
HibFqAGCNJiXo1AnOGGB+EiS/qaCq4jhbq2JWskxwBMf2oCwQsfEvXVu/5k2SMcxDoD62getn/gP
RO6Jm0zS64qu23rBE24LIOVzV0n8jn5Su011vOYuCq8PD1OP0Bzjou8NeNWtorXo9acISibGUhG8
1JzQQz3JOt2B/VLVskFD7rpM8Pz3ZCdHjztJ+YzqSEefYG/1syb4RAWrU69weoKwSPDCoPbyQeOL
2hGlsePITOqSRy2b4g7tM2sV8VGRGs0K/qnloBF7SR1XXTogPc/G+x6wv+jzh1SWTbBndd9fmM5T
8UTsWGGaMtNSKSG7aS3uNc6C8V0lESb3j1K29dHZXasLluK1m6XPKA1OCWh7mFunXbu+wC+3U+ow
JL/W73jDP/SkhvukRq4sMZYZoXIQ1QFDF3ZkxZWOANDcHylyiNe2pXp7w6LYcBYVd94BIJvkMk8z
0vXTE4nehXOt/b65dN7TjRMyouGiKco9Dly+IgzFa+d2fjTermLmUTWB/TIfz6EJHRn3z++3Svml
uA4j9oUxqSSNfJkJQSe7+SABk6YsZR+3hOH0v9AmHlszkjj4uLyGJyRmLdrtnD2GZpC0JmdOZw/w
3Q2w6y3uXzVoXhp0ZfXcA3Oepv0HnzNJlRGagR7cktz3ZiS/XDqu0tQ5ttfiG6ea8Mh6bnNj4DOk
+B1hblw2w/gsUvB4Mm3ha4QXxqIwqjfijqGwPI6L8WYgyKRge3rREViGx9ZxFCynftkjziLJ8q5w
sSih1zfMdFRu6h5abKV6jdK0XIEFV26Yrfvt1txwHhzFxYpmiyoZ2op51ya0XPefNJjlbZ0bISjN
IFbcCjFcct09APs2NUCIkZu3KVjB/cltA1IQEdlJuP5NFvwjFypecl4y+aFgE9JOeNawX6iIIAdv
aQ1Zb1zvqX963FOdnzmLluWcwQ4Vm4hhJsCeH6rNgZRDrjZ0sDw7KuuXUeLsuzvAH42r9PaR8suo
rGulPWPqpui9kdaeDg5QeifH8d8h00ROgavRcW6Xw7pvQcZw7bf+8amiLP/+iZWEWbASRjs2C72F
iynCR3hd5it3unQoSkncqDsbWidcXGsP8ak1A5qh8r8yc2JDN3jNOUrX5ZAOsfmSoXQR5KwxCPRG
FhIIyhwl0hRv1NF/WiDc6xM7Sy2y4uAznwHSCu7JSwU2BuwMWEVBWEXntmOxwIYL0Z6XgxkVwmYo
PGmZAa5rg2IFaZE9jAbfH/uUzK4iHxq2i74aVZ3A8ah99Bz7a4POU/HROV+SWOicamLR0y82jpVI
gQyfqFsyBFUy2jw6kq3i5YVojTglRljtDeIRBt8jiAEAvTNcJNHEws9f+PfcGEhPSgXtIkeHbQhk
0wTwkNX0OoLachV1uPWz2MrK30ggZEbUGU1TcXtYmUZh+vYxQkNQITwujImaw98Qy/SSljFtxUv7
hoxobo8lvdrSh3XqiKvlilS0vI8jY84Z8TfOHwFmKitVWV9GeZqGaAw2pZ3TYLczGUE76eHTznoL
W+yjgPZYqkeyY99h6gUHE/ZfyrnuSR32qpLEez1gi0TSCrCkQL0v5jPzJfcGJLDx/EMYM7BfFayO
v8q/nwjoaGjwlX1ZFIbF6/MlETNjso9jNQd+einaJxmUWItji2pRsighukLRxxsqgU5P1M/CO37b
Z8+xSlEUH0w1/zZEJM8HTytWv8gUoqghkMK9s/cDErAAPXix8xunwr5ssxpPdYet4f43S85ClQID
8QjPnWCg3wJSbdQ7bfbeu1Nu7w0F/LYi1oArHud1DyTnT54UppWxwdn5ix+nhXYPOlO+XACrzA9Y
UNmmI+3QPXySg7TSfGSSHoTzwEKgGQhyVW671MOvy/QVphoCxGh0oTyvCZTFgsXvlfcqWLU8EsOQ
LFjHK02gyAvRlGzQ/enCb931cKT5c9ehZ3i0ZY3w4O1FyOM5InaVhawERDcLexr6EuymBeI7jkxR
gKix/vR5+/JGAcgisREv7FXI2/2C3tX6XYIq/cfgRwuK8lenAGxNIzqe7gNNhu3R398hFOmVcjDs
IIc5ZEEBSKVW5De3ajYn5WB9nVkIbctOt3H4GpSuejkhF5mUEk4OhXifRXIvAMeZn3+UnvXZtamu
L85uJ/ePsdXM154LIi5M+5UhioSKHULAyqikjbvqefy5dIUDQ6ts6fTi+muk4BiKb6wX/8Syv+NY
CBvPY9Stcu+vAUqKnOB8B7aj7ElMnxVhFTsYAOdVeM2ecB0bOJJMpvOW/shTmowhvaHFnGFHLucp
ZOjhIegbjgCoHqj+ev47xWxUWTEo4tqah/pw9bA4zFRQ4gOgntM9JB9hswKGmmx2G16vUREImTJO
IePPTxv+Z1qZunZ3XN0ofcL/1PbfZRygFHL1scjK5lZZPDwxi/m7z78zTNlQDfBWUR6im3ImO+5G
UFfdMKeHrZ7mEXao1fPwztSKsFC0YKcoaWIcMNRepo6NBHEB2kIk5uV2/GRBHZaY9E5UYlDVxKWN
x3CwFasds+UWN1TFOdRFSXOtG7/h9G3iIicp9A4rO0gTxnJ7ATfDNtf5HdFNuC1NOO0OZ8zzlLjJ
N01TSSY0ojTYAMi9gUCboxE7ddeI2HVVlpuAOgXKRUVygmgNv2Yx6ZKXA9NLNIb6Xie7oBRWMn5x
AFFx93/kj8RNEeL+h+mRdgKZG6jgtTZnLENx7/JOISDtCXuXD51rZmegkTdwYDJEU/lv3YYqG/5Q
EPZwvleAPaKJoLapJvo56Z1TvDvM0fgJEoAfHmAFWFflmYNcKD/3VtQ3MFHvG4qWBAieHBpDwFwj
7sSIauOAr7Kl+/Ij/l9FPrA80DKNJ34iR6+pZGOLkVSfXqPEyXO0EMUD7xs7k5VQ3gsXjPMvyPpi
uL1X++ajLth4HqoYjwPWNwjqQ+DvM1ppc8ewvNxkoKOQ1uedrLdcX9MIzSLc1R00MkduuO/0Wfy9
7BORiB4YRTJ8LxnTCZs44EJDd+oVMmT0JHBnSaOJVEXDOFQ8nR9scQXKsXqPKAh+c+uKXL7sc28a
Bl8MsV5ei8VpoxzeTw2VQjDJKgVScWhwWvLMb6p9+Y9bRFCsy3NVoYekwnfcMCOA0201IgSx603p
qx1XEO2rMRRm8Xtlc8kOU1AAepJTdM95zGj61DgFok7utleRgCBFVp6nEYjHTuODPpGUqQ009mZ5
dL/eVvnx51j8TAkI4q0F8NMv5EIKX1yLOZXAvkvSzcQLmoGhUCDcQOQ8sFXTqfN2Tnh+jzoFGlU5
Ld6MbNhamPD/Jf/RID2rlx7BDfLUmNjv5dGN4phcxVpkRi9odpMk7Qp/o5T4SPeT8C1rIbCEWucv
qPAgcLu5I9jdcrJb2cQJu8CkweeCuQchMfzuMU4hBfC0TZosHGVIELRs5SwZlLvsm/nfib+17SAr
1u45MHjpLauUwaAzfoyMKQNq4djvBuXdynwY9JSAZ7ub5NGe0N/n69Yl83YdMC0E+lrll3JysrFF
YHY9AnLWTPPn5urowyW53lWW9yHVP9jaxffYSJ+D9Apwc0lX9iRXwQEBBN97whm1a1wsBiv8DNBG
3Amo56k8ePLZO2f5rc9/FctIXNTTfJtGJ5ajnu3+jRoKgckgqniB74OyGX9GRCOUhsbhZ2jz970z
TvdVKtOzl6DS8U9g86Rcua2RKnTnfzuFTB4TF975qvulQPSKxjNMvhqEAEYV8R00tIhy6P7vryHl
kuoY+MRh0xFg4CKySyHBmMiWzmkkcdN9bJ5v//6c815x+X9t0WjV1kRoXLOEufvq5ik6TL5Ct3rQ
xD0FIrXNTv4RBzD8W2oQeqWk1pEIv5pzF1ApO4NXcKFxWvJ8FU+RCDr3b5G9P5Oq+IaUaMgmXFto
+MbSS1IvF6/8newfdtje3pg74qsLUR7t4ZFM0mAzXLFaMgvd+gb9Y26ypQfOumQY0QQTy1ow60a/
KUUI8g9bdlAwHc1bReSjLoHz66oppiv4kAj9NBu+pM4aedFT8j0wK8gTO4v88QcT8gswbWNDQFqH
WY+Ae4xzlcwu9horXNF+WNWXlITTqBrL47rW0qJUY9E4AtiUVjL6g4hsCQWXnNk70nVZc8X9gaAh
1npKxdd+wXuODGjbZK9scdcP1BHZ5Uj+AN9pzs6caIsuUCvTEEcIqWB1IeqDIAnnL+rZQ7k0F4bC
s1MzsfZtoZCHyCgIv0dj66j7dIifY6o9LmsvPI1/SB4wzICs4lA9S3Es6Sozv/i3hk6neIgB0YYo
8dECd2P4BoF7xpvH82xv0yUOkJ52BdoOX1GXweZ7fXe3xWsqJNMfYzzvzo3VlFBp9Wny8kX+2jUv
l169teLBGLRlaBtUr8jTsiALptIdVxcWZGnbNGjCnA7dgHOnOU7CmncKxs1uKY96TWasE6TfAAL/
L/KKWm55U+tjXlmJ4Wzlrrz9MYp+DgrwSoT4n0gXC0X+VEyWuzofN5+ChogRLXUuLxZndu0DamC8
nSqjn/Go5ZXbk6pzu3kXQTnurbfFA0V5AXJgtL1oBzvEo7/3ZMjS8RPqyi2d+ZM6YTV93SsoQXaC
vatq4UMponmTfdLG3Ip7iFXFVirckWaXgQ8PONUM0+cJiVTEqBJ3t2vDiVZiBpIlpQ4eJWHoahQz
wAPzWQnNQl8U3VQgYXhFX+EEnnse2U2tM1RNUT4OPzdLlxaRLZ/WXGjLykUNgPtSuUFwHm2wrhsq
wR+9Y6JuQya58L4HSPqxhP71LLI7V+dG6PeK59ommkDkT9mI9HOxGKRimNNVHo5fMmP9Qm+7Y52X
aQQLhqCYT8dlL0Ao3+6JzBgfa4tFzhnuUbBwp2QC/J/QPPN60YpVQPN13oomc0immql5Jl9AN3Up
V9uDZtnaBAlHwxXp673QGRoAQ3kxklW6umI3V527XL7592ePBSAgOUQMJrvu8QmfCP0B+RS8tkei
ZLqJXeLJnVjv84ox7CGDJgl+dRYUl3+P5kher+9lOdSuabBjVkplcfg+26lLRGroPakvCcLWh94u
CK617/4qV7/6dJKYM3z7Tavl0RvhLGC5UqHgrUvf0kwW+NdBc2N8KlhCKQOgFHhzUQSaRBxryP5c
JGtiHeTYVA9m+OQ5CcdVGCio7KokuE8qqTZetqLO9MBrhvV6cUsK2qSyKlV6Ja2N8VGcilDijHL6
16GGRyoJLwDyLvKO7BfRYBXRzbnCxpye0i+i9Z9f4bDq9nP4YjlM0EzzqWfVM+zmPDo6YNLkx4Gz
SMGfOLC9n5axkdYXnvp6pa/lN1SopV4yjI6ecxzfgFGq32eppq8NbGoJ+e/aAmWNVOcWwYM0c/TU
h6cdOoRk4H429cpMaEM9Fga90ziGjDNMSCeQqXvqFmw/ltGPSZIKegrXYuWjbUiay4ASoGfVSIHz
tcz6aP9wByoS2XTU16OWZpF5tKnI5JvIkdFU12Opy/zJudHokfAAHjA+oC9qFWmPrHYznbgxRcdG
XBGZR6xZ5etgSrx/69pbZX+gKJzzO42jCvjRpsWTt+WkRFx/I/yk47l/0hBaT3g9HcJDZa/LDL6z
7dh4RUoQDrezKnARZGSDW9vqWidCWWy2q6DDwhpeLohVhK0+TXojbX58zas1pT5PH1oyrUySWrMQ
Ygxu4/CmSs29TQuSjhKkwnxQyslNn3YTZbYQd0yfELRFWnDLClr6b7tEKdumtRUG8S8yRqAEhUnN
uTuXwmSAlnAv7d5PvM5g3UAH3/N9RQIskI/fa84FVsrqEivtZkOAJa9W6X5+cwzkin4bW8rdvKdS
3dLWQ08jTc8NKazeNmqMkMkYAc3935OdndlyTva9zu+FRo+iMi6gEr0gPqsA2TtAsxWdqA0Oget9
2d4NpRc01JuBxguEgcrieOEsUUfTcPZ24TsJEx0JddP3eHAQl34p4AvURKfgnSsGONEQ1X9qdryE
j2nHhq+d41SJaYok6y4R3JuFKOfKxzGQ7qxYX1+O7WEdhBlk63RjVZG8AqZ2zdu3Tle9YF8VoGOH
7IHJsatq9vo8iKV8DUH+a10QWRMcA7WoJw75tHDCr3XwNv+g2DsnybjRw971/ciZl6zUsBn2RNCx
Lo3o29cgY5o0+1ris7QGElPg5kzv6kyPhnKoJpwu/4MS4tQDQwL+M4L6UK/w/naJfSRbpM83oYtZ
+TT5szPl6A1OPbbvk31Dt0PDB+9V1lUrPwaKSfY76td2ZMCdoFzGwNnvTiUysQRIsUVSXAgUZJd2
WvL1jibaB6AhtvJCA5iDF1Bd1bZj9cTjyEfo5TLyepHZ6tyKX72j/l/XFMlkwGjlAtaeEc23LpQy
ivLQcTsgkldfec8w1lHv5wpNl6f/eIPLhke4dQ4KbDW6Cv4Bxs6uHo2gNyM65yRp2/nBk70/mXBU
ybGhaysYd0gSI4+CtfQJNqtvy65HRwvXiGLVjnvNq2gp7wUjK1ajbbnio7IAYZO98buWlfNTqh58
SKgSIRHrdE1nIFqBTziIhmqY30dEOXYTes8TOEeJ2N8v0YhX8V6420PDla2gGerO6I8I/OpGgfAw
7BxbfZgvaHG84ESzUafZgYQgJN3eidRSvzI0jwgWa6n1DF9c1USvnQ13PQx493tsftdDt3P5I+lp
3QtFlnAGglvQMW6sNkmY5wVFMArcMudXIrCNCL6tZ6TkNbXnO9FlD/0jyN8rkHLDTveFeIdVw5ru
jZEXHfbF3mtU4ARgli8ivI9i+uMt1jA4Mbkbsqwxpqn402EWoygTOU9HwTbSn+t79u8L44f91+kL
/7OVtwRQHmkyEdGIiVNWmCMSm2Rf7geSQFXWWl8Kmgdpw/3qham4zGdHtEITEIrJdNfV6TUwwTK5
tQzcXIfI8MDpSdyGA+7t1UfIPLuFKojhqgWLtDxLj4y5lYreLYERoC8wKCCbjkNBsCjGD3bkpCn1
dWfqEKDxVSwpfY57H9DXBAIfU4BnWuZ/yT6kfNGPyngdASr32VQUiNBt0fsoQqxW+5gFk2rF0e/y
au0JFDMfi0Cogop6gGY+9Z+l9gbzX+SBhX2XQQgIAAfxxXr56ttpEnn47rZfbyI8TYMCU/upy3Rv
oVgYTE85/X7Cnepl7ytu152DjLyOgKKJbTLnw76Vb/K0ndfgLIwyRmJW5SOcJppeL2lT+C0YnliH
I2cL6mUmicvjX4NJtTweARlb2GB4oI5Q9tVnBMZ9NBPF7TMMURvcgs+eCPEGxaRh6UBv+67EtA+B
wGQiOLY0d1V6HRHAuZ/w1N0Lm1+vzEWptQA9UthZSZCAmNgreGvWrtO8OGTiT15GigZbJvIypj4w
QW8+x9G1d+nB+z8fF4y+izGaQ14lldDmCp6KPx5CKx5vS6GPu6D9UunmhKiA67JIYAdFCGTkhJEw
ks/Uuttt08LKCGZzHb9ZR6yHU3saD5IRFciMORaXDI2IsI8k99SBU10vNaXQmbjYRjRUBVFpgpqE
nmONwhDD+5Mt5E+BvnoWYDC5+of7OkKEPFUj40gEIH2Nq2DVOswrshpkFKGHQtJiaBxTyeVHy/2n
umEQXOr7OoVAmWaToc9pEjZWkOePsJHS5zDkx0dnUraKgg/JgpEN/royMgpZ6Xnia/8wtbpPiV0H
zWKQSq5MX9knZiMH44gAdo7YhcPZ1Z8BVLwvw9YqF8NxDcNFh63C4BB7uYDCihno6iQ0GChcqR4v
bRWArMI6kdPEOTe3PCqecApZzs+LG4Yelli0+NVi0WwiEcj8j+/HZ2+VzUgJCcOGhRhB7JH5Gkgg
7lYn0LPlqPF3uqwwpvSOmDA28oegPDrEGQXtGLwHNVA7DT/38TxPfGYvKyRPRwc2jA1+3U+y6MKs
DCsFhfMbgyjrC1wMZ6Fu328cORdTXmeB3YrFSl/pYQ+tt0r1ZXRecPKCAqRR77L+yK2y+RqSNhmz
cZT+V6m59fP+ukqwkdCqKdf4nP2Te97WqH8d49PKrLNA7ASYokZGxrFNi0cCDEZOj2MEkx01XLrG
uDnInVlpmBreNDvlvHoT2ixK7Te2zN8rddC7InBTLbXSyuDPKrRudRCyZLxASo11teBRXRAn4Ypq
s9TNR9TkbLnXqITy8cbmsNyabpIOp9vDuFanqos19990xfOpX1tlIvT9/5PcIPpEu/KnxMI0KHiu
1eLLJHWdUYW5RAY+hULDbZFrgi1RQ0S3ndxEswB5yOXTBH5XUUCQedYtXYMmX9Wn+0+PV0OxvvYq
C6oonkffPwu+13NIkCQfoR8LYhrrxD1tWMqxPFBWpTDvI4EZpaLzLGr/3H8UPX3f8kfFC7NTL4e4
B8oR8yWXGNfeGZmzinC2/YmzhF5dLKafag6abdnsS5feLGsW0XVggRFca6pIx3pA8oqusPUweGSz
E6tu7eZI3PazvftGRVINEyRn1nrEBeT/zElxHMqxW4uU4NNJHcOM6UCiVd40A3i3S4rO5hRrufMN
co8TzSkAvrF22D3O+eL26bHG/ToL03MablnnmnUtarHfLfJJblBwx63rMQLZsEik9858pcQ5/BWs
wrHc836jhbbbp5uDepiQT5743B/8mbLoRGVb7v0DAS2Onvrk1dwarIxWLo5QL9qJS0bi9Rm8OVYB
SnqJ4YqZcMyNUgvJslXrVh1ABRwyuvDJJ4BgXG4Sb14acXJke8D+JrHJEjtQ/QHSzbti1aAH5a+A
FhhTgSwjcxht4NSuIkiiiFrZy1DzlHdsoawOaA9LDuRkKB+NSBWyWut6oqR/DhmKGUWctu0JJf9q
YsOeVPp2aE5OS0P7cNyxGhCf+QwU5BC0/R6rK03JarIFzcvihGfT+RFZUruf4hZIv2gEDJZtu3xe
OnFchAk6wsn2fn3L5YE4TW00GC574Ju+Wbt1L9v7aNGF5uvezMBWsJ2Nsa/Tm0zu1TAg6cr9x7tK
aNgPK6EMI+UyLM8zYYc0y5Y5dinrGJYxskJY7Uk5HaDkPY8gadqpvPvkmb+N2J4sUsUP5KgeOZEl
USA4ut1ETPhKlZarAbtKvbtHe+bgpCz5mwnIv/DXownPtEhPrnaRnleU5gpJ18/OlWKHR2tf33M6
EWd2hV9EDWpcTdSwWk4Wp0nT0x1GfvKersbpX+QXlHCx6kfpf4gxw2IM+fRF+bqY9v6LTCXtJMOe
VXVK2ts8S6gdJWbTBuqtOelaAGgEB1q5SXc+bRRcjYITgbLTvcmBejAM8fdbK95UaKwjcC74lPuB
40EvwHhxjAnY5M/u3Tgt6bhebtcL4Q/GDptwE3lBA4QEb+ut/JIvP79xZNlDfCUTp+WfOvilhcju
DCnvPQOdjqz6+7WHiFhXkgOlI5LutmTAksfghyCQmclT8FnsVG+/eWZ0QWLioM1qLPX2/Pb3RYeo
sQ/bb1rT5HIw3Ol/S1+diDLMzblMJWTfYhLi77aXDA0zNGxy2AseDRP/+CEwH79LX7GSiV6KFbDh
j0sekYEtSlgVH5pVW9r228phMejTVCKJk1oycCR/8u6rwTkLaXUwP46xNkDgUZI/fGTTKckKWyt7
q77uPtoVeEeaCUgmsBdBA1PiVZWEt/vRrgk6vCSqpBbwW4GQebhAcvtdigrinRG3HnaYtBm6Z6hM
3k/vsp1Vhzoay20C4VUebb9IvPE6WCEN3u4/G9cY89SvAWZANveLFqC8YM/s10Bi+oE2D49cFNFp
a5fSCX9X7JoOC+7MP5U1T2jzNddX0byU3k57KU/NVWa+qtYZRFvk2ms7jbc5mHxoRdfXoeBk0lA1
xGb164lBfmwq2SYAaLtV9NI1abhmvCnK31odFke+IFOYvKXfJ4IwvXoilHPCu54qNmx4DcRng+IV
WvasVgeyrlsizE2vaDTtF2wgQx7lJGLSr7oq3vf9MCrbnPwH+BnBrLWkk94i1T/W8LGkcnl8l34S
VLEgKXWnX7VaCq19+vOzbovltOnfAD0CXby3/7kbfQRSO2VAPzFzEueA9oherma5BErtXXXxC5pS
X+utEYJ5dWO5x8FtYucSASSzhQCYIZt8WmseY85dOTjCwS+UI7sWdxvGc9SP+jEJubPXoZU7xrWC
6iOAkmAZtBxmbLpFrDhI1HpT5915Tw9YxEsPJUUKCyZh34viQIPJqMxSa3EulHkMRJ4QjzrJDitN
Ikxdh18DJEgSdynr1+zBXzel8I/pwrv1cBmF//FCQgIimgg+NMI//DVreb/+rKNQ144Hpy+WHI0V
IwY95r8SJ8MZbDF6Tmnb3CYjFu0Don8C00qzcgwu3rsZqqdRt6f9o7FzH4YubEoLzuvPLwwUm9Ou
OrrUHeINxzuhTBG7A3Uzs2bUWNa1rAdfVqFgMJhKBhsqYXhtUWSZGeJscA9dEaGx4NjaPyQq0j1u
gDRNK9KgEezWxRRIAvDdNvKRPVqfFMqXMTh6A5JwJsii3hKGWwdORJ+7LaOp5CwwyNTt8TVmBlTp
Yj/5lOEeXfhbxnXly7rH6uMSHVm6vxjfvyF5djzRaid05IcNrX0UDre7RzKdoLr6QXekUFvzz4Ea
54JVhuir11x7aWVmpoKbSRsQk80UFXXTY2w5myDzcaTR5VMgtv9OUCyqAUaX4+tS0uz+E7+EwE4W
N1BWK52QGdUUCnVF+C7FbFYCvHFZGK/kd/DuUzNHVfXAFkRDf/wBbeDCJc9L9ffCSijHaDGzhoXJ
joYwTMutyTBf9x5f8LVo4PyrSIWG7YnCWv08n7kXPnHrQJvn3gSqAcYNKlqdYjkgHD9Em0jlLwLV
xO8FUW69z1Vsb9sSdrJO0iNd1MGRASyRycfAxWNA8le1ZfdrB29bb6gPYNREzmvBKIFJkPpqxH6z
z3lQHRBlXY4WHMMwPb/DJDxLpciPkkX1rBFK/JC69+Wf1gxaBoSV8+VIxqwBLLpu5QEPDJX1J0ja
Ha5kf8IZcW+HMXVTJuRkDK4WRQmRTbFkbW6dfNCxWnmGjW2B5WhzTVF9Dl39p9EyYrdikU1TzaYw
V9ZtUVELJDLFUVvogaPrJnHsdWtlK5bRTvSgXI/3TbbniIsKZw03Y8/vv7/XCLHDacG8dEqVL9so
LGnorgofuSY56JXpA+nUA6b3cYik83kz2k/lqSj4sDdleEo8urF6ivCgBLdoEJhtU6/llUYJZT8b
HWbHxDxEIrjWHbKhFy5OcJYSe5gR3MDkKvi3ZVqhoxHxQH+jS+lSufzaZjHTBA/uMJbmLKSFyIAR
XQoCr1CtCSkeoNdKRWxh6dK0yLCBSHQGTeUFepH6fB9Gjxtk1DLAN0xr1nPfcj81DiWyATr/s/iB
eV5AQFoEtkYeB7mddTBECLlhBpgU3wPlSf2mrHO/r7WHN1WZKtNQJpcR0VKJpzcfxGU4Gd7N+gPM
c5Qt1dN60wMlh0vOQmOqUJWlNGPezAmCfp1nsyPqqfFd/XvZAjeAS+HDcO0iuj2hGyvTK8lUoQ04
f1DQmLxTUngJklcMFmCbSl/PMHT98/WAeFGxJKYfUM6sQqBPOCSX6cS+RD+vacmzlR3PjVUFDfRb
5iKilhvL3YQsb89w8b9p1Sj5rRnxRRAvIAKYVSpm0DnG5S8hCioQuJpxpgozcOxYDDKq1jIpFRWH
KBrEVQnAV6lSR077QUFt58rgtWySOPeGl9G95+gl+0WsUhk7rVF3l65dH1eewb7vy744RhxFh99f
0NuJzJNahTriQPWMo1lNkYOWJ+Y/zq0hKW//gv+DHLuXPVkEaxjJfgU0lFxUqT+QvsFadw4kvB93
edFeT8lBiF25RtQYCYrmsb/V/0hmry4zpr/uzonrzCWhZWgkRvQvTnRxBYDBzbQWbiqKmqoXoif3
qsbynW+1RXgvYKhRbCOT5/3JYWyA1C32xp7KRtdKHXVHfy5rTHS9gvrxj3SIdCr040X87snEx60f
8Fk2zgP/6gfFVdKw+M2h/3AOHsHjdrNTCkwK06GeugA5SBFcgEFqM5US/OMZQvyjEcqhzd2pmFQ4
V0L+gZRcfpCCJaafv9jOQ9w4liI4NI9Gv03zgs3llsKJHEjS0NjjelIxdPGSfQbfy7+tIGN4HWzf
Lv9QJgZMmyNI9AwRr1BktJi7DLWzSMkg5YxkZdgUzB34V4j/sbeiHQecqFm/EjIyTvI4EcTFWyX1
3ggkJRaeJTwkMpbBvcbkD7j879uRoikGfovfcneZLZ/YeVT+hYdKMZbUcEhIFRUVTDtMIwj0MG+G
zgLyZsZA7dYoYej9SrjjrIBqhrfTW3RgPvEUoH93iPsfOrZvtafg7aJEh6/2LZ8cNxA2Vc/a5uTO
WbQ8C5e2GFP0MdxxlrnlLyaJfjF9Mq/hT+ttcq1TWpmv+IakePqk30w90PaHsedTKcxSYIz4yMZz
8CH2oVitfFargwB2n05NC0LNMiQayXAur91iFla8NtBmtb0MsCoSIkIEjWtt2re5aGWAPFegpjjJ
C43GylgEEY/DRrCLOarHmGK1SsunknfOqj3vS/eydHa9NNxAzxE7AEJom1jZlWSXoQPL/ixzGKRQ
T8tWyIxHm3FifUKbqhtDXEyCfmeyecYPqAEfbE/c25NsC41MLUN5lxZzCH7p9rvJtoxaDQsJjbtJ
QTZ765pyIgTYETFeisgeLG8a4fv8N9w0YB4xJYgiFpEhDLyWZLhGhggzu3Y2ZY3yp6WnRp+A4UjF
oiFoegFBPqaM0hk5WNoYHI8G33MtT42O+5Z5pRkHqF/11WFjS9+2KG0F30h47sDIWStZPZhQansE
u6M01TwbAduSIjmVfFIuUPLw1QsfVF6/NR77eW0yRzGqhQxE7B5QbuDXRyeBHMAmbklYwF9ohq01
UNNWtKI33UIJxJPFI3F0AQXL0DWqrAIHuxYukGuBSgoVqN3dhEha3YiDBiK1r8hy61AsXiZG/lVg
PRa46SER9d7d2gj6cvVnJHp+69YckZrhKa0vZDdgjnlJFyPTRtJohuVi49w3Ul6r2c04oe3UVvdn
esbnUh4h79Y+h1cPhZHMOLGUrjf7xfzChlfkoAQcfJR5AVIsNJGVUvvkkwektv2e/0WfyJo5XFCo
aYvQMzBJ2OfZvwHuglT194uJKHb2DTVEHvGtEJgiH4dtgWtyX+c2apdFm8ypBoj3Y6FtKKN2rgDr
1OA7rJrQ4btkOnnwJ00anUoSE8JB9WB3mPYszxAR9JCM119tj/LTgfad7X8GeDMkXh4MqJE+Uqkl
bxUicwOwopOriajaUl6qBoDbqgjGS1IytXsfikF/GZJNAGkaM1uyxYDC9WPBGgiEQMSSxLkBYAeg
7M08wApWNsRQRA7c3+8o4HaXGHT4WE9VNkrRhXFOdNxHxbKK9wYyrudtmu+h+27fumb5URNVyk4q
LSlREJD3onfqfG7GAtNThFjqXY7p0J4KUZOBoKu+0prvFOubSPVZTI/FvNTPs4HHPdRxrBGFowZm
Rbip+RrTVSKcxzDD+RrWhd8MYIEvcVdqZtJ22mWLW+CV0M/J1DS5WTZzA1FBJ0gHoJUnqe4U42H6
TEAL/YQ+vL32WnKD79NS9VKq9mu2/93/DvYjcyG+Xc6INymXEiH1vcVCgJiwhWAsvRkHmiuErSgV
PwgNrzmtOrF9NvCQOReM9mTOeAGgJM+Bv6q3vjA8FmDUrpUv0MyNBnv0o1RXqiVsgJ3gSVt5Xpl1
xoBJhjq/o0X9aof9ZZ5b/uyB5Fauzlwdyddr8TsciVp5lVuQ3iAQVuQ/JU/DtqDGrhcD88G3pIZm
mDOSe3s+4rQJKYzIqTZl4qN7AZckvqAJS27GO7nSAPdCJWrhrZFsFVK53s/fjDs/nLDahlALOb57
/RHEPmc8ZKRL/GpDyLtC4vyYfgY+QS9ar8534RouAQ4wHJomaObwCl2EBNFIuU6ag1rjnwWMcgN+
vcEZqoatfoICvNRL0unXbkVjMtx02T1varXEZQE22EwNG8hau1vKkz4BbN/8+Hui7N+vv0MuaaaH
PApK/yZXuQtNiGLnl543q2ofV/HPmdRKxCEeMT8HgpC7xpkE3RdLf4XEE8AY51sYLF3cW54pZgSz
5CcLZnc/xVJnndF9sdPOXL7FFQSCQEiy1nSFASwqU+RuT7xS/LEIm4snZWVUOJayMHRU4G+79XjT
sGYdejljgj6RzQbX1w58FVvqEkCi61b1aGI3DL9/1RzTMAUW1gv2vgQIfhIlojny2NzrTvO0Nm0S
Aaim0ZtbisxI3GLAeuChZf7HSuZmTxiv/VEJ9xuO4RAgdKFMqalxlJwhh1eOjVUsYZkzhmGW/w+e
q4OpGz9t+SQ/31t4nTC2kAI69hyMctheCRpAO4Sqn3SFDKKObOh5njb/AQmWmRVdHxOJUWBqlTh1
MEjeomYR89ywlb7Q1RPdM/QR8Aahp6pNbEbWMq5kFlosuP+fNePC/d6G/fRd7CWfluqx0azwgjYi
ea/5VHg2KZjA0MDO40hVHYiH2gmORmXX138UBxW4mnHfXfmv7fj97i50yvD1xfZ4wymm76qE3DLf
ine4Y3mdoIvVZBDSaSlbAqho/sAFo4lSwi6lbCymL7eXVjNma13kruzIm+gqnyF1CSbXe6Y0zouP
NSEiFeCenOA6WDeQvBQpYBhYfI8LS3Ekzq4VhP3tesfhLGMiBZ8Z1A14RLO++khIZXt9WQSna1mK
4UgLCxfh/K3hLc/E5WLN7sgA9eUTarwx7mpwntUu1uT0LoB9BqTk01ZXj1MAavap3VxuOaRv2QrQ
OY2tlv5sSNgEezm21uEu0TQlP0Tfl0Z/hR2SXXvxULW9iAWgMTe3lFUKakSRyRmi2tZUqF3w58e9
YGl+O3aBT2R6hGVCkLwoDnAC3EJRIklvjTej3a+ISMJmiYf/sT39csgK9VpkvTPp4YPBk7/32j32
G5DVAYefG3W7Uakg/+yJZSlnW7kYNdQ8TbEpmWnTZx2CSO99S38r3TUet9yx0IdaJHLL3GH0UG54
uw/PaQ57wyAL+IheX/OLDJTuNLBipHowHjIY5q7W6qjxPtpR0hp2yyRjNDOwM9KY7/AXrmrGnoQ2
paSkDQ5jM00XHZSEbfhqaH3W9qbAthU4y2V2HLxesfWtRmJJgCykIWpSuvQ1jvpBVfIEGSUP6Lsb
/ut7yUxmHPxsLQAdQPkpXALVkFjJs61Ec3I4T90Dr2KD+b1SOOHKgrKqb0WSLtAZithliHjkhG5T
/Zv+b3AT1DFJKLYOFMT8hWM4tkfmbHhwbQSqrkxFtjjIdVFOCZrLASSbKTwQojQbCeX5X1q8Athx
PoJ7odCvXKQPURozflL0aHHVHIQAzZ2x5ab8+7IG+jBpx1Ry7vSNTC5sNaCf5XEVbDy0kyp7zenS
HbEinWAF//We24Y99WpuPGtUxFDFpYH920+qkZjqCLMGeXwafRi0q8rZJRvF335W4UXSOCOe1Bva
vAV6wMi4ILTe4J0o3cq0FpUwqi5aMdKXs5lxp4F5KD859wbFZqEZfPemjB6i8Uxxo/2pPm8a4WI7
ezdkerj2xh0n8H5teG9+xZ+LmZoC9KCtMx7PtKEeQqknYUqu3teeWISRBF3Gj8XgsB/s0E7PY6vT
v1lm4D6+1ErQgLIuQG5zPP+Vs8HmAZgGPBjC9LEL+v1qQPfMhsvODmLcNznfzFnRvbso7FGsrNOJ
t4f1z1dJIjaM3zpEdiLHESNolLa5DHR8Xo4oX3lVtlx8VGC2oL4ZB/houcPtGB3BHDKuHfc4H6c0
OExmSqlR7SdNm/KJQl3XrdoM+1FQt/Ngu5IXsmaf66jkR4W1hGwmmkY8UsV8dKETUN/kZZDIOu+e
7UMkdLURN9kUlL8kdmBx3yxGztgKpSEBoMwuQLNv7no0KGjyUC0WNwdNqQRWDoqLgn5xow7Vvsid
0TpM+hTyNQU8ahIia4pL+Z3Ssnxw8OUamBzL8e+IcF618o3RN5+oiz4XN2dXKmyfu+p57sPDnYXF
S3nHmPBobcUyfUXNjuQOWzl3rDb9LG2uovJYillf4ET269mkZYlnrFDutheCPKGLJyMA/+3HK5/1
oPhlT7wUmCSRdOOdgVqzEPE0Tt0hoK+RSEI4DMzV+aVe/JVUzjSNxUp4TRni+jK8g54Iv4f+6+nY
ZFuWznpL8Ku6Ew1Tsu6X3nOdCJEZO3aKrvO+PZ14wEY02yFGRSSm99L4/i3gsWR/jzGeDoKSql40
Mi5io0OIiVGxPSdsYOtVSCKQ8CBuQAhtU5EzyRk6B+TFuoreosRVZeXC8MDP2CP6m7DB670eo/kk
+SMiPqSXWUJfR8Hkgqn3l98h+bKKtWEWnQZ5L3uRXe4qbDwFwaA9aOl6+ZHc8QpiPw2S6+89Iorc
/1LH7kOCXXTWznDCxvzum9d+c8kZKDOMl/ljHr6i3t5AKmORI/uAeTy+++XoVmrPqDrffgD3/0cU
OlxWIqpLfGuW2By37ebll2TOf7qPQiHw7U+WoHvRFmFlodTTSREfmOYmQHGh+vLYwVkHb7+rwJ7u
NS352IZWebtHlIixUvPxCCMudOehhcr0t72ZQRV2RFJMeDo2RBdiwoIr7LDF0H2DTXsIFYwenEPj
uyGBcgnfaTPIYNbtFE65hAQ6HBTixuIS70bGxTZDEDNcnCDcnwti1OjXRgrmaznrpU0TlTVf8JbW
XKLE1csCSqWEqzsSidR2aAVh9dTxDbV4Wypolw+ct1Ty3V47E34Ullpfjow47gFK0iEuVg71+oVK
NsQkmeh9gToJCEzo9s+zUmRfdQ9Z8vI5D7BevK74JiVVtNDa2imxvALe/dR9zD3kea+p7M4MvObF
ZOJIWuO+enGiL5D75/SX/xbVNTyUZjMRz+/fwRyIErdoTMXUtOODVJZRWl3gShYgfjjlxsVA+t8p
QWEODn/CtRNQihHTT5Exw33E/+vt4+HzxLD13txIDuf6+3XLBKKB7uAkgxdXkANEFWqxMgF1Xyt2
D0fSFoLNPwGWB8mczNbOqV2y1I1lf7lP/jqAn/7JSsOIb6hPMW+fnoCPeoI151HeypFvQv3jpB8e
zsJJAVmsDYhyEMs+cZmR5SOvW0QyinGzvYZWL3WrAQaUzkXzAHEvlnOcOVTe2CpZX6RNYlA9y2FQ
/skbCw1m8y299cD+lCBWRecHRQQH7UR21BV3+SYsPOfMCBaMGQZ7AFIiLlsARB9HAa4iR+xwV4cz
9ByUaZma1BwVMnv6BlI5wHSFg87Lv1gPy2IxEooKlhd+as7mS5FBMkZdYKaQEo0TxxNcR5E/QeM8
QeCDnmhuY/oDlczF2EcNXHPCE7jMHeJlFF/DsE+CMifrcjYL0+cLLZKGGE6OP4FIjINtgElT889u
LXBitFHxsQlg+Lbl+YfLd+BUe6lbQzloNvSFjYg7IT8F/lhof5w++JLP1WHAkRFytQFUXsHWZmxq
Ser90j0j10+Zt/uza1rRMkml2fVm4vGYAKMJktph9K4N80pd1KNWsEBsNiS3VF/dTKzyyxtI8Ze4
ceBnI23e1IQFx1e6iSi0C35mcCaHD67kkqZqXOzp2iS/w2NyDg+wsBAmfq8FbJgxsTmNkL4pxJ6D
i/U/xcV6k9ERHMoKyIpZP1BrYD8fBfx4MNQ3FvhUkDUmx7OqWmyVhLqEq+gWkVUiUyEDvdOM4bOg
8jtKV9G+WymcbaMnaYV49rPnup4jmwMjIUFfTuE4OnVfYlUcVvJQpWauvIg+QGaYkkEQNClFT2vv
fd8naeolOMSD1jqudAovxVPWRDAr4ZBv3uqdPmWXkPBaIF7wUBz5f8VF+u8bDpKD0OvDebcnJlWB
b0OK/BAQ6RmBJdCMjE9KiVfGajJeBLrPZJAYz1BAWYinkf8r2nzn8ZhMg7SQEdtq6onM5Xacbp8t
SzTzSvMo9zXxXSLNAHdKcg7vp6Cr3s7q2ARW+oGAsZ4e6HM1/YGQ0sEeRme4FuXT93QbRE/z9vt0
+tQSveANi88tLaKPjGDFKMkoXyujoOWVEzOJYYnl9ZdlKR7jNp0FMHefzSeZ2jEu8bugn4wFfiHw
Z5i2Bfo/6laHokweYztF83ehfZW6MGAVitDpORx3rcOjTbWZ/gxYj28ywW+ZLmqz2UrGYwlCVD5y
SNKigcor3TPeYG6u1Ybhdr2Bv5li73+6ydgAEQKn9tuFCKdqjqgX0Xa5TaM8iW+WdZkraFF5V1hL
rXw4ri3SVSA+eujx+fturLwOFLEuwx73FFcvzSHsFlg0N2EATYNPl/Xz7ht4J0aDJC8Wkq+twe7Q
E109NzN4nFDOEosFwn2woB77WBWLETGBH3b7SS41crUHOnr9S/LNQ83zCOeLyuGDZqdP0GiyUoDG
MAfcfQzG6PBseyuxi75XYBe87U+mHFxaovJjSWaqkaIVU0140eT1sAMQsfPJn4DZ/4t8pMYGN8yC
p/RP6zxqixVDib/rGdpxyokgUrYAs4/C4YikyyC6jJDuZla/TsCXk9iMchymGbzFWXjZ35kQEU2l
ROc/ywlmCSPRGmwHHYALDkSg4DoH7QGhEjvwf9ZQcQfd9L2rg6cNmFr0eaPdzrzw60puNIEaIBVL
dIqoYbikJssvF8jW5qVRy7hwABKC8EoXPBT/4iOpvq/sPLWrxIOWaCPT3LhUZhJsaevPAxMBZGSU
c76wGMfMz5lVEjGd8XbV7EwDLa2xPdd5UzCTax4zUbwSUFjzpiUG2PaBqhTTw12uPq0MjQ1dgYHe
pT6IsLLbc1nv6mwfc5GGx4r36vwKKUHHJJ6fjlXqratfsCjLcC5w5aF61IEK5FuVYG0ytcT3QIsU
0mK1ZKCpCEDHyV6tH0CAGi3m06t4F6q2ymFyyjZcDOguwPhPMBtvzP1wUi56ZcpSCPlre5dMMCXS
yDf2ouiMAJQry42AzVTgw7IANDPUHMeY2VblSHtNnpQkbo7paRKbW7ufohPuZVnaYcBMLtbTE2x3
I/xL/8qX8EMsEDi2pXujROcCLi3CZk3g6lyZRi3oRU0Mj7Puh524j/QTFemff4nQgDNIJD57jNjD
ToZLyytedkd9NAta/GOs++hnVG3ylVHxY5c4XvXs+9gNQ+FCaTkB+J0CoF+DPonB2inKhsmnSSA9
JxfugWdd9mDUFzciz3cHiNGBwwY6BZJ5nmnIfWCZn5SEPWqLYJOZMvUh9/OL6IFvjKqRIknsFGD+
txoHHsm9PnIGpCOylKNQCRxI5dKedFnRPBUIeaz5Wen/xxcN25a6RLBWdbGJ1+sppFvQukUG1nE6
hVfXVNiO4y4Q9h3b8QXURRWmp5T7sKnHop4Pjn9MNdQMSaVlgiDNz9uII2Ty8rVIIvygtUM0vCSg
5zynSbrDas+bfOeuepAKcVSqP2S5ib9yx7XWHcm1yHRfVxqTEe71FpvTsHbGlWvhLwHPFg/osmL3
zGLuYLYlx1nQdelg0GwZphYG2eYhhPu1VjpP+yoOuEeG71wfhBFQRxrDseViMDeBXn48lpXXpUtS
m3us6KdxXbh6thUELQVHF/PyUu+tfNhgOKXJfdUTI69l3kjSzjIHXjnPBXvRGRu5vdynNmbuAyxg
M2TnFbApxhFYe0K55BKk45xbfmeHzKsEWIH7GuXSJgK+ljEuURf7PjRtqGGnegiuq5ckuOQSxHcD
41Fu3zJA8caCi4ZBXhtPy+axxyyWkkRBNevhrQmdiNNhvfOheAl8MqPlFQC+czCDIEUVjvfFzLgG
NZlZ7FNpBUoIJ/AFlPY3QiJvW01iSY8HRPWGqkDNX5Z7mJT0c2FGtVV1/s+B/p0RMZxje9uydi9g
h2ubbWFp9VFKZ1hwUDtJK822ZZsadH/cw8O9uOfM4jmZl9HHXP2vn+H3gcInCuOspsazelOgawFG
3lTCWJ19eXneAmAMEqd1KDijBv+5Cpm+XF2Hqnexurtqxy6C9i56M97BLcgkG3+ZETtdAvH6MoVh
Y+WUmvj/8xHQKrVRnw8HhxkdWIoMClbKtdGhGd6sfh5kj32D1WWir/wLvo5/WtBTRgj/xrFyNmVH
8LWVPJQxnWPnmkIBMDPq6gHnoJ3DEITqYbqNrourZFVzOan4V0k+Rny/p1aby3EChdwv8xkh2vD4
rudTQJXxEeM0pqFZtMF7gN9itQPx6vVZLfEErwmAiSon5AZgMffhsgoV3IVDA7gWHxT6FEV4jSvB
jtw/cJqNSW8J32TCC5+VSIOcFgLN8hkIUpuGYvqEVQE4GY7lQY7cs6NDCvEgQgyzYX3k5ibykm7D
841NUl/KduHAgtnkr0E0kYt4olAADqzZZ9vfOeom5lHisJiprjy5TA6QNX3X3cHKqFXVjXxQLNjm
Cc28IHix+dag5M9IN3T9EmxlnhPROwIUIOiJSUaomvX0h6DBFiDJ0XkvR14uNJjyIPqQEd11awd+
v6JQmTTBs3IucdXvQhFDoK9kgMv/QMOIztmYKzfx94w/yC7fARrELeqNSxgAqfT6ok2CCD/IIMiZ
lBSx8Lum1CMWeoo2933JKXMwjUNef3R/PUkIxi1zVE42qaiHXdjFoPjyrg5yPEdng+LjD50vw7u/
msoxek1ocaMXC0o6MJWy2WGUbitNU52eO4Ekdb8lATfZsb2Py/8MhAmbgj1MG/xZnUnaKIdvt0pN
RfilXlPZNRP3uisQUw5aVucU6hPCNKN71RrfrIvdOXq37/3A/W3iwzMCJW7xsWjboSkW8MBuFdJG
ZZZQcyCmkrGC/ZLed1v+rLaaKrlA6Wx+lQjnZoB8W33wIEdc5V0lBSUUvKEghN03wBFuffqmRGFo
IZxSDjellhTtW0cQHEsKqVp94CQ51YXJW4IqxFPi+AUi5L/qqlGnlxdvLjImft/ChgxrDLjESdCE
UUrKPsAcbNpH9jmVUvcBjxliHYm2SAjxXvEYJFTdlPEOOa81MsJ/1r1LE95zk/EY9Hcxfrbe05O1
eKD7dlouveOys4pcJfsMYJtR6boUgZ+7hLKvCu3SKBr3PiV8zfSpaKO4vOQ1GHfS0qPs3oy2Oqp0
7bLnODNO9DxhtNX2vTQeyVCMouur9nk37BylIzLzecbHZkdPscfdWQoc8t8WaccyGgYnx15FAHHa
/rR1sQCj+c2HnnSZgcJAcGgfTSsKMSt2hpX5nUSfJCIgefUv+/SJ1jzl0WIDwHaKXVrV0o7AXdFp
dzVoGQ7F9Bp+Z7qLqkK1gixktDdGSkh9h4kSrz6FZ2Q6SvcWb5J4/JBiMt9C2Jog2tJe9rrOhsnD
k5SUYx4NfQFnKP4+E1qvifH63qtgyvNgD9stG0QU3WkJz3/xXtt+IoQx9D4XHepgCWnyEX+y2BzS
324A/1V0MjDgwSW94JQNlT9oDsJwCOhxq8Ufu1oLzwp4gWy8ADVKkFXIsSw6JyPcf9g+f2UgImex
QzLSY6PQrOE+seC5xMQriFmPM/2Ra3uL9sW/ZYSUt3PC8uaOkfe55sYB5QTbFvWfun4qCgUNH2+l
QYN7KPpqjeC5Fu4C8bVMfekF4y8PLXCeOhAGmL6KQq21d1eUUMtNOG0hOURJsvGbV9RdWGd7E/wW
mQUIjST9OB/wTIu/k68XYcAO4Ws4GcjbOdeHTjZw/rCKKdxLa/3GoJeerxZqmJUoPKJzxi5Y2GQN
kkxf+2Qa1F/LLVEDYx1nBV5gDZ7FSnpO03CfrQyFwUokNCyyPs0HUyZmVxlIy/K9jnoyaBkV4sR4
xWCpagbsNqoCRX+uk9S9D433oX/yPzB3SBhaN4Kolk69ybbBKh/P6z1UaaaVHWLcSQHnwRjLwOjb
I1dJkB+zPKS43oRgW6IuBxVsRIWk6PvBJY5i1Hdktqgv78kYaES7241xpuZoFymzZNEbwOy7D0Rn
Hig8NMR6TxFw7mgjjm6JekxBejWzec6k0KAp/mJeNGgu1tQ9t5pnmvfSQ6p3jkonJwDTu59vgkES
AeBVbq9+6BS+JqGAGG/PqFaMubQx0tnf1p75SWexEBJ4m0pm9sDcHk4UGmU3q1ILcQlbS0PQO2nO
Etb37BWUD089KGg//laxSx2iGcyzH7CLdNXX9z+tAdVYBf7aejFLt/+R7h8Riemx3LbH1UhSPxPb
FfNltS7cbVCcSCXhKMp5stXaZ44Qjq78hWo89XXVK9RPW5BM/970XZr8+jdJwfXRCOIF5mhUUEqL
2NQ6+qg0G1Q+U8RiTfN4aHIa3hhQKeNxcXE9w8rH/oHd8WEaid7Yfj8WDAz0CSKYwPtvpVFVOtLZ
lqrSx3n+hxN7ng9BeINQTsMGZWG3PWoTqs/9KU+f+e+nBUSw4lVkWvEGHoF01MP1dHe+updoom68
LAfpeRsxQEWlKgXRgouZu0Cixc8Xx1iDjQTTlqfHEKVjDP+07C4lx3SoAD/cptDO1IEnVuEMGlBX
y0yw8IOTHe+uyJrQHhNmBkJYO3KBhBCh+FVkuicabDsWjxzYQ4pUS2qezNH1N07ei8f0XcIJ6lE7
0uA1S0/3xTUJmupuJqEHLr/AdkC0k3i/vuIRunzW08/S+Abg20FlPG34DSwAZGWBWyJhKB5ZElEO
StR3GC73BZ7Mvr8/x8SkAm9QsLn60KJbeRl1XhteMFGs6mZZA7iq1k9SOc5Kgbb0BLABQ0qVinA5
8+2LtAj4mW7ld7Z7qodJkAD/ocxGh3BTwwj4MmHNNxp2OaCvamsVwkwqspj3pyLNQkkKlY5WRI7e
gAb9F/hr/oSS883JB/5A2DmmN7KPE5p5Dx7H7jr5Yn+Ba2Vv4CecfdQsxdcDTgL1YkDK3wUPr4gb
cPd/+IzHs9NjJunVEkVNoktVCa2z1/jldX5wCvn6geTN33HhOt7i4j12dhF3wvX4NB8WTou6XYsb
RQKlH6d2BGh1OhdNPsL3awodOdmlcuKEhw1An5ld9t1YNDhGcvJVZiTo87+Lr1dmFLI3BXhNdcAx
WENMJo7IyFLQ0HnSvWRl2rREBV+mC/gVfVHfP/iI2JMFDynGLAQ/Q00KIUJbNJHLTdFzOVET5zBa
nWGAVOBW8JOxLdQAx1yyvlreZnUZe3B+FV5ahkwYR1OclYMEuIYULYpnWHPBAnsvC2SzWXFcViLs
LuLyZuO/pqOKsovSUBFjJuCux9I9u29EfwXhLHYE4LQw3AIvu5yZDhvC1+R8wGEBrNzyzj2NHE42
AT0PW5wxBE5e5Rmky6JH7m0/dHNBKVhEnFtE8EFAqzJ4ZW1G2PKb6iSLOvAIhODLPQaMWHA3U6qh
RuITZRPfNA5TxKtALSe7n4SlRMyPmO3IldBKiWMS1DNoaP1SuXmG44otPwwZkK31sOhCDrgjtqYF
L3eOksEQsjOvlmcDz/Gr2++4ASxoIdovmvyE1w/6fEffXbDmWXZymEHB6Hkx2WKqbDOSYQjQxpyD
eIbeWXTLS2pM6p7x3cCCMzvQAvwyDQamgrmWly+VZqpXTvJL2vJayta0m8pg114G5K5LUTAh3cKB
2LdwhYJZhWVY+Kut93I0ZQAHXSXzLB5Y2GbZhvy6Y/MYz40OX+9Nz3k81o9Y/FOpixl5dRyLKhdv
ebSgpNvRjylp3GNVID7y12hUPZv6IbPSFaC62XY5Dc+6NFMgQcgTdPvvlHhBDm/rpFokcjkMUSZ/
u9If3D2NyUU9WFmVB60Ymf61tAi5Ht6bTdwnRnbUxp0H7WEdKsCwhp0IsBeI9jf7PRCrwpvvurCK
zEYm1DGDnxJ+elT+ReXwD3iPs7DRGZxBmMtR8s4a7WKqkfgVwDjlkyc54rzHPcpOKl9kpu4w25aZ
M21KKzLCpKsffstgQ5IXvQ7i2cp8czWkO7S793I1JH9Hh6dv/bMw1tdMGpOTSzKUetK+Vd9ugJf3
dS06z/VlLyze8WHNStSK3QHk0A798j0ZoyCEGcLyXYpYdh/SWvpVUd2NdbXVuqLAb14BNcsAbqLp
2GaU52h5ZDSnT1mEXwXQMcNeuv2fEJ+TyFXUW8BaCBVCJDUhk7b7cwHol7lo2oQQkAyDeSnSUB7M
MD39FOTkEEL+vVF1cLM1mjCphtA4lMhS2qJ3X1zIxyd8OhiDb0+IZyqGRYUwZJlq+pnzUU2QiQY/
VfEoY1R1qCBcVmqHbKJXi4cxZUhdKw8Z7OdJ4XTfYAZupdpfLWrp6iUaelW6h3lCTa0wOY+hgzMx
BRSinTYosaX+1gW69SqQM0uRLGBWDJxiPhOzWjOhNprP+fma+W6kldAwS5UsxhK5ZeJXMAXplK3W
avPhgvo1ccTUC2mgRThtonW6txeX5FrRzf98lkoEi1Xm42C2dYH8GMCw7jm2HCQfc224ArFOZZOW
w4pl6SJ9nf2MM/RhJSdXRobNj/I7k3X0RFys0T2TN6G9IJqFHghffLnNL39XTpau+QMP0hxCIpTU
R80mbbkT26gd76JIhPuqLLcWY1IJTxTAW5Pmrly+FybYog4Bi/CAzfc0Npa3cRUk6RnN/dZbGGS/
L+Dia7kYe3EIArIWlss/M/LHp237+t4pwSH68EvVXcWm7/qlwuCkHMNr6hpnY14kuiU0L0qUp1Qh
f96CDSJEYTeyJd/m6vmQDUOTV5wfR80n+Q09XG38ChBrWUso825vT01uHxZtgZIcBBCaEzvPLMUP
/Ds1uHvghr02stSKs+bcl6U98+zxU3Xch24io3MUop5NsrhPy11AlT4TLhndG+XovuYFFq/uSZ35
nfyUgqhzexksdDlBPkJwrERr4JcUhcxdRlIXf2CNiXU4T9wk5dt1V3MdwNfEVgTPE03R5qa4+yiP
7YBf74wT0fZOYWI78VBDxFSPM9ItNU7I7ukpVYjMHoiGZrkyHSvU9lfWvqoAJTygHIdA2EEasJU0
4f3sz4+IS1L2n14+h+HWTKP/m04oFipvkifzXlqHiQe/gixB7IrTprMfla9S6IhLZdVhKW0s6mpj
H4JIoWOYJAB04QyviFf7YhA6c2Spz1ObNSWYjaCM0tMX+t2pck7NwuLpRv/sprepLfx6sIcn4JZt
gIwX8BoixvROddqY9uzaHy3TyakjPduzzkQIK+3gCXTl29lbpECmDvvv82i88t97sS/KN9h57tcI
LZehw5w/9YfkH/iKVqRNJW/CERm8L0o80AeggH/Fa7nibNZkRTcymUMPve3NY6f2uta7PArFs8sE
Yi7MyI5TgIrcC8hGvXBtu6W4s8jExXnXy/1h6R0UsKnpjFzj0SRi6vYXDCL+1utZSc3oe/k01UGl
O/XRXVgkLDx1N9Dm4n34XAZLQc9OnIb7mDxFDt3l+zUQDcAoUvb0bNdm8XmUz2hEMx1VaDNMrOFU
gKlYUD9B3MWc5vDElWex2MfS9uTAbwYsURkWnVh4RNa3GXufmm4geB8ji6Z9sEC9mvl9SU/Cr6kX
X5IVpge1HnIpbP7OXN1M5w5oGU3yXsioZO8HkXMRulFEFhx/XIZTVgP962XWZYsO0uPuXh+B91xi
nWeWrA4kbXrfkaK1280nJF0VeLUvIb4zjhnBbZg7u0xJuZhSJc+Yv3QwY4LVYLp+7sQ7MvaTGY1K
QTirMx774lEn9e0xncLMiDZ1DPCj2Xio45CeIDsK6+nf84rZGVctY7IIxCEEE6H+YDgw3UuoJ6VJ
xErH54/ViPz/6yGSTh0gsfOQNBsIep2M0I4zwMGtnV/J0av7bTdk7ds2eQqTpfxdl8o6H+WyHb3p
NWexJm9RFauzAF3aJPjufglzPPxdfKrrQ7YTpQ2ThpsNYy+vwHt24Y6IYsA4jeJcCbxFRPCiC2ou
/024Oult9zKjj+2NHOEvAd1LaNJJHKdpEmmPXkyBQD3pJdAc0gUX2lE8YisTHnKka+hcq36CHV04
206MeEWQukElSUTdrTA8evRNp1rknICV8i8QO/clL1zqDSJkwPCTj+wlArygIXDuuLvrNssR8A8K
nPEmLHEuvcSbn613KX7A6zxV+t805yG2AhoVXT1Rr5EUAL7zbz9uNRoxrg3VJ4TVCjaLw6DB7ucX
cG7FrvZyPnw/6rWt93Yh7f06U6acGFuDStMHFv42ZBOiuqd0AoMIjx/vRXoQxb0dDhSLvFZK5ht2
U/MGdZzXWpecGLJ+3zourr1XuASuk85OGzo/plnDrCSJ65NJRog/2q0nV8/YwqE7TTMlgdHiLeC+
Jy6nxXnEz+TEJzNhjcUsDY+F1zfyDtTVOY5NEPqFwo8eo49VEjJlPjox2+4gHEoD+EkdPWIDfYp2
G6jVKgAyQIzvQrrHstpdorMGDka9UgZY+TSVz/zB79JCzwVULj5CxehpNaF4dlAhv+ngfnty3DR9
27vpCsdOHrsdKW4hpuEB58XtdlSrjAUGV8L0unDm+7i6zMH5EWsKDYz0KCG8sQoE/SH2oh8Ixt88
9i03cJF7f01cqitbAfYVh73g2tfmcgcMtne9MvTnyZoo6E4qlgckpR7zWqCDwZnuryiQzaAayIfH
xL6iooL2syWf0dYoouS2nJm/wVYRxNPLtAjSfixNmPl6K84nsOlrmv3UFxTVqwH+soBkPjyunEBO
r9aDSKpTDDCKj+dWg4iCjPYs0WmpgxGrDAA3Yj6TqdCqn+xf5uu8I5GpMMPjZkPruXUcvchYV39k
MKAU+7shyxLwED1Ai4/kq7CVEGBQwVxeO9Hs+hVV5FzK+pmSyOA9YyT31WdTkmjLpOz7Jj9CGZhA
EiHyp3eIOvQmLsk6tlaU8C1ZPOfZDnDHCrpronFTt9TqyOC4Yq6MzuEIYkpX9FcgtuLKELaWfSgB
surnvKb3pi1f2P/3/JsiDCzSttgT+h75o4RJNYLs+Ox7YHSj3fzZ6Z1jzEpGHn9F6n8wn5NLvu8T
CFuP+GIpeXka574QKQeYAU01UGg6/drzdut9LYu5uPqCwWMITKKsjS571UYVJgGiOGa4Qjy7qkGQ
tJAUWqYX3k+vPI1HYn8/r9hm8V5/MqMt3oQL87gAOM9OLYXlVBOorb8bkbMV2UyeT3TxJLqveZBS
K9EK0C3g21vrjLpHU3DERYBIJ1HBbTK9JgUOmCmJS5mOj7DQdFT0vFA08ZEgh7zvw3Nc0mMIIQfj
MN7XNRnCDH6Zp2thWc1SQFA7q/9YqNjVDYo/93ZGF4/FSFnPC0qHqznAqlXctPQKFXDgSNUrx/s1
dqHKTmik6rgwUMaYbleKutK0X3Wa+KbJXOupC7ELaK+NlzCH28gdVhnoiGHgzrdlWPzIGPr0+Wbr
3N3DLrgP3T6nO38ZWDKT8m50pHL0FosWcYWwadaM+S2xS9lm64cB+MI8DVCnS1QhYMaWgv2PdSU+
uv++Dq+wTiGuZ98leyxJjbNIKArB+om0aFZW7OJU9sR/a2/C/WvrgZjEUeWCaev72EMI1KaF0/bw
hy1KLdFgHdlHibMqm4aSlkWzMQSLhPeyMQ/WbLce8kcjhr1W1cJBV8w0UDjDiDQTPIH5gsMEry7X
c/pesBXhHy0aG0em9TJIShdDwtp2fmXsqiSjDlWyQJJT3tj12p/kyCvJkjt7gcOAN3+UO4IV51sT
e8lzvCmI7cwmbPXxDaUDEG3YySqtXXiQblBFFyoFpTpv/VD6D+gLcXlUTl8af4TfavfBYFLe+d+W
wa8+/M2CIfKAKY2B7Nj6LEGwFpf72LY7a3CKae7yfXJIBiBda5GbPtzURz7h9QyqFyAYZzNStXah
W8vhU+Br8bbkXABsfYesyHlDDhl5a2/bfuMS/C8GtGq4MzOOS3+FsKHkzBxLDu5wIDLiIsJ5xShD
qdK9+7r4BpnkwrAOJLrLg09A7E2wU8odMrJP489USChX6fPBDRVmdQDINtqUxx8YaJKGP8L7U6mt
JS8dXX8VG9NBl6C1prixGsSMbTuEQPoFTGy99pPCmLip3BifV/Rv9/ALjPpq94GdBjPcFOfylKva
hOsKHoZL2gKVz4SbdBSoAWyyei7fIki476BF9maDQ6HRETa4NCJzCO8YNXu+JL/7QkdtciwEtWvm
A2sZEhhzRGKh6GTdz5zKHy8voVDTS9W6C3ixtzy6TbKYoh8tvtmOHB2f37CTgEoDlBBPQtSiu4yZ
RFQfnqUGa4hBOJUsXIyO5z+IRVoUoOjfi+k6cHFCqtayZtUN+biyNHrszSQfCftRmmUNOBcI46YI
A5U1lqSaafVbIp8TswaO7nlUbdC2OxQY2nQVNm9PJCaOjbdA00vS9Bxa/Gy22DfrhHOOQlBMe9f4
e96jAF9//bon2UvfacJwqGwrrccgAKPEaRdH5sMgZe5DipVpNschvkwh8M/0vFvDHCVv0lyrqhkb
2wOnOEdbXRz6WUU56kJoKEMW81nC+sIARLoaP7zMKavWwmP+qQdt+agBiXxv4KYaMdZFGFNC+Kc8
1OwOQki9wH82XLc1h/tmvsMKGqxHVozN8D23LRVO0jPl5OQMkAATvwUKtExarSAghJfK8SL9F9NQ
spbVurqb4MVb/A9r/NYJkF0y+7HIukhqUd5JR9UJIokScVvc5LDNGGWcgWvGpXbAAcQqJSeVq6Ft
UlEqfC1rKSsiM99P6it3Wx+2JnzzN2yL+7pQG4rdVEi02gc2KdUf887dGHMviIW0ixKVrWddH3TA
QaEubih3MP5UbAJ4ZsuZDR7y9eT/lhvoAskKEQypU8U1NtV6Aan0d6/W7mPB4G786DuDsbBVGVZ5
dIh63h4d3y6pu+deBf3PG8SOrEZV4fHlPWAQtl9KMcLhwMr8kBGI1SUZu4Z7Sk+8GngVGPIzEL66
VOv/1DnTBw8sVA8lMxY5hy2vEa28x37n3dX+SRJxVLCDC95W3CB3Mhpu
`protect end_protected
|
apache-2.0
|
8cb7eca3d71b53792fd7d55507551768
| 0.95337 | 1.833826 | false | false | false | false |
diecaptain/unscented_kalman_mppt
|
k_ukf_Vrefofkplusone.vhd
| 1 | 1,221 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vrefofkplusone is
port (
clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Yofk : in std_logic_vector(31 downto 0);
Vrefofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vrefofkplusone;
architecture struct of k_ukf_Vrefofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => M,
datab => Yofk,
result => Z);
M2 : k_ukf_add port map
( clock => clock,
dataa => Vactcapofk,
datab => Z,
result => Vrefofkplusone);
end struct;
|
gpl-2.0
|
6c4fbf84b1f4a9ced5857aff22fbbe19
| 0.601966 | 3.114796 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/projects/VC707/testbench_vivado_0.vhd
| 1 | 11,212 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the testbench for simulating the
--! Plasma-SoC.
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.boot_pack.all;
use work.vc707_pack.vc707_default_gpio_width;
entity testbench_vivado_0 is
generic ( gpio_width : integer := vc707_default_gpio_width; input_delay : time := 0 ns );
end testbench_vivado_0;
architecture Behavioral of testbench_vivado_0 is
component axiplasma_wrapper is
generic (
lower_app : string := "jump";
upper_app : string := "main";
upper_ext : boolean := false);
port(
sys_clk_p : in std_logic; -- 200 MHz on the VC707.
sys_clk_n : in std_logic; -- 200 MHz on the VC707.
sys_rst : in std_logic;
gpio_output : out std_logic_vector(vc707_default_gpio_width-1 downto 0);
gpio_input : in std_logic_vector(vc707_default_gpio_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR3_addr : out std_logic_vector(13 downto 0);
DDR3_ba : out std_logic_vector(2 downto 0);
DDR3_cas_n : out std_logic;
DDR3_ck_n : out std_logic_vector(0 downto 0);
DDR3_ck_p : out std_logic_vector(0 downto 0);
DDR3_cke : out std_logic_vector(0 downto 0);
DDR3_cs_n : out std_logic_vector(0 downto 0);
DDR3_dm : out std_logic_vector(7 downto 0);
DDR3_dq : inout std_logic_vector(63 downto 0);
DDR3_dqs_n : inout std_logic_vector(7 downto 0);
DDR3_dqs_p : inout std_logic_vector(7 downto 0);
DDR3_odt : out std_logic_vector(0 downto 0);
DDR3_ras_n : out std_logic;
DDR3_reset_n : out std_logic;
DDR3_we_n : out std_logic);
end component;
constant clock_period : time := 5 ns;
constant uart_period : time := 104167 ns;
constant time_out_threshold : integer := 2**30;
subtype gpio_type is std_logic_vector(gpio_width-1 downto 0);
signal sys_clk_p : std_logic := '1';
signal sys_clk_n : std_logic := '0';
signal sys_rst : std_logic := '1';
signal gpio_output : gpio_type;
signal gpio_input : gpio_type := (others=>'0');
signal uart_tx : std_logic;
signal uart_clock : std_logic := '1';
signal uart_tx_data_avail : std_logic := '0';
signal uart_tx_data_ack : std_logic := '0';
signal uart_tx_started : boolean := false;
signal uart_tx_counter : integer range 0 to 8 := 0;
signal uart_tx_buffer : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_tx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx : std_logic;
signal uart_rx_enable : std_logic := '0';
signal uart_rx_done : std_logic := '0';
signal uart_rx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx_counter : integer range 0 to 9 := 0;
signal boot_checksum : std_logic_vector(7 downto 0) := (others=>'0');
begin
axiplasma_wrapper_inst : axiplasma_wrapper
port map (
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst => sys_rst,
gpio_output => gpio_output,
gpio_input => gpio_input,
uart_tx => uart_tx,
uart_rx => uart_rx,
DDR3_addr => open,
DDR3_ba => open,
DDR3_cas_n => open,
DDR3_ck_n => open,
DDR3_ck_p => open,
DDR3_cke => open,
DDR3_cs_n => open,
DDR3_dm => open,
DDR3_dq => open,
DDR3_dqs_n => open,
DDR3_dqs_p => open,
DDR3_odt => open,
DDR3_ras_n => open,
DDR3_reset_n => open,
DDR3_we_n => open);
sys_clk_p <= not sys_clk_p after clock_period/2;
sys_clk_n <= not sys_clk_n after clock_period/2;
sys_rst <= '0' after 10*clock_period+input_delay;
-- Get uart_tx
uart_clock <= not uart_clock after uart_period/2;
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_tx_started then
uart_tx_counter <= uart_tx_counter+1;
if uart_tx_counter=8 then
uart_tx_data <= uart_tx_buffer;
uart_tx_started <= false;
else
uart_tx_buffer(uart_tx_counter) <= uart_tx;
end if;
elsif uart_tx='0' then
uart_tx_started <= true;
uart_tx_counter <= 0;
end if;
if uart_tx_data_ack='1' then
uart_tx_data_avail <= '0';
elsif uart_tx_started and uart_tx_counter=8 then
uart_tx_data_avail <= '1';
end if;
end if;
end process;
-- Set uart_rx
uart_rx_done <= '1' when uart_rx_counter=9 else '0';
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_rx_enable='1' then
if uart_rx_counter/=9 then
uart_rx_counter <= uart_rx_counter+1;
if uart_rx_counter=0 then
uart_rx <= '0';
elsif uart_rx_counter<= 8 then
uart_rx <= uart_rx_data(uart_rx_counter-1);
end if;
else
uart_rx <= '1';
end if;
else
uart_rx_counter <= 0;
uart_rx <= '1';
end if;
end if;
end process;
process
constant word_width : integer := 32;
subtype byte_type is std_logic_vector(7 downto 0);
subtype word_type is std_logic_vector(word_width-1 downto 0);
constant BOOT_LOADER_START_WORD : word_type := x"f0f0f0f0";
constant BOOT_LOADER_ACK_SUCCESS_BYTE : byte_type := x"01";
constant BOOT_LOADER_ACK_FAILURE_BYTE : byte_type := x"02";
constant BOOT_LOADER_STATUS_MORE : byte_type := x"01";
constant BOOT_LOADER_STATUS_DONE : byte_type := x"02";
constant BOOT_LOADER_CHECKSUM_DIVISOR : integer := 230;
variable word : word_type;
variable byte : byte_type;
variable app_data : ram_type := load_hex;
variable app_ptr : integer := 0;
procedure set_uart_rx( byte : in byte_type ) is
begin
uart_rx_data <= byte;
uart_rx_enable <= '1';
wait until uart_rx_done='1';
wait for uart_period;
uart_rx_enable <= '0';
wait for uart_period;
end;
procedure set_uart_word ( word : in word_type ) is
begin
for each_byte in 0 to word_width/8-1 loop
set_uart_rx(word(7+each_byte*8 downto each_byte*8));
end loop;
end;
procedure get_uart_tx is
begin
wait until uart_tx_data_avail='1';
wait for uart_period;
byte := uart_tx_data;
uart_tx_data_ack <= '1';
wait for uart_period;
uart_tx_data_ack <= '0';
wait for uart_period;
end;
begin
-- wait until sys_rst='1';
-- wait until gpio_output=X"0001";
-- wait for 2 ms;
-- set_uart_word(BOOT_LOADER_START_WORD);
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- while true loop
-- -- instruction
-- word := app_data(app_ptr);
-- set_uart_word(word);
-- -- checksum
-- word := std_logic_vector(unsigned(word) mod BOOT_LOADER_CHECKSUM_DIVISOR);
-- boot_checksum <= word(7 downto 0);
-- set_uart_rx(word(7 downto 0));
-- -- status
-- app_ptr := app_ptr+1;
-- --if app_ptr=ram_size then
-- if app_ptr=13 then
-- set_uart_rx(BOOT_LOADER_STATUS_DONE);
-- exit;
-- else
-- set_uart_rx(BOOT_LOADER_STATUS_MORE);
-- end if;
-- -- ack
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- end loop;
wait;
end process;
-- Run testbench application.
process
-- This procedure should force the simulation to stop if a
-- problem becomes apparent.
procedure assert_procedure( state : boolean; mesg : string ) is
variable breaksimulation : std_logic_vector(0 downto 0);
begin
if not state then
assert False report mesg severity error;
breaksimulation(1) := '1';
end if;
end;
-- The procedure sets a single specified bit of the gpio input interface.
procedure set_gpio_input( gpio_index : integer ) is
variable gpio_input_buff : gpio_type := (others=>'0');
begin
gpio_input_buff(gpio_index) := '1';
gpio_input <= gpio_input_buff;
wait for clock_period;
end;
-- Waits for the corresponding output response. If it takes too long,
-- it is assumed there is an error and the simulation should end as a result.
procedure wait_for_gpio_output is
variable assert_counter : integer := 0;
begin
while gpio_output/=gpio_input loop
assert_procedure( state => assert_counter/=time_out_threshold, mesg => "Timeout occurred." );
assert_counter := assert_counter+1;
wait for clock_period;
end loop;
wait for clock_period;
end;
begin
wait until sys_rst='0';
wait until gpio_output=X"01";
wait for 500 us;
gpio_input <= X"03" after input_delay;
wait for 2 ms;
gpio_input <= X"f3" after input_delay;
wait for 2 ms;
while True loop
gpio_input <= X"f1" after input_delay;
wait for 50 us;
gpio_input <= X"f0" after input_delay;
wait for 50 us;
gpio_input <= X"f5" after input_delay;
wait for 50 us;
gpio_input <= X"ff" after input_delay;
wait for 50 us;
gpio_input <= X"f7" after input_delay;
wait for 50 us;
gpio_input <= X"f0" after input_delay;
wait for 50 us;
end loop;
wait;
end process;
end Behavioral;
|
mit
|
f43519ee67f7b418611a76b481423b99
| 0.508384 | 3.794247 | false | false | false | false |
makestuff/dvr-connectors
|
conv-8to24/vhdl/tb_unit/conv_8to24_tb.vhdl
| 1 | 3,279 |
--
-- Copyright (C) 2012-2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_8to24_tb is
end entity;
architecture behavioural of conv_8to24_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
-- 24-bit interface signals
signal data24 : std_logic_vector(23 downto 0);
signal valid24 : std_logic;
signal ready24 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_8to24
port map(
clk_in => sysClk,
reset_in => '0',
data8_in => data8,
valid8_in => valid8,
ready8_out => ready8,
data24_out => data24,
valid24_out => valid24,
ready24_in => ready24
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data8 <= (others => 'Z');
valid8 <= '0';
ready24 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data8 <= to_4(inLine.all(1)) & to_4(inLine.all(2));
valid8 <= to_1(inLine.all(4));
ready24 <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(data24(23 downto 20)) & from_4(data24(19 downto 16)) & from_4(data24(15 downto 12)) & from_4(data24(11 downto 8)) & from_4(data24(7 downto 4)) & from_4(data24(3 downto 0)));
write(outLine, ' ');
write(outLine, valid24);
write(outLine, ' ');
write(outLine, ready8);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data8 <= (others => 'Z');
valid8 <= '0';
ready24 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
0122bef0209b1059eb7b47ff1a4c5db9
| 0.674901 | 3.15896 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_cpu_axi4_write_cntrl.vhd
| 1 | 15,005 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 17, 2017
--! @brief Contains the entity and architecture of the
--! CPU's Master AXI4-Full Write Memory Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.plasoc_cpu_pack.all;
--! The Write Memory Controller implements a Master AXI4-Full Write
--! interface in order to allow the CPU to perform writes to
--! main memory and other devices external to the CPU. Much optimization
--! of the Write and Read Memory Controllers is needed for future revisions,
--! considering the current revision is implemented in a sequential, blocking
--! manner. Specifically, for the sake simplicity, the AXI4-Full Write Address,
--! Write Data, and Write Response channels are implemented as a state machine,
--! rather than as separate processes that can permit concurrent execution.
--!
--! Information specific to the AXI4-Full
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_cpu_axi4_write_cntrl is
generic(
-- CPU parameters.
cpu_address_width : integer := 16; --! Defines the address width of the CPU. This should normally be equal to the CPU's width.
cpu_data_width : integer := 32; --! Defines the data width of the CPU. This should normally be equal to the CPU's width.
-- Cache parameters.
cache_offset_width : integer := 5; --! Indicates whether the requested address of the CPU is cacheable or noncacheable.
-- AXI4-Full Write parameters.
axi_awuser_width : integer := 0; --! Width of user-define AXI4-Full Address Write signal.
axi_wuser_width : integer := 0; --! Width of user-define AXI4-Full Write Data signal.
axi_buser_width : integer := 0 --! Width of user-define AXI4-Full Write Response signal.
);
port(
-- Global interfaces.
clock : in std_logic; --! Clock. Tested with 50 MHz.
nreset : in std_logic; --! Reset on low.
-- Memory interface.
mem_write_address : in std_logic_vector(cpu_address_width-1 downto 0); --! The requested address sent to the write memory controller.
mem_write_data : in std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! The word written to the write memory controller.
mem_write_strobe : in std_logic_vector(cpu_data_width/8-1 downto 0); --! Each bit that is high enables writing for the corresponding byte in mem_write_data.
mem_write_enable : in std_logic; --! Enables the operation of the write memory controller.
mem_write_valid : in std_logic; --! Indicates the cache has a valid word on mem_write_data.
mem_write_ready : out std_logic; --! Indicates the read memory controller is ready to sample a word from mem_write_data.
-- Cache interface.
cache_cacheable : in std_logic; --! Indicates whether the requested address of the CPU is cacheable or noncacheable.
-- Master AXI4-Full Write interface.
axi_awid : out std_logic_vector(-1 downto 0); --! AXI4-Full Address Write signal.
axi_awaddr : out std_logic_vector(cpu_address_width-1 downto 0) := (others=>'0'); --! AXI4-Full Address Write signal.
axi_awlen : out std_logic_vector(7 downto 0); --! AXI4-Full Address Write signal.
axi_awsize : out std_logic_vector(2 downto 0); --! AXI4-Full Address Write signal.
axi_awburst : out std_logic_vector(1 downto 0); --! AXI4-Full Address Write signal.
axi_awlock : out std_logic; --! AXI4-Full Address Write signal.
axi_awcache : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awprot : out std_logic_vector(2 downto 0); --! AXI4-Full Address Write signal.
axi_awqos : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awregion : out std_logic_vector(3 downto 0); --! AXI4-Full Address Write signal.
axi_awuser : out std_logic_vector(axi_awuser_width-1 downto 0); --! AXI4-Full Address Write signal.
axi_awvalid : out std_logic; --! AXI4-Full Address Write signal.
axi_awready : in std_logic; --! AXI4-Full Address Write signal.
axi_wdata : out std_logic_vector(cpu_data_width-1 downto 0) := (others=>'0'); --! AXI4-Full Write Data signal.
axi_wstrb : out std_logic_vector(cpu_data_width/8-1 downto 0) := (others=>'0'); --! AXI4-Full Write Data signal.
axi_wlast : out std_logic := '0'; --! AXI4-Full Write Data signal.
axi_wuser : out std_logic_vector(axi_wuser_width-1 downto 0); --! AXI4-Full Write Data signal.
axi_wvalid : out std_logic; --! AXI4-Full Write Data signal.
axi_wready : in std_logic; --! AXI4-Full Write Data signal.
axi_bid : in std_logic_vector(-1 downto 0); --! AXI4-Full Write Response signal.
axi_bresp : in std_logic_vector(1 downto 0); --! AXI4-Full Write Response signal.
axi_buser : in std_logic_vector(axi_buser_width-1 downto 0); --! AXI4-Full Write Response signal.
axi_bvalid : in std_logic; --! AXI4-Full Write Response signal.
axi_bready : out std_logic; --! AXI4-Full Write Response signal.
-- Error interface.
error_data : out std_logic_vector(2 downto 0) := (others=>'0') --! Returns value signifying error in the transaction.
);
end plasoc_cpu_axi4_write_cntrl;
architecture Behavioral of plasoc_cpu_axi4_write_cntrl is
subtype error_data_type is std_logic_vector(error_data'high downto error_data'low);
constant cpu_bytes_per_word : integer := cpu_data_width/8;
constant cache_words_per_line : integer := 2**cache_offset_width/cpu_bytes_per_word;
constant axi_burst_len_noncacheable : integer := 0;
constant axi_burst_len_cacheable : integer := cache_words_per_line-1;
type state_type is (state_wait,state_write,state_response,state_error);
signal state : state_type := state_wait;
signal counter : integer range 0 to cache_words_per_line;
signal axi_awlen_buff : std_logic_vector(7 downto 0) := (others=>'0');
signal axi_awvalid_buff : std_logic := '0';
signal axi_wvalid_buff : std_logic := '0';
signal axi_wlast_buff : std_logic := '0';
signal mem_write_ready_buff : std_logic := '0';
signal axi_bready_buff : std_logic := '0';
signal finished : boolean;
constant fifo_index_width : integer := cache_offset_width-clogb2(cpu_data_width/8);
type fifo_type is array(0 to 2**fifo_index_width-1) of std_logic_vector(cpu_data_width-1 downto 0);
type cntrl_fifo_type is array(0 to 2**fifo_index_width-1) of std_logic_vector((cpu_data_width/8+1)-1 downto 0);
signal fifo : fifo_type := (others=>(others=>'0'));
signal cntrl_fifo : cntrl_fifo_type := (others=>(others=>'0'));
signal m_ptr : integer range 0 to 2**fifo_index_width-1 := 0;
signal s_ptr : integer range 0 to 2**fifo_index_width-1 := 0;
begin
axi_awid <= (others=>'0');
axi_awlen <= axi_awlen_buff;
axi_awsize <= std_logic_vector(to_unsigned(clogb2(cpu_bytes_per_word),axi_awsize'length));
axi_awburst <= axi_burst_incr;
axi_awlock <= axi_lock_normal_access;
axi_awcache <= axi_cache_device_nonbufferable;
axi_awprot <= axi_prot_instr & not axi_prot_sec & not axi_prot_priv;
axi_awqos <= (others=>'0');
axi_awregion <= (others=>'0');
axi_awuser <= (others=>'0');
axi_awvalid <= axi_awvalid_buff;
axi_wvalid <= axi_wvalid_buff;
axi_wlast <= axi_wlast_buff;
mem_write_ready <= mem_write_ready_buff;
axi_bready <= axi_bready_buff;
axi_wuser <= (others=>'0');
axi_wdata <= fifo(m_ptr);
axi_wstrb <= cntrl_fifo(m_ptr)(cpu_data_width/8-1 downto 0);
axi_wlast_buff <= cntrl_fifo(m_ptr)(cpu_data_width/8);
process (clock)
variable burst_len : integer range 0 to 2**axi_awlen'length-1;
variable error_data_buff : error_data_type := (others=>'0');
begin
if rising_edge(clock) then
if nreset='0' then
error_data <= (others=>'0');
state <= state_wait;
else
case state is
-- WAIT mode.
when state_wait=>
-- Wait until the memory write interface issues a write memory access.
if mem_write_enable='1' then
-- Set control information.
axi_awaddr <= mem_write_address;
-- The burst length will change according to whether the memory access is cacheable or not.
if cache_cacheable='1' then
burst_len := axi_burst_len_cacheable;
else
burst_len := axi_burst_len_noncacheable;
end if;
axi_awlen_buff <= std_logic_vector(to_unsigned(burst_len,axi_awlen'length));
-- Set counter to keep track the number of words written to the axi write interface.
counter <= 0;
m_ptr <= 0;
s_ptr <= 0;
cntrl_fifo <= (others=>(others=>'0'));
finished <= False;
-- Wait until handshake before writing data.
if axi_awvalid_buff='1' and axi_awready='1' then
axi_awvalid_buff <= '0';
mem_write_ready_buff <= '1';
state <= state_write;
else
axi_awvalid_buff <= '1';
end if;
end if;
-- WRITE mode.
when state_write=>
if mem_write_valid='1' and mem_write_ready_buff='1' then
fifo(s_ptr) <= mem_write_data;
cntrl_fifo(s_ptr)(cpu_data_width/8-1 downto 0) <= mem_write_strobe;
if counter=axi_awlen_buff then
cntrl_fifo(s_ptr)(cpu_data_width/8) <= '1';
else
cntrl_fifo(s_ptr)(cpu_data_width/8) <= '0';
end if;
end if;
if s_ptr/=m_ptr and axi_wvalid_buff='1' and axi_wready='1' then
if m_ptr=2**fifo_index_width-1 then
m_ptr <= 0;
else
m_ptr <= m_ptr+1;
end if;
end if;
if mem_write_valid='1' and mem_write_ready_buff='1' and ((s_ptr+1)mod 2**fifo_index_width)/=m_ptr then
if s_ptr=2**fifo_index_width-1 then
s_ptr <= 0;
else
s_ptr <= s_ptr+1;
end if;
end if;
if mem_write_valid='1' and mem_write_ready_buff='1' and counter/=axi_awlen_buff then
counter <= counter+1;
end if;
if mem_write_valid='1' and mem_write_ready_buff='1' and counter=axi_awlen_buff then
finished <= True;
end if;
if (mem_write_valid='1' and mem_write_ready_buff='1' and counter=axi_awlen_buff) or finished then
mem_write_ready_buff <= '0';
elsif ((s_ptr+1)mod 2**fifo_index_width)/=m_ptr then
mem_write_ready_buff <= '1';
else
mem_write_ready_buff <= '0';
end if;
if axi_wvalid_buff='1' and axi_wready='1' and axi_wlast_buff='1' then
axi_wvalid_buff <= '0';
elsif s_ptr/=m_ptr then
axi_wvalid_buff <= '1';
else
axi_wvalid_buff <= '0';
end if;
if axi_wvalid_buff='1' and axi_wready='1' and axi_wlast_buff='1' then
axi_bready_buff <= '1';
state <= state_response;
end if;
when state_response=>
if axi_bvalid='1' and axi_bready_buff='1' then
axi_bready_buff <= '0';
if axi_bresp/=axi_resp_okay then
state <= state_error;
if axi_bresp=axi_resp_exokay then
error_data(error_axi_read_exokay) <= '1';
elsif axi_bresp=axi_resp_slverr then
error_data(error_axi_read_slverr) <= '1';
elsif axi_bresp=axi_resp_decerr then
error_data(error_axi_read_decerr) <= '1';
end if;
else
state <= state_wait;
end if;
end if;
-- ERROR mode.
when state_error=>
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
9474e8032694c3f164586911ff7793e2
| 0.494302 | 4.49117 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_startup_block.vhd
| 2 | 18,458 |
-------------------------------------------------------------------------------
-- qspi_startup_block.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_startup_block.vhd
-- Version: v3.0
-- Description: This module uses the STARTUP primitive based upon the generic.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- Soft_Reset_op signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
--use unisim.vcomponents.STARTUP_SPARTAN6;
--use unisim.vcomponents.STARTUP_VIRTEX6;
use unisim.vcomponents.STARTUPE2; -- for 7-series FPGA's
use unisim.vcomponents.STARTUPE3; -- for 8 series FPGA's
------------------------------
entity qspi_startup_block is
generic
(
C_SUB_FAMILY : string ;
---------------------
C_USE_STARTUP : integer ;
---------------------
C_SHARED_STARTUP : integer range 0 to 1 := 0;
---------------------
C_SPI_MODE : integer
---------------------
);
port
(
SCK_O : in std_logic; -- input from the spi_mode_0_module
IO1_I_startup : in std_logic; -- input from the top level port list
IO1_Int : out std_logic;
Bus2IP_Clk : in std_logic;
reset2ip_reset : in std_logic;
CFGCLK : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS : out std_logic;-- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ : out std_logic;-- REQ , -- 1-bit output: PROGRAM request to fabric output
DI : out std_logic_vector(3 downto 0);-- output
DO : in std_logic_vector(3 downto 0);-- input
DTS : in std_logic_vector(3 downto 0);
FCSBO : in std_logic;
FCSBTS : in std_logic;
CLK : in std_logic;
GSR : in std_logic;
GTS : in std_logic;
KEYCLEARB : in std_logic;
PACK : in std_logic;
USRCCLKTS : in std_logic;
USRDONEO : in std_logic;
USRDONETS : in std_logic
);
end entity qspi_startup_block;
------------------------------
architecture imp of qspi_startup_block is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- 19-11-2012 added below parameter and signals to fix the CR #679609
constant ADD_PIPELINTE : integer := 8;
signal pipe_signal : std_logic_vector(ADD_PIPELINTE-1 downto 0);
signal PREQ_int : std_logic;
signal PACK_int : std_logic;
-----
begin
-----
PREQ_REG_P:process(Bus2IP_Clk)is -- 19-11-2012
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset = '1')then
pipe_signal(0) <= '0';
elsif(PREQ_int = '1')then
pipe_signal(0) <= '1';
end if;
end if;
end process PREQ_REG_P;
PIPE_PACK_P:process(Bus2IP_Clk)is -- 19-11-2012
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset = '1')then
pipe_signal(ADD_PIPELINTE-1 downto 1) <= (others => '0');
else
pipe_signal(1) <= pipe_signal(0);
pipe_signal(2) <= pipe_signal(1);
pipe_signal(3) <= pipe_signal(2);
pipe_signal(4) <= pipe_signal(3);
pipe_signal(5) <= pipe_signal(4);
pipe_signal(6) <= pipe_signal(5);
pipe_signal(7) <= pipe_signal(6);
-- pipe_signal(8) <= pipe_signal(7);
end if;
end if;
end process PIPE_PACK_P;
PACK_int <= pipe_signal(7); -- 19-11-2012
-- STARTUP_7SERIES_GEN: Logic instantiation of STARTUP primitive in the core.
STARTUP_7SERIES_GEN: if ( -- In 7-series, the start up is allowed in all C_SPI_MODE values.
C_SUB_FAMILY = "virtex7" or
C_SUB_FAMILY = "kintex7" or
(C_SUB_FAMILY = "zynq") or
C_SUB_FAMILY = "artix7"
) and (C_USE_STARTUP = 1 and C_SHARED_STARTUP = 0) generate
-----
begin
-----
ASSERT (
( -- no check for C_SPI_MODE is needed here. On S6 the startup is not supported.
-- (C_SUB_FAMILY = "virtex6") or
(C_SUB_FAMILY = "virtex7") or
(C_SUB_FAMILY = "kintex7") or
(C_SUB_FAMILY = "zynq") or
(C_SUB_FAMILY = "artix7")
)and
(C_USE_STARTUP = 1)
)
REPORT "*** The use of STARTUP primitive is not supported on this targeted device. ***"
SEVERITY error;
-------------------
IO1_Int <= IO1_I_startup;
-------------------
STARTUP2_7SERIES_inst : component STARTUPE2
-----------------------
generic map
(
PROG_USR => "FALSE", -- Activate program event security feature.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map
(
USRCCLKO => SCK_O, -- SRCCLKO , -- 1-bit input: User CCLK input
----------
CFGCLK => CFGCLK, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => CFGMCLK, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => EOS, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => PREQ_int, -- REQ , -- 1-bit output: PROGRAM request to fabric output
----------
CLK => '0', -- LK , -- 1-bit input: User start-up clock input
GSR => '0', -- SR , -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- TS , -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- EYCLEARB , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK_int, -- '1', -- ACK , -- 1-bit input: PROGRAM acknowledge input
USRCCLKTS => '0', -- SRCCLKTS , -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- SRDONEO , -- 1-bit input: User DONE pin output control
USRDONETS => '1' -- SRDONETS -- 1-bit input: User DONE 3-state enable output
);
end generate STARTUP_7SERIES_GEN;
STARTUP_SHARE_7SERIES_GEN: if ( -- In 7-series, the start up is allowed in all C_SPI_MODE values.
C_SUB_FAMILY = "virtex7" or
C_SUB_FAMILY = "kintex7" or
(C_SUB_FAMILY = "zynq") or
C_SUB_FAMILY = "artix7"
) and (C_USE_STARTUP = 1 and C_SHARED_STARTUP = 1) generate
-----
begin
-----
ASSERT (
( -- no check for C_SPI_MODE is needed here. On S6 the startup is not supported.
-- (C_SUB_FAMILY = "virtex6") or
(C_SUB_FAMILY = "virtex7") or
(C_SUB_FAMILY = "kintex7") or
(C_SUB_FAMILY = "zynq") or
(C_SUB_FAMILY = "artix7")
)and
(C_USE_STARTUP = 1)
)
REPORT "*** The use of STARTUP primitive is not supported on this targeted device. ***"
SEVERITY error;
-------------------
IO1_Int <= IO1_I_startup;
-------------------
STARTUP2_7SERIES_inst : component STARTUPE2
-----------------------
generic map
(
PROG_USR => "FALSE", -- Activate program event security feature.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map
(
USRCCLKO => SCK_O, -- SRCCLKO , -- 1-bit input: User CCLK input
----------
CFGCLK => CFGCLK, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => CFGMCLK, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => EOS, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => PREQ_int, -- REQ , -- 1-bit output: PROGRAM request to fabric output
----------
CLK => CLK, -- LK , -- 1-bit input: User start-up clock input
GSR => GSR, -- SR , -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => GTS, -- TS , -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => KEYCLEARB, -- EYCLEARB , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK_int, -- '1', -- ACK , -- 1-bit input: PROGRAM acknowledge input
USRCCLKTS => USRCCLKTS, -- SRCCLKTS , -- 1-bit input: User CCLK 3-state enable input
USRDONEO => USRDONEO, -- SRDONEO , -- 1-bit input: User DONE pin output control
USRDONETS => USRDONETS -- SRDONETS -- 1-bit input: User DONE 3-state enable output
);
end generate STARTUP_SHARE_7SERIES_GEN;
---------------------------------
---STARTUP for 8 series STARTUPE3
---------------------------------
STARTUP_8SERIES_GEN: if ( -- In 8-series, the start up is allowed in all C_SPI_MODE values.
(C_SUB_FAMILY /= "virtex7") and
(C_SUB_FAMILY /= "kintex7") and
(C_SUB_FAMILY /= "zynq") and
(C_SUB_FAMILY /= "artix7")
) and C_USE_STARTUP = 1 generate
-- -----
begin
-- -----
ASSERT (
(
(C_SUB_FAMILY /= "virtex7") and
(C_SUB_FAMILY /= "kintex7") and
(C_SUB_FAMILY /= "zynq") and
(C_SUB_FAMILY /= "artix7")
)and
(C_USE_STARTUP = 1)
)
REPORT "*** The use of STARTUP primitive is not supported on this targeted device. ***"
SEVERITY error;
-------------------
IO1_Int <= IO1_I_startup;
-------------------
STARTUP3_8SERIES_inst : component STARTUPE3
-----------------------
generic map
(
PROG_USR => "FALSE", -- Activate program event security feature.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map
(
USRCCLKO => SCK_O, -- SRCCLKO , -- 1-bit input: User CCLK input
----------
CFGCLK => CFGCLK, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => CFGMCLK, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => EOS, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => PREQ_int, -- REQ , -- 1-bit output: PROGRAM request to fabric output
----------
DO => DO, -- input
DI => DI, -- output
DTS => DTS, -- input
FCSBO => FCSBO, -- input
FCSBTS => FCSBTS, -- input
GSR => GSR, -- SR , -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => GTS, -- TS , -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => KEYCLEARB, -- EYCLEARB , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK_int, -- '1', -- ACK , -- 1-bit input: PROGRAM acknowledge input
USRCCLKTS => USRCCLKTS, -- SRCCLKTS , -- 1-bit input: User CCLK 3-state enable input
USRDONEO => USRDONEO, -- SRDONEO , -- 1-bit input: User DONE pin output control
USRDONETS => USRDONETS -- SRDONETS -- 1-bit input: User DONE 3-state enable output
);
end generate STARTUP_8SERIES_GEN;
PREQ <= PREQ_int;
end architecture imp;
|
bsd-3-clause
|
465935432967362f2b094a2e4c298348
| 0.46343 | 4.652886 | false | false | false | false |
makestuff/dvr-connectors
|
conv-56to8/vhdl/conv_56to8.vhdl
| 1 | 3,657 |
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_56to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 56-bit data coming in
data56_in : in std_logic_vector(55 downto 0);
valid56_in : in std_logic;
ready56_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_56to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3,
S_WRITE4,
S_WRITE5,
S_WRITE6
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(47 downto 0) := (others => '0');
signal wip_next : std_logic_vector(47 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data56_in, valid56_in, ready8_in)
begin
state_next <= state;
valid8_out <= '1';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready56_out <= '0'; -- not ready for data from 56-bit side
data8_out <= wip(47 downto 40);
if ( ready8_in = '1' ) then
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready56_out <= '0'; -- not ready for data from 56-bit side
data8_out <= wip(39 downto 32);
if ( ready8_in = '1' ) then
state_next <= S_WRITE3;
end if;
-- Write byte 3
when S_WRITE3 =>
ready56_out <= '0'; -- not ready for data from 56-bit side
data8_out <= wip(31 downto 24);
if ( ready8_in = '1' ) then
state_next <= S_WRITE4;
end if;
-- Write byte 4
when S_WRITE4 =>
ready56_out <= '0'; -- not ready for data from 56-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
state_next <= S_WRITE5;
end if;
-- Write byte 5
when S_WRITE5 =>
ready56_out <= '0'; -- not ready for data from 56-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
state_next <= S_WRITE6;
end if;
-- Write byte 6 (LSB)
when S_WRITE6 =>
ready56_out <= '0'; -- not ready for data from 56-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready56_out <= ready8_in; -- ready for data from 56-bit side
data8_out <= data56_in(55 downto 48);
valid8_out <= valid56_in;
if ( valid56_in = '1' and ready8_in = '1' ) then
wip_next <= data56_in(47 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
122706b20cd6fb39d945dc441e8494f5
| 0.611704 | 2.906995 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/pass_through_upper.vhd
| 1 | 8,880 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Andrew Wilson
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name: Pass-through filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter passes the video signals from input to output.
--
-- Revision:
-- Revision 1.0
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin Pass-through architecture
architecture Behavioral of Video_Box is
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal USER_LOGIC : std_logic_vector(23 downto 0);
begin
--the user can edit the rgb values here
USER_LOGIC <= RGB_IN_reg;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= USER_LOGIC;
VDE_OUT_reg <= VDE_IN_reg;
HS_OUT_reg <= HS_IN_reg;
VS_OUT_reg <= VS_IN_reg;
end if;
end process;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"111111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"111111000" =>
reg_data_out <= slv_reg0;
when b"111111001" =>
reg_data_out <= slv_reg1;
when b"111111010" =>
reg_data_out <= slv_reg2;
when b"111111011" =>
reg_data_out <= slv_reg3;
when b"111111100" =>
reg_data_out <= slv_reg4;
when b"111111101" =>
reg_data_out <= slv_reg5;
when b"111111110" =>
reg_data_out <= slv_reg6;
when b"111111111" =>
reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End Pass-through architecture
|
bsd-3-clause
|
0678e205a866a5e7479a1d68b94bcc81
| 0.612387 | 2.987887 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_gpio_axi4_write_cntrl.vhd
| 1 | 6,873 |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! GPIO Core's Write Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_gpio_pack.all;
entity plasoc_gpio_axi4_write_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Register interface.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_control_enable_bit_loc : integer := 0;
reg_control_ack_bit_loc : integer := 1;
reg_data_out_offset : std_logic_vector := X"0008"
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Register interface.
reg_control_enable : out std_logic := '0'; --! Control register.
reg_control_ack : out std_logic := '0';
reg_data_out : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0')
);
end plasoc_gpio_axi4_write_cntrl;
architecture Behavioral of plasoc_gpio_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
-- Drive the axi write interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
reg_control_enable <= '0';
reg_control_ack <= '0';
reg_data_out <= (others=>'0');
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Sample address interface on handshake and go start
-- performing the write operation.
if axi_awvalid='1' and axi_awready_buff='1' then
-- Prevent the master from sending any more control information.
axi_awready_buff <= '0';
-- Sample the address sent from the master.
axi_awaddr_buff <= axi_awaddr;
-- Begin to read data to write.
axi_wready_buff <= '1';
state <= state_write;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_awready_buff <= '1';
end if;
-- WRITE mode.
when state_write=>
-- Wait for handshake.
if axi_wvalid='1' and axi_wready_buff='1' then
-- Prevent the master from sending any more data.
axi_wready_buff <= '0';
-- Only sample the specified bytes.
for each_byte in 0 to axi_data_width/8-1 loop
if axi_wstrb(each_byte)='1' then
-- Samples the bits of the control register.
if axi_awaddr_buff=reg_control_offset then
reg_control_enable <= axi_wdata(reg_control_enable_bit_loc);
reg_control_ack <= axi_wdata(reg_control_ack_bit_loc);
-- Sample the data for the data out register.
elsif axi_awaddr_buff=reg_data_out_offset then
reg_data_out(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end if;
end loop;
-- Begin to transmit the response.
state <= state_response;
axi_bvalid_buff <= '1';
end if;
-- RESPONSE mode.
when state_response=>
-- The acknlowedge should only be high for a single cycle.
reg_control_ack <= '0';
-- Wait for handshake.
if axi_bvalid_buff='1' and axi_bready='1' then
-- Starting waiting for more address information on
-- successful handshake.
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
6a70daa17ba0d180d06f6d69cecf1f91
| 0.468936 | 4.753112 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_look_up_logic.vhd
| 2 | 86,606 |
---- qspi_look_up_logic - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_look_up_logic.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.comp_defs.all;
library dist_mem_gen_v8_0_10;
use dist_mem_gen_v8_0_10.all;
-- Library declaration XilinxCoreLib
-- library XilinxCoreLib;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
entity qspi_look_up_logic is
generic(
C_FAMILY : string;
C_SPI_MODE : integer;
C_SELECT_XPM : integer := 0;
C_SPI_MEMORY : integer;
C_NUM_TRANSFER_BITS : integer
);
port(
EXT_SPI_CLK : in std_logic;
Rst_to_spi : in std_logic;
TXFIFO_RST : in std_logic;
--------------------
DTR_FIFO_Data_Exists: in std_logic;
Data_From_TxFIFO : in std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
pr_state_idle : in std_logic;
--------------------
Data_Dir : out std_logic;
Data_Mode_1 : out std_logic;
Data_Mode_0 : out std_logic;
Data_Phase : out std_logic;
--------------------
Quad_Phase : out std_logic;
--------------------
Addr_Mode_1 : out std_logic;
Addr_Mode_0 : out std_logic;
Addr_Bit : out std_logic;
Addr_Phase : out std_logic;
--------------------
CMD_Mode_1 : out std_logic;
CMD_Mode_0 : out std_logic;
CMD_Error : out std_logic;
---------------------
CMD_decoded : out std_logic
);
end entity qspi_look_up_logic;
-----------------------------
architecture imp of qspi_look_up_logic is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
component xpm_memory_sprom
generic (
MEMORY_SIZE : integer := 4096*32;
MEMORY_PRIMITIVE : string := "auto";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
MEMORY_INIT_PARAM : string := "";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
READ_DATA_WIDTH_A : integer := 32;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
addra : in std_logic_vector (ADDR_WIDTH_A-1 downto 0); -- [ADDR_WIDTH_A-1:0]
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector (READ_DATA_WIDTH_A-1 downto 0); -- [READ_DATA_WIDTH_A-1:0]
sbiterra : out std_logic;
dbiterra : out std_logic
);
end component;
-- constant declaration
constant C_LUT_DWIDTH : integer := 8;
constant C_LUT_DEPTH : integer := 256;
-- function declaration
-- type declaration
-- signal declaration
--Dummy_Output_Signals-----
signal Local_rst : std_logic;
signal Dummy_3 : std_logic;
signal Dummy_2 : std_logic;
signal Dummy_1 : std_logic;
signal Dummy_0 : std_logic;
signal CMD_decoded_int : std_logic;
-----
begin
-----
Local_rst <= TXFIFO_RST or Rst_to_spi;
-- LUT for C_SPI_MODE = 1 start --
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_1_MEMORY_0: Dual mode. Mixed memories are supported.
-------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_0 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 0) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
---Dummy OUtput signals---------------
signal spo_1 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_1 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_1 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_0 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LOOK_UP_TABLE_WIDTH*C_LUT_DEPTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_1_memory_0_mixed.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_0 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_1_MIXED_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY,
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_0_mixed.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_1,
dpo => dpo_1,
qdpo => qdpo_1
);
end generate;
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Addr Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1); -- 10 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2); -- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3); -- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4); -- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_0;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_1_MEMORY_1: This is Dual mode. Dedicated Winbond memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_1 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 1) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal spo_2 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_2 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_2 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
signal CMD_decoded_int_d1 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
-- DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
-- DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
-- CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_1 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LUT_DEPTH*C_LOOK_UP_TABLE_WIDTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_1_memory_1_wb.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_1 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_1_WB_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_1_wb.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_2,
dpo => dpo_2,
qdpo => qdpo_2
);
end generate;
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_1;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_1_MEMORY_2: This is Dual mode. Dedicated Numonyx memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_2 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 2) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_3 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_3 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_3 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_2 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LUT_DEPTH*C_LOOK_UP_TABLE_WIDTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_1_memory_2_nm.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_2 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_1_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_2_nm.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_3,
dpo => dpo_3,
qdpo => qdpo_3
);
end generate;
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data_Mode_1 Data_Mode_0 Data_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD_Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 -- 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_2;
-----------------------------------------
QSPI_LOOK_UP_MODE_1_MEMORY_3 : if (C_SPI_MODE = 1 and C_SPI_MEMORY = 3) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_7 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_7 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_7 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_3 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LOOK_UP_TABLE_WIDTH*C_LUT_DEPTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_1_memory_3_sp.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_1_MEMORY_3 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_1_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_1_memory_3_sp.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_7,
dpo => dpo_7,
qdpo => qdpo_7
);
end generate;
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data_Mode_1 Data_Mode_0 Data_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD_Mode_0 CMD_ERROR
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 -- 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9); -- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10); -- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_1_MEMORY_3;
-- LUT for C_SPI_MODE = 1 ends --
-- LUT for C_SPI_MODE = 2 starts --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_2_MEMORY_0: This is Dual mode. Mixed mode memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_0 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 0) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 12;-- quad phase bit is added to support DQ3 = 1 in command phase for NM memories.
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_6 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_6 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_6 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2 and
Pr_state_idle;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3) and
-- Pr_state_idle;
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_0 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LOOK_UP_TABLE_WIDTH*C_LUT_DEPTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_2_memory_0_mixed.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_0 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_2_MIXED_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY,
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_0_mixed.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "000000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_6,
dpo => dpo_6,
qdpo => qdpo_6
);
end generate;
-- look up table arrangement is as below
-- 11 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Quad_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 15
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 14
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 13
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 12
-------------
Quad_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 7
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6);-- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7);-- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8);-- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 11);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_0;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_2_MEMORY_1: This is Dual mode. Dedicated Winbond memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_1 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 1) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 11;
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_4 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_4 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_4 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
--DTR_FIFO_Data_Exists_d4 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2;
CMD_decoded_int <= CMD_decoded_int_d1;
-- DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
-- DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
-- --DTR_FIFO_Data_Exists_d4 <= DTR_FIFO_Data_Exists_d3;
-- CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3);
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_1 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LOOK_UP_TABLE_WIDTH*C_LUT_DEPTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_2_memory_1_wb.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_1 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_2_WB_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY,
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_1_wb.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op , -- qspo -- out std_logic_vector(9 downto 0)
d => "00000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_4,
dpo => dpo_4,
qdpo => qdpo_4
);
end generate;
-- look up table arrangement is as below
-- 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Addr Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 10 -- 14
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 9 13
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 8 12
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 7 11
-------------
Quad_Phase <= '0';
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6); -- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7); -- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8); -- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-- Dummy_Bits <= (Dummy_3 and DTR_FIFO_Data_Exists) &
-- (Dummy_2 and DTR_FIFO_Data_Exists) &
-- (Dummy_1 and DTR_FIFO_Data_Exists) &
-- (Dummy_0 and DTR_FIFO_Data_Exists);
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_1;
-----------------------------------------
-------------------------------------------------------------------------------
-- QSPI_LOOK_UP_MODE_2_MEMORY_2: This is Dual mode. Dedicated Numonyx memories are supported.
--------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_2 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 2) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 12;-- quad phase bit is added to support DQ3 = 1 in command phase for NM memories.
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_5 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_5 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_5 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2 and
Pr_state_idle;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3) and
-- Pr_state_idle;
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_2 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LOOK_UP_TABLE_WIDTH*C_LUT_DEPTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_2_memory_2_nm.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_2 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_2_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_2_nm.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op, -- qspo -- out std_logic_vector(9 downto 0)
d => "000000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_5,
dpo => dpo_5,
qdpo => qdpo_5
);
end generate;
-- look up table arrangement is as below
-- 11 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Quad_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 11 -- 15
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 10 -- 14
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 9 -- 13
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 8 -- 12
-------------
Quad_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 7
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6);-- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7);-- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8);-- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 11);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_2;
-----------------------------------------
QSPI_LOOK_UP_MODE_2_MEMORY_3 : if (C_SPI_MODE = 2 and C_SPI_MEMORY = 3) generate
----------------------------
-- constant declaration
constant C_LOOK_UP_TABLE_WIDTH : integer := 12;-- quad phase bit is added to support DQ3 = 1 in command phase for NM memories.
-- signal declaration
signal Look_up_op : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal CMD_decoded_int_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d1 : std_logic;
signal DTR_FIFO_Data_Exists_d2 : std_logic;
signal DTR_FIFO_Data_Exists_d3 : std_logic;
--signal DTR_FIFO_Data_Exists_d4 : std_logic;
signal spo_8 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal dpo_8 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal qdpo_8 : std_logic_vector(C_LOOK_UP_TABLE_WIDTH-1 downto 0);
signal Store_DTR_FIFO_First_Data : std_logic;
signal Look_up_address : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-----
begin
----- _________
-- __| -- DTR_FIFO_Data_Exists
-- ______
-- _____| -- DTR_FIFO_Data_Exists_d1
-- __
-- __| |______ -- Store_DTR_FIFO_First_Data
TRFIFO_DATA_EXIST_D1_PROCESS: process(EXT_SPI_CLK)is
-----
begin
-----
if (EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi = RESET_ACTIVE) then
DTR_FIFO_Data_Exists_d1 <= '0';
DTR_FIFO_Data_Exists_d2 <= '0';
DTR_FIFO_Data_Exists_d3 <= '0';
CMD_decoded_int_d1 <= '0';
CMD_decoded_int <= '0';
else
DTR_FIFO_Data_Exists_d1 <= DTR_FIFO_Data_Exists and pr_state_idle;
CMD_decoded_int_d1 <= DTR_FIFO_Data_Exists_d1 and
not DTR_FIFO_Data_Exists_d2 and
Pr_state_idle;
CMD_decoded_int <= CMD_decoded_int_d1;
--DTR_FIFO_Data_Exists_d2 <= DTR_FIFO_Data_Exists_d1;
--DTR_FIFO_Data_Exists_d3 <= DTR_FIFO_Data_Exists_d2;
--CMD_decoded_int <= DTR_FIFO_Data_Exists_d2 and
-- not(DTR_FIFO_Data_Exists_d3) and
-- Pr_state_idle;
end if;
end if;
end process TRFIFO_DATA_EXIST_D1_PROCESS;
-----------------------------------------
CMD_decoded <= CMD_decoded_int;
Store_DTR_FIFO_First_Data <= DTR_FIFO_Data_Exists and
not(DTR_FIFO_Data_Exists_d1) and
Pr_state_idle;
-----------------------------------------
TXFIFO_ADDR_BITS_GENERATE: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
-----
begin
-----
TXFIFO_FIRST_ENTRY_REG_I: component FDRE
port map
(
Q => Look_up_address(i) ,--: out
C => EXT_SPI_CLK ,--: in
CE => Store_DTR_FIFO_First_Data ,--: in
R => Local_rst ,--: in
D => Data_From_TxFIFO(i) --: in
);
end generate TXFIFO_ADDR_BITS_GENERATE;
---------------------------------------
xpm_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_3 : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_sprom
generic map (
MEMORY_SIZE => C_LOOK_UP_TABLE_WIDTH*C_LUT_DEPTH,
MEMORY_PRIMITIVE => "lutram",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "mode_2_memory_3_sp.mem",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
READ_DATA_WIDTH_A => C_LOOK_UP_TABLE_WIDTH,
ADDR_WIDTH_A => C_LUT_DWIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => EXT_SPI_CLK,
rsta => Rst_to_spi,
ena => '1',
regcea => '1',
addra => Look_up_address,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Look_up_op,
sbiterra => open,
dbiterra => open
);
end generate;
dist_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_3 : if (C_SELECT_XPM = 0) generate
--C_SPI_MODE_2_NM_ROM_I: dist_mem_gen_v6_4
C_SPI_MODE_1_MIXED_ROM_I: entity dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10
-------------------
generic map(
C_HAS_CLK => 1,
C_READ_MIF => 1,
C_HAS_QSPO => 1,
C_ADDR_WIDTH => C_LUT_DWIDTH,
C_WIDTH => C_LOOK_UP_TABLE_WIDTH,
C_FAMILY => C_FAMILY, -- "virtex6",
C_SYNC_ENABLE => 1,
C_DEPTH => C_LUT_DEPTH,
C_HAS_QSPO_SRST => 1,
C_MEM_INIT_FILE => "mode_2_memory_3_sp.mif",
C_DEFAULT_DATA => "0",
------------------------
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_CE => 0,
C_PARSER_TYPE => 1,
C_HAS_D => 0,
C_HAS_SPO => 0,
C_REG_A_D_INPUTS => 0,
C_HAS_WE => 0,
C_PIPELINE_STAGES => 0,
C_HAS_QDPO_RST => 0,
C_REG_DPRA_INPUT => 0,
C_QUALIFY_WE => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_DPRA => 0,
C_QCE_JOINED => 0,
C_MEM_TYPE => 0,
C_HAS_I_CE => 0,
C_HAS_DPO => 0,
-- C_HAS_SPRA => 0, -- removed from dist mem gen core
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QDPO => 0
-------------------------
)
port map(
a => Look_up_address , -- a, -- in std_logic_vector(7 downto 0)
clk => EXT_SPI_CLK , -- clk, -- in
qspo_srst => Rst_to_spi , -- qspo_srst, -- in
qspo => Look_up_op, -- qspo -- out std_logic_vector(9 downto 0)
d => "000000000000",
dpra => "00000000",
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qdpo_srst => '0',
spo => spo_8,
dpo => dpo_8,
qdpo => qdpo_8
);
end generate;
-- look up table arrangement is as below
-- 11 10 9 8 7 6 5 4 3 2 1 0
-- Data_Dir Data Mode_1 Data Mode_0 Data_Phase Quad_Phase Addr_Mode_1 Addr_Mode_0 Addr_Bit Addr_Ph CMD_Mode_1 CMD Mode_0 CMD Error
-------------
Data_Dir <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 1);-- 11 -- 15
Data_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 2);-- 10 -- 14
Data_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 3);-- 9 -- 13
Data_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 4);-- 8 -- 12
-------------
Quad_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 5); -- 7
Addr_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 6);-- 6
Addr_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 7);-- 5
Addr_Bit <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 8);-- 4
Addr_Phase <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 9);-- 3
-------------
CMD_Mode_1 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 10);-- 2
CMD_Mode_0 <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - 11);-- 1
CMD_Error <= Look_up_op(C_LOOK_UP_TABLE_WIDTH - C_LOOK_UP_TABLE_WIDTH)
and CMD_decoded_int; -- 0
-------------
-----------------------------------------
end generate QSPI_LOOK_UP_MODE_2_MEMORY_3;
---------------------
end architecture imp;
---------------------
|
bsd-3-clause
|
2dd3c96417d6ef43189bd4217780f741
| 0.376013 | 4.061243 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_cpu_pack.vhd
| 1 | 6,105 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_cpu_pack is
-- Default parameters.
constant default_cpu_mult_type : string := "DEFAULT";
constant default_cpu_shifter_type : string := "DEFAULT";
constant default_cpu_alu_type : string := "DEFAULT";
constant default_cache_address_width : integer := 25;
constant default_cache_way_width : integer := 1;
constant default_cache_index_width : integer := 6;
constant default_cache_offset_width : integer := 4;
constant default_cache_replace_strat : string := "rr";
constant default_cache_enable : boolean := True;
constant default_oper_base : std_logic_vector := X"ffffff";
constant default_oper_invalidate_offset : integer := 0;
constant default_oper_flush_offset : integer := 4;
-- AXI4-Full error constants.
constant error_axi_read_exokay : integer := 0;
constant error_axi_read_slverr : integer := 1;
constant error_axi_read_decerr : integer := 2;
constant error_axi_read_rlast : integer := 3;
constant error_axi_read_id : integer := 4;
-- AXI4-Full constants.
subtype axi_resp_type is std_logic_vector(1 downto 0);
constant axi_lock_normal_access : std_logic := '0';
constant axi_burst_incr : std_logic_vector(1 downto 0) := "01";
constant axi_resp_okay : axi_resp_type := "00";
constant axi_resp_exokay : axi_resp_type := "01";
constant axi_resp_slverr : axi_resp_type := "10";
constant axi_resp_decerr : axi_resp_type := "11";
constant axi_cache_device_nonbufferable : std_logic_vector(3 downto 0) := "0000";
constant axi_prot_priv : std_logic := '1';
constant axi_prot_sec : std_logic := '0';
constant axi_prot_instr : std_logic := '1';
-- Function declarations.
function clogb2(bit_depth : in integer ) return integer;
function add_offset2base( base_address : in std_logic_vector; offset : in integer ) return std_logic_vector;
-- Component declaration.
component plasoc_cpu is
generic(
cpu_mult_type : string := default_cpu_mult_type;
cpu_shifter_type : string := default_cpu_shifter_type;
cpu_alu_type : string := default_cpu_alu_type;
cache_address_width : integer := default_cache_address_width;
cache_way_width : integer := default_cache_way_width;
cache_index_width : integer := default_cache_index_width;
cache_offset_width : integer := default_cache_offset_width;
cache_replace_strat : string := default_cache_replace_strat;
cache_enable : boolean := default_cache_enable;
oper_base : std_logic_vector := default_oper_base;
oper_invalidate_offset : integer := default_oper_invalidate_offset;
oper_flush_offset : integer := default_oper_flush_offset );
port(
aclk : in std_logic;
aresetn : in std_logic;
axi_awid : out std_logic_vector(-1 downto 0);
axi_awaddr : out std_logic_vector(31 downto 0);
axi_awlen : out std_logic_vector(7 downto 0);
axi_awsize : out std_logic_vector(2 downto 0);
axi_awburst : out std_logic_vector(1 downto 0);
axi_awlock : out std_logic;
axi_awcache : out std_logic_vector(3 downto 0);
axi_awprot : out std_logic_vector(2 downto 0);
axi_awqos : out std_logic_vector(3 downto 0);
axi_awregion : out std_logic_vector(3 downto 0);
axi_awvalid : out std_logic;
axi_awready : in std_logic;
axi_wdata : out std_logic_vector(31 downto 0);
axi_wstrb : out std_logic_vector(3 downto 0);
axi_wlast : out std_logic;
axi_wvalid : out std_logic;
axi_wready : in std_logic;
axi_bid : in std_logic_vector(-1 downto 0);
axi_bresp : in std_logic_vector(1 downto 0);
axi_bvalid : in std_logic;
axi_bready : out std_logic;
axi_arid : out std_logic_vector(-1 downto 0);
axi_araddr : out std_logic_vector(31 downto 0);
axi_arlen : out std_logic_vector(7 downto 0);
axi_arsize : out std_logic_vector(2 downto 0);
axi_arburst : out std_logic_vector(1 downto 0);
axi_arlock : out std_logic;
axi_arcache : out std_logic_vector(3 downto 0);
axi_arprot : out std_logic_vector(2 downto 0);
axi_arqos : out std_logic_vector(3 downto 0);
axi_arregion : out std_logic_vector(3 downto 0);
axi_arvalid : out std_logic;
axi_arready : in std_logic;
axi_rid : in std_logic_vector(-1 downto 0);
axi_rdata : in std_logic_vector(31 downto 0);
axi_rresp : in std_logic_vector(1 downto 0);
axi_rlast : in std_logic;
axi_rvalid : in std_logic;
axi_rready : out std_logic;
intr_in : in std_logic);
end component;
end;
package body plasoc_cpu_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
function add_offset2base( base_address : in std_logic_vector; offset : in integer ) return std_logic_vector is
variable result : std_logic_vector(base_address'length-1 downto 0);
begin
result := std_logic_vector(to_unsigned(to_integer(unsigned(base_address))+offset,base_address'length));
return result;
end;
end;
|
mit
|
5b1aab10df190a8027d5dfc16b761566
| 0.608681 | 3.724832 | false | false | false | false |
tmeissner/cryptocores
|
aes/rtl/vhdl/aes.vhd
| 1 | 3,362 |
-- ======================================================================
-- AES encryption/decryption
-- algorithm according to FIPS 197 specification
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aes_pkg.all;
entity aes is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- mode: 0 = encrypt, 1 = decrypt
key_i : in std_logic_vector(0 to 127); -- key input
data_i : in std_logic_vector(0 to 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity aes;
architecture rtl of aes is
signal s_mode : std_logic;
signal s_accept_enc : std_logic;
signal s_valid_enc : std_logic;
signal s_data_enc : std_logic_vector(data_o'range);
signal s_accept_dec : std_logic;
signal s_valid_dec : std_logic;
signal s_data_dec : std_logic_vector(data_o'range);
begin
inputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_mode <= '0';
elsif(rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
s_mode <= mode_i;
end if;
end if;
end process inputregister;
accept_o <= s_accept_enc and s_accept_dec;
data_o <= s_data_enc when s_mode = '0' else s_data_dec;
valid_o <= s_valid_enc when s_mode = '0' else s_valid_dec;
i_aes_enc : entity work.aes_enc
generic map (
design_type => design_type
)
port map (
reset_i => reset_i,
clk_i => clk_i,
key_i => key_i,
data_i => data_i,
valid_i => valid_i and not mode_i,
accept_o => s_accept_enc,
data_o => s_data_enc,
valid_o => s_valid_enc,
accept_i => accept_i
);
i_aes_dec : entity work.aes_dec
generic map (
design_type => design_type
)
port map (
reset_i => reset_i,
clk_i => clk_i,
key_i => key_i,
data_i => data_i,
valid_i => valid_i and mode_i,
accept_o => s_accept_dec,
data_o => s_data_dec,
valid_o => s_valid_dec,
accept_i => accept_i
);
end architecture rtl;
|
gpl-2.0
|
e12849a33f63a1e504095803f9c40ff7
| 0.562165 | 3.441146 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_mode_0_module.vhd
| 2 | 95,977 |
--
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg;
use lib_pkg_v1_0_2.lib_pkg.log2;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
Rx_FIFO_Empty_i_no_fifo : in std_logic;
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
signal Rx_FIFO_Empty_i_no_fifo_sync : std_logic;
signal SPIXfer_done_drr : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
SPIXfer_done <= SPIXfer_done_drr;
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
rx_empty_no_fifo_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty_i_no_fifo,
scndry_aclk => Bus2IP_Clk,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0',
scndry_out => Rx_FIFO_Empty_i_no_fifo_sync
);
-----------------------------------------
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
------------------------------
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')then
-- Rx_FIFO_Full_reg <= '1';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif((SPIXfer_done_int_pulse = '1') and (Rx_FIFO_Empty_i_no_fifo_sync = '0'))then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse_d1; --_d2;
--SPIXfer_done_int_pulse_d1; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
-- --if ((Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') or (Rx_FIFO_Full_reg = '1' and SPIXfer_done_int_pulse = '0')) then
-- --if ((Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') or (Rx_FIFO_Empty_i_no_fifo = '1'))then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')then
-- Rx_FIFO_Full_reg <= '1';
-- elsif(Rx_FIFO_Empty_i_no_fifo = '1')then --Clear only if no simultaneous SPIXfer_done_int_pulse
-- Rx_FIFO_Full_reg <= '0';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
------------------------
--begin
-------
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
-- Rx_FIFO_Full_reg <= '1';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
------------------------------------
--DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-------
--begin
-------
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- DRR_Overrun_reg_int <= '0';
-- else
-- DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
-- Rx_FIFO_Full_reg and
-- SPIXfer_done_int_pulse_d1; --_d2;
-- --SPIXfer_done_int_pulse_d1; --_d2;
-- end if;
-- end if;
--end process DRR_OVERRUN_REG_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full and
SPIXfer_done_drr; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
-------------------- To remove glitch----------------((SPIXfer_done_int = '1' or SPIXfer_done_int_pulse_d1 = '1' ) and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_8: if C_NUM_TRANSFER_BITS = 8 generate
TRANSFER_DONE_PROCESS_8: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_8;
end generate TRANSFER_DONE_8;
TRANSFER_DONE_16: if C_NUM_TRANSFER_BITS = 16 generate
TRANSFER_DONE_PROCESS_16: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_16;
end generate TRANSFER_DONE_16;
TRANSFER_DONE_32: if C_NUM_TRANSFER_BITS = 32 generate
TRANSFER_DONE_PROCESS_32: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '1' and
Count(COUNT_WIDTH-6) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_32;
end generate TRANSFER_DONE_32;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
end if;
else
if(SPIXfer_done_int_pulse_d2 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
--RatioSlave_2_GEN : if (Mst_N_Slv = '0') generate
--begin
---ratio count for spi = 2
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS_SPI2: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= "1";
else if(Ratio_Count = "1" and Mst_N_Slv = '0') then
Ratio_Count <= "0"; --not (Ratio_Count);-- - 1;
else
Ratio_Count <= "1";--not (Ratio_Count);-- - 1;
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS_SPI2;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_SCK2_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0 and Mst_N_Slv = '0') then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_SCK2_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_SCK2_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_SCK2_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
--end generate RatioSlave_2_GEN;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
then
SPIXfer_done_int <= '1';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '0') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- transfer_start_pulse = '1' or
-- SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- elsif(Mst_N_Slv = '1') and
-- --and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
-- and
-- Count_trigger = '1'
-- then
-- SPIXfer_done_int <= '1';
-- elsif--(Mst_N_Slv = '0') and
-- and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
-- if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
-- end if;
-- end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
begin
miso_i_sync <= MISO_I;
mosi_i_sync <= MOSI_I;
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
-- CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
-- sck_d1 <= sck_o_int;
-- sck_d2 <= sck_d1;
-- -- if (sck_rising_edge = '1') then
-- if (sck_d1 = '1') then
-- rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
-- (1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
-- end if;
-- end if;
-- end process CAPT_RX_FE_MODE_00_11;
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- sck_d3 <= sck_d2;
-- if (sck_rising_edge = '1') then
if (sck_d2 = '0') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
-------------------if ((sck_d1 = '1') and (transfer_start = '1')) then
if (sck_d2 = '1') then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
-------------------if ((sck_fe1 = '0') and (transfer_start = '1')) then
if (sck_fe1 = '1') then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
|
bsd-3-clause
|
e358056840f53e6ea3836e2af1efcbbd
| 0.439501 | 4.062862 | false | false | false | false |
makestuff/vga_test
|
vhdl/vga_sync/vga_sync.vhdl
| 1 | 3,757 |
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sync is
generic(
-- Horizontal parameters (numbers are pixel clock counts)
HORIZ_DISP : integer := 640; -- display area
HORIZ_FP : integer := 16; -- front porch
HORIZ_RT : integer := 96; -- beam retrace
HORIZ_BP : integer := 48; -- back porch
-- Vertical parameters (in line counts)
VERT_DISP : integer := 480; -- display area
VERT_FP : integer := 10; -- front porch
VERT_RT : integer := 2; -- beam retrace
VERT_BP : integer := 29; -- back porch
-- Pixel coordinate bit-widths
COORD_WIDTH : integer := 10
);
port(
clk_in : in std_logic;
reset_in : in std_logic;
hSync_out : out std_logic;
vSync_out : out std_logic;
pixX_out : out unsigned(COORD_WIDTH-1 downto 0) := (others => '0');
pixY_out : out unsigned(COORD_WIDTH-1 downto 0) := (others => '0')
);
end vga_sync;
architecture arch of vga_sync is
-- Line & pixel counters
signal vCount : unsigned(COORD_WIDTH-1 downto 0) := (others => '0');
signal vCount_next : unsigned(COORD_WIDTH-1 downto 0);
signal hCount : unsigned(COORD_WIDTH-1 downto 0) := (others => '0');
signal hCount_next : unsigned(COORD_WIDTH-1 downto 0);
-- Registered horizontal & vertical sync signals
signal vSync : std_logic := '1';
signal vSync_next : std_logic;
signal hSync : std_logic := '1';
signal hSync_next : std_logic;
-- End-of-line/screen flags
signal hEnd : std_logic;
signal vEnd : std_logic;
begin
-- Registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
vCount <= (others => '0');
hCount <= (others => '0');
vSync <= '1';
hSync <= '1';
else
vCount <= vCount_next;
hCount <= hCount_next;
vSync <= vSync_next;
hSync <= hSync_next;
end if;
end if;
end process;
-- End-of-line flag
hEnd <=
'1' when hCount = HORIZ_DISP + HORIZ_FP + HORIZ_BP + HORIZ_RT - 1
else '0';
-- End-of-frame flag
vEnd <=
'1' when vCount = VERT_DISP + VERT_FP + VERT_BP + VERT_RT - 1
else '0';
-- Current pixel within the current line, 0-639 for 640x480@60Hz
hCount_next <=
hCount + 1 when hEnd = '0' else
(others => '0');
-- Current line within the current frame, 0-524 for 640x480@60Hz
vCount_next <=
(others => '0') when hEnd = '1' and vEnd = '1' else
vCount + 1 when hEnd = '1' and vEnd = '0'
else vCount;
-- Registered horizontal and vertical syncs
hSync_next <=
'0' when hCount >= HORIZ_DISP + HORIZ_FP - 1 and hCount < HORIZ_DISP + HORIZ_FP + HORIZ_RT - 1
else '1';
vSync_next <=
'0' when vCount = VERT_DISP + VERT_FP - 1 and hEnd = '1' else
'1' when vCount = VERT_DISP + VERT_FP + VERT_RT - 1 and hEnd = '1' else
vSync;
-- Drive output signals
hSync_out <= hSync;
vSync_out <= vSync;
pixX_out <= hCount;
pixY_out <= vCount;
end arch;
|
gpl-3.0
|
2ca6adbcf5156c14d420ef3ca8e558d7
| 0.615651 | 3.181202 | false | false | false | false |
a3f/r3k.vhdl
|
vhdl/tb/regFile_tb.vhdl
| 1 | 3,485 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.txt_utils.all;
use work.utils.all;
-- A testbench has no ports.
entity regFile_tb is
end regFile_tb;
architecture behav of regFile_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
signal readreg1, readreg2 : reg_t := R0;
signal writereg: reg_t := R0;
signal writedata: word_t := ZERO;
signal readData1, readData2 : word_t := ZERO;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal regWrite : std_logic := '0';
constant errormsg : string := ANSI_RED & "Testcase failed" & ANSI_NONE;
signal done : boolean := false;
begin
regFile1: regFile
port map(
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg, writedata => writedata,
readData1 => readData1, readData2 => readData2,
clk => clk, rst => rst,
regWrite => regWrite
);
test: process
begin
wait for 2 ns;
rst <= '1';
wait for 2 ns;
rst <= '0';
wait for 2 ns;
for i in 0 to 30 loop
readreg1 <= toreg(i);
readreg2 <= toreg(i+1);
wait for 2 ns;
assert readdata1 = ZERO and readdata2 = ZERO report
errormsg & ": 0 /= " & to_string(readdata1)
severity error;
end loop;
writereg <= R7;
writedata <= X"01234567";
regWrite <= '1';
wait for 2 ns;
regWrite <= '0';
wait for 2 ns;
readreg1 <= R7;
wait for 2 ns;
assert readdata1 = X"01234567" report
errormsg & to_string(readdata1)
severity error;
readreg1 <= R7;
wait for 2 ns;
assert readdata1 = X"01234567" report
errormsg & to_string(readdata1)
severity error;
writereg <= R0;
writedata <= X"01234567";
regWrite <= '1';
wait for 2 ns;
regWrite <= '0';
wait for 2 ns;
readreg1 <= R7;
wait for 2 ns;
assert readdata1 = X"01234567" report
errormsg & to_string(readdata1)
severity error;
readreg1 <= R0;
wait for 2 ns;
assert readdata1 = X"00000000" report
errormsg & to_string(readdata1)
severity error;
wait for 2 ns;
readreg1 <= R2;
wait for 2 ns;
assert readdata1 = ZERO report
errormsg &": "& to_hstring(readdata1)
severity error;
for i in 0 to 31 loop
writereg <= toreg(i);
writedata <= (31 downto 5 => '0') & toreg(i);
regWrite <= '1';
wait for 2 ns;
end loop;
for i in 0 to 31 loop
readreg1 <= toreg(i);
wait for 2 ns;
assert readData1 = (31 downto 5 => '0') & toreg(i) report
errormsg & ": " & to_string(readData1)
severity error;
end loop;
done <= true;
wait;
end process;
clkproc: process begin
clk <= not clk;
wait for 1 ns;
if done then wait; end if;
end process;
end behav;
|
gpl-3.0
|
e0b868d66b6e3b8f1311f37ab412add0
| 0.517647 | 4.005747 | false | false | false | false |
andrewandrepowell/axiplasma
|
hdl/plasma/mult.vhd
| 13 | 7,612 |
---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the multiplication and division unit in 32 clocks.
--
-- To reduce space, compile your code using the flag "-mno-mul" which
-- will use software base routines in math.c if USE_SW_MULT is defined.
-- Then remove references to the entity mult in mlite_cpu.vhd.
--
-- MULTIPLICATION
-- long64 answer = 0;
-- for(i = 0; i < 32; ++i)
-- {
-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
-- b = b >> 1;
-- }
--
-- DIVISION
-- long upper=a, lower=0;
-- a = b << 31;
-- for(i = 0; i < 32; ++i)
-- {
-- lower = lower << 1;
-- if(upper >= a && a && b < 2)
-- {
-- upper = upper - a;
-- lower |= 1;
-- }
-- a = ((b&2) << 30) | (a >> 1);
-- b = b >> 1;
-- }
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.mlite_pack.all;
entity mult is
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end; --entity mult
architecture logic of mult is
constant MODE_MULT : std_logic := '1';
constant MODE_DIV : std_logic := '0';
signal mode_reg : std_logic;
signal negate_reg : std_logic;
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal count_reg : std_logic_vector(5 downto 0);
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(32 downto 0);
begin
-- Result
c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
bv_negate(lower_reg) when mult_func = MULT_READ_LO
and negate_reg = '1' else
upper_reg when mult_func = MULT_READ_HI and negate_reg = '0' else
bv_negate(upper_reg) when mult_func = MULT_READ_HI
and negate_reg = '1' else
ZERO;
pause_out <= '1' when (count_reg /= "000000") and
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
-- ABS and remainder signals
a_neg <= bv_negate(a);
b_neg <= bv_negate(b);
sum <= bv_adder(upper_reg, aa_reg, mode_reg);
--multiplication/division unit
mult_proc: process(clk, reset_in, a, b, mult_func,
a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
variable count : std_logic_vector(2 downto 0);
begin
count := "001";
if reset_in = '1' then
mode_reg <= '0';
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
count_reg <= "000000";
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
elsif rising_edge(clk) then
case mult_func is
when MULT_WRITE_LO =>
lower_reg <= a;
negate_reg <= '0';
when MULT_WRITE_HI =>
upper_reg <= a;
negate_reg <= '0';
when MULT_MULT =>
mode_reg <= MODE_MULT;
aa_reg <= a;
bb_reg <= b;
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
when MULT_SIGNED_MULT =>
mode_reg <= MODE_MULT;
if b(31) = '0' then
aa_reg <= a;
bb_reg <= b;
else
aa_reg <= a_neg;
bb_reg <= b_neg;
end if;
if a /= ZERO then
sign_reg <= a(31) xor b(31);
else
sign_reg <= '0';
end if;
sign2_reg <= '0';
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
when MULT_DIVIDE =>
mode_reg <= MODE_DIV;
aa_reg <= b(0) & ZERO(30 downto 0);
bb_reg <= b;
upper_reg <= a;
count_reg <= "100000";
negate_reg <= '0';
when MULT_SIGNED_DIVIDE =>
mode_reg <= MODE_DIV;
if b(31) = '0' then
aa_reg(31) <= b(0);
bb_reg <= b;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if a(31) = '0' then
upper_reg <= a;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
count_reg <= "100000";
negate_reg <= a(31) xor b(31);
when others =>
if count_reg /= "000000" then
if mode_reg = MODE_MULT then
-- Multiplication
if bb_reg(0) = '1' then
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
lower_reg <= sum(0) & lower_reg(31 downto 1);
sign2_reg <= sign2_reg or sign_reg;
sign_reg <= '0';
bb_reg <= '0' & bb_reg(31 downto 1);
-- The following six lines are optional for speedup
--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
-- count_reg(5 downto 2) /= "0000" then
-- upper_reg <= "0000" & upper_reg(31 downto 4);
-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
-- count := "100";
-- bb_reg <= "0000" & bb_reg(31 downto 4);
else
upper_reg <= sign2_reg & upper_reg(31 downto 1);
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
else
-- Division
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= sum(31 downto 0);
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
count_reg <= count_reg - count;
end if; --count
end case;
end if;
end process;
end; --architecture logic
|
mit
|
40f49dbbf46cb9b8f1770c122f19d043
| 0.443116 | 3.736868 | false | false | false | false |
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_skid2mm_buf.vhd
| 4 | 17,330 |
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1_9.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
bsd-3-clause
|
986ec47097d2135790074805119c55b3
| 0.470629 | 4.487312 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.