repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
andbet050197/IS773UTP
|
modulo3/Divisor.vhd
| 1 | 688 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Divisor is
Port ( clk : in STD_LOGIC;
newC : out STD_LOGIC);
end Divisor;
architecture Behavioral of Divisor is
--signal aux: integer range 0 to 433; --115200 (433, 217)
--signal aux: integer range 0 to 2603; --19200 (2603, 1302)
signal aux: integer range 0 to 5207; --9600 (5207, 2604)
begin
process (clk)
begin
if rising_edge (clk) then
if (aux = 5207) then
aux <= 0;
elsif (aux < 2604 or aux > 2604) then
newC <= '0';
aux <= aux + 1;
elsif (aux = 2604) then
newC <= '1';
aux <= aux + 1;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
6bcf94c98e16f473966f081cda797ebc
| 0.614826 | 2.95279 | false | false | false | false |
inforichland/freezing-spice
|
src/if.vhd
| 1 | 2,464 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.if_pkg.all;
entity instruction_fetch is
port (clk : in std_logic;
rst_n : in std_logic;
d : in if_in;
q : out if_out);
end entity instruction_fetch;
architecture Behavioral of instruction_fetch is
-------------------------------------------------
-- Types
-------------------------------------------------
type registers is record
pc : unsigned(word'range);
npc : unsigned(word'range);
end record registers;
-------------------------------------------------
-- Signals
-------------------------------------------------
signal r, rin : registers;
signal zero : std_logic := '1';
-------------------------------------------------
-- Constants
-------------------------------------------------
constant c_four : unsigned(2 downto 0) := to_unsigned(4, 3);
begin -- architecture Behavioral
-------------------------------------------------
-- assign outputs
-------------------------------------------------
q.fetch_addr <= std_logic_vector(rin.pc);
q.pc <= std_logic_vector(r.pc);
-------------------------------------------------
-- PC mux
-------------------------------------------------
pc_next_proc : process (d, r, zero) is
variable v : registers;
begin -- process pc_next_proc
-- defaults
v := r;
if (zero = '1') then
v.pc := (others => '0');
elsif (d.irq = '1') then
v.pc := IRQ_VECTOR_ADDRESS;
elsif (d.load_pc = '1') then
v.pc := unsigned(d.next_pc);
elsif (d.stall = '1') then
v.pc := r.pc;
else
v.pc := r.pc + c_four;
end if;
rin <= v;
end process pc_next_proc;
-------------------------------------------------
-- create the Program Counter register
-------------------------------------------------
pc_reg_proc : process (clk, rst_n) is
begin -- process pc_reg
if (rst_n = '0') then
r.pc <= (others => '0');
zero <= '1';
elsif (rising_edge(clk)) then
r <= rin;
zero <= '0';
end if;
end process pc_reg_proc;
end architecture Behavioral;
|
bsd-3-clause
|
52f718e24381f4aa9fe476688fe6e2b2
| 0.366477 | 4.684411 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/Table_package.vhd
| 1 | 2,149 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
package TablePackage is
constant NREG : integer := 2;
constant MEMORY_SIZE : integer := NREG;
constant NBITS : integer := 1;
constant CELL_SIZE : integer := 2*NPORT+4*NBITS;
subtype cell is std_logic_vector(CELL_SIZE-1 downto 0);
subtype regAddr is std_logic_vector(2*NBITS-1 downto 0);
type memory is array (0 to MEMORY_SIZE-1) of cell;
type tables is array (0 to NROT-1) of memory;
subtype ports is std_logic_vector(NPORT-1 downto 0);
function input_ports(region : cell) return ports;
function output_ports(region : cell) return ports;
function upper_right_x(region : cell) return natural;
function upper_right_y(region : cell) return natural;
function lower_left_x(region : cell) return natural;
function lower_left_y(region : cell) return natural;
constant TAB: tables :=(
-- Router 0.0
(("10001010100100"),
("10100101100001")
),
-- Router 0.1
(("10001001001000"),
("11000111100001")
),
-- Router 1.0
(("10100000100010"),
("10010111100100")
),
-- Router 1.1
(("10000010100010"),
("10000001001000")
)
);
end TablePackage;
package body TablePackage is
function input_ports(region : cell) return ports is
variable result : std_logic_vector(NPORT-1 downto 0);
begin
result := region(CELL_SIZE-1 downto CELL_SIZE-5);
return result;
end input_ports;
function output_ports(region : cell) return ports is
begin
return region(NPORT-1 downto 0);
end output_ports;
function upper_right_x(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6-2*NBITS downto CELL_SIZE-5-3*NBITS)));
end upper_right_x;
function upper_right_y(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6-3*NBITS downto 5)));
end upper_right_y;
function lower_left_x(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6 downto CELL_SIZE-5-NBITS)));
end lower_left_x;
function lower_left_y(region : cell) return natural is
begin
return TO_INTEGER(unsigned(region(CELL_SIZE-6-NBITS downto CELL_SIZE-5-2*NBITS)));
end lower_left_y;
end TablePackage;
|
lgpl-3.0
|
0dd58482a83c0a582ba0de31b180684a
| 0.734295 | 3.306154 | false | false | false | false |
andbet050197/IS773UTP
|
modulo4/Memoria.vhd
| 1 | 864 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Memoria is
port( clk, lectura_escritura, habilitador: in STD_LOGIC;
direccion: in STD_LOGIC_VECTOR(3 downto 0);
dato_entrada: in STD_LOGIC_VECTOR(2 downto 0);
dato_salida: out STD_LOGIC_VECTOR(2 downto 0));
end Memoria;
architecture Behavioral of Memoria is
constant bits_direccion : integer := 4;
constant bits_dato : integer := 3;
type Block_ram is array(2**bits_direccion-1 downto 0) of STD_LOGIC_VECTOR(bits_dato-1 downto 0);
signal RAM: Block_ram;
begin
process(clk)
begin
if clk'event and clk = '1' then
if habilitador = '1' then
if lectura_escritura = '1' then
RAM(conv_integer(direccion)) <= dato_entrada;
else
dato_salida <= RAM(conv_integer(direccion));
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
dc2d7e99d152ab662a53d38b3225bd39
| 0.69213 | 3.107914 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/procesoBolita.vhd
| 1 | 1,781 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:48:05 10/30/2011
-- Design Name:
-- Module Name: procesoBolita - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity procesoBolita is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
inicio : in STD_LOGIC_VECTOR (7 downto 0);
filasOut : out STD_LOGIC_VECTOR (7 downto 0);
columnasOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end procesoBolita;
architecture Behavioral of procesoBolita is
signal filas : STD_LOGIC_VECTOR (7 downto 0);
signal columnas: STD_LOGIC_VECTOR (7 downto 0);
begin
process(clk,reset,inicio,filas)
begin
if reset = '1' then
filas <= "10000000";
columnas <= "00000000";
elsif clk'event and clk = '1' then
filas(7 downto 1) <= filas(6 downto 0);
filas(0) <= filas(7);
if (filas = "10000000") then
columnas <= inicio;
end if;
end if;
end process;
process(reset,clk,filas,columnas)
begin
if reset = '1' then
filasOut <= "00000001";
columnasOut <= "00000000";
elsif clk'event and clk = '1' then
filasOut <= filas;
columnasOut <= columnas;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
0c23d6efbabe0b83c62183b4321979df
| 0.608647 | 3.499018 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Phoenix_package.vhd
| 1 | 14,210 |
--------------------------------------------------------------------------
-- package com tipos basicos
--------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
package PhoenixPackage is
-----------------------------------------------------------------------
-- OCP PARAMETERS
-----------------------------------------------------------------------
------------------ command Enconding - p. 13 ---------------------------
constant IDLE: Std_Logic_Vector(2 downto 0) :="000";
constant WR: Std_Logic_Vector(2 downto 0) :="001";
constant RD: Std_Logic_Vector(2 downto 0) :="010";
constant RDEX: Std_Logic_Vector(2 downto 0) :="011";
constant BCST: Std_Logic_Vector(2 downto 0) :="111";
-----------------------Response Enconding------------------------------
constant DVA: Std_Logic_Vector(1 downto 0) :="01";
constant ERR: Std_Logic_Vector(1 downto 0) :="11";
constant NULO: Std_Logic_Vector(1 downto 0) :="00";
constant ALVO: Std_Logic_Vector(7 downto 0) :="00000000";
---------------------------------------------------------
-- CONSTANTS INDEPENDENTES
---------------------------------------------------------
constant NPORT: integer := 5;
constant EAST : integer := 0;
constant WEST : integer := 1;
constant NORTH : integer := 2;
constant SOUTH : integer := 3;
constant LOCAL : integer := 4;
---------------------------------------------------------
-- CONSTANT DEPENDENTE DA LARGURA DE BANDA DA REDE
---------------------------------------------------------
constant TAM_FLIT : integer range 1 to 64 := 16;
constant METADEFLIT : integer range 1 to 32 := (TAM_FLIT/2);
constant QUARTOFLIT : integer range 1 to 16 := (TAM_FLIT/4);
---------------------------------------------------------
-- CONSTANTS DEPENDENTES DA PROFUNDIDADE DA FILA
---------------------------------------------------------
constant TAM_BUFFER: integer := 16;
constant TAM_POINTER : integer range 1 to 32 := 5;
---------------------------------------------------------
-- CONSTANTS DEPENDENTES DO NUMERO DE ROTEADORES
---------------------------------------------------------
constant NUM_X : integer := 5;
constant NUM_Y : integer := 5;
constant NROT: integer := NUM_X*NUM_Y;
constant MIN_X : integer := 0;
constant MIN_Y : integer := 0;
constant MAX_X : integer := NUM_X-1;
constant MAX_Y : integer := NUM_Y-1;
---------------------------------------------------------
-- CONSTANT TB
---------------------------------------------------------
constant TAM_LINHA : integer := 500;
---------------------------------------------------------
-- VARIAVEIS DO NOVO HARDWARE
---------------------------------------------------------
subtype reg21 is std_logic_vector(20 downto 0);
type buffControl is array(0 to 4) of std_logic_vector((TAM_FLIT-1) downto 0);
type RouterControl is (invalidRegion, validRegion, faultPort, portError);
type ArrayRouterControl is array(NPORT downto 0) of RouterControl;
constant c_WR_ROUT_TAB : integer := 1;
constant c_WR_FAULT_TAB : integer := 2;
constant c_RD_FAULT_TAB_STEP1 : integer := 3;
constant c_RD_FAULT_TAB_STEP2 : integer := 4;
constant c_TEST_LINKS : integer := 5;
---------------------------------------------------------
-- SUBTIPOS, TIPOS E FUNCOES
---------------------------------------------------------
subtype reg3 is std_logic_vector(2 downto 0);
subtype reg8 is std_logic_vector(7 downto 0);
subtype reg32 is std_logic_vector(31 downto 0);
subtype regNrot is std_logic_vector((NROT-1) downto 0);
subtype regNport is std_logic_vector((NPORT-1) downto 0);
subtype regflit is std_logic_vector((TAM_FLIT-1) downto 0);
subtype regmetadeflit is std_logic_vector(((TAM_FLIT/2)-1) downto 0);
subtype regquartoflit is std_logic_vector((QUARTOFLIT-1) downto 0);
subtype pointer is std_logic_vector((TAM_POINTER-1) downto 0);
type buff is array(0 to TAM_BUFFER-1) of regflit;
type arrayNport_reg3 is array((NPORT-1) downto 0) of reg3;
type arrayNport_reg8 is array((NPORT-1) downto 0) of reg8;
type arrayNport_regflit is array((NPORT-1) downto 0) of regflit;
type arrayNrot_reg3 is array((NROT-1) downto 0) of reg3;
type arrayNrot_regflit is array((NROT-1) downto 0) of regflit;
type arrayNrot_regmetadeflit is array((NROT-1) downto 0) of regmetadeflit;
type arrayNrot_regNport is array((NROT-1) downto 0) of regNport;
function CONV_VECTOR( int: integer ) return std_logic_vector;
type arrayRegNport is array ((NPORT-1) downto 0) of regNport;
type routingTable is array(0 to MAX_X, 0 to MAX_Y) of std_logic_vector(NPORT-1 downto 0);
---------------------------------------------------------
-- FUNCOES TB
---------------------------------------------------------
function CONV_VECTOR( letra : string(1 to TAM_LINHA); pos: integer ) return std_logic_vector;
function CONV_HEX( int : integer ) return string;
function CONV_STRING_4BITS( dado : std_logic_vector(3 downto 0)) return string;
function CONV_STRING_8BITS( dado : std_logic_vector(7 downto 0)) return string;
function CONV_STRING_16BITS( dado : std_logic_vector(15 downto 0)) return string;
function CONV_STRING_32BITS( dado : std_logic_vector(31 downto 0)) return string;
function NUMBER_TO_ADDRESS(number: integer) return regflit;
function ADDRESS_TO_NUMBER (address: std_logic_vector) return integer;
function ADDRESS_TO_NUMBER_NOIA (address: std_logic_vector) return integer;
function to_hstring(value: std_logic_vector) return string;
function PORT_NAME(value: integer) return string;
function GET_ADDR(index : integer) return regflit;
end PhoenixPackage;
package body PhoenixPackage is
--
-- dado o index do roteador retorna o endereço correspondente
--
function GET_ADDR( index: integer) return regflit is
variable addrX, addrY: regmetadeflit;
variable addr: regflit;
begin
addrX := CONV_STD_LOGIC_VECTOR(index/NUM_X,METADEFLIT);
addrY := CONV_STD_LOGIC_VECTOR(index mod NUM_Y, METADEFLIT);
addr := addrX & addrY;
return addr;
end GET_ADDR;
--
-- converte um inteiro em um std_logic_vector(2 downto 0)
--
function CONV_VECTOR( int: integer ) return std_logic_vector is
variable bin: reg3;
begin
case(int) is
when 0 => bin := "000";
when 1 => bin := "001";
when 2 => bin := "010";
when 3 => bin := "011";
when 4 => bin := "100";
when 5 => bin := "101";
when 6 => bin := "110";
when 7 => bin := "111";
when others => bin := "000";
end case;
return bin;
end CONV_VECTOR;
---------------------------------------------------------
-- FUNCOES TB
---------------------------------------------------------
--
-- converte um caracter de uma dada linha em um std_logic_vector
--
function CONV_VECTOR( letra:string(1 to TAM_LINHA); pos: integer ) return std_logic_vector is
variable bin: std_logic_vector(3 downto 0);
begin
case (letra(pos)) is
when '0' => bin := "0000";
when '1' => bin := "0001";
when '2' => bin := "0010";
when '3' => bin := "0011";
when '4' => bin := "0100";
when '5' => bin := "0101";
when '6' => bin := "0110";
when '7' => bin := "0111";
when '8' => bin := "1000";
when '9' => bin := "1001";
when 'A' => bin := "1010";
when 'B' => bin := "1011";
when 'C' => bin := "1100";
when 'D' => bin := "1101";
when 'E' => bin := "1110";
when 'F' => bin := "1111";
when others => bin := "0000";
end case;
return bin;
end CONV_VECTOR;
-- converte um inteiro em um string
function CONV_HEX( int: integer ) return string is
variable str: string(1 to 1);
begin
case(int) is
when 0 => str := "0";
when 1 => str := "1";
when 2 => str := "2";
when 3 => str := "3";
when 4 => str := "4";
when 5 => str := "5";
when 6 => str := "6";
when 7 => str := "7";
when 8 => str := "8";
when 9 => str := "9";
when 10 => str := "A";
when 11 => str := "B";
when 12 => str := "C";
when 13 => str := "D";
when 14 => str := "E";
when 15 => str := "F";
when others => str := "U";
end case;
return str;
end CONV_HEX;
function CONV_STRING_4BITS(dado : std_logic_vector(3 downto 0)) return string is
variable str: string(1 to 1);
begin
str := CONV_HEX(CONV_INTEGER(dado));
return str;
end CONV_STRING_4BITS;
function CONV_STRING_8BITS(dado : std_logic_vector(7 downto 0)) return string is
variable str1,str2: string(1 to 1);
variable str: string(1 to 2);
begin
str1 := CONV_STRING_4BITS(dado(7 downto 4));
str2 := CONV_STRING_4BITS(dado(3 downto 0));
str := str1 & str2;
return str;
end CONV_STRING_8BITS;
function CONV_STRING_16BITS(dado : std_logic_vector(15 downto 0)) return string is
variable str1,str2: string(1 to 2);
variable str: string(1 to 4);
begin
str1 := CONV_STRING_8BITS(dado(15 downto 8));
str2 := CONV_STRING_8BITS(dado(7 downto 0));
str := str1 & str2;
return str;
end CONV_STRING_16BITS;
function CONV_STRING_32BITS(dado : std_logic_vector(31 downto 0)) return string is
variable str1,str2: string(1 to 4);
variable str: string(1 to 8);
begin
str1 := CONV_STRING_16BITS(dado(31 downto 16));
str2 := CONV_STRING_16BITS(dado(15 downto 0));
str := str1 & str2;
return str;
end CONV_STRING_32BITS;
function NUMBER_TO_ADDRESS( number: integer ) return regflit is
variable address: regflit := (others => '0');
begin
address(TAM_FLIT-1 downto METADEFLIT) := (others=>'0');
address(METADEFLIT-1 downto QUARTOFLIT) := CONV_STD_LOGIC_VECTOR(number/NUM_X, QUARTOFLIT);
address(QUARTOFLIT-1 downto 0) := CONV_STD_LOGIC_VECTOR(number mod NUM_Y, QUARTOFLIT);
return address;
end NUMBER_TO_ADDRESS;
function ADDRESS_TO_NUMBER (address: std_logic_vector) return integer is
variable number: integer := 0;
alias addrX is address(METADEFLIT-1 downto QUARTOFLIT);
alias addrY is address(QUARTOFLIT-1 downto 0);
variable X : integer := CONV_INTEGER(addrX);
variable Y : integer := CONV_INTEGER(addrY);
begin
number := Y*(MAX_X+1) + X;
return number;
end ADDRESS_TO_NUMBER;
function ADDRESS_TO_NUMBER_NOIA (address: std_logic_vector) return integer is
variable number: integer := 0;
alias addrX is address(METADEFLIT-1 downto QUARTOFLIT);
alias addrY is address(QUARTOFLIT-1 downto 0);
variable X : integer := CONV_INTEGER(addrX);
variable Y : integer := CONV_INTEGER(addrY);
begin
number := X*(MAX_Y+1) + Y;
return number;
end ADDRESS_TO_NUMBER_NOIA;
-- converte hexa para string
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4; -- numero minimo de blocos de 4 bits (truncado)
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1); -- valores finais, no caso do value nao ser multiplo de 4
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1); -- o valor em si.
variable result : STRING(1 to ne); -- blocos de 4 bits
variable quad : STD_LOGIC_VECTOR(0 to 3); -- um bloco.
begin
if value'length < 1 then
return result;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function PORT_NAME(value: integer) return string is
variable str: string (1 to 8);
begin
case value is
when EAST => str(1 to 4) := "EAST";
when WEST => str(1 to 4) := "WEST";
when NORTH => str(1 to 5) := "NORTH";
when SOUTH => str(1 to 5) := "SOUTH";
when LOCAL => str(1 to 5) := "LOCAL";
when others => str(1 to 7) := "INVALID";
end case;
return str;
end function PORT_NAME;
end PhoenixPackage;
|
lgpl-3.0
|
aee4753b22ec5cda9d27936bc3caa6e4
| 0.503273 | 4.003663 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Decoder.vhd
| 1 | 3,317 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.Numeric_std.all;
use work.HammingPack16.all;
use work.PhoenixPackage.all;
entity HAM_DEC is
port
(
data_in : in regflit; -- data input
parity_in : in reghamm; -- parity input
data_out : out regflit; -- data output (corrected data)
parity_out : out reghamm; -- parity output (corrected parity)
credit_out : out std_logic_vector(2 downto 0) -- status output (hamming results status)
);
end HAM_DEC;
architecture HAM_DEC of HAM_DEC is
begin
process(data_in, parity_in)
--overall mod-2 of all bits
variable P0 : Std_logic;
--syndrome
variable Synd : Std_logic_vector(5 downto 1);
begin
--calculate overall parity of all bits---------
P0 := xor_reduce(data_in & parity_in);
----------------------------------------------
--generate each syndrome bit C1 to C4---------------------------
Synd(1) := xor_reduce((data_in and MaskP1) & parity_in(1));
Synd(2) := xor_reduce((data_in and MaskP2) & parity_in(2));
Synd(3) := xor_reduce((data_in and MaskP4) & parity_in(3));
Synd(4) := xor_reduce((data_in and MaskP8) & parity_in(4));
Synd(5) := xor_reduce((data_in and MaskP16) & parity_in(5));
----------------------------------------------------------------
if (Synd = "0000") and (P0 = '0') then --no errors
credit_out <= NE;
data_out <= data_in;
parity_out <= parity_in;
null; --accept default o/p's assigned above
elsif P0 = '1' then --single error (or odd no of errors!)
credit_out <= EC;
data_out <= data_in;
parity_out <= parity_in;
--correct single error
case to_integer(unsigned(Synd)) is
when 0 => parity_out(0) <= not parity_in(0);
when 1 => parity_out(1) <= not parity_in(1);
when 2 => parity_out(2) <= not parity_in(2);
when 3 => data_out(0) <= not data_in(0);
when 4 => parity_out(3) <= not parity_in(3);
when 5 => data_out(1) <= not data_in(1);
when 6 => data_out(2) <= not data_in(2);
when 7 => data_out(3) <= not data_in(3);
when 8 => parity_out(4) <= not parity_in(4);
when 9 => data_out(4) <= not data_in(4);
when 10 => data_out(5) <= not data_in(5);
when 11 => data_out(6) <= not data_in(6);
when 12 => data_out(7) <= not data_in(7);
when 13 => data_out(8) <= not data_in(8);
when 14 => data_out(9) <= not data_in(9);
when 15 => data_out(10) <= not data_in(10);
when 16 => parity_out(5) <= not parity_in(5);
when 17 => data_out(11) <= not data_in(11);
when 18 => data_out(12) <= not data_in(12);
when 19 => data_out(13) <= not data_in(13);
when 20 => data_out(14) <= not data_in(14);
when 21 => data_out(15) <= not data_in(15);
when others => data_out <= "0000000000000000"; parity_out <= "000000";
end case;
elsif (P0 = '0') and (Synd /= "00000") then --double error
credit_out <= ED;
data_out <= "0000000000000000";
parity_out <= "000000";
end if;
end process;
end HAM_DEC;
|
lgpl-3.0
|
159578a3b13decb54b77de2aa9a03ee4
| 0.517033 | 3.029224 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/ula.vhd
| 1 | 1,570 |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
entity ula is
Port ( X : in STD_LOGIC_VECTOR (7 downto 0);
Y : in STD_LOGIC_VECTOR (7 downto 0);
sel_ula : in STD_LOGIC_VECTOR (2 downto 0);
N : out STD_LOGIC;
Z : out STD_LOGIC;
ula_output : out STD_LOGIC_VECTOR (7 downto 0)
);
end ula;
architecture Behavioral of ula is
signal result : STD_LOGIC_VECTOR(8 downto 0);
signal X_temp, Y_temp : STD_LOGIC_VECTOR(8 downto 0);
begin
X_temp(8 downto 0) <= '0' & X(7 downto 0);
Y_temp(8 downto 0) <= '0' & Y(7 downto 0);
ula_output <= result(7 downto 0);
result <= (X_temp(8 downto 0) + Y_temp(8 downto 0)) when sel_ula = "000" else -- ADD
(X_temp(8 downto 0) AND Y_temp(8 downto 0)) when sel_ula = "001" else -- AND
(X_temp(8 downto 0) OR Y_temp(8 downto 0)) when sel_ula = "010" else -- OR
('0' & not(X_temp(7 downto 0))) when sel_ula = "011" else -- NOT
'0' & Y when sel_ula = "100" else -- LDA
("00" & X_temp(7 downto 1)) when sel_ula = "101" else -- SHR
('0' & X_temp(6 downto 0) & '0') when sel_ula = "110" else -- SHL
(X_temp(8 downto 0) + Y_temp(8 downto 0)) when sel_ula = "111" else -- MUL
"000000000";
-- Carry
-- C <= result(8);
-- Zero
Z <= '1' when result(7 downto 0) = "00000000"
else '0';
-- Negative
N <= result(7);
end Behavioral;
|
mit
|
644da45236c0d8ccb76afd4f669908d9
| 0.586735 | 2.703448 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica4/fijas.vhd
| 1 | 1,862 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:36:09 09/11/2011
-- Design Name:
-- Module Name: fijas - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fijas is
Port ( sw1 : in STD_LOGIC_VECTOR (2 downto 0);
sw2 : in STD_LOGIC_VECTOR (2 downto 0);
sw3 : in STD_LOGIC_VECTOR (2 downto 0);
nu1 : in STD_LOGIC_VECTOR (2 downto 0);
nu2 : in STD_LOGIC_VECTOR (2 downto 0);
nu3 : in STD_LOGIC_VECTOR (2 downto 0);
fijas : out STD_LOGIC_VECTOR (2 downto 0);
led : out STD_LOGIC);
end fijas;
architecture Behavioral of fijas is
begin
fijas(0) <= ((sw1(0) xnor nu1(0))and(sw1(1) xnor nu1(1))and(sw1(2) xnor nu1(2)));
fijas(1) <= ((sw2(0) xnor nu2(0))and(sw2(1) xnor nu2(1))and(sw2(2) xnor nu2(2)));
fijas(2) <= ((sw3(0) xnor nu3(0))and(sw3(1) xnor nu3(1))and(sw3(2) xnor nu3(2)));
led <= '0' when (((sw1(0) xnor nu1(0))and(sw1(1) xnor nu1(1))and(sw1(2) xnor nu1(2)))and
((sw2(0) xnor nu2(0))and(sw2(1) xnor nu2(1))and(sw2(2) xnor nu2(2)))and
((sw3(0) xnor nu3(0))and(sw3(1) xnor nu3(1))and(sw3(2) xnor nu3(2))))= '1'
else '1';
end Behavioral;
|
gpl-2.0
|
9fc0985c91b5bd13f8fec9cd1f542476
| 0.544576 | 3.067545 | false | false | false | false |
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/hdl/internoc_ni_axi_master_v1_0.vhd
| 2 | 12,458 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity internoc_ni_axi_master_v1_0 is
generic (
-- Users to add parameters here
C_IF00_DATA_WIDTH : integer := 8;
C_PACKET_WIDTH : integer := 40;
C_PACKET_CTRL_WIDTH : integer := 3;
C_PACKET_ADDR_WIDTH : integer := 5;
C_PACKET_DATA_WIDTH : integer := 32;
C_AXI_PACKET_ADDR_OFFSET : integer := 16;
C_M00_AXI_ADDR_WIDTH : integer := 32;
C_M00_SELF_ADDR : integer := 10;
C_TIMEOUT_PERIOD : integer := 65535
);
port (
-- Users to add ports here
if00_data_in : in std_logic_vector(C_IF00_DATA_WIDTH-1 downto 0);
if00_load_in : in std_logic;
if00_data_out : out std_logic_vector(C_IF00_DATA_WIDTH-1 downto 0);
if00_load_out : out std_logic;
if00_send_done : in std_logic;
if00_send_busy : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Master Bus Interface M00_AXI;
m00_axi_aclk : in std_logic;
m00_axi_aresetn : in std_logic;
m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
m00_axi_awprot : out std_logic_vector(2 downto 0);
m00_axi_awvalid : out std_logic;
m00_axi_awready : in std_logic;
m00_axi_wdata : out std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0);
m00_axi_wstrb : out std_logic_vector(C_PACKET_DATA_WIDTH/8-1 downto 0);
m00_axi_wvalid : out std_logic;
m00_axi_wready : in std_logic;
m00_axi_bresp : in std_logic_vector(1 downto 0);
m00_axi_bvalid : in std_logic;
m00_axi_bready : out std_logic;
m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
m00_axi_arprot : out std_logic_vector(2 downto 0);
m00_axi_arvalid : out std_logic;
m00_axi_arready : in std_logic;
m00_axi_rdata : in std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0);
m00_axi_rresp : in std_logic_vector(1 downto 0);
m00_axi_rvalid : in std_logic;
m00_axi_rready : out std_logic
);
end internoc_ni_axi_master_v1_0;
architecture arch_imp of internoc_ni_axi_master_v1_0 is
-- component declaration
component internoc_ni_axi_master_v1_0_M00_AXI is
generic (
C_IF00_DATA_WIDTH : integer;
C_PACKET_WIDTH : integer;
C_PACKET_ADDR_WIDTH : integer;
C_PACKET_DATA_WIDTH : integer;
C_AXI_PACKET_ADDR_OFFSET : integer;
C_M_AXI_DATA_WIDTH : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_PACKET_CTRL_WIDTH : integer
);
port (
PACKET_TX : in std_logic_vector(C_PACKET_WIDTH-1 downto 0);
RXN_DATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
SLV_TYPE : in std_logic_vector(2 downto 0);
INIT_AXI_TXN : in std_logic;
INIT_AXI_RXN : in std_logic;
ERROR : out std_logic;
TXN_DONE : out std_logic;
RXN_DONE : out std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component internoc_ni_axi_master_v1_0_M00_AXI;
component internoc_interface_type_map is
Port (
clk_i : in STD_LOGIC;
addr_i : in STD_LOGIC_VECTOR (4 downto 0);
type_o : out STD_LOGIC_VECTOR (2 downto 0);
mode_o : out STD_LOGIC
);
end component internoc_interface_type_map;
--Counters
signal next_body_count, current_body_count : unsigned(2 downto 0) := (others=>'0');
signal next_timeout_count, current_timeout_count : integer range 0 to C_TIMEOUT_PERIOD := 0;
--Buffers
signal next_packet, current_packet : std_logic_vector(C_PACKET_WIDTH-1 downto 0) := (others=>'0');
signal next_head, current_head : unsigned(C_IF00_DATA_WIDTH-1 downto 0) := (others=>'0');
signal next_body, current_body : unsigned(C_PACKET_DATA_WIDTH-1 downto 0) := (others=>'0');
signal next_axi_data, current_axi_data : std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0) := (others=>'0');
--Control signals
signal current_interface_mode : std_logic := '0';
signal current_interface_type : std_logic_vector(2 downto 0) := (others=>'0');
signal next_if00_load, current_if00_load : std_logic := '0';
signal next_init_axi_tx, current_init_axi_tx : std_logic := '0';
signal next_init_axi_rx, current_init_axi_rx : std_logic := '0';
type protocol_state is
(
ST_IDLE,
ST_RX_HEAD,
ST_RX_BODY,
ST_PACK,
ST_AXI_INIT,
ST_AXI_RESP,
ST_TX_DATA,
ST_TX_WAIT,
ST_RESET
);
signal current_state, next_state : protocol_state;
--AXI
signal axi_read_done : std_logic := '0';
signal axi_write_done : std_logic := '0';
signal axi_data : std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0) := (others=>'0');
--Aliases
alias header_access : unsigned(0 downto 0) is current_head(C_PACKET_CTRL_WIDTH+C_PACKET_ADDR_WIDTH-1 downto C_PACKET_CTRL_WIDTH+C_PACKET_ADDR_WIDTH-1);
alias header_bytes : unsigned(C_PACKET_CTRL_WIDTH-2 downto 0) is current_head(C_PACKET_CTRL_WIDTH+C_PACKET_ADDR_WIDTH-2 downto C_PACKET_ADDR_WIDTH);
alias packet_access : std_logic is current_packet(C_PACKET_WIDTH-1);
alias packet_bytes : std_logic_vector(C_PACKET_CTRL_WIDTH-2 downto 0) is current_packet(C_PACKET_WIDTH-2 downto C_PACKET_ADDR_WIDTH+C_PACKET_DATA_WIDTH);
alias packet_address : std_logic_vector is current_packet(C_PACKET_WIDTH-C_PACKET_CTRL_WIDTH-1 downto C_PACKET_DATA_WIDTH);
alias packet_data : std_logic_vector(C_PACKET_DATA_WIDTH-1 downto 0) is current_packet(C_PACKET_DATA_WIDTH-1 downto 0);
begin
-- User logic
seq_logic: process(m00_axi_aclk)
begin
if rising_edge(m00_axi_aclk) then
if (m00_axi_aresetn='0') then
current_state <= ST_RESET;
else
-- Register control signals
current_state <= next_state;
current_init_axi_rx <= next_init_axi_rx;
current_init_axi_tx <= next_init_axi_tx;
current_axi_data <= next_axi_data;
current_packet <= next_packet;
current_body_count <= next_body_count;
current_head <= next_head;
current_body <= next_body;
current_timeout_count <= next_timeout_count;
-- Register interface load pulse
next_if00_load <= if00_load_in;
current_if00_load <= next_if00_load;
end if;
end if;
end process;
comb_logic: process(m00_axi_aclk)
begin
-- Avoid latches
next_state <= current_state;
next_init_axi_rx <= current_init_axi_rx;
next_init_axi_tx <= current_init_axi_tx;
next_axi_data <= current_axi_data;
next_packet <= current_packet;
next_body_count <= current_body_count;
next_head <= current_head;
next_body <= current_body;
next_timeout_count <= current_timeout_count;
if00_load_out <= '0';
-- Drive FSM
case current_state is
when ST_IDLE=>
if00_load_out <= '0';
if00_data_out <= (others=>'0');
if (current_if00_load='0' and next_if00_load='1') then --TODO:check for valid address
next_head <= unsigned(if00_data_in);
next_state <= ST_RX_HEAD;
end if;
when ST_RX_HEAD=>
next_body_count <= resize(header_bytes, 3)+1;
next_state <= ST_RX_BODY;
when ST_RX_BODY=>
if (current_body_count=0) then
next_state <= ST_PACK;
else
if (current_if00_load='0' and next_if00_load='1') then
next_timeout_count <= 0;
case current_body_count is
when "001"=>
next_body(7 downto 0) <= unsigned(if00_data_in);
when "010"=>
next_body(15 downto 8) <= unsigned(if00_data_in);
when "011"=>
next_body(23 downto 16) <= unsigned(if00_data_in);
when "100"=>
next_body(31 downto 24) <= unsigned(if00_data_in);
when others=>
next_state <= ST_RESET;
end case;
next_body_count <= current_body_count - 1;
else
if (current_timeout_count = C_TIMEOUT_PERIOD-1) then
next_timeout_count <= 0;
next_state <= ST_RESET;
else
next_timeout_count <= current_timeout_count + 1;
end if;
end if;
end if;
when ST_PACK=>
next_packet <= std_logic_vector(current_head) & std_logic_vector(current_body);
next_state <= ST_AXI_INIT;
when ST_AXI_INIT=>
if (packet_access='1') then
next_init_axi_rx <= '1';
else
next_init_axi_tx <= '1';
end if;
if (current_init_axi_rx='1') then
next_init_axi_rx <= '0';
next_state <= ST_AXI_RESP;
end if;
if (current_init_axi_tx='1') then
next_init_axi_tx <= '0';
next_state <= ST_AXI_RESP;
end if;
when ST_AXI_RESP=>
if (axi_write_done='1') then
next_state <= ST_IDLE;
next_head <= (others=>'0');
next_body <= (others=>'0');
next_packet <= (others=>'0');
end if;
if (axi_read_done='1') then
next_state <= ST_TX_DATA;
next_body_count <= resize(unsigned(packet_bytes), 3)+1;
next_axi_data <= axi_data;
end if;
when ST_TX_DATA=>
if (current_body_count=0) then
next_state <= ST_IDLE;
next_head <= (others=>'0');
next_body <= (others=>'0');
next_packet <= (others=>'0');
else
if (if00_send_busy='0' and if00_send_done='0') then
if00_load_out <= '1';
case current_body_count is
when "001"=>
if00_data_out <= current_axi_data(7 downto 0);
when "010"=>
if00_data_out <= current_axi_data(15 downto 8);
when "011"=>
if00_data_out <= current_axi_data(23 downto 16);
when "100"=>
if00_data_out <= current_axi_data(31 downto 24);
when others=>
if00_data_out <= (others=>'0');
end case;
next_body_count <= current_body_count - 1;
next_state <= ST_TX_WAIT;
end if;
end if;
when ST_TX_WAIT=>
if (if00_send_busy='0') then
if00_load_out <= '1';
end if;
if (if00_send_done='1') then
next_state <= ST_TX_DATA;
end if;
when ST_RESET=>
if00_data_out <= (others=>'0');
next_init_axi_rx <= '0';
next_init_axi_tx <= '0';
next_axi_data <= (others=>'0');
next_packet <= (others=>'0');
next_body_count <= (others=>'0');
next_head <= (others=>'0');
next_body <= (others=>'0');
next_timeout_count <= 0;
next_state <= ST_IDLE;
end case;
end process;
-- Instantiations
internoc_interface_type_map_inst: internoc_interface_type_map
port map (
clk_i => m00_axi_aclk,
addr_i => packet_address,
type_o => current_interface_type,
mode_o => current_interface_mode
);
internoc_ni_axi_master_v1_0_M00_AXI_inst : internoc_ni_axi_master_v1_0_M00_AXI
generic map (
C_IF00_DATA_WIDTH => C_IF00_DATA_WIDTH,
C_PACKET_WIDTH => C_PACKET_WIDTH,
C_PACKET_ADDR_WIDTH => C_PACKET_ADDR_WIDTH,
C_PACKET_DATA_WIDTH => C_PACKET_DATA_WIDTH,
C_PACKET_CTRL_WIDTH => C_PACKET_CTRL_WIDTH,
C_AXI_PACKET_ADDR_OFFSET => C_AXI_PACKET_ADDR_OFFSET,
C_M_AXI_ADDR_WIDTH => C_M00_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_PACKET_DATA_WIDTH
)
port map (
PACKET_TX => current_packet,
RXN_DATA => axi_data,
SLV_TYPE => current_interface_type,
INIT_AXI_RXN => current_init_axi_rx,
INIT_AXI_TXN => current_init_axi_tx,
TXN_DONE => axi_write_done,
RXN_DONE => axi_read_done,
M_AXI_ACLK => m00_axi_aclk,
M_AXI_ARESETN => m00_axi_aresetn,
M_AXI_AWADDR => m00_axi_awaddr,
M_AXI_AWPROT => m00_axi_awprot,
M_AXI_AWVALID => m00_axi_awvalid,
M_AXI_AWREADY => m00_axi_awready,
M_AXI_WDATA => m00_axi_wdata,
M_AXI_WSTRB => m00_axi_wstrb,
M_AXI_WVALID => m00_axi_wvalid,
M_AXI_WREADY => m00_axi_wready,
M_AXI_BRESP => m00_axi_bresp,
M_AXI_BVALID => m00_axi_bvalid,
M_AXI_BREADY => m00_axi_bready,
M_AXI_ARADDR => m00_axi_araddr,
M_AXI_ARPROT => m00_axi_arprot,
M_AXI_ARVALID => m00_axi_arvalid,
M_AXI_ARREADY => m00_axi_arready,
M_AXI_RDATA => m00_axi_rdata,
M_AXI_RRESP => m00_axi_rresp,
M_AXI_RVALID => m00_axi_rvalid,
M_AXI_RREADY => m00_axi_rready
);
end arch_imp;
|
mit
|
b39dc0db2586c76297949fbc5284dd45
| 0.634773 | 2.667095 | false | false | false | false |
inforichland/freezing-spice
|
src/csr.vhd
| 1 | 2,363 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.id_pkg.all;
use work.csr_pkg.all;
entity csr is
port (clk : in std_logic;
csr_in : in csr_in_t;
value : out word);
end entity csr;
architecture behavioral of csr is
signal cycler : unsigned(word'range) := (others => '0');
signal cyclerh : unsigned(word'range) := (others => '0');
signal timer : unsigned(word'range) := (others => '0');
signal timerh : unsigned(word'range) := (others => '0');
signal instretr : unsigned(word'range) := (others => '0');
signal instretrh : unsigned(word'range) := (others => '0');
constant c_word_max : unsigned(word'range) := (others => '1');
begin -- architecture behavioral
-- purpose: Create the CSRs
-- type : sequential
-- inputs : clk
-- outputs: value
registers_proc : process (clk) is
begin -- process registers_proc
if rising_edge(clk) then
-- CYCLE and CYCLEH
if valid = '1' then
cycler <= cycler + 1;
if cycler = c_word_max then
cyclerh <= cyclerh + 1;
end if;
end if;
-- TIME and TIMEH
if tick = '1' then
timer <= timer + 1;
if timer = c_word_max then
timerh <= timerh + 1;
end if;
end if;
-- INSTRET and INSTRETH
if instret = '1' then
instretr <= instretr + 1;
if instretr = c_word_max then
instretrh <= instretrh + 1;
end if;
end if;
-- address decode
case addr is
when CSR_CYCLE => value <= std_logic_vector(cycler);
when CSR_CYCLEH => value <= std_logic_vector(cyclerh);
when CSR_TIME => value <= std_logic_vector(timer);
when CSR_TIMEH => value <= std_logic_vector(timerh);
when CSR_INSTRET => value <= std_logic_vector(instretr);
when CSR_INSTRETH => value <= std_logic_vector(instretrh);
when others => value <= (others => '0');
end case;
end if;
end process registers_proc;
end architecture behavioral;
|
bsd-3-clause
|
11c2634adbc358bcec5711df6da7583e
| 0.509099 | 3.93178 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_uart_transceiver_0_0/synth/DemoInterconnect_uart_transceiver_0_0.vhd
| 1 | 4,632 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_0 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_0;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_0_arch OF DemoInterconnect_uart_transceiver_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_uart_transceiver_0_0_arch: ARCHITECTURE IS "uart_top,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_uart_transceiver_0_0_arch : ARCHITECTURE IS "DemoInterconnect_uart_transceiver_0_0,uart_top,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_0_arch;
|
mit
|
4e205d56163c0bcc6d92df13d6f48140
| 0.711356 | 3.732474 | false | false | false | false |
andbet050197/IS773UTP
|
modulo3/ProtocoloRS232_v2.vhd
| 1 | 1,075 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ProtocoloRS232_v2 is
Port ( Tx_salida : out STD_LOGIC;
Rx_entrada : in STD_LOGIC;
CLK : in STD_LOGIC;
CampanaTx : in STD_LOGIC;
CampanaRx : out STD_LOGIC;
Dato_Tx : in STD_LOGIC_VECTOR (7 downto 0);
Dato_Rx : out STD_LOGIC_VECTOR (7 downto 0));
end ProtocoloRS232_v2;
architecture Behavioral of ProtocoloRS232_v2 is
COMPONENT Rx
PORT(
Dato_entrada : IN std_logic;
CLK : IN std_logic;
Dato_salida : OUT std_logic_vector(7 downto 0);
Campana : OUT std_logic
);
END COMPONENT;
COMPONENT Tx
PORT(
Campana : IN std_logic;
CLK : IN std_logic;
Dato_entrada : IN std_logic_vector(7 downto 0);
Dato_salida : OUT std_logic
);
END COMPONENT;
begin
Inst_Rx: Rx PORT MAP(
Dato_entrada => Rx_entrada,
CLK => CLK,
Dato_salida => Dato_Rx,
Campana => CampanaRx
);
Inst_Tx: Tx PORT MAP(
Campana => CampanaTx,
CLK => CLK,
Dato_entrada => Dato_Tx,
Dato_salida => Tx_salida
);
end Behavioral;
|
gpl-3.0
|
5f0905eff2ef6f819e0518f0401025cf
| 0.616744 | 3.011204 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_0_1/synth/DemoInterconnect_axi_spi_master_0_1.vhd
| 1 | 11,283 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_0_1 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_0_1;
ARCHITECTURE DemoInterconnect_axi_spi_master_0_1_arch OF DemoInterconnect_axi_spi_master_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_axi_spi_master_0_1_arch: ARCHITECTURE IS "axi_spi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_axi_spi_master_0_1_arch : ARCHITECTURE IS "DemoInterconnect_axi_spi_master_0_1,axi_spi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_1_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_0_1_arch;
|
mit
|
5c0241944d807106bc18047bd6b3dc71
| 0.714349 | 3.191796 | false | false | false | false |
egk696/InterNoC
|
ip_repo/uart_transceiver_v1_0/uart_top.vhd
| 3 | 2,581 |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- The receiver is able to
-- receive 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When receive is complete o_rx_dv will be
-- driven high for one clock cycle.
--
-- The transmitter is able to
-- transmit 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When transmit is complete o_TX_Done will be
-- driven high for one clock cycle.
--
entity uart_top is
generic(
CLK_FREQ : integer := 10000000;
BAUD_RATE : integer := 115200
);
port(
--GLOBAL
i_Clk : in std_logic;
--RX
i_RX_Serial : in std_logic;
o_RX_Done : out std_logic;
o_RX_Byte : out std_logic_vector(7 downto 0);
--TX
i_TX_Load : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end uart_top;
architecture rtl of uart_top is
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
--
constant c_CLKS_PER_BIT : integer := CLK_FREQ/BAUD_RATE; -- Needs to be set correctly
--component declaration
component UART_RX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_RX_Serial : in std_logic;
o_RX_DV : out std_logic;
o_RX_Byte : out std_logic_vector(7 downto 0)
);
end component;
component UART_TX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_TX_DV : in std_logic;
i_TX_Byte : in std_logic_vector(7 downto 0);
o_TX_Active : out std_logic;
o_TX_Serial : out std_logic;
o_TX_Done : out std_logic
);
end component;
begin
--component instantiation
uart_rx_inst: UART_RX
generic map(
g_CLKS_PER_BIT => c_CLKS_PER_BIT
)
port map(
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_DV => o_RX_Done,
o_RX_Byte => o_RX_Byte
);
uart_tx_inst: UART_TX
generic map(
g_CLKS_PER_BIT => c_CLKS_PER_BIT
)
port map(
i_Clk => i_Clk,
i_TX_DV => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
end rtl;
|
mit
|
6c84660e4ee41e05403eabec7d735371
| 0.572646 | 3.054438 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_1_1/sim/DemoInterconnect_axi_spi_master_1_1.vhd
| 2 | 10,931 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_1 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_1;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_1_arch OF DemoInterconnect_axi_spi_master_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_1_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_1_arch;
|
mit
|
c77a6351f52254d6a979122a22f94b12
| 0.712744 | 3.190601 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AB_HAA.vhd
| 1 | 673 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LatchSR_AB_HAA is
Port ( Sn : in STD_LOGIC;
Rn : in STD_LOGIC;
EN : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end LatchSR_AB_HAA;
architecture Behavioral of LatchSR_AB_HAA is
COMPONENT LatchSR_AA
PORT(
S : IN std_logic;
R : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
signal S_aux : std_logic := '0';
signal R_aux : std_logic := '0';
begin
S_aux <= Sn nor (not EN);
R_aux <= Rn nor (not EN);
Inst_LatchSR_AA: LatchSR_AA PORT MAP(
S => S_aux,
R => R_aux,
Q => Q,
Qn => Qn
);
end Behavioral;
|
gpl-3.0
|
594c5612665a5463fecace2096f8d003
| 0.566122 | 2.724696 | false | false | false | false |
inforichland/freezing-spice
|
tests/decoder_tb.vhd
| 1 | 15,313 |
library ieee;
use ieee.std_logic_1164.all;
use work.id_pkg.all;
use work.common.all;
use work.encode_pkg.all;
entity decoder_tb is
end entity decoder_tb;
architecture testbench of decoder_tb is
-- inputs
signal insn : word;
-- outputs
signal decoded : decoded_t;
procedure verify_r_type (insn_type : in insn_type_t;
r_insn : in r_insn_t;
rs1, rs2, d : in std_logic_vector(4 downto 0)) is
begin
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
case (r_insn) is
when R_ADD => assert decoded.alu_func = ALU_ADD report "Invalid ALU function" severity error;
when R_SLT => assert decoded.alu_func = ALU_SLT report "Invalid ALU function" severity error;
when R_SLTU => assert decoded.alu_func = ALU_SLTU report "Invalid ALU function" severity error;
when R_AND => assert decoded.alu_func = ALU_AND report "Invalid ALU function" severity error;
when R_OR => assert decoded.alu_func = ALU_OR report "Invalid ALU function" severity error;
when R_XOR => assert decoded.alu_func = ALU_XOR report "Invalid ALU function" severity error;
when R_SLL => assert decoded.alu_func = ALU_SLL report "Invalid ALU function" severity error;
when R_SRL => assert decoded.alu_func = ALU_SRL report "Invalid ALU function" severity error;
when R_SUB => assert decoded.alu_func = ALU_SUB report "Invalid ALU function" severity error;
when R_SRA => assert decoded.alu_func = ALU_SRA report "Invalid ALU function" severity error;
end case;
end procedure verify_r_type;
-- purpose: verify U-type instruction
procedure verify_u_type (
insn_type : in insn_type_t;
imm : in word;
rd : in std_logic_vector(4 downto 0)) is
begin
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid Immediate Value" severity error;
assert decoded.rd = rd report "Invalid Rd" severity error;
end procedure verify_u_type;
-- purpose: verify UJ-type instruction
procedure verify_uj_type (
insn_type : in insn_type_t;
imm : in word;
rd : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_uj_type
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid immediate" severity error;
assert decoded.rd = rd report "Invalid Rd" severity error;
end procedure verify_uj_type;
-- purpose: verify a decoded I-type instruction
procedure verify_i_type (insn_type : in insn_type_t;
i_type : in i_insn_t;
imm : in word;
rs1, rd : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_i_type
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid immediate" severity error;
assert decoded.rs1 = rs1 report "Invalid Rs1" severity error;
assert decoded.rd = rd report "Invalid Rd" severity error;
case (insn_type) is
when OP_LOAD =>
case i_type is
when I_LB => assert decoded.load_type = LB report "Invalid load type" severity error;
when I_LH => assert decoded.load_type = LH report "Invalid load type" severity error;
when I_LW => assert decoded.load_type = LW report "Invalid load type" severity error;
when I_LBU => assert decoded.load_type = LBU report "Invalid load type" severity error;
when I_LHU => assert decoded.load_type = LHU report "Invalid load type" severity error;
when others => assert false report "Unexpected load type" severity error;
end case;
when OP_ALU =>
case i_type is
when I_ADDI => assert decoded.alu_func = ALU_ADD report "Invalid ALU function" severity error;
when I_SLTI => assert decoded.alu_func = ALU_SLT report "Invalid ALU function" severity error;
when I_SLTIU => assert decoded.alu_func = ALU_SLTU report "Invalid ALU function" severity error;
when I_XORI => assert decoded.alu_func = ALU_XOR report "Invalid ALU function" severity error;
when I_ORI => assert decoded.alu_func = ALU_OR report "Invalid ALU function" severity error;
when I_ANDI => assert decoded.alu_func = ALU_AND report "Invalid ALU function" severity error;
when others => assert false report "Unexpected ALU function" severity error;
end case;
when OP_JALR => null;
when others =>
assert false report "Unexpected instruction type" severity error;
end case;
end procedure verify_i_type;
procedure verify_s_type (insn_type : in insn_type_t;
s_type : in s_insn_t;
imm : in word;
rs1, rs2 : in std_logic_vector(4 downto 0)) is
begin
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "" severity error;
assert decoded.rs1 = rs1 report "Invalid Rs1" severity error;
assert decoded.rs2 = rs2 report "Invalid Rs2" severity error;
case s_type is
when S_SB => assert decoded.store_type = SB report "Invalid store type" severity error;
when S_SH => assert decoded.store_type = SH report "Invalid store type" severity error;
when S_SW => assert decoded.store_type = SW report "Invalid store type" severity error;
when others => assert false report "Unexpected store type" severity error;
end case;
end procedure verify_s_type;
-- purpose: verify a decoded SB-type instruction
procedure verify_sb_type (
insn_type : in insn_type_t;
imm : in word;
branch_type : in branch_type_t;
rs1, rs2 : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_sb_type
print_insn(insn_type);
assert decoded.insn_type = insn_type report "Invalid instruction type" severity error;
assert decoded.imm = imm report "Invalid immediate" severity error;
assert decoded.branch_type = branch_type report "Invalid branch type" severity error;
assert decoded.rs1 = rs1 report "Invalid Rs1" severity error;
assert decoded.rs2 = rs2 report "Invalid Rs2" severity error;
end procedure verify_sb_type;
-- purpose: verify a decoded I-type shift instruction
procedure verify_i_shift (
i_insn : in i_insn_t;
shamt : in std_logic_vector(4 downto 0);
rs1, rd : in std_logic_vector(4 downto 0)) is
begin -- procedure verify_i_shift
println("Instruction type: ALU SHIFT");
assert decoded.insn_type = OP_ALU report "Expected OP_ALU" severity error;
case i_insn is
when I_SLLI =>
assert decoded.alu_func = ALU_SLL report "Invalid ALU type" severity error;
when I_SRLI =>
assert decoded.alu_func = ALU_SRL report "Invalid ALU type" severity error;
when I_SRAI =>
assert decoded.alu_func = ALU_SRA report "Invalid ALU type" severity error;
when others =>
assert false report "Invalid Shift type" severity error;
end case;
end procedure verify_i_shift;
begin -- architecture test
uut : entity work.instruction_decoder(behavioral)
port map (d => insn,
q => decoded);
-- purpose: provide stimulus and verification of the RISCV decoder
-- type : combinational
-- inputs :
-- outputs: asserts
stimulus_proc : process is
begin -- process stimulus_proc
-- LUI
insn <= encode_u_type(U_LUI, "01010101010101010101", 31);
wait for 1 ns;
verify_u_type(OP_LUI, "01010101010101010101000000000000", "11111");
-- AUIPC
insn <= encode_u_type(U_AUIPC, "10101010101010101010", 21);
wait for 1 ns;
verify_u_type(OP_AUIPC, "10101010101010101010000000000000", "10101");
-- JAL
insn <= encode_uj_type(UJ_JAL, "11010101001010101010", 10);
wait for 1 ns;
verify_uj_type(OP_JAL, "11111111111110101010010101010100", "01010");
-- JALR
insn <= encode_i_type(I_JALR, "110011001100", 6, 5);
wait for 1 ns;
verify_i_type(OP_JALR, I_JALR, "11111111111111111111110011001100", "00110", "00101");
-- BEQ
insn <= encode_sb_type(SB_BEQ, "101101101101", 20, 1);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "11111111111111111111011011011010", BEQ, "10100", "00001");
-- BNE
insn <= encode_sb_type(SB_BNE, "000010000101", 16, 18);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000000100001010", BNE, "10000", "10010");
-- BLT
insn <= encode_sb_type(SB_BLT, "001011001110", 15, 14);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000010110011100", BLT, "01111", "01110");
-- BGE
insn <= encode_sb_type(SB_BGE, "001010101001", 13, 12);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000010101010010", BGE, "01101", "01100");
-- BLTU
insn <= encode_sb_type(SB_BLTU, "001010101001", 13, 12);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "00000000000000000000010101010010", BLTU, "01101", "01100");
-- BGEU
insn <= encode_sb_type(SB_BGEU, "101111000110", 11, 10);
wait for 1 ns;
verify_sb_type(OP_BRANCH, "11111111111111111111011110001100", BGEU, "01011", "01010");
-- LB
insn <= encode_i_type(I_LB, "000111000111", 9, 8);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LB, "00000000000000000000000111000111", "01001", "01000");
-- LH
insn <= encode_i_type(I_LH, "011011011011", 7, 6);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LH, "00000000000000000000011011011011", "00111", "00110");
-- LW
insn <= encode_i_type(I_LW, "011011011010", 5, 4);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LW, "00000000000000000000011011011010", "00101", "00100");
-- LBU
insn <= encode_i_type(I_LBU, "110110110110", 3, 2);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LBU, "11111111111111111111110110110110", "00011", "00010");
-- LHU
insn <= encode_i_type(I_LHU, "111111111111", 1, 0);
wait for 1 ns;
verify_i_type(OP_LOAD, I_LHU, "11111111111111111111111111111111", "00001", "00000");
-- SB
insn <= encode_s_type(S_SB, "011111111110", 21, 22);
wait for 1 ns;
verify_s_type(OP_STORE, S_SB, "00000000000000000000011111111110", "10101", "10110");
-- SH
insn <= encode_s_type(S_SH, "011111111110", 21, 22);
wait for 1 ns;
verify_s_type(OP_STORE, S_SH, "00000000000000000000011111111110", "10101", "10110");
-- SW
insn <= encode_s_type(S_SW, "001111111110", 23, 24);
wait for 1 ns;
verify_s_type(OP_STORE, S_SW, "00000000000000000000001111111110", "10111", "11000");
-- ADDI
insn <= encode_i_type(I_ADDI, "111111111111", 25, 26);
wait for 1 ns;
verify_i_type(OP_ALU, I_ADDI, "11111111111111111111111111111111", "11001", "11010");
-- SLTI
insn <= encode_i_type(I_SLTI, "111111111110", 27, 28);
wait for 1 ns;
verify_i_type(OP_ALU, I_SLTI, "11111111111111111111111111111110", "11011", "11100");
-- SLTIU
insn <= encode_i_type(I_SLTIU, "111111111100", 29, 30);
wait for 1 ns;
verify_i_type(OP_ALU, I_SLTIU, "11111111111111111111111111111100", "11101", "11110");
-- XORI
insn <= encode_i_type(I_XORI, "111111111110", 31, 30);
wait for 1 ns;
verify_i_type(OP_ALU, I_XORI, "11111111111111111111111111111110", "11111", "11110");
-- ORI
insn <= encode_i_type(I_ORI, "111111111110", 1, 2);
wait for 1 ns;
verify_i_type(OP_ALU, I_ORI, "11111111111111111111111111111110", "00001", "00010");
-- ANDI
insn <= encode_i_type(I_ANDI, "111111111110", 3, 4);
wait for 1 ns;
verify_i_type(OP_ALU, I_ANDI, "11111111111111111111111111111110", "00011", "00100");
-- SLLI
insn <= encode_i_shift(I_SLLI, "11100", 5, 6);
wait for 1 ns;
verify_i_shift(I_SLLI, "11100", "00101", "00110");
-- SRLI
insn <= encode_i_shift(I_SRLI, "11101", 7, 8);
wait for 1 ns;
verify_i_shift(I_SRLI, "11101", "00101", "00110");
-- SRAI
insn <= encode_i_shift(I_SRAI, "11110", 9, 10);
wait for 1 ns;
verify_i_shift(I_SRAI, "11110", "00101", "00110");
-- ADD
insn <= encode_r_type(R_ADD, 2, 4, 8);
wait for 1 ns;
verify_r_type(OP_ALU, R_ADD, "00010", "00100", "01000");
-- SUB
insn <= encode_r_type(R_SUB, 16, 31, 1);
wait for 1 ns;
verify_r_type(OP_ALU, R_SUB, "10000", "11111", "00001");
-- SLL
insn <= encode_r_type(R_SLL, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_SLL, "00000", "00000", "00000");
-- SLT
insn <= encode_r_type(R_SLT, 16, 8, 4);
wait for 1 ns;
verify_r_type(OP_ALU, R_SLT, "10000", "01000", "00100");
-- SLTU
insn <= encode_r_type(R_SLTU, 24, 12, 6);
wait for 1 ns;
verify_r_type(OP_ALU, R_SLTU, "11000", "01100", "00110");
-- XOR
insn <= encode_r_type(R_XOR, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_XOR, "00000", "00000", "00000");
-- SRL
insn <= encode_r_type(R_SRL, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_SRL, "00000", "00000", "00000");
-- SRA
insn <= encode_r_type(R_SRA, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_SRA, "00000", "00000", "00000");
-- OR
insn <= encode_r_type(R_OR, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_OR, "00000", "00000", "00000");
-- AND
insn <= encode_r_type(R_AND, 0, 0, 0);
wait for 1 ns;
verify_r_type(OP_ALU, R_AND, "00000", "00000", "00000");
-- @todo others
----------------------------------------------------------------
println("Verification complete");
----------------------------------------------------------------
wait;
end process stimulus_proc;
end architecture testbench;
|
bsd-3-clause
|
6faeebfc6215c389ee45277d79a641bf
| 0.575328 | 3.874747 | false | false | false | false |
dl3yc/sdr-fm
|
dev/pfd/pfd.vhd
| 1 | 1,367 |
-- PFD module for Betty SDR
-- implements a polar frequency discriminator
-- file: pfd.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - tested with matlab against reference implementation
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pfd is
port (
clk : in std_logic;
stb : in std_logic;
i_in : in signed(26 downto 0);
q_in : in signed(26 downto 0);
i_out : out signed(26 downto 0);
q_out : out signed(26 downto 0);
rdy : out std_logic
);
end entity pfd;
architecture rtl of pfd is
signal i_delay : signed(26 downto 0);
signal q_delay : signed(26 downto 0);
signal i_prod0 : signed(26 downto 0);
signal i_prod1 : signed(26 downto 0);
signal q_prod0 : signed(26 downto 0);
signal q_prod1 : signed(26 downto 0);
signal stb_d : std_logic;
begin
process
begin
wait until rising_edge(clk);
if stb = '1' then
i_delay <= i_in;
q_delay <= q_in;
i_prod0 <= resize(shift_right(i_in * i_delay,26),27);
i_prod1 <= resize(shift_right(q_in * q_delay,26),27);
q_prod0 <= resize(shift_right(-i_in * q_delay,26),27);
q_prod1 <= resize(shift_right(q_in * i_delay,26),27);
end if;
i_out <= i_prod0 + i_prod1;
q_out <= q_prod0 + q_prod1;
stb_d <= stb;
rdy <= stb_d;
end process;
end architecture rtl;
|
gpl-2.0
|
9a4661b3c27d8e75d57f2f49f05289aa
| 0.64594 | 2.638996 | false | false | false | false |
andbet050197/IS773UTP
|
Registros/PISO8bits_TB.vhd
| 1 | 1,264 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PISO8bits_TB IS
END PISO8bits_TB;
ARCHITECTURE behavior OF PISO8bits_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PISO8bits
PORT(
Reset : IN std_logic;
D : IN std_logic_vector(7 downto 0);
CLK : IN std_logic;
SL : IN std_logic;
O : OUT std_logic
);
END COMPONENT;
--Inputs
signal Reset : std_logic := '0';
signal D : std_logic_vector(7 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal SL : std_logic := '0';
--Outputs
signal O : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PISO8bits PORT MAP (
Reset => Reset,
D => D,
CLK => CLK,
SL => SL,
O => O
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
SL <= '1';
D <= "10011010";
wait for 10 ns;
SL <= '0';
D <= "00000000";
wait;
end process;
END;
|
gpl-3.0
|
c8f7ae24855e6870acf3aaf9fa770fd9
| 0.548259 | 3.416216 | false | false | false | false |
andbet050197/IS773UTP
|
Flip-Flops/F-F-D-CLR.vhd
| 1 | 514 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FFDCLR is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end FFDCLR;
architecture Behavioral of FFDCLR is
signal aux : std_logic := '0';
begin
with CLR select
Q <= '0' when '1',
aux when Others;
process (CLK)
begin
if CLK'event and CLK='1' then
if CLR = '1' then
aux <= '0';
else
aux <= D;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
5ff31039ffe646e7cb99a1fdef781e50
| 0.560311 | 2.937143 | false | false | false | false |
inforichland/freezing-spice
|
tests/pipeline_tb.vhd
| 1 | 5,955 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.id_pkg.all;
use work.encode_pkg.all;
use work.test_config.all;
entity pipeline_tb is
end entity pipeline_tb;
architecture testbench of pipeline_tb is
signal clk : std_logic := '0';
signal rst_n : std_logic := '1';
-- inputs
signal insn_in : word := (others => '0');
signal insn_addr : word := (others => '0');
signal insn_valid : std_logic := '0';
-- shift registers to simulate delays in accessing memory
constant c_data_in_delay : integer := 4; -- number of delay cycles for memory reads
type data_in_sr_t is array (0 to c_data_in_delay - 1) of std_logic_vector(31 downto 0); --word;
type data_in_valid_sr_t is array (0 to c_data_in_delay - 1) of std_logic;
signal data_in : data_in_sr_t := (others => (others => '0'));
signal data_in_valid : data_in_valid_sr_t := (others => '0');
signal data_valid : std_logic;
-- outputs
signal data_write_en : std_logic;
signal data_read_en : std_logic;
signal data_addr : word;
signal data_out : word;
-- simulation specific
signal done : boolean := false;
constant clk_period : time := 10 ns; -- 100 MHz
file memfile : text open write_mode is "sim/memio.vec";
-- data memory
type ram_t is array(0 to 100) of word;
signal ram : ram_t := (0 => X"80008081",
others => (others => '0'));
begin
instruction_memory : entity work.dpram(rtl)
generic map (g_data_width => 32,
g_addr_width => 8,
g_init => true,
g_init_file => pipeline_tb_test_vector_input_filename)
port map (clk => clk,
addr_a => insn_addr(7 downto 0),
data_a => (others => '0'),
we_a => '0',
q_a => insn_in,
addr_b => (others => '0'),
data_b => (others => '0'),
we_b => '0',
q_b => open);
-- create a clock
clk <= '0' when done else (not clk) after clk_period / 2;
-- purpose: data memory
ram_proc : process (clk, rst_n) is
variable addr : integer;
variable valid : std_logic;
begin
if rst_n = '0' then
reset_shift_regs : for i in data_in'range loop
data_in(i) <= (others => '0');
data_in_valid(i) <= '0';
end loop reset_shift_regs;
elsif rising_edge(clk) then
-- default values
data_in_valid(0) <= '0';
data_in(0) <= (others => '0');
-- create shift registers
shift_regs : for i in 1 to data_in'high loop
data_in(i) <= data_in(i - 1);
data_in_valid(i) <= data_in_valid(i - 1);
end loop shift_regs;
if ((data_in_valid(data_in_valid'high) = '0')
and (data_in_valid(data_in_valid'high - 1) = '1')) then
valid := '1';
else
valid := '0';
end if;
data_valid <= valid;
-- writes/reads
addr := to_integer(unsigned(data_addr));
if data_write_en = '1' then
ram(addr) <= data_out;
elsif data_read_en = '1' then
data_in(0) <= ram(addr);
data_in_valid(0) <= '1';
end if;
end if;
end process ram_proc;
---------------------------------------------------
-- print memory bus transactions
---------------------------------------------------
log_memio_proc : process (data_write_en, data_read_en, data_valid, clk) is
variable l : line;
begin -- process log_memio_proc
if data_write_en = '1' and clk = '0' then
write(l, string'("W "));
write(l, hstr(data_addr));
write(l, string'(", "));
write(l, hstr(data_out));
writeline(memfile, l);
end if;
if (data_valid = '1' and clk = '0') then
write(l, string'("R "));
write(l, hstr(data_addr));
write(l, string'(", "));
write(l, hstr(data_in(data_in'high)));
writeline(memfile, l);
end if;
end process log_memio_proc;
-- instantiate the unit under test
uut : entity work.pipeline(Behavioral)
generic map (
g_initial_pc => (others => '0'),
g_for_sim => true)
port map (
clk => clk,
rst_n => rst_n,
insn_in => insn_in,
insn_addr => insn_addr,
insn_valid => insn_valid,
data_in => data_in(data_in'high),
data_out => data_out,
data_addr => data_addr,
data_write_en => data_write_en,
data_read_en => data_read_en,
data_in_valid => data_valid);
-- purpose: Provide stimulus to test the pipeline
stimulus_proc : process is
variable i : natural := 0;
begin -- process stimulus_proc
-- reset sequence
println ("Beginning simulation");
-- fill up the instruction memory
rst_n <= '0';
wait for clk_period * 2;
rst_n <= '1';
-- begin stimulus
wait for clk_period;
insn_valid <= '1';
-- run for a bit.
wait for clk_period * 35;
-- finished with simulation
----------------------------------------------------------------
println("Simulation complete");
----------------------------------------------------------------
done <= true;
wait;
end process stimulus_proc;
end architecture testbench;
|
bsd-3-clause
|
92f90c3b9d47d43486d4bbcfb4a2fc9d
| 0.467003 | 3.859365 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_mutex_0_0/synth/DemoInterconnect_mutex_0_0.vhd
| 1 | 29,688 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mutex:2.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mutex_v2_1_8;
USE mutex_v2_1_8.mutex;
ENTITY DemoInterconnect_mutex_0_0 IS
PORT (
S0_AXI_ACLK : IN STD_LOGIC;
S0_AXI_ARESETN : IN STD_LOGIC;
S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_AWVALID : IN STD_LOGIC;
S0_AXI_AWREADY : OUT STD_LOGIC;
S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S0_AXI_WVALID : IN STD_LOGIC;
S0_AXI_WREADY : OUT STD_LOGIC;
S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_BVALID : OUT STD_LOGIC;
S0_AXI_BREADY : IN STD_LOGIC;
S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_ARVALID : IN STD_LOGIC;
S0_AXI_ARREADY : OUT STD_LOGIC;
S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_RVALID : OUT STD_LOGIC;
S0_AXI_RREADY : IN STD_LOGIC;
S1_AXI_ACLK : IN STD_LOGIC;
S1_AXI_ARESETN : IN STD_LOGIC;
S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_AWVALID : IN STD_LOGIC;
S1_AXI_AWREADY : OUT STD_LOGIC;
S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S1_AXI_WVALID : IN STD_LOGIC;
S1_AXI_WREADY : OUT STD_LOGIC;
S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_BVALID : OUT STD_LOGIC;
S1_AXI_BREADY : IN STD_LOGIC;
S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_ARVALID : IN STD_LOGIC;
S1_AXI_ARREADY : OUT STD_LOGIC;
S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_RVALID : OUT STD_LOGIC;
S1_AXI_RREADY : IN STD_LOGIC;
S2_AXI_ACLK : IN STD_LOGIC;
S2_AXI_ARESETN : IN STD_LOGIC;
S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_AWVALID : IN STD_LOGIC;
S2_AXI_AWREADY : OUT STD_LOGIC;
S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S2_AXI_WVALID : IN STD_LOGIC;
S2_AXI_WREADY : OUT STD_LOGIC;
S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_BVALID : OUT STD_LOGIC;
S2_AXI_BREADY : IN STD_LOGIC;
S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_ARVALID : IN STD_LOGIC;
S2_AXI_ARREADY : OUT STD_LOGIC;
S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_RVALID : OUT STD_LOGIC;
S2_AXI_RREADY : IN STD_LOGIC
);
END DemoInterconnect_mutex_0_0;
ARCHITECTURE DemoInterconnect_mutex_0_0_arch OF DemoInterconnect_mutex_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT mutex IS
GENERIC (
C_FAMILY : STRING;
C_NUM_AXI : INTEGER;
C_S0_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S0_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S0_AXI_ADDR_WIDTH : INTEGER;
C_S0_AXI_DATA_WIDTH : INTEGER;
C_S1_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S1_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S1_AXI_ADDR_WIDTH : INTEGER;
C_S1_AXI_DATA_WIDTH : INTEGER;
C_S2_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S2_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S2_AXI_ADDR_WIDTH : INTEGER;
C_S2_AXI_DATA_WIDTH : INTEGER;
C_S3_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S3_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S3_AXI_ADDR_WIDTH : INTEGER;
C_S3_AXI_DATA_WIDTH : INTEGER;
C_S4_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S4_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S4_AXI_ADDR_WIDTH : INTEGER;
C_S4_AXI_DATA_WIDTH : INTEGER;
C_S5_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S5_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S5_AXI_ADDR_WIDTH : INTEGER;
C_S5_AXI_DATA_WIDTH : INTEGER;
C_S6_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S6_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S6_AXI_ADDR_WIDTH : INTEGER;
C_S6_AXI_DATA_WIDTH : INTEGER;
C_S7_AXI_BASEADDR : STD_LOGIC_VECTOR;
C_S7_AXI_HIGHADDR : STD_LOGIC_VECTOR;
C_S7_AXI_ADDR_WIDTH : INTEGER;
C_S7_AXI_DATA_WIDTH : INTEGER;
C_ASYNC_CLKS : INTEGER;
C_NUM_SYNC_FF : INTEGER;
C_ENABLE_USER : INTEGER;
C_OWNER_ID_WIDTH : INTEGER;
C_ENABLE_HW_PROT : INTEGER;
C_NUM_MUTEX : INTEGER
);
PORT (
S0_AXI_ACLK : IN STD_LOGIC;
S0_AXI_ARESETN : IN STD_LOGIC;
S0_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_AWVALID : IN STD_LOGIC;
S0_AXI_AWREADY : OUT STD_LOGIC;
S0_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S0_AXI_WVALID : IN STD_LOGIC;
S0_AXI_WREADY : OUT STD_LOGIC;
S0_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_BVALID : OUT STD_LOGIC;
S0_AXI_BREADY : IN STD_LOGIC;
S0_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_ARVALID : IN STD_LOGIC;
S0_AXI_ARREADY : OUT STD_LOGIC;
S0_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S0_AXI_RVALID : OUT STD_LOGIC;
S0_AXI_RREADY : IN STD_LOGIC;
S1_AXI_ACLK : IN STD_LOGIC;
S1_AXI_ARESETN : IN STD_LOGIC;
S1_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_AWVALID : IN STD_LOGIC;
S1_AXI_AWREADY : OUT STD_LOGIC;
S1_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S1_AXI_WVALID : IN STD_LOGIC;
S1_AXI_WREADY : OUT STD_LOGIC;
S1_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_BVALID : OUT STD_LOGIC;
S1_AXI_BREADY : IN STD_LOGIC;
S1_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_ARVALID : IN STD_LOGIC;
S1_AXI_ARREADY : OUT STD_LOGIC;
S1_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S1_AXI_RVALID : OUT STD_LOGIC;
S1_AXI_RREADY : IN STD_LOGIC;
S2_AXI_ACLK : IN STD_LOGIC;
S2_AXI_ARESETN : IN STD_LOGIC;
S2_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_AWVALID : IN STD_LOGIC;
S2_AXI_AWREADY : OUT STD_LOGIC;
S2_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S2_AXI_WVALID : IN STD_LOGIC;
S2_AXI_WREADY : OUT STD_LOGIC;
S2_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_BVALID : OUT STD_LOGIC;
S2_AXI_BREADY : IN STD_LOGIC;
S2_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_ARVALID : IN STD_LOGIC;
S2_AXI_ARREADY : OUT STD_LOGIC;
S2_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S2_AXI_RVALID : OUT STD_LOGIC;
S2_AXI_RREADY : IN STD_LOGIC;
S3_AXI_ACLK : IN STD_LOGIC;
S3_AXI_ARESETN : IN STD_LOGIC;
S3_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_AWVALID : IN STD_LOGIC;
S3_AXI_AWREADY : OUT STD_LOGIC;
S3_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S3_AXI_WVALID : IN STD_LOGIC;
S3_AXI_WREADY : OUT STD_LOGIC;
S3_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S3_AXI_BVALID : OUT STD_LOGIC;
S3_AXI_BREADY : IN STD_LOGIC;
S3_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_ARVALID : IN STD_LOGIC;
S3_AXI_ARREADY : OUT STD_LOGIC;
S3_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S3_AXI_RVALID : OUT STD_LOGIC;
S3_AXI_RREADY : IN STD_LOGIC;
S4_AXI_ACLK : IN STD_LOGIC;
S4_AXI_ARESETN : IN STD_LOGIC;
S4_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_AWVALID : IN STD_LOGIC;
S4_AXI_AWREADY : OUT STD_LOGIC;
S4_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4_AXI_WVALID : IN STD_LOGIC;
S4_AXI_WREADY : OUT STD_LOGIC;
S4_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S4_AXI_BVALID : OUT STD_LOGIC;
S4_AXI_BREADY : IN STD_LOGIC;
S4_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_ARVALID : IN STD_LOGIC;
S4_AXI_ARREADY : OUT STD_LOGIC;
S4_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S4_AXI_RVALID : OUT STD_LOGIC;
S4_AXI_RREADY : IN STD_LOGIC;
S5_AXI_ACLK : IN STD_LOGIC;
S5_AXI_ARESETN : IN STD_LOGIC;
S5_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_AWVALID : IN STD_LOGIC;
S5_AXI_AWREADY : OUT STD_LOGIC;
S5_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S5_AXI_WVALID : IN STD_LOGIC;
S5_AXI_WREADY : OUT STD_LOGIC;
S5_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S5_AXI_BVALID : OUT STD_LOGIC;
S5_AXI_BREADY : IN STD_LOGIC;
S5_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_ARVALID : IN STD_LOGIC;
S5_AXI_ARREADY : OUT STD_LOGIC;
S5_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S5_AXI_RVALID : OUT STD_LOGIC;
S5_AXI_RREADY : IN STD_LOGIC;
S6_AXI_ACLK : IN STD_LOGIC;
S6_AXI_ARESETN : IN STD_LOGIC;
S6_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_AWVALID : IN STD_LOGIC;
S6_AXI_AWREADY : OUT STD_LOGIC;
S6_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S6_AXI_WVALID : IN STD_LOGIC;
S6_AXI_WREADY : OUT STD_LOGIC;
S6_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S6_AXI_BVALID : OUT STD_LOGIC;
S6_AXI_BREADY : IN STD_LOGIC;
S6_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_ARVALID : IN STD_LOGIC;
S6_AXI_ARREADY : OUT STD_LOGIC;
S6_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S6_AXI_RVALID : OUT STD_LOGIC;
S6_AXI_RREADY : IN STD_LOGIC;
S7_AXI_ACLK : IN STD_LOGIC;
S7_AXI_ARESETN : IN STD_LOGIC;
S7_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_AWVALID : IN STD_LOGIC;
S7_AXI_AWREADY : OUT STD_LOGIC;
S7_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S7_AXI_WVALID : IN STD_LOGIC;
S7_AXI_WREADY : OUT STD_LOGIC;
S7_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S7_AXI_BVALID : OUT STD_LOGIC;
S7_AXI_BREADY : IN STD_LOGIC;
S7_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_ARVALID : IN STD_LOGIC;
S7_AXI_ARREADY : OUT STD_LOGIC;
S7_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S7_AXI_RVALID : OUT STD_LOGIC;
S7_AXI_RREADY : IN STD_LOGIC
);
END COMPONENT mutex;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "mutex,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_mutex_0_0_arch : ARCHITECTURE IS "DemoInterconnect_mutex_0_0,mutex,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DemoInterconnect_mutex_0_0_arch: ARCHITECTURE IS "DemoInterconnect_mutex_0_0,mutex,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mutex,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_NUM_AXI=3,C_S0_AXI_BASEADDR=0x00100000,C_S0_AXI_HIGHADDR=0x0010FFFF,C_S0_AXI_ADDR_WIDTH=32,C_S0_AXI_DATA_WIDTH=32,C_S1_AXI_BASEADDR=0x00200000,C_S1_AXI_HIGHADDR=0x0020FFFF,C_S1_AXI_ADDR_WIDTH=32,C_S1_AXI_DATA_WIDTH=32,C_S2_AXI_BASEADDR=0x00300000,C_S2_AXI_HIGHADDR=0x0030FFFF,C_S2_AXI_ADDR_WIDTH" &
"=32,C_S2_AXI_DATA_WIDTH=32,C_S3_AXI_BASEADDR=0xFFFFFFFF,C_S3_AXI_HIGHADDR=0x00000000,C_S3_AXI_ADDR_WIDTH=32,C_S3_AXI_DATA_WIDTH=32,C_S4_AXI_BASEADDR=0xFFFFFFFF,C_S4_AXI_HIGHADDR=0x00000000,C_S4_AXI_ADDR_WIDTH=32,C_S4_AXI_DATA_WIDTH=32,C_S5_AXI_BASEADDR=0xFFFFFFFF,C_S5_AXI_HIGHADDR=0x00000000,C_S5_AXI_ADDR_WIDTH=32,C_S5_AXI_DATA_WIDTH=32,C_S6_AXI_BASEADDR=0xFFFFFFFF,C_S6_AXI_HIGHADDR=0x00000000,C_S6_AXI_ADDR_WIDTH=32,C_S6_AXI_DATA_WIDTH=32,C_S7_AXI_BASEADDR=0xFFFFFFFF,C_S7_AXI_HIGHADDR=0x00000000" &
",C_S7_AXI_ADDR_WIDTH=32,C_S7_AXI_DATA_WIDTH=32,C_ASYNC_CLKS=0,C_NUM_SYNC_FF=2,C_ENABLE_USER=1,C_OWNER_ID_WIDTH=8,C_ENABLE_HW_PROT=1,C_NUM_MUTEX=16}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S2_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S2_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S2_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S2_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S2_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S2_AXI_ACLK, ASSOCIATED_BUSIF S2_AXI, ASSOCIATED_RESET S2_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S2_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S2_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S1_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S1_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S1_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S1_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S1_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S1_AXI_ACLK, ASSOCIATED_BUSIF S1_AXI, ASSOCIATED_RESET S1_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S1_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S1_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_AWADDR: SIGNAL IS "XIL_INTERFACENAME S0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S0_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME RST.S0_AXI_ARESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.S0_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF S0_AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME CLK.S0_AXI_ACLK, ASSOCIATED_BUSIF S0_AXI, ASSOCIATED_RESET S0_AXI_ARESETN, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF S0_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.S0_AXI_ACLK CLK";
BEGIN
U0 : mutex
GENERIC MAP (
C_FAMILY => "artix7",
C_NUM_AXI => 3,
C_S0_AXI_BASEADDR => X"00100000",
C_S0_AXI_HIGHADDR => X"0010FFFF",
C_S0_AXI_ADDR_WIDTH => 32,
C_S0_AXI_DATA_WIDTH => 32,
C_S1_AXI_BASEADDR => X"00200000",
C_S1_AXI_HIGHADDR => X"0020FFFF",
C_S1_AXI_ADDR_WIDTH => 32,
C_S1_AXI_DATA_WIDTH => 32,
C_S2_AXI_BASEADDR => X"00300000",
C_S2_AXI_HIGHADDR => X"0030FFFF",
C_S2_AXI_ADDR_WIDTH => 32,
C_S2_AXI_DATA_WIDTH => 32,
C_S3_AXI_BASEADDR => X"FFFFFFFF",
C_S3_AXI_HIGHADDR => X"00000000",
C_S3_AXI_ADDR_WIDTH => 32,
C_S3_AXI_DATA_WIDTH => 32,
C_S4_AXI_BASEADDR => X"FFFFFFFF",
C_S4_AXI_HIGHADDR => X"00000000",
C_S4_AXI_ADDR_WIDTH => 32,
C_S4_AXI_DATA_WIDTH => 32,
C_S5_AXI_BASEADDR => X"FFFFFFFF",
C_S5_AXI_HIGHADDR => X"00000000",
C_S5_AXI_ADDR_WIDTH => 32,
C_S5_AXI_DATA_WIDTH => 32,
C_S6_AXI_BASEADDR => X"FFFFFFFF",
C_S6_AXI_HIGHADDR => X"00000000",
C_S6_AXI_ADDR_WIDTH => 32,
C_S6_AXI_DATA_WIDTH => 32,
C_S7_AXI_BASEADDR => X"FFFFFFFF",
C_S7_AXI_HIGHADDR => X"00000000",
C_S7_AXI_ADDR_WIDTH => 32,
C_S7_AXI_DATA_WIDTH => 32,
C_ASYNC_CLKS => 0,
C_NUM_SYNC_FF => 2,
C_ENABLE_USER => 1,
C_OWNER_ID_WIDTH => 8,
C_ENABLE_HW_PROT => 1,
C_NUM_MUTEX => 16
)
PORT MAP (
S0_AXI_ACLK => S0_AXI_ACLK,
S0_AXI_ARESETN => S0_AXI_ARESETN,
S0_AXI_AWADDR => S0_AXI_AWADDR,
S0_AXI_AWVALID => S0_AXI_AWVALID,
S0_AXI_AWREADY => S0_AXI_AWREADY,
S0_AXI_WDATA => S0_AXI_WDATA,
S0_AXI_WSTRB => S0_AXI_WSTRB,
S0_AXI_WVALID => S0_AXI_WVALID,
S0_AXI_WREADY => S0_AXI_WREADY,
S0_AXI_BRESP => S0_AXI_BRESP,
S0_AXI_BVALID => S0_AXI_BVALID,
S0_AXI_BREADY => S0_AXI_BREADY,
S0_AXI_ARADDR => S0_AXI_ARADDR,
S0_AXI_ARVALID => S0_AXI_ARVALID,
S0_AXI_ARREADY => S0_AXI_ARREADY,
S0_AXI_RDATA => S0_AXI_RDATA,
S0_AXI_RRESP => S0_AXI_RRESP,
S0_AXI_RVALID => S0_AXI_RVALID,
S0_AXI_RREADY => S0_AXI_RREADY,
S1_AXI_ACLK => S1_AXI_ACLK,
S1_AXI_ARESETN => S1_AXI_ARESETN,
S1_AXI_AWADDR => S1_AXI_AWADDR,
S1_AXI_AWVALID => S1_AXI_AWVALID,
S1_AXI_AWREADY => S1_AXI_AWREADY,
S1_AXI_WDATA => S1_AXI_WDATA,
S1_AXI_WSTRB => S1_AXI_WSTRB,
S1_AXI_WVALID => S1_AXI_WVALID,
S1_AXI_WREADY => S1_AXI_WREADY,
S1_AXI_BRESP => S1_AXI_BRESP,
S1_AXI_BVALID => S1_AXI_BVALID,
S1_AXI_BREADY => S1_AXI_BREADY,
S1_AXI_ARADDR => S1_AXI_ARADDR,
S1_AXI_ARVALID => S1_AXI_ARVALID,
S1_AXI_ARREADY => S1_AXI_ARREADY,
S1_AXI_RDATA => S1_AXI_RDATA,
S1_AXI_RRESP => S1_AXI_RRESP,
S1_AXI_RVALID => S1_AXI_RVALID,
S1_AXI_RREADY => S1_AXI_RREADY,
S2_AXI_ACLK => S2_AXI_ACLK,
S2_AXI_ARESETN => S2_AXI_ARESETN,
S2_AXI_AWADDR => S2_AXI_AWADDR,
S2_AXI_AWVALID => S2_AXI_AWVALID,
S2_AXI_AWREADY => S2_AXI_AWREADY,
S2_AXI_WDATA => S2_AXI_WDATA,
S2_AXI_WSTRB => S2_AXI_WSTRB,
S2_AXI_WVALID => S2_AXI_WVALID,
S2_AXI_WREADY => S2_AXI_WREADY,
S2_AXI_BRESP => S2_AXI_BRESP,
S2_AXI_BVALID => S2_AXI_BVALID,
S2_AXI_BREADY => S2_AXI_BREADY,
S2_AXI_ARADDR => S2_AXI_ARADDR,
S2_AXI_ARVALID => S2_AXI_ARVALID,
S2_AXI_ARREADY => S2_AXI_ARREADY,
S2_AXI_RDATA => S2_AXI_RDATA,
S2_AXI_RRESP => S2_AXI_RRESP,
S2_AXI_RVALID => S2_AXI_RVALID,
S2_AXI_RREADY => S2_AXI_RREADY,
S3_AXI_ACLK => '0',
S3_AXI_ARESETN => '0',
S3_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_AWVALID => '0',
S3_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S3_AXI_WVALID => '0',
S3_AXI_BREADY => '0',
S3_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXI_ARVALID => '0',
S3_AXI_RREADY => '0',
S4_AXI_ACLK => '0',
S4_AXI_ARESETN => '0',
S4_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_AWVALID => '0',
S4_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S4_AXI_WVALID => '0',
S4_AXI_BREADY => '0',
S4_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXI_ARVALID => '0',
S4_AXI_RREADY => '0',
S5_AXI_ACLK => '0',
S5_AXI_ARESETN => '0',
S5_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_AWVALID => '0',
S5_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S5_AXI_WVALID => '0',
S5_AXI_BREADY => '0',
S5_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXI_ARVALID => '0',
S5_AXI_RREADY => '0',
S6_AXI_ACLK => '0',
S6_AXI_ARESETN => '0',
S6_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_AWVALID => '0',
S6_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S6_AXI_WVALID => '0',
S6_AXI_BREADY => '0',
S6_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXI_ARVALID => '0',
S6_AXI_RREADY => '0',
S7_AXI_ACLK => '0',
S7_AXI_ARESETN => '0',
S7_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_AWVALID => '0',
S7_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S7_AXI_WVALID => '0',
S7_AXI_BREADY => '0',
S7_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXI_ARVALID => '0',
S7_AXI_RREADY => '0'
);
END DemoInterconnect_mutex_0_0_arch;
|
mit
|
47f8cd9321e1c271af01f3a79f4ce34c
| 0.669328 | 2.885131 | false | false | false | false |
andbet050197/IS773UTP
|
modulo3/ECO_TB.vhd
| 1 | 1,376 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ECO_TB IS
END ECO_TB;
ARCHITECTURE behavior OF ECO_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ECO
PORT(
Rx : IN std_logic;
Tx : OUT std_logic;
CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal Rx : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal Tx : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ECO PORT MAP (
Rx => Rx,
Tx => Tx,
CLK => CLK
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Rx <= '1';
wait for 10 ns;
wait for 156240 ns;
Rx <= '0';
wait for 104160 ns;
Rx <= '1';
wait for 104160 ns;
Rx <= '0';
wait for 104160 ns;
Rx <= '1';
wait for 104160 ns;
Rx <= '0';
wait for 104160 ns;
Rx <= '1';
wait for 104160 ns;
Rx <= '1';
wait for 104160 ns;
Rx <= '0';
wait for 104160 ns;
Rx <= '0';
wait for 104160 ns;
Rx <= '0';
wait for 104160 ns;
Rx <= '1';
wait for 104160 ns;
Rx <= '1';
wait;
end process;
END;
|
gpl-3.0
|
0bfb16e1a1dc4c8627ba3619e0d94521
| 0.539971 | 3.177829 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/hdl/DemoInterconnect_wrapper.vhd
| 1 | 3,387 |
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
--Date : Fri Nov 17 16:04:47 2017
--Host : egk-pc running 64-bit major release (build 9200)
--Command : generate_target DemoInterconnect_wrapper.bd
--Design : DemoInterconnect_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect_wrapper is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
end DemoInterconnect_wrapper;
architecture STRUCTURE of DemoInterconnect_wrapper is
component DemoInterconnect is
port (
LED0_pll_aclk : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
sys_clk : in STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
sys_reset : in STD_LOGIC
);
end component DemoInterconnect;
begin
DemoInterconnect_i: component DemoInterconnect
port map (
LED0_pll_aclk => LED0_pll_aclk,
LED1_pll_uart => LED1_pll_uart,
LED2_pll_lock => LED2_pll_lock,
UART_RX_0 => UART_RX_0,
UART_RX_1 => UART_RX_1,
UART_TX_0 => UART_TX_0,
UART_TX_1 => UART_TX_1,
m_spi_miso => m_spi_miso,
m_spi_miso_1 => m_spi_miso_1,
m_spi_miso_2 => m_spi_miso_2,
m_spi_miso_3 => m_spi_miso_3,
m_spi_mosi => m_spi_mosi,
m_spi_mosi_1 => m_spi_mosi_1,
m_spi_mosi_2 => m_spi_mosi_2,
m_spi_mosi_3 => m_spi_mosi_3,
m_spi_sclk => m_spi_sclk,
m_spi_sclk_1 => m_spi_sclk_1,
m_spi_sclk_2 => m_spi_sclk_2,
m_spi_sclk_3 => m_spi_sclk_3,
m_spi_ss => m_spi_ss,
m_spi_ss_1 => m_spi_ss_1,
m_spi_ss_2 => m_spi_ss_2,
m_spi_ss_3 => m_spi_ss_3,
sys_clk => sys_clk,
sys_reset => sys_reset
);
end STRUCTURE;
|
mit
|
2a0f8b1c38ea8f688fa8730b644a0ae1
| 0.569235 | 2.796862 | false | false | false | false |
andbet050197/IS773UTP
|
modulo1/Detectordepulso.vhd
| 1 | 1,531 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:32:17 02/15/2017
-- Design Name:
-- Module Name: Detectordepulso - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Detectordepulso is
Port ( Button : in STD_LOGIC; --boton
Clk : in STD_LOGIC; --reloj
S : out STD_LOGIC); --respuesta
end Detectordepulso;
architecture Behavioral of Detectordepulso is
signal cont: std_logic_vector (23 downto 0) := (others => '0'); -- variable contador alcanza un maximo de 262143 en 17 bits "11111111111111111"
begin
process (Clk)
begin
if rising_edge(Clk)then --subida de señal de reloj
S <= '0';
if ((Button = '1') or (cont > 0 and Button = '0')) then
if (cont < 10000000) then
cont <= cont + 1;
else
S <= '1';
cont <= (others => '0');
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
eb5d6d22fa948e646d5df5cd873f5cf8
| 0.590196 | 3.768473 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/src/SPI_Master.vhd
| 3 | 5,196 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spi_master is
generic(
DATA_WIDTH : integer := 8;
CLK_DIV : integer := 100 -- input clock divider to generate output serial clock; o_sclk frequency = i_clk/(2*CLK_DIV)
);
port(
--Out port
o_sclk : out std_logic := '1';
o_mosi : out std_logic := '1';
o_ss : out std_logic := '1';
o_tx_rx_busy : out std_logic := '0';
o_tx_rx_end : out std_logic := '0';
o_data_rx : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
--In port
i_miso : in std_logic := '0';
i_data_tx : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0'); -- data to send
--Control
i_clk : in std_logic := '0';
i_reset : in std_logic := '0';
i_tx_rx_start : in std_logic := '0' -- Start TX
);
end spi_master;
architecture behave_v2 of spi_master is
--control
signal spi_en : std_logic := '0';
signal spi_busy : std_logic := '0';
signal spi_done : std_logic := '0';
signal load_buffer : std_logic := '0';
signal buffer_ready : std_logic := '0';
--single buffer SPI
signal tx_rx_buffer : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'1');
signal load_buffer_val : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'1');
--counters
signal spi_bit_counter : integer range 0 to DATA_WIDTH := 0;
signal spi_clock_counter : integer range 0 to CLK_DIV := 0;
--I/O reg
signal mosi : std_logic := '1';
signal ss : std_logic := '1';
signal sclk : std_logic := '1';
begin
-- I/O Connections assignments
o_mosi <= mosi;
o_ss <= ss;
o_tx_rx_busy <= spi_busy;
o_tx_rx_end <= spi_done;
o_data_rx <= tx_rx_buffer;
p_gen_sclk: process(i_clk)
begin
if rising_edge(i_clk) then
if spi_clock_counter=CLK_DIV-1 then
spi_clock_counter <= 0;
sclk <= not(sclk);
if (ss='0' and spi_en='1') then
o_sclk <= sclk;
else
o_sclk <= '1';
end if;
else
spi_clock_counter <= spi_clock_counter + 1;
end if;
end if;
end process;
p_spi: process(i_clk)
begin
if rising_edge(i_clk) then
if (i_tx_rx_start='1') then
spi_busy <= '1'; --busy starts before 'spi_en' to signal the user request
load_buffer <= '1';
load_buffer_val <= i_data_tx;
else
if (buffer_ready = '1') then --after buffer is initialized
load_buffer <= '0'; --de-assert load buffer
spi_en <= '1'; --enable spi Tx-Rx
end if;
if (spi_done='1') then
spi_en <= '0';
end if;
if (load_buffer='0' and spi_done='0' and spi_en='0') then
spi_busy <= '0';
end if;
end if;
end if;
end process;
p_count: process(sclk)
begin
if rising_edge(sclk) then
if (spi_en='1') then
if (spi_bit_counter=DATA_WIDTH) then
spi_bit_counter <= 0;
spi_done <= '1';
else
spi_bit_counter <= spi_bit_counter + 1;
end if;
end if;
if (spi_done = '1') then
spi_done <= '0';
end if;
end if;
end process;
p_ss: process(sclk)
begin
if rising_edge(sclk) then
if (spi_en='1') then
ss <= '0'; --active LOW 'ss' is asserted on rising edge before data
else
ss <= '1';
end if;
end if;
end process;
p_tx_rx: process(sclk)
begin
if falling_edge(sclk) then
mosi <= '1';
if (load_buffer='1') then
tx_rx_buffer <= load_buffer_val; --load buffer in parallel with user data
buffer_ready <= '1';
elsif (ss='0' and spi_en='1') then
mosi <= tx_rx_buffer(DATA_WIDTH-1); --shift out TX MSB
tx_rx_buffer <= tx_rx_buffer(DATA_WIDTH-2 downto 0) & i_miso; --shift in RX MSB
end if;
if (buffer_ready = '1') then
buffer_ready <= '0'; --pulse buffer ready
end if;
end if;
end process;
end behave_v2;
|
mit
|
9b31a3ba5a4ca39b670837580c42a9b9
| 0.429561 | 4.009259 | false | false | false | false |
mariobarbareschi/vhdl_ci
|
src/mux4_1/mux4_1.vhd
| 1 | 960 |
--This file describes a mux4_1
--Mario Barbareschi
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_1 is
Port ( SEL : in STD_LOGIC_VECTOR(1 downto 0);
A : in STD_LOGIC_VECTOR(3 downto 0);
X : out STD_LOGIC
);
end mux4_1;
architecture structural of mux4_1 is
component mux2_1 is
Port(
SEL : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC
);
end component;
signal mux_out1, mux_out2 : std_logic := '0';
begin
inst_mux0: mux2_1 port map(
SEL => SEL(0),
A => A(0),
B => A(1),
X => mux_out1
);
inst_mux1: mux2_1 port map(
SEL => SEL(0),
A => A(2),
B => A(3),
X => mux_out2
);
inst_mux2: mux2_1 port map(
SEL => SEL(1),
A => mux_out1,
B => mux_out2,
X => x
);
end structural;
|
agpl-3.0
|
e95c0117a045e27c610d52f2e5b0cd3a
| 0.463542 | 3 | false | false | false | false |
andbet050197/IS773UTP
|
sumadorcompleto/SumadorCompleto.vhd
| 1 | 518 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SumadorCompleto is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC);
end SumadorCompleto;
architecture Behavioral of SumadorCompleto is
signal s1 : std_logic := '0';
signal co1 : std_logic := '0';
signal co2 : std_logic := '0';
begin
s1 <= a xor b;
co1 <= a and b;
s <= s1 xor cin;
co2 <= s1 and cin;
cout <= co2 xor co1;
end Behavioral;
|
gpl-3.0
|
8c74bfe70c15937f800f611bdd746608
| 0.579151 | 2.943182 | false | false | false | false |
dl3yc/sdr-fm
|
testing/vcordic-1.0/src/vcordic.vhd
| 1 | 2,240 |
-- VCORDIC module for Betty SDR
-- implements CORDIC in Vector Mode
-- file: vcordic.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with some test cases
-- - known bug: don't use the phase!
--
-- !!! because of the arctan table used in the CORDIC algorithm
-- !!! it only converges in the range of -99.7° to 99.7°
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of vcordic is
type alpha_t is array(0 to N-1) of signed(P-1 downto 0); -- -180°..180°
type xy_vector is array(natural range <>) of signed(A+2 downto 0); -- -3.999..+3.999
type z_vector is array(natural range <>) of signed(P-1 downto 0); -- -180°..180°
constant K : signed(A-1 downto 0) := to_signed(integer(0.6073*2**(A-1)),A);
signal alpha : alpha_t;
signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
signal z : z_vector(N downto 0) := (others => (others => '0'));
begin
table: for i in 0 to N-1 generate
alpha(i) <= to_signed(integer( atan(1.0/real(2**i)) * (real(2**(P-1))-1.0) / math_pi ),P);
end generate;
process begin
wait until rising_edge(clk);
if i >= 0 then
x(0) <= resize(i,A+3);
y(0) <= resize(q,A+3);
z(0) <= (others => '0');
elsif q >= 0 then
x(0) <= resize(q,A+3);
y(0) <= resize(-i,A+3);
z(0) <= to_signed(2**(P-2),P);-- 90°
else
x(0) <= resize(-q,A+3);
y(0) <= resize(i,A+3);
z(0) <= to_signed(-2**(P-2),P);-- -90°
end if;
for i in 1 to N loop
if x(i-1) >= 0 then
x(i) <= x(i-1) - y(i-1) / 2**(i-1);
y(i) <= y(i-1) + x(i-1) / 2**(i-1);
z(i) <= z(i-1) + alpha(i-1);
else
x(i) <= x(i-1) + y(i-1) / 2**(i-1);
y(i) <= y(i-1) - x(i-1) / 2**(i-1);
z(i) <= z(i-1) - alpha(i-1);
end if;
end loop;
amp <= resize(unsigned(shift_right((y(N) * K), (A-1))),A);
phi <= z(N);
end process;
end behavioral;
|
gpl-2.0
|
b3aac9e79211aa65bf10bbe5f07caf99
| 0.562724 | 2.387166 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/testGeneradorAleatorio.vhd
| 1 | 2,662 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:09:45 11/02/2011
-- Design Name:
-- Module Name: /home/cvargasc/Documentos/Uniandes/201120/Fundamentos de Sistemas Digitales/Laboratorios/practica7/practica7/testGeneradorAleatorio.vhd
-- Project Name: practica7
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: generadorAleatorio
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testGeneradorAleatorio IS
END testGeneradorAleatorio;
ARCHITECTURE behavior OF testGeneradorAleatorio IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT generadorAleatorio
PORT(
clk : IN std_logic;
reset : IN std_logic;
derecha : IN std_logic;
izquierda : IN std_logic;
inicioOut : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal derecha : std_logic := '0';
signal izquierda : std_logic := '0';
--Outputs
signal inicioOut : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: generadorAleatorio PORT MAP (
clk => clk,
reset => reset,
derecha => derecha,
izquierda => izquierda,
inicioOut => inicioOut
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period*3;
reset <= '0';
wait for clk_period*3;
derecha <= '1';
wait for clk_period*6;
derecha <= '0';
wait for clk_period*20;
izquierda <= '1';
wait for clk_period*6;
izquierda <= '0';
end process;
END;
|
gpl-2.0
|
b66e11c9202ca63c56c464b5e57d67d4
| 0.612697 | 3.98503 | false | true | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_internoc_ni_axi_master_0_0/sim/DemoInterconnect_internoc_ni_axi_master_0_0.vhd
| 2 | 10,681 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: e.kyriakakis:user:internoc_ni_axi_master:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_internoc_ni_axi_master_0_0 IS
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_internoc_ni_axi_master_0_0;
ARCHITECTURE DemoInterconnect_internoc_ni_axi_master_0_0_arch OF DemoInterconnect_internoc_ni_axi_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_internoc_ni_axi_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT internoc_ni_axi_master_v1_0 IS
GENERIC (
C_IF00_DATA_WIDTH : INTEGER;
C_PACKET_WIDTH : INTEGER;
C_PACKET_DATA_WIDTH : INTEGER;
C_PACKET_CTRL_WIDTH : INTEGER;
C_PACKET_ADDR_WIDTH : INTEGER;
C_AXI_PACKET_ADDR_OFFSET : INTEGER;
C_M00_AXI_ADDR_WIDTH : INTEGER;
C_M00_SELF_ADDR : INTEGER;
C_TIMEOUT_PERIOD : INTEGER
);
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT internoc_ni_axi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXI_RST RST, xilinx.com:signal:reset:1.0 m00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXI_CLK, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 m00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME M00_AXI, WIZ_DATA_WIDTH 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
BEGIN
U0 : internoc_ni_axi_master_v1_0
GENERIC MAP (
C_IF00_DATA_WIDTH => 8,
C_PACKET_WIDTH => 40,
C_PACKET_DATA_WIDTH => 32,
C_PACKET_CTRL_WIDTH => 3,
C_PACKET_ADDR_WIDTH => 5,
C_AXI_PACKET_ADDR_OFFSET => 16,
C_M00_AXI_ADDR_WIDTH => 32,
C_M00_SELF_ADDR => 16,
C_TIMEOUT_PERIOD => 16383
)
PORT MAP (
if00_data_in => if00_data_in,
if00_load_in => if00_load_in,
if00_data_out => if00_data_out,
if00_load_out => if00_load_out,
if00_send_done => if00_send_done,
if00_send_busy => if00_send_busy,
m00_axi_awaddr => m00_axi_awaddr,
m00_axi_awprot => m00_axi_awprot,
m00_axi_awvalid => m00_axi_awvalid,
m00_axi_awready => m00_axi_awready,
m00_axi_wdata => m00_axi_wdata,
m00_axi_wstrb => m00_axi_wstrb,
m00_axi_wvalid => m00_axi_wvalid,
m00_axi_wready => m00_axi_wready,
m00_axi_bresp => m00_axi_bresp,
m00_axi_bvalid => m00_axi_bvalid,
m00_axi_bready => m00_axi_bready,
m00_axi_araddr => m00_axi_araddr,
m00_axi_arprot => m00_axi_arprot,
m00_axi_arvalid => m00_axi_arvalid,
m00_axi_arready => m00_axi_arready,
m00_axi_rdata => m00_axi_rdata,
m00_axi_rresp => m00_axi_rresp,
m00_axi_rvalid => m00_axi_rvalid,
m00_axi_rready => m00_axi_rready,
m00_axi_aclk => m00_axi_aclk,
m00_axi_aresetn => m00_axi_aresetn
);
END DemoInterconnect_internoc_ni_axi_master_0_0_arch;
|
mit
|
78c288bf4ed03026af6c6a1d555205d0
| 0.705458 | 3.188358 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/neander.vhd
| 1 | 8,777 |
-- Author: Ronaldo Dall'Agnol Veiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ramses is
Port ( clk_in : IN std_logic;
rst_in : IN std_logic;
enable_ramses : IN std_logic;
debug_out : OUT std_logic);
end ramses;
architecture Behavioral of ramses is
component PC_register is
port (
clk_in : in std_logic;
rst_in : in std_logic;
cargaPC_i : in std_logic;
incPC_i : in std_logic;
pc_data_i : in std_logic_vector(7 downto 0);
pc_data_o : out std_logic_vector(7 downto 0)
);
end component;
component control_unit is
Port ( clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
enable_ramses : in STD_LOGIC;
--NZC : in STD_LOGIC_VECTOR (2 downto 0);
N : in STD_LOGIC;
Z : in STD_LOGIC;
C : in STD_LOGIC;
decod_instr : in STD_LOGIC_VECTOR (3 downto 0);
reg_type : in STD_LOGIC_VECTOR (1 downto 0);
address_mode: in STD_LOGIC_VECTOR (1 downto 0);
--outputs--
--seletor de operacao
sel_ula : out STD_LOGIC_VECTOR(3 downto 0);
--carga dos regs
loadRX : out STD_LOGIC;
loadRA : out STD_LOGIC;
loadRB : out STD_LOGIC;
loadPC : out STD_LOGIC;
loadREM : out STD_LOGIC;
loadRDM : out STD_LOGIC;
--loadNZC : out STD_LOGIC_VECTOR(2 downto 0);
loadN : out STD_LOGIC;
loadZ : out STD_LOGIC;
loadC : out STD_LOGIC;
loadRI : out STD_LOGIC;
--write da mem (nao tem read_en)
wr_enable_mem : out STD_LOGIC_VECTOR (0 downto 0);
--seletor de mux da arq do livro
s1s2 : out STD_LOGIC_VECTOR(1 downto 0);
s3s4 : out STD_LOGIC_VECTOR(1 downto 0);
s5 : out STD_LOGIC;
-- incremento do PC
PC_inc : out STD_LOGIC;
-- seletor do mux2to1 extra para RDM
sel_mux_RDM : out STD_LOGIC;
stop : out STD_LOGIC
);
end component;
component decoder is
Port ( instruction_in : in STD_LOGIC_VECTOR (7 downto 0);
decod_instr : out STD_LOGIC_VECTOR(3 downto 0);
reg_type : out STD_LOGIC_VECTOR(1 downto 0);
address_mode : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component memoria is
port (
addra : in STD_LOGIC_VECTOR (7 downto 0);
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR (7 downto 0);
douta : out STD_LOGIC_VECTOR (7 downto 0);
wea : in STD_LOGIC_VECTOR (0 downto 0)
);
end component;
component mux2to1 is
port (
mux_data1_i : in std_logic_vector(7 downto 0);
mux_data2_i : in std_logic_vector(7 downto 0);
mux2_sel_i : in std_logic;
mux_data_o : out std_logic_vector(7 downto 0)
);
end component;
component reg1bit is
Port ( data_in : in STD_LOGIC;
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
load : in STD_LOGIC;
data_out : out STD_LOGIC
);
end component;
component reg8bits is
Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0);
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
load : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component ula is
Port ( X : in STD_LOGIC_VECTOR (7 downto 0);
Y : in STD_LOGIC_VECTOR (7 downto 0);
sel_ula : in STD_LOGIC_VECTOR (3 downto 0);
--NZC : out STD_LOGIC_VECTOR (2 downto 0);
N : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC;
ula_output : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
--sinais
signal loadRA_s : STD_LOGIC;
signal loadRB_s : STD_LOGIC;
signal loadRX_s : STD_LOGIC;
signal loadPC_s : STD_LOGIC;
signal loadRDM_s : STD_LOGIC;
signal loadREM_s : STD_LOGIC;
signal loadRI_s : STD_LOGIC;
signal PC_inc_s : STD_LOGIC;
signal RAdata_out_s : STD_LOGIC_VECTOR (7 downto 0);
signal RBdata_out_s : STD_LOGIC_VECTOR (7 downto 0);
signal RXdata_out_s : STD_LOGIC_VECTOR (7 downto 0);
signal REMdata_in_s : STD_LOGIC_VECTOR (7 downto 0);
signal REMdata_out_s : STD_LOGIC_VECTOR (7 downto 0);
signal RDMdata_in_s : STD_LOGIC_VECTOR (7 downto 0);
signal RDMdata_out_s : STD_LOGIC_VECTOR (7 downto 0);
signal PCdata_in_s : STD_LOGIC_VECTOR (7 downto 0);
signal PCdata_out_s : STD_LOGIC_VECTOR (7 downto 0);
signal N_reg_s : STD_LOGIC; -- saem do registrador e vo pra unidade de controle
signal Z_reg_s : STD_LOGIC;
signal C_reg_s : STD_LOGIC;
signal N_s : STD_LOGIC; -- saem da ula e vo pro registrador de flag
signal Z_s : STD_LOGIC;
signal C_s : STD_LOGIC;
signal loadN_s :STD_LOGIC;
signal loadZ_s :STD_LOGIC;
signal loadC_s :STD_LOGIC;
signal decod_instr_s : STD_LOGIC_VECTOR (3 downto 0);
signal instruction_s : STD_LOGIC_VECTOR (7 downto 0);
signal reg_type_s : STD_LOGIC_VECTOR (1 downto 0);
signal address_mode_s : STD_LOGIC_VECTOR (1 downto 0);
signal wr_enable_mem_s : STD_LOGIC_VECTOR (0 downto 0);
signal s1s2_s : STD_LOGIC_VECTOR(1 downto 0);
signal s3s4_s : STD_LOGIC_VECTOR(1 downto 0);
signal s5_s : STD_LOGIC;
signal sel_mux_RDM_s : STD_LOGIC;
signal X_s : STD_LOGIC_VECTOR (7 downto 0);
signal sel_ula_s : STD_LOGIC_VECTOR (3 downto 0);
signal ula_output_s : STD_LOGIC_VECTOR (7 downto 0);
signal MEMdata_out_s : STD_LOGIC_VECTOR (7 downto 0);
signal stop_s : STD_LOGIC;
begin
control_unit_0 : control_unit
Port map (
clk_in => clk_in,
rst_in => rst_in,
enable_ramses => enable_ramses,
--NZC : in STD_LOGIC_VECTOR (2 downto 0);
N => N_reg_s,
Z => Z_reg_s,
C => C_reg_s,
decod_instr => decod_instr_s,
reg_type => reg_type_s,
address_mode => address_mode_s,
--outputs--
--seletor de operacao
sel_ula => sel_ula_s,
--carga dos regs
loadRX => loadRX_s,
loadRA => loadRA_s,
loadRB => loadRB_s,
loadPC => loadPC_s,
loadREM => loadREM_s,
loadRDM => loadRDM_s,
--loadNZC : out STD_LOGIC_VECTOR(2 downto 0);
loadN => loadN_s,
loadZ => loadZ_s,
loadC => loadC_s,
loadRI => loadRI_s,
--write da mem (nao tem read_en)
wr_enable_mem => wr_enable_mem_s,
--seletor de mux da arq do livro
s1s2 => s1s2_s,
s3s4 => s3s4_s,
s5 => s5_s,
-- incremento do PC
PC_inc => PC_inc_s,
-- seletor do mux2to1 extra para RDM
sel_mux_RDM => sel_mux_RDM_s,
stop => stop_s
);
N_flag : reg1bit
Port map (
data_in => N_s,
clk_in => clk_in,
rst_in => rst_in,
load => loadN_s,
data_out => N_reg_s
);
Z_flag : reg1bit
Port map (
data_in => Z_s,
clk_in => clk_in,
rst_in => rst_in,
load => loadN_s,
data_out => Z_reg_s
);
decoder_0 : decoder
Port map (
instruction_in => instruction_s,
decod_instr => decod_instr_s,
reg_type => reg_type_s,
address_mode => address_mode_s
);
ula_0 : ula
Port map (
X => X_s,
Y => RDMdata_out_s,
sel_ula => sel_ula_s,
N => N_s,
Z => Z_s,
C => C_s,
ula_output => ula_output_s
);
REM_0 : reg8bits
port map (
data_in => REMdata_in_s,
clk_in => clk_in,
rst_in => rst_in,
load => loadREM_s,
data_out => REMdata_out_s
);
RDM_0 : reg8bits
port map (
data_in => RDMdata_in_s,
clk_in => clk_in,
rst_in => rst_in,
load => loadRDM_s,
data_out => RDMdata_out_s
);
RI_0 : reg8bits
port map (
data_in => RDMdata_out_s,
clk_in => clk_in,
rst_in => rst_in,
load => loadRI_s,
data_out => instruction_s
);
PC_0 : PC_register
port map (
clk_in => clk_in,
rst_in => rst_in,
cargaPC_i => loadPC_s,
incPC_i => PC_inc_s,
pc_data_i => PCdata_in_s,
pc_data_o => PCdata_out_s
);
mux_s5 : mux2to1
port map (
mux_data1_i => ula_output_s,
mux_data2_i => REMdata_out_s,
mux2_sel_i => s5_s,
mux_data_o => PCdata_in_s
);
mux_RDM : mux2to1 --mux extra para selecionar entrada no RDM
port map (
mux_data1_i => MEMdata_out_s,
mux_data2_i => X_s,
mux2_sel_i => sel_mux_RDM_s,
mux_data_o => RDMdata_in_s
);
memoriaRamses : memoria
port map (
addra => REMdata_out_s,
clka => clk_in,
dina => RDMdata_out_s,
douta => MEMdata_out_s,
wea => wr_enable_mem_s
);
debug_out <= stop_s;
end Behavioral;
|
mit
|
a2a26110fe96f54029ba74564c671448
| 0.588148 | 2.609277 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_uart_transceiver_0_1/synth/DemoInterconnect_uart_transceiver_0_1.vhd
| 1 | 4,632 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr:user:uart_transceiver:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_uart_transceiver_0_1 IS
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END DemoInterconnect_uart_transceiver_0_1;
ARCHITECTURE DemoInterconnect_uart_transceiver_0_1_arch OF DemoInterconnect_uart_transceiver_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_uart_transceiver_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT uart_top IS
GENERIC (
CLK_FREQ : INTEGER;
BAUD_RATE : INTEGER
);
PORT (
i_Clk : IN STD_LOGIC;
i_RX_Serial : IN STD_LOGIC;
o_RX_Done : OUT STD_LOGIC;
o_RX_Byte : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i_TX_Load : IN STD_LOGIC;
i_TX_Byte : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o_TX_Active : OUT STD_LOGIC;
o_TX_Serial : OUT STD_LOGIC;
o_TX_Done : OUT STD_LOGIC
);
END COMPONENT uart_top;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_uart_transceiver_0_1_arch: ARCHITECTURE IS "uart_top,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_uart_transceiver_0_1_arch : ARCHITECTURE IS "DemoInterconnect_uart_transceiver_0_1,uart_top,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF i_Clk: SIGNAL IS "XIL_INTERFACENAME i_Clk, FREQ_HZ 12000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1";
ATTRIBUTE X_INTERFACE_INFO OF i_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 i_Clk CLK";
BEGIN
U0 : uart_top
GENERIC MAP (
CLK_FREQ => 12000000,
BAUD_RATE => 115200
)
PORT MAP (
i_Clk => i_Clk,
i_RX_Serial => i_RX_Serial,
o_RX_Done => o_RX_Done,
o_RX_Byte => o_RX_Byte,
i_TX_Load => i_TX_Load,
i_TX_Byte => i_TX_Byte,
o_TX_Active => o_TX_Active,
o_TX_Serial => o_TX_Serial,
o_TX_Done => o_TX_Done
);
END DemoInterconnect_uart_transceiver_0_1_arch;
|
mit
|
f93d4ff7fbe876a14205e32026c0b2e8
| 0.711356 | 3.732474 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/procesoJugador.vhd
| 1 | 2,504 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:37:51 10/29/2011
-- Design Name:
-- Module Name: procesoJugador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity procesoJugador is
Port( reset : in STD_LOGIC;
clk : in STD_LOGIC;
derecha : in STD_LOGIC;
izquierda : in STD_LOGIC;
filasOut : out STD_LOGIC_VECTOR (7 downto 0);
columnasOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end procesoJugador;
architecture Behavioral of procesoJugador is
type estados is (listo,der,izq,presionado);
signal estado : estados;
signal filas : STD_LOGIC_VECTOR (7 downto 0);
signal columnas: STD_LOGIC_VECTOR (7 downto 0);
begin
process(reset,clk,estado,filas,columnas)
begin
if reset='1' then
columnas <= "00001000";
filas <= "10000000";
elsif clk'event and clk = '1' then
case estado is
when der =>
columnas(7) <= columnas(0);
columnas(6 downto 0) <= columnas(7 downto 1);
when izq =>
columnas(7 downto 1) <= columnas(6 downto 0);
columnas(0) <= columnas(7);
when others =>
columnas <= columnas;
end case;
end if;
end process;
process(reset,clk,estado,derecha,izquierda)
begin
if reset = '1' then
estado <= listo;
elsif clk'event and clk = '1' then
if estado = listo and derecha = '1' then
estado <= der;
elsif estado = listo and izquierda = '1' then
estado <= izq;
elsif estado = izq or estado = der then
estado <= presionado;
elsif estado = presionado and izquierda = '0' and derecha = '0' then
estado <= listo;
end if;
end if;
end process;
process(reset,clk,filas,columnas)
begin
if reset = '1' then
filasOut <= "10000000";
columnasOut <= "00001000";
elsif clk'event and clk = '1' then
filasOut <= filas;
columnasOut <= columnas;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
1572d928d39714082101f0356f793973
| 0.621805 | 3.420765 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Encoder.vhd
| 1 | 642 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.HammingPack16.all;
use work.PhoenixPackage.all;
entity HAM_ENC is
port
(
data_in : in regflit; -- data input
data_out : out reghamm -- data output
);
end HAM_ENC;
architecture HAM_ENC of HAM_ENC is
signal P : Std_logic_vector(5 downto 1); --Hamming bits
begin
P(1) <= xor_reduce(data_in and MaskP1);
P(2) <= xor_reduce(data_in and MaskP2);
P(3) <= xor_reduce(data_in and MaskP4);
P(4) <= xor_reduce(data_in and MaskP8);
P(5) <= xor_reduce(data_in and MaskP16);
data_out <= P & xor_reduce(P & data_in);
end HAM_ENC;
|
lgpl-3.0
|
daf3350e2270240fd0e649916453a190
| 0.655763 | 2.708861 | false | false | false | false |
mosass/HexapodRobot
|
VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/sim/design_1_axi_gpio_0_0.vhd
| 1 | 8,880 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_1_axi_gpio_0_0;
ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 4,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => gpio2_io_i
);
END design_1_axi_gpio_0_0_arch;
|
mit
|
f7fc4d2d0962946a08ddd191cc0d19f0
| 0.679842 | 3.227917 | false | false | false | false |
dl3yc/sdr-fm
|
dev/bdd/bdd.vhd
| 1 | 1,184 |
-- BDD module for Betty SDR
-- implements a baseband differentiator demodulator
-- heavily based on Jes Toft Kristensen "FM radio receiver"
-- file: bsd.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bdd is
port (
clk : in std_logic;
stb : in std_logic;
i : in signed(26 downto 0);
q : in signed(26 downto 0);
demod : out signed(26 downto 0);
rdy : out std_logic
);
end entity bdd;
architecture rtl of bdd is
signal i_d: signed(26 downto 0);
signal q_d: signed(26 downto 0);
signal i_dt : signed(26 downto 0);
signal q_dt : signed(26 downto 0);
signal i_p : signed(53 downto 0);
signal q_p : signed(53 downto 0);
signal stb_d : std_logic_vector(1 downto 0);
begin
process
begin
wait until rising_edge(clk);
if stb = '1' then
i_d <= i;
q_d <= q;
i_dt <= i - i_d;
q_dt <= q - q_d;
end if;
i_p <= q_d * i_dt;
q_p <= i_d * q_dt;
demod <= q_p(53 downto 27) - i_p(53 downto 27);
stb_d(0) <= stb;
stb_d(1) <= stb_d(0);
rdy <= stb_d(1);
end process;
end architecture rtl;
|
gpl-2.0
|
0eb5bef3d0178c72e0ca0b88ef441c82
| 0.624155 | 2.49789 | false | false | false | false |
rmilfont/Phoenix
|
NoC/HammingPack16.vhd
| 1 | 2,698 |
library ieee;
use ieee.std_logic_1164.all;
use work.PhoenixPackage.all;
package HammingPack16 is
--define sizes and types
--constant TAM_FLIT : integer range 1 to 64 := 16;
constant TAM_HAMM : integer range 1 to 64 := 6;
constant TAM_PHIT : integer range 1 to 64 := TAM_FLIT + TAM_HAMM;
constant HAMM_NPORT: integer := 4; -- 4 portas (EAST,WEST,NORTH,SOUTH)
constant COUNTERS_SIZE: integer := 5; -- 5 bits cada contador
subtype reghamm is std_logic_vector((TAM_HAMM-1) downto 0);
subtype regphit is std_logic_vector((TAM_PHIT-1) downto 0);
subtype regHamm_Nport is std_logic_vector((HAMM_NPORT-1) downto 0);
subtype row_FaultTable is std_logic_vector((3*COUNTERS_SIZE+1) downto 0);
type row_FaultTable_Ports is array ((HAMM_NPORT-1) downto 0) of row_FaultTable;
type row_FaultTable_Nport_Ports is array ((NPORT-1) downto 0) of row_FaultTable_Ports;
type array_statusHamming is array ((HAMM_NPORT-1) downto 0) of reg3;
type arrayNport_regphit is array ((NPORT-1) downto 0) of regphit;
type arrayNrot_regphit is array ((NROT-1) downto 0) of regphit;
type matrixNrot_Nport_regphit is array((NROT-1) downto 0) of arrayNport_regphit; -- a -- array(NROT)(NPORT)(TAM_FLIT)
type arrayNport_reghamm is array((NPORT-1) downto 0) of reghamm;
type arrayNrot_reghamm is array((NROT-1) downto 0) of reghamm;
type matrixNrot_Nport_reghamm is array((NROT-1) downto 0) of arrayNport_reghamm; -- a -- array(NROT)(NPORT)(TAM_FLIT)
--define maks to select bits to xor for each parity
constant MaskP1 : std_logic_vector(15 downto 0) := "1010110101011011";
constant MaskP2 : std_logic_vector(15 downto 0) := "0011011001101101";
constant MaskP4 : std_logic_vector(15 downto 0) := "1100011110001110";
constant MaskP8 : std_logic_vector(15 downto 0) := "0000011111110000";
constant MaskP16 : std_logic_vector(15 downto 0) := "1111100000000000";
constant NE: std_logic_vector (2 downto 0) := "101"; -- no error
constant EC: std_logic_vector (2 downto 0) := "011"; -- error corrected
constant ED: std_logic_vector (2 downto 0) := "111"; -- error detected
constant BF: std_logic_vector (2 downto 0) := "000"; -- "stand by" or buffer full
--function to exclusive-OR all the bits in a std_logic_vector
function xor_reduce(arg : std_logic_vector) return std_logic;
end HammingPack16;
package body HammingPack16 is
--function to exclusive-OR all the bits in a std_logic_vector
function xor_reduce(arg : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for b in arg'range loop
result := result xor arg(b);
end loop;
return result;
end function xor_reduce;
end HammingPack16;
|
lgpl-3.0
|
2cc091a66a257ca456667cbf9df0769f
| 0.709414 | 3.266344 | false | false | false | false |
inforichland/freezing-spice
|
src/dpram.vhd
| 1 | 2,666 |
-- Based on the Quartus II VHDL Template for True Dual-Port RAM with single clock
-- Read-during-write on port A or B returns newly written data
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_textio.all;
use work.std_logic_textio.all;
use std.textio.all;
entity dpram is
generic(g_data_width : natural := 16;
g_addr_width : natural := 10;
g_init : boolean := false;
g_init_file : string := "");
port(clk : in std_logic;
addr_a : in std_logic_vector(g_addr_width-1 downto 0);
addr_b : in std_logic_vector(g_addr_width-1 downto 0);
data_a : in std_logic_vector((g_data_width-1) downto 0);
data_b : in std_logic_vector((g_data_width-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((g_data_width -1) downto 0);
q_b : out std_logic_vector((g_data_width -1) downto 0));
end dpram;
architecture rtl of dpram is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((g_data_width-1) downto 0);
type ram_t is array(0 to 2**g_addr_width-1) of word_t;
-- function to initialize the RAM from a file
impure function init_ram(fn : in string) return ram_t is
file f : text;
variable l : line;
variable ram : ram_t;
begin
if g_init = true then
file_open(f, fn, READ_MODE);
for i in ram_t'range loop
readline(f, l);
read(l, ram(i));
end loop;
file_close(f);
else
ram := (others => (others => '0'));
end if;
return ram;
end function;
-- Declare the RAM
shared variable ram : ram_t := init_ram(g_init_file); --(others => (others => '0'));
begin
-- Port A
process (clk)
variable addr : natural range 0 to 2**g_addr_width-1;
begin
if (rising_edge(clk)) then
addr := to_integer(unsigned(addr_a));
if (we_a = '1') then
ram(addr) := data_a;
end if;
q_a <= ram(addr);
end if;
end process;
-- Port B
process (clk)
variable addr : natural range 0 to 2**g_addr_width-1;
begin
if (rising_edge(clk)) then
addr := to_integer(unsigned(addr_b));
if (we_b = '1') then
ram(addr) := data_b;
end if;
q_b <= ram(addr);
end if;
end process;
end rtl;
|
bsd-3-clause
|
615bc13853d9e458d0323a505bbded6c
| 0.514629 | 3.457847 | false | false | false | false |
andbet050197/IS773UTP
|
modulo3/Tx.vhd
| 1 | 2,014 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Tx is
Port ( Campana : in STD_LOGIC;
CLK : in STD_LOGIC;
Dato_entrada : in STD_LOGIC_VECTOR (7 downto 0);
Dato_salida : out STD_LOGIC);
end Tx;
architecture Behavioral of Tx is
COMPONENT Divisor
PORT(
clk : IN std_logic;
newC : OUT std_logic
);
END COMPONENT;
signal reloj_baudios : std_logic := '0';
signal estado : std_logic_vector(1 downto 0) := "00";
-- 00 -> Salida Idle
-- 01 -> Envio de dato
-- 10 -> Envio de bit de paridad
-- 11 -> Envio de bits de parada
signal contador_de_bits : std_logic_vector(3 downto 0) := "0000";
signal Paridad : std_logic := '0';
signal aux : std_logic := '1'; -- inicializar la salida en '1', en idle.
begin
Inst_Divisor: Divisor PORT MAP(
clk => CLK,
newC => reloj_baudios
);
Dato_salida <= aux;
process (CLK)
variable Dato_temporal : std_logic_vector(7 downto 0) := (others => '0');
begin
if (rising_edge(CLK) and reloj_baudios = '1') then
if (estado = "00") then
aux <= '1';
if (Campana = '1') then
Dato_temporal := Dato_entrada;
estado <= "01";
aux <= '0';
end if;
elsif (estado = "01") then
if (Dato_temporal(0) = '1') then
Paridad <= not Paridad;
end if;
aux <= Dato_temporal(0);
Dato_temporal := '0' & Dato_temporal(7 downto 1);
contador_de_bits <= contador_de_bits + 1;
if (contador_de_bits >= "0111") then
contador_de_bits <= (others => '0');
estado <= "10";
end if;
elsif (estado = "10") then
aux <= Paridad;
estado <= "11";
elsif (estado = "11") then
if (contador_de_bits = "0001") then
estado <= "00";
contador_de_bits <= (others => '0');
aux <= '1';
Paridad <= '0';
else
aux <= '1';
contador_de_bits <= contador_de_bits + 1;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
e0f50d06b9914af9a9be9c4f85c60264
| 0.555611 | 3.024024 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Phoenix_switchcontrol.vhd
| 1 | 15,000 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.PhoenixPackage.all;
use work.HammingPack16.all;
entity SwitchControl is
generic(address : regmetadeflit := (others=>'0'));
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport; -- solicitacoes de chaveamento
ack_h : out regNport; -- resposta para as solitacoes de chaveamento
data : in arrayNport_regflit; -- dado do buffer (contem o endereco destino)
c_ctrl : in std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_CodControle : in regflit; -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
c_BuffCtrl : in buffControl; -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
c_buffTabelaFalhas_in: in row_FaultTable_Nport_Ports;
c_ce : in std_logic; -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
c_ceTF_in : in regNport; -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_dir: out regNport; -- indica qual direcao/porta de saida o pacote sera encaminhado
c_error_ArrayFind: out ArrayRouterControl; -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_tabelaFalhas : out row_FaultTable_Ports; -- tabela de falhas atualizada/final
c_strLinkTst : in regNport; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links
c_faultTableFDM : in regNPort; -- tabela de falhas gerado pelo teste de links
sender : in regNport;
free : out regNport; -- portas de saida que estao livres
mux_in : out arrayNport_reg3;
mux_out : out arrayNport_reg3;
row_FaultTablePorts_in: in row_FaultTable_Ports; -- linhas a serem escritas na tabela (do FFPM)
write_FaultTable: in regHamm_Nport); -- sinal para indicar escrita na tabela (do FPPM)
end SwitchControl;
architecture RoutingTable of SwitchControl is
type state is (S0,S1,S2,S3,S4,S5,S6,S7);
signal ES, PES: state;
-- sinais do arbitro
signal ask: std_logic := '0';
signal sel,prox: integer range 0 to (NPORT-1) := 0;
signal incoming: reg3 := (others=> '0');
signal header : regflit := (others=> '0');
-- sinais do controle
signal indice_dir: integer range 0 to (NPORT-1) := 0;
signal tx,ty: regquartoflit := (others=> '0');
signal auxfree: regNport := (others=> '0');
signal source: arrayNport_reg3 := (others=> (others=> '0'));
signal sender_ant: regNport := (others=> '0');
signal dir: std_logic_vector(NPORT-1 downto 0):= (others=> '0');
-- sinais de controle da tabela
signal find: RouterControl;
signal ceTable: std_logic := '0';
-- sinais de controle de atualizacao da tabela de falhas
signal c_ceTF : std_logic := '0';
signal c_buffTabelaFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
--sinais da Tabela de Falhas
signal tabelaDeFalhas : row_FaultTable_Ports := (others=>(others=>'0'));
signal c_checked: regNPort:= (others=>'0');
signal c_checkedArray: arrayRegNport :=(others=>(others=>'0'));
signal dirBuff : std_logic_vector(NPORT-1 downto 0):= (others=> '0');
signal strLinkTstAll : std_logic := '0';
signal ant_c_ceTF_in: regNPort:= (others=>'0');
begin
ask <= '1' when (h(LOCAL)='1' or h(EAST)='1' or h(WEST)='1' or h(NORTH)='1' or h(SOUTH)='1') else '0';
incoming <= CONV_VECTOR(sel);
header <= data(CONV_INTEGER(incoming));
-- escolhe uma das portas que solicitou chaveamento
process(sel, h)
begin
case sel is
when LOCAL=>
if h(EAST)='1' then prox<=EAST;
elsif h(WEST)='1' then prox<=WEST;
elsif h(NORTH)='1' then prox<=NORTH;
elsif h(SOUTH)='1' then prox<=SOUTH;
else prox<=LOCAL; end if;
when EAST=>
if h(WEST)='1' then prox<=WEST;
elsif h(NORTH)='1' then prox<=NORTH;
elsif h(SOUTH)='1' then prox<=SOUTH;
elsif h(LOCAL)='1' then prox<=LOCAL;
else prox<=EAST; end if;
when WEST=>
if h(NORTH)='1' then prox<=NORTH;
elsif h(SOUTH)='1' then prox<=SOUTH;
elsif h(LOCAL)='1' then prox<=LOCAL;
elsif h(EAST)='1' then prox<=EAST;
else prox<=WEST; end if;
when NORTH=>
if h(SOUTH)='1' then prox<=SOUTH;
elsif h(LOCAL)='1' then prox<=LOCAL;
elsif h(EAST)='1' then prox<=EAST;
elsif h(WEST)='1' then prox<=WEST;
else prox<=NORTH; end if;
when SOUTH=>
if h(LOCAL)='1' then prox<=LOCAL;
elsif h(EAST)='1' then prox<=EAST;
elsif h(WEST)='1' then prox<=WEST;
elsif h(NORTH)='1' then prox<=NORTH;
else prox<=SOUTH; end if;
end case;
end process;
tx <= header((METADEFLIT - 1) downto QUARTOFLIT); -- coordenada X do destino
ty <= header((QUARTOFLIT - 1) downto 0); -- coordernada Y do destino
------------------------------------------------------------
--gravacao da tabela de falhas
------------------------------------------------------------
--registrador para tabela de falhas
process(reset,clock)
begin
if reset='1' then
tabelaDeFalhas <= (others=>(others=>'0'));
elsif clock'event and clock='0' then
ant_c_ceTF_in <= c_ceTF_in;
-- se receber um pacote de controle para escrever/atualizar a tabela, escreve na tabela conforme a tabela recebida no pacote
if c_ceTF='1' then
tabelaDeFalhas <= c_buffTabelaFalhas;
-- se tiver feito o teste dos links, atualiza a tabela de falha conforme o resultado do teste
elsif strLinkTstAll = '1' then
--tabelaDeFalhas <= c_faultTableFDM;
tabelaDeFalhas(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(EAST) & '0';
tabelaDeFalhas(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(WEST) & '0';
tabelaDeFalhas(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(NORTH) & '0';
tabelaDeFalhas(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= c_faultTableFDM(SOUTH) & '0';
-- escrita na tabela de falhas pelo FPPM
elsif (write_FaultTable /= 0) then
-- escreve apenas se o sinal de escrit tiver ativo e se o sttus do link tiver uma severidade maior ou igual a contida na tabela
for i in 0 to HAMM_NPORT-1 loop
if (write_FaultTable(i) = '1' and row_FaultTablePorts_in(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) >= tabelaDeFalhas(i)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE)) then
tabelaDeFalhas(i) <= row_FaultTablePorts_in(i);
end if;
end loop;
end if;
end if;
end process;
-- '1' se em algum buffer houve o pedido de teste de link (por causa do pacote de controle do tipo TEST_LINKS)
strLinkTstAll <= c_strLinkTst(0) or c_strLinkTst(1) or c_strLinkTst(2) or c_strLinkTst(3) or c_strLinkTst(4);
-- "merge" das telas recebidas
process(c_ceTF_in)
variable achou: regHamm_Nport := (others=>'0');
begin
for i in 0 to NPORT-1 loop
if (ant_c_ceTF_in(i)='1' and c_ceTF_in(i)='0') then
achou := (others=>'0');
exit;
end if;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "10") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como tendencia de falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "01") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
-- pergunta para cada buffer quais que desejam escrever na tabela e, conforme os que desejam, copia as linhas da tabela do buffer que tiver como sem falha
for i in 0 to NPORT-1 loop
for j in 0 to HAMM_NPORT-1 loop
if (achou(j)='0' and c_ceTF_in(i)='1' and c_buffTabelaFalhas_in(i)(j)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) = "00") then
c_buffTabelaFalhas(j) <= c_buffTabelaFalhas_in(i)(j);
achou(j) := '1';
end if;
end loop;
end loop;
end process;
-- '1' se em algum buffer tiver habilita o ce para escrever/atualizar a tabela de falhas
c_ceTF <= ( c_ceTF_in(EAST) OR
c_ceTF_in(WEST) OR
c_ceTF_in(SOUTH) OR
c_ceTF_in(NORTH) OR
c_ceTF_in(LOCAL));
------------------------------------------------------------
process(clock,reset)
begin
c_error_ArrayFind <= (others=>invalidRegion);
c_error_ArrayFind(sel) <= find;
end process;
c_error_dir <= dir;
c_tabelafalhas <= tabelaDeFalhas;
RoutingMechanism : entity work.routingMechanism
generic map(address => address)
port map(
clock => clock,
reset => reset,
buffCtrl => c_BuffCtrl, -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
ctrl=> c_Ctrl, -- indica se foi lido ou criado de um pacote de controle pelo buffer
operacao => c_CodControle, -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
ceT => c_ce, -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
oe => ceTable, -- usado para solicitar direcao/porta destino para a tabela de roteamento
dest => header((METADEFLIT - 1) downto 0), -- primeiro flit/header do pacote (contem o destino do pacote)
inputPort => sel, -- porta de entrada selecionada pelo arbitro para ser chaveada
outputPort => dir, -- indica qual porta de saida o pacote sera encaminhado
find => find -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
);
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif clock'event and clock='0' then
ES<=PES;
end if;
end process;
------------------------------------------------------------------------------------------------------
-- PARTE COMBINACIONAL PARA DEFINIR O PROXIMO ESTADO DA MAQUINA
--
-- SO -> O estado S0 eh o estado de inicializacao da maquina. Este estado somente eh
-- atingido quando o sinal reset eh ativado.
-- S1 -> O estado S1 eh o estado de espera por requisicao de chaveamento. Quando o
-- arbitro recebe uma ou mais requisicoes, o sinal ask eh ativado fazendo a
-- maquina avancar para o estado S2.
-- S2 -> No estado S2 a porta de entrada que solicitou chaveamento eh selecionada. Se
-- houver mais de uma, aquela com maior prioridade eh a selecionada. Se o destino
-- for o proprio roteador pula para o estado S4, caso contrario segue o fluxo
-- normal.
-- S3 -> Este estado eh muito parecido com o do algoritmo XY, a diferenca eh que ele
-- verifica o destino do pacote atraves de uma tabela e nao por calculos.
-- 4 3 2 1 0
-- dir -> | Local | South | North | West | East |
process(ES,ask,h,tx,ty,auxfree,dir,find)
begin
case ES is
when S0 => PES <= S1;
when S1 => if ask='1' then PES <= S2; else PES <= S1; end if;
when S2 => PES <= S3;
when S3 =>
if address = header((METADEFLIT - 1) downto 0) and auxfree(LOCAL)='1' then PES<=S4;
-- se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
elsif(find = validRegion)then
if (h(sel)='0') then -- se desistiu de chavear (por causa do descarte do pacote)
PES <= S1;
-- se a porta de sai eh EAST e se ela estiver livre
elsif (dir(EAST)='1' and auxfree(EAST)='1') then
indice_dir <= EAST ;
PES<=S5;
elsif (dir(WEST)='1' and auxfree(WEST)='1') then
indice_dir <= WEST;
PES<=S5;
elsif (dir(NORTH)='1' and auxfree(NORTH)='1' ) then
indice_dir <= NORTH;
PES<=S6;
elsif (dir(SOUTH)='1' and auxfree(SOUTH)='1' ) then
indice_dir <= SOUTH;
PES<=S6;
else PES<=S1;
end if;
elsif(find = portError)then
PES <= S1;
else
PES<=S3;
end if;
when S4 => PES<=S7;
when S5 => PES<=S7;
when S6 => PES<=S7;
when S7 => PES<=S1;
end case;
end process;
------------------------------------------------------------------------------------------------------
-- executa as acoes correspondente ao estado atual da maquina de estados
------------------------------------------------------------------------------------------------------
process(clock)
begin
if clock'event and clock='1' then
case ES is
-- Zera variaveis
when S0 =>
ceTable <= '0';
sel <= 0;
ack_h <= (others => '0');
auxfree <= (others=> '1');
sender_ant <= (others=> '0');
mux_out <= (others=>(others=>'0'));
source <= (others=>(others=>'0'));
-- Chegou um header
when S1=>
ceTable <= '0';
ack_h <= (others => '0');
-- Seleciona quem tera direito a requisitar roteamento
when S2=>
sel <= prox;
-- Aguarda resposta da Tabela
when S3 =>
if address /= header((METADEFLIT - 1) downto 0) then
ceTable <= '1';
end if;
-- Estabelece a conexao com a porta LOCAL
when S4 =>
source(CONV_INTEGER(incoming)) <= CONV_VECTOR(LOCAL); -- sinal para a crossbar
mux_out(LOCAL) <= incoming; -- sinal para crossbar
auxfree(LOCAL) <= '0'; -- conexao estabelecida, logo porta ocupado
ack_h(sel)<='1'; -- responde que houve chaveamento com sucesso
-- Estabelece a conexao com a porta EAST ou WEST
when S5 =>
source(CONV_INTEGER(incoming)) <= CONV_VECTOR(indice_dir);
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel)<='1';
-- Estabelece a conexao com a porta NORTH ou SOUTH
when S6 =>
source(CONV_INTEGER(incoming)) <= CONV_VECTOR(indice_dir);
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel)<='1';
when others =>
ack_h(sel)<='0';
ceTable <= '0';
end case;
sender_ant(LOCAL) <= sender(LOCAL);
sender_ant(EAST) <= sender(EAST);
sender_ant(WEST) <= sender(WEST);
sender_ant(NORTH) <= sender(NORTH);
sender_ant(SOUTH) <= sender(SOUTH);
-- se uma porta estava transmitindo dados e agora nao esta mais, entao a porta ficou livre
if sender(LOCAL)='0' and sender_ant(LOCAL)='1' then auxfree(CONV_INTEGER(source(LOCAL))) <='1'; end if;
if sender(EAST) ='0' and sender_ant(EAST)='1' then auxfree(CONV_INTEGER(source(EAST))) <='1'; end if;
if sender(WEST) ='0' and sender_ant(WEST)='1' then auxfree(CONV_INTEGER(source(WEST))) <='1'; end if;
if sender(NORTH)='0' and sender_ant(NORTH)='1' then auxfree(CONV_INTEGER(source(NORTH))) <='1'; end if;
if sender(SOUTH)='0' and sender_ant(SOUTH)='1' then auxfree(CONV_INTEGER(source(SOUTH))) <='1'; end if;
end if;
end process;
mux_in <= source;
free <= auxfree;
end RoutingTable;
|
lgpl-3.0
|
8f2ae86f719fbfc1c1f0d696fbdc15ea
| 0.6348 | 3.266551 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/src/SPI_Slave.vhd
| 1 | 4,559 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
entity spi_slave is
generic(
DATA_WIDTH : integer := 8
);
port(
--In port
i_clk : in std_logic;
i_sclk : in std_logic;
i_mosi : in std_logic := '0';
i_ss : in std_logic := '1';
i_tx_send : in std_logic := '0';
i_in_data : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
--Out port
o_miso : out std_logic;
o_done : out std_logic := '0';
o_out_data : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0')
);
end spi_slave;
architecture behave of spi_slave is
function reverse_any_vector (a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_vector
type t_SM_RX is (s_Idle, s_RX, s_RX_Stop);
--type t_SM_TX is (s_Idle, s_TX, s_TX_Stop);
signal SM_RX : t_SM_RX := s_Idle;
--signal SM_TX : t_SM_TX := s_Idle;
signal r_RX_Data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
signal to_TX_Data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
signal r_SS_in : std_logic := '1';
signal r_SS : std_logic := '1';
signal bit_counter : integer range 0 to DATA_WIDTH := 0;
signal rx_complete : std_logic := '0';
signal rx_complete_in : std_logic := '0';
signal rx_sync_complete : std_logic := '0';
signal tx_sending : std_logic := '0';
signal r_RX_Received : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
begin
--Double buffer the sclk signals
p_mosi_register : process (i_sclk)
begin
if rising_edge(i_sclk) then
if i_ss = '0' then
r_RX_Received <= r_RX_Received(DATA_WIDTH-2 downto 0) & i_mosi;
end if;
end if;
end process p_mosi_register;
p_rx_bit_counter : process(i_sclk)
begin
if rising_edge(i_sclk) then
rx_complete <= '0';
if i_ss = '0' then
if bit_counter = DATA_WIDTH then
bit_counter <= 0;
rx_complete <= '1';
else
bit_counter <= bit_counter + 1;
end if;
end if;
end if;
end process p_rx_bit_counter;
p_sync : process(i_clk)
begin
if rising_edge(i_clk) then
r_SS_in <= i_ss;
r_SS <= r_SS_in;
rx_complete_in <= rx_complete;
rx_sync_complete <= rx_complete_in;
end if;
end process p_sync;
--Main running clk
p_SPI : process(i_clk)
begin
if rising_edge(i_clk) then
case SM_RX is
--Idle reset everything
when s_Idle =>
--If SS is pulled go to RX state
o_done <= '0';
if r_SS = '0' then
SM_RX <= s_RX;
else
SM_RX <= s_Idle;
end if;
--RX State
when s_RX =>
if rx_sync_complete = '1' then
r_RX_Data <= r_RX_Received;
SM_RX <= s_RX_Stop;
else
SM_RX <= s_RX;
end if;
-- Stop receiving send the received data and send ACK ?
when s_RX_Stop =>
o_done <= '1';
o_out_data <= reverse_any_vector(r_RX_Data);
SM_RX <= s_Idle;
when others =>
SM_RX <= s_Idle;
end case;
end if;
end process p_SPI;
o_miso <= to_TX_Data(DATA_WIDTH-1) when i_ss = '0' else 'Z';
p_miso_register : process (i_sclk)
begin
if rising_edge(i_sclk) then
if i_ss = '0' and i_tx_send = '1' then
to_TX_Data <= std_logic_vector(shift_left(unsigned(to_TX_Data), 1));
else
to_TX_Data <= i_in_data;
end if;
end if;
end process p_miso_register;
end behave;
|
mit
|
e0ef8cc9a32de3b1769d627a87c5df5c
| 0.459311 | 3.601106 | false | false | false | false |
dl3yc/sdr-fm
|
dev/vcordic/vcordic.vhd
| 1 | 2,229 |
-- VCORDIC module for Betty SDR
-- implements CORDIC in Vector Mode
-- file: vcordic.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with matlab as reference implementation
--
-- !!! because of the arctan table used in the CORDIC algorithm
-- !!! it only converges in the range of –1(rad) to +1(rad)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of vcordic is
type alpha_t is array(0 to N-1) of signed(P-1 downto 0); -- -180°..180°
type xy_vector is array(natural range <>) of signed(A+2 downto 0); -- -3.999..+3.999
type z_vector is array(natural range <>) of signed(P-1 downto 0); -- -180°..180°
constant K : signed(A-1 downto 0) := to_signed(integer(0.6073*2**(A-1)),A);
signal alpha : alpha_t;
signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
signal z : z_vector(N downto 0) := (others => (others => '0'));
begin
table: for i in 0 to N-1 generate
alpha(i) <= to_signed(integer( atan(1.0/real(2**i)) * (real(2**(P-1))-1.0) / math_pi ),P);
end generate;
process begin
wait until rising_edge(clk);
if i >= 0 then
x(0) <= resize(i,A+3);
y(0) <= resize(q,A+3);
z(0) <= (others => '0');
elsif q => 0 then
x(0) <= resize(q,A+3);
y(0) <= resize(-i,A+3);
z(0) <= to_signed(2**(P-3))-1,P);-- 90°
else
x(0) <= resize(-q,A+3);
y(0) <= resize(i,A+3);
z(0) <= to_signed(-2**(P-3))-1,P);-- -90°
end if;
for i in 1 to N loop
if x(i-1) >= 0 then
x(i) <= x(i-1) - y(i-1) / 2**(i-1);
y(i) <= y(i-1) + x(i-1) / 2**(i-1);
z(i) <= z(i-1) + alpha(i-1);
else
x(i) <= x(i-1) + y(i-1) / 2**(i-1);
y(i) <= y(i-1) - x(i-1) / 2**(i-1);
z(i) <= z(i-1) - alpha(i-1);
end if;
end loop;
amp <= resize(unsigned(shift_right((y(N) * K), (A-1))),A);
phi <= z(N);
end process;
end behavioral;
|
gpl-2.0
|
c9fd63e3be29875b1286ee12a5147c2c
| 0.565061 | 2.390743 | false | false | false | false |
rmilfont/Phoenix
|
NoC/FaultInjector.vhd
| 1 | 6,936 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
use work.HammingPack16.all;
use STD.textio.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
USE ieee.math_real.ALL;
entity FaultInjector is
generic(
address: regmetadeflit
);
port(
clock: in std_logic;
reset: in std_logic;
tx: in regNport;
restransmit: in regNPort;
data_in: in arrayNport_regphit;
data_out: out arrayNport_regphit;
credit: in regNport
);
end FaultInjector;
architecture FaultInjector of FaultInjector is
constant SA0: integer := 0; -- stuck-at 0
constant SA1: integer := 1; -- stuck-at 1
constant BF: integer := 2; -- bitflit error
constant OK: integer := 3; -- OK (sem falha)
type fault_bits is array (0 to 2) of regphit; -- 3 possiveis falhas (SA0, SA1, BT)
type arrayFaultNports is array (0 to NPORT-1) of fault_bits;
signal FaultNPorts: arrayFaultNports := (others=>(others=>(others=>'0')));
begin
-- aqui eh escolhido os bits dos dados de saida
-- baseados nos bits selecionados que ocorrerao a injecao de falha
-- tipos de falha: stuck-at 0, stuck-at 1, bitflip
data_fault: for i in 0 to NPORT-1 generate
begin
bit_fault: for j in 0 to TAM_PHIT-1 generate
begin
data_out(i)(j) <= '0' when (FaultNPorts(i)(SA0)(j)='1') else -- stuck-at 0
'1' when (FaultNPorts(i)(SA1)(j)='1') else -- stuck-at 1
not data_in(i)(j) when (FaultNPorts(i)(BF) (j)='1') -- bitflip
else data_in(i)(j); -- normal
end generate bit_fault;
end generate data_fault;
process
file file_pointer: text;
variable line_num : line; -- linha lida
variable tmp_word: string (1 to 50);
variable tmp_line: line;
variable line_counter: integer := 0;
variable char_pointer: integer;
variable char_pointer_tmp: integer;
variable time_now: integer := 0;
variable fault_rate: real;
variable fault_port: integer;
type real_array is array (0 to NPORT-1) of real;
variable fault_counter_Nports: real_array := (others=>0.0);
variable fault_rate_Nports: real_array := (others=>0.0);
variable fault_injected: regNPort;
variable seed1, seed2: positive; -- Seed values for random generator
variable rand: real; -- Random real-number value in range 0 to 1.0
begin
file_open(file_pointer,"fault_00"&to_hstring(address)&".txt",READ_MODE);
while not endfile(file_pointer) loop
-- limpa a string tmp_word
for i in 1 to tmp_word'length loop
tmp_word(i) := NUL;
end loop;
readline(file_pointer,line_num);
line_counter := line_counter + 1;
char_pointer := line_num'low;
-- copia a string da linha lida ate encontrar espaco (ira copiar o tempo do inicio da falha)
while (line_num(char_pointer) /= ' ' and char_pointer <= line_num'high) loop
tmp_word(char_pointer) := line_num(char_pointer);
char_pointer := char_pointer + 1;
end loop;
-- converte string lida (taxa de falhas) para real
write(tmp_line,tmp_word);
read(tmp_line,fault_rate);
-- limpa a string tmp_word
for i in 1 to tmp_word'length loop
tmp_word(i) := NUL;
end loop;
char_pointer := char_pointer + 1;
char_pointer_tmp := 1;
-- copia a string da linha lida ate encontrar espaco ou fim (ira copiar a porta de saida)
while (line_num(char_pointer) /= ' ' and line_num(char_pointer) /= NUL and char_pointer < line_num'high) loop
tmp_word(char_pointer_tmp) := line_num(char_pointer);
char_pointer := char_pointer + 1;
char_pointer_tmp := char_pointer_tmp + 1;
end loop;
-- copiar o ultimo character
tmp_word(char_pointer_tmp) := line_num(char_pointer);
if (tmp_word(1 to 4) = "EAST") then
fault_port := EAST;
elsif (tmp_word(1 to 4) = "WEST") then
fault_port := WEST;
elsif (tmp_word(1 to 5) = "NORTH") then
fault_port := NORTH;
elsif (tmp_word(1 to 5) = "SOUTH") then
fault_port := SOUTH;
elsif (tmp_word(1 to 5) = "LOCAL") then
fault_port := LOCAL;
else
assert false report "Erro de leitura da porta de saida: linha "&integer'image(line_counter)&" do arquivo fault_00"&to_hstring(address)&".txt" severity error;
wait;
end if;
--assert false report "Porta de saida: "&integer'image(fault_port) severity note;
-- limpa a string fault_type_string
for i in 1 to tmp_word'length loop
tmp_word(i) := NUL;
end loop;
fault_rate_Nports(fault_port) := fault_rate;
Deallocate(tmp_line);
end loop; -- fim da leitura do arquivo
wait until reset='0';
wait until clock='1';
wait for 1 ns;
--for i in 0 to NPORT-1 loop
--assert false report "Router 00"&to_hstring(address)&" => Fault rate in port "&PORT_NAME(i)&": "&real'image(fault_rate_Nports(i)) severity note;
--end loop;
fault_injected := (others=>'0');
uniform(seed1, seed2, rand); -- generate random number
while true loop
for i in 0 to NPORT-1 loop
if (tx(i)='1' and credit(i)='1' and restransmit(i)='0') then
fault_counter_Nports(i) := fault_counter_Nports(i) + fault_rate_Nports(i);
if (fault_counter_Nports(i) >= rand and fault_injected(i) = '0') then
FaultNPorts(i)(BF)(0) <= '1';
FaultNPorts(i)(BF)(1) <= '1';
fault_injected(i) := '1';
else
FaultNPorts(i)(BF)(0) <= '0';
FaultNPorts(i)(BF)(1) <= '0';
end if;
if (fault_counter_Nports(i) >= 1.0) then
fault_counter_Nports(i) := fault_counter_Nports(i) - 1.0;
fault_injected(i) := '0';
uniform(seed1, seed2, rand); -- generate random number
end if;
else
FaultNPorts(i)(BF)(0) <= '0';
FaultNPorts(i)(BF)(1) <= '0';
end if;
end loop;
wait for 20 ns; -- clock period
end loop;
wait;
end process;
end FaultInjector;
|
lgpl-3.0
|
44d736f30d6e4ad7bed35a906151bd8a
| 0.535179 | 3.892256 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/test.vhd
| 1 | 1,536 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:20:35 11/03/2011
-- Design Name:
-- Module Name: juegoBolita - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
Port( clk : in STD_LOGIC;
reset : in STD_LOGIC;
filasOut : out STD_LOGIC_VECTOR (7 downto 0);
columnasOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end test;
architecture Behavioral of test is
type estados is (e1,e2);
signal estado : estados;
begin
process(clk,reset)
begin
if reset = '1' then
estado <= e1;
filasOut <= "10000001";
columnasOut <= "11111111";
elsif clk'event and clk = '1' then
case estado is
when e1 =>
columnasOut <= "10000000";
filasOut <= "10000000";
estado <= e2;
when e2 =>
columnasOut <= "01000000";
filasOut <= "01000000";
estado <= e1;
end case;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
7fb87de842925252d96a6bb67d2800dc
| 0.576172 | 3.58042 | false | false | false | false |
dl3yc/sdr-fm
|
dev/sql/sql.vhd
| 1 | 1,032 |
-- SQL module for Betty SDR
-- implements a squelch control
-- file: sql.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sql is
port (
clk : in std_logic;
stb : in std_logic;
tresh : in unsigned(7 downto 0);
amp_in : in unsigned(26 downto 0);
i_in : in signed(26 downto 0);
q_in : in signed(26 downto 0);
amp_out : out unsigned(26 downto 0);
i_out : out signed(26 downto 0);
q_out : out signed(26 downto 0);
sql_out : out std_logic;
rdy : out std_logic
);
end entity sql;
architecture rtl of sql is
alias amplitude : unsigned(7 downto 0) is amp_in(26 downto 19);
begin
process
begin
wait until rising_edge(clk);
if amplitude < tresh then
sql_out <= '0';
i_out <= (others => '0');
q_out <= (others => '0');
else
sql_out <= '1';
i_out <= i_in;
q_out <= q_in;
end if;
rdy <= stb;
end process;
end architecture rtl;
|
gpl-2.0
|
d0ecf802b790a3f7ec189109fd0ac1e2
| 0.626938 | 2.632653 | false | false | false | false |
mosass/HexapodRobot
|
VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/sim/design_1_axi_gpio_1_0.vhd
| 1 | 9,115 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY design_1_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_1_axi_gpio_1_0;
ARCHITECTURE design_1_axi_gpio_1_0_arch OF design_1_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_gpio_1_0_arch;
|
mit
|
8f627dd82caa86e8594ac0b4fb8291f3
| 0.6791 | 3.217437 | false | false | false | false |
inforichland/freezing-spice
|
src/compare_unit.vhd
| 1 | 2,309 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.id_pkg.all;
entity compare_unit is
port (
branch_type : in branch_type_t;
op1 : in word;
op2 : in word;
compare_result : out std_logic);
end entity compare_unit;
architecture behavioral of compare_unit is
signal compare : std_logic;
begin -- architecture behavioral
-- assign output
compare_result <= compare;
-- purpose: compares two numbers according to branch_type
-- type : combinational
-- inputs : branch_type, op1, op2
-- outputs: compare_result
compare_proc: process (branch_type, op1, op2) is
variable ou1, ou2 : unsigned(31 downto 0);
variable os1, os2 : signed(31 downto 0);
begin -- process compare_proc
ou1 := unsigned(op1);
os1 := signed(op1);
ou2 := unsigned(op2);
os2 := signed(op2);
compare <= '0';
case (branch_type) is
when BEQ =>
if op1 = op2 then
compare <= '1';
else
compare <= '0';
end if;
when BNE =>
if op1 /= op2 then
compare <= '1';
else
compare <= '0';
end if;
when BLT =>
if os1 < os2 then
compare <= '1';
else
compare <= '0';
end if;
when BGE =>
if os1 >= os2 then
compare <= '1';
else
compare <= '0';
end if;
when BLTU =>
if ou1 < ou2 then
compare <= '1';
else
compare <= '0';
end if;
when BGEU =>
if ou1 >= ou2 then
compare <= '1';
else
compare <= '0';
end if;
when others => compare <= '0';
end case;
end process compare_proc;
end architecture behavioral;
|
bsd-3-clause
|
853fad6bc9744abf757826f93b99ea58
| 0.409701 | 4.702648 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/memory.vhd
| 1 | 5,727 |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file memory.vhd when simulating
-- the core, memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY memory IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END memory;
ARCHITECTURE memory_a OF memory IS
-- synthesis translate_off
COMPONENT wrapped_memory
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 256,
c_read_depth_b => 256,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 256,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_memory
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END memory_a;
|
mit
|
023f2672fadc11316e069bf9e49b3ac2
| 0.53607 | 3.986769 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/Thor_switchcontrol.vhd
| 1 | 5,086 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity SwitchControl is
generic(
address : regflit := (others=>'0');
ramInit : memory);
port(
clock : in std_logic;
reset : in std_logic;
h : in regNport;
ack_h : out regNport;
data : in arrayNport_regflit;
sender : in regNport;
free : out regNport;
mux_in : out arrayNport_reg3;
mux_out : out arrayNport_reg3);
end SwitchControl;
architecture RoutingTable of SwitchControl is
type state is (S0,S1,S2,S3,S4,S5);
signal ES, PES: state;
signal ask: std_logic := '0';
signal sel,prox: integer range 0 to (NPORT-1) := 0;
signal incoming: reg3 := (others=> '0');
signal header : regflit := (others=> '0');
signal ready, enable : std_logic;
signal indice_dir: integer range 0 to (NPORT-1) := 0;
signal auxfree: regNport := (others=> '0');
signal source: arrayNport_reg3 := (others=> (others=> '0'));
signal sender_ant: regNport := (others=> '0');
signal dir: regNport:= (others=> '0');
signal requests: regNport := (others=> '0');
signal find: RouterControl;
signal ceTable: std_logic := '0';
signal selectedOutput : integer := 0;
signal isOutputSelected : std_logic;
begin
ask <= '1' when OR_REDUCTION(h) else '0';
incoming <= std_logic_vector(to_unsigned(sel, incoming'length));
header <= data(TO_INTEGER(unsigned(incoming)));
RoundRobinArbiter : entity work.arbiter(RoundRobinArbiter)
generic map(size => requests'length)
port map(
requests => h,
enable => enable,
selectedOutput => prox,
isOutputSelected => ready
);
RoutingMechanism : entity work.routingMechanism
generic map(
ramInit => ramInit,
LOCAL_ADDRESS => address
)
port map(
clock => clock,
reset => reset,
oe => ceTable,
dst_address => header,
inputPort => sel,
outputPort => dir,
find => find
);
FixedPriorityArbiter : entity work.arbiter(FixedPriorityArbiter)
generic map(size => requests'length)
port map(
requests => requests,
enable => '1',
isOutputSelected => isOutputSelected,
selectedOutput => selectedOutput
);
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif rising_edge(clock) then
ES<=PES;
end if;
end process;
process(ES, ask, find, isOutputSelected)
begin
case ES is
when S0 => PES <= S1;
when S1 =>
if ask='1' then
PES <= S2;
else
PES <= S1;
end if;
when S2 => PES <= S3;
when S3 =>
if(find = validRegion) then
if (isOutputSelected = '1') then
PES <= S4;
else
PES <= S1;
end if;
elsif(find = portError) then
PES <= S1;
else
PES <= S3;
end if;
when S4 => PES <= S5;
when S5 => PES <= S1;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
case ES is
when S0 =>
ceTable <= '0';
sel <= 0;
ack_h <= (others => '0');
auxfree <= (others=> '1');
sender_ant <= (others=> '0');
mux_out <= (others=>(others=>'0'));
source <= (others=>(others=>'0'));
when S1=>
enable <= ask;
ceTable <= '0';
ack_h <= (others => '0');
when S2=>
sel <= prox;
enable <= not ready;
when S3 =>
if(find = validRegion and isOutputSelected = '1') then
indice_dir <= selectedOutput;
else
ceTable <= '1';
end if;
when S4 =>
source(TO_INTEGER(unsigned(incoming))) <= std_logic_vector(to_unsigned(indice_dir, incoming'length));
mux_out(indice_dir) <= incoming;
auxfree(indice_dir) <= '0';
ack_h(sel)<='1';
when others =>
ack_h(sel)<='0';
ceTable <= '0';
end case;
sender_ant <= sender;
for i in EAST to LOCAL loop
if sender(i)='0' and sender_ant(i)='1' then
auxfree(TO_INTEGER(unsigned(source(i)))) <= '1';
end if;
end loop;
end if;
end process;
mux_in <= source;
free <= auxfree;
requests <= auxfree AND dir;
end RoutingTable;
|
lgpl-3.0
|
c49fe703411cc5828730a474911e7128
| 0.473063 | 4.284751 | false | false | false | false |
inforichland/freezing-spice
|
src/id.vhd
| 1 | 12,417 |
library ieee;
use ieee.std_logic_1164.all;
use work.common.all;
use work.id_pkg.all;
use work.csr_pkg.all;
entity instruction_decoder is
port (d : in word;
q : out decoded_t); -- decoded data
end entity instruction_decoder;
architecture behavioral of instruction_decoder is
-------------------------------------------------
-- Types
-------------------------------------------------
type imm_type_t is (IMM_NONE, IMM_I, IMM_S, IMM_B, IMM_U, IMM_J, IMM_Z);
-------------------------------------------------
-- Signals
-------------------------------------------------
signal decoded : decoded_t := c_decoded_reset;
begin -- architecture behavioral
-------------------------------------------------
-- Assign module outputs
-------------------------------------------------
q <= decoded;
-------------------------------------------------
-- Decode the RISCV instruction
-------------------------------------------------
decode_proc : process (d) is
variable opcode : std_logic_vector(6 downto 0);
variable funct3 : std_logic_vector(2 downto 0);
variable imm_type : imm_type_t := IMM_NONE;
variable insn : word;
variable rd : std_logic_vector(4 downto 0);
begin -- process decode_proc
insn := d;
rd := insn(11 downto 7);
-- defaults & "global" fields
opcode := insn(6 downto 0);
funct3 := insn(14 downto 12);
decoded.rs1 <= insn(19 downto 15);
decoded.rs2 <= insn(24 downto 20);
decoded.rd <= rd;
decoded.opcode <= opcode;
decoded.rs1_rd <= '0';
decoded.rs2_rd <= '0';
decoded.alu_func <= ALU_NONE;
decoded.op2_src <= '0';
decoded.insn_type <= OP_ILLEGAL;
decoded.load_type <= LOAD_NONE;
decoded.store_type <= STORE_NONE;
decoded.imm <= (others => 'X');
decoded.use_imm <= '0';
decoded.branch_type <= BRANCH_NONE;
decoded.rf_we <= '0';
decoded.is_csr <= '0';
decoded.csr_addr <= (others => 'X');
case (opcode) is
-- Load Upper Immediate
when c_op_lui =>
decoded.insn_type <= OP_LUI;
imm_type := IMM_U;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Add Upper Immediate to PC
when c_op_auipc =>
decoded.insn_type <= OP_AUIPC;
imm_type := IMM_U;
decoded.alu_func <= ALU_ADD;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Jump And Link
when c_op_jal =>
decoded.insn_type <= OP_JAL;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_J;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Jump And Link Register
when c_op_jalr =>
decoded.insn_type <= OP_JALR;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
-- Branch to target address, if condition is met
when c_op_branch =>
decoded.insn_type <= OP_BRANCH;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_B;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.branch_type <= BEQ;
when "001" => decoded.branch_type <= BNE;
when "100" => decoded.branch_type <= BLT;
when "101" => decoded.branch_type <= BGE;
when "110" => decoded.branch_type <= BLTU;
when "111" => decoded.branch_type <= BGEU;
when others => null;
end case;
-- load data from memory
when c_op_load =>
decoded.insn_type <= OP_LOAD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
decoded.alu_func <= ALU_ADD;
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
case (funct3) is
when "000" => decoded.load_type <= LB;
when "001" => decoded.load_type <= LH;
when "010" => decoded.load_type <= LW;
when "100" => decoded.load_type <= LBU;
when "101" => decoded.load_type <= LHU;
when others => null;
end case;
-- store data to memory
when c_op_store =>
decoded.insn_type <= OP_STORE;
imm_type := IMM_S;
decoded.alu_func <= ALU_ADD;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.store_type <= SB;
when "001" => decoded.store_type <= SH;
when "010" => decoded.store_type <= SW;
when others => null;
end case;
-- perform computation with immediate value and a register
when c_op_imm =>
decoded.insn_type <= OP_ALU;
decoded.op2_src <= '1';
imm_type := IMM_I;
decoded.rs1_rd <= '1';
decoded.use_imm <= '1';
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
case (funct3) is
when "000" => decoded.alu_func <= ALU_ADD;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when others => null;
end case;
-- perform computation with two register values
when c_op_reg =>
decoded.insn_type <= OP_ALU;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
if (rd /= "00000") then
decoded.rf_we <= '1';
end if;
case (funct3) is
when "000" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SUB;
else
decoded.alu_func <= ALU_ADD;
end if;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when others => null;
end case;
-- system functions
when c_op_system =>
decoded.insn_type <= OP_SYSTEM;
decoded.csr_addr <= insn(31 downto 20);
case (funct3) is
when "000" =>
if insn(20) = '0' then
decoded.system_type <= SYSTEM_ECALL;
else
decoded.system_type <= SYSTEM_EBREAK;
end if;
when "001" =>
decoded.system_type <= SYSTEM_CSRRW;
decoded.rf_we <= '1';
decoded.rs1_rd <= '1';
when "010" =>
decoded.system_type <= SYSTEM_CSRRS;
decoded.rf_we <= '1';
decoded.rs1_rd <= '1';
when "011" =>
decoded.system_type <= SYSTEM_CSRRC;
decoded.rf_we <= '1';
decoded.rs1_rd <= '1';
when "101" =>
decoded.system_type <= SYSTEM_CSRRWI;
decoded.rf_we <= '1';
decoded.use_imm <= '1';
when "110" =>
decoded.system_type <= SYSTEM_CSRRSI;
decoded.rf_we <= '1';
decoded.use_imm <= '1';
when "111" =>
decoded.system_type <= SYSTEM_CSRRC;
decoded.rf_we <= '1';
decoded.use_imm <= '1';
when others =>
decoded.insn_type <= OP_ILLEGAL;
end case;
when others =>
decoded.insn_type <= OP_ILLEGAL;
end case;
-- @TODO other insnructions
--when c_op_misc_mem =>
-- insn_type <= OP_FENCE;
-- decode and sign-extend the immediate value
case imm_type is
when IMM_I =>
for i in 31 downto 12 loop
decoded.imm(i) <= insn(31);
end loop;
decoded.imm(11 downto 5) <= insn(31 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= insn(20);
when IMM_S =>
for i in 31 downto 11 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= insn(7);
when IMM_B =>
for i in 31 downto 13 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(12) <= insn(31);
decoded.imm(11) <= insn(7);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= '0';
when IMM_U =>
decoded.imm(31) <= insn(31);
decoded.imm(30 downto 20) <= insn(30 downto 20);
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11 downto 0) <= (others => '0');
when IMM_J =>
for i in 31 downto 20 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11) <= insn(20);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= '0';
when IMM_Z =>
for i in 31 downto 5 loop
decoded.imm(i) <= insn(4);
end loop; -- i
decoded.imm(4 downto 0) <= insn(4 downto 0);
when others => decoded.imm <= (others => 'X');
end case;
end process decode_proc;
end architecture behavioral;
|
bsd-3-clause
|
102b07c6e922833888960be90da857c3
| 0.383104 | 4.492402 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AA_AA_TB.vhd
| 1 | 1,245 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AA_AA_TB IS
END LatchSR_AA_AA_TB;
ARCHITECTURE behavior OF LatchSR_AA_AA_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AA_AA
PORT(
S : IN std_logic;
R : IN std_logic;
EN : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
--Inputs
signal S : std_logic := '0';
signal R : std_logic := '0';
signal EN : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LatchSR_AA_AA PORT MAP (
S => S,
R => R,
EN => EN,
Q => Q,
Qn => Qn
);
-- Stimulus process
stim_proc: process
begin
-- EN = '1', S = '1' , R = '1'.
EN <= '1';
S <= '1';
R <= '1';
wait for 100 ns;
-- EN = '1', S = '1' , R = '0';
R <= '0';
wait for 100 ns;
-- EN = '1', S = '0' , R = '1';
S <= '0';
R <= '1';
wait for 100 ns;
-- EN = '1', S = '0' , R = '0'.
R <= '0';
wait for 100 ns;
-- EN = '0', S = 'x' , R = 'x'.
EN <= '0';
wait;
end process;
END;
|
gpl-3.0
|
9ef564c31ef91267c29f1462c2e9a769
| 0.449799 | 2.922535 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/Thor_package.vhd
| 1 | 3,974 |
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
package NoCPackage is
---------------------------------------------------------
-- INDEPENDENT CONSTANTS
---------------------------------------------------------
constant NPORT: integer := 5;
constant EAST : integer := 0;
constant WEST : integer := 1;
constant NORTH : integer := 2;
constant SOUTH : integer := 3;
constant LOCAL : integer := 4;
---------------------------------------------------------
-- CONSTANTS RELATED TO THE NETWORK BANDWIDTH
---------------------------------------------------------
constant TAM_FLIT : integer range 1 to 64 := 16;
constant METADEFLIT : integer range 1 to 32 := (TAM_FLIT/2);
constant QUARTOFLIT : integer range 1 to 16 := (TAM_FLIT/4);
---------------------------------------------------------
-- CONSTANTS RELATED TO THE DEPTH OF THE QUEUE
---------------------------------------------------------
constant TAM_BUFFER: integer := 16;
constant TAM_POINTER : integer range 1 to 32 := 5;
---------------------------------------------------------
-- CONSTANTS RELATED TO THE NUMBER OF ROUTERS
---------------------------------------------------------
constant NUM_X : integer := 2;
constant NUM_Y : integer := 2;
constant NROT: integer := NUM_X*NUM_Y;
constant MIN_X : integer := 0;
constant MIN_Y : integer := 0;
constant MAX_X : integer := NUM_X-1;
constant MAX_Y : integer := NUM_Y-1;
---------------------------------------------------------
-- NEW HARDWARE VARIABLES
---------------------------------------------------------
type RouterControl is (invalidRegion, validRegion, faultPort, portError);
---------------------------------------------------------
-- SUBTYPES, TYPES AND FUNCTIONS
---------------------------------------------------------
subtype reg3 is std_logic_vector(2 downto 0);
subtype regNrot is std_logic_vector((NROT-1) downto 0);
subtype regNport is std_logic_vector((NPORT-1) downto 0);
subtype regflit is std_logic_vector((TAM_FLIT-1) downto 0);
subtype regmetadeflit is std_logic_vector((METADEFLIT-1) downto 0);
subtype regquartoflit is std_logic_vector((QUARTOFLIT-1) downto 0);
type arrayNport_reg3 is array((NPORT-1) downto 0) of reg3;
type arrayNport_regflit is array((NPORT-1) downto 0) of regflit;
type arrayNrot_regflit is array((NROT-1) downto 0) of regflit;
type arrayNrot_regNport is array((NROT-1) downto 0) of regNport;
type matrixNrot_Nport_regflit is array((NROT-1) downto 0) of arrayNport_regflit;
---------------------------------------------------------
-- TB FUNCTIONS
---------------------------------------------------------
function ADDRESS_FROM_INDEX(index : integer) return regflit;
function X_COORDINATE(address: regflit) return natural;
function Y_COORDINATE(address: regflit) return natural;
function OR_REDUCTION(arrayN : std_logic_vector ) return boolean;
end NoCPackage;
package body NoCPackage is
function ADDRESS_FROM_INDEX(index: integer) return regflit is
variable addrX, addrY: regmetadeflit;
variable addr: regflit;
begin
addrX := std_logic_vector(to_unsigned(index/NUM_X, METADEFLIT));
addrY := std_logic_vector(to_unsigned(index mod NUM_Y, METADEFLIT));
addr := addrX & addrY;
return addr;
end ADDRESS_FROM_INDEX;
function X_COORDINATE(address: regflit) return natural is
begin
return TO_INTEGER(unsigned(address(TAM_FLIT-1 downto METADEFLIT)));
end X_COORDINATE;
function Y_COORDINATE(address: regflit) return natural is
begin
return TO_INTEGER(unsigned(address(METADEFLIT-1 downto 0)));
end Y_COORDINATE;
--
-- Do a OR operation between all elements in an array
--
function OR_REDUCTION( arrayN: in std_logic_vector ) return boolean is
begin
return unsigned(arrayN) /= 0;
end OR_REDUCTION;
end NoCPackage;
|
lgpl-3.0
|
f180a51a367f719b5fbe133f14c0e9ed
| 0.546553 | 4.714116 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica4/multiplex5bits.vhd
| 1 | 1,402 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:49:20 09/11/2011
-- Design Name:
-- Module Name: multiplex5bits - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity multiplex5bits is
Port ( SELECTOR : in STD_LOGIC;
JUEGO : in STD_LOGIC_VECTOR (4 downto 0);
SWITCH : in STD_LOGIC_VECTOR (2 downto 0);
DISPLAY: out STD_LOGIC_VECTOR (4 downto 0));
end multiplex5bits;
architecture Behavioral of multiplex5bits is
begin
process(SELECTOR,JUEGO,SWITCH)
begin
if(SELECTOR='1') then DISPLAY <= JUEGO;
else
DISPLAY(4) <= SWITCH(2);
DISPLAY(3) <= SWITCH(1);
DISPLAY(2) <= SWITCH(0);
DISPLAY(1) <= '1';
DISPLAY(0) <= '1';
end if;
end process;
end Behavioral;
|
gpl-2.0
|
b5b19137496e565e65995705b32730fa
| 0.572753 | 3.689474 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/NOC.vhd
| 1 | 2,881 |
library IEEE;
use IEEE.std_logic_1164.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity NOC is
port(
clock : in regNrot;
reset : in std_logic;
clock_rxLocal : in regNrot;
rxLocal : in regNrot;
data_inLocal : in arrayNrot_regflit;
credit_oLocal : out regNrot;
clock_txLocal : out regNrot;
txLocal : out regNrot;
data_outLocal : out arrayNrot_regflit;
credit_iLocal : in regNrot);
end NOC;
architecture NOC of NOC is
signal rx, clock_rx, credit_i, tx, clock_tx, credit_o, testLink_i, testLink_o : arrayNrot_regNport;
signal data_in, data_out : matrixNrot_Nport_regflit;
begin
Router: FOR i IN 0 TO (NROT-1) GENERATE
n : Entity work.RouterCC
generic map
(
address => ADDRESS_FROM_INDEX(i),
ramInit => TAB(i)
)
port map
(
clock => clock(i),
reset => reset,
clock_rx => clock_rx(i),
rx => rx(i),
data_in => data_in(i),
credit_o => credit_o(i),
clock_tx => clock_tx(i),
tx => tx(i),
data_out => data_out(i),
credit_i => credit_i(i)
);
END GENERATE Router;
internal_ports: FOR i IN 0 TO (NROT-1) GENERATE
east: if i < NUM_Y*MAX_X GENERATE
clock_rx(i)(0) <= clock_tx(i+NUM_Y)(1);
rx(i)(0) <= tx(i+NUM_Y)(1);
data_in(i)(0) <= data_out(i+NUM_Y)(1);
credit_i(i)(0) <= credit_o(i+NUM_Y)(1);
end GENERATE;
west: if i >= NUM_Y GENERATE
clock_rx(i)(1) <= clock_tx(i-NUM_Y)(0);
rx(i)(1) <= tx(i-NUM_Y)(0);
data_in(i)(1) <= data_out(i-NUM_Y)(0);
credit_i(i)(1) <= credit_o(i-NUM_Y)(0);
end GENERATE;
north: if (i-(i/NUM_Y)*NUM_Y) < MAX_Y GENERATE
clock_rx(i)(2) <= clock_tx(i+1)(3);
rx(i)(2) <= tx(i+1)(3);
data_in(i)(2) <= data_out(i+1)(3);
credit_i(i)(2) <= credit_o(i+1)(3);
end GENERATE;
south: if (i-(i/NUM_Y)*NUM_Y) > MIN_Y GENERATE
clock_rx(i)(3) <= clock_tx(i-1)(2);
rx(i)(3)<=tx(i-1)(2);
data_in(i)(3)<=data_out(i-1)(2);
credit_i(i)(3)<=credit_o(i-1)(2);
end GENERATE;
END GENERATE;
local_port : FOR i IN 0 TO (NROT-1) GENERATE
clock_rx(i)(LOCAL)<= clock_rxLocal(i);
data_in(i)(LOCAL)<=data_inLocal(i);
credit_i(i)(LOCAL)<=credit_iLocal(i);
rx(i)(LOCAL)<=rxLocal(i);
clock_txLocal(i)<= clock_tx(i)(LOCAL);
data_outLocal(i)<=data_out(i)(LOCAL);
credit_oLocal(i)<=credit_o(i)(LOCAL);
txLocal(i)<=tx(i)(LOCAL);
END GENERATE;
end NOC;
|
lgpl-3.0
|
3aeb23874b2ee686f9d0e07c49c8bbae
| 0.481777 | 3.077991 | false | false | false | false |
dl3yc/sdr-fm
|
testing/dfir-1.0/src/dfir.vhd
| 1 | 5,433 |
-- DFIR module for Betty SDR
-- implements a decimating FIR filter for odd filter order without symmetry presumption
-- file: dfir.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with dirac impulse
-- - test for linear phase with complex carrier
--
-- needs generics with definition of dfir_order and dfir_coeff
-- with dfir_order+1 elements in Q0.26 signed fixed point format
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dfir_types is
type dfir_coeff_t is array(natural range <>) of signed(26 downto 0);
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dfir_types.all;
entity dfir is
generic (
dfir_order : natural;
dfir_coeff : dfir_coeff_t
);
port (
clk : in std_logic;
stb : in std_logic;
d : in signed(26 downto 0);
q : out signed(26 downto 0);
rdy : out std_logic
);
end entity dfir;
architecture rtl of dfir is
-- shift register
type shift_t is array(dfir_order/2 downto 0) of signed(26 downto 0);
type sr_t is record
input : signed(26 downto 0);
shift : shift_t;
sel : std_logic;
en : std_logic;
end record;
constant sr_default : sr_t := (
input => (others => '0'),
shift => (others => (others => '0')),
sel => '0',
en => '0'
);
signal sr0 : sr_t := sr_default;
signal sr1 : sr_t := sr_default;
signal sr_en : std_logic;
signal sr_sel : std_logic := '0';
-- coeff ROM
signal rom : dfir_coeff_t(dfir_order downto 0) := dfir_coeff;
signal coeff : signed(26 downto 0);
signal coeff_index : natural range 0 to dfir_order;
-- MAC unit
type mac_t is record
in_a : signed(26 downto 0);
in_b : signed(26 downto 0);
mult_out : signed(53 downto 0);
acc_out : signed(53 downto 0);
mac_out : signed(26 downto 0);
clr : std_logic;
stb : std_logic;
en : std_logic;
end record;
constant mac_default : mac_t := (
in_a => (others => '0'),
in_b => (others => '0'),
mult_out => (others => '0'),
acc_out => (others => '0'),
mac_out => (others => '0'),
clr => '0',
stb => '0',
en => '0'
);
signal mac : mac_t := mac_default;
-- finite state machine
type state_t is (reset, prolog, multiply_and_add, epilog);
signal state : state_t;
signal fsm_index : natural range 0 to dfir_order/2;
signal phase : std_logic := '0';
begin
rom_register : process
begin
wait until rising_edge(clk);
coeff <= rom(coeff_index);
end process rom_register;
shift_register0 : process
begin
wait until rising_edge(clk);
if sr0.en = '1' and phase = '0' then
sr0.shift(sr0.shift'high downto sr0.shift'low+1) <= sr0.shift(sr0.shift'high-1 downto sr0.shift'low);
if sr0.sel = '1' then
sr0.shift(sr0.shift'low) <= sr0.input;
else
sr0.shift(sr0.shift'low) <= sr0.shift(sr0.shift'high);
end if;
end if;
end process shift_register0;
sr0.input <= d;
sr0.en <= sr_en when phase = '0' else '0';
sr0.sel <= sr_sel;
shift_register1 : process
begin
wait until rising_edge(clk);
if sr1.en = '1' and phase = '1' then
sr1.shift(sr1.shift'high downto sr1.shift'low+1) <= sr1.shift(sr1.shift'high-1 downto sr1.shift'low);
if sr1.sel = '1' then
sr1.shift(sr1.shift'low) <= sr1.input;
else
sr1.shift(sr1.shift'low) <= sr1.shift(sr1.shift'high);
end if;
end if;
end process shift_register1;
sr1.input <= d;
sr1.en <= sr_en when phase = '1' else '0';
sr1.sel <= sr_sel;
mac_unit : process
begin
wait until rising_edge(clk);
mac.in_a <= coeff;
if phase = '0' then
mac.in_b <= sr0.shift(sr0.shift'high);
else
mac.in_b <= sr1.shift(sr1.shift'high);
end if;
mac.mult_out <= mac.in_a * mac.in_b;
if mac.clr = '1' then
mac.acc_out <= (others => '0');
else
if mac.en = '1' then
mac.acc_out <= mac.acc_out + mac.mult_out;
end if;
end if;
if mac.stb = '1' then
mac.mac_out <= mac.acc_out(52 downto 26);
end if;
end process mac_unit;
fsm : process
begin
wait until rising_edge(clk);
case state is
when reset =>
sr_en <= '0';
rdy <= '0';
mac.stb <= '0';
fsm_index <= 0;
if stb = '1' then
sr_en <= '1';
sr_sel <= '1';
state <= prolog;
end if;
when prolog =>
sr_sel <= '0';
fsm_index <= fsm_index + 1;
if phase = '0' then
coeff_index <= 2 * fsm_index + 1;
else
coeff_index <= 2 * fsm_index;
end if;
if fsm_index = 0 then
sr_en <= '0';
else
sr_en <= '1';
end if;
if fsm_index = 2 and phase = '0' then
mac.clr <= '1';
end if;
if fsm_index = 3 then
mac.clr <= '0';
mac.en <= '1';
state <= multiply_and_add;
end if;
when multiply_and_add =>
if phase = '0' then
coeff_index <= 2 * fsm_index + 1;
else
coeff_index <= 2 * fsm_index;
end if;
if fsm_index = dfir_order/2 then
state <= epilog;
fsm_index <= 0;
else
fsm_index <= fsm_index + 1;
end if;
when epilog =>
fsm_index <= fsm_index + 1;
if fsm_index = 1 then
sr_en <= '0';
end if;
if fsm_index = 3 then
phase <= not phase;
state <= reset;
mac.en <= '0';
if phase = '1' then
mac.stb <= '1';
rdy <= '1';
end if;
end if;
end case;
end process fsm;
q <= mac.mac_out;
assert (dfir_order mod 2 = 1) report("only odd filter order are supported") severity failure;
end architecture rtl;
|
gpl-2.0
|
f503c92807bee26cf3ecac1a1d8be90c
| 0.600221 | 2.675037 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_1_0/synth/DemoInterconnect_axi_spi_master_1_0.vhd
| 1 | 11,283 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_1_0 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_1_0;
ARCHITECTURE DemoInterconnect_axi_spi_master_1_0_arch OF DemoInterconnect_axi_spi_master_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_axi_spi_master_1_0_arch: ARCHITECTURE IS "axi_spi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_axi_spi_master_1_0_arch : ARCHITECTURE IS "DemoInterconnect_axi_spi_master_1_0,axi_spi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_1_0_arch;
|
mit
|
e957cfb9ab3789a802ae115a7c1fb74b
| 0.714349 | 3.191796 | false | false | false | false |
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/src/internoc_pack.vhd
| 2 | 735 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package internoc_pack is
--constants
constant INVALID_INTERFACE : std_logic_vector(2 downto 0) := (others=>'1');
constant UART_INTERFACE : std_logic_vector(2 downto 0) := "001";
constant SPI_INTERFACE : std_logic_vector(2 downto 0) := "010";
constant I2C_INTERFACE : std_logic_vector(2 downto 0) := "100";
constant MASTER_MODE : std_logic := '0';
constant SLAVE_MODE : std_logic := '1';
--types
type INTERFACE_T is record
addr : std_logic_vector(4 downto 0);
mode : std_logic;
interface : std_logic_vector(2 downto 0);
end record;
type INTERFACE_MAP_T is array(natural range <>) of INTERFACE_T;
--functions
end package internoc_pack;
|
mit
|
61d6bb931b51d8d80ea2c2150cd7bb8f
| 0.692517 | 3.114407 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/proyecto/roadWarrior.vhd
| 1 | 2,174 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:13:01 11/24/2011
-- Design Name:
-- Module Name: roadWarrior - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity roadWarrior is
Port ( clk : in std_logic;
avance : in std_logic;
reset : in std_logic;
memoria : out std_logic_vector(6 downto 0);
registro : out std_logic
);
end roadWarrior;
architecture Behavioral of roadWarrior is
signal contadorRegistro : std_logic_vector(2 downto 0) := (others => '0');
signal contadorCuadros : std_logic_vector(6 downto 0) := (others => '0');
signal contadorMemoria : std_logic_vector(6 downto 0) := (others => '0');
begin
-- Proceso memoria
process(clk,avance,reset,contadorRegistro,contadorCuadros,contadorMemoria)
begin
if reset = '1' then
contadorCuadros <= "0000000";
contadorMemoria <= "0000000";
contadorRegistro <= "000";
memoria <= "0000000";
registro <= '0';
elsif clk'event and clk = '1' then
-- Proceso para el registro y la memoria
case contadorRegistro is
when "000" =>
registro <= '1';
contadorMemoria <= contadorCuadros;
when others =>
registro <= '0';
contadorMemoria <= contadorMemoria + 1;
end case;
contadorRegistro <= contadorRegistro + 1;
memoria <= contadorMemoria;
-- Proceso para el avance del escenario
if avance = '1' then
contadorCuadros <= contadorCuadros + 1;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
738d686595b3dd42881d95141ea1c83c
| 0.610856 | 3.659933 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/Thor_RM.vhd
| 1 | 3,266 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity routingMechanism is
generic(
LOCAL_ADDRESS : regflit;
ramInit : memory := (others=>(others=>'0')));
port(
clock : in std_logic;
reset : in std_logic;
oe : in std_logic;
dst_address : in regflit;
inputPort : in integer range 0 to (NPORT-1);
outputPort : out regNPort;
find : out RouterControl
);
end routingMechanism;
architecture behavior of routingMechanism is
signal dst_x, dst_y : integer;
type row is array ((NREG-1) downto 0) of integer;
signal bottom_left_x, bottom_left_y, top_right_x, top_right_y : row;
signal H : std_logic_vector((NREG-1) downto 0);
type arrayIP is array ((NREG-1) downto 0) of ports;
signal IP : arrayIP;
signal RAM: memory := ramInit;
begin
dst_x <= X_COORDINATE(dst_address) when oe = '1' else 0;
dst_y <= Y_COORDINATE(dst_address) when oe = '1' else 0;
cond: for j in 0 to (NREG - 1) generate
IP(j) <= input_ports(RAM(j)) when oe = '1' else (others=>'0');
bottom_left_x(j) <= lower_left_x(RAM(j)) when oe = '1' else 0;
bottom_left_y(j) <= lower_left_y(RAM(j)) when oe = '1' else 0;
top_right_x(j) <= upper_right_x(RAM(j)) when oe = '1' else 0;
top_right_y(j) <= upper_right_y(RAM(j)) when oe = '1' else 0;
H(j) <= '1' when dst_x >= bottom_left_x(j) and dst_x <= top_right_x(j) and
dst_y >= bottom_left_y(j) and dst_y <= top_right_y(j) and
IP(j)(inputPort) = '1' and oe = '1' else
'0';
end generate;
process(RAM, H, oe, dst_address)
variable data : regNPort;
begin
data := (others=>'0');
find <= invalidRegion;
if oe = '1' then
if LOCAL_ADDRESS = dst_address then
data := (LOCAL=>'1', others=>'0');
find <= validRegion;
else
for i in 0 to (NREG-1) loop
if H(i) = '1' then
data := data or output_ports(RAM(i));
find <= validRegion;
exit;
end if;
end loop;
end if;
end if;
outputPort <= data;
end process;
end behavior;
architecture DOR_XY of routingMechanism is
signal local_x: natural;
signal dest_x: natural;
signal local_y: natural;
signal dest_y: natural;
begin
local_x <= X_COORDINATE(LOCAL_ADDRESS);
local_y <= Y_COORDINATE(LOCAL_ADDRESS);
dest_x <= X_COORDINATE(dst_address);
dest_y <= Y_COORDINATE(dst_address);
find <= validRegion;
process(local_x, dest_x, local_y, dest_y)
begin
outputPort <= (others => '0');
if dest_x > local_x then
outputPort(EAST) <='1';
elsif dest_x < local_x then
outputPort(WEST) <= '1';
elsif dest_y < local_y then
outputPort(SOUTH) <= '1';
elsif dest_y > local_y then
outputPort(NORTH) <= '1';
else
outputPort(LOCAL) <= '1';
end if;
end process;
end architecture DOR_XY;
|
lgpl-3.0
|
59e79daf8fdce78897e72d20d410ce89
| 0.534905 | 3.511828 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/synth/DemoInterconnect.vhd
| 3 | 231,236 |
--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
--Date : Fri Nov 17 16:04:47 2017
--Host : egk-pc running 64-bit major release (build 9200)
--Command : generate_target DemoInterconnect.bd
--Design : DemoInterconnect
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_4EB6IN is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_4EB6IN;
architecture STRUCTURE of m00_couplers_imp_4EB6IN is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1SL2GIW is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1SL2GIW;
architecture STRUCTURE of m01_couplers_imp_1SL2GIW is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_7DG2C0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_7DG2C0;
architecture STRUCTURE of m02_couplers_imp_7DG2C0 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m02_couplers_to_m02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m02_couplers_to_m02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1YCPS1Z is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1YCPS1Z;
architecture STRUCTURE of m03_couplers_imp_1YCPS1Z is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_ACM7VL is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_ACM7VL;
architecture STRUCTURE of m04_couplers_imp_ACM7VL is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_1HWY5FA is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_1HWY5FA;
architecture STRUCTURE of m05_couplers_imp_1HWY5FA is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_DBR4EM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_DBR4EM;
architecture STRUCTURE of m06_couplers_imp_DBR4EM is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7XIH8P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_7XIH8P;
architecture STRUCTURE of s00_couplers_imp_7XIH8P is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC;
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s00_couplers_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s00_couplers_to_s00_couplers_AWVALID;
M_AXI_bready <= s00_couplers_to_s00_couplers_BREADY;
M_AXI_rready <= s00_couplers_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s00_couplers_to_s00_couplers_WVALID;
S_AXI_arready <= s00_couplers_to_s00_couplers_ARREADY;
S_AXI_awready <= s00_couplers_to_s00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_s00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_s00_couplers_RVALID;
S_AXI_wready <= s00_couplers_to_s00_couplers_WREADY;
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY <= M_AXI_arready;
s00_couplers_to_s00_couplers_ARVALID <= S_AXI_arvalid;
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY <= M_AXI_awready;
s00_couplers_to_s00_couplers_AWVALID <= S_AXI_awvalid;
s00_couplers_to_s00_couplers_BREADY <= S_AXI_bready;
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID <= M_AXI_bvalid;
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY <= S_AXI_rready;
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1XSI6OU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1XSI6OU;
architecture STRUCTURE of s01_couplers_imp_1XSI6OU is
signal s01_couplers_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_ARVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_RREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_RVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s01_couplers_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s01_couplers_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= s01_couplers_to_s01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= s01_couplers_to_s01_couplers_AWVALID;
M_AXI_bready <= s01_couplers_to_s01_couplers_BREADY;
M_AXI_rready <= s01_couplers_to_s01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s01_couplers_to_s01_couplers_WVALID;
S_AXI_arready <= s01_couplers_to_s01_couplers_ARREADY;
S_AXI_awready <= s01_couplers_to_s01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_s01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= s01_couplers_to_s01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s01_couplers_to_s01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s01_couplers_to_s01_couplers_RVALID;
S_AXI_wready <= s01_couplers_to_s01_couplers_WREADY;
s01_couplers_to_s01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_s01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_s01_couplers_ARREADY <= M_AXI_arready;
s01_couplers_to_s01_couplers_ARVALID <= S_AXI_arvalid;
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY <= M_AXI_awready;
s01_couplers_to_s01_couplers_AWVALID <= S_AXI_awvalid;
s01_couplers_to_s01_couplers_BREADY <= S_AXI_bready;
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID <= M_AXI_bvalid;
s01_couplers_to_s01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s01_couplers_to_s01_couplers_RREADY <= S_AXI_rready;
s01_couplers_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s01_couplers_to_s01_couplers_RVALID <= M_AXI_rvalid;
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_2QLUHY is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s02_couplers_imp_2QLUHY;
architecture STRUCTURE of s02_couplers_imp_2QLUHY is
component DemoInterconnect_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s02_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s02_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s02_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s02_couplers_WVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_ARLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_pc_AWLOCK : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s02_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s02_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s02_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s02_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s02_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s02_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s02_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s02_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s02_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= s02_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= s02_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s02_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(0) <= s02_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= s02_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s02_couplers_to_auto_pc_WREADY;
auto_pc_to_s02_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s02_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s02_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s02_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s02_couplers_WREADY <= M_AXI_wready;
s02_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
s02_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_auto_pc_ARLOCK <= S_AXI_arlock;
s02_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s02_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s02_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s02_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s02_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s02_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
s02_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s02_couplers_to_auto_pc_AWLOCK <= S_AXI_awlock;
s02_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s02_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s02_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s02_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s02_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s02_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s02_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s02_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s02_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s02_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component DemoInterconnect_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s02_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s02_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s02_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s02_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s02_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s02_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s02_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s02_couplers_AWVALID,
m_axi_bready => auto_pc_to_s02_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s02_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s02_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s02_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s02_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s02_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s02_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s02_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s02_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s02_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s02_couplers_WVALID,
s_axi_araddr(31 downto 0) => s02_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s02_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s02_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => s02_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => s02_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => s02_couplers_to_auto_pc_ARLOCK,
s_axi_arprot(2 downto 0) => s02_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s02_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s02_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s02_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s02_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s02_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s02_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s02_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => s02_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => s02_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => s02_couplers_to_auto_pc_AWLOCK,
s_axi_awprot(2 downto 0) => s02_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s02_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s02_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s02_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s02_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => s02_couplers_to_auto_pc_BID(0),
s_axi_bready => s02_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s02_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s02_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s02_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(0) => s02_couplers_to_auto_pc_RID(0),
s_axi_rlast => s02_couplers_to_auto_pc_RLAST,
s_axi_rready => s02_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s02_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s02_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s02_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => s02_couplers_to_auto_pc_WLAST,
s_axi_wready => s02_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s02_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s02_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arlock : in STD_LOGIC;
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awlock : in STD_LOGIC;
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awready : out STD_LOGIC;
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_bready : in STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_wvalid : in STD_LOGIC
);
end DemoInterconnect_axi_interconnect_0_0;
architecture STRUCTURE of DemoInterconnect_axi_interconnect_0_0 is
component DemoInterconnect_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component DemoInterconnect_xbar_0;
signal interconnect_ACLK_net : STD_LOGIC;
signal interconnect_ARESETN_net : STD_LOGIC;
signal interconnect_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s00_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s00_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s00_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s00_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s01_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s01_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s01_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s01_couplers_WVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_ARLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_ARREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_ARVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_to_s02_couplers_AWLOCK : STD_LOGIC;
signal interconnect_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_AWREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_to_s02_couplers_AWVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_BREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_BVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal interconnect_to_s02_couplers_RLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_RREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_to_s02_couplers_RVALID : STD_LOGIC;
signal interconnect_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_to_s02_couplers_WLAST : STD_LOGIC;
signal interconnect_to_s02_couplers_WREADY : STD_LOGIC;
signal interconnect_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_to_s02_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m00_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m00_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m01_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m01_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m02_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m02_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m03_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m03_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m04_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m04_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m05_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m05_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_interconnect_WVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_ARREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_ARVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_AWREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_AWVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_BREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_BVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_RREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_interconnect_RVALID : STD_LOGIC;
signal m06_couplers_to_interconnect_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_interconnect_WREADY : STD_LOGIC;
signal m06_couplers_to_interconnect_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_interconnect_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC;
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s02_couplers_to_xbar_BREADY : STD_LOGIC;
signal s02_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 12 );
begin
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_interconnect_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_interconnect_ARPROT(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_interconnect_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_interconnect_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_interconnect_AWPROT(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_interconnect_AWVALID;
M00_AXI_bready <= m00_couplers_to_interconnect_BREADY;
M00_AXI_rready <= m00_couplers_to_interconnect_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_interconnect_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_interconnect_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_interconnect_WVALID;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_interconnect_ARADDR(31 downto 0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_interconnect_ARPROT(2 downto 0);
M01_AXI_arvalid <= m01_couplers_to_interconnect_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_interconnect_AWADDR(31 downto 0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_interconnect_AWPROT(2 downto 0);
M01_AXI_awvalid <= m01_couplers_to_interconnect_AWVALID;
M01_AXI_bready <= m01_couplers_to_interconnect_BREADY;
M01_AXI_rready <= m01_couplers_to_interconnect_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_interconnect_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_interconnect_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_interconnect_WVALID;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_interconnect_ARADDR(31 downto 0);
M02_AXI_arprot(2 downto 0) <= m02_couplers_to_interconnect_ARPROT(2 downto 0);
M02_AXI_arvalid <= m02_couplers_to_interconnect_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_interconnect_AWADDR(31 downto 0);
M02_AXI_awprot(2 downto 0) <= m02_couplers_to_interconnect_AWPROT(2 downto 0);
M02_AXI_awvalid <= m02_couplers_to_interconnect_AWVALID;
M02_AXI_bready <= m02_couplers_to_interconnect_BREADY;
M02_AXI_rready <= m02_couplers_to_interconnect_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_interconnect_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_interconnect_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_interconnect_WVALID;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_interconnect_ARADDR(31 downto 0);
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_interconnect_ARPROT(2 downto 0);
M03_AXI_arvalid <= m03_couplers_to_interconnect_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_interconnect_AWADDR(31 downto 0);
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_interconnect_AWPROT(2 downto 0);
M03_AXI_awvalid <= m03_couplers_to_interconnect_AWVALID;
M03_AXI_bready <= m03_couplers_to_interconnect_BREADY;
M03_AXI_rready <= m03_couplers_to_interconnect_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_interconnect_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_interconnect_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_interconnect_WVALID;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_interconnect_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_interconnect_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_interconnect_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_interconnect_AWVALID;
M04_AXI_bready <= m04_couplers_to_interconnect_BREADY;
M04_AXI_rready <= m04_couplers_to_interconnect_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_interconnect_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_interconnect_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_interconnect_WVALID;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_interconnect_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_interconnect_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_interconnect_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_interconnect_AWVALID;
M05_AXI_bready <= m05_couplers_to_interconnect_BREADY;
M05_AXI_rready <= m05_couplers_to_interconnect_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_interconnect_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_interconnect_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_interconnect_WVALID;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_interconnect_ARADDR(31 downto 0);
M06_AXI_arvalid <= m06_couplers_to_interconnect_ARVALID;
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_interconnect_AWADDR(31 downto 0);
M06_AXI_awvalid <= m06_couplers_to_interconnect_AWVALID;
M06_AXI_bready <= m06_couplers_to_interconnect_BREADY;
M06_AXI_rready <= m06_couplers_to_interconnect_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_interconnect_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_interconnect_WSTRB(3 downto 0);
M06_AXI_wvalid <= m06_couplers_to_interconnect_WVALID;
S00_AXI_arready <= interconnect_to_s00_couplers_ARREADY;
S00_AXI_awready <= interconnect_to_s00_couplers_AWREADY;
S00_AXI_bresp(1 downto 0) <= interconnect_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= interconnect_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= interconnect_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= interconnect_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= interconnect_to_s00_couplers_RVALID;
S00_AXI_wready <= interconnect_to_s00_couplers_WREADY;
S01_AXI_arready <= interconnect_to_s01_couplers_ARREADY;
S01_AXI_awready <= interconnect_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= interconnect_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= interconnect_to_s01_couplers_BVALID;
S01_AXI_rdata(31 downto 0) <= interconnect_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rresp(1 downto 0) <= interconnect_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid <= interconnect_to_s01_couplers_RVALID;
S01_AXI_wready <= interconnect_to_s01_couplers_WREADY;
S02_AXI_arready <= interconnect_to_s02_couplers_ARREADY;
S02_AXI_awready <= interconnect_to_s02_couplers_AWREADY;
S02_AXI_bid(0) <= interconnect_to_s02_couplers_BID(0);
S02_AXI_bresp(1 downto 0) <= interconnect_to_s02_couplers_BRESP(1 downto 0);
S02_AXI_bvalid <= interconnect_to_s02_couplers_BVALID;
S02_AXI_rdata(31 downto 0) <= interconnect_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rid(0) <= interconnect_to_s02_couplers_RID(0);
S02_AXI_rlast <= interconnect_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= interconnect_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= interconnect_to_s02_couplers_RVALID;
S02_AXI_wready <= interconnect_to_s02_couplers_WREADY;
interconnect_ACLK_net <= ACLK;
interconnect_ARESETN_net <= ARESETN;
interconnect_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
interconnect_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
interconnect_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
interconnect_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
interconnect_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
interconnect_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
interconnect_to_s00_couplers_BREADY <= S00_AXI_bready;
interconnect_to_s00_couplers_RREADY <= S00_AXI_rready;
interconnect_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
interconnect_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
interconnect_to_s00_couplers_WVALID <= S00_AXI_wvalid;
interconnect_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
interconnect_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
interconnect_to_s01_couplers_ARVALID <= S01_AXI_arvalid;
interconnect_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
interconnect_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
interconnect_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
interconnect_to_s01_couplers_BREADY <= S01_AXI_bready;
interconnect_to_s01_couplers_RREADY <= S01_AXI_rready;
interconnect_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
interconnect_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
interconnect_to_s01_couplers_WVALID <= S01_AXI_wvalid;
interconnect_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
interconnect_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
interconnect_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
interconnect_to_s02_couplers_ARID(0) <= S02_AXI_arid(0);
interconnect_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
interconnect_to_s02_couplers_ARLOCK <= S02_AXI_arlock;
interconnect_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
interconnect_to_s02_couplers_ARQOS(3 downto 0) <= S02_AXI_arqos(3 downto 0);
interconnect_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
interconnect_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
interconnect_to_s02_couplers_AWADDR(31 downto 0) <= S02_AXI_awaddr(31 downto 0);
interconnect_to_s02_couplers_AWBURST(1 downto 0) <= S02_AXI_awburst(1 downto 0);
interconnect_to_s02_couplers_AWCACHE(3 downto 0) <= S02_AXI_awcache(3 downto 0);
interconnect_to_s02_couplers_AWID(0) <= S02_AXI_awid(0);
interconnect_to_s02_couplers_AWLEN(7 downto 0) <= S02_AXI_awlen(7 downto 0);
interconnect_to_s02_couplers_AWLOCK <= S02_AXI_awlock;
interconnect_to_s02_couplers_AWPROT(2 downto 0) <= S02_AXI_awprot(2 downto 0);
interconnect_to_s02_couplers_AWQOS(3 downto 0) <= S02_AXI_awqos(3 downto 0);
interconnect_to_s02_couplers_AWSIZE(2 downto 0) <= S02_AXI_awsize(2 downto 0);
interconnect_to_s02_couplers_AWVALID <= S02_AXI_awvalid;
interconnect_to_s02_couplers_BREADY <= S02_AXI_bready;
interconnect_to_s02_couplers_RREADY <= S02_AXI_rready;
interconnect_to_s02_couplers_WDATA(31 downto 0) <= S02_AXI_wdata(31 downto 0);
interconnect_to_s02_couplers_WLAST <= S02_AXI_wlast;
interconnect_to_s02_couplers_WSTRB(3 downto 0) <= S02_AXI_wstrb(3 downto 0);
interconnect_to_s02_couplers_WVALID <= S02_AXI_wvalid;
m00_couplers_to_interconnect_ARREADY <= M00_AXI_arready;
m00_couplers_to_interconnect_AWREADY <= M00_AXI_awready;
m00_couplers_to_interconnect_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_interconnect_BVALID <= M00_AXI_bvalid;
m00_couplers_to_interconnect_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_interconnect_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_interconnect_RVALID <= M00_AXI_rvalid;
m00_couplers_to_interconnect_WREADY <= M00_AXI_wready;
m01_couplers_to_interconnect_ARREADY <= M01_AXI_arready;
m01_couplers_to_interconnect_AWREADY <= M01_AXI_awready;
m01_couplers_to_interconnect_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_interconnect_BVALID <= M01_AXI_bvalid;
m01_couplers_to_interconnect_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_interconnect_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_interconnect_RVALID <= M01_AXI_rvalid;
m01_couplers_to_interconnect_WREADY <= M01_AXI_wready;
m02_couplers_to_interconnect_ARREADY <= M02_AXI_arready;
m02_couplers_to_interconnect_AWREADY <= M02_AXI_awready;
m02_couplers_to_interconnect_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_interconnect_BVALID <= M02_AXI_bvalid;
m02_couplers_to_interconnect_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_interconnect_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_interconnect_RVALID <= M02_AXI_rvalid;
m02_couplers_to_interconnect_WREADY <= M02_AXI_wready;
m03_couplers_to_interconnect_ARREADY <= M03_AXI_arready;
m03_couplers_to_interconnect_AWREADY <= M03_AXI_awready;
m03_couplers_to_interconnect_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_interconnect_BVALID <= M03_AXI_bvalid;
m03_couplers_to_interconnect_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_interconnect_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_interconnect_RVALID <= M03_AXI_rvalid;
m03_couplers_to_interconnect_WREADY <= M03_AXI_wready;
m04_couplers_to_interconnect_ARREADY <= M04_AXI_arready;
m04_couplers_to_interconnect_AWREADY <= M04_AXI_awready;
m04_couplers_to_interconnect_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_interconnect_BVALID <= M04_AXI_bvalid;
m04_couplers_to_interconnect_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_interconnect_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_interconnect_RVALID <= M04_AXI_rvalid;
m04_couplers_to_interconnect_WREADY <= M04_AXI_wready;
m05_couplers_to_interconnect_ARREADY <= M05_AXI_arready;
m05_couplers_to_interconnect_AWREADY <= M05_AXI_awready;
m05_couplers_to_interconnect_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_interconnect_BVALID <= M05_AXI_bvalid;
m05_couplers_to_interconnect_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_interconnect_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_interconnect_RVALID <= M05_AXI_rvalid;
m05_couplers_to_interconnect_WREADY <= M05_AXI_wready;
m06_couplers_to_interconnect_ARREADY <= M06_AXI_arready;
m06_couplers_to_interconnect_AWREADY <= M06_AXI_awready;
m06_couplers_to_interconnect_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_interconnect_BVALID <= M06_AXI_bvalid;
m06_couplers_to_interconnect_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_interconnect_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_interconnect_RVALID <= M06_AXI_rvalid;
m06_couplers_to_interconnect_WREADY <= M06_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_4EB6IN
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m00_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m00_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m00_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m00_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m00_couplers_to_interconnect_AWVALID,
M_AXI_bready => m00_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1SL2GIW
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m01_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m01_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m01_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m01_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m01_couplers_to_interconnect_AWVALID,
M_AXI_bready => m01_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_7DG2C0
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m02_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m02_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m02_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m02_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m02_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m02_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m02_couplers_to_interconnect_AWVALID,
M_AXI_bready => m02_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1YCPS1Z
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m03_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m03_couplers_to_interconnect_ARPROT(2 downto 0),
M_AXI_arready => m03_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m03_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m03_couplers_to_interconnect_AWPROT(2 downto 0),
M_AXI_awready => m03_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m03_couplers_to_interconnect_AWVALID,
M_AXI_bready => m03_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_ACM7VL
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m04_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m04_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m04_couplers_to_interconnect_AWVALID,
M_AXI_bready => m04_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_1HWY5FA
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m05_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m05_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m05_couplers_to_interconnect_AWVALID,
M_AXI_bready => m05_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_DBR4EM
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => m06_couplers_to_interconnect_ARADDR(31 downto 0),
M_AXI_arready => m06_couplers_to_interconnect_ARREADY,
M_AXI_arvalid => m06_couplers_to_interconnect_ARVALID,
M_AXI_awaddr(31 downto 0) => m06_couplers_to_interconnect_AWADDR(31 downto 0),
M_AXI_awready => m06_couplers_to_interconnect_AWREADY,
M_AXI_awvalid => m06_couplers_to_interconnect_AWVALID,
M_AXI_bready => m06_couplers_to_interconnect_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_interconnect_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_interconnect_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_interconnect_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_interconnect_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_interconnect_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_interconnect_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_interconnect_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_interconnect_WREADY,
M_AXI_wstrb(3 downto 0) => m06_couplers_to_interconnect_WSTRB(3 downto 0),
M_AXI_wvalid => m06_couplers_to_interconnect_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_7XIH8P
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s00_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s00_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s00_couplers_AWVALID,
S_AXI_bready => interconnect_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s00_couplers_WVALID
);
s01_couplers: entity work.s01_couplers_imp_1XSI6OU
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arvalid => s01_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_rdata(31 downto 0) => s01_couplers_to_xbar_RDATA(63 downto 32),
M_AXI_rready => s01_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid => s01_couplers_to_xbar_RVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => interconnect_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arready => interconnect_to_s01_couplers_ARREADY,
S_AXI_arvalid => interconnect_to_s01_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => interconnect_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => interconnect_to_s01_couplers_AWREADY,
S_AXI_awvalid => interconnect_to_s01_couplers_AWVALID,
S_AXI_bready => interconnect_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rready => interconnect_to_s01_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wready => interconnect_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_2QLUHY
port map (
M_ACLK => interconnect_ACLK_net,
M_ARESETN => interconnect_ARESETN_net,
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s02_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s02_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s02_couplers_to_xbar_AWREADY(2),
M_AXI_awvalid => s02_couplers_to_xbar_AWVALID,
M_AXI_bready => s02_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s02_couplers_to_xbar_BRESP(5 downto 4),
M_AXI_bvalid => s02_couplers_to_xbar_BVALID(2),
M_AXI_rdata(31 downto 0) => s02_couplers_to_xbar_RDATA(95 downto 64),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
M_AXI_wdata(31 downto 0) => s02_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s02_couplers_to_xbar_WREADY(2),
M_AXI_wstrb(3 downto 0) => s02_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s02_couplers_to_xbar_WVALID,
S_ACLK => interconnect_ACLK_net,
S_ARESETN => interconnect_ARESETN_net,
S_AXI_araddr(31 downto 0) => interconnect_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => interconnect_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => interconnect_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => interconnect_to_s02_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => interconnect_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arlock => interconnect_to_s02_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => interconnect_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => interconnect_to_s02_couplers_ARQOS(3 downto 0),
S_AXI_arready => interconnect_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => interconnect_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => interconnect_to_s02_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => interconnect_to_s02_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => interconnect_to_s02_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => interconnect_to_s02_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => interconnect_to_s02_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => interconnect_to_s02_couplers_AWLEN(7 downto 0),
S_AXI_awlock => interconnect_to_s02_couplers_AWLOCK,
S_AXI_awprot(2 downto 0) => interconnect_to_s02_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => interconnect_to_s02_couplers_AWQOS(3 downto 0),
S_AXI_awready => interconnect_to_s02_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => interconnect_to_s02_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => interconnect_to_s02_couplers_AWVALID,
S_AXI_bid(0) => interconnect_to_s02_couplers_BID(0),
S_AXI_bready => interconnect_to_s02_couplers_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_to_s02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_to_s02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => interconnect_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => interconnect_to_s02_couplers_RID(0),
S_AXI_rlast => interconnect_to_s02_couplers_RLAST,
S_AXI_rready => interconnect_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_to_s02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => interconnect_to_s02_couplers_WDATA(31 downto 0),
S_AXI_wlast => interconnect_to_s02_couplers_WLAST,
S_AXI_wready => interconnect_to_s02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => interconnect_to_s02_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => interconnect_to_s02_couplers_WVALID
);
xbar: component DemoInterconnect_xbar_0
port map (
aclk => interconnect_ACLK_net,
aresetn => interconnect_ARESETN_net,
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 12) => NLW_xbar_m_axi_arprot_UNCONNECTED(20 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 12) => NLW_xbar_m_axi_awprot_UNCONNECTED(20 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(95 downto 64) => s02_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(8 downto 6) => s02_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(2) => s02_couplers_to_xbar_AWREADY(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(2) => s02_couplers_to_xbar_AWVALID,
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(2) => s02_couplers_to_xbar_BREADY,
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(5 downto 4) => s02_couplers_to_xbar_BRESP(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(2) => s02_couplers_to_xbar_BVALID(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(95 downto 64) => s02_couplers_to_xbar_RDATA(95 downto 64),
s_axi_rdata(63 downto 32) => s01_couplers_to_xbar_RDATA(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => s01_couplers_to_xbar_RREADY,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(95 downto 64) => s02_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(2) => s02_couplers_to_xbar_WREADY(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(11 downto 8) => s02_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(2) => s02_couplers_to_xbar_WVALID,
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DemoInterconnect is
port (
LED0_pll_aclk : out STD_LOGIC;
LED1_pll_uart : out STD_LOGIC;
LED2_pll_lock : out STD_LOGIC;
UART_RX_0 : in STD_LOGIC;
UART_RX_1 : in STD_LOGIC;
UART_TX_0 : out STD_LOGIC;
UART_TX_1 : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_miso_1 : in STD_LOGIC;
m_spi_miso_2 : in STD_LOGIC;
m_spi_miso_3 : in STD_LOGIC;
m_spi_mosi : out STD_LOGIC;
m_spi_mosi_1 : out STD_LOGIC;
m_spi_mosi_2 : out STD_LOGIC;
m_spi_mosi_3 : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
m_spi_sclk_1 : out STD_LOGIC;
m_spi_sclk_2 : out STD_LOGIC;
m_spi_sclk_3 : out STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_ss_1 : out STD_LOGIC;
m_spi_ss_2 : out STD_LOGIC;
m_spi_ss_3 : out STD_LOGIC;
sys_clk : in STD_LOGIC;
sys_reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of DemoInterconnect : entity is "DemoInterconnect,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=DemoInterconnect,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=25,numReposBlks=14,numNonXlnxBlks=8,numHierBlks=11,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=6,da_board_cnt=5,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of DemoInterconnect : entity is "DemoInterconnect.hwdef";
end DemoInterconnect;
architecture STRUCTURE of DemoInterconnect is
component DemoInterconnect_clk_wiz_0_0 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
aclk : out STD_LOGIC;
uart : out STD_LOGIC;
locked : out STD_LOGIC
);
end component DemoInterconnect_clk_wiz_0_0;
component DemoInterconnect_jtag_axi_0_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC;
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC;
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component DemoInterconnect_jtag_axi_0_0;
component DemoInterconnect_mutex_0_0 is
port (
S0_AXI_ACLK : in STD_LOGIC;
S0_AXI_ARESETN : in STD_LOGIC;
S0_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_AWVALID : in STD_LOGIC;
S0_AXI_AWREADY : out STD_LOGIC;
S0_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S0_AXI_WVALID : in STD_LOGIC;
S0_AXI_WREADY : out STD_LOGIC;
S0_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_BVALID : out STD_LOGIC;
S0_AXI_BREADY : in STD_LOGIC;
S0_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_ARVALID : in STD_LOGIC;
S0_AXI_ARREADY : out STD_LOGIC;
S0_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S0_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S0_AXI_RVALID : out STD_LOGIC;
S0_AXI_RREADY : in STD_LOGIC;
S1_AXI_ACLK : in STD_LOGIC;
S1_AXI_ARESETN : in STD_LOGIC;
S1_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_AWVALID : in STD_LOGIC;
S1_AXI_AWREADY : out STD_LOGIC;
S1_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S1_AXI_WVALID : in STD_LOGIC;
S1_AXI_WREADY : out STD_LOGIC;
S1_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_BVALID : out STD_LOGIC;
S1_AXI_BREADY : in STD_LOGIC;
S1_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_ARVALID : in STD_LOGIC;
S1_AXI_ARREADY : out STD_LOGIC;
S1_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S1_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S1_AXI_RVALID : out STD_LOGIC;
S1_AXI_RREADY : in STD_LOGIC;
S2_AXI_ACLK : in STD_LOGIC;
S2_AXI_ARESETN : in STD_LOGIC;
S2_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_AWVALID : in STD_LOGIC;
S2_AXI_AWREADY : out STD_LOGIC;
S2_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S2_AXI_WVALID : in STD_LOGIC;
S2_AXI_WREADY : out STD_LOGIC;
S2_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_BVALID : out STD_LOGIC;
S2_AXI_BREADY : in STD_LOGIC;
S2_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_ARVALID : in STD_LOGIC;
S2_AXI_ARREADY : out STD_LOGIC;
S2_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S2_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S2_AXI_RVALID : out STD_LOGIC;
S2_AXI_RREADY : in STD_LOGIC
);
end component DemoInterconnect_mutex_0_0;
component DemoInterconnect_uart_transceiver_0_0 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_0;
component DemoInterconnect_uart_transceiver_0_1 is
port (
i_Clk : in STD_LOGIC;
i_RX_Serial : in STD_LOGIC;
o_RX_Done : out STD_LOGIC;
o_RX_Byte : out STD_LOGIC_VECTOR ( 7 downto 0 );
i_TX_Load : in STD_LOGIC;
i_TX_Byte : in STD_LOGIC_VECTOR ( 7 downto 0 );
o_TX_Active : out STD_LOGIC;
o_TX_Serial : out STD_LOGIC;
o_TX_Done : out STD_LOGIC
);
end component DemoInterconnect_uart_transceiver_0_1;
component DemoInterconnect_axi_spi_master_0_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_0;
component DemoInterconnect_axi_spi_master_0_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_0_1;
component DemoInterconnect_axi_spi_master_1_0 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_0;
component DemoInterconnect_axi_spi_master_1_1 is
port (
m_spi_mosi : out STD_LOGIC;
m_spi_miso : in STD_LOGIC;
m_spi_ss : out STD_LOGIC;
m_spi_sclk : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_axi_spi_master_1_1;
component DemoInterconnect_ila_0_0 is
port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component DemoInterconnect_ila_0_0;
component DemoInterconnect_internoc_ni_axi_master_0_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_0_0;
component DemoInterconnect_internoc_ni_axi_master_1_0 is
port (
if00_data_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_in : in STD_LOGIC;
if00_data_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
if00_load_out : out STD_LOGIC;
if00_send_done : in STD_LOGIC;
if00_send_busy : in STD_LOGIC;
m00_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_awvalid : out STD_LOGIC;
m00_axi_awready : in STD_LOGIC;
m00_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m00_axi_wvalid : out STD_LOGIC;
m00_axi_wready : in STD_LOGIC;
m00_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_bvalid : in STD_LOGIC;
m00_axi_bready : out STD_LOGIC;
m00_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m00_axi_arvalid : out STD_LOGIC;
m00_axi_arready : in STD_LOGIC;
m00_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m00_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m00_axi_rvalid : in STD_LOGIC;
m00_axi_rready : out STD_LOGIC;
m00_axi_aclk : in STD_LOGIC;
m00_axi_aresetn : in STD_LOGIC
);
end component DemoInterconnect_internoc_ni_axi_master_1_0;
signal UART_RX_0_1 : STD_LOGIC;
signal UART_RX_1_1 : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M05_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M05_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M05_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M06_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M06_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M06_AXI_WVALID : STD_LOGIC;
signal axi_spi_master_0_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_0_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_0_m_spi_ss : STD_LOGIC;
signal axi_spi_master_1_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_1_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_1_m_spi_ss : STD_LOGIC;
signal axi_spi_master_2_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_2_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_2_m_spi_ss : STD_LOGIC;
signal axi_spi_master_3_m_spi_mosi : STD_LOGIC;
signal axi_spi_master_3_m_spi_sclk : STD_LOGIC;
signal axi_spi_master_3_m_spi_ss : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_0_locked : STD_LOGIC;
signal clk_wiz_0_uart : STD_LOGIC;
signal interface_axi_master_0_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interface_axi_master_0_if00_load_out : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_0_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_ARREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_ARVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_AWREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_AWVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_BVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_RVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WREADY : STD_LOGIC;
signal internoc_ni_axi_master_1_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal internoc_ni_axi_master_1_M00_AXI_WVALID : STD_LOGIC;
signal internoc_ni_axi_master_1_if00_data_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal internoc_ni_axi_master_1_if00_load_out : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_ARLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_ARREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_ARVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal jtag_axi_0_M_AXI_AWLOCK : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_AWREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal jtag_axi_0_M_AXI_AWVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_BREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_BVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal jtag_axi_0_M_AXI_RLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_RREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal jtag_axi_0_M_AXI_RVALID : STD_LOGIC;
signal jtag_axi_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal jtag_axi_0_M_AXI_WLAST : STD_LOGIC;
signal jtag_axi_0_M_AXI_WREADY : STD_LOGIC;
signal jtag_axi_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal jtag_axi_0_M_AXI_WVALID : STD_LOGIC;
signal \^m_spi_miso_1\ : STD_LOGIC;
signal m_spi_miso_1_1 : STD_LOGIC;
signal m_spi_miso_2_1 : STD_LOGIC;
signal m_spi_miso_3_1 : STD_LOGIC;
signal sys_clk_1 : STD_LOGIC;
signal uart_transceiver_0_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_0_o_RX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Active : STD_LOGIC;
signal uart_transceiver_0_o_TX_Done : STD_LOGIC;
signal uart_transceiver_0_o_TX_Serial : STD_LOGIC;
signal uart_transceiver_1_o_RX_Byte : STD_LOGIC_VECTOR ( 7 downto 0 );
signal uart_transceiver_1_o_RX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Active : STD_LOGIC;
signal uart_transceiver_1_o_TX_Done : STD_LOGIC;
signal uart_transceiver_1_o_TX_Serial : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of UART_RX_0 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_0 DATA";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of UART_RX_0 : signal is "XIL_INTERFACENAME DATA.UART_RX_0, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_RX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_RX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_RX_1 : signal is "XIL_INTERFACENAME DATA.UART_RX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of UART_TX_1 : signal is "xilinx.com:signal:data:1.0 DATA.UART_TX_1 DATA";
attribute X_INTERFACE_PARAMETER of UART_TX_1 : signal is "XIL_INTERFACENAME DATA.UART_TX_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_miso_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MISO_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_miso_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MISO_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_1 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_1 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_1 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_1, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_2 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_2 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_2 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_2, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_mosi_3 : signal is "xilinx.com:signal:data:1.0 DATA.M_SPI_MOSI_3 DATA";
attribute X_INTERFACE_PARAMETER of m_spi_mosi_3 : signal is "XIL_INTERFACENAME DATA.M_SPI_MOSI_3, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of m_spi_sclk : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_1 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_1 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_1 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_1, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_2 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_2 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_2 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_2, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_0_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_sclk_3 : signal is "xilinx.com:signal:clock:1.0 CLK.M_SPI_SCLK_3 CLK";
attribute X_INTERFACE_PARAMETER of m_spi_sclk_3 : signal is "XIL_INTERFACENAME CLK.M_SPI_SCLK_3, CLK_DOMAIN DemoInterconnect_axi_spi_master_1_1_m_spi_sclk, FREQ_HZ 100000000, PHASE 0.000";
attribute X_INTERFACE_INFO of m_spi_ss : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss : signal is "XIL_INTERFACENAME CE.M_SPI_SS, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_1 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_1 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_1 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_1, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_2 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_2 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_2 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_2, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_spi_ss_3 : signal is "xilinx.com:signal:clockenable:1.0 CE.M_SPI_SS_3 CE";
attribute X_INTERFACE_PARAMETER of m_spi_ss_3 : signal is "XIL_INTERFACENAME CE.M_SPI_SS_3, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK";
attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME CLK.SYS_CLK, ASSOCIATED_RESET sys_reset, CLK_DOMAIN DemoInterconnect_sys_clk, FREQ_HZ 12000000, PHASE 0.000";
attribute X_INTERFACE_INFO of sys_reset : signal is "xilinx.com:signal:reset:1.0 RST.SYS_RESET RST";
attribute X_INTERFACE_PARAMETER of sys_reset : signal is "XIL_INTERFACENAME RST.SYS_RESET, POLARITY ACTIVE_HIGH";
begin
LED0_pll_aclk <= clk_wiz_0_clk_out1;
LED1_pll_uart <= clk_wiz_0_uart;
LED2_pll_lock <= clk_wiz_0_locked;
UART_RX_0_1 <= UART_RX_0;
UART_RX_1_1 <= UART_RX_1;
UART_TX_0 <= uart_transceiver_0_o_TX_Serial;
UART_TX_1 <= uart_transceiver_1_o_TX_Serial;
\^m_spi_miso_1\ <= m_spi_miso;
m_spi_miso_1_1 <= m_spi_miso_1;
m_spi_miso_2_1 <= m_spi_miso_2;
m_spi_miso_3_1 <= m_spi_miso_3;
m_spi_mosi <= axi_spi_master_0_m_spi_mosi;
m_spi_mosi_1 <= axi_spi_master_1_m_spi_mosi;
m_spi_mosi_2 <= axi_spi_master_2_m_spi_mosi;
m_spi_mosi_3 <= axi_spi_master_3_m_spi_mosi;
m_spi_sclk <= axi_spi_master_0_m_spi_sclk;
m_spi_sclk_1 <= axi_spi_master_1_m_spi_sclk;
m_spi_sclk_2 <= axi_spi_master_2_m_spi_sclk;
m_spi_sclk_3 <= axi_spi_master_3_m_spi_sclk;
m_spi_ss <= axi_spi_master_0_m_spi_ss;
m_spi_ss_1 <= axi_spi_master_1_m_spi_ss;
m_spi_ss_2 <= axi_spi_master_2_m_spi_ss;
m_spi_ss_3 <= axi_spi_master_3_m_spi_ss;
sys_clk_1 <= sys_clk;
axi_spi_master_0: component DemoInterconnect_axi_spi_master_0_0
port map (
m_spi_miso => \^m_spi_miso_1\,
m_spi_mosi => axi_spi_master_0_m_spi_mosi,
m_spi_sclk => axi_spi_master_0_m_spi_sclk,
m_spi_ss => axi_spi_master_0_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID
);
axi_spi_master_1: component DemoInterconnect_axi_spi_master_0_1
port map (
m_spi_miso => m_spi_miso_1_1,
m_spi_mosi => axi_spi_master_1_m_spi_mosi,
m_spi_sclk => axi_spi_master_1_m_spi_sclk,
m_spi_ss => axi_spi_master_1_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
axi_spi_master_2: component DemoInterconnect_axi_spi_master_1_0
port map (
m_spi_miso => m_spi_miso_2_1,
m_spi_mosi => axi_spi_master_2_m_spi_mosi,
m_spi_sclk => axi_spi_master_2_m_spi_sclk,
m_spi_ss => axi_spi_master_2_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
axi_spi_master_3: component DemoInterconnect_axi_spi_master_1_1
port map (
m_spi_miso => m_spi_miso_3_1,
m_spi_mosi => axi_spi_master_3_m_spi_mosi,
m_spi_sclk => axi_spi_master_3_m_spi_sclk,
m_spi_ss => axi_spi_master_3_m_spi_ss,
s00_axi_aclk => clk_wiz_0_clk_out1,
s00_axi_araddr(3 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => clk_wiz_0_locked,
s00_axi_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
s00_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
s00_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
s00_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
s00_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
s00_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
s00_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
s00_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
s00_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
s00_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
s00_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
s00_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
s00_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
s00_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
clk_wiz_0: component DemoInterconnect_clk_wiz_0_0
port map (
aclk => clk_wiz_0_clk_out1,
clk_in1 => sys_clk_1,
locked => clk_wiz_0_locked,
reset => sys_reset,
uart => clk_wiz_0_uart
);
ila_0: component DemoInterconnect_ila_0_0
port map (
clk => clk_wiz_0_clk_out1,
probe0(0) => uart_transceiver_0_o_RX_Done,
probe1(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
probe2(0) => interface_axi_master_0_if00_load_out,
probe3(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0)
);
interconnect: entity work.DemoInterconnect_axi_interconnect_0_0
port map (
ACLK => clk_wiz_0_clk_out1,
ARESETN => clk_wiz_0_locked,
M00_ACLK => clk_wiz_0_clk_out1,
M00_ARESETN => clk_wiz_0_locked,
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => clk_wiz_0_clk_out1,
M01_ARESETN => clk_wiz_0_locked,
M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arprot(2 downto 0) => axi_interconnect_0_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awprot(2 downto 0) => axi_interconnect_0_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
M02_ACLK => clk_wiz_0_clk_out1,
M02_ARESETN => clk_wiz_0_locked,
M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arprot(2 downto 0) => axi_interconnect_0_M02_AXI_ARPROT(2 downto 0),
M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awprot(2 downto 0) => axi_interconnect_0_M02_AXI_AWPROT(2 downto 0),
M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_out1,
M03_ARESETN => clk_wiz_0_locked,
M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arprot(2 downto 0) => axi_interconnect_0_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awprot(2 downto 0) => axi_interconnect_0_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
M04_ACLK => clk_wiz_0_clk_out1,
M04_ARESETN => clk_wiz_0_locked,
M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
M05_ACLK => clk_wiz_0_clk_out1,
M05_ARESETN => clk_wiz_0_locked,
M05_AXI_araddr(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => axi_interconnect_0_M05_AXI_ARREADY,
M05_AXI_arvalid => axi_interconnect_0_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => axi_interconnect_0_M05_AXI_AWREADY,
M05_AXI_awvalid => axi_interconnect_0_M05_AXI_AWVALID,
M05_AXI_bready => axi_interconnect_0_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => axi_interconnect_0_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => axi_interconnect_0_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => axi_interconnect_0_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => axi_interconnect_0_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => axi_interconnect_0_M05_AXI_WVALID,
M06_ACLK => clk_wiz_0_clk_out1,
M06_ARESETN => clk_wiz_0_locked,
M06_AXI_araddr(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready => axi_interconnect_0_M06_AXI_ARREADY,
M06_AXI_arvalid => axi_interconnect_0_M06_AXI_ARVALID,
M06_AXI_awaddr(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready => axi_interconnect_0_M06_AXI_AWREADY,
M06_AXI_awvalid => axi_interconnect_0_M06_AXI_AWVALID,
M06_AXI_bready => axi_interconnect_0_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => axi_interconnect_0_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => axi_interconnect_0_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => axi_interconnect_0_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => axi_interconnect_0_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid => axi_interconnect_0_M06_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_out1,
S00_ARESETN => clk_wiz_0_locked,
S00_AXI_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
S00_AXI_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
S00_AXI_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
S00_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
S00_AXI_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
S00_AXI_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
S00_AXI_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
S00_AXI_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
S00_AXI_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
S00_AXI_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
S00_AXI_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
S00_AXI_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
S00_AXI_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
S00_AXI_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
S00_AXI_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
S00_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
S00_AXI_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID,
S01_ACLK => clk_wiz_0_clk_out1,
S01_ARESETN => clk_wiz_0_locked,
S01_AXI_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
S01_AXI_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
S01_AXI_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
S01_AXI_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
S01_AXI_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
S01_AXI_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
S01_AXI_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
S01_AXI_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
S01_AXI_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
S01_AXI_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
S01_AXI_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
S01_AXI_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
S01_AXI_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
S01_AXI_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
S01_AXI_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
S01_AXI_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
S01_AXI_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
S01_AXI_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
S01_AXI_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID,
S02_ACLK => clk_wiz_0_clk_out1,
S02_ARESETN => clk_wiz_0_locked,
S02_AXI_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
S02_AXI_arid(0) => jtag_axi_0_M_AXI_ARID(0),
S02_AXI_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
S02_AXI_arlock => jtag_axi_0_M_AXI_ARLOCK,
S02_AXI_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
S02_AXI_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
S02_AXI_arready => jtag_axi_0_M_AXI_ARREADY,
S02_AXI_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
S02_AXI_arvalid => jtag_axi_0_M_AXI_ARVALID,
S02_AXI_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
S02_AXI_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
S02_AXI_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
S02_AXI_awid(0) => jtag_axi_0_M_AXI_AWID(0),
S02_AXI_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
S02_AXI_awlock => jtag_axi_0_M_AXI_AWLOCK,
S02_AXI_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
S02_AXI_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
S02_AXI_awready => jtag_axi_0_M_AXI_AWREADY,
S02_AXI_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
S02_AXI_awvalid => jtag_axi_0_M_AXI_AWVALID,
S02_AXI_bid(0) => jtag_axi_0_M_AXI_BID(0),
S02_AXI_bready => jtag_axi_0_M_AXI_BREADY,
S02_AXI_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
S02_AXI_bvalid => jtag_axi_0_M_AXI_BVALID,
S02_AXI_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
S02_AXI_rid(0) => jtag_axi_0_M_AXI_RID(0),
S02_AXI_rlast => jtag_axi_0_M_AXI_RLAST,
S02_AXI_rready => jtag_axi_0_M_AXI_RREADY,
S02_AXI_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
S02_AXI_rvalid => jtag_axi_0_M_AXI_RVALID,
S02_AXI_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
S02_AXI_wlast => jtag_axi_0_M_AXI_WLAST,
S02_AXI_wready => jtag_axi_0_M_AXI_WREADY,
S02_AXI_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
S02_AXI_wvalid => jtag_axi_0_M_AXI_WVALID
);
internoc_ni_axi_master_0: component DemoInterconnect_internoc_ni_axi_master_0_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_0_o_RX_Done,
if00_load_out => interface_axi_master_0_if00_load_out,
if00_send_busy => uart_transceiver_0_o_TX_Active,
if00_send_done => uart_transceiver_0_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_0_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_0_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_0_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_0_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_0_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_0_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_0_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_0_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_0_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_0_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_0_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_0_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_0_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_0_M00_AXI_WVALID
);
internoc_ni_axi_master_1: component DemoInterconnect_internoc_ni_axi_master_1_0
port map (
if00_data_in(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
if00_data_out(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
if00_load_in => uart_transceiver_1_o_RX_Done,
if00_load_out => internoc_ni_axi_master_1_if00_load_out,
if00_send_busy => uart_transceiver_1_o_TX_Active,
if00_send_done => uart_transceiver_1_o_TX_Done,
m00_axi_aclk => clk_wiz_0_clk_out1,
m00_axi_araddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARADDR(31 downto 0),
m00_axi_aresetn => clk_wiz_0_locked,
m00_axi_arprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_ARPROT(2 downto 0),
m00_axi_arready => internoc_ni_axi_master_1_M00_AXI_ARREADY,
m00_axi_arvalid => internoc_ni_axi_master_1_M00_AXI_ARVALID,
m00_axi_awaddr(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWADDR(31 downto 0),
m00_axi_awprot(2 downto 0) => internoc_ni_axi_master_1_M00_AXI_AWPROT(2 downto 0),
m00_axi_awready => internoc_ni_axi_master_1_M00_AXI_AWREADY,
m00_axi_awvalid => internoc_ni_axi_master_1_M00_AXI_AWVALID,
m00_axi_bready => internoc_ni_axi_master_1_M00_AXI_BREADY,
m00_axi_bresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_BRESP(1 downto 0),
m00_axi_bvalid => internoc_ni_axi_master_1_M00_AXI_BVALID,
m00_axi_rdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_RDATA(31 downto 0),
m00_axi_rready => internoc_ni_axi_master_1_M00_AXI_RREADY,
m00_axi_rresp(1 downto 0) => internoc_ni_axi_master_1_M00_AXI_RRESP(1 downto 0),
m00_axi_rvalid => internoc_ni_axi_master_1_M00_AXI_RVALID,
m00_axi_wdata(31 downto 0) => internoc_ni_axi_master_1_M00_AXI_WDATA(31 downto 0),
m00_axi_wready => internoc_ni_axi_master_1_M00_AXI_WREADY,
m00_axi_wstrb(3 downto 0) => internoc_ni_axi_master_1_M00_AXI_WSTRB(3 downto 0),
m00_axi_wvalid => internoc_ni_axi_master_1_M00_AXI_WVALID
);
jtag_axi_0: component DemoInterconnect_jtag_axi_0_0
port map (
aclk => clk_wiz_0_clk_out1,
aresetn => clk_wiz_0_locked,
m_axi_araddr(31 downto 0) => jtag_axi_0_M_AXI_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => jtag_axi_0_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => jtag_axi_0_M_AXI_ARCACHE(3 downto 0),
m_axi_arid(0) => jtag_axi_0_M_AXI_ARID(0),
m_axi_arlen(7 downto 0) => jtag_axi_0_M_AXI_ARLEN(7 downto 0),
m_axi_arlock => jtag_axi_0_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => jtag_axi_0_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => jtag_axi_0_M_AXI_ARQOS(3 downto 0),
m_axi_arready => jtag_axi_0_M_AXI_ARREADY,
m_axi_arsize(2 downto 0) => jtag_axi_0_M_AXI_ARSIZE(2 downto 0),
m_axi_arvalid => jtag_axi_0_M_AXI_ARVALID,
m_axi_awaddr(31 downto 0) => jtag_axi_0_M_AXI_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => jtag_axi_0_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => jtag_axi_0_M_AXI_AWCACHE(3 downto 0),
m_axi_awid(0) => jtag_axi_0_M_AXI_AWID(0),
m_axi_awlen(7 downto 0) => jtag_axi_0_M_AXI_AWLEN(7 downto 0),
m_axi_awlock => jtag_axi_0_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => jtag_axi_0_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => jtag_axi_0_M_AXI_AWQOS(3 downto 0),
m_axi_awready => jtag_axi_0_M_AXI_AWREADY,
m_axi_awsize(2 downto 0) => jtag_axi_0_M_AXI_AWSIZE(2 downto 0),
m_axi_awvalid => jtag_axi_0_M_AXI_AWVALID,
m_axi_bid(0) => jtag_axi_0_M_AXI_BID(0),
m_axi_bready => jtag_axi_0_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => jtag_axi_0_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => jtag_axi_0_M_AXI_BVALID,
m_axi_rdata(31 downto 0) => jtag_axi_0_M_AXI_RDATA(31 downto 0),
m_axi_rid(0) => jtag_axi_0_M_AXI_RID(0),
m_axi_rlast => jtag_axi_0_M_AXI_RLAST,
m_axi_rready => jtag_axi_0_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => jtag_axi_0_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => jtag_axi_0_M_AXI_RVALID,
m_axi_wdata(31 downto 0) => jtag_axi_0_M_AXI_WDATA(31 downto 0),
m_axi_wlast => jtag_axi_0_M_AXI_WLAST,
m_axi_wready => jtag_axi_0_M_AXI_WREADY,
m_axi_wstrb(3 downto 0) => jtag_axi_0_M_AXI_WSTRB(3 downto 0),
m_axi_wvalid => jtag_axi_0_M_AXI_WVALID
);
master_comm_mutex: component DemoInterconnect_mutex_0_0
port map (
S0_AXI_ACLK => clk_wiz_0_clk_out1,
S0_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
S0_AXI_ARESETN => clk_wiz_0_locked,
S0_AXI_ARREADY => axi_interconnect_0_M04_AXI_ARREADY,
S0_AXI_ARVALID => axi_interconnect_0_M04_AXI_ARVALID,
S0_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
S0_AXI_AWREADY => axi_interconnect_0_M04_AXI_AWREADY,
S0_AXI_AWVALID => axi_interconnect_0_M04_AXI_AWVALID,
S0_AXI_BREADY => axi_interconnect_0_M04_AXI_BREADY,
S0_AXI_BRESP(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
S0_AXI_BVALID => axi_interconnect_0_M04_AXI_BVALID,
S0_AXI_RDATA(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
S0_AXI_RREADY => axi_interconnect_0_M04_AXI_RREADY,
S0_AXI_RRESP(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
S0_AXI_RVALID => axi_interconnect_0_M04_AXI_RVALID,
S0_AXI_WDATA(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
S0_AXI_WREADY => axi_interconnect_0_M04_AXI_WREADY,
S0_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
S0_AXI_WVALID => axi_interconnect_0_M04_AXI_WVALID,
S1_AXI_ACLK => clk_wiz_0_clk_out1,
S1_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M05_AXI_ARADDR(31 downto 0),
S1_AXI_ARESETN => clk_wiz_0_locked,
S1_AXI_ARREADY => axi_interconnect_0_M05_AXI_ARREADY,
S1_AXI_ARVALID => axi_interconnect_0_M05_AXI_ARVALID,
S1_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M05_AXI_AWADDR(31 downto 0),
S1_AXI_AWREADY => axi_interconnect_0_M05_AXI_AWREADY,
S1_AXI_AWVALID => axi_interconnect_0_M05_AXI_AWVALID,
S1_AXI_BREADY => axi_interconnect_0_M05_AXI_BREADY,
S1_AXI_BRESP(1 downto 0) => axi_interconnect_0_M05_AXI_BRESP(1 downto 0),
S1_AXI_BVALID => axi_interconnect_0_M05_AXI_BVALID,
S1_AXI_RDATA(31 downto 0) => axi_interconnect_0_M05_AXI_RDATA(31 downto 0),
S1_AXI_RREADY => axi_interconnect_0_M05_AXI_RREADY,
S1_AXI_RRESP(1 downto 0) => axi_interconnect_0_M05_AXI_RRESP(1 downto 0),
S1_AXI_RVALID => axi_interconnect_0_M05_AXI_RVALID,
S1_AXI_WDATA(31 downto 0) => axi_interconnect_0_M05_AXI_WDATA(31 downto 0),
S1_AXI_WREADY => axi_interconnect_0_M05_AXI_WREADY,
S1_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M05_AXI_WSTRB(3 downto 0),
S1_AXI_WVALID => axi_interconnect_0_M05_AXI_WVALID,
S2_AXI_ACLK => clk_wiz_0_clk_out1,
S2_AXI_ARADDR(31 downto 0) => axi_interconnect_0_M06_AXI_ARADDR(31 downto 0),
S2_AXI_ARESETN => clk_wiz_0_locked,
S2_AXI_ARREADY => axi_interconnect_0_M06_AXI_ARREADY,
S2_AXI_ARVALID => axi_interconnect_0_M06_AXI_ARVALID,
S2_AXI_AWADDR(31 downto 0) => axi_interconnect_0_M06_AXI_AWADDR(31 downto 0),
S2_AXI_AWREADY => axi_interconnect_0_M06_AXI_AWREADY,
S2_AXI_AWVALID => axi_interconnect_0_M06_AXI_AWVALID,
S2_AXI_BREADY => axi_interconnect_0_M06_AXI_BREADY,
S2_AXI_BRESP(1 downto 0) => axi_interconnect_0_M06_AXI_BRESP(1 downto 0),
S2_AXI_BVALID => axi_interconnect_0_M06_AXI_BVALID,
S2_AXI_RDATA(31 downto 0) => axi_interconnect_0_M06_AXI_RDATA(31 downto 0),
S2_AXI_RREADY => axi_interconnect_0_M06_AXI_RREADY,
S2_AXI_RRESP(1 downto 0) => axi_interconnect_0_M06_AXI_RRESP(1 downto 0),
S2_AXI_RVALID => axi_interconnect_0_M06_AXI_RVALID,
S2_AXI_WDATA(31 downto 0) => axi_interconnect_0_M06_AXI_WDATA(31 downto 0),
S2_AXI_WREADY => axi_interconnect_0_M06_AXI_WREADY,
S2_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M06_AXI_WSTRB(3 downto 0),
S2_AXI_WVALID => axi_interconnect_0_M06_AXI_WVALID
);
uart_transceiver_0: component DemoInterconnect_uart_transceiver_0_0
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_0_1,
i_TX_Byte(7 downto 0) => interface_axi_master_0_if00_data_out(7 downto 0),
i_TX_Load => interface_axi_master_0_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_0_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_0_o_RX_Done,
o_TX_Active => uart_transceiver_0_o_TX_Active,
o_TX_Done => uart_transceiver_0_o_TX_Done,
o_TX_Serial => uart_transceiver_0_o_TX_Serial
);
uart_transceiver_1: component DemoInterconnect_uart_transceiver_0_1
port map (
i_Clk => clk_wiz_0_uart,
i_RX_Serial => UART_RX_1_1,
i_TX_Byte(7 downto 0) => internoc_ni_axi_master_1_if00_data_out(7 downto 0),
i_TX_Load => internoc_ni_axi_master_1_if00_load_out,
o_RX_Byte(7 downto 0) => uart_transceiver_1_o_RX_Byte(7 downto 0),
o_RX_Done => uart_transceiver_1_o_RX_Done,
o_TX_Active => uart_transceiver_1_o_TX_Active,
o_TX_Done => uart_transceiver_1_o_TX_Done,
o_TX_Serial => uart_transceiver_1_o_TX_Serial
);
end STRUCTURE;
|
mit
|
369d10e8ef3a364dc56a5af72ccf87f0
| 0.684132 | 2.886733 | false | false | false | false |
Dasio/FIT-Projects
|
INP/proj1/fpga/ledc8x8.vhd
| 1 | 1,996 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ledc8x8 is
port(
SMCLK : in std_logic;
RESET : in std_logic;
ROW : out std_logic_vector(0 to 7);
LED : out std_logic_vector(0 to 7)
);
end entity ledc8x8;
architecture behavioral of ledc8x8 is
-- 5 bitovy citac
signal citac : std_logic_vector(4 downto 0) := (others => '0');
signal clock_enable : std_logic;
signal row_cnt : std_logic_vector(2 downto 0) := (others => '0');
begin
-- Delic frekvencie
citac_gen : process(SMCLK, RESET)
begin
if RESET = '1' then
citac <= (others => '0');
elsif SMCLK'event and SMCLK = '1' then
citac <= citac + 1;
end if;
end process;
-- Paralelne priradenie
clock_enable <= '1' when citac = "11111" else '0';
---------------------------------------------------
-- Citac aktualneho riadku, inkrementuje sa len ked
-- delic frekvencie prave preteka
row_cnt_gen : process(SMCLK, RESET)
begin
if RESET = '1' then
row_cnt <= (others => '0');
elsif SMCLK'event and SMCLK = '1' then
if clock_enable = '1' then
row_cnt <= row_cnt + 1;
end if;
end if;
end process;
---------------------------------------------------
-- one-hot convertor
with row_cnt select
ROW <= "10000000" when "000",
"01000000" when "001",
"00100000" when "010",
"00010000" when "011",
"00001000" when "100",
"00000100" when "101",
"00000010" when "110",
"00000001" when "111",
"XXXXXXXX" when others;
-- samotne rozsvietenie diody podla aktualneho riadku
-- invertovane !
with row_cnt select
LED <= "00011111" when "000",
"01101111" when "001",
"01101111" when "010",
"01101110" when "011",
"00000100" when "100",
"11101010" when "101",
"11101110" when "110",
"11101110" when "111",
"XXXXXXXX" when others;
end architecture behavioral;
|
mit
|
248c4f2e5b2e41b55698d84bb41187ce
| 0.569639 | 3.109034 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_internoc_ni_axi_master_0_0/synth/DemoInterconnect_internoc_ni_axi_master_0_0.vhd
| 1 | 11,146 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: e.kyriakakis:user:internoc_ni_axi_master:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY xil_defaultlib;
USE xil_defaultlib.internoc_ni_axi_master_v1_0;
ENTITY DemoInterconnect_internoc_ni_axi_master_0_0 IS
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_internoc_ni_axi_master_0_0;
ARCHITECTURE DemoInterconnect_internoc_ni_axi_master_0_0_arch OF DemoInterconnect_internoc_ni_axi_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_internoc_ni_axi_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT internoc_ni_axi_master_v1_0 IS
GENERIC (
C_IF00_DATA_WIDTH : INTEGER;
C_PACKET_WIDTH : INTEGER;
C_PACKET_DATA_WIDTH : INTEGER;
C_PACKET_CTRL_WIDTH : INTEGER;
C_PACKET_ADDR_WIDTH : INTEGER;
C_AXI_PACKET_ADDR_OFFSET : INTEGER;
C_M00_AXI_ADDR_WIDTH : INTEGER;
C_M00_SELF_ADDR : INTEGER;
C_TIMEOUT_PERIOD : INTEGER
);
PORT (
if00_data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_in : IN STD_LOGIC;
if00_data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
if00_load_out : OUT STD_LOGIC;
if00_send_done : IN STD_LOGIC;
if00_send_busy : IN STD_LOGIC;
m00_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_awvalid : OUT STD_LOGIC;
m00_axi_awready : IN STD_LOGIC;
m00_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m00_axi_wvalid : OUT STD_LOGIC;
m00_axi_wready : IN STD_LOGIC;
m00_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_bvalid : IN STD_LOGIC;
m00_axi_bready : OUT STD_LOGIC;
m00_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m00_axi_arvalid : OUT STD_LOGIC;
m00_axi_arready : IN STD_LOGIC;
m00_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m00_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m00_axi_rvalid : IN STD_LOGIC;
m00_axi_rready : OUT STD_LOGIC;
m00_axi_aclk : IN STD_LOGIC;
m00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT internoc_ni_axi_master_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_internoc_ni_axi_master_0_0_arch: ARCHITECTURE IS "internoc_ni_axi_master_v1_0,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_internoc_ni_axi_master_0_0_arch : ARCHITECTURE IS "DemoInterconnect_internoc_ni_axi_master_0_0,internoc_ni_axi_master_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME M00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 M00_AXI_RST RST, xilinx.com:signal:reset:1.0 m00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M00_AXI_CLK, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 m00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF m00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME M00_AXI, WIZ_DATA_WIDTH 32, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
BEGIN
U0 : internoc_ni_axi_master_v1_0
GENERIC MAP (
C_IF00_DATA_WIDTH => 8,
C_PACKET_WIDTH => 40,
C_PACKET_DATA_WIDTH => 32,
C_PACKET_CTRL_WIDTH => 3,
C_PACKET_ADDR_WIDTH => 5,
C_AXI_PACKET_ADDR_OFFSET => 16,
C_M00_AXI_ADDR_WIDTH => 32,
C_M00_SELF_ADDR => 16,
C_TIMEOUT_PERIOD => 16383
)
PORT MAP (
if00_data_in => if00_data_in,
if00_load_in => if00_load_in,
if00_data_out => if00_data_out,
if00_load_out => if00_load_out,
if00_send_done => if00_send_done,
if00_send_busy => if00_send_busy,
m00_axi_awaddr => m00_axi_awaddr,
m00_axi_awprot => m00_axi_awprot,
m00_axi_awvalid => m00_axi_awvalid,
m00_axi_awready => m00_axi_awready,
m00_axi_wdata => m00_axi_wdata,
m00_axi_wstrb => m00_axi_wstrb,
m00_axi_wvalid => m00_axi_wvalid,
m00_axi_wready => m00_axi_wready,
m00_axi_bresp => m00_axi_bresp,
m00_axi_bvalid => m00_axi_bvalid,
m00_axi_bready => m00_axi_bready,
m00_axi_araddr => m00_axi_araddr,
m00_axi_arprot => m00_axi_arprot,
m00_axi_arvalid => m00_axi_arvalid,
m00_axi_arready => m00_axi_arready,
m00_axi_rdata => m00_axi_rdata,
m00_axi_rresp => m00_axi_rresp,
m00_axi_rvalid => m00_axi_rvalid,
m00_axi_rready => m00_axi_rready,
m00_axi_aclk => m00_axi_aclk,
m00_axi_aresetn => m00_axi_aresetn
);
END DemoInterconnect_internoc_ni_axi_master_0_0_arch;
|
mit
|
139048b5c01b26fc1b0460ba99becf94
| 0.708505 | 3.189127 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AA_AA.vhd
| 1 | 1,425 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:32:45 03/09/2017
-- Design Name:
-- Module Name: LatchSR_AA_AA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LatchSR_AA_AA is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
EN : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end LatchSR_AA_AA;
architecture Behavioral of LatchSR_AA_AA is
COMPONENT LatchSR_AB
PORT(
Sn : IN std_logic;
Rn : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
signal S_aux : std_logic := '0';
signal R_aux : std_logic := '0';
begin
S_aux <= S nand EN;
R_aux <= R nand EN;
Inst_LatchSR_AB: LatchSR_AB PORT MAP(
Sn => S_aux,
Rn => R_aux,
Q => Q,
Qn => Qn
);
end Behavioral;
|
gpl-3.0
|
5ce068c05793cd22869de19df7869e76
| 0.555088 | 3.442029 | false | false | false | false |
ktemkin/ruby-adept
|
firmware/epp_stream/fifo.vhd
| 1 | 5,763 |
----------------------------------------------------------------------------------
-- Simple Synchronous FIFO
--
-- Author: Kyle J. Temkin, <[email protected]>
-- Copyright (c) Kyle J. Temkin, 2013 Binghamton University
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.-
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fifo is
generic
(
-- The width of the _count_ signal, which will store the amount of
-- full elements in the FIFO. This signal is used to set the size
-- of the FIFO; a FIFO with count_bits equal to 5 will have a depth
-- of 31.
--
-- Note the odd number of elements; this allows us to use 0 as our
-- special "empty" case, which makes several things more efficient.
--
count_bits : integer := 5;
--The width of each element in the FIFO.
element_width : integer := 8
);
port(
--System clock.
clk : in std_logic;
--Active-high reset; clears the contents of the FIF0.
reset : in std_logic;
--The data inputs and outputs of for the FIFO.
data_in : in std_logic_vector(element_width - 1 downto 0);
data_out : out std_logic_vector(element_width - 1 downto 0);
--The total amount of data elements currently stored in the FIFO.
count : out std_logic_vector(count_bits - 1 downto 0);
--Enqueue and dequeue control signals; adds and removes an element
--from the FIFO, respectively.
enqueue : in std_logic;
dequeue : in std_logic;
--Status flags; note when the queue is empty (count == 0) and full
--(count is at its maximum value) respectively.
empty : out std_logic;
full : out std_logic
);
end fifo;
architecture Behavioral of fifo is
--Quick reference to the total amount of elements in the FIFO.
constant element_count : integer := (2 ** count_bits) - 1;
--Create an array type, which will represent the contents of the FIFO.
type queue is array (element_count - 1 downto 0)
of std_logic_vector(element_width - 1 downto 0);
--The array of registers which will house our FIFO data.
signal element : queue;
--Register wihch stores our current place in the FIFO.
signal count_reg : integer range 0 to element_count;
--Internal empty and full signals.
signal empty_sig, full_sig : std_logic;
--Internal "write allowed" signal.
signal enqueue_allowed : std_logic;
--Intermediary signal which stores the current write target for the FPGA.
signal enqueue_target : integer range 0 to element_count;
begin
--Count output; outputs the current value of the count signal.
count <= std_logic_vector(to_unsigned(count_reg, count_bits));
--Data output.
data_out <= element(0);
--Determine the register which will be updated on the next
--write operation.
enqueue_target <= count_reg - 1 when dequeue = '1' and enqueue = '1' else count_reg;
--Determine if a write operation should be allowed:
--We can write whenever there's space in the FIFO:
-- * When the FIFO isn't full, or;
-- * When we're going to _make_ room for the new element by dequeueing.
enqueue_allowed <= not full_sig or dequeue;
--Empty and full flags: indicate when the FIFO is empty and full,
--respectively.
empty_sig <= '1' when count_reg = 0 else '0';
full_sig <= '1' when count_reg = element_count else '0';
--Attach outputs to the values of the empty and full signals.
empty <= empty_sig;
full <= full_sig;
--
--Main "shift register" for the FIFO.
--
FIFO_BODY:
process(clk)
begin
--Trigger on rising edge of the clock.
if rising_edge(clk) then
if reset = '1' then
element <= (others => (others => '0'));
else
--If the enqueue operation is selected...
if enqueue = '1' and enqueue_allowed = '1' then
--Add the new element in the new free space.
element(enqueue_target) <= data_in;
--If only the write flag is set, increment the element count.
if dequeue = '0' then
count_reg <= count_reg + 1;
end if;
end if;
--If the dequeue flag is set (and there are elements to read), remove an element from the queue.
if dequeue = '1' and empty_sig = '0' then
--Shift each element one towards zero.
--Note that this isn't "expensive", as it would be in software-
--we're simultaneously adjusting the value of each element, in parallel.
for i in 0 to element_count - 2 loop
element(i) <= element(i + 1);
end loop;
--If only the read flag is set, decrement the count.
if enqueue = '0' then
count_reg <= count_reg - 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
b0d82850eff54dc08cb3301662e517c7
| 0.640118 | 4.044211 | false | false | false | false |
nkkav/ledramp-s3esk
|
ledramp.vhd
| 1 | 1,573 |
-- Original source:
-- http://www.avrfreaks.net/index.php?name=PNphpBB2&file=printview&t=54866&start=40
-- by user "buserror"
library IEEE;
use IEEE.std_logic_1164.all;
entity ledramp is
generic (
PWM_RANGE_MAX : integer := 5000000
);
port (
clk : in std_logic;
ramp : out std_logic_vector(7 downto 0)
);
end ledramp;
architecture behavioral of ledramp is
-- Type declarations
type state_type is (PULSE, SHIFT);
--
-- Signal declarations
signal state : state_type := PULSE;
--
begin
process (clk)
-- Variable declarations
variable up : std_logic_vector(7 downto 0) := "00000001";
variable direction : std_logic := '0';
variable mark : integer := 0;
--
begin
if (rising_edge(clk)) then
case state is
when PULSE =>
ramp <= up;
--
mark := mark + 1;
--
if (mark = PWM_RANGE_MAX) then
state <= SHIFT;
mark := 0;
end if;
--
when SHIFT =>
if (direction = '0') then
if (up = "10000000") then
direction := '1';
up := "01000000";
else
up := up(6 downto 0) & up(7);
end if;
else
if (up = "00000001") then
direction := '0';
up := "00000010";
else
up := up(0) & up(7 downto 1);
end if;
end if;
--
state <= PULSE;
--
end case;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
efd20d32c717304058dab900b9b5980f
| 0.486968 | 3.893564 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_spi_master_1.0/src/serial2parallel.vhd
| 3 | 2,755 |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: S2P Parallelizer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity byte2word is
generic (
DATA_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
en_i : in std_logic;
rstn_i : in std_logic;
shift_cnt_i : in std_logic_vector(2 downto 0);
shift_i : in std_logic_vector(7 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end byte2word;
architecture behave of byte2word is
signal shift_count : integer range 0 to 7 := 0;
signal rx_done : std_logic := '0';
signal shift_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal init_rx_ff, init_rx_ff2 : std_logic := '0';
signal rx_en : std_logic := '0';
----------------------------------
attribute shreg_extract : string;
attribute shreg_extract of shift_data : signal is "yes";
begin
init_rx_pulse: process(clk_i, en_i)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
else
init_rx_ff <= en_i;
init_rx_ff2 <= init_rx_ff;
rx_en <= not(init_rx_ff2) and init_rx_ff;
end if;
end if;
end process;
shift_in: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_data <= (others=>'0');
else
if rx_en = '1' and rx_done='0' then
--shift_data(TX_WIDTH-1 downto 0) <= shift_i; --MSB First
--shift_data(DATA_WIDTH-1 downto TX_WIDTH) <= shift_data(DATA_WIDTH-TX_WIDTH-1 downto 0);
shift_data <= shift_data(DATA_WIDTH-8-1 downto 0) & shift_i;
end if;
end if;
end if;
end process;
count_shift: process(clk_i, en_i, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if (rstn_i = '0') then
shift_count <= 0;
rx_done <= '0';
else
if rx_en = '1' and rx_done='0' then
if shift_count = to_integer(unsigned(shift_cnt_i))-1 then
rx_done <= '1';
shift_count <= 0;
else
shift_count <= shift_count + 1;
end if;
else
rx_done <= '0';
end if;
end if;
end if;
end process;
done_o <= rx_done;
data_o <= shift_data(DATA_WIDTH-1 downto 0); --align data to the requested width
end architecture ;
|
mit
|
836875bd84b130badd06cd1a4b12393b
| 0.541561 | 3.279762 | false | false | false | false |
mosass/HexapodRobot
|
VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/synth/design_1_rst_ps7_0_100M_0.vhd
| 1 | 6,597 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_ps7_0_100M_0;
ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_ps7_0_100M_0_arch;
|
mit
|
4b1e693e5891a505b965d1ef72bf7c98
| 0.71199 | 3.414596 | false | false | false | false |
dl3yc/sdr-fm
|
dev/div/div_tb.vhd
| 1 | 1,172 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity div_tb is
end entity div_tb;
architecture sim of div_tb is
constant D : natural := 28;
constant N : natural := 27;
signal clk : std_logic := '0';
signal stb : std_logic := '0';
signal num : signed(N-1 downto 0);
signal denom : signed(D-1 downto 0);
signal quot : signed(N-1 downto 0);
signal remaind : signed(D-1 downto 0);
signal rdy : std_logic;
begin
dut : entity work.div
generic map(
WN => N,
WD => D
)
port map(
clk => clk,
stb => stb,
num => num,
denom => denom,
quot => quot,
remaind => remaind,
rdy => rdy
);
clk <= not clk after 20345 ps;
process
variable cnt : unsigned(8 downto 0) := (others => '0');
begin
wait until rising_edge(clk);
if cnt = 511 then
stb <= '1';
else
stb <= '0';
end if;
cnt := cnt + 1;
end process;
process begin
num <= to_signed(10,num'length);
denom <= to_signed(1,denom'length);
wait until stb = '1';
wait;
end process;
process
variable i : integer := 0;
begin
wait until stb = '1';
i := i + 1;
assert (i < 40) severity failure;
end process;
end architecture sim;
|
gpl-2.0
|
725386f571591112c1fcfb3166e892b8
| 0.609215 | 2.790476 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ipshared/859e/hdl/mutex_v2_1_vh_rfs.vhd
| 1 | 116,298 |
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
-------------------------------------------------------------------------------
-- gen_dram.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Author: satish
--
-- History:
-- satish 2004-03-24 New Version
-- rikardw 2006-10-19 Single port version
--
-- Description:
-- Code to infer synchronous single port lut ram
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Gen_DRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
do : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity Gen_DRAM;
architecture syn of Gen_DRAM is
type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
-- signal RAM : ram_type := (others => (others => '0'));
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(a));
end syn;
-------------------------------------------------------------------------------
-- multi_channel_register.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: multi_channel_register.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.Gen_DRAM;
entity multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end entity multi_channel_register;
architecture IMP of multi_channel_register is
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component Gen_DRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
do : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end component Gen_DRAM;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Single channel storage
-----------------------------------------------------------------------------
Use_Single_Ch_Reg: if( C_NUM_CHANNELS = 1 ) generate
begin
Store_Cnt: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Data_Out <= (others=>'0');
elsif( Write_Strobe = '1' ) then
Data_Out <= Data_In;
end if;
end if;
end process Store_Cnt;
end generate Use_Single_Ch_Reg;
-----------------------------------------------------------------------------
-- Multiple channel storage
-----------------------------------------------------------------------------
Use_Multi_Ch_Reg: if( C_NUM_CHANNELS > 1 ) generate
begin
-- Counter storage.
RAM_Storage: Gen_DRAM
generic map(
C_DWIDTH => C_DWIDTH,
C_AWIDTH => C_AWIDTH
)
port map(
clk => Clk,
we => Write_Strobe,
a => Channel,
di => Data_In,
do => Data_Out
);
end generate Use_Multi_Ch_Reg;
end architecture IMP;
-------------------------------------------------------------------------------
-- multi_channel_mutex.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: multi_channel_mutex.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.multi_channel_register;
entity multi_channel_mutex is
generic (
C_NUM_CHANNELS : natural := 2;
C_OWNER_ID_WIDTH : natural := 0;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
New_Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0)
);
end entity multi_channel_mutex;
architecture IMP of multi_channel_mutex is
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end component multi_channel_register;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal Mutex_I : std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
signal Mutex_New : std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Channel Counter Storage
-----------------------------------------------------------------------------
Mutex_Store: multi_channel_register
generic map(
C_NUM_CHANNELS => C_NUM_CHANNELS,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH + C_OWNER_ID_WIDTH
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe,
Channel => Channel,
Data_In => Mutex_New,
Data_Out => Mutex_I
);
-----------------------------------------------------------------------------
-- Write to lock and pure write to release function
-----------------------------------------------------------------------------
Write_2_Lock: process(Data_In, Mutex_I)
variable OwnerMatched : boolean;
begin
-- Check if the owner is writing.
if( C_OWNER_ID_WIDTH > 0 ) then
OwnerMatched := Mutex_I(C_OWNER_ID_WIDTH + C_DWIDTH - 1 downto C_DWIDTH) =
Data_In(C_OWNER_ID_WIDTH + C_DWIDTH - 1 downto C_DWIDTH);
else
OwnerMatched := true;
end if;
-- Update mutex accordingly.
if( Mutex_I(0) /= '1' or OwnerMatched ) then
-- Write new value.
if( Data_In(0) = '0' ) then
Mutex_New <= (others=>'0');
else
Mutex_New <= Data_In;
end if;
else
-- Keep old value.
Mutex_New <= Mutex_I;
end if;
end process Write_2_Lock;
-----------------------------------------------------------------------------
-- Rename output signals
-----------------------------------------------------------------------------
New_Mutex_Out <= Mutex_New;
Mutex_Out <= Mutex_I;
end architecture IMP;
-------------------------------------------------------------------------------
-- mutex_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mutex_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mutex_core.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mutex_core is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- Mutex specific.
C_NUM_INTERFACE : integer range 1 to 16 := 1; -- Number of interfaces to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 1; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16; -- Number of mutexes.
C_MUTEX_NUMBER : integer := 0; -- Mutex number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_REGISTER_WIDTH : integer := 4; -- Width of register offset.
C_DWIDTH : integer := 32; -- Width of data bus.
C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
C_DWIDTH_MUTEX : integer := 1 -- Width of mutex field (usually 1).
);
port (
-- System signals
Clk : in std_logic;
Rst : in std_logic;
-- Bus slave signals
Mutex_Access : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_RnW : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_HW_Id : in std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
Mutex_Addr : in std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
Mutex_Wr_Data : in std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
Mutex_Rd_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : out std_logic_vector(0 to C_NUM_INTERFACE - 1)
);
end entity mutex_core;
library unisim;
use unisim.all;
architecture IMP of mutex_core is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
function Get_Num_Bits(data : natural) return natural is
variable num_bits : natural:= 1;
begin
while( data > 2**num_bits ) loop
num_bits := num_bits + 1;
end loop;
return num_bits;
end function Get_Num_Bits;
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component multi_channel_mutex is
generic (
C_NUM_CHANNELS : natural := 2;
C_OWNER_ID_WIDTH : natural := 0;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
New_Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0)
);
end component multi_channel_mutex;
component multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end component multi_channel_register;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
-- Internal arbitrated signals
signal Mutex_Access_I : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_RnW_I : std_logic;
signal Mutex_HW_Id_I : std_logic_vector(0 to C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) - 1);
signal Mutex_Addr_I : std_logic_vector(0 to C_AWIDTH - 1);
signal Mutex_Wr_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Rd_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Ack_I : std_logic;
signal Access_In_Progress : std_logic;
signal Write_Strobe_Mutex : std_logic;
signal Write_Strobe_User : std_logic;
signal Second_Cycle : std_logic;
signal Read_Data_Type : std_logic_vector(0 to 1);
-- Configuration register related.
signal User_Reg : std_logic_vector(0 to C_DWIDTH_USER_REG - 1);
signal User_Reg_I : std_logic_vector(0 to C_DWIDTH - 1);
-- Mutex related.
signal Mutex : std_logic_vector(0 to C_DWIDTH_MUTEX + C_OWNER_ID_WIDTH - 1);
signal Mutex_I : std_logic_vector(0 to C_DWIDTH - 1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Interface arbitration
-----------------------------------------------------------------------------
Using_SingleIf_Mutex: if C_NUM_INTERFACE = 1 generate
begin
-- Only one interface to all Mutexes.
-- => Simply connect w/o any arbitration.
Access_In_Progress <= Mutex_Access(0);
Mutex_Access_I <= Mutex_Access(0 to 0);
Mutex_RnW_I <= Mutex_RnW(0);
Mutex_HW_Id_I <= Mutex_HW_Id(0 to C_HW_ID_WIDTH - 1) & '0';
Mutex_Addr_I <= Mutex_Addr(0 to C_AWIDTH - 1);
Mutex_Wr_Data_I <= Mutex_Wr_Data(0 to C_DWIDTH - 1);
Mutex_Ack <= (others=>Mutex_Ack_I);
end generate Using_SingleIf_Mutex;
-- Multiple interfaces.
Using_MultiIf_Mutex: if C_NUM_INTERFACE > 1 generate
begin
Interface_Arbitration: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Access_In_Progress <= '0';
Mutex_Access_I <= (others=>'0');
Mutex_RnW_I <= '0';
Mutex_HW_Id_I <= (others=>'0');
Mutex_Addr_I <= (others=>'0');
Mutex_Wr_Data_I <= (others=>'0');
else
if( Access_In_Progress = '1' ) then
if( ( Mutex_Access_I and Mutex_Access ) = (Mutex_Access'range=>'0') ) then
-- Selected interface has acknowledged that this end
-- has performed all its tasks.
-- => Get ready for the next access.
Access_In_Progress <= '0';
Mutex_Access_I <= (others=>'0');
end if;
else
for I in natural range C_NUM_INTERFACE - 1 downto 0 loop
-- Loop in ascending priority order.
if( Mutex_Access(I) = '1' ) then
-- This interface wants to access a mutexes in this bank.
-- => Forward information to the rest of the core.
Access_In_Progress <= '1';
Mutex_Access_I <= (others=>'0');
Mutex_Access_I(I) <= '1';
Mutex_RnW_I <= Mutex_RnW(I);
Mutex_HW_Id_I <= Mutex_HW_Id(C_HW_ID_WIDTH * I to C_HW_ID_WIDTH * (I + 1) - 1) &
std_logic_vector(to_unsigned(I, Get_Num_Bits(C_NUM_INTERFACE)));
Mutex_Addr_I <= Mutex_Addr(C_AWIDTH * I to C_AWIDTH * (I + 1) - 1);
Mutex_Wr_Data_I <= Mutex_Wr_Data(C_DWIDTH * I to C_DWIDTH * (I + 1) - 1);
end if;
end loop;
end if;
-- Assign the Acknowledge signal.
Mutex_Ack <= (Mutex_Ack'range=>Mutex_Ack_I) and Mutex_Access_I and Mutex_Access;
end if;
end if;
end process Interface_Arbitration;
end generate Using_MultiIf_Mutex;
-----------------------------------------------------------------------------
-- Access control
-----------------------------------------------------------------------------
Access_Handle: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
-- Reset.
Write_Strobe_User <= '0';
Write_Strobe_Mutex <= '0';
Mutex_Ack_I <= '0';
Second_Cycle <= '0';
Read_Data_Type <= (others=>'0');
else
-- Generate second cycle.
Second_Cycle <= (not Second_Cycle ) and Access_In_Progress and (not Mutex_Ack_I);
-- Default assignment.
Write_Strobe_User <= '0';
Write_Strobe_Mutex <= '0';
-- Control read data mux.
Read_Data_Type <= Mutex_Addr_I(Mutex_Addr_I'right - 1 - 2 to Mutex_Addr_I'right - 2);
-- Create write strobes for resources.
if( Mutex_Addr_I(Mutex_Addr_I'right - 2) = '0' ) then
-- Access mutex registers.
Write_Strobe_Mutex <= Access_In_Progress and (not Mutex_RnW_I);
else
-- Access Configuration/Address register.
if( C_ENABLE_USER /= 0 ) then
Write_Strobe_User <= Access_In_Progress and (not Mutex_RnW_I);
end if;
end if;
-- Finish access.
Mutex_Ack_I <= Second_Cycle or (Access_In_Progress and (not Mutex_RnW_I)) or (Mutex_Ack_I and Access_In_Progress);
end if;
end if;
end process Access_Handle;
-----------------------------------------------------------------------------
-- Instantiating MUTEX Register
-----------------------------------------------------------------------------
Using_HW_Protection: if( C_ENABLE_HW_PROT /= 0 ) generate
signal Mutex_Wr_Data_II : std_logic_vector(0 to C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) + C_DWIDTH_MUTEX -1);
signal Mutex_II : std_logic_vector(0 to C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) + C_DWIDTH_MUTEX -1);
begin
Protected_Mutex_Inst: multi_channel_mutex
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE),
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_MUTEX
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_Mutex,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_II,
New_Mutex_Out => open,
Mutex_Out => Mutex_II
);
-- Append and remove hardware information invisibly.
Mutex_Wr_Data_II <= Mutex_HW_Id_I & Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH - 1);
Mutex <= Mutex_II(C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) to Mutex_II'right);
end generate Using_HW_Protection;
No_HW_Protection: if( C_ENABLE_HW_PROT = 0 ) generate
begin
Normal_Mutex_Inst: multi_channel_mutex
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH,
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_MUTEX
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_Mutex,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH - 1),
New_Mutex_Out => open,
Mutex_Out => Mutex
);
end generate No_HW_Protection;
-----------------------------------------------------------------------------
-- Instantiating USER Register
-----------------------------------------------------------------------------
Using_User_Reg: if( C_ENABLE_USER /= 0 ) generate
begin
User_Reg_Inst: multi_channel_register
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_USER_REG
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_User,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1),
Data_Out => User_Reg
);
end generate Using_User_Reg;
No_User_Reg: if( C_ENABLE_USER = 0 ) generate
begin
User_Reg <= (others=>'0');
end generate No_User_Reg;
-----------------------------------------------------------------------------
-- Read multiplexer
-----------------------------------------------------------------------------
ReadDataMux: process(Read_Data_Type, User_Reg, Mutex)
begin
-- Extend the data to full width.
-- User_Reg_I <= (others=>'0');
-- User_Reg_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1) <= User_Reg;
-- Mutex_I <= (others=>'0');
-- Mutex_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH-1) <= Mutex;
-- Default assignment.
Mutex_Rd_Data_I <= (others=>'0');
case Read_Data_Type is
when "00" =>
Mutex_Rd_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH-1) <= Mutex;
when "01" =>
Mutex_Rd_Data_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1) <= User_Reg;
when others =>
-- Reserved registers.
null;
end case;
end process ReadDataMux;
ReadDataMux_DFF: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Mutex_Rd_Data <= (others=>'0');
elsif( Second_Cycle = '1' ) then
Mutex_Rd_Data <= Mutex_Rd_Data_I;
end if;
end if;
end process ReadDataMux_DFF;
end architecture IMP;
-------------------------------------------------------------------------------
-- axi_decode.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_decode.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_decode.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2007-03-27 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_decode is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_DWIDTH : integer := 32 -- Width of data bus.
);
port (
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Mutex signals.
Mutex_Clk : in std_logic;
Mutex_Rst : in std_logic;
Mutex_Access : out std_logic;
Mutex_RnW : out std_logic;
Mutex_HW_Id : out std_logic_vector(0 to C_HW_ID_WIDTH - 1);
Mutex_Addr : out std_logic_vector(0 to C_AWIDTH - 1);
Mutex_Wr_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Rd_Data : in std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : in std_logic
);
end entity axi_decode;
library unisim;
use unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.all;
architecture IMP of axi_decode is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal valid_read_data : std_logic;
signal new_write_access_cmb : std_logic;
signal new_read_access_cmb : std_logic;
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal end_write : std_logic; -- Write cycle end.
signal end_read : std_logic; -- Read cycle end.
signal completed_write : std_logic; -- Write response acknowledged.
signal completed_read : std_logic; -- Read response acknowledged.
signal access_end : std_logic; -- Access is completed.
signal Mutex_Access_I : std_logic;
signal Mutex_RnW_I : std_logic;
signal Mutex_HW_Id_I : std_logic_vector(0 to C_HW_ID_WIDTH - 1);
signal Mutex_Addr_I : std_logic_vector(0 to C_AWIDTH - 1);
signal Mutex_Wr_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Rd_Data_I : std_logic_vector(C_DWIDTH - 1 downto 0);
signal Mutex_Ack_I : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Write has priority.
-- Make sure new write is blocked if it arrives after a read is acknowledged (prior to Mutex_Access_I is set).
new_write_access_cmb <= (not Mutex_Access_I) and (not Mutex_Ack_I) and S_AXI_AWVALID and S_AXI_WVALID and
(not new_read_access);
new_read_access_cmb <= (not Mutex_Access_I) and (not Mutex_Ack_I) and S_AXI_ARVALID and
(not new_write_access_cmb);
Start_of_Transfer_Control : process (S_AXI_ACLK) is
begin -- process End_of_Transfer_Control
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
new_write_access <= '0';
new_read_access <= '0';
else
-- Make sure it is a one cycle pulse only.
new_write_access <= new_write_access_cmb and not new_write_access;
new_read_access <= new_read_access_cmb and not new_read_access;
end if;
end if;
end process Start_of_Transfer_Control;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Capture new access.
AccessAck: process (S_AXI_ACLK) is
begin -- process AddrAck
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
Mutex_Access_I <= '0';
Mutex_RnW_I <= '0';
Mutex_Addr_I <= (others=>'0');
Mutex_HW_Id_I <= (others=>'0');
Mutex_Wr_Data_I <= (others=>'0');
else
if( new_write_access = '1' or new_read_access = '1' ) then
-- Get data for new access.
if( new_write_access = '1' ) then
Mutex_Addr_I <= S_AXI_AWADDR(C_AWIDTH-1 downto 0);
else
Mutex_Addr_I <= S_AXI_ARADDR(C_AWIDTH-1 downto 0);
end if;
Mutex_Wr_Data_I <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
Mutex_HW_Id_I <= (others=>'0');
Mutex_RnW_I <= new_read_access;
Mutex_Access_I <= '1';
elsif( access_end = '1' ) then
Mutex_Access_I <= '0';
end if;
end if;
end if;
end process AccessAck;
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (B/R)
-----------------------------------------------------------------------------
End_of_Transfer_Control : process (S_AXI_ACLK) is
begin -- process End_of_Transfer_Control
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
end_write <= '0';
end_read <= '0';
else
if( completed_write = '1' ) then
end_write <= '0';
elsif( Mutex_Access_I = '1' and Mutex_Ack_I = '1' and Mutex_RnW_I = '0' ) then
end_write <= '1';
end if;
if( completed_read = '1' ) then
end_read <= '0';
elsif( valid_read_data = '1' ) then
end_read <= '1';
end if;
end if;
end if;
end process End_of_Transfer_Control;
valid_read_data <= Mutex_Access_I and Mutex_Ack_I and Mutex_RnW_I;
S_AXI_BVALID <= end_write;
S_AXI_RVALID <= end_read;
S_AXI_BRESP <= (others=>'0');
S_AXI_RRESP <= (others=>'0');
completed_write <= end_write and S_AXI_BREADY;
completed_read <= end_read and S_AXI_RREADY;
access_end <= completed_write or completed_read;
Read_Align: process (Mutex_Rd_Data) is
begin -- process Read_Mux
Mutex_Rd_Data_i <= (others=>'0');
Mutex_Rd_Data_i(C_DWIDTH - 1 downto 0) <= Mutex_Rd_Data;
end process Read_Align;
Not_All_32_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_32_Bits_Are_Used;
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I), -- [out std_logic]
C => S_AXI_ACLK, -- [in std_logic]
CE => valid_read_data, -- [in std_logic]
D => Mutex_Rd_Data_i(I), -- [in std_logic]
R => completed_read); -- [in std_logic]
end generate S_AXI_RDATA_DFF;
-----------------------------------------------------------------------------
-- Domain synchronization
-----------------------------------------------------------------------------
-- Always move the data signals directly accross.
-- Sync signals will guarantee safe crossing.
Mutex_RnW <= Mutex_RnW_I;
Mutex_HW_Id <= Mutex_HW_Id_I;
Mutex_Addr <= Mutex_Addr_I;
Mutex_Wr_Data <= Mutex_Wr_Data_I;
Mutex_Rd_Data_I <= Mutex_Rd_Data;
No_Crossing: if( C_ASYNC_CLKS = 0 ) generate
begin
-- No need to synchronize.
Mutex_Access <= Mutex_Access_I;
Mutex_Ack_I <= Mutex_Ack;
end generate No_Crossing;
Domain_Crossing: if( C_ASYNC_CLKS /= 0 ) generate
signal Mutex_Access_d : std_logic_vector(0 to C_NUM_SYNC_FF);
signal Mutex_Ack_d : std_logic_vector(0 to C_NUM_SYNC_FF);
signal S_AXI_ARESET : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of Mutex_Access_d : signal is "TRUE";
-- attribute ASYNC_REG of Mutex_Ack_d : signal is "TRUE";
begin
-- Handle transfer of asynchronous interface sync signal transfer
-- with unknown clock relation.
--
-- C_NUM_SYNC_FF = 2 (default):
--
-- MutexClk -------+-----+-----------+
-- | | |
-- | | +---------+
-- Event ----FF----FF----FF---->| Mutex |
-- | | |
-- WrData ---FF---------------->| |
-- | | |
-- IfClk ----+-----+-----+ | |
-- | | | |
-- Ack <-----------FF----FF-----| |
-- | |
-- RdData <---------------------| |
-- +---------+
--
--
-- General case for C_NUM_SYNC_FF:
--
-- MutexClk -------+----------------+
-- | |
-- | +---------+
-- Event ----FF----(FF x n)---->| Mutex |
-- | | |
-- WrData ---FF---------------->| |
-- | | |
-- IfClk ----+-----+ | |
-- | | |
-- Ack <-----------(FF x n)-----| |
-- | |
-- RdData <---------------------| |
-- +---------+
--
S_AXI_ARESET <= not S_AXI_ARESETN;
-- Move the out bound access signal to the common domain.
Mutex_Access_d(0) <= Mutex_Access_I;
Cross_Out: for I in 1 to C_NUM_SYNC_FF generate
begin
Block_Gen: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FDR_INST : label is "TRUE";
begin
FDR_INST: FDR
port map (
Q => Mutex_Access_d(I),
C => Mutex_Clk,
D => Mutex_Access_d(I-1),
R => Mutex_Rst
);
end block Block_Gen;
end generate Cross_Out;
-- Select synchronized bit.
Mutex_Access <= Mutex_Access_d(C_NUM_SYNC_FF);
-- Get back to interface domain.
Mutex_Ack_d(0) <= Mutex_Ack;
Cross_Back: for I in 1 to C_NUM_SYNC_FF generate
begin
Block_Gen: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FDR_INST : label is "TRUE";
begin
FDR_INST: FDR
port map (
Q => Mutex_Ack_d(I),
C => S_AXI_ACLK,
D => Mutex_Ack_d(I-1),
R => S_AXI_ARESET
);
end block Block_Gen;
end generate Cross_Back;
-- Select synchronized bit.
Mutex_Ack_I <= Mutex_Ack_d(C_NUM_SYNC_FF);
end generate Domain_Crossing;
end architecture IMP;
-------------------------------------------------------------------------------
-- mutex.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mutex.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mutex.vhd
-- axi_decode.vhd
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
-- mutex_core.vhd
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-- stefana 2012-12-14 Removed legacy interfaces
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mutex is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- AXI4 interface #0 specific.
C_S0_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S0_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S0_AXI_ADDR_WIDTH : integer := 32;
C_S0_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #1 specific.
C_S1_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S1_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S1_AXI_ADDR_WIDTH : integer := 32;
C_S1_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #2 specific.
C_S2_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S2_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S2_AXI_ADDR_WIDTH : integer := 32;
C_S2_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #3 specific.
C_S3_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S3_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S3_AXI_ADDR_WIDTH : integer := 32;
C_S3_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #4 specific.
C_S4_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S4_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S4_AXI_ADDR_WIDTH : integer := 32;
C_S4_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #5 specific.
C_S5_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S5_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S5_AXI_ADDR_WIDTH : integer := 32;
C_S5_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #6 specific.
C_S6_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S6_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S6_AXI_ADDR_WIDTH : integer := 32;
C_S6_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #7 specific.
C_S7_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S7_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S7_AXI_ADDR_WIDTH : integer := 32;
C_S7_AXI_DATA_WIDTH : integer := 32;
-- Mutex specific.
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_NUM_AXI : integer range 0 to 8 := 2; -- Number of AXI to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 0; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16 -- Number of mutexes.
);
port (
-- AXI4-Lite interface #0 slave signals.
S0_AXI_ACLK : in std_logic;
S0_AXI_ARESETN : in std_logic;
S0_AXI_AWADDR : in std_logic_vector(C_S0_AXI_ADDR_WIDTH-1 downto 0);
S0_AXI_AWVALID : in std_logic;
S0_AXI_AWREADY : out std_logic;
S0_AXI_WDATA : in std_logic_vector(C_S0_AXI_DATA_WIDTH-1 downto 0);
S0_AXI_WSTRB : in std_logic_vector((C_S0_AXI_DATA_WIDTH/8)-1 downto 0);
S0_AXI_WVALID : in std_logic;
S0_AXI_WREADY : out std_logic;
S0_AXI_BRESP : out std_logic_vector(1 downto 0);
S0_AXI_BVALID : out std_logic;
S0_AXI_BREADY : in std_logic;
S0_AXI_ARADDR : in std_logic_vector(C_S0_AXI_ADDR_WIDTH-1 downto 0);
S0_AXI_ARVALID : in std_logic;
S0_AXI_ARREADY : out std_logic;
S0_AXI_RDATA : out std_logic_vector(C_S0_AXI_DATA_WIDTH-1 downto 0);
S0_AXI_RRESP : out std_logic_vector(1 downto 0);
S0_AXI_RVALID : out std_logic;
S0_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #1 slave signals.
S1_AXI_ACLK : in std_logic;
S1_AXI_ARESETN : in std_logic;
S1_AXI_AWADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S1_AXI_AWVALID : in std_logic;
S1_AXI_AWREADY : out std_logic;
S1_AXI_WDATA : in std_logic_vector(C_S1_AXI_DATA_WIDTH-1 downto 0);
S1_AXI_WSTRB : in std_logic_vector((C_S1_AXI_DATA_WIDTH/8)-1 downto 0);
S1_AXI_WVALID : in std_logic;
S1_AXI_WREADY : out std_logic;
S1_AXI_BRESP : out std_logic_vector(1 downto 0);
S1_AXI_BVALID : out std_logic;
S1_AXI_BREADY : in std_logic;
S1_AXI_ARADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S1_AXI_ARVALID : in std_logic;
S1_AXI_ARREADY : out std_logic;
S1_AXI_RDATA : out std_logic_vector(C_S1_AXI_DATA_WIDTH-1 downto 0);
S1_AXI_RRESP : out std_logic_vector(1 downto 0);
S1_AXI_RVALID : out std_logic;
S1_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #2 slave signals.
S2_AXI_ACLK : in std_logic;
S2_AXI_ARESETN : in std_logic;
S2_AXI_AWADDR : in std_logic_vector(C_S2_AXI_ADDR_WIDTH-1 downto 0);
S2_AXI_AWVALID : in std_logic;
S2_AXI_AWREADY : out std_logic;
S2_AXI_WDATA : in std_logic_vector(C_S2_AXI_DATA_WIDTH-1 downto 0);
S2_AXI_WSTRB : in std_logic_vector((C_S2_AXI_DATA_WIDTH/8)-1 downto 0);
S2_AXI_WVALID : in std_logic;
S2_AXI_WREADY : out std_logic;
S2_AXI_BRESP : out std_logic_vector(1 downto 0);
S2_AXI_BVALID : out std_logic;
S2_AXI_BREADY : in std_logic;
S2_AXI_ARADDR : in std_logic_vector(C_S2_AXI_ADDR_WIDTH-1 downto 0);
S2_AXI_ARVALID : in std_logic;
S2_AXI_ARREADY : out std_logic;
S2_AXI_RDATA : out std_logic_vector(C_S2_AXI_DATA_WIDTH-1 downto 0);
S2_AXI_RRESP : out std_logic_vector(1 downto 0);
S2_AXI_RVALID : out std_logic;
S2_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #3 slave signals.
S3_AXI_ACLK : in std_logic;
S3_AXI_ARESETN : in std_logic;
S3_AXI_AWADDR : in std_logic_vector(C_S3_AXI_ADDR_WIDTH-1 downto 0);
S3_AXI_AWVALID : in std_logic;
S3_AXI_AWREADY : out std_logic;
S3_AXI_WDATA : in std_logic_vector(C_S3_AXI_DATA_WIDTH-1 downto 0);
S3_AXI_WSTRB : in std_logic_vector((C_S3_AXI_DATA_WIDTH/8)-1 downto 0);
S3_AXI_WVALID : in std_logic;
S3_AXI_WREADY : out std_logic;
S3_AXI_BRESP : out std_logic_vector(1 downto 0);
S3_AXI_BVALID : out std_logic;
S3_AXI_BREADY : in std_logic;
S3_AXI_ARADDR : in std_logic_vector(C_S3_AXI_ADDR_WIDTH-1 downto 0);
S3_AXI_ARVALID : in std_logic;
S3_AXI_ARREADY : out std_logic;
S3_AXI_RDATA : out std_logic_vector(C_S3_AXI_DATA_WIDTH-1 downto 0);
S3_AXI_RRESP : out std_logic_vector(1 downto 0);
S3_AXI_RVALID : out std_logic;
S3_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #4 slave signals.
S4_AXI_ACLK : in std_logic;
S4_AXI_ARESETN : in std_logic;
S4_AXI_AWADDR : in std_logic_vector(C_S4_AXI_ADDR_WIDTH-1 downto 0);
S4_AXI_AWVALID : in std_logic;
S4_AXI_AWREADY : out std_logic;
S4_AXI_WDATA : in std_logic_vector(C_S4_AXI_DATA_WIDTH-1 downto 0);
S4_AXI_WSTRB : in std_logic_vector((C_S4_AXI_DATA_WIDTH/8)-1 downto 0);
S4_AXI_WVALID : in std_logic;
S4_AXI_WREADY : out std_logic;
S4_AXI_BRESP : out std_logic_vector(1 downto 0);
S4_AXI_BVALID : out std_logic;
S4_AXI_BREADY : in std_logic;
S4_AXI_ARADDR : in std_logic_vector(C_S4_AXI_ADDR_WIDTH-1 downto 0);
S4_AXI_ARVALID : in std_logic;
S4_AXI_ARREADY : out std_logic;
S4_AXI_RDATA : out std_logic_vector(C_S4_AXI_DATA_WIDTH-1 downto 0);
S4_AXI_RRESP : out std_logic_vector(1 downto 0);
S4_AXI_RVALID : out std_logic;
S4_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #5 slave signals.
S5_AXI_ACLK : in std_logic;
S5_AXI_ARESETN : in std_logic;
S5_AXI_AWADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S5_AXI_AWVALID : in std_logic;
S5_AXI_AWREADY : out std_logic;
S5_AXI_WDATA : in std_logic_vector(C_S5_AXI_DATA_WIDTH-1 downto 0);
S5_AXI_WSTRB : in std_logic_vector((C_S5_AXI_DATA_WIDTH/8)-1 downto 0);
S5_AXI_WVALID : in std_logic;
S5_AXI_WREADY : out std_logic;
S5_AXI_BRESP : out std_logic_vector(1 downto 0);
S5_AXI_BVALID : out std_logic;
S5_AXI_BREADY : in std_logic;
S5_AXI_ARADDR : in std_logic_vector(C_S5_AXI_ADDR_WIDTH-1 downto 0);
S5_AXI_ARVALID : in std_logic;
S5_AXI_ARREADY : out std_logic;
S5_AXI_RDATA : out std_logic_vector(C_S5_AXI_DATA_WIDTH-1 downto 0);
S5_AXI_RRESP : out std_logic_vector(1 downto 0);
S5_AXI_RVALID : out std_logic;
S5_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #6 slave signals.
S6_AXI_ACLK : in std_logic;
S6_AXI_ARESETN : in std_logic;
S6_AXI_AWADDR : in std_logic_vector(C_S6_AXI_ADDR_WIDTH-1 downto 0);
S6_AXI_AWVALID : in std_logic;
S6_AXI_AWREADY : out std_logic;
S6_AXI_WDATA : in std_logic_vector(C_S6_AXI_DATA_WIDTH-1 downto 0);
S6_AXI_WSTRB : in std_logic_vector((C_S6_AXI_DATA_WIDTH/8)-1 downto 0);
S6_AXI_WVALID : in std_logic;
S6_AXI_WREADY : out std_logic;
S6_AXI_BRESP : out std_logic_vector(1 downto 0);
S6_AXI_BVALID : out std_logic;
S6_AXI_BREADY : in std_logic;
S6_AXI_ARADDR : in std_logic_vector(C_S6_AXI_ADDR_WIDTH-1 downto 0);
S6_AXI_ARVALID : in std_logic;
S6_AXI_ARREADY : out std_logic;
S6_AXI_RDATA : out std_logic_vector(C_S6_AXI_DATA_WIDTH-1 downto 0);
S6_AXI_RRESP : out std_logic_vector(1 downto 0);
S6_AXI_RVALID : out std_logic;
S6_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #7 slave signals.
S7_AXI_ACLK : in std_logic;
S7_AXI_ARESETN : in std_logic;
S7_AXI_AWADDR : in std_logic_vector(C_S7_AXI_ADDR_WIDTH-1 downto 0);
S7_AXI_AWVALID : in std_logic;
S7_AXI_AWREADY : out std_logic;
S7_AXI_WDATA : in std_logic_vector(C_S7_AXI_DATA_WIDTH-1 downto 0);
S7_AXI_WSTRB : in std_logic_vector((C_S7_AXI_DATA_WIDTH/8)-1 downto 0);
S7_AXI_WVALID : in std_logic;
S7_AXI_WREADY : out std_logic;
S7_AXI_BRESP : out std_logic_vector(1 downto 0);
S7_AXI_BVALID : out std_logic;
S7_AXI_BREADY : in std_logic;
S7_AXI_ARADDR : in std_logic_vector(C_S7_AXI_ADDR_WIDTH-1 downto 0);
S7_AXI_ARVALID : in std_logic;
S7_AXI_ARREADY : out std_logic;
S7_AXI_RDATA : out std_logic_vector(C_S7_AXI_DATA_WIDTH-1 downto 0);
S7_AXI_RRESP : out std_logic_vector(1 downto 0);
S7_AXI_RVALID : out std_logic;
S7_AXI_RREADY : in std_logic
);
end entity mutex;
library unisim;
use unisim.all;
architecture IMP of mutex is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
-- Returns at least 1
function MakePos(a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
-- Returns the minimum value of the two parameters
function IntMin(a, b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function IntMin;
-- Returns the maximum value of the two parameters
function IntMax(a, b : integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function IntMax;
-- Returns the maximum value of the two parameters
function IntSelect(s : boolean; a, b : integer) return integer is
begin
if s then
return a;
else
return b;
end if;
end function IntSelect;
function Get_Num_Bits(data : natural) return natural is
variable num_bits : natural:= 1;
begin
while( data > 2**num_bits ) loop
num_bits := num_bits + 1;
end loop;
return num_bits;
end function Get_Num_Bits;
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-- Mutex specific.
constant C_NUM_INTERFACE : integer range 1 to 16 := C_NUM_AXI;
-- Number of interfaces to access Mutexes.
constant C_AXI_HW_ID_WIDTH : integer:= IntMax(IntMax(IntMax(IntSelect(C_NUM_AXI>0,1,0),
IntSelect(C_NUM_AXI>1,1,0)),
IntMax(IntSelect(C_NUM_AXI>2,1,0),
IntSelect(C_NUM_AXI>3,1,0))),
IntMax(IntMax(IntSelect(C_NUM_AXI>4,1,0),
IntSelect(C_NUM_AXI>5,1,0)),
IntMax(IntSelect(C_NUM_AXI>6,1,0),
IntSelect(C_NUM_AXI>7,1,0))));
constant C_HW_ID_WIDTH : integer:= C_AXI_HW_ID_WIDTH;
constant C_REGISTER_WIDTH : integer := 8; -- Width of register offset.
constant C_AWIDTH : integer := C_REGISTER_WIDTH + Get_Num_Bits(C_NUM_MUTEX);
-- Address bits including register offset.
constant C_DWIDTH : integer := 32; -- Width of data bus.
constant C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
constant C_DWIDTH_MUTEX : integer := 1; -- Width of mutex field (usually 1).
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component axi_decode is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_DWIDTH : integer := 32 -- Width of data bus.
);
port (
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Mutex signals.
Mutex_Clk : in std_logic;
Mutex_Rst : in std_logic;
Mutex_Access : out std_logic;
Mutex_RnW : out std_logic;
Mutex_HW_Id : out std_logic_vector(0 to C_HW_ID_WIDTH - 1);
Mutex_Addr : out std_logic_vector(0 to C_AWIDTH - 1);
Mutex_Wr_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Rd_Data : in std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : in std_logic
);
end component axi_decode;
component mutex_core is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- Mutex specific.
C_NUM_INTERFACE : integer range 1 to 16 := 1; -- Number of interfaces to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 1; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16; -- Number of mutexes.
C_MUTEX_NUMBER : integer := 0; -- Mutex number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_REGISTER_WIDTH : integer := 4; -- Width of register offset.
C_DWIDTH : integer := 32; -- Width of data bus.
C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
C_DWIDTH_MUTEX : integer := 1 -- Width of mutex field (usually 1).
);
port (
-- System signals
Clk : in std_logic;
Rst : in std_logic;
-- Bus slave signals
Mutex_Access : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_RnW : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_HW_Id : in std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
Mutex_Addr : in std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
Mutex_Wr_Data : in std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
Mutex_Rd_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : out std_logic_vector(0 to C_NUM_INTERFACE - 1)
);
end component mutex_core;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
-- Internal MUTEX signals.
signal Mutex_Clk : std_logic;
signal Mutex_Rst : std_logic;
signal Mutex_Access : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_RnW : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_HW_Id : std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
signal Mutex_Addr : std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
signal Mutex_Wr_Data : std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
signal Mutex_Rd_Data : std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
signal Mutex_Ack : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_Rd_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #0
-----------------------------------------------------------------------------
Using_AXI_0: if C_NUM_AXI > 0 generate
begin
AXI_If_0: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S0_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S0_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S0_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S0_AXI_DATA_WIDTH,
C_ASYNC_CLKS => 0,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S0_AXI_ACLK,
S_AXI_ARESETN => S0_AXI_ARESETN,
S_AXI_AWADDR => S0_AXI_AWADDR,
S_AXI_AWVALID => S0_AXI_AWVALID,
S_AXI_AWREADY => S0_AXI_AWREADY,
S_AXI_WDATA => S0_AXI_WDATA,
S_AXI_WSTRB => S0_AXI_WSTRB,
S_AXI_WVALID => S0_AXI_WVALID,
S_AXI_WREADY => S0_AXI_WREADY,
S_AXI_BRESP => S0_AXI_BRESP,
S_AXI_BVALID => S0_AXI_BVALID,
S_AXI_BREADY => S0_AXI_BREADY,
S_AXI_ARADDR => S0_AXI_ARADDR,
S_AXI_ARVALID => S0_AXI_ARVALID,
S_AXI_ARREADY => S0_AXI_ARREADY,
S_AXI_RDATA => S0_AXI_RDATA,
S_AXI_RRESP => S0_AXI_RRESP,
S_AXI_RVALID => S0_AXI_RVALID,
S_AXI_RREADY => S0_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(0),
Mutex_RnW => Mutex_RnW(0),
Mutex_HW_Id => Mutex_HW_Id((0) * C_HW_ID_WIDTH to (1) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((0) * C_AWIDTH to (1) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((0) * C_DWIDTH to (1) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((0) * C_DWIDTH to (1) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(0)
);
end generate Using_AXI_0;
No_AXI_0: if C_NUM_AXI < 1 generate
begin
S0_AXI_AWREADY <= '0';
S0_AXI_WREADY <= '0';
S0_AXI_BRESP <= (others=>'0');
S0_AXI_BVALID <= '0';
S0_AXI_ARREADY <= '0';
S0_AXI_RDATA <= (others=>'0');
S0_AXI_RRESP <= (others=>'0');
S0_AXI_RVALID <= '0';
end generate No_AXI_0;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #1
-----------------------------------------------------------------------------
Using_AXI_1: if C_NUM_AXI > 1 generate
begin
AXI_If_1: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S1_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S1_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S1_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S1_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S1_AXI_ACLK,
S_AXI_ARESETN => S1_AXI_ARESETN,
S_AXI_AWADDR => S1_AXI_AWADDR,
S_AXI_AWVALID => S1_AXI_AWVALID,
S_AXI_AWREADY => S1_AXI_AWREADY,
S_AXI_WDATA => S1_AXI_WDATA,
S_AXI_WSTRB => S1_AXI_WSTRB,
S_AXI_WVALID => S1_AXI_WVALID,
S_AXI_WREADY => S1_AXI_WREADY,
S_AXI_BRESP => S1_AXI_BRESP,
S_AXI_BVALID => S1_AXI_BVALID,
S_AXI_BREADY => S1_AXI_BREADY,
S_AXI_ARADDR => S1_AXI_ARADDR,
S_AXI_ARVALID => S1_AXI_ARVALID,
S_AXI_ARREADY => S1_AXI_ARREADY,
S_AXI_RDATA => S1_AXI_RDATA,
S_AXI_RRESP => S1_AXI_RRESP,
S_AXI_RVALID => S1_AXI_RVALID,
S_AXI_RREADY => S1_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(1),
Mutex_RnW => Mutex_RnW(1),
Mutex_HW_Id => Mutex_HW_Id((1) * C_HW_ID_WIDTH to (2) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((1) * C_AWIDTH to (2) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((1) * C_DWIDTH to (2) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((1) * C_DWIDTH to (2) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(1)
);
end generate Using_AXI_1;
No_AXI_1: if C_NUM_AXI < 2 generate
begin
S1_AXI_AWREADY <= '0';
S1_AXI_WREADY <= '0';
S1_AXI_BRESP <= (others=>'0');
S1_AXI_BVALID <= '0';
S1_AXI_ARREADY <= '0';
S1_AXI_RDATA <= (others=>'0');
S1_AXI_RRESP <= (others=>'0');
S1_AXI_RVALID <= '0';
end generate No_AXI_1;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #2
-----------------------------------------------------------------------------
Using_AXI_2: if C_NUM_AXI > 2 generate
begin
AXI_If_2: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S2_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S2_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S2_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S2_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S2_AXI_ACLK,
S_AXI_ARESETN => S2_AXI_ARESETN,
S_AXI_AWADDR => S2_AXI_AWADDR,
S_AXI_AWVALID => S2_AXI_AWVALID,
S_AXI_AWREADY => S2_AXI_AWREADY,
S_AXI_WDATA => S2_AXI_WDATA,
S_AXI_WSTRB => S2_AXI_WSTRB,
S_AXI_WVALID => S2_AXI_WVALID,
S_AXI_WREADY => S2_AXI_WREADY,
S_AXI_BRESP => S2_AXI_BRESP,
S_AXI_BVALID => S2_AXI_BVALID,
S_AXI_BREADY => S2_AXI_BREADY,
S_AXI_ARADDR => S2_AXI_ARADDR,
S_AXI_ARVALID => S2_AXI_ARVALID,
S_AXI_ARREADY => S2_AXI_ARREADY,
S_AXI_RDATA => S2_AXI_RDATA,
S_AXI_RRESP => S2_AXI_RRESP,
S_AXI_RVALID => S2_AXI_RVALID,
S_AXI_RREADY => S2_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(2),
Mutex_RnW => Mutex_RnW(2),
Mutex_HW_Id => Mutex_HW_Id((2) * C_HW_ID_WIDTH to (3) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((2) * C_AWIDTH to (3) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((2) * C_DWIDTH to (3) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((2) * C_DWIDTH to (3) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(2)
);
end generate Using_AXI_2;
No_AXI_2: if C_NUM_AXI < 3 generate
begin
S2_AXI_AWREADY <= '0';
S2_AXI_WREADY <= '0';
S2_AXI_BRESP <= (others=>'0');
S2_AXI_BVALID <= '0';
S2_AXI_ARREADY <= '0';
S2_AXI_RDATA <= (others=>'0');
S2_AXI_RRESP <= (others=>'0');
S2_AXI_RVALID <= '0';
end generate No_AXI_2;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #3
-----------------------------------------------------------------------------
Using_AXI_3: if C_NUM_AXI > 3 generate
begin
AXI_If_3: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S3_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S3_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S3_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S3_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S3_AXI_ACLK,
S_AXI_ARESETN => S3_AXI_ARESETN,
S_AXI_AWADDR => S3_AXI_AWADDR,
S_AXI_AWVALID => S3_AXI_AWVALID,
S_AXI_AWREADY => S3_AXI_AWREADY,
S_AXI_WDATA => S3_AXI_WDATA,
S_AXI_WSTRB => S3_AXI_WSTRB,
S_AXI_WVALID => S3_AXI_WVALID,
S_AXI_WREADY => S3_AXI_WREADY,
S_AXI_BRESP => S3_AXI_BRESP,
S_AXI_BVALID => S3_AXI_BVALID,
S_AXI_BREADY => S3_AXI_BREADY,
S_AXI_ARADDR => S3_AXI_ARADDR,
S_AXI_ARVALID => S3_AXI_ARVALID,
S_AXI_ARREADY => S3_AXI_ARREADY,
S_AXI_RDATA => S3_AXI_RDATA,
S_AXI_RRESP => S3_AXI_RRESP,
S_AXI_RVALID => S3_AXI_RVALID,
S_AXI_RREADY => S3_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(3),
Mutex_RnW => Mutex_RnW(3),
Mutex_HW_Id => Mutex_HW_Id((3) * C_HW_ID_WIDTH to (4) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((3) * C_AWIDTH to (4) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((3) * C_DWIDTH to (4) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((3) * C_DWIDTH to (4) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(3)
);
end generate Using_AXI_3;
No_AXI_3: if C_NUM_AXI < 4 generate
begin
S3_AXI_AWREADY <= '0';
S3_AXI_WREADY <= '0';
S3_AXI_BRESP <= (others=>'0');
S3_AXI_BVALID <= '0';
S3_AXI_ARREADY <= '0';
S3_AXI_RDATA <= (others=>'0');
S3_AXI_RRESP <= (others=>'0');
S3_AXI_RVALID <= '0';
end generate No_AXI_3;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #4
-----------------------------------------------------------------------------
Using_AXI_4: if C_NUM_AXI > 4 generate
begin
AXI_If_4: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S4_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S4_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S4_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S4_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S4_AXI_ACLK,
S_AXI_ARESETN => S4_AXI_ARESETN,
S_AXI_AWADDR => S4_AXI_AWADDR,
S_AXI_AWVALID => S4_AXI_AWVALID,
S_AXI_AWREADY => S4_AXI_AWREADY,
S_AXI_WDATA => S4_AXI_WDATA,
S_AXI_WSTRB => S4_AXI_WSTRB,
S_AXI_WVALID => S4_AXI_WVALID,
S_AXI_WREADY => S4_AXI_WREADY,
S_AXI_BRESP => S4_AXI_BRESP,
S_AXI_BVALID => S4_AXI_BVALID,
S_AXI_BREADY => S4_AXI_BREADY,
S_AXI_ARADDR => S4_AXI_ARADDR,
S_AXI_ARVALID => S4_AXI_ARVALID,
S_AXI_ARREADY => S4_AXI_ARREADY,
S_AXI_RDATA => S4_AXI_RDATA,
S_AXI_RRESP => S4_AXI_RRESP,
S_AXI_RVALID => S4_AXI_RVALID,
S_AXI_RREADY => S4_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(4),
Mutex_RnW => Mutex_RnW(4),
Mutex_HW_Id => Mutex_HW_Id((4) * C_HW_ID_WIDTH to (5) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((4) * C_AWIDTH to (5) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((4) * C_DWIDTH to (5) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((4) * C_DWIDTH to (5) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(4)
);
end generate Using_AXI_4;
No_AXI_4: if C_NUM_AXI < 5 generate
begin
S4_AXI_AWREADY <= '0';
S4_AXI_WREADY <= '0';
S4_AXI_BRESP <= (others=>'0');
S4_AXI_BVALID <= '0';
S4_AXI_ARREADY <= '0';
S4_AXI_RDATA <= (others=>'0');
S4_AXI_RRESP <= (others=>'0');
S4_AXI_RVALID <= '0';
end generate No_AXI_4;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #5
-----------------------------------------------------------------------------
Using_AXI_5: if C_NUM_AXI > 5 generate
begin
AXI_If_5: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S5_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S5_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S5_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S5_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S5_AXI_ACLK,
S_AXI_ARESETN => S5_AXI_ARESETN,
S_AXI_AWADDR => S5_AXI_AWADDR,
S_AXI_AWVALID => S5_AXI_AWVALID,
S_AXI_AWREADY => S5_AXI_AWREADY,
S_AXI_WDATA => S5_AXI_WDATA,
S_AXI_WSTRB => S5_AXI_WSTRB,
S_AXI_WVALID => S5_AXI_WVALID,
S_AXI_WREADY => S5_AXI_WREADY,
S_AXI_BRESP => S5_AXI_BRESP,
S_AXI_BVALID => S5_AXI_BVALID,
S_AXI_BREADY => S5_AXI_BREADY,
S_AXI_ARADDR => S5_AXI_ARADDR,
S_AXI_ARVALID => S5_AXI_ARVALID,
S_AXI_ARREADY => S5_AXI_ARREADY,
S_AXI_RDATA => S5_AXI_RDATA,
S_AXI_RRESP => S5_AXI_RRESP,
S_AXI_RVALID => S5_AXI_RVALID,
S_AXI_RREADY => S5_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(5),
Mutex_RnW => Mutex_RnW(5),
Mutex_HW_Id => Mutex_HW_Id((5) * C_HW_ID_WIDTH to (6) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((5) * C_AWIDTH to (6) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((5) * C_DWIDTH to (6) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((5) * C_DWIDTH to (6) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(5)
);
end generate Using_AXI_5;
No_AXI_5: if C_NUM_AXI < 6 generate
begin
S5_AXI_AWREADY <= '0';
S5_AXI_WREADY <= '0';
S5_AXI_BRESP <= (others=>'0');
S5_AXI_BVALID <= '0';
S5_AXI_ARREADY <= '0';
S5_AXI_RDATA <= (others=>'0');
S5_AXI_RRESP <= (others=>'0');
S5_AXI_RVALID <= '0';
end generate No_AXI_5;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #6
-----------------------------------------------------------------------------
Using_AXI_6: if C_NUM_AXI > 6 generate
begin
AXI_If_6: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S6_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S6_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S6_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S6_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S6_AXI_ACLK,
S_AXI_ARESETN => S6_AXI_ARESETN,
S_AXI_AWADDR => S6_AXI_AWADDR,
S_AXI_AWVALID => S6_AXI_AWVALID,
S_AXI_AWREADY => S6_AXI_AWREADY,
S_AXI_WDATA => S6_AXI_WDATA,
S_AXI_WSTRB => S6_AXI_WSTRB,
S_AXI_WVALID => S6_AXI_WVALID,
S_AXI_WREADY => S6_AXI_WREADY,
S_AXI_BRESP => S6_AXI_BRESP,
S_AXI_BVALID => S6_AXI_BVALID,
S_AXI_BREADY => S6_AXI_BREADY,
S_AXI_ARADDR => S6_AXI_ARADDR,
S_AXI_ARVALID => S6_AXI_ARVALID,
S_AXI_ARREADY => S6_AXI_ARREADY,
S_AXI_RDATA => S6_AXI_RDATA,
S_AXI_RRESP => S6_AXI_RRESP,
S_AXI_RVALID => S6_AXI_RVALID,
S_AXI_RREADY => S6_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(6),
Mutex_RnW => Mutex_RnW(6),
Mutex_HW_Id => Mutex_HW_Id((6) * C_HW_ID_WIDTH to (7) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((6) * C_AWIDTH to (7) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((6) * C_DWIDTH to (7) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((6) * C_DWIDTH to (7) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(6)
);
end generate Using_AXI_6;
No_AXI_6: if C_NUM_AXI < 7 generate
begin
S6_AXI_AWREADY <= '0';
S6_AXI_WREADY <= '0';
S6_AXI_BRESP <= (others=>'0');
S6_AXI_BVALID <= '0';
S6_AXI_ARREADY <= '0';
S6_AXI_RDATA <= (others=>'0');
S6_AXI_RRESP <= (others=>'0');
S6_AXI_RVALID <= '0';
end generate No_AXI_6;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #7
-----------------------------------------------------------------------------
Using_AXI_7: if C_NUM_AXI > 7 generate
begin
AXI_If_7: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S7_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S7_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S7_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S7_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S7_AXI_ACLK,
S_AXI_ARESETN => S7_AXI_ARESETN,
S_AXI_AWADDR => S7_AXI_AWADDR,
S_AXI_AWVALID => S7_AXI_AWVALID,
S_AXI_AWREADY => S7_AXI_AWREADY,
S_AXI_WDATA => S7_AXI_WDATA,
S_AXI_WSTRB => S7_AXI_WSTRB,
S_AXI_WVALID => S7_AXI_WVALID,
S_AXI_WREADY => S7_AXI_WREADY,
S_AXI_BRESP => S7_AXI_BRESP,
S_AXI_BVALID => S7_AXI_BVALID,
S_AXI_BREADY => S7_AXI_BREADY,
S_AXI_ARADDR => S7_AXI_ARADDR,
S_AXI_ARVALID => S7_AXI_ARVALID,
S_AXI_ARREADY => S7_AXI_ARREADY,
S_AXI_RDATA => S7_AXI_RDATA,
S_AXI_RRESP => S7_AXI_RRESP,
S_AXI_RVALID => S7_AXI_RVALID,
S_AXI_RREADY => S7_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(7),
Mutex_RnW => Mutex_RnW(7),
Mutex_HW_Id => Mutex_HW_Id((7) * C_HW_ID_WIDTH to (8) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((7) * C_AWIDTH to (8) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((7) * C_DWIDTH to (8) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((7) * C_DWIDTH to (8) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(7)
);
end generate Using_AXI_7;
No_AXI_7: if C_NUM_AXI < 8 generate
begin
S7_AXI_AWREADY <= '0';
S7_AXI_WREADY <= '0';
S7_AXI_BRESP <= (others=>'0');
S7_AXI_BVALID <= '0';
S7_AXI_ARREADY <= '0';
S7_AXI_RDATA <= (others=>'0');
S7_AXI_RRESP <= (others=>'0');
S7_AXI_RVALID <= '0';
end generate No_AXI_7;
-----------------------------------------------------------------------------
-- Instantiating MUTEX Core
-----------------------------------------------------------------------------
Mutex_Clk <= S0_AXI_ACLK;
Mutex_Rst <= not S0_AXI_ARESETN;
SingleAccess: mutex_core
generic map(
-- General.
C_FAMILY => C_FAMILY,
-- Mutex specific.
C_NUM_INTERFACE => C_NUM_INTERFACE,
C_ENABLE_USER => C_ENABLE_USER,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_ENABLE_HW_PROT => C_ENABLE_HW_PROT,
C_NUM_MUTEX => C_NUM_MUTEX,
C_MUTEX_NUMBER => 0,
C_AWIDTH => C_AWIDTH,
C_REGISTER_WIDTH => C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH,
C_DWIDTH_MUTEX => C_DWIDTH_MUTEX
)
port map(
-- System signals
Clk => Mutex_Clk,
Rst => Mutex_Rst,
-- Bus slave signals
Mutex_Access => Mutex_Access,
Mutex_RnW => Mutex_RnW,
Mutex_HW_Id => Mutex_HW_Id,
Mutex_Addr => Mutex_Addr,
Mutex_Wr_Data => Mutex_Wr_Data,
Mutex_Rd_Data => Mutex_Rd_Data_I,
Mutex_Ack => Mutex_Ack
);
-- Distribute result to all interfaces.
If_Num_Distr: for I in 0 to C_NUM_INTERFACE - 1 generate
begin
Mutex_Rd_Data(I * C_DWIDTH to (I + 1) * C_DWIDTH - 1) <= Mutex_Rd_Data_I;
end generate If_Num_Distr;
end architecture IMP;
|
mit
|
c4dc79693d9536570de5004a5205c43d
| 0.480326 | 3.946988 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/neander_tb.vhd
| 1 | 1,483 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ramses_tb IS
END ramses_tb;
ARCHITECTURE behavior OF ramses_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ramses
PORT(
clk_in : IN std_logic;
rst_in : IN std_logic;
enable_ramses : IN std_logic;
debug_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_in : std_logic := '0';
signal rst_in : std_logic := '0';
signal enable_ramses : std_logic := '0';
--Outputs
signal debug_out : std_logic;
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ramses PORT MAP (
clk_in => clk_in,
rst_in => rst_in,
enable_ramses => enable_ramses,
debug_out => debug_out
);
-- Clock process definitions
clk_in_process :process
begin
clk_in <= '0';
wait for clock_period/2;
clk_in <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10us.
rst_in <= '1';
enable_ramses <= '0';
wait for clock_period*5;
rst_in <= '0';
wait for clock_period*5;
wait until rising_edge(clk_in);
enable_ramses <= '1';
--wait for clock_period*50;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
7c14ab0ede36b7359c3802b12ca1a5e1
| 0.581254 | 3.489412 | false | false | false | false |
inforichland/freezing-spice
|
src/ex.vhd
| 1 | 2,151 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.ex_pkg.all;
entity instruction_executor is
port (ex_d : in ex_in;
ex_q : out ex_out);
end entity instruction_executor;
architecture Behavioral of instruction_executor is
signal op1 : word;
signal op2 : word;
signal alu_out : word;
signal compare_result : std_logic;
signal return_addr : unsigned(word'range);
constant c_four : unsigned(2 downto 0) := to_unsigned(4, 3);
begin -- architecture Behavioral
-- assign modules outputs
ex_q.alu_result <= alu_out;
ex_q.compare_result <= compare_result;
ex_q.return_addr <= std_logic_vector(return_addr);
-- ALU operand 1 multiplexer
op1 <= ex_d.npc when (ex_d.insn_type = OP_BRANCH or
ex_d.insn_type = OP_JAL or
ex_d.insn_type = OP_JALR or
ex_d.insn_type = OP_AUIPC)
else ex_d.op1;
-- ALU operand 2 multiplexer
op2 <= ex_d.imm when ((ex_d.insn_type = OP_ALU and ex_d.use_imm = '1') or
ex_d.insn_type = OP_BRANCH or
ex_d.insn_type = OP_JAL or
ex_d.insn_type = OP_JALR or
ex_d.insn_type = OP_LOAD or
ex_d.insn_type = OP_STORE or
ex_d.insn_type = OP_AUIPC)
else ex_d.op2;
-- ALU
arithmetic_logic_unit : entity work.alu(Behavioral)
port map (alu_func => ex_d.alu_func,
op1 => op1,
op2 => op2,
result => alu_out);
-- compare unit
conditionals : entity work.compare_unit(Behavioral)
port map (branch_type => ex_d.branch_type,
op1 => op1,
op2 => op2,
compare_result => compare_result);
-- return address for JAL/JALR
return_addr <= unsigned(ex_d.npc) + c_four;
end architecture Behavioral;
|
bsd-3-clause
|
52517fec62b8076f56e83a10ea4f7c08
| 0.504881 | 3.74087 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Phoenix_RM.vhd
| 1 | 5,774 |
---------------------------------------------------------
-- Routing Mechanism
---------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.PhoenixPackage.all;
use work.TablePackage.all;
entity routingMechanism is
generic(address : regmetadeflit := (others=>'0'));
port(
clock : in std_logic;
reset : in std_logic;
buffCtrl: in buffControl; -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
ctrl : in std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
operacao: in regflit; -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
ceT: in std_logic; -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
oe : in std_logic;
dest : in reg8;
inputPort : in integer range 0 to (NPORT-1); -- porta de entrada selecionada pelo arbitro para ser chaveada
outputPort : out regNPort; -- indica qual porta de saida o pacote sera encaminhado
find : out RouterControl
);
end routingMechanism;
architecture behavior of routingMechanism is
-- sinais da máquina de estado
type state is (S0,S1,S2,S3,S4);
signal ES, PES : state;
-- sinais da Tabela
signal ce: std_logic := '0';
signal data : std_logic_vector(4 downto 0) := (others=>'0');
signal rowDst, colDst : integer;
type row is array ((NREG-1) downto 0) of integer;
signal rowInf, colInf, rowSup, colSup : row;
signal H : std_logic_vector((NREG-1) downto 0);
-------------New Hardware---------------
signal VertInf, VertSup : regAddr;
signal func : STD_LOGIC_VECTOR(7 downto 0);
signal OP : STD_LOGIC_VECTOR(4 downto 0);
type arrayIP is array ((NREG-1) downto 0) of std_logic_vector(4 downto 0);
signal IP : arrayIP;
signal IP_lido: STD_LOGIC_VECTOR(4 downto 0);
signal i : integer := 0;
signal RAM: memory := TAB(ADDRESS_TO_NUMBER_NOIA(address));
begin
rowDst <= TO_INTEGER(unsigned(dest(7 downto 4))) when ctrl = '0' else 0;
colDst <= TO_INTEGER(unsigned(dest(3 downto 0))) when ctrl = '0' else 0;
cond: for j in 0 to (NREG - 1) generate
rowInf(j) <= TO_INTEGER(unsigned(RAM(j)(20 downto 17))) when ctrl = '0' else 0;
colInf(j) <= TO_INTEGER(unsigned(RAM(j)(16 downto 13))) when ctrl = '0' else 0;
rowSup(j) <= TO_INTEGER(unsigned(RAM(j)(12 downto 9))) when ctrl = '0' else 0;
colSup(j) <= TO_INTEGER(unsigned(RAM(j)(8 downto 5))) when ctrl = '0' else 0;
IP(j) <= RAM(j)(25 downto 21) when ctrl = '0' else (others=>'0');
H(j) <= '1' when rowDst >= rowInf(j) and rowDst <= rowSup(j) and
colDst >= colInf(j) and colDst <= colSup(j) and
IP(j)(inputPort) = '1' and ctrl = '0' else
'0';
end generate;
process(RAM, H, ce, ctrl)
begin
data <= (others=>'Z');
if ce = '1' and ctrl = '0' then
for i in 0 to (NREG-1) loop
if H(i) = '1' then
data <= RAM(i)(4 downto 0);
end if;
end loop;
end if;
end process;
func <= operacao(7 downto 0);
IP_lido <= buffCtrl(0)(4 downto 0);
VertInf <= buffCtrl(1)(7 downto 0);
VertSup <= buffCtrl(2)(7 downto 0);
OP <= buffCtrl(3)(4 downto 0);
process(ceT,ctrl)
begin
if ctrl = '0' then
i <= 0;
elsif ctrl = '1' and ceT = '1' and func = x"01" then
RAM(i)(25 downto 21) <= IP_lido(4 downto 0);
RAM(i)(20 downto 13) <= VertInf(7 downto 0);
RAM(i)(12 downto 5) <= VertSup(7 downto 0);
RAM(i)(4 downto 0) <= OP(4 downto 0);
if (i = NREG-1) then
i <= 0;
else
i <= i + 1;
end if;
end if;
end process;
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif clock'event and clock='0' then
ES<=PES;
end if;
end process;
------------------------------------------------------------------------------------------------------
-- PARTE COMBINACIONAL PARA DEFINIR O PROXIMO ESTADO DA MAQUINA
--
-- S0 -> Este estado espera oe = '1' (operation enabled), indicando que ha um pacote que que deve
-- ser roteado.
-- S1 -> Este estado ocorre a leitura na memeria - tabela, a fim de obter as
-- definicoes de uma regiao.
-- S2 -> Este estado verifica se o roteador destino (destRouter) pertence aquela
-- regiao. Caso ele pertenca, o sinal de RM eh ativado e a maquina de estados
-- avanca para o proximo estado, caso contrario retorna para o estado S1 e
-- busca por uma nova regiao.
-- S3 -> Neste estado o switch control eh avisado (find="01") que foi descoberto por
-- qual porta este pacote deve sair. Este estado tambem zera count, valor que
-- aponta qual o proximo endereco deve ser lido na memoria.
-- S4 -> Aguarda oe = '0' e retorna para o estado S0.
process(ES, oe)
begin
case ES is
when S0 => if oe = '1' then PES <= S1; else PES <= S0; end if;
when S1 => PES <= S2;
when S2 => PES <= S3;
when S3 => if oe = '0' then PES <= S0; else PES <= S3; end if;
when others => PES <= S0;
end case;
end process;
------------------------------------------------------------------------------------------------------
-- executa as acoes correspondente ao estado atual da maquina de estados
------------------------------------------------------------------------------------------------------
process(clock)
begin
if(clock'event and clock = '1') then
case ES is
-- Aguarda oe='1'
when S0 =>
find <= invalidRegion;
-- Leitura da tabela
when S1 =>
ce <= '1';
-- Informa que achou a porta de saida para o pacote
when S2 =>
find <= validRegion;
-- Aguarda oe='0'
when S3 =>
ce <= '0';
find <= invalidRegion;
when others =>
find <= portError;
end case;
end if;
end process;
outputPort <= data;
end behavior;
|
lgpl-3.0
|
de719ddcaf430f0d1d4a1112aa5569b3
| 0.588327 | 3.218506 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AA.vhd
| 1 | 415 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LatchSR_AA is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end LatchSR_AA;
architecture Behavioral of LatchSR_AA is
signal Q_aux : std_logic := '0';
signal Qn_aux : std_logic := '0';
begin
Q <= Q_aux;
Qn <= Qn_aux;
Q_aux <= R nor Qn_aux;
Qn_aux <= S nor Q_aux;
end Behavioral;
|
gpl-3.0
|
47da4658b3a44b9dc47a74de9bc1013b
| 0.585542 | 2.785235 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Phoenix_buffer.vhd
| 1 | 35,952 |
---------------------------------------------------------------------------------------
-- BUFFER
-- --------------
-- RX ->| |-> H
-- DATA_IN ->| |<- ACK_H
-- CLOCK_RX ->| |
-- CREDIT_O <-| |-> DATA_AV
-- | |-> DATA
-- | |<- DATA_ACK
-- | |
-- | |
-- | |=> SENDER
-- | | all ports
-- --------------
--
-- Quando o algoritmo de chaveamento resulta no bloqueio dos flits de um pacote,
-- ocorre uma perda de desempenho em toda rede de interconexao, porque os flits sao
-- bloqueados nao somente na chave atual, mas em todas as intermediarias.
-- Para diminuir a perda de desempenho foi adicionada uma fila em cada porta de
-- entrada da chave, reduzindo as chaves afetadas com o bloqueio dos flits de um
-- pacote. E importante observar que quanto maior for o tamanho da fila menor sera o
-- numero de chaves intermediarias afetadas.
-- As filas usadas contem dimensao e largura de flit parametrizaveis, para altera-las
-- modifique as constantes TAM_BUFFER e TAM_FLIT no arquivo "Phoenix_packet.vhd".
-- As filas funcionam como FIFOs circulares. Cada fila possui dois ponteiros: first e
-- last. First aponta para a posicao da fila onde se encontra o flit a ser consumido.
-- Last aponta para a posicao onde deve ser inserido o proximo flit.
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
use work.HammingPack16.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
use STD.textio.all;
-- interface da Phoenix_buffer
entity Phoenix_buffer is
generic(address : regmetadeflit := (others=>'0');
bufLocation: integer := 0);
port(
clock: in std_logic;
reset: in std_logic;
clock_rx: in std_logic;
rx: in std_logic;
data_in: in regflit;
credit_o: out std_logic;
h: out std_logic; -- requisicao de chaveamento
c_ctrl: out std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
c_buffCtrlOut:out buffControl; -- linha da tabela de roteamento lida do pacote de controle que sera escrita na tabela de roteamento
c_buffCtrlFalha:out row_FaultTable_Ports; -- tabela de falhas lida do pacote de controle que solicitou escrever/atualizar a tabela
c_codigoCtrl: out regFlit; -- tipo do pacote de controle (leitura do Code). Terceiro flit do pacote de controle
c_chipETable: out std_logic; -- chip enable da tabela de roteamento
c_ceTF_out: out std_logic; -- ce (chip enable) para escrever/atualizar a tabela de falhas
c_error_find: in RouterControl; -- indica se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
c_error_dir : in regNport; -- indica qual destino/porta de saida o pacote sera encaminhado
c_tabelaFalhas :in row_FaultTable_Ports; -- tabela de falhas atualizada/final
ack_h: in std_logic; -- resposta da requisicao de chaveamento
data_av: out std_logic;
data: out regflit;
data_ack: in std_logic;
sender: out std_logic;
c_strLinkTst: out std_logic; -- (start link test) indica que houve um pacote de controle do tipo TEST_LINKS para testar os links. Comentario antigo: send to router (testa as falhas)
c_strLinkTstOthers: in std_logic; -- indica se algum vizinho pediu para testar o link
c_strLinkTstNeighbor: in std_logic; -- indica se o vizinho pediu para testar o link
c_strLinkTstAll: in std_logic; -- se algum buffer fez o pedido de teste de links
c_stpLinkTst: in std_logic; -- (stop link test) indica se algum vizinho pediu para testar o link. Gerado pelo FaultDetection
retransmission_in: in std_logic;
retransmission_out: out std_logic;
statusHamming: in reg3);
end Phoenix_buffer;
architecture Phoenix_buffer of Phoenix_buffer is
type fila_out is (S_INIT, S_PAYLOAD, S_SENDHEADER, S_HEADER, S_END, S_END2,C_PAYLOAD,C_SIZE);
signal EA : fila_out;
signal buf: buff := (others=>(others=>'0'));
signal first,last: pointer := (others=>'0');
signal tem_espaco: std_logic := '0';
signal counter_flit: regflit := (others=>'0');
signal eh_controle : std_logic := '0';
signal buffCtrl : buffControl := (others=>(others=>'0')); -- XY | XY | DIR
signal codigoControl : regflit:= (others=>'0');
signal buffCtrlFalha : row_FaultTable_Ports := (others=>(others=>'0'));
signal ceTF_out : std_logic := '0';
signal c_error : std_logic := '0'; -- '0' sem erro para o destino, '1' com erro para o destino
signal c_direcao: regNport :=(others=>'0'); -- registrador com a direcao que esta mandando o pacote
signal c_createmessage : std_logic := '0'; -- sinal usado para criar um pacote de controle com a tabela de falhas
signal c_Buffer : regflit := (others=>'0'); -- dado de saida gerado ao criar um pacote de controle (pacote de resposta eh criado quando eh pedido leitura da tabela de falhas)
signal c_strLinkTstLocal : std_logic := '0'; -- sinal do pedido de inicio de teste de links
signal old_tabelaFalhas : regNport :=(others=>'0'); -- antiga tabela e falhas com 1 bit para cada porta. '0' indica sem falha, '1' indica com falha
signal discard: std_logic := '0'; -- sinal que indica para voltar a maquina de estados (usada para envio do pacote) para votlar a o estado inicial, pois o pacote sera descartado
signal last_retransmission: regflit := (others=>'0');
signal counter_flit_up: regflit := (others=>'0');
signal last_count_rx: regflit := (others=>'0');
signal retransmission_o: std_logic := '0';
signal pkt_size: regflit := (others=>'0');
begin
retransmission_out <= retransmission_o;
old_tabelaFalhas(LOCAL) <= '0';
old_tabelaFalhas(EAST) <= c_tabelafalhas(EAST)(3*COUNTERS_SIZE+1);
old_tabelaFalhas(WEST) <= c_tabelafalhas(WEST)(3*COUNTERS_SIZE+1);
old_tabelaFalhas(NORTH) <= c_tabelafalhas(NORTH)(3*COUNTERS_SIZE+1);
old_tabelaFalhas(SOUTH) <= c_tabelafalhas(SOUTH)(3*COUNTERS_SIZE+1);
-- sinal indica se tem falha no link destino
c_error <= '1' when (c_direcao and old_tabelafalhas) /= 0 else '0';
-------------------------------------------------------------------------------------------
-- ENTRADA DE DADOS NA FILA
-------------------------------------------------------------------------------------------
-- Verifica se existe espaco na fila para armazenamento de flits.
-- Se existe espaco na fila o sinal tem_espaco_na_fila eh igual a 1.
process(reset, clock_rx)
begin
if reset = '1' then
tem_espaco <= '1';
elsif clock_rx'event and clock_rx = '1' then
if not ((first = x"0" and last = TAM_BUFFER - 1) or (first = last + 1)) then
tem_espaco <= '1';
else
tem_espaco <= '0';
end if;
end if;
end process;
credit_o <= tem_espaco;
-- O ponteiro last eh inicializado com o valor zero quando o reset eh ativado.
-- Quando o sinal rx eh ativado indicando que existe um flit na porta de entrada. Eh
-- verificado se existe espaco na fila para armazena-lo. Se existir espaco na fila o
-- flit recebido eh armazenado na posicao apontada pelo ponteiro last e o mesmo eh
-- incrementado. Quando last atingir o tamanho da fila, ele recebe zero.
process(reset, clock_rx)
variable count: integer;
variable ignore: std_logic := '0';
variable pkt_received: std_logic := '0';
file my_output : TEXT open WRITE_MODE is "retransmission_00"&to_hstring(address)&".txt";
variable my_output_line : LINE;
variable count_retx: integer;
variable total_count_retx: regflit;
begin
if reset = '1' then
last <= (others=>'0');
count := 0;
ignore := '0';
discard <= '0';
last_count_rx <= (others=>'0');
pkt_size <= (others=>'0');
pkt_received := '1';
elsif clock_rx'event and clock_rx = '0' then
if (rx = '0' and (pkt_received='1' or ignore='1')) then
count := 0;
ignore := '0';
discard <= '0';
last_count_rx <= (others=>'1');
pkt_received := '0';
pkt_size <= (others=>'0');
count_retx := 0;
end if;
-- se tenho espaco e se tem alguem enviando, armazena, mas
-- nao queremos armazenar os flits recebidos durante o teste de link, entao
-- se meu roteador esta testando os links ou se o link ligado a este buffer esta sendo testando pelo vizinho, irei ignorar os flits durante o teste
-- o buffer local que eh conectado ao link local (assumido que nunca falha) nunca sera testado
if tem_espaco = '1' and rx = '1' and ((c_strLinkTstAll = '0' and c_strLinkTstNeighbor='0') or bufLocation = LOCAL) then
-- "ignore" eh um auxiliar usado para indicar que estou ignorando os flits que estao chegando, pois
-- o pacote foi descartado. O descarte eh feito ao descartar os flits que ja chegaram (voltando o ponteiro de maneira que possa sobreescrever os flits ja recebidos) e
-- ignorando os flits subsequentes.
if (ignore = '0') then
-- se nao deu erro, esta tudo normal. Posso armazenar o flit no buffer e incrementar o ponteiro
if (statusHamming /= ED) then
retransmission_o <= '0';
-- modifica o ultimo flit do pacote para armazenar o numero de retransmissoes
if (count = pkt_size+1 and pkt_size > 0) then
total_count_retx := data_in;
total_count_retx := total_count_retx + count_retx;
buf(CONV_INTEGER(last)) <= total_count_retx;
else
buf(CONV_INTEGER(last)) <= data_in; -- armazena o flit
end if;
if (count = 1) then
pkt_size <= data_in;
end if;
--incrementa o last
if last = TAM_BUFFER - 1 then
last <= (others=>'0');
else
last <= last + 1;
end if;
count := count + 1;
-- detectado erro e nao corrigido. Posso tentar mais uma vez pedindo retransmissao...
else
count_retx := count_retx + 1;
last_count_rx <= CONV_STD_LOGIC_VECTOR(count,TAM_FLIT);
-- desiste se deu erro duas vezes no mesmo flit
if (last_count_rx = count and count /= 1) then
retransmission_o <= '0';
buf(CONV_INTEGER(last)) <= data_in; -- armazena o flit (mesmo com falha)
--incrementa o last
if last = TAM_BUFFER - 1 then
last <= (others=>'0');
else
last <= last + 1;
end if;
count := count + 1;
else
retransmission_o <= '1';
end if;
end if;
-- se estou no segundo flit recebido e, mesmo depois de pedir retransmissao dele, veio com falha
if (count = 1 and statusHamming = ED and last_count_rx = 1) then
ignore := '1';
retransmission_o <= '0';
-- volta uma posicao o ponteiro last e sinaliza com discard em '1' para reiniciar a maquina de estados que
-- ja estava iniciando o envio do pacote
if (last = 0) then
last <= CONV_STD_LOGIC_VECTOR(TAM_BUFFER-1, TAM_POINTER);
if (first = TAM_BUFFER - 1) then
discard <= '1';
else
discard <= '0';
end if;
else
last <= last - 1;
if (first = last-1) then
discard <= '1';
else
discard <= '0';
end if;
end if;
end if; -- end if do if (count = 1...
if (count = pkt_size+2 and pkt_size > 0) then
pkt_received := '1';
if (bufLocation /= LOCAL) then
write(my_output_line, "Packet in port "&PORT_NAME(bufLocation)&" received "&integer'image(count_retx)&" flits with double error "&time'image(now));
writeline(my_output, my_output_line);
end if;
else
pkt_received := '0';
end if;
-- deixar so um ciclo o discard em '1'
else
discard <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------
-- SAIDA DE DADOS NA FILA
-------------------------------------------------------------------------------------------
-- disponibiliza o dado para transmissao. Se nao estiver criando um pacote de controle, envia normalmente o dado do buffer, caso contrario envia dado criado (c_buffer)
data <= buf(CONV_INTEGER(first)) when c_createmessage ='0' else c_Buffer;
-- Quando sinal reset eh ativado a maquina de estados avanca para o estado S_INIT.
-- No estado S_INIT os sinais counter_flit (contador de flits do corpo do pacote), h (que
-- indica requisicao de chaveamento) e data_av (que indica a existencia de flit a ser
-- transmitido) sao inicializados com zero. Se existir algum flit na fila, ou seja, os
-- ponteiros first e last apontarem para posicoes diferentes, a maquina de estados avanca
-- para o estado S_HEADER.
-- No estado S_HEADER eh requisitado o chaveamento (h='1'), porque o flit na posicao
-- apontada pelo ponteiro first, quando a maquina encontra-se nesse estado, eh sempre o
-- header do pacote. A maquina permanece neste estado ate que receba a confirmacao do
-- chaveamento (ack_h='1') entao o sinal h recebe o valor zero e a maquina avanca para
-- S_SENDHEADER.
-- Em S_SENDHEADER eh indicado que existe um flit a ser transmitido (data_av='1'). A maquina de
-- estados permanece em S_SENDHEADER ate receber a confirmacao da transmissao (data_ack='1')
-- entao o ponteiro first aponta para o segundo flit do pacote e avanca para o estado S_PAYLOAD.
-- No estado S_PAYLOAD eh indicado que existe um flit a ser transmitido (data_av='1') quando
-- eh recebida a confirmacao da transmissao (data_ack='1') eh verificado qual o valor do sinal
-- counter_flit. Se counter_flit eh igual a um, a maquina avanca para o estado S_INIT. Caso
-- counter_flit seja igual a zero, o sinal counter_flit eh inicializado com o valor do flit, pois
-- este ao numero de flits do corpo do pacote. Caso counter_flit seja diferente de um e de zero
-- o mesmo eh decrementado e a maquina de estados permanece em S_PAYLOAD enviando o proximo flit
-- do pacote.
process(reset, clock)
variable indexFlitCtrl: integer :=0;
variable varControlCom: integer :=1; -- variavel de comando, para fazer as iteracoes
begin
if reset = '1' then
counter_flit <= (others=>'0');
counter_flit_up <= (others=>'0');
h <= '0';
data_av <= '0';
sender <= '0';
first <= (others=>'0');
eh_controle <= '0';
c_chipETable <= '0';
EA <= S_INIT;
elsif clock'event and clock = '1' then
case EA is
when S_INIT =>
c_chipETable <= '0'; -- desabilita escrita na tabela de roteamento
counter_flit <= (others=>'0');
counter_flit_up <= (others=>'0');
data_av <= '0';
eh_controle <= '0';
last_retransmission <= (others=>'0');
-- se existe dados no buffer a serem transmitidos (por causa dos ponteiros first e last diferentes) OU se devo criar um pacote de controle com a tabela de falhas
if first /= last or c_createmessage = '1' then
-- se o primeiro flit do pacote a ser transmitido possui o bit indicando que eh um pacote de controle E se nesse primeiro flit possui o endereco do roteador em que o buffer se encontra
-- OU se devo criar um pacote de controle com a tabela de falhas (este pacote eh criado se for pedido a leitura da tabela de falhas)
if((buf(CONV_INTEGER(first))(TAM_FLIT-1)='1') and (buf(CONV_INTEGER(first))((METADEFLIT - 1) downto 0)=address)) or c_createmessage = '1' then -- PACOTE DE CONTROLE
-- se preciso criar um pacote com a tabela de falhas. Comentario antigo: o pacote de controle pare este roteador
if c_createmessage = '1' then
-- se ultimo pacote de controle recebido foi de leitura da tabela de falhas
if codigoControl = c_RD_FAULT_TAB_STEP1 then
c_Buffer <= x"80" & address((METADEFLIT-1) downto 0); -- entao crio o primeiro flit do pacote que vai conter a tabela de falhas
h <= '1'; -- requisicao de chaveamento (chavear os dados de entrada para a porta de saida atraves da crossbar)
EA <= S_HEADER; -- maquina de estados avanca para o estado S_HEADER
eh_controle <= '1'; -- indica que o pacote lido/criado eh de controle
c_direcao <= "10000"; --direcao para a saida Local
end if;
-- nao irei criar pacote de controle com a tabela de falhas, irei apenas transmitir o pacote do buffer
else
-- incrementa ponteiro first (ponteiro usado para envio)
-- nao preciso tratar erro detectado aqui, pq em ED o flit eh igual a zero, logo nao sera pacote de controle
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
EA <= C_SIZE; -- maquina de estados avanca para o estado S_SIZE (estado onde eh lido o tamanho do pacote)
eh_controle <= '1'; -- indica que o pacote lido/criado eh de controle
c_direcao <= "10000"; -- direcao para o a saida Local
end if;
-- tenho dados para enviar e nao sao de controle (apenas pacote de dados)
else
h <= '1'; -- requisicao de chaveamento (chavear os dados de entrada para a porta de saida atraves da crossbar)
EA <= S_HEADER; -- maquina de estados avanca para o estado S_HEADER
end if;
-- entao nao tenho dados no buffer para enviar nem preciso criar um pacote de controle
else
h <= '0'; -- nao pede/solicita chaveamento pq nao preciso enviar nada
end if;
when S_HEADER =>
-- se terminou de achar uma porta de saida para o pacote conforme a tabela de roteamento
if (c_error_find = validRegion) then
c_direcao <= c_error_dir; -- direcao/porta de saida da tabela de roteamento
end if;
if (discard = '1') then
h <= '0';
EA <= S_INIT;
end if;
-- atendido/confirmado a requisicao de chaveamento OU se link destino tiver falhar
if ack_h = '1' or c_error = '1' then
EA <= S_SENDHEADER;
h <= '0'; -- nao preciso mais solicitar o chaveamento pq ele foi ja foi atendido :)
data_av <= '1'; -- data available (usado para indicar que exite flit a ser transmitido)
sender <= '1'; -- usado para indicar que esta transmitindo (por este sinal sabemos quando termina a transmissao e a porta destino desocupa)
end if;
when S_SENDHEADER =>
-- se recebeu confirmacao de dado recebido OU o link destino esta com falha
if data_ack = '1' or c_error = '1' then
-- incrementa pointeiro first (usado para transmitir flit) e sinaliza que tem dado disponivel
if c_createmessage = '0' then
-- se receptor nao pediu retransmissao, continua enviando
if (retransmission_in='0') then
EA <= S_PAYLOAD;
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
if last /= 0 then data_av <= '1';
else data_av <= '0';
end if;
else
first <= first + 1;
if first + 1 /= last then data_av <= '1';
else data_av <= '0';
end if;
end if;
-- solicitou reenvio do pacote, logo ponteiro nao sera incrementado e dado sera enviado novamente
else
last_retransmission <= (0=>'1', others=>'0'); -- 1
--assert last_retransmission /= 1 report "sender detectou que nao conseguiu transmitir flit correto. Pacote descartado. Flit "&integer'image(CONV_INTEGER(last_retransmission));
end if;
-- irei criar um pacote de controle com a tabela de falhas
else
-- se ultimo pacote de controle recebido foi pedido de leitura da tabela de falhas
if codigoControl = c_RD_FAULT_TAB_STEP1 then
counter_flit <= x"000A"; -- 10 flits de payload (code + origem + tabela)
c_Buffer <= x"000A"; -- segundo flit do pacote de controle criado (tamanho de pacote)
EA <= C_PAYLOAD;
indexFlitCtrl := 0;
varControlCom := 10;
end if;
end if;
end if;
when S_PAYLOAD =>
-- se tiver que retransmitir, nao incrementa ponteiro first
if (( data_ack = '1' or c_error = '1') and retransmission_in = '1') then
if (counter_flit = 0) then
last_retransmission <= (1=>'1', others=>'0'); -- 2
--assert last_retransmission /= 2 report "sender detectou que nao conseguiu transmitir flit correto. Pacote descartado. Flit "&integer'image(CONV_INTEGER(last_retransmission));
else
last_retransmission <= counter_flit_up;
--assert last_retransmission /= counter_flit_up report "sender detectou que nao conseguiu transmitir flit correto. Pacote descartado. Flit "&integer'image(CONV_INTEGER(last_retransmission));
end if;
-- se nao eh o ultimo flit do pacote E se foi confirmado que foi recebido com sucesso o dado transmitido OU o link destino esta com falha. Comentario antigo: confirmacao do envio de um dado que nao eh o tail
elsif counter_flit /= x"1" and ( data_ack = '1' or c_error = '1') then
-- se counter_flit eh zero indica que terei que receber o size do payload
if counter_flit = x"0" then
counter_flit <= buf(CONV_INTEGER(first));
counter_flit_up <= (1=>'1', others=>'0'); -- 2
else
counter_flit <= counter_flit - 1;
counter_flit_up <= counter_flit_up + 1;
end if;
-- incrementa pointeiro first (usado para transmitir flit) e sinaliza que tem dado disponivel
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
if last /= 0 then
data_av <= '1'; -- (data available)
else
data_av <= '0';
end if;
else
first <= first + 1;
if first + 1 /= last then
data_av <= '1';
else
data_av <= '0';
end if;
end if;
-- se eh o ultimo flit do pacote E se foi confirmado que foi recebido com sucesso o dado transmitido OU o link destino esta com falha. Comentario antigo: confirmacao do envio do tail
elsif counter_flit = x"1" and (data_ack = '1' or c_error = '1') then
-- Incrementa pointeiro de envio. Comentario antigo: retira um dado do buffer
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
data_av <= '0'; -- como o ultimo flit sera enviado, nao tem mais dados disponiveis
sender <= '0'; -- como o ultimo flit sera enviado, nao preciso sinalizar que estou enviando dados
EA <= S_END; -- -- como o ultimo flit sera enviado, posso ir para o estado S_END
-- se tem dado a ser enviado, sinaliza
elsif first /= last then
data_av <= '1'; -- (data available)
end if;
when C_SIZE =>
-- detectou dado na fila (tem dados a serem enviados no buffer) e nao pediu retransmissao
if (first /= last and retransmission_o='0') then
counter_flit <= buf(CONV_INTEGER(first)); -- leitura do segundo flit (tamanho do pacote)
-- incrementa o pointeiro first (pointeiro usado para envio)
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
EA <= C_PAYLOAD;
indexFlitCtrl := 0; -- coloca o indice do flit de controle igual 0 (esse indice eh usado para percorrer os flits de payload de controle). O indice igual a 0 representa o terceito flit do pacote e nele havera o Code (codigo que indica o tipo do pacote de controle)
varControlCom := 1; -- numero de flits no payload usados para processar o pacote de controle
end if;
when C_PAYLOAD =>
c_chipETable <= '0'; -- desabilita escrita na tabela de roteamento
if (first /= last) and indexFlitCtrl /= varControlCom and c_createmessage = '0' and retransmission_o='0' then
if first = TAM_BUFFER - 1 then
first <= (others=>'0');
else
first <= first + 1;
end if;
end if;
-- indice igual a zero, ou seja, primeiro flit do payload do pacote (onde possui o codigo do pacote de controle)
if (indexFlitCtrl = 0 and retransmission_o='0') then
codigoControl <= buf(CONV_INTEGER(first)); -- leitura do tipo do pacote de controle (leitura do Code)
indexFlitCtrl := indexFlitCtrl + 1; -- incrementa o indice do payload que sera lido
counter_flit <= counter_flit - 1; -- decrementa o numero de flits que faltam a ser lidos/processados do pacote
-- define qual o tamanho da variavel de comando (tamanho do payload).
-- Pode ser entendido como o numero de flits no payload usados para processar o pacote de controle
if c_createmessage = '0' then
if(CONV_INTEGER(buf(CONV_INTEGER(first))) = c_WR_ROUT_TAB) then
varControlCom := 5;
elsif(CONV_INTEGER(buf(CONV_INTEGER(first))) = c_WR_FAULT_TAB) then
varControlCom := 9; -- code + tabela
elsif(CONV_INTEGER(buf(CONV_INTEGER(first))) = c_RD_FAULT_TAB_STEP1) then
varControlCom := 1;
elsif(CONV_INTEGER(buf(CONV_INTEGER(first))) = c_TEST_LINKS ) then
varControlCom := 1;
end if;
-- se c_createmessage='1', logo tenho que criar um pacote com a tabela de falhas para o OsPhoenix
else
-- se ultimo pacote de controle recebido foi pedido de leitura da tabela de falhas
if codigoControl = c_RD_FAULT_TAB_STEP1 then
varControlCom := 10; -- code + origem + tabela
codigoControl <= CONV_STD_LOGIC_VECTOR(c_RD_FAULT_TAB_STEP2, TAM_FLIT); -- atualiza codigo com c_RD_FAULT_TAB_STEP2
c_Buffer <= x"0004"; -- terceiro flit do pacote de controle criado que contem o tipo do pacote (code/codigo)
end if;
end if;
-- escrita de linha na tabela de roteamento. Comentario antigo: codigo para atualizar tabela de roteamento.
-- a linha do pacote de roteamento eh divida em 3 flits: o primeiro flit tem o XY do ponto inferior, o segundo flit tem o XY do ponto superior,
-- o terceiro flit contem os 5 bits que indica a direcao/porta de saida dos pacotes conforme a regiao
elsif (codigoControl = c_WR_ROUT_TAB and retransmission_o='0') then
-- terminou de processar todos os flits do pacote de controle
if indexFlitCtrl = 5 then
counter_flit <= counter_flit - 1;
if counter_flit = x"1" then
EA <= S_END;
end if;
c_chipETable <= '1'; -- habilita escrita na tabela de roteamento
indexFlitCtrl := 1;
else
buffCtrl(indexFlitCtrl-1) <= buf(CONV_INTEGER(first)); -- vai armazenando os dados lido do pacote de controle (o pacote tera uma linha da tabela de roteamento)
if (first /= last) then
if indexFlitCtrl /= 4 then
counter_flit <= counter_flit - 1;
end if;
indexFlitCtrl := indexFlitCtrl + 1;
end if;
c_chipETable <= '0';
end if;
-- escrita na tabela de falhas (irei ler a tabela recebido no pacote de controle). Comentario antigo: codigo para atualizar tabela de portas com falhas
elsif (codigoControl = c_WR_FAULT_TAB and retransmission_o='0') then
case (indexFlitCtrl) is
when 1 => buffCtrlFalha(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(EAST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 2 => buffCtrlFalha(EAST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(EAST)((COUNTERS_SIZE-1) downto 0) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when 3 => buffCtrlFalha(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(WEST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 4 => buffCtrlFalha(WEST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(WEST)((COUNTERS_SIZE-1) downto 0) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when 5 => buffCtrlFalha(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(NORTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 6 => buffCtrlFalha(NORTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(NORTH)((COUNTERS_SIZE-1) downto 0) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when 7 => buffCtrlFalha(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+1) downto METADEFLIT); -- leitura dos 2 bits que indicam falha que sera armazenado/atualizado na tabela de falhas
buffCtrlFalha(SOUTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador N
when 8 => buffCtrlFalha(SOUTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE) <= buf(CONV_INTEGER(first))((METADEFLIT+COUNTERS_SIZE-1) downto METADEFLIT); -- leitura do contador M
buffCtrlFalha(SOUTH)((COUNTERS_SIZE-1) downto 0) <= buf(CONV_INTEGER(first))(COUNTERS_SIZE-1 downto 0); -- leitura do contador P
when others => null;
end case;
if (first /= last) then
indexFlitCtrl := indexFlitCtrl + 1;
counter_flit <= counter_flit - 1;
end if;
-- ultimo flit?
if counter_flit = 0 then
ceTF_out <= '1'; -- habilita ce para escrever/atualizar a tabela de falhas
EA <= S_END;
end if;
-- pedido de leitura da tabela de falhas
elsif codigoControl = c_RD_FAULT_TAB_STEP1 then
--codigo requerindo a tabela de falhas
counter_flit <= counter_flit - 1;
EA <= S_INIT;
-- sinal usado para criar um pacote de controle com a tabela de falhas. Comentario antigo: envia msg para tabela
c_createmessage <= '1';
-- resposta da leitura da tabela de falhas
elsif codigoControl = c_RD_FAULT_TAB_STEP2 then
-- code complement. Comentario antigo: codigo para enviar a msg de falhas para o PE
if (data_ack = '1') then
case (indexFlitCtrl) is
when 1 => c_Buffer <= x"00" & address; -- neste quarto flit havera o endereco do roteador
when 2 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-2) & c_TabelaFalhas(EAST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(EAST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 3 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(EAST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(EAST)((COUNTERS_SIZE-1) downto 0);
when 4 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-2) & c_TabelaFalhas(WEST)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(WEST)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 5 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(WEST)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(WEST)((COUNTERS_SIZE-1) downto 0);
when 6 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-2) & c_TabelaFalhas(NORTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(NORTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 7 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(NORTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(NORTH)((COUNTERS_SIZE-1) downto 0);
when 8 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-2) & c_TabelaFalhas(SOUTH)((3*COUNTERS_SIZE+1) downto 3*COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(SOUTH)((3*COUNTERS_SIZE-1) downto 2*COUNTERS_SIZE);
when 9 => c_Buffer((TAM_FLIT-1) downto METADEFLIT) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(SOUTH)((2*COUNTERS_SIZE-1) downto COUNTERS_SIZE);
c_Buffer((METADEFLIT-1) downto 0) <= CONV_STD_LOGIC_VECTOR(0,METADEFLIT-COUNTERS_SIZE) & c_TabelaFalhas(SOUTH)((COUNTERS_SIZE-1) downto 0);
when others => null;
end case;
counter_flit <= counter_flit - 1; -- decrementa o numero de payloads que faltam processar
indexFlitCtrl := indexFlitCtrl + 1; -- incrementa o indice do payload
end if;
-- se enviou todos os flits
if counter_flit = x"0" then
c_createmessage <= '0'; -- nao preciso mais sinalizar para criar um pacote, pq ele ja foi criado e enviado :)
data_av <= '0'; -- ja enviei o pacote, entao nao tem mais dados disponiveis
sender <= '0'; -- ja enviei o pacote, nao preciso sinalizar que estou enviando
EA <= S_END;
-- se tem dado a ser enviado, sinalizado que existe dados disponiveis
else
data_av <= '1'; -- (data available)
end if;
-- se o pacote gerado pelo OsPhoenix eh um pacote de controle do tipo TEST_LINKS.
elsif codigoControl = c_TEST_LINKS then
-- pede para verificar os links aos vizinhos caso nenhum vizinho tenha pedido o teste de link. Comentario antigo: codigo para testar falhas e gravar na tabela de falhas do switchControl
-- SE nenhum vizinho pediu o teste de link ENTAO...
if c_strLinkTstOthers = '0' then
c_strLinkTstLocal <= '1'; -- pede para iniciar o teste de links
end if;
-- se terminou o teste de links
if c_stpLinkTst = '1' then
c_strLinkTstLocal <= '0'; -- nao preciso mais pedir para iniciar o teste de link pq ele ja acabou :)
EA <= S_END;
end if;
end if;
when S_END =>
c_chipETable <= '0';
ceTF_out <= '0';
eh_controle <= '0';
data_av <= '0';
c_direcao <= (others=>'0');
indexFlitCtrl := 0;
EA <= S_END2;
when S_END2 => -- estado necessario para permitir a liberacao da porta antes da solicitacao de novo envio
data_av <= '0';
EA <= S_INIT;
end case;
end if;
end process;
------------New Hardware------------
c_ctrl <= eh_controle;
c_buffCtrlOut <= buffCtrl;
c_codigoCtrl <= codigoControl;
c_buffCtrlFalha <= buffCtrlFalha;
c_ceTF_out <= ceTF_out;
c_strLinkTst <= c_strLinkTstLocal;
end Phoenix_buffer;
|
lgpl-3.0
|
cacf5fd42aa344ccaead56316228d952
| 0.637183 | 3.643291 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_ila_0_0/synth/DemoInterconnect_ila_0_0.vhd
| 1 | 315,547 |
-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_ila_0_0 IS
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DemoInterconnect_ila_0_0;
ARCHITECTURE DemoInterconnect_ila_0_0_arch OF DemoInterconnect_ila_0_0 IS
COMPONENT ila_v6_2_4_ila IS
GENERIC (
C_XLNX_HW_PROBE_INFO : STRING;
C_XDEVICEFAMILY : STRING;
C_CORE_TYPE : INTEGER;
C_CORE_INFO1 : INTEGER;
C_CORE_INFO2 : INTEGER;
C_CAPTURE_TYPE : INTEGER;
C_MU_TYPE : INTEGER;
C_TC_TYPE : INTEGER;
C_NUM_OF_PROBES : INTEGER;
C_DATA_DEPTH : INTEGER;
C_MAJOR_VERSION : INTEGER;
C_MINOR_VERSION : INTEGER;
C_BUILD_REVISION : INTEGER;
C_CORE_MAJOR_VER : INTEGER;
C_CORE_MINOR_VER : INTEGER;
C_XSDB_SLAVE_TYPE : INTEGER;
C_NEXT_SLAVE : INTEGER;
C_CSE_DRV_VER : INTEGER;
C_USE_TEST_REG : INTEGER;
C_PIPE_IFACE : INTEGER;
C_RAM_STYLE : STRING;
C_TRIGOUT_EN : INTEGER;
C_TRIGIN_EN : INTEGER;
C_ADV_TRIGGER : INTEGER;
C_EN_DDR_ILA : INTEGER;
C_EN_STRG_QUAL : INTEGER;
C_INPUT_PIPE_STAGES : INTEGER;
C_EN_TIME_TAG : INTEGER;
C_TIME_TAG_WIDTH : INTEGER;
C_ILA_CLK_FREQ : INTEGER;
C_PROBE0_WIDTH : INTEGER;
C_PROBE1_WIDTH : INTEGER;
C_PROBE2_WIDTH : INTEGER;
C_PROBE3_WIDTH : INTEGER;
C_PROBE4_WIDTH : INTEGER;
C_PROBE5_WIDTH : INTEGER;
C_PROBE6_WIDTH : INTEGER;
C_PROBE7_WIDTH : INTEGER;
C_PROBE8_WIDTH : INTEGER;
C_PROBE9_WIDTH : INTEGER;
C_PROBE10_WIDTH : INTEGER;
C_PROBE11_WIDTH : INTEGER;
C_PROBE12_WIDTH : INTEGER;
C_PROBE13_WIDTH : INTEGER;
C_PROBE14_WIDTH : INTEGER;
C_PROBE15_WIDTH : INTEGER;
C_PROBE16_WIDTH : INTEGER;
C_PROBE17_WIDTH : INTEGER;
C_PROBE18_WIDTH : INTEGER;
C_PROBE19_WIDTH : INTEGER;
C_PROBE20_WIDTH : INTEGER;
C_PROBE21_WIDTH : INTEGER;
C_PROBE22_WIDTH : INTEGER;
C_PROBE23_WIDTH : INTEGER;
C_PROBE24_WIDTH : INTEGER;
C_PROBE25_WIDTH : INTEGER;
C_PROBE26_WIDTH : INTEGER;
C_PROBE27_WIDTH : INTEGER;
C_PROBE28_WIDTH : INTEGER;
C_PROBE29_WIDTH : INTEGER;
C_PROBE30_WIDTH : INTEGER;
C_PROBE31_WIDTH : INTEGER;
C_PROBE32_WIDTH : INTEGER;
C_PROBE33_WIDTH : INTEGER;
C_PROBE34_WIDTH : INTEGER;
C_PROBE35_WIDTH : INTEGER;
C_PROBE36_WIDTH : INTEGER;
C_PROBE37_WIDTH : INTEGER;
C_PROBE38_WIDTH : INTEGER;
C_PROBE39_WIDTH : INTEGER;
C_PROBE40_WIDTH : INTEGER;
C_PROBE41_WIDTH : INTEGER;
C_PROBE42_WIDTH : INTEGER;
C_PROBE43_WIDTH : INTEGER;
C_PROBE44_WIDTH : INTEGER;
C_PROBE45_WIDTH : INTEGER;
C_PROBE46_WIDTH : INTEGER;
C_PROBE47_WIDTH : INTEGER;
C_PROBE48_WIDTH : INTEGER;
C_PROBE49_WIDTH : INTEGER;
C_PROBE50_WIDTH : INTEGER;
C_PROBE51_WIDTH : INTEGER;
C_PROBE52_WIDTH : INTEGER;
C_PROBE53_WIDTH : INTEGER;
C_PROBE54_WIDTH : INTEGER;
C_PROBE55_WIDTH : INTEGER;
C_PROBE56_WIDTH : INTEGER;
C_PROBE57_WIDTH : INTEGER;
C_PROBE58_WIDTH : INTEGER;
C_PROBE59_WIDTH : INTEGER;
C_PROBE60_WIDTH : INTEGER;
C_PROBE61_WIDTH : INTEGER;
C_PROBE62_WIDTH : INTEGER;
C_PROBE63_WIDTH : INTEGER;
C_PROBE64_WIDTH : INTEGER;
C_PROBE65_WIDTH : INTEGER;
C_PROBE66_WIDTH : INTEGER;
C_PROBE67_WIDTH : INTEGER;
C_PROBE68_WIDTH : INTEGER;
C_PROBE69_WIDTH : INTEGER;
C_PROBE70_WIDTH : INTEGER;
C_PROBE71_WIDTH : INTEGER;
C_PROBE72_WIDTH : INTEGER;
C_PROBE73_WIDTH : INTEGER;
C_PROBE74_WIDTH : INTEGER;
C_PROBE75_WIDTH : INTEGER;
C_PROBE76_WIDTH : INTEGER;
C_PROBE77_WIDTH : INTEGER;
C_PROBE78_WIDTH : INTEGER;
C_PROBE79_WIDTH : INTEGER;
C_PROBE80_WIDTH : INTEGER;
C_PROBE81_WIDTH : INTEGER;
C_PROBE82_WIDTH : INTEGER;
C_PROBE83_WIDTH : INTEGER;
C_PROBE84_WIDTH : INTEGER;
C_PROBE85_WIDTH : INTEGER;
C_PROBE86_WIDTH : INTEGER;
C_PROBE87_WIDTH : INTEGER;
C_PROBE88_WIDTH : INTEGER;
C_PROBE89_WIDTH : INTEGER;
C_PROBE90_WIDTH : INTEGER;
C_PROBE91_WIDTH : INTEGER;
C_PROBE92_WIDTH : INTEGER;
C_PROBE93_WIDTH : INTEGER;
C_PROBE94_WIDTH : INTEGER;
C_PROBE95_WIDTH : INTEGER;
C_PROBE96_WIDTH : INTEGER;
C_PROBE97_WIDTH : INTEGER;
C_PROBE98_WIDTH : INTEGER;
C_PROBE99_WIDTH : INTEGER;
C_PROBE100_WIDTH : INTEGER;
C_PROBE101_WIDTH : INTEGER;
C_PROBE102_WIDTH : INTEGER;
C_PROBE103_WIDTH : INTEGER;
C_PROBE104_WIDTH : INTEGER;
C_PROBE105_WIDTH : INTEGER;
C_PROBE106_WIDTH : INTEGER;
C_PROBE107_WIDTH : INTEGER;
C_PROBE108_WIDTH : INTEGER;
C_PROBE109_WIDTH : INTEGER;
C_PROBE110_WIDTH : INTEGER;
C_PROBE111_WIDTH : INTEGER;
C_PROBE112_WIDTH : INTEGER;
C_PROBE113_WIDTH : INTEGER;
C_PROBE114_WIDTH : INTEGER;
C_PROBE115_WIDTH : INTEGER;
C_PROBE116_WIDTH : INTEGER;
C_PROBE117_WIDTH : INTEGER;
C_PROBE118_WIDTH : INTEGER;
C_PROBE119_WIDTH : INTEGER;
C_PROBE120_WIDTH : INTEGER;
C_PROBE121_WIDTH : INTEGER;
C_PROBE122_WIDTH : INTEGER;
C_PROBE123_WIDTH : INTEGER;
C_PROBE124_WIDTH : INTEGER;
C_PROBE125_WIDTH : INTEGER;
C_PROBE126_WIDTH : INTEGER;
C_PROBE127_WIDTH : INTEGER;
C_PROBE128_WIDTH : INTEGER;
C_PROBE129_WIDTH : INTEGER;
C_PROBE130_WIDTH : INTEGER;
C_PROBE131_WIDTH : INTEGER;
C_PROBE132_WIDTH : INTEGER;
C_PROBE133_WIDTH : INTEGER;
C_PROBE134_WIDTH : INTEGER;
C_PROBE135_WIDTH : INTEGER;
C_PROBE136_WIDTH : INTEGER;
C_PROBE137_WIDTH : INTEGER;
C_PROBE138_WIDTH : INTEGER;
C_PROBE139_WIDTH : INTEGER;
C_PROBE140_WIDTH : INTEGER;
C_PROBE141_WIDTH : INTEGER;
C_PROBE142_WIDTH : INTEGER;
C_PROBE143_WIDTH : INTEGER;
C_PROBE144_WIDTH : INTEGER;
C_PROBE145_WIDTH : INTEGER;
C_PROBE146_WIDTH : INTEGER;
C_PROBE147_WIDTH : INTEGER;
C_PROBE148_WIDTH : INTEGER;
C_PROBE149_WIDTH : INTEGER;
C_PROBE150_WIDTH : INTEGER;
C_PROBE151_WIDTH : INTEGER;
C_PROBE152_WIDTH : INTEGER;
C_PROBE153_WIDTH : INTEGER;
C_PROBE154_WIDTH : INTEGER;
C_PROBE155_WIDTH : INTEGER;
C_PROBE156_WIDTH : INTEGER;
C_PROBE157_WIDTH : INTEGER;
C_PROBE158_WIDTH : INTEGER;
C_PROBE159_WIDTH : INTEGER;
C_PROBE160_WIDTH : INTEGER;
C_PROBE161_WIDTH : INTEGER;
C_PROBE162_WIDTH : INTEGER;
C_PROBE163_WIDTH : INTEGER;
C_PROBE164_WIDTH : INTEGER;
C_PROBE165_WIDTH : INTEGER;
C_PROBE166_WIDTH : INTEGER;
C_PROBE167_WIDTH : INTEGER;
C_PROBE168_WIDTH : INTEGER;
C_PROBE169_WIDTH : INTEGER;
C_PROBE170_WIDTH : INTEGER;
C_PROBE171_WIDTH : INTEGER;
C_PROBE172_WIDTH : INTEGER;
C_PROBE173_WIDTH : INTEGER;
C_PROBE174_WIDTH : INTEGER;
C_PROBE175_WIDTH : INTEGER;
C_PROBE176_WIDTH : INTEGER;
C_PROBE177_WIDTH : INTEGER;
C_PROBE178_WIDTH : INTEGER;
C_PROBE179_WIDTH : INTEGER;
C_PROBE180_WIDTH : INTEGER;
C_PROBE181_WIDTH : INTEGER;
C_PROBE182_WIDTH : INTEGER;
C_PROBE183_WIDTH : INTEGER;
C_PROBE184_WIDTH : INTEGER;
C_PROBE185_WIDTH : INTEGER;
C_PROBE186_WIDTH : INTEGER;
C_PROBE187_WIDTH : INTEGER;
C_PROBE188_WIDTH : INTEGER;
C_PROBE189_WIDTH : INTEGER;
C_PROBE190_WIDTH : INTEGER;
C_PROBE191_WIDTH : INTEGER;
C_PROBE192_WIDTH : INTEGER;
C_PROBE193_WIDTH : INTEGER;
C_PROBE194_WIDTH : INTEGER;
C_PROBE195_WIDTH : INTEGER;
C_PROBE196_WIDTH : INTEGER;
C_PROBE197_WIDTH : INTEGER;
C_PROBE198_WIDTH : INTEGER;
C_PROBE199_WIDTH : INTEGER;
C_PROBE200_WIDTH : INTEGER;
C_PROBE201_WIDTH : INTEGER;
C_PROBE202_WIDTH : INTEGER;
C_PROBE203_WIDTH : INTEGER;
C_PROBE204_WIDTH : INTEGER;
C_PROBE205_WIDTH : INTEGER;
C_PROBE206_WIDTH : INTEGER;
C_PROBE207_WIDTH : INTEGER;
C_PROBE208_WIDTH : INTEGER;
C_PROBE209_WIDTH : INTEGER;
C_PROBE210_WIDTH : INTEGER;
C_PROBE211_WIDTH : INTEGER;
C_PROBE212_WIDTH : INTEGER;
C_PROBE213_WIDTH : INTEGER;
C_PROBE214_WIDTH : INTEGER;
C_PROBE215_WIDTH : INTEGER;
C_PROBE216_WIDTH : INTEGER;
C_PROBE217_WIDTH : INTEGER;
C_PROBE218_WIDTH : INTEGER;
C_PROBE219_WIDTH : INTEGER;
C_PROBE220_WIDTH : INTEGER;
C_PROBE221_WIDTH : INTEGER;
C_PROBE222_WIDTH : INTEGER;
C_PROBE223_WIDTH : INTEGER;
C_PROBE224_WIDTH : INTEGER;
C_PROBE225_WIDTH : INTEGER;
C_PROBE226_WIDTH : INTEGER;
C_PROBE227_WIDTH : INTEGER;
C_PROBE228_WIDTH : INTEGER;
C_PROBE229_WIDTH : INTEGER;
C_PROBE230_WIDTH : INTEGER;
C_PROBE231_WIDTH : INTEGER;
C_PROBE232_WIDTH : INTEGER;
C_PROBE233_WIDTH : INTEGER;
C_PROBE234_WIDTH : INTEGER;
C_PROBE235_WIDTH : INTEGER;
C_PROBE236_WIDTH : INTEGER;
C_PROBE237_WIDTH : INTEGER;
C_PROBE238_WIDTH : INTEGER;
C_PROBE239_WIDTH : INTEGER;
C_PROBE240_WIDTH : INTEGER;
C_PROBE241_WIDTH : INTEGER;
C_PROBE242_WIDTH : INTEGER;
C_PROBE243_WIDTH : INTEGER;
C_PROBE244_WIDTH : INTEGER;
C_PROBE245_WIDTH : INTEGER;
C_PROBE246_WIDTH : INTEGER;
C_PROBE247_WIDTH : INTEGER;
C_PROBE248_WIDTH : INTEGER;
C_PROBE249_WIDTH : INTEGER;
C_PROBE250_WIDTH : INTEGER;
C_PROBE251_WIDTH : INTEGER;
C_PROBE252_WIDTH : INTEGER;
C_PROBE253_WIDTH : INTEGER;
C_PROBE254_WIDTH : INTEGER;
C_PROBE255_WIDTH : INTEGER;
C_PROBE256_WIDTH : INTEGER;
C_PROBE257_WIDTH : INTEGER;
C_PROBE258_WIDTH : INTEGER;
C_PROBE259_WIDTH : INTEGER;
C_PROBE260_WIDTH : INTEGER;
C_PROBE261_WIDTH : INTEGER;
C_PROBE262_WIDTH : INTEGER;
C_PROBE263_WIDTH : INTEGER;
C_PROBE264_WIDTH : INTEGER;
C_PROBE265_WIDTH : INTEGER;
C_PROBE266_WIDTH : INTEGER;
C_PROBE267_WIDTH : INTEGER;
C_PROBE268_WIDTH : INTEGER;
C_PROBE269_WIDTH : INTEGER;
C_PROBE270_WIDTH : INTEGER;
C_PROBE271_WIDTH : INTEGER;
C_PROBE272_WIDTH : INTEGER;
C_PROBE273_WIDTH : INTEGER;
C_PROBE274_WIDTH : INTEGER;
C_PROBE275_WIDTH : INTEGER;
C_PROBE276_WIDTH : INTEGER;
C_PROBE277_WIDTH : INTEGER;
C_PROBE278_WIDTH : INTEGER;
C_PROBE279_WIDTH : INTEGER;
C_PROBE280_WIDTH : INTEGER;
C_PROBE281_WIDTH : INTEGER;
C_PROBE282_WIDTH : INTEGER;
C_PROBE283_WIDTH : INTEGER;
C_PROBE284_WIDTH : INTEGER;
C_PROBE285_WIDTH : INTEGER;
C_PROBE286_WIDTH : INTEGER;
C_PROBE287_WIDTH : INTEGER;
C_PROBE288_WIDTH : INTEGER;
C_PROBE289_WIDTH : INTEGER;
C_PROBE290_WIDTH : INTEGER;
C_PROBE291_WIDTH : INTEGER;
C_PROBE292_WIDTH : INTEGER;
C_PROBE293_WIDTH : INTEGER;
C_PROBE294_WIDTH : INTEGER;
C_PROBE295_WIDTH : INTEGER;
C_PROBE296_WIDTH : INTEGER;
C_PROBE297_WIDTH : INTEGER;
C_PROBE298_WIDTH : INTEGER;
C_PROBE299_WIDTH : INTEGER;
C_PROBE300_WIDTH : INTEGER;
C_PROBE301_WIDTH : INTEGER;
C_PROBE302_WIDTH : INTEGER;
C_PROBE303_WIDTH : INTEGER;
C_PROBE304_WIDTH : INTEGER;
C_PROBE305_WIDTH : INTEGER;
C_PROBE306_WIDTH : INTEGER;
C_PROBE307_WIDTH : INTEGER;
C_PROBE308_WIDTH : INTEGER;
C_PROBE309_WIDTH : INTEGER;
C_PROBE310_WIDTH : INTEGER;
C_PROBE311_WIDTH : INTEGER;
C_PROBE312_WIDTH : INTEGER;
C_PROBE313_WIDTH : INTEGER;
C_PROBE314_WIDTH : INTEGER;
C_PROBE315_WIDTH : INTEGER;
C_PROBE316_WIDTH : INTEGER;
C_PROBE317_WIDTH : INTEGER;
C_PROBE318_WIDTH : INTEGER;
C_PROBE319_WIDTH : INTEGER;
C_PROBE320_WIDTH : INTEGER;
C_PROBE321_WIDTH : INTEGER;
C_PROBE322_WIDTH : INTEGER;
C_PROBE323_WIDTH : INTEGER;
C_PROBE324_WIDTH : INTEGER;
C_PROBE325_WIDTH : INTEGER;
C_PROBE326_WIDTH : INTEGER;
C_PROBE327_WIDTH : INTEGER;
C_PROBE328_WIDTH : INTEGER;
C_PROBE329_WIDTH : INTEGER;
C_PROBE330_WIDTH : INTEGER;
C_PROBE331_WIDTH : INTEGER;
C_PROBE332_WIDTH : INTEGER;
C_PROBE333_WIDTH : INTEGER;
C_PROBE334_WIDTH : INTEGER;
C_PROBE335_WIDTH : INTEGER;
C_PROBE336_WIDTH : INTEGER;
C_PROBE337_WIDTH : INTEGER;
C_PROBE338_WIDTH : INTEGER;
C_PROBE339_WIDTH : INTEGER;
C_PROBE340_WIDTH : INTEGER;
C_PROBE341_WIDTH : INTEGER;
C_PROBE342_WIDTH : INTEGER;
C_PROBE343_WIDTH : INTEGER;
C_PROBE344_WIDTH : INTEGER;
C_PROBE345_WIDTH : INTEGER;
C_PROBE346_WIDTH : INTEGER;
C_PROBE347_WIDTH : INTEGER;
C_PROBE348_WIDTH : INTEGER;
C_PROBE349_WIDTH : INTEGER;
C_PROBE350_WIDTH : INTEGER;
C_PROBE351_WIDTH : INTEGER;
C_PROBE352_WIDTH : INTEGER;
C_PROBE353_WIDTH : INTEGER;
C_PROBE354_WIDTH : INTEGER;
C_PROBE355_WIDTH : INTEGER;
C_PROBE356_WIDTH : INTEGER;
C_PROBE357_WIDTH : INTEGER;
C_PROBE358_WIDTH : INTEGER;
C_PROBE359_WIDTH : INTEGER;
C_PROBE360_WIDTH : INTEGER;
C_PROBE361_WIDTH : INTEGER;
C_PROBE362_WIDTH : INTEGER;
C_PROBE363_WIDTH : INTEGER;
C_PROBE364_WIDTH : INTEGER;
C_PROBE365_WIDTH : INTEGER;
C_PROBE366_WIDTH : INTEGER;
C_PROBE367_WIDTH : INTEGER;
C_PROBE368_WIDTH : INTEGER;
C_PROBE369_WIDTH : INTEGER;
C_PROBE370_WIDTH : INTEGER;
C_PROBE371_WIDTH : INTEGER;
C_PROBE372_WIDTH : INTEGER;
C_PROBE373_WIDTH : INTEGER;
C_PROBE374_WIDTH : INTEGER;
C_PROBE375_WIDTH : INTEGER;
C_PROBE376_WIDTH : INTEGER;
C_PROBE377_WIDTH : INTEGER;
C_PROBE378_WIDTH : INTEGER;
C_PROBE379_WIDTH : INTEGER;
C_PROBE380_WIDTH : INTEGER;
C_PROBE381_WIDTH : INTEGER;
C_PROBE382_WIDTH : INTEGER;
C_PROBE383_WIDTH : INTEGER;
C_PROBE384_WIDTH : INTEGER;
C_PROBE385_WIDTH : INTEGER;
C_PROBE386_WIDTH : INTEGER;
C_PROBE387_WIDTH : INTEGER;
C_PROBE388_WIDTH : INTEGER;
C_PROBE389_WIDTH : INTEGER;
C_PROBE390_WIDTH : INTEGER;
C_PROBE391_WIDTH : INTEGER;
C_PROBE392_WIDTH : INTEGER;
C_PROBE393_WIDTH : INTEGER;
C_PROBE394_WIDTH : INTEGER;
C_PROBE395_WIDTH : INTEGER;
C_PROBE396_WIDTH : INTEGER;
C_PROBE397_WIDTH : INTEGER;
C_PROBE398_WIDTH : INTEGER;
C_PROBE399_WIDTH : INTEGER;
C_PROBE400_WIDTH : INTEGER;
C_PROBE401_WIDTH : INTEGER;
C_PROBE402_WIDTH : INTEGER;
C_PROBE403_WIDTH : INTEGER;
C_PROBE404_WIDTH : INTEGER;
C_PROBE405_WIDTH : INTEGER;
C_PROBE406_WIDTH : INTEGER;
C_PROBE407_WIDTH : INTEGER;
C_PROBE408_WIDTH : INTEGER;
C_PROBE409_WIDTH : INTEGER;
C_PROBE410_WIDTH : INTEGER;
C_PROBE411_WIDTH : INTEGER;
C_PROBE412_WIDTH : INTEGER;
C_PROBE413_WIDTH : INTEGER;
C_PROBE414_WIDTH : INTEGER;
C_PROBE415_WIDTH : INTEGER;
C_PROBE416_WIDTH : INTEGER;
C_PROBE417_WIDTH : INTEGER;
C_PROBE418_WIDTH : INTEGER;
C_PROBE419_WIDTH : INTEGER;
C_PROBE420_WIDTH : INTEGER;
C_PROBE421_WIDTH : INTEGER;
C_PROBE422_WIDTH : INTEGER;
C_PROBE423_WIDTH : INTEGER;
C_PROBE424_WIDTH : INTEGER;
C_PROBE425_WIDTH : INTEGER;
C_PROBE426_WIDTH : INTEGER;
C_PROBE427_WIDTH : INTEGER;
C_PROBE428_WIDTH : INTEGER;
C_PROBE429_WIDTH : INTEGER;
C_PROBE430_WIDTH : INTEGER;
C_PROBE431_WIDTH : INTEGER;
C_PROBE432_WIDTH : INTEGER;
C_PROBE433_WIDTH : INTEGER;
C_PROBE434_WIDTH : INTEGER;
C_PROBE435_WIDTH : INTEGER;
C_PROBE436_WIDTH : INTEGER;
C_PROBE437_WIDTH : INTEGER;
C_PROBE438_WIDTH : INTEGER;
C_PROBE439_WIDTH : INTEGER;
C_PROBE440_WIDTH : INTEGER;
C_PROBE441_WIDTH : INTEGER;
C_PROBE442_WIDTH : INTEGER;
C_PROBE443_WIDTH : INTEGER;
C_PROBE444_WIDTH : INTEGER;
C_PROBE445_WIDTH : INTEGER;
C_PROBE446_WIDTH : INTEGER;
C_PROBE447_WIDTH : INTEGER;
C_PROBE448_WIDTH : INTEGER;
C_PROBE449_WIDTH : INTEGER;
C_PROBE450_WIDTH : INTEGER;
C_PROBE451_WIDTH : INTEGER;
C_PROBE452_WIDTH : INTEGER;
C_PROBE453_WIDTH : INTEGER;
C_PROBE454_WIDTH : INTEGER;
C_PROBE455_WIDTH : INTEGER;
C_PROBE456_WIDTH : INTEGER;
C_PROBE457_WIDTH : INTEGER;
C_PROBE458_WIDTH : INTEGER;
C_PROBE459_WIDTH : INTEGER;
C_PROBE460_WIDTH : INTEGER;
C_PROBE461_WIDTH : INTEGER;
C_PROBE462_WIDTH : INTEGER;
C_PROBE463_WIDTH : INTEGER;
C_PROBE464_WIDTH : INTEGER;
C_PROBE465_WIDTH : INTEGER;
C_PROBE466_WIDTH : INTEGER;
C_PROBE467_WIDTH : INTEGER;
C_PROBE468_WIDTH : INTEGER;
C_PROBE469_WIDTH : INTEGER;
C_PROBE470_WIDTH : INTEGER;
C_PROBE471_WIDTH : INTEGER;
C_PROBE472_WIDTH : INTEGER;
C_PROBE473_WIDTH : INTEGER;
C_PROBE474_WIDTH : INTEGER;
C_PROBE475_WIDTH : INTEGER;
C_PROBE476_WIDTH : INTEGER;
C_PROBE477_WIDTH : INTEGER;
C_PROBE478_WIDTH : INTEGER;
C_PROBE479_WIDTH : INTEGER;
C_PROBE480_WIDTH : INTEGER;
C_PROBE481_WIDTH : INTEGER;
C_PROBE482_WIDTH : INTEGER;
C_PROBE483_WIDTH : INTEGER;
C_PROBE484_WIDTH : INTEGER;
C_PROBE485_WIDTH : INTEGER;
C_PROBE486_WIDTH : INTEGER;
C_PROBE487_WIDTH : INTEGER;
C_PROBE488_WIDTH : INTEGER;
C_PROBE489_WIDTH : INTEGER;
C_PROBE490_WIDTH : INTEGER;
C_PROBE491_WIDTH : INTEGER;
C_PROBE492_WIDTH : INTEGER;
C_PROBE493_WIDTH : INTEGER;
C_PROBE494_WIDTH : INTEGER;
C_PROBE495_WIDTH : INTEGER;
C_PROBE496_WIDTH : INTEGER;
C_PROBE497_WIDTH : INTEGER;
C_PROBE498_WIDTH : INTEGER;
C_PROBE499_WIDTH : INTEGER;
C_PROBE500_WIDTH : INTEGER;
C_PROBE501_WIDTH : INTEGER;
C_PROBE502_WIDTH : INTEGER;
C_PROBE503_WIDTH : INTEGER;
C_PROBE504_WIDTH : INTEGER;
C_PROBE505_WIDTH : INTEGER;
C_PROBE506_WIDTH : INTEGER;
C_PROBE507_WIDTH : INTEGER;
C_PROBE508_WIDTH : INTEGER;
C_PROBE509_WIDTH : INTEGER;
C_PROBE510_WIDTH : INTEGER;
C_PROBE511_WIDTH : INTEGER;
C_PROBE512_WIDTH : INTEGER;
C_PROBE513_WIDTH : INTEGER;
C_PROBE514_WIDTH : INTEGER;
C_PROBE515_WIDTH : INTEGER;
C_PROBE516_WIDTH : INTEGER;
C_PROBE517_WIDTH : INTEGER;
C_PROBE518_WIDTH : INTEGER;
C_PROBE519_WIDTH : INTEGER;
C_PROBE520_WIDTH : INTEGER;
C_PROBE521_WIDTH : INTEGER;
C_PROBE522_WIDTH : INTEGER;
C_PROBE523_WIDTH : INTEGER;
C_PROBE524_WIDTH : INTEGER;
C_PROBE525_WIDTH : INTEGER;
C_PROBE526_WIDTH : INTEGER;
C_PROBE527_WIDTH : INTEGER;
C_PROBE528_WIDTH : INTEGER;
C_PROBE529_WIDTH : INTEGER;
C_PROBE530_WIDTH : INTEGER;
C_PROBE531_WIDTH : INTEGER;
C_PROBE532_WIDTH : INTEGER;
C_PROBE533_WIDTH : INTEGER;
C_PROBE534_WIDTH : INTEGER;
C_PROBE535_WIDTH : INTEGER;
C_PROBE536_WIDTH : INTEGER;
C_PROBE537_WIDTH : INTEGER;
C_PROBE538_WIDTH : INTEGER;
C_PROBE539_WIDTH : INTEGER;
C_PROBE540_WIDTH : INTEGER;
C_PROBE541_WIDTH : INTEGER;
C_PROBE542_WIDTH : INTEGER;
C_PROBE543_WIDTH : INTEGER;
C_PROBE544_WIDTH : INTEGER;
C_PROBE545_WIDTH : INTEGER;
C_PROBE546_WIDTH : INTEGER;
C_PROBE547_WIDTH : INTEGER;
C_PROBE548_WIDTH : INTEGER;
C_PROBE549_WIDTH : INTEGER;
C_PROBE550_WIDTH : INTEGER;
C_PROBE551_WIDTH : INTEGER;
C_PROBE552_WIDTH : INTEGER;
C_PROBE553_WIDTH : INTEGER;
C_PROBE554_WIDTH : INTEGER;
C_PROBE555_WIDTH : INTEGER;
C_PROBE556_WIDTH : INTEGER;
C_PROBE557_WIDTH : INTEGER;
C_PROBE558_WIDTH : INTEGER;
C_PROBE559_WIDTH : INTEGER;
C_PROBE560_WIDTH : INTEGER;
C_PROBE561_WIDTH : INTEGER;
C_PROBE562_WIDTH : INTEGER;
C_PROBE563_WIDTH : INTEGER;
C_PROBE564_WIDTH : INTEGER;
C_PROBE565_WIDTH : INTEGER;
C_PROBE566_WIDTH : INTEGER;
C_PROBE567_WIDTH : INTEGER;
C_PROBE568_WIDTH : INTEGER;
C_PROBE569_WIDTH : INTEGER;
C_PROBE570_WIDTH : INTEGER;
C_PROBE571_WIDTH : INTEGER;
C_PROBE572_WIDTH : INTEGER;
C_PROBE573_WIDTH : INTEGER;
C_PROBE574_WIDTH : INTEGER;
C_PROBE575_WIDTH : INTEGER;
C_PROBE576_WIDTH : INTEGER;
C_PROBE577_WIDTH : INTEGER;
C_PROBE578_WIDTH : INTEGER;
C_PROBE579_WIDTH : INTEGER;
C_PROBE580_WIDTH : INTEGER;
C_PROBE581_WIDTH : INTEGER;
C_PROBE582_WIDTH : INTEGER;
C_PROBE583_WIDTH : INTEGER;
C_PROBE584_WIDTH : INTEGER;
C_PROBE585_WIDTH : INTEGER;
C_PROBE586_WIDTH : INTEGER;
C_PROBE587_WIDTH : INTEGER;
C_PROBE588_WIDTH : INTEGER;
C_PROBE589_WIDTH : INTEGER;
C_PROBE590_WIDTH : INTEGER;
C_PROBE591_WIDTH : INTEGER;
C_PROBE592_WIDTH : INTEGER;
C_PROBE593_WIDTH : INTEGER;
C_PROBE594_WIDTH : INTEGER;
C_PROBE595_WIDTH : INTEGER;
C_PROBE596_WIDTH : INTEGER;
C_PROBE597_WIDTH : INTEGER;
C_PROBE598_WIDTH : INTEGER;
C_PROBE599_WIDTH : INTEGER;
C_PROBE600_WIDTH : INTEGER;
C_PROBE601_WIDTH : INTEGER;
C_PROBE602_WIDTH : INTEGER;
C_PROBE603_WIDTH : INTEGER;
C_PROBE604_WIDTH : INTEGER;
C_PROBE605_WIDTH : INTEGER;
C_PROBE606_WIDTH : INTEGER;
C_PROBE607_WIDTH : INTEGER;
C_PROBE608_WIDTH : INTEGER;
C_PROBE609_WIDTH : INTEGER;
C_PROBE610_WIDTH : INTEGER;
C_PROBE611_WIDTH : INTEGER;
C_PROBE612_WIDTH : INTEGER;
C_PROBE613_WIDTH : INTEGER;
C_PROBE614_WIDTH : INTEGER;
C_PROBE615_WIDTH : INTEGER;
C_PROBE616_WIDTH : INTEGER;
C_PROBE617_WIDTH : INTEGER;
C_PROBE618_WIDTH : INTEGER;
C_PROBE619_WIDTH : INTEGER;
C_PROBE620_WIDTH : INTEGER;
C_PROBE621_WIDTH : INTEGER;
C_PROBE622_WIDTH : INTEGER;
C_PROBE623_WIDTH : INTEGER;
C_PROBE624_WIDTH : INTEGER;
C_PROBE625_WIDTH : INTEGER;
C_PROBE626_WIDTH : INTEGER;
C_PROBE627_WIDTH : INTEGER;
C_PROBE628_WIDTH : INTEGER;
C_PROBE629_WIDTH : INTEGER;
C_PROBE630_WIDTH : INTEGER;
C_PROBE631_WIDTH : INTEGER;
C_PROBE632_WIDTH : INTEGER;
C_PROBE633_WIDTH : INTEGER;
C_PROBE634_WIDTH : INTEGER;
C_PROBE635_WIDTH : INTEGER;
C_PROBE636_WIDTH : INTEGER;
C_PROBE637_WIDTH : INTEGER;
C_PROBE638_WIDTH : INTEGER;
C_PROBE639_WIDTH : INTEGER;
C_PROBE640_WIDTH : INTEGER;
C_PROBE641_WIDTH : INTEGER;
C_PROBE642_WIDTH : INTEGER;
C_PROBE643_WIDTH : INTEGER;
C_PROBE644_WIDTH : INTEGER;
C_PROBE645_WIDTH : INTEGER;
C_PROBE646_WIDTH : INTEGER;
C_PROBE647_WIDTH : INTEGER;
C_PROBE648_WIDTH : INTEGER;
C_PROBE649_WIDTH : INTEGER;
C_PROBE650_WIDTH : INTEGER;
C_PROBE651_WIDTH : INTEGER;
C_PROBE652_WIDTH : INTEGER;
C_PROBE653_WIDTH : INTEGER;
C_PROBE654_WIDTH : INTEGER;
C_PROBE655_WIDTH : INTEGER;
C_PROBE656_WIDTH : INTEGER;
C_PROBE657_WIDTH : INTEGER;
C_PROBE658_WIDTH : INTEGER;
C_PROBE659_WIDTH : INTEGER;
C_PROBE660_WIDTH : INTEGER;
C_PROBE661_WIDTH : INTEGER;
C_PROBE662_WIDTH : INTEGER;
C_PROBE663_WIDTH : INTEGER;
C_PROBE664_WIDTH : INTEGER;
C_PROBE665_WIDTH : INTEGER;
C_PROBE666_WIDTH : INTEGER;
C_PROBE667_WIDTH : INTEGER;
C_PROBE668_WIDTH : INTEGER;
C_PROBE669_WIDTH : INTEGER;
C_PROBE670_WIDTH : INTEGER;
C_PROBE671_WIDTH : INTEGER;
C_PROBE672_WIDTH : INTEGER;
C_PROBE673_WIDTH : INTEGER;
C_PROBE674_WIDTH : INTEGER;
C_PROBE675_WIDTH : INTEGER;
C_PROBE676_WIDTH : INTEGER;
C_PROBE677_WIDTH : INTEGER;
C_PROBE678_WIDTH : INTEGER;
C_PROBE679_WIDTH : INTEGER;
C_PROBE680_WIDTH : INTEGER;
C_PROBE681_WIDTH : INTEGER;
C_PROBE682_WIDTH : INTEGER;
C_PROBE683_WIDTH : INTEGER;
C_PROBE684_WIDTH : INTEGER;
C_PROBE685_WIDTH : INTEGER;
C_PROBE686_WIDTH : INTEGER;
C_PROBE687_WIDTH : INTEGER;
C_PROBE688_WIDTH : INTEGER;
C_PROBE689_WIDTH : INTEGER;
C_PROBE690_WIDTH : INTEGER;
C_PROBE691_WIDTH : INTEGER;
C_PROBE692_WIDTH : INTEGER;
C_PROBE693_WIDTH : INTEGER;
C_PROBE694_WIDTH : INTEGER;
C_PROBE695_WIDTH : INTEGER;
C_PROBE696_WIDTH : INTEGER;
C_PROBE697_WIDTH : INTEGER;
C_PROBE698_WIDTH : INTEGER;
C_PROBE699_WIDTH : INTEGER;
C_PROBE700_WIDTH : INTEGER;
C_PROBE701_WIDTH : INTEGER;
C_PROBE702_WIDTH : INTEGER;
C_PROBE703_WIDTH : INTEGER;
C_PROBE704_WIDTH : INTEGER;
C_PROBE705_WIDTH : INTEGER;
C_PROBE706_WIDTH : INTEGER;
C_PROBE707_WIDTH : INTEGER;
C_PROBE708_WIDTH : INTEGER;
C_PROBE709_WIDTH : INTEGER;
C_PROBE710_WIDTH : INTEGER;
C_PROBE711_WIDTH : INTEGER;
C_PROBE712_WIDTH : INTEGER;
C_PROBE713_WIDTH : INTEGER;
C_PROBE714_WIDTH : INTEGER;
C_PROBE715_WIDTH : INTEGER;
C_PROBE716_WIDTH : INTEGER;
C_PROBE717_WIDTH : INTEGER;
C_PROBE718_WIDTH : INTEGER;
C_PROBE719_WIDTH : INTEGER;
C_PROBE720_WIDTH : INTEGER;
C_PROBE721_WIDTH : INTEGER;
C_PROBE722_WIDTH : INTEGER;
C_PROBE723_WIDTH : INTEGER;
C_PROBE724_WIDTH : INTEGER;
C_PROBE725_WIDTH : INTEGER;
C_PROBE726_WIDTH : INTEGER;
C_PROBE727_WIDTH : INTEGER;
C_PROBE728_WIDTH : INTEGER;
C_PROBE729_WIDTH : INTEGER;
C_PROBE730_WIDTH : INTEGER;
C_PROBE731_WIDTH : INTEGER;
C_PROBE732_WIDTH : INTEGER;
C_PROBE733_WIDTH : INTEGER;
C_PROBE734_WIDTH : INTEGER;
C_PROBE735_WIDTH : INTEGER;
C_PROBE736_WIDTH : INTEGER;
C_PROBE737_WIDTH : INTEGER;
C_PROBE738_WIDTH : INTEGER;
C_PROBE739_WIDTH : INTEGER;
C_PROBE740_WIDTH : INTEGER;
C_PROBE741_WIDTH : INTEGER;
C_PROBE742_WIDTH : INTEGER;
C_PROBE743_WIDTH : INTEGER;
C_PROBE744_WIDTH : INTEGER;
C_PROBE745_WIDTH : INTEGER;
C_PROBE746_WIDTH : INTEGER;
C_PROBE747_WIDTH : INTEGER;
C_PROBE748_WIDTH : INTEGER;
C_PROBE749_WIDTH : INTEGER;
C_PROBE750_WIDTH : INTEGER;
C_PROBE751_WIDTH : INTEGER;
C_PROBE752_WIDTH : INTEGER;
C_PROBE753_WIDTH : INTEGER;
C_PROBE754_WIDTH : INTEGER;
C_PROBE755_WIDTH : INTEGER;
C_PROBE756_WIDTH : INTEGER;
C_PROBE757_WIDTH : INTEGER;
C_PROBE758_WIDTH : INTEGER;
C_PROBE759_WIDTH : INTEGER;
C_PROBE760_WIDTH : INTEGER;
C_PROBE761_WIDTH : INTEGER;
C_PROBE762_WIDTH : INTEGER;
C_PROBE763_WIDTH : INTEGER;
C_PROBE764_WIDTH : INTEGER;
C_PROBE765_WIDTH : INTEGER;
C_PROBE766_WIDTH : INTEGER;
C_PROBE767_WIDTH : INTEGER;
C_PROBE768_WIDTH : INTEGER;
C_PROBE769_WIDTH : INTEGER;
C_PROBE770_WIDTH : INTEGER;
C_PROBE771_WIDTH : INTEGER;
C_PROBE772_WIDTH : INTEGER;
C_PROBE773_WIDTH : INTEGER;
C_PROBE774_WIDTH : INTEGER;
C_PROBE775_WIDTH : INTEGER;
C_PROBE776_WIDTH : INTEGER;
C_PROBE777_WIDTH : INTEGER;
C_PROBE778_WIDTH : INTEGER;
C_PROBE779_WIDTH : INTEGER;
C_PROBE780_WIDTH : INTEGER;
C_PROBE781_WIDTH : INTEGER;
C_PROBE782_WIDTH : INTEGER;
C_PROBE783_WIDTH : INTEGER;
C_PROBE784_WIDTH : INTEGER;
C_PROBE785_WIDTH : INTEGER;
C_PROBE786_WIDTH : INTEGER;
C_PROBE787_WIDTH : INTEGER;
C_PROBE788_WIDTH : INTEGER;
C_PROBE789_WIDTH : INTEGER;
C_PROBE790_WIDTH : INTEGER;
C_PROBE791_WIDTH : INTEGER;
C_PROBE792_WIDTH : INTEGER;
C_PROBE793_WIDTH : INTEGER;
C_PROBE794_WIDTH : INTEGER;
C_PROBE795_WIDTH : INTEGER;
C_PROBE796_WIDTH : INTEGER;
C_PROBE797_WIDTH : INTEGER;
C_PROBE798_WIDTH : INTEGER;
C_PROBE799_WIDTH : INTEGER;
C_PROBE800_WIDTH : INTEGER;
C_PROBE801_WIDTH : INTEGER;
C_PROBE802_WIDTH : INTEGER;
C_PROBE803_WIDTH : INTEGER;
C_PROBE804_WIDTH : INTEGER;
C_PROBE805_WIDTH : INTEGER;
C_PROBE806_WIDTH : INTEGER;
C_PROBE807_WIDTH : INTEGER;
C_PROBE808_WIDTH : INTEGER;
C_PROBE809_WIDTH : INTEGER;
C_PROBE810_WIDTH : INTEGER;
C_PROBE811_WIDTH : INTEGER;
C_PROBE812_WIDTH : INTEGER;
C_PROBE813_WIDTH : INTEGER;
C_PROBE814_WIDTH : INTEGER;
C_PROBE815_WIDTH : INTEGER;
C_PROBE816_WIDTH : INTEGER;
C_PROBE817_WIDTH : INTEGER;
C_PROBE818_WIDTH : INTEGER;
C_PROBE819_WIDTH : INTEGER;
C_PROBE820_WIDTH : INTEGER;
C_PROBE821_WIDTH : INTEGER;
C_PROBE822_WIDTH : INTEGER;
C_PROBE823_WIDTH : INTEGER;
C_PROBE824_WIDTH : INTEGER;
C_PROBE825_WIDTH : INTEGER;
C_PROBE826_WIDTH : INTEGER;
C_PROBE827_WIDTH : INTEGER;
C_PROBE828_WIDTH : INTEGER;
C_PROBE829_WIDTH : INTEGER;
C_PROBE830_WIDTH : INTEGER;
C_PROBE831_WIDTH : INTEGER;
C_PROBE832_WIDTH : INTEGER;
C_PROBE833_WIDTH : INTEGER;
C_PROBE834_WIDTH : INTEGER;
C_PROBE835_WIDTH : INTEGER;
C_PROBE836_WIDTH : INTEGER;
C_PROBE837_WIDTH : INTEGER;
C_PROBE838_WIDTH : INTEGER;
C_PROBE839_WIDTH : INTEGER;
C_PROBE840_WIDTH : INTEGER;
C_PROBE841_WIDTH : INTEGER;
C_PROBE842_WIDTH : INTEGER;
C_PROBE843_WIDTH : INTEGER;
C_PROBE844_WIDTH : INTEGER;
C_PROBE845_WIDTH : INTEGER;
C_PROBE846_WIDTH : INTEGER;
C_PROBE847_WIDTH : INTEGER;
C_PROBE848_WIDTH : INTEGER;
C_PROBE849_WIDTH : INTEGER;
C_PROBE850_WIDTH : INTEGER;
C_PROBE851_WIDTH : INTEGER;
C_PROBE852_WIDTH : INTEGER;
C_PROBE853_WIDTH : INTEGER;
C_PROBE854_WIDTH : INTEGER;
C_PROBE855_WIDTH : INTEGER;
C_PROBE856_WIDTH : INTEGER;
C_PROBE857_WIDTH : INTEGER;
C_PROBE858_WIDTH : INTEGER;
C_PROBE859_WIDTH : INTEGER;
C_PROBE860_WIDTH : INTEGER;
C_PROBE861_WIDTH : INTEGER;
C_PROBE862_WIDTH : INTEGER;
C_PROBE863_WIDTH : INTEGER;
C_PROBE864_WIDTH : INTEGER;
C_PROBE865_WIDTH : INTEGER;
C_PROBE866_WIDTH : INTEGER;
C_PROBE867_WIDTH : INTEGER;
C_PROBE868_WIDTH : INTEGER;
C_PROBE869_WIDTH : INTEGER;
C_PROBE870_WIDTH : INTEGER;
C_PROBE871_WIDTH : INTEGER;
C_PROBE872_WIDTH : INTEGER;
C_PROBE873_WIDTH : INTEGER;
C_PROBE874_WIDTH : INTEGER;
C_PROBE875_WIDTH : INTEGER;
C_PROBE876_WIDTH : INTEGER;
C_PROBE877_WIDTH : INTEGER;
C_PROBE878_WIDTH : INTEGER;
C_PROBE879_WIDTH : INTEGER;
C_PROBE880_WIDTH : INTEGER;
C_PROBE881_WIDTH : INTEGER;
C_PROBE882_WIDTH : INTEGER;
C_PROBE883_WIDTH : INTEGER;
C_PROBE884_WIDTH : INTEGER;
C_PROBE885_WIDTH : INTEGER;
C_PROBE886_WIDTH : INTEGER;
C_PROBE887_WIDTH : INTEGER;
C_PROBE888_WIDTH : INTEGER;
C_PROBE889_WIDTH : INTEGER;
C_PROBE890_WIDTH : INTEGER;
C_PROBE891_WIDTH : INTEGER;
C_PROBE892_WIDTH : INTEGER;
C_PROBE893_WIDTH : INTEGER;
C_PROBE894_WIDTH : INTEGER;
C_PROBE895_WIDTH : INTEGER;
C_PROBE896_WIDTH : INTEGER;
C_PROBE897_WIDTH : INTEGER;
C_PROBE898_WIDTH : INTEGER;
C_PROBE899_WIDTH : INTEGER;
C_PROBE900_WIDTH : INTEGER;
C_PROBE901_WIDTH : INTEGER;
C_PROBE902_WIDTH : INTEGER;
C_PROBE903_WIDTH : INTEGER;
C_PROBE904_WIDTH : INTEGER;
C_PROBE905_WIDTH : INTEGER;
C_PROBE906_WIDTH : INTEGER;
C_PROBE907_WIDTH : INTEGER;
C_PROBE908_WIDTH : INTEGER;
C_PROBE909_WIDTH : INTEGER;
C_PROBE910_WIDTH : INTEGER;
C_PROBE911_WIDTH : INTEGER;
C_PROBE912_WIDTH : INTEGER;
C_PROBE913_WIDTH : INTEGER;
C_PROBE914_WIDTH : INTEGER;
C_PROBE915_WIDTH : INTEGER;
C_PROBE916_WIDTH : INTEGER;
C_PROBE917_WIDTH : INTEGER;
C_PROBE918_WIDTH : INTEGER;
C_PROBE919_WIDTH : INTEGER;
C_PROBE920_WIDTH : INTEGER;
C_PROBE921_WIDTH : INTEGER;
C_PROBE922_WIDTH : INTEGER;
C_PROBE923_WIDTH : INTEGER;
C_PROBE924_WIDTH : INTEGER;
C_PROBE925_WIDTH : INTEGER;
C_PROBE926_WIDTH : INTEGER;
C_PROBE927_WIDTH : INTEGER;
C_PROBE928_WIDTH : INTEGER;
C_PROBE929_WIDTH : INTEGER;
C_PROBE930_WIDTH : INTEGER;
C_PROBE931_WIDTH : INTEGER;
C_PROBE932_WIDTH : INTEGER;
C_PROBE933_WIDTH : INTEGER;
C_PROBE934_WIDTH : INTEGER;
C_PROBE935_WIDTH : INTEGER;
C_PROBE936_WIDTH : INTEGER;
C_PROBE937_WIDTH : INTEGER;
C_PROBE938_WIDTH : INTEGER;
C_PROBE939_WIDTH : INTEGER;
C_PROBE940_WIDTH : INTEGER;
C_PROBE941_WIDTH : INTEGER;
C_PROBE942_WIDTH : INTEGER;
C_PROBE943_WIDTH : INTEGER;
C_PROBE944_WIDTH : INTEGER;
C_PROBE945_WIDTH : INTEGER;
C_PROBE946_WIDTH : INTEGER;
C_PROBE947_WIDTH : INTEGER;
C_PROBE948_WIDTH : INTEGER;
C_PROBE949_WIDTH : INTEGER;
C_PROBE950_WIDTH : INTEGER;
C_PROBE951_WIDTH : INTEGER;
C_PROBE952_WIDTH : INTEGER;
C_PROBE953_WIDTH : INTEGER;
C_PROBE954_WIDTH : INTEGER;
C_PROBE955_WIDTH : INTEGER;
C_PROBE956_WIDTH : INTEGER;
C_PROBE957_WIDTH : INTEGER;
C_PROBE958_WIDTH : INTEGER;
C_PROBE959_WIDTH : INTEGER;
C_PROBE960_WIDTH : INTEGER;
C_PROBE961_WIDTH : INTEGER;
C_PROBE962_WIDTH : INTEGER;
C_PROBE963_WIDTH : INTEGER;
C_PROBE964_WIDTH : INTEGER;
C_PROBE965_WIDTH : INTEGER;
C_PROBE966_WIDTH : INTEGER;
C_PROBE967_WIDTH : INTEGER;
C_PROBE968_WIDTH : INTEGER;
C_PROBE969_WIDTH : INTEGER;
C_PROBE970_WIDTH : INTEGER;
C_PROBE971_WIDTH : INTEGER;
C_PROBE972_WIDTH : INTEGER;
C_PROBE973_WIDTH : INTEGER;
C_PROBE974_WIDTH : INTEGER;
C_PROBE975_WIDTH : INTEGER;
C_PROBE976_WIDTH : INTEGER;
C_PROBE977_WIDTH : INTEGER;
C_PROBE978_WIDTH : INTEGER;
C_PROBE979_WIDTH : INTEGER;
C_PROBE980_WIDTH : INTEGER;
C_PROBE981_WIDTH : INTEGER;
C_PROBE982_WIDTH : INTEGER;
C_PROBE983_WIDTH : INTEGER;
C_PROBE984_WIDTH : INTEGER;
C_PROBE985_WIDTH : INTEGER;
C_PROBE986_WIDTH : INTEGER;
C_PROBE987_WIDTH : INTEGER;
C_PROBE988_WIDTH : INTEGER;
C_PROBE989_WIDTH : INTEGER;
C_PROBE990_WIDTH : INTEGER;
C_PROBE991_WIDTH : INTEGER;
C_PROBE992_WIDTH : INTEGER;
C_PROBE993_WIDTH : INTEGER;
C_PROBE994_WIDTH : INTEGER;
C_PROBE995_WIDTH : INTEGER;
C_PROBE996_WIDTH : INTEGER;
C_PROBE997_WIDTH : INTEGER;
C_PROBE998_WIDTH : INTEGER;
C_PROBE999_WIDTH : INTEGER;
C_PROBE1000_WIDTH : INTEGER;
C_PROBE1001_WIDTH : INTEGER;
C_PROBE1002_WIDTH : INTEGER;
C_PROBE1003_WIDTH : INTEGER;
C_PROBE1004_WIDTH : INTEGER;
C_PROBE1005_WIDTH : INTEGER;
C_PROBE1006_WIDTH : INTEGER;
C_PROBE1007_WIDTH : INTEGER;
C_PROBE1008_WIDTH : INTEGER;
C_PROBE1009_WIDTH : INTEGER;
C_PROBE1010_WIDTH : INTEGER;
C_PROBE1011_WIDTH : INTEGER;
C_PROBE1012_WIDTH : INTEGER;
C_PROBE1013_WIDTH : INTEGER;
C_PROBE1014_WIDTH : INTEGER;
C_PROBE1015_WIDTH : INTEGER;
C_PROBE1016_WIDTH : INTEGER;
C_PROBE1017_WIDTH : INTEGER;
C_PROBE1018_WIDTH : INTEGER;
C_PROBE1019_WIDTH : INTEGER;
C_PROBE1020_WIDTH : INTEGER;
C_PROBE1021_WIDTH : INTEGER;
C_PROBE1022_WIDTH : INTEGER;
C_PROBE1023_WIDTH : INTEGER;
C_PROBE0_MU_CNT : INTEGER;
C_PROBE1_MU_CNT : INTEGER;
C_PROBE2_MU_CNT : INTEGER;
C_PROBE3_MU_CNT : INTEGER;
C_PROBE4_MU_CNT : INTEGER;
C_PROBE5_MU_CNT : INTEGER;
C_PROBE6_MU_CNT : INTEGER;
C_PROBE7_MU_CNT : INTEGER;
C_PROBE8_MU_CNT : INTEGER;
C_PROBE9_MU_CNT : INTEGER;
C_PROBE10_MU_CNT : INTEGER;
C_PROBE11_MU_CNT : INTEGER;
C_PROBE12_MU_CNT : INTEGER;
C_PROBE13_MU_CNT : INTEGER;
C_PROBE14_MU_CNT : INTEGER;
C_PROBE15_MU_CNT : INTEGER;
C_PROBE16_MU_CNT : INTEGER;
C_PROBE17_MU_CNT : INTEGER;
C_PROBE18_MU_CNT : INTEGER;
C_PROBE19_MU_CNT : INTEGER;
C_PROBE20_MU_CNT : INTEGER;
C_PROBE21_MU_CNT : INTEGER;
C_PROBE22_MU_CNT : INTEGER;
C_PROBE23_MU_CNT : INTEGER;
C_PROBE24_MU_CNT : INTEGER;
C_PROBE25_MU_CNT : INTEGER;
C_PROBE26_MU_CNT : INTEGER;
C_PROBE27_MU_CNT : INTEGER;
C_PROBE28_MU_CNT : INTEGER;
C_PROBE29_MU_CNT : INTEGER;
C_PROBE30_MU_CNT : INTEGER;
C_PROBE31_MU_CNT : INTEGER;
C_PROBE32_MU_CNT : INTEGER;
C_PROBE33_MU_CNT : INTEGER;
C_PROBE34_MU_CNT : INTEGER;
C_PROBE35_MU_CNT : INTEGER;
C_PROBE36_MU_CNT : INTEGER;
C_PROBE37_MU_CNT : INTEGER;
C_PROBE38_MU_CNT : INTEGER;
C_PROBE39_MU_CNT : INTEGER;
C_PROBE40_MU_CNT : INTEGER;
C_PROBE41_MU_CNT : INTEGER;
C_PROBE42_MU_CNT : INTEGER;
C_PROBE43_MU_CNT : INTEGER;
C_PROBE44_MU_CNT : INTEGER;
C_PROBE45_MU_CNT : INTEGER;
C_PROBE46_MU_CNT : INTEGER;
C_PROBE47_MU_CNT : INTEGER;
C_PROBE48_MU_CNT : INTEGER;
C_PROBE49_MU_CNT : INTEGER;
C_PROBE50_MU_CNT : INTEGER;
C_PROBE51_MU_CNT : INTEGER;
C_PROBE52_MU_CNT : INTEGER;
C_PROBE53_MU_CNT : INTEGER;
C_PROBE54_MU_CNT : INTEGER;
C_PROBE55_MU_CNT : INTEGER;
C_PROBE56_MU_CNT : INTEGER;
C_PROBE57_MU_CNT : INTEGER;
C_PROBE58_MU_CNT : INTEGER;
C_PROBE59_MU_CNT : INTEGER;
C_PROBE60_MU_CNT : INTEGER;
C_PROBE61_MU_CNT : INTEGER;
C_PROBE62_MU_CNT : INTEGER;
C_PROBE63_MU_CNT : INTEGER;
C_PROBE64_MU_CNT : INTEGER;
C_PROBE65_MU_CNT : INTEGER;
C_PROBE66_MU_CNT : INTEGER;
C_PROBE67_MU_CNT : INTEGER;
C_PROBE68_MU_CNT : INTEGER;
C_PROBE69_MU_CNT : INTEGER;
C_PROBE70_MU_CNT : INTEGER;
C_PROBE71_MU_CNT : INTEGER;
C_PROBE72_MU_CNT : INTEGER;
C_PROBE73_MU_CNT : INTEGER;
C_PROBE74_MU_CNT : INTEGER;
C_PROBE75_MU_CNT : INTEGER;
C_PROBE76_MU_CNT : INTEGER;
C_PROBE77_MU_CNT : INTEGER;
C_PROBE78_MU_CNT : INTEGER;
C_PROBE79_MU_CNT : INTEGER;
C_PROBE80_MU_CNT : INTEGER;
C_PROBE81_MU_CNT : INTEGER;
C_PROBE82_MU_CNT : INTEGER;
C_PROBE83_MU_CNT : INTEGER;
C_PROBE84_MU_CNT : INTEGER;
C_PROBE85_MU_CNT : INTEGER;
C_PROBE86_MU_CNT : INTEGER;
C_PROBE87_MU_CNT : INTEGER;
C_PROBE88_MU_CNT : INTEGER;
C_PROBE89_MU_CNT : INTEGER;
C_PROBE90_MU_CNT : INTEGER;
C_PROBE91_MU_CNT : INTEGER;
C_PROBE92_MU_CNT : INTEGER;
C_PROBE93_MU_CNT : INTEGER;
C_PROBE94_MU_CNT : INTEGER;
C_PROBE95_MU_CNT : INTEGER;
C_PROBE96_MU_CNT : INTEGER;
C_PROBE97_MU_CNT : INTEGER;
C_PROBE98_MU_CNT : INTEGER;
C_PROBE99_MU_CNT : INTEGER;
C_PROBE100_MU_CNT : INTEGER;
C_PROBE101_MU_CNT : INTEGER;
C_PROBE102_MU_CNT : INTEGER;
C_PROBE103_MU_CNT : INTEGER;
C_PROBE104_MU_CNT : INTEGER;
C_PROBE105_MU_CNT : INTEGER;
C_PROBE106_MU_CNT : INTEGER;
C_PROBE107_MU_CNT : INTEGER;
C_PROBE108_MU_CNT : INTEGER;
C_PROBE109_MU_CNT : INTEGER;
C_PROBE110_MU_CNT : INTEGER;
C_PROBE111_MU_CNT : INTEGER;
C_PROBE112_MU_CNT : INTEGER;
C_PROBE113_MU_CNT : INTEGER;
C_PROBE114_MU_CNT : INTEGER;
C_PROBE115_MU_CNT : INTEGER;
C_PROBE116_MU_CNT : INTEGER;
C_PROBE117_MU_CNT : INTEGER;
C_PROBE118_MU_CNT : INTEGER;
C_PROBE119_MU_CNT : INTEGER;
C_PROBE120_MU_CNT : INTEGER;
C_PROBE121_MU_CNT : INTEGER;
C_PROBE122_MU_CNT : INTEGER;
C_PROBE123_MU_CNT : INTEGER;
C_PROBE124_MU_CNT : INTEGER;
C_PROBE125_MU_CNT : INTEGER;
C_PROBE126_MU_CNT : INTEGER;
C_PROBE127_MU_CNT : INTEGER;
C_PROBE128_MU_CNT : INTEGER;
C_PROBE129_MU_CNT : INTEGER;
C_PROBE130_MU_CNT : INTEGER;
C_PROBE131_MU_CNT : INTEGER;
C_PROBE132_MU_CNT : INTEGER;
C_PROBE133_MU_CNT : INTEGER;
C_PROBE134_MU_CNT : INTEGER;
C_PROBE135_MU_CNT : INTEGER;
C_PROBE136_MU_CNT : INTEGER;
C_PROBE137_MU_CNT : INTEGER;
C_PROBE138_MU_CNT : INTEGER;
C_PROBE139_MU_CNT : INTEGER;
C_PROBE140_MU_CNT : INTEGER;
C_PROBE141_MU_CNT : INTEGER;
C_PROBE142_MU_CNT : INTEGER;
C_PROBE143_MU_CNT : INTEGER;
C_PROBE144_MU_CNT : INTEGER;
C_PROBE145_MU_CNT : INTEGER;
C_PROBE146_MU_CNT : INTEGER;
C_PROBE147_MU_CNT : INTEGER;
C_PROBE148_MU_CNT : INTEGER;
C_PROBE149_MU_CNT : INTEGER;
C_PROBE150_MU_CNT : INTEGER;
C_PROBE151_MU_CNT : INTEGER;
C_PROBE152_MU_CNT : INTEGER;
C_PROBE153_MU_CNT : INTEGER;
C_PROBE154_MU_CNT : INTEGER;
C_PROBE155_MU_CNT : INTEGER;
C_PROBE156_MU_CNT : INTEGER;
C_PROBE157_MU_CNT : INTEGER;
C_PROBE158_MU_CNT : INTEGER;
C_PROBE159_MU_CNT : INTEGER;
C_PROBE160_MU_CNT : INTEGER;
C_PROBE161_MU_CNT : INTEGER;
C_PROBE162_MU_CNT : INTEGER;
C_PROBE163_MU_CNT : INTEGER;
C_PROBE164_MU_CNT : INTEGER;
C_PROBE165_MU_CNT : INTEGER;
C_PROBE166_MU_CNT : INTEGER;
C_PROBE167_MU_CNT : INTEGER;
C_PROBE168_MU_CNT : INTEGER;
C_PROBE169_MU_CNT : INTEGER;
C_PROBE170_MU_CNT : INTEGER;
C_PROBE171_MU_CNT : INTEGER;
C_PROBE172_MU_CNT : INTEGER;
C_PROBE173_MU_CNT : INTEGER;
C_PROBE174_MU_CNT : INTEGER;
C_PROBE175_MU_CNT : INTEGER;
C_PROBE176_MU_CNT : INTEGER;
C_PROBE177_MU_CNT : INTEGER;
C_PROBE178_MU_CNT : INTEGER;
C_PROBE179_MU_CNT : INTEGER;
C_PROBE180_MU_CNT : INTEGER;
C_PROBE181_MU_CNT : INTEGER;
C_PROBE182_MU_CNT : INTEGER;
C_PROBE183_MU_CNT : INTEGER;
C_PROBE184_MU_CNT : INTEGER;
C_PROBE185_MU_CNT : INTEGER;
C_PROBE186_MU_CNT : INTEGER;
C_PROBE187_MU_CNT : INTEGER;
C_PROBE188_MU_CNT : INTEGER;
C_PROBE189_MU_CNT : INTEGER;
C_PROBE190_MU_CNT : INTEGER;
C_PROBE191_MU_CNT : INTEGER;
C_PROBE192_MU_CNT : INTEGER;
C_PROBE193_MU_CNT : INTEGER;
C_PROBE194_MU_CNT : INTEGER;
C_PROBE195_MU_CNT : INTEGER;
C_PROBE196_MU_CNT : INTEGER;
C_PROBE197_MU_CNT : INTEGER;
C_PROBE198_MU_CNT : INTEGER;
C_PROBE199_MU_CNT : INTEGER;
C_PROBE200_MU_CNT : INTEGER;
C_PROBE201_MU_CNT : INTEGER;
C_PROBE202_MU_CNT : INTEGER;
C_PROBE203_MU_CNT : INTEGER;
C_PROBE204_MU_CNT : INTEGER;
C_PROBE205_MU_CNT : INTEGER;
C_PROBE206_MU_CNT : INTEGER;
C_PROBE207_MU_CNT : INTEGER;
C_PROBE208_MU_CNT : INTEGER;
C_PROBE209_MU_CNT : INTEGER;
C_PROBE210_MU_CNT : INTEGER;
C_PROBE211_MU_CNT : INTEGER;
C_PROBE212_MU_CNT : INTEGER;
C_PROBE213_MU_CNT : INTEGER;
C_PROBE214_MU_CNT : INTEGER;
C_PROBE215_MU_CNT : INTEGER;
C_PROBE216_MU_CNT : INTEGER;
C_PROBE217_MU_CNT : INTEGER;
C_PROBE218_MU_CNT : INTEGER;
C_PROBE219_MU_CNT : INTEGER;
C_PROBE220_MU_CNT : INTEGER;
C_PROBE221_MU_CNT : INTEGER;
C_PROBE222_MU_CNT : INTEGER;
C_PROBE223_MU_CNT : INTEGER;
C_PROBE224_MU_CNT : INTEGER;
C_PROBE225_MU_CNT : INTEGER;
C_PROBE226_MU_CNT : INTEGER;
C_PROBE227_MU_CNT : INTEGER;
C_PROBE228_MU_CNT : INTEGER;
C_PROBE229_MU_CNT : INTEGER;
C_PROBE230_MU_CNT : INTEGER;
C_PROBE231_MU_CNT : INTEGER;
C_PROBE232_MU_CNT : INTEGER;
C_PROBE233_MU_CNT : INTEGER;
C_PROBE234_MU_CNT : INTEGER;
C_PROBE235_MU_CNT : INTEGER;
C_PROBE236_MU_CNT : INTEGER;
C_PROBE237_MU_CNT : INTEGER;
C_PROBE238_MU_CNT : INTEGER;
C_PROBE239_MU_CNT : INTEGER;
C_PROBE240_MU_CNT : INTEGER;
C_PROBE241_MU_CNT : INTEGER;
C_PROBE242_MU_CNT : INTEGER;
C_PROBE243_MU_CNT : INTEGER;
C_PROBE244_MU_CNT : INTEGER;
C_PROBE245_MU_CNT : INTEGER;
C_PROBE246_MU_CNT : INTEGER;
C_PROBE247_MU_CNT : INTEGER;
C_PROBE248_MU_CNT : INTEGER;
C_PROBE249_MU_CNT : INTEGER;
C_PROBE250_MU_CNT : INTEGER;
C_PROBE251_MU_CNT : INTEGER;
C_PROBE252_MU_CNT : INTEGER;
C_PROBE253_MU_CNT : INTEGER;
C_PROBE254_MU_CNT : INTEGER;
C_PROBE255_MU_CNT : INTEGER;
C_PROBE256_MU_CNT : INTEGER;
C_PROBE257_MU_CNT : INTEGER;
C_PROBE258_MU_CNT : INTEGER;
C_PROBE259_MU_CNT : INTEGER;
C_PROBE260_MU_CNT : INTEGER;
C_PROBE261_MU_CNT : INTEGER;
C_PROBE262_MU_CNT : INTEGER;
C_PROBE263_MU_CNT : INTEGER;
C_PROBE264_MU_CNT : INTEGER;
C_PROBE265_MU_CNT : INTEGER;
C_PROBE266_MU_CNT : INTEGER;
C_PROBE267_MU_CNT : INTEGER;
C_PROBE268_MU_CNT : INTEGER;
C_PROBE269_MU_CNT : INTEGER;
C_PROBE270_MU_CNT : INTEGER;
C_PROBE271_MU_CNT : INTEGER;
C_PROBE272_MU_CNT : INTEGER;
C_PROBE273_MU_CNT : INTEGER;
C_PROBE274_MU_CNT : INTEGER;
C_PROBE275_MU_CNT : INTEGER;
C_PROBE276_MU_CNT : INTEGER;
C_PROBE277_MU_CNT : INTEGER;
C_PROBE278_MU_CNT : INTEGER;
C_PROBE279_MU_CNT : INTEGER;
C_PROBE280_MU_CNT : INTEGER;
C_PROBE281_MU_CNT : INTEGER;
C_PROBE282_MU_CNT : INTEGER;
C_PROBE283_MU_CNT : INTEGER;
C_PROBE284_MU_CNT : INTEGER;
C_PROBE285_MU_CNT : INTEGER;
C_PROBE286_MU_CNT : INTEGER;
C_PROBE287_MU_CNT : INTEGER;
C_PROBE288_MU_CNT : INTEGER;
C_PROBE289_MU_CNT : INTEGER;
C_PROBE290_MU_CNT : INTEGER;
C_PROBE291_MU_CNT : INTEGER;
C_PROBE292_MU_CNT : INTEGER;
C_PROBE293_MU_CNT : INTEGER;
C_PROBE294_MU_CNT : INTEGER;
C_PROBE295_MU_CNT : INTEGER;
C_PROBE296_MU_CNT : INTEGER;
C_PROBE297_MU_CNT : INTEGER;
C_PROBE298_MU_CNT : INTEGER;
C_PROBE299_MU_CNT : INTEGER;
C_PROBE300_MU_CNT : INTEGER;
C_PROBE301_MU_CNT : INTEGER;
C_PROBE302_MU_CNT : INTEGER;
C_PROBE303_MU_CNT : INTEGER;
C_PROBE304_MU_CNT : INTEGER;
C_PROBE305_MU_CNT : INTEGER;
C_PROBE306_MU_CNT : INTEGER;
C_PROBE307_MU_CNT : INTEGER;
C_PROBE308_MU_CNT : INTEGER;
C_PROBE309_MU_CNT : INTEGER;
C_PROBE310_MU_CNT : INTEGER;
C_PROBE311_MU_CNT : INTEGER;
C_PROBE312_MU_CNT : INTEGER;
C_PROBE313_MU_CNT : INTEGER;
C_PROBE314_MU_CNT : INTEGER;
C_PROBE315_MU_CNT : INTEGER;
C_PROBE316_MU_CNT : INTEGER;
C_PROBE317_MU_CNT : INTEGER;
C_PROBE318_MU_CNT : INTEGER;
C_PROBE319_MU_CNT : INTEGER;
C_PROBE320_MU_CNT : INTEGER;
C_PROBE321_MU_CNT : INTEGER;
C_PROBE322_MU_CNT : INTEGER;
C_PROBE323_MU_CNT : INTEGER;
C_PROBE324_MU_CNT : INTEGER;
C_PROBE325_MU_CNT : INTEGER;
C_PROBE326_MU_CNT : INTEGER;
C_PROBE327_MU_CNT : INTEGER;
C_PROBE328_MU_CNT : INTEGER;
C_PROBE329_MU_CNT : INTEGER;
C_PROBE330_MU_CNT : INTEGER;
C_PROBE331_MU_CNT : INTEGER;
C_PROBE332_MU_CNT : INTEGER;
C_PROBE333_MU_CNT : INTEGER;
C_PROBE334_MU_CNT : INTEGER;
C_PROBE335_MU_CNT : INTEGER;
C_PROBE336_MU_CNT : INTEGER;
C_PROBE337_MU_CNT : INTEGER;
C_PROBE338_MU_CNT : INTEGER;
C_PROBE339_MU_CNT : INTEGER;
C_PROBE340_MU_CNT : INTEGER;
C_PROBE341_MU_CNT : INTEGER;
C_PROBE342_MU_CNT : INTEGER;
C_PROBE343_MU_CNT : INTEGER;
C_PROBE344_MU_CNT : INTEGER;
C_PROBE345_MU_CNT : INTEGER;
C_PROBE346_MU_CNT : INTEGER;
C_PROBE347_MU_CNT : INTEGER;
C_PROBE348_MU_CNT : INTEGER;
C_PROBE349_MU_CNT : INTEGER;
C_PROBE350_MU_CNT : INTEGER;
C_PROBE351_MU_CNT : INTEGER;
C_PROBE352_MU_CNT : INTEGER;
C_PROBE353_MU_CNT : INTEGER;
C_PROBE354_MU_CNT : INTEGER;
C_PROBE355_MU_CNT : INTEGER;
C_PROBE356_MU_CNT : INTEGER;
C_PROBE357_MU_CNT : INTEGER;
C_PROBE358_MU_CNT : INTEGER;
C_PROBE359_MU_CNT : INTEGER;
C_PROBE360_MU_CNT : INTEGER;
C_PROBE361_MU_CNT : INTEGER;
C_PROBE362_MU_CNT : INTEGER;
C_PROBE363_MU_CNT : INTEGER;
C_PROBE364_MU_CNT : INTEGER;
C_PROBE365_MU_CNT : INTEGER;
C_PROBE366_MU_CNT : INTEGER;
C_PROBE367_MU_CNT : INTEGER;
C_PROBE368_MU_CNT : INTEGER;
C_PROBE369_MU_CNT : INTEGER;
C_PROBE370_MU_CNT : INTEGER;
C_PROBE371_MU_CNT : INTEGER;
C_PROBE372_MU_CNT : INTEGER;
C_PROBE373_MU_CNT : INTEGER;
C_PROBE374_MU_CNT : INTEGER;
C_PROBE375_MU_CNT : INTEGER;
C_PROBE376_MU_CNT : INTEGER;
C_PROBE377_MU_CNT : INTEGER;
C_PROBE378_MU_CNT : INTEGER;
C_PROBE379_MU_CNT : INTEGER;
C_PROBE380_MU_CNT : INTEGER;
C_PROBE381_MU_CNT : INTEGER;
C_PROBE382_MU_CNT : INTEGER;
C_PROBE383_MU_CNT : INTEGER;
C_PROBE384_MU_CNT : INTEGER;
C_PROBE385_MU_CNT : INTEGER;
C_PROBE386_MU_CNT : INTEGER;
C_PROBE387_MU_CNT : INTEGER;
C_PROBE388_MU_CNT : INTEGER;
C_PROBE389_MU_CNT : INTEGER;
C_PROBE390_MU_CNT : INTEGER;
C_PROBE391_MU_CNT : INTEGER;
C_PROBE392_MU_CNT : INTEGER;
C_PROBE393_MU_CNT : INTEGER;
C_PROBE394_MU_CNT : INTEGER;
C_PROBE395_MU_CNT : INTEGER;
C_PROBE396_MU_CNT : INTEGER;
C_PROBE397_MU_CNT : INTEGER;
C_PROBE398_MU_CNT : INTEGER;
C_PROBE399_MU_CNT : INTEGER;
C_PROBE400_MU_CNT : INTEGER;
C_PROBE401_MU_CNT : INTEGER;
C_PROBE402_MU_CNT : INTEGER;
C_PROBE403_MU_CNT : INTEGER;
C_PROBE404_MU_CNT : INTEGER;
C_PROBE405_MU_CNT : INTEGER;
C_PROBE406_MU_CNT : INTEGER;
C_PROBE407_MU_CNT : INTEGER;
C_PROBE408_MU_CNT : INTEGER;
C_PROBE409_MU_CNT : INTEGER;
C_PROBE410_MU_CNT : INTEGER;
C_PROBE411_MU_CNT : INTEGER;
C_PROBE412_MU_CNT : INTEGER;
C_PROBE413_MU_CNT : INTEGER;
C_PROBE414_MU_CNT : INTEGER;
C_PROBE415_MU_CNT : INTEGER;
C_PROBE416_MU_CNT : INTEGER;
C_PROBE417_MU_CNT : INTEGER;
C_PROBE418_MU_CNT : INTEGER;
C_PROBE419_MU_CNT : INTEGER;
C_PROBE420_MU_CNT : INTEGER;
C_PROBE421_MU_CNT : INTEGER;
C_PROBE422_MU_CNT : INTEGER;
C_PROBE423_MU_CNT : INTEGER;
C_PROBE424_MU_CNT : INTEGER;
C_PROBE425_MU_CNT : INTEGER;
C_PROBE426_MU_CNT : INTEGER;
C_PROBE427_MU_CNT : INTEGER;
C_PROBE428_MU_CNT : INTEGER;
C_PROBE429_MU_CNT : INTEGER;
C_PROBE430_MU_CNT : INTEGER;
C_PROBE431_MU_CNT : INTEGER;
C_PROBE432_MU_CNT : INTEGER;
C_PROBE433_MU_CNT : INTEGER;
C_PROBE434_MU_CNT : INTEGER;
C_PROBE435_MU_CNT : INTEGER;
C_PROBE436_MU_CNT : INTEGER;
C_PROBE437_MU_CNT : INTEGER;
C_PROBE438_MU_CNT : INTEGER;
C_PROBE439_MU_CNT : INTEGER;
C_PROBE440_MU_CNT : INTEGER;
C_PROBE441_MU_CNT : INTEGER;
C_PROBE442_MU_CNT : INTEGER;
C_PROBE443_MU_CNT : INTEGER;
C_PROBE444_MU_CNT : INTEGER;
C_PROBE445_MU_CNT : INTEGER;
C_PROBE446_MU_CNT : INTEGER;
C_PROBE447_MU_CNT : INTEGER;
C_PROBE448_MU_CNT : INTEGER;
C_PROBE449_MU_CNT : INTEGER;
C_PROBE450_MU_CNT : INTEGER;
C_PROBE451_MU_CNT : INTEGER;
C_PROBE452_MU_CNT : INTEGER;
C_PROBE453_MU_CNT : INTEGER;
C_PROBE454_MU_CNT : INTEGER;
C_PROBE455_MU_CNT : INTEGER;
C_PROBE456_MU_CNT : INTEGER;
C_PROBE457_MU_CNT : INTEGER;
C_PROBE458_MU_CNT : INTEGER;
C_PROBE459_MU_CNT : INTEGER;
C_PROBE460_MU_CNT : INTEGER;
C_PROBE461_MU_CNT : INTEGER;
C_PROBE462_MU_CNT : INTEGER;
C_PROBE463_MU_CNT : INTEGER;
C_PROBE464_MU_CNT : INTEGER;
C_PROBE465_MU_CNT : INTEGER;
C_PROBE466_MU_CNT : INTEGER;
C_PROBE467_MU_CNT : INTEGER;
C_PROBE468_MU_CNT : INTEGER;
C_PROBE469_MU_CNT : INTEGER;
C_PROBE470_MU_CNT : INTEGER;
C_PROBE471_MU_CNT : INTEGER;
C_PROBE472_MU_CNT : INTEGER;
C_PROBE473_MU_CNT : INTEGER;
C_PROBE474_MU_CNT : INTEGER;
C_PROBE475_MU_CNT : INTEGER;
C_PROBE476_MU_CNT : INTEGER;
C_PROBE477_MU_CNT : INTEGER;
C_PROBE478_MU_CNT : INTEGER;
C_PROBE479_MU_CNT : INTEGER;
C_PROBE480_MU_CNT : INTEGER;
C_PROBE481_MU_CNT : INTEGER;
C_PROBE482_MU_CNT : INTEGER;
C_PROBE483_MU_CNT : INTEGER;
C_PROBE484_MU_CNT : INTEGER;
C_PROBE485_MU_CNT : INTEGER;
C_PROBE486_MU_CNT : INTEGER;
C_PROBE487_MU_CNT : INTEGER;
C_PROBE488_MU_CNT : INTEGER;
C_PROBE489_MU_CNT : INTEGER;
C_PROBE490_MU_CNT : INTEGER;
C_PROBE491_MU_CNT : INTEGER;
C_PROBE492_MU_CNT : INTEGER;
C_PROBE493_MU_CNT : INTEGER;
C_PROBE494_MU_CNT : INTEGER;
C_PROBE495_MU_CNT : INTEGER;
C_PROBE496_MU_CNT : INTEGER;
C_PROBE497_MU_CNT : INTEGER;
C_PROBE498_MU_CNT : INTEGER;
C_PROBE499_MU_CNT : INTEGER;
C_PROBE500_MU_CNT : INTEGER;
C_PROBE501_MU_CNT : INTEGER;
C_PROBE502_MU_CNT : INTEGER;
C_PROBE503_MU_CNT : INTEGER;
C_PROBE504_MU_CNT : INTEGER;
C_PROBE505_MU_CNT : INTEGER;
C_PROBE506_MU_CNT : INTEGER;
C_PROBE507_MU_CNT : INTEGER;
C_PROBE508_MU_CNT : INTEGER;
C_PROBE509_MU_CNT : INTEGER;
C_PROBE510_MU_CNT : INTEGER;
C_PROBE511_MU_CNT : INTEGER;
C_PROBE512_MU_CNT : INTEGER;
C_PROBE513_MU_CNT : INTEGER;
C_PROBE514_MU_CNT : INTEGER;
C_PROBE515_MU_CNT : INTEGER;
C_PROBE516_MU_CNT : INTEGER;
C_PROBE517_MU_CNT : INTEGER;
C_PROBE518_MU_CNT : INTEGER;
C_PROBE519_MU_CNT : INTEGER;
C_PROBE520_MU_CNT : INTEGER;
C_PROBE521_MU_CNT : INTEGER;
C_PROBE522_MU_CNT : INTEGER;
C_PROBE523_MU_CNT : INTEGER;
C_PROBE524_MU_CNT : INTEGER;
C_PROBE525_MU_CNT : INTEGER;
C_PROBE526_MU_CNT : INTEGER;
C_PROBE527_MU_CNT : INTEGER;
C_PROBE528_MU_CNT : INTEGER;
C_PROBE529_MU_CNT : INTEGER;
C_PROBE530_MU_CNT : INTEGER;
C_PROBE531_MU_CNT : INTEGER;
C_PROBE532_MU_CNT : INTEGER;
C_PROBE533_MU_CNT : INTEGER;
C_PROBE534_MU_CNT : INTEGER;
C_PROBE535_MU_CNT : INTEGER;
C_PROBE536_MU_CNT : INTEGER;
C_PROBE537_MU_CNT : INTEGER;
C_PROBE538_MU_CNT : INTEGER;
C_PROBE539_MU_CNT : INTEGER;
C_PROBE540_MU_CNT : INTEGER;
C_PROBE541_MU_CNT : INTEGER;
C_PROBE542_MU_CNT : INTEGER;
C_PROBE543_MU_CNT : INTEGER;
C_PROBE544_MU_CNT : INTEGER;
C_PROBE545_MU_CNT : INTEGER;
C_PROBE546_MU_CNT : INTEGER;
C_PROBE547_MU_CNT : INTEGER;
C_PROBE548_MU_CNT : INTEGER;
C_PROBE549_MU_CNT : INTEGER;
C_PROBE550_MU_CNT : INTEGER;
C_PROBE551_MU_CNT : INTEGER;
C_PROBE552_MU_CNT : INTEGER;
C_PROBE553_MU_CNT : INTEGER;
C_PROBE554_MU_CNT : INTEGER;
C_PROBE555_MU_CNT : INTEGER;
C_PROBE556_MU_CNT : INTEGER;
C_PROBE557_MU_CNT : INTEGER;
C_PROBE558_MU_CNT : INTEGER;
C_PROBE559_MU_CNT : INTEGER;
C_PROBE560_MU_CNT : INTEGER;
C_PROBE561_MU_CNT : INTEGER;
C_PROBE562_MU_CNT : INTEGER;
C_PROBE563_MU_CNT : INTEGER;
C_PROBE564_MU_CNT : INTEGER;
C_PROBE565_MU_CNT : INTEGER;
C_PROBE566_MU_CNT : INTEGER;
C_PROBE567_MU_CNT : INTEGER;
C_PROBE568_MU_CNT : INTEGER;
C_PROBE569_MU_CNT : INTEGER;
C_PROBE570_MU_CNT : INTEGER;
C_PROBE571_MU_CNT : INTEGER;
C_PROBE572_MU_CNT : INTEGER;
C_PROBE573_MU_CNT : INTEGER;
C_PROBE574_MU_CNT : INTEGER;
C_PROBE575_MU_CNT : INTEGER;
C_PROBE576_MU_CNT : INTEGER;
C_PROBE577_MU_CNT : INTEGER;
C_PROBE578_MU_CNT : INTEGER;
C_PROBE579_MU_CNT : INTEGER;
C_PROBE580_MU_CNT : INTEGER;
C_PROBE581_MU_CNT : INTEGER;
C_PROBE582_MU_CNT : INTEGER;
C_PROBE583_MU_CNT : INTEGER;
C_PROBE584_MU_CNT : INTEGER;
C_PROBE585_MU_CNT : INTEGER;
C_PROBE586_MU_CNT : INTEGER;
C_PROBE587_MU_CNT : INTEGER;
C_PROBE588_MU_CNT : INTEGER;
C_PROBE589_MU_CNT : INTEGER;
C_PROBE590_MU_CNT : INTEGER;
C_PROBE591_MU_CNT : INTEGER;
C_PROBE592_MU_CNT : INTEGER;
C_PROBE593_MU_CNT : INTEGER;
C_PROBE594_MU_CNT : INTEGER;
C_PROBE595_MU_CNT : INTEGER;
C_PROBE596_MU_CNT : INTEGER;
C_PROBE597_MU_CNT : INTEGER;
C_PROBE598_MU_CNT : INTEGER;
C_PROBE599_MU_CNT : INTEGER;
C_PROBE600_MU_CNT : INTEGER;
C_PROBE601_MU_CNT : INTEGER;
C_PROBE602_MU_CNT : INTEGER;
C_PROBE603_MU_CNT : INTEGER;
C_PROBE604_MU_CNT : INTEGER;
C_PROBE605_MU_CNT : INTEGER;
C_PROBE606_MU_CNT : INTEGER;
C_PROBE607_MU_CNT : INTEGER;
C_PROBE608_MU_CNT : INTEGER;
C_PROBE609_MU_CNT : INTEGER;
C_PROBE610_MU_CNT : INTEGER;
C_PROBE611_MU_CNT : INTEGER;
C_PROBE612_MU_CNT : INTEGER;
C_PROBE613_MU_CNT : INTEGER;
C_PROBE614_MU_CNT : INTEGER;
C_PROBE615_MU_CNT : INTEGER;
C_PROBE616_MU_CNT : INTEGER;
C_PROBE617_MU_CNT : INTEGER;
C_PROBE618_MU_CNT : INTEGER;
C_PROBE619_MU_CNT : INTEGER;
C_PROBE620_MU_CNT : INTEGER;
C_PROBE621_MU_CNT : INTEGER;
C_PROBE622_MU_CNT : INTEGER;
C_PROBE623_MU_CNT : INTEGER;
C_PROBE624_MU_CNT : INTEGER;
C_PROBE625_MU_CNT : INTEGER;
C_PROBE626_MU_CNT : INTEGER;
C_PROBE627_MU_CNT : INTEGER;
C_PROBE628_MU_CNT : INTEGER;
C_PROBE629_MU_CNT : INTEGER;
C_PROBE630_MU_CNT : INTEGER;
C_PROBE631_MU_CNT : INTEGER;
C_PROBE632_MU_CNT : INTEGER;
C_PROBE633_MU_CNT : INTEGER;
C_PROBE634_MU_CNT : INTEGER;
C_PROBE635_MU_CNT : INTEGER;
C_PROBE636_MU_CNT : INTEGER;
C_PROBE637_MU_CNT : INTEGER;
C_PROBE638_MU_CNT : INTEGER;
C_PROBE639_MU_CNT : INTEGER;
C_PROBE640_MU_CNT : INTEGER;
C_PROBE641_MU_CNT : INTEGER;
C_PROBE642_MU_CNT : INTEGER;
C_PROBE643_MU_CNT : INTEGER;
C_PROBE644_MU_CNT : INTEGER;
C_PROBE645_MU_CNT : INTEGER;
C_PROBE646_MU_CNT : INTEGER;
C_PROBE647_MU_CNT : INTEGER;
C_PROBE648_MU_CNT : INTEGER;
C_PROBE649_MU_CNT : INTEGER;
C_PROBE650_MU_CNT : INTEGER;
C_PROBE651_MU_CNT : INTEGER;
C_PROBE652_MU_CNT : INTEGER;
C_PROBE653_MU_CNT : INTEGER;
C_PROBE654_MU_CNT : INTEGER;
C_PROBE655_MU_CNT : INTEGER;
C_PROBE656_MU_CNT : INTEGER;
C_PROBE657_MU_CNT : INTEGER;
C_PROBE658_MU_CNT : INTEGER;
C_PROBE659_MU_CNT : INTEGER;
C_PROBE660_MU_CNT : INTEGER;
C_PROBE661_MU_CNT : INTEGER;
C_PROBE662_MU_CNT : INTEGER;
C_PROBE663_MU_CNT : INTEGER;
C_PROBE664_MU_CNT : INTEGER;
C_PROBE665_MU_CNT : INTEGER;
C_PROBE666_MU_CNT : INTEGER;
C_PROBE667_MU_CNT : INTEGER;
C_PROBE668_MU_CNT : INTEGER;
C_PROBE669_MU_CNT : INTEGER;
C_PROBE670_MU_CNT : INTEGER;
C_PROBE671_MU_CNT : INTEGER;
C_PROBE672_MU_CNT : INTEGER;
C_PROBE673_MU_CNT : INTEGER;
C_PROBE674_MU_CNT : INTEGER;
C_PROBE675_MU_CNT : INTEGER;
C_PROBE676_MU_CNT : INTEGER;
C_PROBE677_MU_CNT : INTEGER;
C_PROBE678_MU_CNT : INTEGER;
C_PROBE679_MU_CNT : INTEGER;
C_PROBE680_MU_CNT : INTEGER;
C_PROBE681_MU_CNT : INTEGER;
C_PROBE682_MU_CNT : INTEGER;
C_PROBE683_MU_CNT : INTEGER;
C_PROBE684_MU_CNT : INTEGER;
C_PROBE685_MU_CNT : INTEGER;
C_PROBE686_MU_CNT : INTEGER;
C_PROBE687_MU_CNT : INTEGER;
C_PROBE688_MU_CNT : INTEGER;
C_PROBE689_MU_CNT : INTEGER;
C_PROBE690_MU_CNT : INTEGER;
C_PROBE691_MU_CNT : INTEGER;
C_PROBE692_MU_CNT : INTEGER;
C_PROBE693_MU_CNT : INTEGER;
C_PROBE694_MU_CNT : INTEGER;
C_PROBE695_MU_CNT : INTEGER;
C_PROBE696_MU_CNT : INTEGER;
C_PROBE697_MU_CNT : INTEGER;
C_PROBE698_MU_CNT : INTEGER;
C_PROBE699_MU_CNT : INTEGER;
C_PROBE700_MU_CNT : INTEGER;
C_PROBE701_MU_CNT : INTEGER;
C_PROBE702_MU_CNT : INTEGER;
C_PROBE703_MU_CNT : INTEGER;
C_PROBE704_MU_CNT : INTEGER;
C_PROBE705_MU_CNT : INTEGER;
C_PROBE706_MU_CNT : INTEGER;
C_PROBE707_MU_CNT : INTEGER;
C_PROBE708_MU_CNT : INTEGER;
C_PROBE709_MU_CNT : INTEGER;
C_PROBE710_MU_CNT : INTEGER;
C_PROBE711_MU_CNT : INTEGER;
C_PROBE712_MU_CNT : INTEGER;
C_PROBE713_MU_CNT : INTEGER;
C_PROBE714_MU_CNT : INTEGER;
C_PROBE715_MU_CNT : INTEGER;
C_PROBE716_MU_CNT : INTEGER;
C_PROBE717_MU_CNT : INTEGER;
C_PROBE718_MU_CNT : INTEGER;
C_PROBE719_MU_CNT : INTEGER;
C_PROBE720_MU_CNT : INTEGER;
C_PROBE721_MU_CNT : INTEGER;
C_PROBE722_MU_CNT : INTEGER;
C_PROBE723_MU_CNT : INTEGER;
C_PROBE724_MU_CNT : INTEGER;
C_PROBE725_MU_CNT : INTEGER;
C_PROBE726_MU_CNT : INTEGER;
C_PROBE727_MU_CNT : INTEGER;
C_PROBE728_MU_CNT : INTEGER;
C_PROBE729_MU_CNT : INTEGER;
C_PROBE730_MU_CNT : INTEGER;
C_PROBE731_MU_CNT : INTEGER;
C_PROBE732_MU_CNT : INTEGER;
C_PROBE733_MU_CNT : INTEGER;
C_PROBE734_MU_CNT : INTEGER;
C_PROBE735_MU_CNT : INTEGER;
C_PROBE736_MU_CNT : INTEGER;
C_PROBE737_MU_CNT : INTEGER;
C_PROBE738_MU_CNT : INTEGER;
C_PROBE739_MU_CNT : INTEGER;
C_PROBE740_MU_CNT : INTEGER;
C_PROBE741_MU_CNT : INTEGER;
C_PROBE742_MU_CNT : INTEGER;
C_PROBE743_MU_CNT : INTEGER;
C_PROBE744_MU_CNT : INTEGER;
C_PROBE745_MU_CNT : INTEGER;
C_PROBE746_MU_CNT : INTEGER;
C_PROBE747_MU_CNT : INTEGER;
C_PROBE748_MU_CNT : INTEGER;
C_PROBE749_MU_CNT : INTEGER;
C_PROBE750_MU_CNT : INTEGER;
C_PROBE751_MU_CNT : INTEGER;
C_PROBE752_MU_CNT : INTEGER;
C_PROBE753_MU_CNT : INTEGER;
C_PROBE754_MU_CNT : INTEGER;
C_PROBE755_MU_CNT : INTEGER;
C_PROBE756_MU_CNT : INTEGER;
C_PROBE757_MU_CNT : INTEGER;
C_PROBE758_MU_CNT : INTEGER;
C_PROBE759_MU_CNT : INTEGER;
C_PROBE760_MU_CNT : INTEGER;
C_PROBE761_MU_CNT : INTEGER;
C_PROBE762_MU_CNT : INTEGER;
C_PROBE763_MU_CNT : INTEGER;
C_PROBE764_MU_CNT : INTEGER;
C_PROBE765_MU_CNT : INTEGER;
C_PROBE766_MU_CNT : INTEGER;
C_PROBE767_MU_CNT : INTEGER;
C_PROBE768_MU_CNT : INTEGER;
C_PROBE769_MU_CNT : INTEGER;
C_PROBE770_MU_CNT : INTEGER;
C_PROBE771_MU_CNT : INTEGER;
C_PROBE772_MU_CNT : INTEGER;
C_PROBE773_MU_CNT : INTEGER;
C_PROBE774_MU_CNT : INTEGER;
C_PROBE775_MU_CNT : INTEGER;
C_PROBE776_MU_CNT : INTEGER;
C_PROBE777_MU_CNT : INTEGER;
C_PROBE778_MU_CNT : INTEGER;
C_PROBE779_MU_CNT : INTEGER;
C_PROBE780_MU_CNT : INTEGER;
C_PROBE781_MU_CNT : INTEGER;
C_PROBE782_MU_CNT : INTEGER;
C_PROBE783_MU_CNT : INTEGER;
C_PROBE784_MU_CNT : INTEGER;
C_PROBE785_MU_CNT : INTEGER;
C_PROBE786_MU_CNT : INTEGER;
C_PROBE787_MU_CNT : INTEGER;
C_PROBE788_MU_CNT : INTEGER;
C_PROBE789_MU_CNT : INTEGER;
C_PROBE790_MU_CNT : INTEGER;
C_PROBE791_MU_CNT : INTEGER;
C_PROBE792_MU_CNT : INTEGER;
C_PROBE793_MU_CNT : INTEGER;
C_PROBE794_MU_CNT : INTEGER;
C_PROBE795_MU_CNT : INTEGER;
C_PROBE796_MU_CNT : INTEGER;
C_PROBE797_MU_CNT : INTEGER;
C_PROBE798_MU_CNT : INTEGER;
C_PROBE799_MU_CNT : INTEGER;
C_PROBE800_MU_CNT : INTEGER;
C_PROBE801_MU_CNT : INTEGER;
C_PROBE802_MU_CNT : INTEGER;
C_PROBE803_MU_CNT : INTEGER;
C_PROBE804_MU_CNT : INTEGER;
C_PROBE805_MU_CNT : INTEGER;
C_PROBE806_MU_CNT : INTEGER;
C_PROBE807_MU_CNT : INTEGER;
C_PROBE808_MU_CNT : INTEGER;
C_PROBE809_MU_CNT : INTEGER;
C_PROBE810_MU_CNT : INTEGER;
C_PROBE811_MU_CNT : INTEGER;
C_PROBE812_MU_CNT : INTEGER;
C_PROBE813_MU_CNT : INTEGER;
C_PROBE814_MU_CNT : INTEGER;
C_PROBE815_MU_CNT : INTEGER;
C_PROBE816_MU_CNT : INTEGER;
C_PROBE817_MU_CNT : INTEGER;
C_PROBE818_MU_CNT : INTEGER;
C_PROBE819_MU_CNT : INTEGER;
C_PROBE820_MU_CNT : INTEGER;
C_PROBE821_MU_CNT : INTEGER;
C_PROBE822_MU_CNT : INTEGER;
C_PROBE823_MU_CNT : INTEGER;
C_PROBE824_MU_CNT : INTEGER;
C_PROBE825_MU_CNT : INTEGER;
C_PROBE826_MU_CNT : INTEGER;
C_PROBE827_MU_CNT : INTEGER;
C_PROBE828_MU_CNT : INTEGER;
C_PROBE829_MU_CNT : INTEGER;
C_PROBE830_MU_CNT : INTEGER;
C_PROBE831_MU_CNT : INTEGER;
C_PROBE832_MU_CNT : INTEGER;
C_PROBE833_MU_CNT : INTEGER;
C_PROBE834_MU_CNT : INTEGER;
C_PROBE835_MU_CNT : INTEGER;
C_PROBE836_MU_CNT : INTEGER;
C_PROBE837_MU_CNT : INTEGER;
C_PROBE838_MU_CNT : INTEGER;
C_PROBE839_MU_CNT : INTEGER;
C_PROBE840_MU_CNT : INTEGER;
C_PROBE841_MU_CNT : INTEGER;
C_PROBE842_MU_CNT : INTEGER;
C_PROBE843_MU_CNT : INTEGER;
C_PROBE844_MU_CNT : INTEGER;
C_PROBE845_MU_CNT : INTEGER;
C_PROBE846_MU_CNT : INTEGER;
C_PROBE847_MU_CNT : INTEGER;
C_PROBE848_MU_CNT : INTEGER;
C_PROBE849_MU_CNT : INTEGER;
C_PROBE850_MU_CNT : INTEGER;
C_PROBE851_MU_CNT : INTEGER;
C_PROBE852_MU_CNT : INTEGER;
C_PROBE853_MU_CNT : INTEGER;
C_PROBE854_MU_CNT : INTEGER;
C_PROBE855_MU_CNT : INTEGER;
C_PROBE856_MU_CNT : INTEGER;
C_PROBE857_MU_CNT : INTEGER;
C_PROBE858_MU_CNT : INTEGER;
C_PROBE859_MU_CNT : INTEGER;
C_PROBE860_MU_CNT : INTEGER;
C_PROBE861_MU_CNT : INTEGER;
C_PROBE862_MU_CNT : INTEGER;
C_PROBE863_MU_CNT : INTEGER;
C_PROBE864_MU_CNT : INTEGER;
C_PROBE865_MU_CNT : INTEGER;
C_PROBE866_MU_CNT : INTEGER;
C_PROBE867_MU_CNT : INTEGER;
C_PROBE868_MU_CNT : INTEGER;
C_PROBE869_MU_CNT : INTEGER;
C_PROBE870_MU_CNT : INTEGER;
C_PROBE871_MU_CNT : INTEGER;
C_PROBE872_MU_CNT : INTEGER;
C_PROBE873_MU_CNT : INTEGER;
C_PROBE874_MU_CNT : INTEGER;
C_PROBE875_MU_CNT : INTEGER;
C_PROBE876_MU_CNT : INTEGER;
C_PROBE877_MU_CNT : INTEGER;
C_PROBE878_MU_CNT : INTEGER;
C_PROBE879_MU_CNT : INTEGER;
C_PROBE880_MU_CNT : INTEGER;
C_PROBE881_MU_CNT : INTEGER;
C_PROBE882_MU_CNT : INTEGER;
C_PROBE883_MU_CNT : INTEGER;
C_PROBE884_MU_CNT : INTEGER;
C_PROBE885_MU_CNT : INTEGER;
C_PROBE886_MU_CNT : INTEGER;
C_PROBE887_MU_CNT : INTEGER;
C_PROBE888_MU_CNT : INTEGER;
C_PROBE889_MU_CNT : INTEGER;
C_PROBE890_MU_CNT : INTEGER;
C_PROBE891_MU_CNT : INTEGER;
C_PROBE892_MU_CNT : INTEGER;
C_PROBE893_MU_CNT : INTEGER;
C_PROBE894_MU_CNT : INTEGER;
C_PROBE895_MU_CNT : INTEGER;
C_PROBE896_MU_CNT : INTEGER;
C_PROBE897_MU_CNT : INTEGER;
C_PROBE898_MU_CNT : INTEGER;
C_PROBE899_MU_CNT : INTEGER;
C_PROBE900_MU_CNT : INTEGER;
C_PROBE901_MU_CNT : INTEGER;
C_PROBE902_MU_CNT : INTEGER;
C_PROBE903_MU_CNT : INTEGER;
C_PROBE904_MU_CNT : INTEGER;
C_PROBE905_MU_CNT : INTEGER;
C_PROBE906_MU_CNT : INTEGER;
C_PROBE907_MU_CNT : INTEGER;
C_PROBE908_MU_CNT : INTEGER;
C_PROBE909_MU_CNT : INTEGER;
C_PROBE910_MU_CNT : INTEGER;
C_PROBE911_MU_CNT : INTEGER;
C_PROBE912_MU_CNT : INTEGER;
C_PROBE913_MU_CNT : INTEGER;
C_PROBE914_MU_CNT : INTEGER;
C_PROBE915_MU_CNT : INTEGER;
C_PROBE916_MU_CNT : INTEGER;
C_PROBE917_MU_CNT : INTEGER;
C_PROBE918_MU_CNT : INTEGER;
C_PROBE919_MU_CNT : INTEGER;
C_PROBE920_MU_CNT : INTEGER;
C_PROBE921_MU_CNT : INTEGER;
C_PROBE922_MU_CNT : INTEGER;
C_PROBE923_MU_CNT : INTEGER;
C_PROBE924_MU_CNT : INTEGER;
C_PROBE925_MU_CNT : INTEGER;
C_PROBE926_MU_CNT : INTEGER;
C_PROBE927_MU_CNT : INTEGER;
C_PROBE928_MU_CNT : INTEGER;
C_PROBE929_MU_CNT : INTEGER;
C_PROBE930_MU_CNT : INTEGER;
C_PROBE931_MU_CNT : INTEGER;
C_PROBE932_MU_CNT : INTEGER;
C_PROBE933_MU_CNT : INTEGER;
C_PROBE934_MU_CNT : INTEGER;
C_PROBE935_MU_CNT : INTEGER;
C_PROBE936_MU_CNT : INTEGER;
C_PROBE937_MU_CNT : INTEGER;
C_PROBE938_MU_CNT : INTEGER;
C_PROBE939_MU_CNT : INTEGER;
C_PROBE940_MU_CNT : INTEGER;
C_PROBE941_MU_CNT : INTEGER;
C_PROBE942_MU_CNT : INTEGER;
C_PROBE943_MU_CNT : INTEGER;
C_PROBE944_MU_CNT : INTEGER;
C_PROBE945_MU_CNT : INTEGER;
C_PROBE946_MU_CNT : INTEGER;
C_PROBE947_MU_CNT : INTEGER;
C_PROBE948_MU_CNT : INTEGER;
C_PROBE949_MU_CNT : INTEGER;
C_PROBE950_MU_CNT : INTEGER;
C_PROBE951_MU_CNT : INTEGER;
C_PROBE952_MU_CNT : INTEGER;
C_PROBE953_MU_CNT : INTEGER;
C_PROBE954_MU_CNT : INTEGER;
C_PROBE955_MU_CNT : INTEGER;
C_PROBE956_MU_CNT : INTEGER;
C_PROBE957_MU_CNT : INTEGER;
C_PROBE958_MU_CNT : INTEGER;
C_PROBE959_MU_CNT : INTEGER;
C_PROBE960_MU_CNT : INTEGER;
C_PROBE961_MU_CNT : INTEGER;
C_PROBE962_MU_CNT : INTEGER;
C_PROBE963_MU_CNT : INTEGER;
C_PROBE964_MU_CNT : INTEGER;
C_PROBE965_MU_CNT : INTEGER;
C_PROBE966_MU_CNT : INTEGER;
C_PROBE967_MU_CNT : INTEGER;
C_PROBE968_MU_CNT : INTEGER;
C_PROBE969_MU_CNT : INTEGER;
C_PROBE970_MU_CNT : INTEGER;
C_PROBE971_MU_CNT : INTEGER;
C_PROBE972_MU_CNT : INTEGER;
C_PROBE973_MU_CNT : INTEGER;
C_PROBE974_MU_CNT : INTEGER;
C_PROBE975_MU_CNT : INTEGER;
C_PROBE976_MU_CNT : INTEGER;
C_PROBE977_MU_CNT : INTEGER;
C_PROBE978_MU_CNT : INTEGER;
C_PROBE979_MU_CNT : INTEGER;
C_PROBE980_MU_CNT : INTEGER;
C_PROBE981_MU_CNT : INTEGER;
C_PROBE982_MU_CNT : INTEGER;
C_PROBE983_MU_CNT : INTEGER;
C_PROBE984_MU_CNT : INTEGER;
C_PROBE985_MU_CNT : INTEGER;
C_PROBE986_MU_CNT : INTEGER;
C_PROBE987_MU_CNT : INTEGER;
C_PROBE988_MU_CNT : INTEGER;
C_PROBE989_MU_CNT : INTEGER;
C_PROBE990_MU_CNT : INTEGER;
C_PROBE991_MU_CNT : INTEGER;
C_PROBE992_MU_CNT : INTEGER;
C_PROBE993_MU_CNT : INTEGER;
C_PROBE994_MU_CNT : INTEGER;
C_PROBE995_MU_CNT : INTEGER;
C_PROBE996_MU_CNT : INTEGER;
C_PROBE997_MU_CNT : INTEGER;
C_PROBE998_MU_CNT : INTEGER;
C_PROBE999_MU_CNT : INTEGER;
C_PROBE1000_MU_CNT : INTEGER;
C_PROBE1001_MU_CNT : INTEGER;
C_PROBE1002_MU_CNT : INTEGER;
C_PROBE1003_MU_CNT : INTEGER;
C_PROBE1004_MU_CNT : INTEGER;
C_PROBE1005_MU_CNT : INTEGER;
C_PROBE1006_MU_CNT : INTEGER;
C_PROBE1007_MU_CNT : INTEGER;
C_PROBE1008_MU_CNT : INTEGER;
C_PROBE1009_MU_CNT : INTEGER;
C_PROBE1010_MU_CNT : INTEGER;
C_PROBE1011_MU_CNT : INTEGER;
C_PROBE1012_MU_CNT : INTEGER;
C_PROBE1013_MU_CNT : INTEGER;
C_PROBE1014_MU_CNT : INTEGER;
C_PROBE1015_MU_CNT : INTEGER;
C_PROBE1016_MU_CNT : INTEGER;
C_PROBE1017_MU_CNT : INTEGER;
C_PROBE1018_MU_CNT : INTEGER;
C_PROBE1019_MU_CNT : INTEGER;
C_PROBE1020_MU_CNT : INTEGER;
C_PROBE1021_MU_CNT : INTEGER;
C_PROBE1022_MU_CNT : INTEGER;
C_PROBE1023_MU_CNT : INTEGER;
C_PROBE0_TYPE : INTEGER;
C_PROBE1_TYPE : INTEGER;
C_PROBE2_TYPE : INTEGER;
C_PROBE3_TYPE : INTEGER;
C_PROBE4_TYPE : INTEGER;
C_PROBE5_TYPE : INTEGER;
C_PROBE6_TYPE : INTEGER;
C_PROBE7_TYPE : INTEGER;
C_PROBE8_TYPE : INTEGER;
C_PROBE9_TYPE : INTEGER;
C_PROBE10_TYPE : INTEGER;
C_PROBE11_TYPE : INTEGER;
C_PROBE12_TYPE : INTEGER;
C_PROBE13_TYPE : INTEGER;
C_PROBE14_TYPE : INTEGER;
C_PROBE15_TYPE : INTEGER;
C_PROBE16_TYPE : INTEGER;
C_PROBE17_TYPE : INTEGER;
C_PROBE18_TYPE : INTEGER;
C_PROBE19_TYPE : INTEGER;
C_PROBE20_TYPE : INTEGER;
C_PROBE21_TYPE : INTEGER;
C_PROBE22_TYPE : INTEGER;
C_PROBE23_TYPE : INTEGER;
C_PROBE24_TYPE : INTEGER;
C_PROBE25_TYPE : INTEGER;
C_PROBE26_TYPE : INTEGER;
C_PROBE27_TYPE : INTEGER;
C_PROBE28_TYPE : INTEGER;
C_PROBE29_TYPE : INTEGER;
C_PROBE30_TYPE : INTEGER;
C_PROBE31_TYPE : INTEGER;
C_PROBE32_TYPE : INTEGER;
C_PROBE33_TYPE : INTEGER;
C_PROBE34_TYPE : INTEGER;
C_PROBE35_TYPE : INTEGER;
C_PROBE36_TYPE : INTEGER;
C_PROBE37_TYPE : INTEGER;
C_PROBE38_TYPE : INTEGER;
C_PROBE39_TYPE : INTEGER;
C_PROBE40_TYPE : INTEGER;
C_PROBE41_TYPE : INTEGER;
C_PROBE42_TYPE : INTEGER;
C_PROBE43_TYPE : INTEGER;
C_PROBE44_TYPE : INTEGER;
C_PROBE45_TYPE : INTEGER;
C_PROBE46_TYPE : INTEGER;
C_PROBE47_TYPE : INTEGER;
C_PROBE48_TYPE : INTEGER;
C_PROBE49_TYPE : INTEGER;
C_PROBE50_TYPE : INTEGER;
C_PROBE51_TYPE : INTEGER;
C_PROBE52_TYPE : INTEGER;
C_PROBE53_TYPE : INTEGER;
C_PROBE54_TYPE : INTEGER;
C_PROBE55_TYPE : INTEGER;
C_PROBE56_TYPE : INTEGER;
C_PROBE57_TYPE : INTEGER;
C_PROBE58_TYPE : INTEGER;
C_PROBE59_TYPE : INTEGER;
C_PROBE60_TYPE : INTEGER;
C_PROBE61_TYPE : INTEGER;
C_PROBE62_TYPE : INTEGER;
C_PROBE63_TYPE : INTEGER;
C_PROBE64_TYPE : INTEGER;
C_PROBE65_TYPE : INTEGER;
C_PROBE66_TYPE : INTEGER;
C_PROBE67_TYPE : INTEGER;
C_PROBE68_TYPE : INTEGER;
C_PROBE69_TYPE : INTEGER;
C_PROBE70_TYPE : INTEGER;
C_PROBE71_TYPE : INTEGER;
C_PROBE72_TYPE : INTEGER;
C_PROBE73_TYPE : INTEGER;
C_PROBE74_TYPE : INTEGER;
C_PROBE75_TYPE : INTEGER;
C_PROBE76_TYPE : INTEGER;
C_PROBE77_TYPE : INTEGER;
C_PROBE78_TYPE : INTEGER;
C_PROBE79_TYPE : INTEGER;
C_PROBE80_TYPE : INTEGER;
C_PROBE81_TYPE : INTEGER;
C_PROBE82_TYPE : INTEGER;
C_PROBE83_TYPE : INTEGER;
C_PROBE84_TYPE : INTEGER;
C_PROBE85_TYPE : INTEGER;
C_PROBE86_TYPE : INTEGER;
C_PROBE87_TYPE : INTEGER;
C_PROBE88_TYPE : INTEGER;
C_PROBE89_TYPE : INTEGER;
C_PROBE90_TYPE : INTEGER;
C_PROBE91_TYPE : INTEGER;
C_PROBE92_TYPE : INTEGER;
C_PROBE93_TYPE : INTEGER;
C_PROBE94_TYPE : INTEGER;
C_PROBE95_TYPE : INTEGER;
C_PROBE96_TYPE : INTEGER;
C_PROBE97_TYPE : INTEGER;
C_PROBE98_TYPE : INTEGER;
C_PROBE99_TYPE : INTEGER;
C_PROBE100_TYPE : INTEGER;
C_PROBE101_TYPE : INTEGER;
C_PROBE102_TYPE : INTEGER;
C_PROBE103_TYPE : INTEGER;
C_PROBE104_TYPE : INTEGER;
C_PROBE105_TYPE : INTEGER;
C_PROBE106_TYPE : INTEGER;
C_PROBE107_TYPE : INTEGER;
C_PROBE108_TYPE : INTEGER;
C_PROBE109_TYPE : INTEGER;
C_PROBE110_TYPE : INTEGER;
C_PROBE111_TYPE : INTEGER;
C_PROBE112_TYPE : INTEGER;
C_PROBE113_TYPE : INTEGER;
C_PROBE114_TYPE : INTEGER;
C_PROBE115_TYPE : INTEGER;
C_PROBE116_TYPE : INTEGER;
C_PROBE117_TYPE : INTEGER;
C_PROBE118_TYPE : INTEGER;
C_PROBE119_TYPE : INTEGER;
C_PROBE120_TYPE : INTEGER;
C_PROBE121_TYPE : INTEGER;
C_PROBE122_TYPE : INTEGER;
C_PROBE123_TYPE : INTEGER;
C_PROBE124_TYPE : INTEGER;
C_PROBE125_TYPE : INTEGER;
C_PROBE126_TYPE : INTEGER;
C_PROBE127_TYPE : INTEGER;
C_PROBE128_TYPE : INTEGER;
C_PROBE129_TYPE : INTEGER;
C_PROBE130_TYPE : INTEGER;
C_PROBE131_TYPE : INTEGER;
C_PROBE132_TYPE : INTEGER;
C_PROBE133_TYPE : INTEGER;
C_PROBE134_TYPE : INTEGER;
C_PROBE135_TYPE : INTEGER;
C_PROBE136_TYPE : INTEGER;
C_PROBE137_TYPE : INTEGER;
C_PROBE138_TYPE : INTEGER;
C_PROBE139_TYPE : INTEGER;
C_PROBE140_TYPE : INTEGER;
C_PROBE141_TYPE : INTEGER;
C_PROBE142_TYPE : INTEGER;
C_PROBE143_TYPE : INTEGER;
C_PROBE144_TYPE : INTEGER;
C_PROBE145_TYPE : INTEGER;
C_PROBE146_TYPE : INTEGER;
C_PROBE147_TYPE : INTEGER;
C_PROBE148_TYPE : INTEGER;
C_PROBE149_TYPE : INTEGER;
C_PROBE150_TYPE : INTEGER;
C_PROBE151_TYPE : INTEGER;
C_PROBE152_TYPE : INTEGER;
C_PROBE153_TYPE : INTEGER;
C_PROBE154_TYPE : INTEGER;
C_PROBE155_TYPE : INTEGER;
C_PROBE156_TYPE : INTEGER;
C_PROBE157_TYPE : INTEGER;
C_PROBE158_TYPE : INTEGER;
C_PROBE159_TYPE : INTEGER;
C_PROBE160_TYPE : INTEGER;
C_PROBE161_TYPE : INTEGER;
C_PROBE162_TYPE : INTEGER;
C_PROBE163_TYPE : INTEGER;
C_PROBE164_TYPE : INTEGER;
C_PROBE165_TYPE : INTEGER;
C_PROBE166_TYPE : INTEGER;
C_PROBE167_TYPE : INTEGER;
C_PROBE168_TYPE : INTEGER;
C_PROBE169_TYPE : INTEGER;
C_PROBE170_TYPE : INTEGER;
C_PROBE171_TYPE : INTEGER;
C_PROBE172_TYPE : INTEGER;
C_PROBE173_TYPE : INTEGER;
C_PROBE174_TYPE : INTEGER;
C_PROBE175_TYPE : INTEGER;
C_PROBE176_TYPE : INTEGER;
C_PROBE177_TYPE : INTEGER;
C_PROBE178_TYPE : INTEGER;
C_PROBE179_TYPE : INTEGER;
C_PROBE180_TYPE : INTEGER;
C_PROBE181_TYPE : INTEGER;
C_PROBE182_TYPE : INTEGER;
C_PROBE183_TYPE : INTEGER;
C_PROBE184_TYPE : INTEGER;
C_PROBE185_TYPE : INTEGER;
C_PROBE186_TYPE : INTEGER;
C_PROBE187_TYPE : INTEGER;
C_PROBE188_TYPE : INTEGER;
C_PROBE189_TYPE : INTEGER;
C_PROBE190_TYPE : INTEGER;
C_PROBE191_TYPE : INTEGER;
C_PROBE192_TYPE : INTEGER;
C_PROBE193_TYPE : INTEGER;
C_PROBE194_TYPE : INTEGER;
C_PROBE195_TYPE : INTEGER;
C_PROBE196_TYPE : INTEGER;
C_PROBE197_TYPE : INTEGER;
C_PROBE198_TYPE : INTEGER;
C_PROBE199_TYPE : INTEGER;
C_PROBE200_TYPE : INTEGER;
C_PROBE201_TYPE : INTEGER;
C_PROBE202_TYPE : INTEGER;
C_PROBE203_TYPE : INTEGER;
C_PROBE204_TYPE : INTEGER;
C_PROBE205_TYPE : INTEGER;
C_PROBE206_TYPE : INTEGER;
C_PROBE207_TYPE : INTEGER;
C_PROBE208_TYPE : INTEGER;
C_PROBE209_TYPE : INTEGER;
C_PROBE210_TYPE : INTEGER;
C_PROBE211_TYPE : INTEGER;
C_PROBE212_TYPE : INTEGER;
C_PROBE213_TYPE : INTEGER;
C_PROBE214_TYPE : INTEGER;
C_PROBE215_TYPE : INTEGER;
C_PROBE216_TYPE : INTEGER;
C_PROBE217_TYPE : INTEGER;
C_PROBE218_TYPE : INTEGER;
C_PROBE219_TYPE : INTEGER;
C_PROBE220_TYPE : INTEGER;
C_PROBE221_TYPE : INTEGER;
C_PROBE222_TYPE : INTEGER;
C_PROBE223_TYPE : INTEGER;
C_PROBE224_TYPE : INTEGER;
C_PROBE225_TYPE : INTEGER;
C_PROBE226_TYPE : INTEGER;
C_PROBE227_TYPE : INTEGER;
C_PROBE228_TYPE : INTEGER;
C_PROBE229_TYPE : INTEGER;
C_PROBE230_TYPE : INTEGER;
C_PROBE231_TYPE : INTEGER;
C_PROBE232_TYPE : INTEGER;
C_PROBE233_TYPE : INTEGER;
C_PROBE234_TYPE : INTEGER;
C_PROBE235_TYPE : INTEGER;
C_PROBE236_TYPE : INTEGER;
C_PROBE237_TYPE : INTEGER;
C_PROBE238_TYPE : INTEGER;
C_PROBE239_TYPE : INTEGER;
C_PROBE240_TYPE : INTEGER;
C_PROBE241_TYPE : INTEGER;
C_PROBE242_TYPE : INTEGER;
C_PROBE243_TYPE : INTEGER;
C_PROBE244_TYPE : INTEGER;
C_PROBE245_TYPE : INTEGER;
C_PROBE246_TYPE : INTEGER;
C_PROBE247_TYPE : INTEGER;
C_PROBE248_TYPE : INTEGER;
C_PROBE249_TYPE : INTEGER;
C_PROBE250_TYPE : INTEGER;
C_PROBE251_TYPE : INTEGER;
C_PROBE252_TYPE : INTEGER;
C_PROBE253_TYPE : INTEGER;
C_PROBE254_TYPE : INTEGER;
C_PROBE255_TYPE : INTEGER;
C_PROBE256_TYPE : INTEGER;
C_PROBE257_TYPE : INTEGER;
C_PROBE258_TYPE : INTEGER;
C_PROBE259_TYPE : INTEGER;
C_PROBE260_TYPE : INTEGER;
C_PROBE261_TYPE : INTEGER;
C_PROBE262_TYPE : INTEGER;
C_PROBE263_TYPE : INTEGER;
C_PROBE264_TYPE : INTEGER;
C_PROBE265_TYPE : INTEGER;
C_PROBE266_TYPE : INTEGER;
C_PROBE267_TYPE : INTEGER;
C_PROBE268_TYPE : INTEGER;
C_PROBE269_TYPE : INTEGER;
C_PROBE270_TYPE : INTEGER;
C_PROBE271_TYPE : INTEGER;
C_PROBE272_TYPE : INTEGER;
C_PROBE273_TYPE : INTEGER;
C_PROBE274_TYPE : INTEGER;
C_PROBE275_TYPE : INTEGER;
C_PROBE276_TYPE : INTEGER;
C_PROBE277_TYPE : INTEGER;
C_PROBE278_TYPE : INTEGER;
C_PROBE279_TYPE : INTEGER;
C_PROBE280_TYPE : INTEGER;
C_PROBE281_TYPE : INTEGER;
C_PROBE282_TYPE : INTEGER;
C_PROBE283_TYPE : INTEGER;
C_PROBE284_TYPE : INTEGER;
C_PROBE285_TYPE : INTEGER;
C_PROBE286_TYPE : INTEGER;
C_PROBE287_TYPE : INTEGER;
C_PROBE288_TYPE : INTEGER;
C_PROBE289_TYPE : INTEGER;
C_PROBE290_TYPE : INTEGER;
C_PROBE291_TYPE : INTEGER;
C_PROBE292_TYPE : INTEGER;
C_PROBE293_TYPE : INTEGER;
C_PROBE294_TYPE : INTEGER;
C_PROBE295_TYPE : INTEGER;
C_PROBE296_TYPE : INTEGER;
C_PROBE297_TYPE : INTEGER;
C_PROBE298_TYPE : INTEGER;
C_PROBE299_TYPE : INTEGER;
C_PROBE300_TYPE : INTEGER;
C_PROBE301_TYPE : INTEGER;
C_PROBE302_TYPE : INTEGER;
C_PROBE303_TYPE : INTEGER;
C_PROBE304_TYPE : INTEGER;
C_PROBE305_TYPE : INTEGER;
C_PROBE306_TYPE : INTEGER;
C_PROBE307_TYPE : INTEGER;
C_PROBE308_TYPE : INTEGER;
C_PROBE309_TYPE : INTEGER;
C_PROBE310_TYPE : INTEGER;
C_PROBE311_TYPE : INTEGER;
C_PROBE312_TYPE : INTEGER;
C_PROBE313_TYPE : INTEGER;
C_PROBE314_TYPE : INTEGER;
C_PROBE315_TYPE : INTEGER;
C_PROBE316_TYPE : INTEGER;
C_PROBE317_TYPE : INTEGER;
C_PROBE318_TYPE : INTEGER;
C_PROBE319_TYPE : INTEGER;
C_PROBE320_TYPE : INTEGER;
C_PROBE321_TYPE : INTEGER;
C_PROBE322_TYPE : INTEGER;
C_PROBE323_TYPE : INTEGER;
C_PROBE324_TYPE : INTEGER;
C_PROBE325_TYPE : INTEGER;
C_PROBE326_TYPE : INTEGER;
C_PROBE327_TYPE : INTEGER;
C_PROBE328_TYPE : INTEGER;
C_PROBE329_TYPE : INTEGER;
C_PROBE330_TYPE : INTEGER;
C_PROBE331_TYPE : INTEGER;
C_PROBE332_TYPE : INTEGER;
C_PROBE333_TYPE : INTEGER;
C_PROBE334_TYPE : INTEGER;
C_PROBE335_TYPE : INTEGER;
C_PROBE336_TYPE : INTEGER;
C_PROBE337_TYPE : INTEGER;
C_PROBE338_TYPE : INTEGER;
C_PROBE339_TYPE : INTEGER;
C_PROBE340_TYPE : INTEGER;
C_PROBE341_TYPE : INTEGER;
C_PROBE342_TYPE : INTEGER;
C_PROBE343_TYPE : INTEGER;
C_PROBE344_TYPE : INTEGER;
C_PROBE345_TYPE : INTEGER;
C_PROBE346_TYPE : INTEGER;
C_PROBE347_TYPE : INTEGER;
C_PROBE348_TYPE : INTEGER;
C_PROBE349_TYPE : INTEGER;
C_PROBE350_TYPE : INTEGER;
C_PROBE351_TYPE : INTEGER;
C_PROBE352_TYPE : INTEGER;
C_PROBE353_TYPE : INTEGER;
C_PROBE354_TYPE : INTEGER;
C_PROBE355_TYPE : INTEGER;
C_PROBE356_TYPE : INTEGER;
C_PROBE357_TYPE : INTEGER;
C_PROBE358_TYPE : INTEGER;
C_PROBE359_TYPE : INTEGER;
C_PROBE360_TYPE : INTEGER;
C_PROBE361_TYPE : INTEGER;
C_PROBE362_TYPE : INTEGER;
C_PROBE363_TYPE : INTEGER;
C_PROBE364_TYPE : INTEGER;
C_PROBE365_TYPE : INTEGER;
C_PROBE366_TYPE : INTEGER;
C_PROBE367_TYPE : INTEGER;
C_PROBE368_TYPE : INTEGER;
C_PROBE369_TYPE : INTEGER;
C_PROBE370_TYPE : INTEGER;
C_PROBE371_TYPE : INTEGER;
C_PROBE372_TYPE : INTEGER;
C_PROBE373_TYPE : INTEGER;
C_PROBE374_TYPE : INTEGER;
C_PROBE375_TYPE : INTEGER;
C_PROBE376_TYPE : INTEGER;
C_PROBE377_TYPE : INTEGER;
C_PROBE378_TYPE : INTEGER;
C_PROBE379_TYPE : INTEGER;
C_PROBE380_TYPE : INTEGER;
C_PROBE381_TYPE : INTEGER;
C_PROBE382_TYPE : INTEGER;
C_PROBE383_TYPE : INTEGER;
C_PROBE384_TYPE : INTEGER;
C_PROBE385_TYPE : INTEGER;
C_PROBE386_TYPE : INTEGER;
C_PROBE387_TYPE : INTEGER;
C_PROBE388_TYPE : INTEGER;
C_PROBE389_TYPE : INTEGER;
C_PROBE390_TYPE : INTEGER;
C_PROBE391_TYPE : INTEGER;
C_PROBE392_TYPE : INTEGER;
C_PROBE393_TYPE : INTEGER;
C_PROBE394_TYPE : INTEGER;
C_PROBE395_TYPE : INTEGER;
C_PROBE396_TYPE : INTEGER;
C_PROBE397_TYPE : INTEGER;
C_PROBE398_TYPE : INTEGER;
C_PROBE399_TYPE : INTEGER;
C_PROBE400_TYPE : INTEGER;
C_PROBE401_TYPE : INTEGER;
C_PROBE402_TYPE : INTEGER;
C_PROBE403_TYPE : INTEGER;
C_PROBE404_TYPE : INTEGER;
C_PROBE405_TYPE : INTEGER;
C_PROBE406_TYPE : INTEGER;
C_PROBE407_TYPE : INTEGER;
C_PROBE408_TYPE : INTEGER;
C_PROBE409_TYPE : INTEGER;
C_PROBE410_TYPE : INTEGER;
C_PROBE411_TYPE : INTEGER;
C_PROBE412_TYPE : INTEGER;
C_PROBE413_TYPE : INTEGER;
C_PROBE414_TYPE : INTEGER;
C_PROBE415_TYPE : INTEGER;
C_PROBE416_TYPE : INTEGER;
C_PROBE417_TYPE : INTEGER;
C_PROBE418_TYPE : INTEGER;
C_PROBE419_TYPE : INTEGER;
C_PROBE420_TYPE : INTEGER;
C_PROBE421_TYPE : INTEGER;
C_PROBE422_TYPE : INTEGER;
C_PROBE423_TYPE : INTEGER;
C_PROBE424_TYPE : INTEGER;
C_PROBE425_TYPE : INTEGER;
C_PROBE426_TYPE : INTEGER;
C_PROBE427_TYPE : INTEGER;
C_PROBE428_TYPE : INTEGER;
C_PROBE429_TYPE : INTEGER;
C_PROBE430_TYPE : INTEGER;
C_PROBE431_TYPE : INTEGER;
C_PROBE432_TYPE : INTEGER;
C_PROBE433_TYPE : INTEGER;
C_PROBE434_TYPE : INTEGER;
C_PROBE435_TYPE : INTEGER;
C_PROBE436_TYPE : INTEGER;
C_PROBE437_TYPE : INTEGER;
C_PROBE438_TYPE : INTEGER;
C_PROBE439_TYPE : INTEGER;
C_PROBE440_TYPE : INTEGER;
C_PROBE441_TYPE : INTEGER;
C_PROBE442_TYPE : INTEGER;
C_PROBE443_TYPE : INTEGER;
C_PROBE444_TYPE : INTEGER;
C_PROBE445_TYPE : INTEGER;
C_PROBE446_TYPE : INTEGER;
C_PROBE447_TYPE : INTEGER;
C_PROBE448_TYPE : INTEGER;
C_PROBE449_TYPE : INTEGER;
C_PROBE450_TYPE : INTEGER;
C_PROBE451_TYPE : INTEGER;
C_PROBE452_TYPE : INTEGER;
C_PROBE453_TYPE : INTEGER;
C_PROBE454_TYPE : INTEGER;
C_PROBE455_TYPE : INTEGER;
C_PROBE456_TYPE : INTEGER;
C_PROBE457_TYPE : INTEGER;
C_PROBE458_TYPE : INTEGER;
C_PROBE459_TYPE : INTEGER;
C_PROBE460_TYPE : INTEGER;
C_PROBE461_TYPE : INTEGER;
C_PROBE462_TYPE : INTEGER;
C_PROBE463_TYPE : INTEGER;
C_PROBE464_TYPE : INTEGER;
C_PROBE465_TYPE : INTEGER;
C_PROBE466_TYPE : INTEGER;
C_PROBE467_TYPE : INTEGER;
C_PROBE468_TYPE : INTEGER;
C_PROBE469_TYPE : INTEGER;
C_PROBE470_TYPE : INTEGER;
C_PROBE471_TYPE : INTEGER;
C_PROBE472_TYPE : INTEGER;
C_PROBE473_TYPE : INTEGER;
C_PROBE474_TYPE : INTEGER;
C_PROBE475_TYPE : INTEGER;
C_PROBE476_TYPE : INTEGER;
C_PROBE477_TYPE : INTEGER;
C_PROBE478_TYPE : INTEGER;
C_PROBE479_TYPE : INTEGER;
C_PROBE480_TYPE : INTEGER;
C_PROBE481_TYPE : INTEGER;
C_PROBE482_TYPE : INTEGER;
C_PROBE483_TYPE : INTEGER;
C_PROBE484_TYPE : INTEGER;
C_PROBE485_TYPE : INTEGER;
C_PROBE486_TYPE : INTEGER;
C_PROBE487_TYPE : INTEGER;
C_PROBE488_TYPE : INTEGER;
C_PROBE489_TYPE : INTEGER;
C_PROBE490_TYPE : INTEGER;
C_PROBE491_TYPE : INTEGER;
C_PROBE492_TYPE : INTEGER;
C_PROBE493_TYPE : INTEGER;
C_PROBE494_TYPE : INTEGER;
C_PROBE495_TYPE : INTEGER;
C_PROBE496_TYPE : INTEGER;
C_PROBE497_TYPE : INTEGER;
C_PROBE498_TYPE : INTEGER;
C_PROBE499_TYPE : INTEGER;
C_PROBE500_TYPE : INTEGER;
C_PROBE501_TYPE : INTEGER;
C_PROBE502_TYPE : INTEGER;
C_PROBE503_TYPE : INTEGER;
C_PROBE504_TYPE : INTEGER;
C_PROBE505_TYPE : INTEGER;
C_PROBE506_TYPE : INTEGER;
C_PROBE507_TYPE : INTEGER;
C_PROBE508_TYPE : INTEGER;
C_PROBE509_TYPE : INTEGER;
C_PROBE510_TYPE : INTEGER;
C_PROBE511_TYPE : INTEGER;
C_PROBE512_TYPE : INTEGER;
C_PROBE513_TYPE : INTEGER;
C_PROBE514_TYPE : INTEGER;
C_PROBE515_TYPE : INTEGER;
C_PROBE516_TYPE : INTEGER;
C_PROBE517_TYPE : INTEGER;
C_PROBE518_TYPE : INTEGER;
C_PROBE519_TYPE : INTEGER;
C_PROBE520_TYPE : INTEGER;
C_PROBE521_TYPE : INTEGER;
C_PROBE522_TYPE : INTEGER;
C_PROBE523_TYPE : INTEGER;
C_PROBE524_TYPE : INTEGER;
C_PROBE525_TYPE : INTEGER;
C_PROBE526_TYPE : INTEGER;
C_PROBE527_TYPE : INTEGER;
C_PROBE528_TYPE : INTEGER;
C_PROBE529_TYPE : INTEGER;
C_PROBE530_TYPE : INTEGER;
C_PROBE531_TYPE : INTEGER;
C_PROBE532_TYPE : INTEGER;
C_PROBE533_TYPE : INTEGER;
C_PROBE534_TYPE : INTEGER;
C_PROBE535_TYPE : INTEGER;
C_PROBE536_TYPE : INTEGER;
C_PROBE537_TYPE : INTEGER;
C_PROBE538_TYPE : INTEGER;
C_PROBE539_TYPE : INTEGER;
C_PROBE540_TYPE : INTEGER;
C_PROBE541_TYPE : INTEGER;
C_PROBE542_TYPE : INTEGER;
C_PROBE543_TYPE : INTEGER;
C_PROBE544_TYPE : INTEGER;
C_PROBE545_TYPE : INTEGER;
C_PROBE546_TYPE : INTEGER;
C_PROBE547_TYPE : INTEGER;
C_PROBE548_TYPE : INTEGER;
C_PROBE549_TYPE : INTEGER;
C_PROBE550_TYPE : INTEGER;
C_PROBE551_TYPE : INTEGER;
C_PROBE552_TYPE : INTEGER;
C_PROBE553_TYPE : INTEGER;
C_PROBE554_TYPE : INTEGER;
C_PROBE555_TYPE : INTEGER;
C_PROBE556_TYPE : INTEGER;
C_PROBE557_TYPE : INTEGER;
C_PROBE558_TYPE : INTEGER;
C_PROBE559_TYPE : INTEGER;
C_PROBE560_TYPE : INTEGER;
C_PROBE561_TYPE : INTEGER;
C_PROBE562_TYPE : INTEGER;
C_PROBE563_TYPE : INTEGER;
C_PROBE564_TYPE : INTEGER;
C_PROBE565_TYPE : INTEGER;
C_PROBE566_TYPE : INTEGER;
C_PROBE567_TYPE : INTEGER;
C_PROBE568_TYPE : INTEGER;
C_PROBE569_TYPE : INTEGER;
C_PROBE570_TYPE : INTEGER;
C_PROBE571_TYPE : INTEGER;
C_PROBE572_TYPE : INTEGER;
C_PROBE573_TYPE : INTEGER;
C_PROBE574_TYPE : INTEGER;
C_PROBE575_TYPE : INTEGER;
C_PROBE576_TYPE : INTEGER;
C_PROBE577_TYPE : INTEGER;
C_PROBE578_TYPE : INTEGER;
C_PROBE579_TYPE : INTEGER;
C_PROBE580_TYPE : INTEGER;
C_PROBE581_TYPE : INTEGER;
C_PROBE582_TYPE : INTEGER;
C_PROBE583_TYPE : INTEGER;
C_PROBE584_TYPE : INTEGER;
C_PROBE585_TYPE : INTEGER;
C_PROBE586_TYPE : INTEGER;
C_PROBE587_TYPE : INTEGER;
C_PROBE588_TYPE : INTEGER;
C_PROBE589_TYPE : INTEGER;
C_PROBE590_TYPE : INTEGER;
C_PROBE591_TYPE : INTEGER;
C_PROBE592_TYPE : INTEGER;
C_PROBE593_TYPE : INTEGER;
C_PROBE594_TYPE : INTEGER;
C_PROBE595_TYPE : INTEGER;
C_PROBE596_TYPE : INTEGER;
C_PROBE597_TYPE : INTEGER;
C_PROBE598_TYPE : INTEGER;
C_PROBE599_TYPE : INTEGER;
C_PROBE600_TYPE : INTEGER;
C_PROBE601_TYPE : INTEGER;
C_PROBE602_TYPE : INTEGER;
C_PROBE603_TYPE : INTEGER;
C_PROBE604_TYPE : INTEGER;
C_PROBE605_TYPE : INTEGER;
C_PROBE606_TYPE : INTEGER;
C_PROBE607_TYPE : INTEGER;
C_PROBE608_TYPE : INTEGER;
C_PROBE609_TYPE : INTEGER;
C_PROBE610_TYPE : INTEGER;
C_PROBE611_TYPE : INTEGER;
C_PROBE612_TYPE : INTEGER;
C_PROBE613_TYPE : INTEGER;
C_PROBE614_TYPE : INTEGER;
C_PROBE615_TYPE : INTEGER;
C_PROBE616_TYPE : INTEGER;
C_PROBE617_TYPE : INTEGER;
C_PROBE618_TYPE : INTEGER;
C_PROBE619_TYPE : INTEGER;
C_PROBE620_TYPE : INTEGER;
C_PROBE621_TYPE : INTEGER;
C_PROBE622_TYPE : INTEGER;
C_PROBE623_TYPE : INTEGER;
C_PROBE624_TYPE : INTEGER;
C_PROBE625_TYPE : INTEGER;
C_PROBE626_TYPE : INTEGER;
C_PROBE627_TYPE : INTEGER;
C_PROBE628_TYPE : INTEGER;
C_PROBE629_TYPE : INTEGER;
C_PROBE630_TYPE : INTEGER;
C_PROBE631_TYPE : INTEGER;
C_PROBE632_TYPE : INTEGER;
C_PROBE633_TYPE : INTEGER;
C_PROBE634_TYPE : INTEGER;
C_PROBE635_TYPE : INTEGER;
C_PROBE636_TYPE : INTEGER;
C_PROBE637_TYPE : INTEGER;
C_PROBE638_TYPE : INTEGER;
C_PROBE639_TYPE : INTEGER;
C_PROBE640_TYPE : INTEGER;
C_PROBE641_TYPE : INTEGER;
C_PROBE642_TYPE : INTEGER;
C_PROBE643_TYPE : INTEGER;
C_PROBE644_TYPE : INTEGER;
C_PROBE645_TYPE : INTEGER;
C_PROBE646_TYPE : INTEGER;
C_PROBE647_TYPE : INTEGER;
C_PROBE648_TYPE : INTEGER;
C_PROBE649_TYPE : INTEGER;
C_PROBE650_TYPE : INTEGER;
C_PROBE651_TYPE : INTEGER;
C_PROBE652_TYPE : INTEGER;
C_PROBE653_TYPE : INTEGER;
C_PROBE654_TYPE : INTEGER;
C_PROBE655_TYPE : INTEGER;
C_PROBE656_TYPE : INTEGER;
C_PROBE657_TYPE : INTEGER;
C_PROBE658_TYPE : INTEGER;
C_PROBE659_TYPE : INTEGER;
C_PROBE660_TYPE : INTEGER;
C_PROBE661_TYPE : INTEGER;
C_PROBE662_TYPE : INTEGER;
C_PROBE663_TYPE : INTEGER;
C_PROBE664_TYPE : INTEGER;
C_PROBE665_TYPE : INTEGER;
C_PROBE666_TYPE : INTEGER;
C_PROBE667_TYPE : INTEGER;
C_PROBE668_TYPE : INTEGER;
C_PROBE669_TYPE : INTEGER;
C_PROBE670_TYPE : INTEGER;
C_PROBE671_TYPE : INTEGER;
C_PROBE672_TYPE : INTEGER;
C_PROBE673_TYPE : INTEGER;
C_PROBE674_TYPE : INTEGER;
C_PROBE675_TYPE : INTEGER;
C_PROBE676_TYPE : INTEGER;
C_PROBE677_TYPE : INTEGER;
C_PROBE678_TYPE : INTEGER;
C_PROBE679_TYPE : INTEGER;
C_PROBE680_TYPE : INTEGER;
C_PROBE681_TYPE : INTEGER;
C_PROBE682_TYPE : INTEGER;
C_PROBE683_TYPE : INTEGER;
C_PROBE684_TYPE : INTEGER;
C_PROBE685_TYPE : INTEGER;
C_PROBE686_TYPE : INTEGER;
C_PROBE687_TYPE : INTEGER;
C_PROBE688_TYPE : INTEGER;
C_PROBE689_TYPE : INTEGER;
C_PROBE690_TYPE : INTEGER;
C_PROBE691_TYPE : INTEGER;
C_PROBE692_TYPE : INTEGER;
C_PROBE693_TYPE : INTEGER;
C_PROBE694_TYPE : INTEGER;
C_PROBE695_TYPE : INTEGER;
C_PROBE696_TYPE : INTEGER;
C_PROBE697_TYPE : INTEGER;
C_PROBE698_TYPE : INTEGER;
C_PROBE699_TYPE : INTEGER;
C_PROBE700_TYPE : INTEGER;
C_PROBE701_TYPE : INTEGER;
C_PROBE702_TYPE : INTEGER;
C_PROBE703_TYPE : INTEGER;
C_PROBE704_TYPE : INTEGER;
C_PROBE705_TYPE : INTEGER;
C_PROBE706_TYPE : INTEGER;
C_PROBE707_TYPE : INTEGER;
C_PROBE708_TYPE : INTEGER;
C_PROBE709_TYPE : INTEGER;
C_PROBE710_TYPE : INTEGER;
C_PROBE711_TYPE : INTEGER;
C_PROBE712_TYPE : INTEGER;
C_PROBE713_TYPE : INTEGER;
C_PROBE714_TYPE : INTEGER;
C_PROBE715_TYPE : INTEGER;
C_PROBE716_TYPE : INTEGER;
C_PROBE717_TYPE : INTEGER;
C_PROBE718_TYPE : INTEGER;
C_PROBE719_TYPE : INTEGER;
C_PROBE720_TYPE : INTEGER;
C_PROBE721_TYPE : INTEGER;
C_PROBE722_TYPE : INTEGER;
C_PROBE723_TYPE : INTEGER;
C_PROBE724_TYPE : INTEGER;
C_PROBE725_TYPE : INTEGER;
C_PROBE726_TYPE : INTEGER;
C_PROBE727_TYPE : INTEGER;
C_PROBE728_TYPE : INTEGER;
C_PROBE729_TYPE : INTEGER;
C_PROBE730_TYPE : INTEGER;
C_PROBE731_TYPE : INTEGER;
C_PROBE732_TYPE : INTEGER;
C_PROBE733_TYPE : INTEGER;
C_PROBE734_TYPE : INTEGER;
C_PROBE735_TYPE : INTEGER;
C_PROBE736_TYPE : INTEGER;
C_PROBE737_TYPE : INTEGER;
C_PROBE738_TYPE : INTEGER;
C_PROBE739_TYPE : INTEGER;
C_PROBE740_TYPE : INTEGER;
C_PROBE741_TYPE : INTEGER;
C_PROBE742_TYPE : INTEGER;
C_PROBE743_TYPE : INTEGER;
C_PROBE744_TYPE : INTEGER;
C_PROBE745_TYPE : INTEGER;
C_PROBE746_TYPE : INTEGER;
C_PROBE747_TYPE : INTEGER;
C_PROBE748_TYPE : INTEGER;
C_PROBE749_TYPE : INTEGER;
C_PROBE750_TYPE : INTEGER;
C_PROBE751_TYPE : INTEGER;
C_PROBE752_TYPE : INTEGER;
C_PROBE753_TYPE : INTEGER;
C_PROBE754_TYPE : INTEGER;
C_PROBE755_TYPE : INTEGER;
C_PROBE756_TYPE : INTEGER;
C_PROBE757_TYPE : INTEGER;
C_PROBE758_TYPE : INTEGER;
C_PROBE759_TYPE : INTEGER;
C_PROBE760_TYPE : INTEGER;
C_PROBE761_TYPE : INTEGER;
C_PROBE762_TYPE : INTEGER;
C_PROBE763_TYPE : INTEGER;
C_PROBE764_TYPE : INTEGER;
C_PROBE765_TYPE : INTEGER;
C_PROBE766_TYPE : INTEGER;
C_PROBE767_TYPE : INTEGER;
C_PROBE768_TYPE : INTEGER;
C_PROBE769_TYPE : INTEGER;
C_PROBE770_TYPE : INTEGER;
C_PROBE771_TYPE : INTEGER;
C_PROBE772_TYPE : INTEGER;
C_PROBE773_TYPE : INTEGER;
C_PROBE774_TYPE : INTEGER;
C_PROBE775_TYPE : INTEGER;
C_PROBE776_TYPE : INTEGER;
C_PROBE777_TYPE : INTEGER;
C_PROBE778_TYPE : INTEGER;
C_PROBE779_TYPE : INTEGER;
C_PROBE780_TYPE : INTEGER;
C_PROBE781_TYPE : INTEGER;
C_PROBE782_TYPE : INTEGER;
C_PROBE783_TYPE : INTEGER;
C_PROBE784_TYPE : INTEGER;
C_PROBE785_TYPE : INTEGER;
C_PROBE786_TYPE : INTEGER;
C_PROBE787_TYPE : INTEGER;
C_PROBE788_TYPE : INTEGER;
C_PROBE789_TYPE : INTEGER;
C_PROBE790_TYPE : INTEGER;
C_PROBE791_TYPE : INTEGER;
C_PROBE792_TYPE : INTEGER;
C_PROBE793_TYPE : INTEGER;
C_PROBE794_TYPE : INTEGER;
C_PROBE795_TYPE : INTEGER;
C_PROBE796_TYPE : INTEGER;
C_PROBE797_TYPE : INTEGER;
C_PROBE798_TYPE : INTEGER;
C_PROBE799_TYPE : INTEGER;
C_PROBE800_TYPE : INTEGER;
C_PROBE801_TYPE : INTEGER;
C_PROBE802_TYPE : INTEGER;
C_PROBE803_TYPE : INTEGER;
C_PROBE804_TYPE : INTEGER;
C_PROBE805_TYPE : INTEGER;
C_PROBE806_TYPE : INTEGER;
C_PROBE807_TYPE : INTEGER;
C_PROBE808_TYPE : INTEGER;
C_PROBE809_TYPE : INTEGER;
C_PROBE810_TYPE : INTEGER;
C_PROBE811_TYPE : INTEGER;
C_PROBE812_TYPE : INTEGER;
C_PROBE813_TYPE : INTEGER;
C_PROBE814_TYPE : INTEGER;
C_PROBE815_TYPE : INTEGER;
C_PROBE816_TYPE : INTEGER;
C_PROBE817_TYPE : INTEGER;
C_PROBE818_TYPE : INTEGER;
C_PROBE819_TYPE : INTEGER;
C_PROBE820_TYPE : INTEGER;
C_PROBE821_TYPE : INTEGER;
C_PROBE822_TYPE : INTEGER;
C_PROBE823_TYPE : INTEGER;
C_PROBE824_TYPE : INTEGER;
C_PROBE825_TYPE : INTEGER;
C_PROBE826_TYPE : INTEGER;
C_PROBE827_TYPE : INTEGER;
C_PROBE828_TYPE : INTEGER;
C_PROBE829_TYPE : INTEGER;
C_PROBE830_TYPE : INTEGER;
C_PROBE831_TYPE : INTEGER;
C_PROBE832_TYPE : INTEGER;
C_PROBE833_TYPE : INTEGER;
C_PROBE834_TYPE : INTEGER;
C_PROBE835_TYPE : INTEGER;
C_PROBE836_TYPE : INTEGER;
C_PROBE837_TYPE : INTEGER;
C_PROBE838_TYPE : INTEGER;
C_PROBE839_TYPE : INTEGER;
C_PROBE840_TYPE : INTEGER;
C_PROBE841_TYPE : INTEGER;
C_PROBE842_TYPE : INTEGER;
C_PROBE843_TYPE : INTEGER;
C_PROBE844_TYPE : INTEGER;
C_PROBE845_TYPE : INTEGER;
C_PROBE846_TYPE : INTEGER;
C_PROBE847_TYPE : INTEGER;
C_PROBE848_TYPE : INTEGER;
C_PROBE849_TYPE : INTEGER;
C_PROBE850_TYPE : INTEGER;
C_PROBE851_TYPE : INTEGER;
C_PROBE852_TYPE : INTEGER;
C_PROBE853_TYPE : INTEGER;
C_PROBE854_TYPE : INTEGER;
C_PROBE855_TYPE : INTEGER;
C_PROBE856_TYPE : INTEGER;
C_PROBE857_TYPE : INTEGER;
C_PROBE858_TYPE : INTEGER;
C_PROBE859_TYPE : INTEGER;
C_PROBE860_TYPE : INTEGER;
C_PROBE861_TYPE : INTEGER;
C_PROBE862_TYPE : INTEGER;
C_PROBE863_TYPE : INTEGER;
C_PROBE864_TYPE : INTEGER;
C_PROBE865_TYPE : INTEGER;
C_PROBE866_TYPE : INTEGER;
C_PROBE867_TYPE : INTEGER;
C_PROBE868_TYPE : INTEGER;
C_PROBE869_TYPE : INTEGER;
C_PROBE870_TYPE : INTEGER;
C_PROBE871_TYPE : INTEGER;
C_PROBE872_TYPE : INTEGER;
C_PROBE873_TYPE : INTEGER;
C_PROBE874_TYPE : INTEGER;
C_PROBE875_TYPE : INTEGER;
C_PROBE876_TYPE : INTEGER;
C_PROBE877_TYPE : INTEGER;
C_PROBE878_TYPE : INTEGER;
C_PROBE879_TYPE : INTEGER;
C_PROBE880_TYPE : INTEGER;
C_PROBE881_TYPE : INTEGER;
C_PROBE882_TYPE : INTEGER;
C_PROBE883_TYPE : INTEGER;
C_PROBE884_TYPE : INTEGER;
C_PROBE885_TYPE : INTEGER;
C_PROBE886_TYPE : INTEGER;
C_PROBE887_TYPE : INTEGER;
C_PROBE888_TYPE : INTEGER;
C_PROBE889_TYPE : INTEGER;
C_PROBE890_TYPE : INTEGER;
C_PROBE891_TYPE : INTEGER;
C_PROBE892_TYPE : INTEGER;
C_PROBE893_TYPE : INTEGER;
C_PROBE894_TYPE : INTEGER;
C_PROBE895_TYPE : INTEGER;
C_PROBE896_TYPE : INTEGER;
C_PROBE897_TYPE : INTEGER;
C_PROBE898_TYPE : INTEGER;
C_PROBE899_TYPE : INTEGER;
C_PROBE900_TYPE : INTEGER;
C_PROBE901_TYPE : INTEGER;
C_PROBE902_TYPE : INTEGER;
C_PROBE903_TYPE : INTEGER;
C_PROBE904_TYPE : INTEGER;
C_PROBE905_TYPE : INTEGER;
C_PROBE906_TYPE : INTEGER;
C_PROBE907_TYPE : INTEGER;
C_PROBE908_TYPE : INTEGER;
C_PROBE909_TYPE : INTEGER;
C_PROBE910_TYPE : INTEGER;
C_PROBE911_TYPE : INTEGER;
C_PROBE912_TYPE : INTEGER;
C_PROBE913_TYPE : INTEGER;
C_PROBE914_TYPE : INTEGER;
C_PROBE915_TYPE : INTEGER;
C_PROBE916_TYPE : INTEGER;
C_PROBE917_TYPE : INTEGER;
C_PROBE918_TYPE : INTEGER;
C_PROBE919_TYPE : INTEGER;
C_PROBE920_TYPE : INTEGER;
C_PROBE921_TYPE : INTEGER;
C_PROBE922_TYPE : INTEGER;
C_PROBE923_TYPE : INTEGER;
C_PROBE924_TYPE : INTEGER;
C_PROBE925_TYPE : INTEGER;
C_PROBE926_TYPE : INTEGER;
C_PROBE927_TYPE : INTEGER;
C_PROBE928_TYPE : INTEGER;
C_PROBE929_TYPE : INTEGER;
C_PROBE930_TYPE : INTEGER;
C_PROBE931_TYPE : INTEGER;
C_PROBE932_TYPE : INTEGER;
C_PROBE933_TYPE : INTEGER;
C_PROBE934_TYPE : INTEGER;
C_PROBE935_TYPE : INTEGER;
C_PROBE936_TYPE : INTEGER;
C_PROBE937_TYPE : INTEGER;
C_PROBE938_TYPE : INTEGER;
C_PROBE939_TYPE : INTEGER;
C_PROBE940_TYPE : INTEGER;
C_PROBE941_TYPE : INTEGER;
C_PROBE942_TYPE : INTEGER;
C_PROBE943_TYPE : INTEGER;
C_PROBE944_TYPE : INTEGER;
C_PROBE945_TYPE : INTEGER;
C_PROBE946_TYPE : INTEGER;
C_PROBE947_TYPE : INTEGER;
C_PROBE948_TYPE : INTEGER;
C_PROBE949_TYPE : INTEGER;
C_PROBE950_TYPE : INTEGER;
C_PROBE951_TYPE : INTEGER;
C_PROBE952_TYPE : INTEGER;
C_PROBE953_TYPE : INTEGER;
C_PROBE954_TYPE : INTEGER;
C_PROBE955_TYPE : INTEGER;
C_PROBE956_TYPE : INTEGER;
C_PROBE957_TYPE : INTEGER;
C_PROBE958_TYPE : INTEGER;
C_PROBE959_TYPE : INTEGER;
C_PROBE960_TYPE : INTEGER;
C_PROBE961_TYPE : INTEGER;
C_PROBE962_TYPE : INTEGER;
C_PROBE963_TYPE : INTEGER;
C_PROBE964_TYPE : INTEGER;
C_PROBE965_TYPE : INTEGER;
C_PROBE966_TYPE : INTEGER;
C_PROBE967_TYPE : INTEGER;
C_PROBE968_TYPE : INTEGER;
C_PROBE969_TYPE : INTEGER;
C_PROBE970_TYPE : INTEGER;
C_PROBE971_TYPE : INTEGER;
C_PROBE972_TYPE : INTEGER;
C_PROBE973_TYPE : INTEGER;
C_PROBE974_TYPE : INTEGER;
C_PROBE975_TYPE : INTEGER;
C_PROBE976_TYPE : INTEGER;
C_PROBE977_TYPE : INTEGER;
C_PROBE978_TYPE : INTEGER;
C_PROBE979_TYPE : INTEGER;
C_PROBE980_TYPE : INTEGER;
C_PROBE981_TYPE : INTEGER;
C_PROBE982_TYPE : INTEGER;
C_PROBE983_TYPE : INTEGER;
C_PROBE984_TYPE : INTEGER;
C_PROBE985_TYPE : INTEGER;
C_PROBE986_TYPE : INTEGER;
C_PROBE987_TYPE : INTEGER;
C_PROBE988_TYPE : INTEGER;
C_PROBE989_TYPE : INTEGER;
C_PROBE990_TYPE : INTEGER;
C_PROBE991_TYPE : INTEGER;
C_PROBE992_TYPE : INTEGER;
C_PROBE993_TYPE : INTEGER;
C_PROBE994_TYPE : INTEGER;
C_PROBE995_TYPE : INTEGER;
C_PROBE996_TYPE : INTEGER;
C_PROBE997_TYPE : INTEGER;
C_PROBE998_TYPE : INTEGER;
C_PROBE999_TYPE : INTEGER;
C_PROBE1000_TYPE : INTEGER;
C_PROBE1001_TYPE : INTEGER;
C_PROBE1002_TYPE : INTEGER;
C_PROBE1003_TYPE : INTEGER;
C_PROBE1004_TYPE : INTEGER;
C_PROBE1005_TYPE : INTEGER;
C_PROBE1006_TYPE : INTEGER;
C_PROBE1007_TYPE : INTEGER;
C_PROBE1008_TYPE : INTEGER;
C_PROBE1009_TYPE : INTEGER;
C_PROBE1010_TYPE : INTEGER;
C_PROBE1011_TYPE : INTEGER;
C_PROBE1012_TYPE : INTEGER;
C_PROBE1013_TYPE : INTEGER;
C_PROBE1014_TYPE : INTEGER;
C_PROBE1015_TYPE : INTEGER;
C_PROBE1016_TYPE : INTEGER;
C_PROBE1017_TYPE : INTEGER;
C_PROBE1018_TYPE : INTEGER;
C_PROBE1019_TYPE : INTEGER;
C_PROBE1020_TYPE : INTEGER;
C_PROBE1021_TYPE : INTEGER;
C_PROBE1022_TYPE : INTEGER;
C_PROBE1023_TYPE : INTEGER
);
PORT (
clk : IN STD_LOGIC;
sl_iport0 : IN STD_LOGIC_VECTOR (36 downto 0);
sl_oport0 : OUT STD_LOGIC_VECTOR (16 downto 0);
trig_in : IN STD_LOGIC;
trig_in_ack : OUT STD_LOGIC;
trig_out : OUT STD_LOGIC;
trig_out_ack : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe32 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe33 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe34 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe35 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe38 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe39 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe41 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe42 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe45 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe46 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe47 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe48 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe49 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe50 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe51 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe52 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe53 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe54 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe55 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe56 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe57 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe58 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe59 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe60 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe61 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe62 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe63 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe64 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe65 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe66 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe67 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe68 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe69 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe70 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe71 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe72 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe73 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe74 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe75 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe76 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe77 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe78 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe79 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe80 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe81 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe82 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe83 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe84 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe85 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe86 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe87 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe88 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe89 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe90 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe91 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe92 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe93 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe94 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe95 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe96 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe97 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe98 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe99 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe100 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe101 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe102 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe103 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe104 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe105 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe106 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe107 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe108 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe109 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe110 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe111 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe112 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe113 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe114 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe115 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe116 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe117 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe118 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe119 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe120 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe121 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe122 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe123 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe124 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe125 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe126 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe127 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe128 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe129 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe130 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe131 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe132 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe133 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe134 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe135 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe136 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe137 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe138 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe139 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe140 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe141 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe142 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe143 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe144 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe145 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe146 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe147 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe148 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe149 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe150 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe151 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe152 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe153 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe154 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe155 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe156 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe157 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe158 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe159 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe160 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe161 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe162 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe163 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe164 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe165 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe166 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe167 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe168 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe169 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe170 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe171 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe172 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe173 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe174 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe175 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe176 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe177 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe178 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe179 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe180 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe181 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe182 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe183 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe184 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe185 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe186 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe187 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe188 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe189 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe190 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe191 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe192 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe193 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe194 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe195 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe196 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe197 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe198 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe199 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe200 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe201 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe202 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe203 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe204 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe205 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe206 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe207 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe208 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe209 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe210 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe211 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe212 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe213 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe214 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe215 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe216 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe217 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe218 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe219 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe220 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe221 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe222 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe223 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe224 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe225 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe226 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe227 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe228 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe229 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe230 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe231 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe232 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe233 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe234 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe235 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe236 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe237 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe238 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe239 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe240 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe241 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe242 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe243 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe244 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe245 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe246 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe247 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe248 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe249 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe250 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe251 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe252 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe253 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe254 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe255 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe256 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe257 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe258 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe259 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe260 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe261 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe262 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe263 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe264 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe265 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe266 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe267 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe268 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe269 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe270 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe271 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe272 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe273 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe274 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe275 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe276 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe277 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe278 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe279 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe280 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe281 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe282 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe283 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe284 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe285 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe286 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe287 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe288 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe289 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe290 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe291 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe292 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe293 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe294 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe295 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe296 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe297 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe298 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe299 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe300 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe301 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe302 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe303 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe304 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe305 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe306 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe307 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe308 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe309 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe310 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe311 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe312 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe313 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe314 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe315 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe316 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe317 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe318 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe319 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe320 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe321 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe322 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe323 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe324 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe325 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe326 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe327 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe328 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe329 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe330 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe331 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe332 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe333 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe334 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe335 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe336 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe337 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe338 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe339 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe340 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe341 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe342 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe343 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe344 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe345 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe346 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe347 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe348 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe349 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe350 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe351 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe352 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe353 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe354 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe355 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe356 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe357 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe358 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe359 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe360 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe361 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe362 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe363 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe364 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe365 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe366 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe367 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe368 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe369 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe370 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe371 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe372 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe373 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe374 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe375 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe376 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe377 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe378 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe379 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe380 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe381 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe382 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe383 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe384 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe385 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe386 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe387 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe388 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe389 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe390 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe391 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe392 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe393 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe394 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe395 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe396 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe397 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe398 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe399 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe400 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe401 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe402 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe403 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe404 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe405 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe406 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe407 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe408 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe409 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe410 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe411 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe412 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe413 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe414 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe415 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe416 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe417 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe418 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe419 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe420 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe421 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe422 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe423 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe424 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe425 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe426 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe427 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe428 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe429 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe430 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe431 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe432 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe433 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe434 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe435 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe436 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe437 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe438 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe439 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe440 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe441 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe442 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe443 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe444 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe445 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe446 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe447 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe448 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe449 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe450 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe451 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe452 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe453 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe454 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe455 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe456 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe457 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe458 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe459 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe460 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe461 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe462 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe463 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe464 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe465 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe466 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe467 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe468 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe469 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe470 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe471 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe472 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe473 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe474 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe475 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe476 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe477 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe478 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe479 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe480 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe481 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe482 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe483 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe484 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe485 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe486 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe487 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe488 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe489 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe490 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe491 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe492 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe493 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe494 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe495 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe496 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe497 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe498 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe499 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe500 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe501 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe502 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe503 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe504 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe505 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe506 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe507 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe508 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe509 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe510 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe511 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe512 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe513 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe514 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe515 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe516 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe517 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe518 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe519 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe520 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe521 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe522 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe523 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe524 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe525 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe526 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe527 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe528 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe529 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe530 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe531 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe532 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe533 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe534 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe535 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe536 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe537 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe538 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe539 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe540 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe541 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe542 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe543 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe544 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe545 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe546 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe547 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe548 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe549 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe550 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe551 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe552 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe553 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe554 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe555 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe556 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe557 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe558 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe559 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe560 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe561 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe562 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe563 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe564 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe565 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe566 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe567 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe568 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe569 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe570 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe571 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe572 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe573 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe574 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe575 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe576 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe577 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe578 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe579 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe580 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe581 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe582 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe583 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe584 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe585 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe586 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe587 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe588 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe589 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe590 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe591 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe592 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe593 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe594 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe595 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe596 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe597 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe598 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe599 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe600 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe601 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe602 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe603 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe604 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe605 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe606 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe607 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe608 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe609 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe610 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe611 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe612 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe613 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe614 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe615 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe616 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe617 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe618 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe619 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe620 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe621 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe622 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe623 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe624 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe625 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe626 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe627 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe628 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe629 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe630 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe631 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe632 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe633 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe634 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe635 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe636 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe637 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe638 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe639 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe640 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe641 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe642 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe643 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe644 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe645 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe646 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe647 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe648 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe649 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe650 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe651 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe652 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe653 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe654 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe655 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe656 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe657 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe658 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe659 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe660 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe661 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe662 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe663 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe664 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe665 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe666 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe667 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe668 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe669 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe670 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe671 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe672 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe673 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe674 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe675 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe676 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe677 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe678 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe679 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe680 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe681 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe682 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe683 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe684 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe685 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe686 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe687 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe688 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe689 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe690 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe691 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe692 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe693 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe694 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe695 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe696 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe697 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe698 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe699 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe700 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe701 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe702 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe703 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe704 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe705 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe706 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe707 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe708 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe709 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe710 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe711 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe712 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe713 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe714 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe715 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe716 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe717 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe718 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe719 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe720 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe721 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe722 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe723 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe724 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe725 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe726 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe727 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe728 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe729 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe730 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe731 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe732 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe733 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe734 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe735 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe736 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe737 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe738 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe739 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe740 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe741 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe742 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe743 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe744 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe745 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe746 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe747 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe748 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe749 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe750 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe751 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe752 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe753 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe754 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe755 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe756 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe757 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe758 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe759 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe760 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe761 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe762 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe763 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe764 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe765 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe766 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe767 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe768 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe769 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe770 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe771 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe772 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe773 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe774 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe775 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe776 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe777 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe778 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe779 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe780 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe781 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe782 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe783 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe784 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe785 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe786 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe787 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe788 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe789 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe790 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe791 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe792 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe793 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe794 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe795 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe796 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe797 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe798 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe799 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe800 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe801 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe802 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe803 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe804 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe805 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe806 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe807 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe808 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe809 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe810 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe811 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe812 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe813 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe814 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe815 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe816 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe817 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe818 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe819 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe820 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe821 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe822 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe823 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe824 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe825 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe826 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe827 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe828 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe829 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe830 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe831 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe832 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe833 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe834 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe835 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe836 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe837 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe838 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe839 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe840 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe841 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe842 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe843 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe844 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe845 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe846 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe847 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe848 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe849 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe850 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe851 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe852 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe853 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe854 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe855 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe856 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe857 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe858 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe859 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe860 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe861 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe862 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe863 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe864 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe865 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe866 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe867 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe868 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe869 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe870 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe871 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe872 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe873 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe874 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe875 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe876 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe877 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe878 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe879 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe880 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe881 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe882 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe883 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe884 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe885 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe886 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe887 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe888 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe889 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe890 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe891 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe892 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe893 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe894 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe895 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe896 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe897 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe898 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe899 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe900 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe901 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe902 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe903 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe904 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe905 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe906 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe907 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe908 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe909 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe910 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe911 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe912 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe913 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe914 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe915 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe916 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe917 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe918 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe919 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe920 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe921 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe922 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe923 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe924 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe925 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe926 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe927 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe928 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe929 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe930 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe931 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe932 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe933 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe934 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe935 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe936 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe937 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe938 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe939 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe940 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe941 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe942 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe943 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe944 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe945 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe946 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe947 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe948 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe949 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe950 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe951 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe952 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe953 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe954 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe955 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe956 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe957 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe958 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe959 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe960 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe961 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe962 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe963 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe964 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe965 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe966 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe967 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe968 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe969 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe970 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe971 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe972 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe973 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe974 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe975 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe976 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe977 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe978 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe979 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe980 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe981 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe982 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe983 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe984 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe985 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe986 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe987 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe988 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe989 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe990 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe991 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe992 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe993 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe994 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe995 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe996 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe997 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe998 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe999 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1000 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1001 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1002 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1003 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1004 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1005 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1006 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1007 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1008 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1009 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1010 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1011 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1012 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1013 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1014 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1015 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1016 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1017 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1018 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1019 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1020 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1021 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1022 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1023 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT ila_v6_2_4_ila;
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "yes";
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "ila,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "DemoInterconnect_ila_0_0,ila_v6_2_4_ila,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DemoInterconnect_ila_0_0_arch : ARCHITECTURE IS "DemoInterconnect_ila_0_0,ila,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=artix7,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=4,C_DATA_DEPTH=8192,C_MAJOR_VERSION=2017,C_MINOR_VERSION=3,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=1,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=2,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=72000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=8,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=8,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
"C_PROBE354_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE398_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE453_WIDTH=1,"&
"C_PROBE454_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE477_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE503_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE529_WIDTH=1,C_PROBE530_WIDTH=1,C_PROBE531_WIDTH=1,C_PROBE532_WIDTH=1,C_PROBE533_WIDTH=1,C_PROBE534_WIDTH=1,C_PROBE535_WIDTH=1,C_PROBE536_WIDTH=1,C_PROBE537_WIDTH=1,C_PROBE538_WIDTH=1,C_PROBE539_WIDTH=1,C_PROBE540_WIDTH=1,C_PROBE541_WIDTH=1,C_PROBE542_WIDTH=1,C_PROBE543_WIDTH=1,C_PROBE544_WIDTH=1,C_PROBE545_WIDTH=1,C_PROBE546_WIDTH=1,C_PROBE547_WIDTH=1,C_PROBE548_WIDTH=1,C_PROBE549_WIDTH=1,C_PROBE550_WIDTH=1,C_PROBE551_WIDTH=1,C_PROBE552_WIDTH=1,C_PROBE553_WIDTH=1,"&
"C_PROBE554_WIDTH=1,C_PROBE555_WIDTH=1,C_PROBE556_WIDTH=1,C_PROBE557_WIDTH=1,C_PROBE558_WIDTH=1,C_PROBE559_WIDTH=1,C_PROBE560_WIDTH=1,C_PROBE561_WIDTH=1,C_PROBE562_WIDTH=1,C_PROBE563_WIDTH=1,C_PROBE564_WIDTH=1,C_PROBE565_WIDTH=1,C_PROBE566_WIDTH=1,C_PROBE567_WIDTH=1,C_PROBE568_WIDTH=1,C_PROBE569_WIDTH=1,C_PROBE570_WIDTH=1,C_PROBE571_WIDTH=1,C_PROBE572_WIDTH=1,C_PROBE573_WIDTH=1,C_PROBE574_WIDTH=1,C_PROBE575_WIDTH=1,C_PROBE576_WIDTH=1,C_PROBE577_WIDTH=1,C_PROBE578_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE581_WIDTH=1,C_PROBE582_WIDTH=1,C_PROBE583_WIDTH=1,C_PROBE584_WIDTH=1,C_PROBE585_WIDTH=1,C_PROBE586_WIDTH=1,C_PROBE587_WIDTH=1,C_PROBE588_WIDTH=1,C_PROBE589_WIDTH=1,C_PROBE590_WIDTH=1,C_PROBE591_WIDTH=1,C_PROBE592_WIDTH=1,C_PROBE593_WIDTH=1,C_PROBE594_WIDTH=1,C_PROBE595_WIDTH=1,C_PROBE596_WIDTH=1,C_PROBE597_WIDTH=1,C_PROBE598_WIDTH=1,C_PROBE599_WIDTH=1,C_PROBE600_WIDTH=1,C_PROBE601_WIDTH=1,C_PROBE602_WIDTH=1,C_PROBE603_WIDTH=1,C_PROBE604_WIDTH=1,C_PROBE605_WIDTH=1,C_PROBE606_WIDTH=1,C_PROBE607_WIDTH=1,C_PROBE608_WIDTH=1,C_PROBE609_WIDTH=1,C_PROBE610_WIDTH=1,C_PROBE611_WIDTH=1,C_PROBE612_WIDTH=1,C_PROBE613_WIDTH=1,C_PROBE614_WIDTH=1,C_PROBE615_WIDTH=1,C_PROBE616_WIDTH=1,C_PROBE617_WIDTH=1,C_PROBE618_WIDTH=1,C_PROBE619_WIDTH=1,C_PROBE620_WIDTH=1,C_PROBE621_WIDTH=1,C_PROBE622_WIDTH=1,C_PROBE623_WIDTH=1,C_PROBE624_WIDTH=1,C_PROBE625_WIDTH=1,C_PROBE626_WIDTH=1,C_PROBE627_WIDTH=1,C_PROBE628_WIDTH=1,C_PROBE629_WIDTH=1,C_PROBE630_WIDTH=1,C_PROBE631_WIDTH=1,C_PROBE632_WIDTH=1,C_PROBE633_WIDTH=1,C_PROBE634_WIDTH=1,C_PROBE635_WIDTH=1,C_PROBE636_WIDTH=1,C_PROBE637_WIDTH=1,C_PROBE638_WIDTH=1,C_PROBE639_WIDTH=1,C_PROBE640_WIDTH=1,C_PROBE641_WIDTH=1,C_PROBE642_WIDTH=1,C_PROBE643_WIDTH=1,C_PROBE644_WIDTH=1,C_PROBE645_WIDTH=1,C_PROBE646_WIDTH=1,C_PROBE647_WIDTH=1,C_PROBE648_WIDTH=1,C_PROBE649_WIDTH=1,C_PROBE650_WIDTH=1,C_PROBE651_WIDTH=1,C_PROBE652_WIDTH=1,C_PROBE653_WIDTH=1,"&
"C_PROBE654_WIDTH=1,C_PROBE655_WIDTH=1,C_PROBE656_WIDTH=1,C_PROBE657_WIDTH=1,C_PROBE658_WIDTH=1,C_PROBE659_WIDTH=1,C_PROBE660_WIDTH=1,C_PROBE661_WIDTH=1,C_PROBE662_WIDTH=1,C_PROBE663_WIDTH=1,C_PROBE664_WIDTH=1,C_PROBE665_WIDTH=1,C_PROBE666_WIDTH=1,C_PROBE667_WIDTH=1,C_PROBE668_WIDTH=1,C_PROBE669_WIDTH=1,C_PROBE670_WIDTH=1,C_PROBE671_WIDTH=1,C_PROBE672_WIDTH=1,C_PROBE673_WIDTH=1,C_PROBE674_WIDTH=1,C_PROBE675_WIDTH=1,C_PROBE676_WIDTH=1,C_PROBE677_WIDTH=1,C_PROBE678_WIDTH=1,C_PROBE679_WIDTH=1,C_PROBE680_WIDTH=1,C_PROBE681_WIDTH=1,C_PROBE682_WIDTH=1,C_PROBE683_WIDTH=1,C_PROBE684_WIDTH=1,C_PROBE685_WIDTH=1,C_PROBE686_WIDTH=1,C_PROBE687_WIDTH=1,C_PROBE688_WIDTH=1,C_PROBE689_WIDTH=1,C_PROBE690_WIDTH=1,C_PROBE691_WIDTH=1,C_PROBE692_WIDTH=1,C_PROBE693_WIDTH=1,C_PROBE694_WIDTH=1,C_PROBE695_WIDTH=1,C_PROBE696_WIDTH=1,C_PROBE697_WIDTH=1,C_PROBE698_WIDTH=1,C_PROBE699_WIDTH=1,C_PROBE700_WIDTH=1,C_PROBE701_WIDTH=1,C_PROBE702_WIDTH=1,C_PROBE703_WIDTH=1,C_PROBE704_WIDTH=1,C_PROBE705_WIDTH=1,C_PROBE706_WIDTH=1,C_PROBE707_WIDTH=1,C_PROBE708_WIDTH=1,C_PROBE709_WIDTH=1,C_PROBE710_WIDTH=1,C_PROBE711_WIDTH=1,C_PROBE712_WIDTH=1,C_PROBE713_WIDTH=1,C_PROBE714_WIDTH=1,C_PROBE715_WIDTH=1,C_PROBE716_WIDTH=1,C_PROBE717_WIDTH=1,C_PROBE718_WIDTH=1,C_PROBE719_WIDTH=1,C_PROBE720_WIDTH=1,C_PROBE721_WIDTH=1,C_PROBE722_WIDTH=1,C_PROBE723_WIDTH=1,C_PROBE724_WIDTH=1,C_PROBE725_WIDTH=1,C_PROBE726_WIDTH=1,C_PROBE727_WIDTH=1,C_PROBE728_WIDTH=1,C_PROBE729_WIDTH=1,C_PROBE730_WIDTH=1,C_PROBE731_WIDTH=1,C_PROBE732_WIDTH=1,C_PROBE733_WIDTH=1,C_PROBE734_WIDTH=1,C_PROBE735_WIDTH=1,C_PROBE736_WIDTH=1,C_PROBE737_WIDTH=1,C_PROBE738_WIDTH=1,C_PROBE739_WIDTH=1,C_PROBE740_WIDTH=1,C_PROBE741_WIDTH=1,C_PROBE742_WIDTH=1,C_PROBE743_WIDTH=1,C_PROBE744_WIDTH=1,C_PROBE745_WIDTH=1,C_PROBE746_WIDTH=1,C_PROBE747_WIDTH=1,C_PROBE748_WIDTH=1,C_PROBE749_WIDTH=1,C_PROBE750_WIDTH=1,C_PROBE751_WIDTH=1,C_PROBE752_WIDTH=1,C_PROBE753_WIDTH=1,"&
"C_PROBE754_WIDTH=1,C_PROBE755_WIDTH=1,C_PROBE756_WIDTH=1,C_PROBE757_WIDTH=1,C_PROBE758_WIDTH=1,C_PROBE759_WIDTH=1,C_PROBE760_WIDTH=1,C_PROBE761_WIDTH=1,C_PROBE762_WIDTH=1,C_PROBE763_WIDTH=1,C_PROBE764_WIDTH=1,C_PROBE765_WIDTH=1,C_PROBE766_WIDTH=1,C_PROBE767_WIDTH=1,C_PROBE768_WIDTH=1,C_PROBE769_WIDTH=1,C_PROBE770_WIDTH=1,C_PROBE771_WIDTH=1,C_PROBE772_WIDTH=1,C_PROBE773_WIDTH=1,C_PROBE774_WIDTH=1,C_PROBE775_WIDTH=1,C_PROBE776_WIDTH=1,C_PROBE777_WIDTH=1,C_PROBE778_WIDTH=1,C_PROBE779_WIDTH=1,C_PROBE780_WIDTH=1,C_PROBE781_WIDTH=1,C_PROBE782_WIDTH=1,C_PROBE783_WIDTH=1,C_PROBE784_WIDTH=1,C_PROBE785_WIDTH=1,C_PROBE786_WIDTH=1,C_PROBE787_WIDTH=1,C_PROBE788_WIDTH=1,C_PROBE789_WIDTH=1,C_PROBE790_WIDTH=1,C_PROBE791_WIDTH=1,C_PROBE792_WIDTH=1,C_PROBE793_WIDTH=1,C_PROBE794_WIDTH=1,C_PROBE795_WIDTH=1,C_PROBE796_WIDTH=1,C_PROBE797_WIDTH=1,C_PROBE798_WIDTH=1,C_PROBE799_WIDTH=1,C_PROBE800_WIDTH=1,C_PROBE801_WIDTH=1,C_PROBE802_WIDTH=1,C_PROBE803_WIDTH=1,C_PROBE804_WIDTH=1,C_PROBE805_WIDTH=1,C_PROBE806_WIDTH=1,C_PROBE807_WIDTH=1,C_PROBE808_WIDTH=1,C_PROBE809_WIDTH=1,C_PROBE810_WIDTH=1,C_PROBE811_WIDTH=1,C_PROBE812_WIDTH=1,C_PROBE813_WIDTH=1,C_PROBE814_WIDTH=1,C_PROBE815_WIDTH=1,C_PROBE816_WIDTH=1,C_PROBE817_WIDTH=1,C_PROBE818_WIDTH=1,C_PROBE819_WIDTH=1,C_PROBE820_WIDTH=1,C_PROBE821_WIDTH=1,C_PROBE822_WIDTH=1,C_PROBE823_WIDTH=1,C_PROBE824_WIDTH=1,C_PROBE825_WIDTH=1,C_PROBE826_WIDTH=1,C_PROBE827_WIDTH=1,C_PROBE828_WIDTH=1,C_PROBE829_WIDTH=1,C_PROBE830_WIDTH=1,C_PROBE831_WIDTH=1,C_PROBE832_WIDTH=1,C_PROBE833_WIDTH=1,C_PROBE834_WIDTH=1,C_PROBE835_WIDTH=1,C_PROBE836_WIDTH=1,C_PROBE837_WIDTH=1,C_PROBE838_WIDTH=1,C_PROBE839_WIDTH=1,C_PROBE840_WIDTH=1,C_PROBE841_WIDTH=1,C_PROBE842_WIDTH=1,C_PROBE843_WIDTH=1,C_PROBE844_WIDTH=1,C_PROBE845_WIDTH=1,C_PROBE846_WIDTH=1,C_PROBE847_WIDTH=1,C_PROBE848_WIDTH=1,C_PROBE849_WIDTH=1,C_PROBE850_WIDTH=1,C_PROBE851_WIDTH=1,C_PROBE852_WIDTH=1,C_PROBE853_WIDTH=1,"&
"C_PROBE854_WIDTH=1,C_PROBE855_WIDTH=1,C_PROBE856_WIDTH=1,C_PROBE857_WIDTH=1,C_PROBE858_WIDTH=1,C_PROBE859_WIDTH=1,C_PROBE860_WIDTH=1,C_PROBE861_WIDTH=1,C_PROBE862_WIDTH=1,C_PROBE863_WIDTH=1,C_PROBE864_WIDTH=1,C_PROBE865_WIDTH=1,C_PROBE866_WIDTH=1,C_PROBE867_WIDTH=1,C_PROBE868_WIDTH=1,C_PROBE869_WIDTH=1,C_PROBE870_WIDTH=1,C_PROBE871_WIDTH=1,C_PROBE872_WIDTH=1,C_PROBE873_WIDTH=1,C_PROBE874_WIDTH=1,C_PROBE875_WIDTH=1,C_PROBE876_WIDTH=1,C_PROBE877_WIDTH=1,C_PROBE878_WIDTH=1,C_PROBE879_WIDTH=1,C_PROBE880_WIDTH=1,C_PROBE881_WIDTH=1,C_PROBE882_WIDTH=1,C_PROBE883_WIDTH=1,C_PROBE884_WIDTH=1,C_PROBE885_WIDTH=1,C_PROBE886_WIDTH=1,C_PROBE887_WIDTH=1,C_PROBE888_WIDTH=1,C_PROBE889_WIDTH=1,C_PROBE890_WIDTH=1,C_PROBE891_WIDTH=1,C_PROBE892_WIDTH=1,C_PROBE893_WIDTH=1,C_PROBE894_WIDTH=1,C_PROBE895_WIDTH=1,C_PROBE896_WIDTH=1,C_PROBE897_WIDTH=1,C_PROBE898_WIDTH=1,C_PROBE899_WIDTH=1,C_PROBE900_WIDTH=1,C_PROBE901_WIDTH=1,C_PROBE902_WIDTH=1,C_PROBE903_WIDTH=1,C_PROBE904_WIDTH=1,C_PROBE905_WIDTH=1,C_PROBE906_WIDTH=1,C_PROBE907_WIDTH=1,C_PROBE908_WIDTH=1,C_PROBE909_WIDTH=1,C_PROBE910_WIDTH=1,C_PROBE911_WIDTH=1,C_PROBE912_WIDTH=1,C_PROBE913_WIDTH=1,C_PROBE914_WIDTH=1,C_PROBE915_WIDTH=1,C_PROBE916_WIDTH=1,C_PROBE917_WIDTH=1,C_PROBE918_WIDTH=1,C_PROBE919_WIDTH=1,C_PROBE920_WIDTH=1,C_PROBE921_WIDTH=1,C_PROBE922_WIDTH=1,C_PROBE923_WIDTH=1,C_PROBE924_WIDTH=1,C_PROBE925_WIDTH=1,C_PROBE926_WIDTH=1,C_PROBE927_WIDTH=1,C_PROBE928_WIDTH=1,C_PROBE929_WIDTH=1,C_PROBE930_WIDTH=1,C_PROBE931_WIDTH=1,C_PROBE932_WIDTH=1,C_PROBE933_WIDTH=1,C_PROBE934_WIDTH=1,C_PROBE935_WIDTH=1,C_PROBE936_WIDTH=1,C_PROBE937_WIDTH=1,C_PROBE938_WIDTH=1,C_PROBE939_WIDTH=1,C_PROBE940_WIDTH=1,C_PROBE941_WIDTH=1,C_PROBE942_WIDTH=1,C_PROBE943_WIDTH=1,C_PROBE944_WIDTH=1,C_PROBE945_WIDTH=1,C_PROBE946_WIDTH=1,C_PROBE947_WIDTH=1,C_PROBE948_WIDTH=1,C_PROBE949_WIDTH=1,C_PROBE950_WIDTH=1,C_PROBE951_WIDTH=1,C_PROBE952_WIDTH=1,C_PROBE953_WIDTH=1,"&
"C_PROBE954_WIDTH=1,C_PROBE955_WIDTH=1,C_PROBE956_WIDTH=1,C_PROBE957_WIDTH=1,C_PROBE958_WIDTH=1,C_PROBE959_WIDTH=1,C_PROBE960_WIDTH=1,C_PROBE961_WIDTH=1,C_PROBE962_WIDTH=1,C_PROBE963_WIDTH=1,C_PROBE964_WIDTH=1,C_PROBE965_WIDTH=1,C_PROBE966_WIDTH=1,C_PROBE967_WIDTH=1,C_PROBE968_WIDTH=1,C_PROBE969_WIDTH=1,C_PROBE970_WIDTH=1,C_PROBE971_WIDTH=1,C_PROBE972_WIDTH=1,C_PROBE973_WIDTH=1,C_PROBE974_WIDTH=1,C_PROBE975_WIDTH=1,C_PROBE976_WIDTH=1,C_PROBE977_WIDTH=1,C_PROBE978_WIDTH=1,C_PROBE979_WIDTH=1,C_PROBE980_WIDTH=1,C_PROBE981_WIDTH=1,C_PROBE982_WIDTH=1,C_PROBE983_WIDTH=1,C_PROBE984_WIDTH=1,C_PROBE985_WIDTH=1,C_PROBE986_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=2,C_PROBE1_MU_CNT=2,C_PROBE2_MU_CNT=2,C_PROBE3_MU_CNT=2,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,"&
"C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,"&
"C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,"&
"C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,"&
"C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,"&
"C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,"&
"C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,"&
"C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,"&
"C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,"&
"C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,"&
"C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=1,C_PROBE2_TYPE=0,C_PROBE3_TYPE=1,C_PROBE4_TYPE=1,C_PROBE5_TYPE=1,"&
"C_PROBE6_TYPE=1,C_PROBE7_TYPE=1,C_PROBE8_TYPE=1,C_PROBE9_TYPE=1,C_PROBE10_TYPE=1,C_PROBE11_TYPE=1,C_PROBE12_TYPE=1,C_PROBE13_TYPE=1,C_PROBE14_TYPE=1,C_PROBE15_TYPE=1,C_PROBE16_TYPE=1,C_PROBE17_TYPE=1,C_PROBE18_TYPE=1,C_PROBE19_TYPE=1,C_PROBE20_TYPE=1,C_PROBE21_TYPE=1,C_PROBE22_TYPE=1,C_PROBE23_TYPE=1,C_PROBE24_TYPE=1,C_PROBE25_TYPE=1,C_PROBE26_TYPE=1,C_PROBE27_TYPE=1,C_PROBE28_TYPE=1,C_PROBE29_TYPE=1,C_PROBE30_TYPE=1,C_PROBE31_TYPE=1,C_PROBE32_TYPE=1,C_PROBE33_TYPE=1,C_PROBE34_TYPE=1,C_PROBE35_TYPE=1,C_PROBE36_TYPE=1,C_PROBE37_TYPE=1,C_PROBE38_TYPE=1,C_PROBE39_TYPE=1,C_PROBE40_TYPE=1,C_PROBE41_TYPE=1,C_PROBE42_TYPE=1,C_PROBE43_TYPE=1,C_PROBE44_TYPE=1,C_PROBE45_TYPE=1,C_PROBE46_TYPE=1,C_PROBE47_TYPE=1,C_PROBE48_TYPE=1,C_PROBE49_TYPE=1,C_PROBE50_TYPE=1,C_PROBE51_TYPE=1,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,"&
"C_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,"&
"C_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PROBE248_TYPE=1,C_PROBE249_TYPE=1,C_PROBE250_TYPE=1,C_PROBE251_TYPE=1,C_PROBE252_TYPE=1,C_PROBE253_TYPE=1,C_PROBE254_TYPE=1,C_PROBE255_TYPE=1,C_PROBE256_TYPE=1,C_PROBE257_TYPE=1,C_PROBE258_TYPE=1,C_PROBE259_TYPE=1,C_PROBE260_TYPE=1,C_PROBE261_TYPE=1,C_PROBE262_TYPE=1,C_PROBE263_TYPE=1,C_PROBE264_TYPE=1,C_PROBE265_TYPE=1,C_PROBE266_TYPE=1,C_PROBE267_TYPE=1,C_PROBE268_TYPE=1,C_PROBE269_TYPE=1,C_PROBE270_TYPE=1,C_PROBE271_TYPE=1,C_PROBE272_TYPE=1,C_PROBE273_TYPE=1,C_PROBE274_TYPE=1,C_PROBE275_TYPE=1,C_PROBE276_TYPE=1,C_PROBE277_TYPE=1,C_PROBE278_TYPE=1,C_PROBE279_TYPE=1,C_PROBE280_TYPE=1,C_PROBE281_TYPE=1,C_PROBE282_TYPE=1,C_PROBE283_TYPE=1,C_PROBE284_TYPE=1,C_PROBE285_TYPE=1,C_PROBE286_TYPE=1,C_PROBE287_TYPE=1,C_PROBE288_TYPE=1,C_PROBE289_TYPE=1,C_PROBE290_TYPE=1,C_PROBE291_TYPE=1,C_PROBE292_TYPE=1,C_PROBE293_TYPE=1,C_PROBE294_TYPE=1,C_PROBE295_TYPE=1,C_PROBE296_TYPE=1,C_PROBE297_TYPE=1,C_PROBE298_TYPE=1,C_PROBE299_TYPE=1,C_PROBE300_TYPE=1,C_PROBE301_TYPE=1,C_PROBE302_TYPE=1,C_PROBE303_TYPE=1,C_PROBE304_TYPE=1,C_PROBE305_TYPE=1,"&
"C_PROBE306_TYPE=1,C_PROBE307_TYPE=1,C_PROBE308_TYPE=1,C_PROBE309_TYPE=1,C_PROBE310_TYPE=1,C_PROBE311_TYPE=1,C_PROBE312_TYPE=1,C_PROBE313_TYPE=1,C_PROBE314_TYPE=1,C_PROBE315_TYPE=1,C_PROBE316_TYPE=1,C_PROBE317_TYPE=1,C_PROBE318_TYPE=1,C_PROBE319_TYPE=1,C_PROBE320_TYPE=1,C_PROBE321_TYPE=1,C_PROBE322_TYPE=1,C_PROBE323_TYPE=1,C_PROBE324_TYPE=1,C_PROBE325_TYPE=1,C_PROBE326_TYPE=1,C_PROBE327_TYPE=1,C_PROBE328_TYPE=1,C_PROBE329_TYPE=1,C_PROBE330_TYPE=1,C_PROBE331_TYPE=1,C_PROBE332_TYPE=1,C_PROBE333_TYPE=1,C_PROBE334_TYPE=1,C_PROBE335_TYPE=1,C_PROBE336_TYPE=1,C_PROBE337_TYPE=1,C_PROBE338_TYPE=1,C_PROBE339_TYPE=1,C_PROBE340_TYPE=1,C_PROBE341_TYPE=1,C_PROBE342_TYPE=1,C_PROBE343_TYPE=1,C_PROBE344_TYPE=1,C_PROBE345_TYPE=1,C_PROBE346_TYPE=1,C_PROBE347_TYPE=1,C_PROBE348_TYPE=1,C_PROBE349_TYPE=1,C_PROBE350_TYPE=1,C_PROBE351_TYPE=1,C_PROBE352_TYPE=1,C_PROBE353_TYPE=1,C_PROBE354_TYPE=1,C_PROBE355_TYPE=1,C_PROBE356_TYPE=1,C_PROBE357_TYPE=1,C_PROBE358_TYPE=1,C_PROBE359_TYPE=1,C_PROBE360_TYPE=1,C_PROBE361_TYPE=1,C_PROBE362_TYPE=1,C_PROBE363_TYPE=1,C_PROBE364_TYPE=1,C_PROBE365_TYPE=1,C_PROBE366_TYPE=1,C_PROBE367_TYPE=1,C_PROBE368_TYPE=1,C_PROBE369_TYPE=1,C_PROBE370_TYPE=1,C_PROBE371_TYPE=1,C_PROBE372_TYPE=1,C_PROBE373_TYPE=1,C_PROBE374_TYPE=1,C_PROBE375_TYPE=1,C_PROBE376_TYPE=1,C_PROBE377_TYPE=1,C_PROBE378_TYPE=1,C_PROBE379_TYPE=1,C_PROBE380_TYPE=1,C_PROBE381_TYPE=1,C_PROBE382_TYPE=1,C_PROBE383_TYPE=1,C_PROBE384_TYPE=1,C_PROBE385_TYPE=1,C_PROBE386_TYPE=1,C_PROBE387_TYPE=1,C_PROBE388_TYPE=1,C_PROBE389_TYPE=1,C_PROBE390_TYPE=1,C_PROBE391_TYPE=1,C_PROBE392_TYPE=1,C_PROBE393_TYPE=1,C_PROBE394_TYPE=1,C_PROBE395_TYPE=1,C_PROBE396_TYPE=1,C_PROBE397_TYPE=1,C_PROBE398_TYPE=1,C_PROBE399_TYPE=1,C_PROBE400_TYPE=1,C_PROBE401_TYPE=1,C_PROBE402_TYPE=1,C_PROBE403_TYPE=1,C_PROBE404_TYPE=1,C_PROBE405_TYPE=1,"&
"C_PROBE406_TYPE=1,C_PROBE407_TYPE=1,C_PROBE408_TYPE=1,C_PROBE409_TYPE=1,C_PROBE410_TYPE=1,C_PROBE411_TYPE=1,C_PROBE412_TYPE=1,C_PROBE413_TYPE=1,C_PROBE414_TYPE=1,C_PROBE415_TYPE=1,C_PROBE416_TYPE=1,C_PROBE417_TYPE=1,C_PROBE418_TYPE=1,C_PROBE419_TYPE=1,C_PROBE420_TYPE=1,C_PROBE421_TYPE=1,C_PROBE422_TYPE=1,C_PROBE423_TYPE=1,C_PROBE424_TYPE=1,C_PROBE425_TYPE=1,C_PROBE426_TYPE=1,C_PROBE427_TYPE=1,C_PROBE428_TYPE=1,C_PROBE429_TYPE=1,C_PROBE430_TYPE=1,C_PROBE431_TYPE=1,C_PROBE432_TYPE=1,C_PROBE433_TYPE=1,C_PROBE434_TYPE=1,C_PROBE435_TYPE=1,C_PROBE436_TYPE=1,C_PROBE437_TYPE=1,C_PROBE438_TYPE=1,C_PROBE439_TYPE=1,C_PROBE440_TYPE=1,C_PROBE441_TYPE=1,C_PROBE442_TYPE=1,C_PROBE443_TYPE=1,C_PROBE444_TYPE=1,C_PROBE445_TYPE=1,C_PROBE446_TYPE=1,C_PROBE447_TYPE=1,C_PROBE448_TYPE=1,C_PROBE449_TYPE=1,C_PROBE450_TYPE=1,C_PROBE451_TYPE=1,C_PROBE452_TYPE=1,C_PROBE453_TYPE=1,C_PROBE454_TYPE=1,C_PROBE455_TYPE=1,C_PROBE456_TYPE=1,C_PROBE457_TYPE=1,C_PROBE458_TYPE=1,C_PROBE459_TYPE=1,C_PROBE460_TYPE=1,C_PROBE461_TYPE=1,C_PROBE462_TYPE=1,C_PROBE463_TYPE=1,C_PROBE464_TYPE=1,C_PROBE465_TYPE=1,C_PROBE466_TYPE=1,C_PROBE467_TYPE=1,C_PROBE468_TYPE=1,C_PROBE469_TYPE=1,C_PROBE470_TYPE=1,C_PROBE471_TYPE=1,C_PROBE472_TYPE=1,C_PROBE473_TYPE=1,C_PROBE474_TYPE=1,C_PROBE475_TYPE=1,C_PROBE476_TYPE=1,C_PROBE477_TYPE=1,C_PROBE478_TYPE=1,C_PROBE479_TYPE=1,C_PROBE480_TYPE=1,C_PROBE481_TYPE=1,C_PROBE482_TYPE=1,C_PROBE483_TYPE=1,C_PROBE484_TYPE=1,C_PROBE485_TYPE=1,C_PROBE486_TYPE=1,C_PROBE487_TYPE=1,C_PROBE488_TYPE=1,C_PROBE489_TYPE=1,C_PROBE490_TYPE=1,C_PROBE491_TYPE=1,C_PROBE492_TYPE=1,C_PROBE493_TYPE=1,C_PROBE494_TYPE=1,C_PROBE495_TYPE=1,C_PROBE496_TYPE=1,C_PROBE497_TYPE=1,C_PROBE498_TYPE=1,C_PROBE499_TYPE=1,C_PROBE500_TYPE=1,C_PROBE501_TYPE=1,C_PROBE502_TYPE=1,C_PROBE503_TYPE=1,C_PROBE504_TYPE=1,C_PROBE505_TYPE=1,"&
"C_PROBE506_TYPE=1,C_PROBE507_TYPE=1,C_PROBE508_TYPE=1,C_PROBE509_TYPE=1,C_PROBE510_TYPE=1,C_PROBE511_TYPE=1,C_PROBE512_TYPE=1,C_PROBE513_TYPE=1,C_PROBE514_TYPE=1,C_PROBE515_TYPE=1,C_PROBE516_TYPE=1,C_PROBE517_TYPE=1,C_PROBE518_TYPE=1,C_PROBE519_TYPE=1,C_PROBE520_TYPE=1,C_PROBE521_TYPE=1,C_PROBE522_TYPE=1,C_PROBE523_TYPE=1,C_PROBE524_TYPE=1,C_PROBE525_TYPE=1,C_PROBE526_TYPE=1,C_PROBE527_TYPE=1,C_PROBE528_TYPE=1,C_PROBE529_TYPE=1,C_PROBE530_TYPE=1,C_PROBE531_TYPE=1,C_PROBE532_TYPE=1,C_PROBE533_TYPE=1,C_PROBE534_TYPE=1,C_PROBE535_TYPE=1,C_PROBE536_TYPE=1,C_PROBE537_TYPE=1,C_PROBE538_TYPE=1,C_PROBE539_TYPE=1,C_PROBE540_TYPE=1,C_PROBE541_TYPE=1,C_PROBE542_TYPE=1,C_PROBE543_TYPE=1,C_PROBE544_TYPE=1,C_PROBE545_TYPE=1,C_PROBE546_TYPE=1,C_PROBE547_TYPE=1,C_PROBE548_TYPE=1,C_PROBE549_TYPE=1,C_PROBE550_TYPE=1,C_PROBE551_TYPE=1,C_PROBE552_TYPE=1,C_PROBE553_TYPE=1,C_PROBE554_TYPE=1,C_PROBE555_TYPE=1,C_PROBE556_TYPE=1,C_PROBE557_TYPE=1,C_PROBE558_TYPE=1,C_PROBE559_TYPE=1,C_PROBE560_TYPE=1,C_PROBE561_TYPE=1,C_PROBE562_TYPE=1,C_PROBE563_TYPE=1,C_PROBE564_TYPE=1,C_PROBE565_TYPE=1,C_PROBE566_TYPE=1,C_PROBE567_TYPE=1,C_PROBE568_TYPE=1,C_PROBE569_TYPE=1,C_PROBE570_TYPE=1,C_PROBE571_TYPE=1,C_PROBE572_TYPE=1,C_PROBE573_TYPE=1,C_PROBE574_TYPE=1,C_PROBE575_TYPE=1,C_PROBE576_TYPE=1,C_PROBE577_TYPE=1,C_PROBE578_TYPE=1,C_PROBE579_TYPE=1,C_PROBE580_TYPE=1,C_PROBE581_TYPE=1,C_PROBE582_TYPE=1,C_PROBE583_TYPE=1,C_PROBE584_TYPE=1,C_PROBE585_TYPE=1,C_PROBE586_TYPE=1,C_PROBE587_TYPE=1,C_PROBE588_TYPE=1,C_PROBE589_TYPE=1,C_PROBE590_TYPE=1,C_PROBE591_TYPE=1,C_PROBE592_TYPE=1,C_PROBE593_TYPE=1,C_PROBE594_TYPE=1,C_PROBE595_TYPE=1,C_PROBE596_TYPE=1,C_PROBE597_TYPE=1,C_PROBE598_TYPE=1,C_PROBE599_TYPE=1,C_PROBE600_TYPE=1,C_PROBE601_TYPE=1,C_PROBE602_TYPE=1,C_PROBE603_TYPE=1,C_PROBE604_TYPE=1,C_PROBE605_TYPE=1,"&
"C_PROBE606_TYPE=1,C_PROBE607_TYPE=1,C_PROBE608_TYPE=1,C_PROBE609_TYPE=1,C_PROBE610_TYPE=1,C_PROBE611_TYPE=1,C_PROBE612_TYPE=1,C_PROBE613_TYPE=1,C_PROBE614_TYPE=1,C_PROBE615_TYPE=1,C_PROBE616_TYPE=1,C_PROBE617_TYPE=1,C_PROBE618_TYPE=1,C_PROBE619_TYPE=1,C_PROBE620_TYPE=1,C_PROBE621_TYPE=1,C_PROBE622_TYPE=1,C_PROBE623_TYPE=1,C_PROBE624_TYPE=1,C_PROBE625_TYPE=1,C_PROBE626_TYPE=1,C_PROBE627_TYPE=1,C_PROBE628_TYPE=1,C_PROBE629_TYPE=1,C_PROBE630_TYPE=1,C_PROBE631_TYPE=1,C_PROBE632_TYPE=1,C_PROBE633_TYPE=1,C_PROBE634_TYPE=1,C_PROBE635_TYPE=1,C_PROBE636_TYPE=1,C_PROBE637_TYPE=1,C_PROBE638_TYPE=1,C_PROBE639_TYPE=1,C_PROBE640_TYPE=1,C_PROBE641_TYPE=1,C_PROBE642_TYPE=1,C_PROBE643_TYPE=1,C_PROBE644_TYPE=1,C_PROBE645_TYPE=1,C_PROBE646_TYPE=1,C_PROBE647_TYPE=1,C_PROBE648_TYPE=1,C_PROBE649_TYPE=1,C_PROBE650_TYPE=1,C_PROBE651_TYPE=1,C_PROBE652_TYPE=1,C_PROBE653_TYPE=1,C_PROBE654_TYPE=1,C_PROBE655_TYPE=1,C_PROBE656_TYPE=1,C_PROBE657_TYPE=1,C_PROBE658_TYPE=1,C_PROBE659_TYPE=1,C_PROBE660_TYPE=1,C_PROBE661_TYPE=1,C_PROBE662_TYPE=1,C_PROBE663_TYPE=1,C_PROBE664_TYPE=1,C_PROBE665_TYPE=1,C_PROBE666_TYPE=1,C_PROBE667_TYPE=1,C_PROBE668_TYPE=1,C_PROBE669_TYPE=1,C_PROBE670_TYPE=1,C_PROBE671_TYPE=1,C_PROBE672_TYPE=1,C_PROBE673_TYPE=1,C_PROBE674_TYPE=1,C_PROBE675_TYPE=1,C_PROBE676_TYPE=1,C_PROBE677_TYPE=1,C_PROBE678_TYPE=1,C_PROBE679_TYPE=1,C_PROBE680_TYPE=1,C_PROBE681_TYPE=1,C_PROBE682_TYPE=1,C_PROBE683_TYPE=1,C_PROBE684_TYPE=1,C_PROBE685_TYPE=1,C_PROBE686_TYPE=1,C_PROBE687_TYPE=1,C_PROBE688_TYPE=1,C_PROBE689_TYPE=1,C_PROBE690_TYPE=1,C_PROBE691_TYPE=1,C_PROBE692_TYPE=1,C_PROBE693_TYPE=1,C_PROBE694_TYPE=1,C_PROBE695_TYPE=1,C_PROBE696_TYPE=1,C_PROBE697_TYPE=1,C_PROBE698_TYPE=1,C_PROBE699_TYPE=1,C_PROBE700_TYPE=1,C_PROBE701_TYPE=1,C_PROBE702_TYPE=1,C_PROBE703_TYPE=1,C_PROBE704_TYPE=1,C_PROBE705_TYPE=1,"&
"C_PROBE706_TYPE=1,C_PROBE707_TYPE=1,C_PROBE708_TYPE=1,C_PROBE709_TYPE=1,C_PROBE710_TYPE=1,C_PROBE711_TYPE=1,C_PROBE712_TYPE=1,C_PROBE713_TYPE=1,C_PROBE714_TYPE=1,C_PROBE715_TYPE=1,C_PROBE716_TYPE=1,C_PROBE717_TYPE=1,C_PROBE718_TYPE=1,C_PROBE719_TYPE=1,C_PROBE720_TYPE=1,C_PROBE721_TYPE=1,C_PROBE722_TYPE=1,C_PROBE723_TYPE=1,C_PROBE724_TYPE=1,C_PROBE725_TYPE=1,C_PROBE726_TYPE=1,C_PROBE727_TYPE=1,C_PROBE728_TYPE=1,C_PROBE729_TYPE=1,C_PROBE730_TYPE=1,C_PROBE731_TYPE=1,C_PROBE732_TYPE=1,C_PROBE733_TYPE=1,C_PROBE734_TYPE=1,C_PROBE735_TYPE=1,C_PROBE736_TYPE=1,C_PROBE737_TYPE=1,C_PROBE738_TYPE=1,C_PROBE739_TYPE=1,C_PROBE740_TYPE=1,C_PROBE741_TYPE=1,C_PROBE742_TYPE=1,C_PROBE743_TYPE=1,C_PROBE744_TYPE=1,C_PROBE745_TYPE=1,C_PROBE746_TYPE=1,C_PROBE747_TYPE=1,C_PROBE748_TYPE=1,C_PROBE749_TYPE=1,C_PROBE750_TYPE=1,C_PROBE751_TYPE=1,C_PROBE752_TYPE=1,C_PROBE753_TYPE=1,C_PROBE754_TYPE=1,C_PROBE755_TYPE=1,C_PROBE756_TYPE=1,C_PROBE757_TYPE=1,C_PROBE758_TYPE=1,C_PROBE759_TYPE=1,C_PROBE760_TYPE=1,C_PROBE761_TYPE=1,C_PROBE762_TYPE=1,C_PROBE763_TYPE=1,C_PROBE764_TYPE=1,C_PROBE765_TYPE=1,C_PROBE766_TYPE=1,C_PROBE767_TYPE=1,C_PROBE768_TYPE=1,C_PROBE769_TYPE=1,C_PROBE770_TYPE=1,C_PROBE771_TYPE=1,C_PROBE772_TYPE=1,C_PROBE773_TYPE=1,C_PROBE774_TYPE=1,C_PROBE775_TYPE=1,C_PROBE776_TYPE=1,C_PROBE777_TYPE=1,C_PROBE778_TYPE=1,C_PROBE779_TYPE=1,C_PROBE780_TYPE=1,C_PROBE781_TYPE=1,C_PROBE782_TYPE=1,C_PROBE783_TYPE=1,C_PROBE784_TYPE=1,C_PROBE785_TYPE=1,C_PROBE786_TYPE=1,C_PROBE787_TYPE=1,C_PROBE788_TYPE=1,C_PROBE789_TYPE=1,C_PROBE790_TYPE=1,C_PROBE791_TYPE=1,C_PROBE792_TYPE=1,C_PROBE793_TYPE=1,C_PROBE794_TYPE=1,C_PROBE795_TYPE=1,C_PROBE796_TYPE=1,C_PROBE797_TYPE=1,C_PROBE798_TYPE=1,C_PROBE799_TYPE=1,C_PROBE800_TYPE=1,C_PROBE801_TYPE=1,C_PROBE802_TYPE=1,C_PROBE803_TYPE=1,C_PROBE804_TYPE=1,C_PROBE805_TYPE=1,"&
"C_PROBE806_TYPE=1,C_PROBE807_TYPE=1,C_PROBE808_TYPE=1,C_PROBE809_TYPE=1,C_PROBE810_TYPE=1,C_PROBE811_TYPE=1,C_PROBE812_TYPE=1,C_PROBE813_TYPE=1,C_PROBE814_TYPE=1,C_PROBE815_TYPE=1,C_PROBE816_TYPE=1,C_PROBE817_TYPE=1,C_PROBE818_TYPE=1,C_PROBE819_TYPE=1,C_PROBE820_TYPE=1,C_PROBE821_TYPE=1,C_PROBE822_TYPE=1,C_PROBE823_TYPE=1,C_PROBE824_TYPE=1,C_PROBE825_TYPE=1,C_PROBE826_TYPE=1,C_PROBE827_TYPE=1,C_PROBE828_TYPE=1,C_PROBE829_TYPE=1,C_PROBE830_TYPE=1,C_PROBE831_TYPE=1,C_PROBE832_TYPE=1,C_PROBE833_TYPE=1,C_PROBE834_TYPE=1,C_PROBE835_TYPE=1,C_PROBE836_TYPE=1,C_PROBE837_TYPE=1,C_PROBE838_TYPE=1,C_PROBE839_TYPE=1,C_PROBE840_TYPE=1,C_PROBE841_TYPE=1,C_PROBE842_TYPE=1,C_PROBE843_TYPE=1,C_PROBE844_TYPE=1,C_PROBE845_TYPE=1,C_PROBE846_TYPE=1,C_PROBE847_TYPE=1,C_PROBE848_TYPE=1,C_PROBE849_TYPE=1,C_PROBE850_TYPE=1,C_PROBE851_TYPE=1,C_PROBE852_TYPE=1,C_PROBE853_TYPE=1,C_PROBE854_TYPE=1,C_PROBE855_TYPE=1,C_PROBE856_TYPE=1,C_PROBE857_TYPE=1,C_PROBE858_TYPE=1,C_PROBE859_TYPE=1,C_PROBE860_TYPE=1,C_PROBE861_TYPE=1,C_PROBE862_TYPE=1,C_PROBE863_TYPE=1,C_PROBE864_TYPE=1,C_PROBE865_TYPE=1,C_PROBE866_TYPE=1,C_PROBE867_TYPE=1,C_PROBE868_TYPE=1,C_PROBE869_TYPE=1,C_PROBE870_TYPE=1,C_PROBE871_TYPE=1,C_PROBE872_TYPE=1,C_PROBE873_TYPE=1,C_PROBE874_TYPE=1,C_PROBE875_TYPE=1,C_PROBE876_TYPE=1,C_PROBE877_TYPE=1,C_PROBE878_TYPE=1,C_PROBE879_TYPE=1,C_PROBE880_TYPE=1,C_PROBE881_TYPE=1,C_PROBE882_TYPE=1,C_PROBE883_TYPE=1,C_PROBE884_TYPE=1,C_PROBE885_TYPE=1,C_PROBE886_TYPE=1,C_PROBE887_TYPE=1,C_PROBE888_TYPE=1,C_PROBE889_TYPE=1,C_PROBE890_TYPE=1,C_PROBE891_TYPE=1,C_PROBE892_TYPE=1,C_PROBE893_TYPE=1,C_PROBE894_TYPE=1,C_PROBE895_TYPE=1,C_PROBE896_TYPE=1,C_PROBE897_TYPE=1,C_PROBE898_TYPE=1,C_PROBE899_TYPE=1,C_PROBE900_TYPE=1,C_PROBE901_TYPE=1,C_PROBE902_TYPE=1,C_PROBE903_TYPE=1,C_PROBE904_TYPE=1,C_PROBE905_TYPE=1,"&
"C_PROBE906_TYPE=1,C_PROBE907_TYPE=1,C_PROBE908_TYPE=1,C_PROBE909_TYPE=1,C_PROBE910_TYPE=1,C_PROBE911_TYPE=1,C_PROBE912_TYPE=1,C_PROBE913_TYPE=1,C_PROBE914_TYPE=1,C_PROBE915_TYPE=1,C_PROBE916_TYPE=1,C_PROBE917_TYPE=1,C_PROBE918_TYPE=1,C_PROBE919_TYPE=1,C_PROBE920_TYPE=1,C_PROBE921_TYPE=1,C_PROBE922_TYPE=1,C_PROBE923_TYPE=1,C_PROBE924_TYPE=1,C_PROBE925_TYPE=1,C_PROBE926_TYPE=1,C_PROBE927_TYPE=1,C_PROBE928_TYPE=1,C_PROBE929_TYPE=1,C_PROBE930_TYPE=1,C_PROBE931_TYPE=1,C_PROBE932_TYPE=1,C_PROBE933_TYPE=1,C_PROBE934_TYPE=1,C_PROBE935_TYPE=1,C_PROBE936_TYPE=1,C_PROBE937_TYPE=1,C_PROBE938_TYPE=1,C_PROBE939_TYPE=1,C_PROBE940_TYPE=1,C_PROBE941_TYPE=1,C_PROBE942_TYPE=1,C_PROBE943_TYPE=1,C_PROBE944_TYPE=1,C_PROBE945_TYPE=1,C_PROBE946_TYPE=1,C_PROBE947_TYPE=1,C_PROBE948_TYPE=1,C_PROBE949_TYPE=1,C_PROBE950_TYPE=1,C_PROBE951_TYPE=1,C_PROBE952_TYPE=1,C_PROBE953_TYPE=1,C_PROBE954_TYPE=1,C_PROBE955_TYPE=1,C_PROBE956_TYPE=1,C_PROBE957_TYPE=1,C_PROBE958_TYPE=1,C_PROBE959_TYPE=1,C_PROBE960_TYPE=1,C_PROBE961_TYPE=1,C_PROBE962_TYPE=1,C_PROBE963_TYPE=1,C_PROBE964_TYPE=1,C_PROBE965_TYPE=1,C_PROBE966_TYPE=1,C_PROBE967_TYPE=1,C_PROBE968_TYPE=1,C_PROBE969_TYPE=1,C_PROBE970_TYPE=1,C_PROBE971_TYPE=1,C_PROBE972_TYPE=1,C_PROBE973_TYPE=1,C_PROBE974_TYPE=1,C_PROBE975_TYPE=1,C_PROBE976_TYPE=1,C_PROBE977_TYPE=1,C_PROBE978_TYPE=1,C_PROBE979_TYPE=1,C_PROBE980_TYPE=1,C_PROBE981_TYPE=1,C_PROBE982_TYPE=1,C_PROBE983_TYPE=1,C_PROBE984_TYPE=1,C_PROBE985_TYPE=1,C_PROBE986_TYPE=1,C_PROBE987_TYPE=1,C_PROBE988_TYPE=1,C_PROBE989_TYPE=1,C_PROBE990_TYPE=1,C_PROBE991_TYPE=1,C_PROBE992_TYPE=1,C_PROBE993_TYPE=1,C_PROBE994_TYPE=1,C_PROBE995_TYPE=1,C_PROBE996_TYPE=1,C_PROBE997_TYPE=1,C_PROBE998_TYPE=1,C_PROBE999_TYPE=1,C_PROBE1000_TYPE=1,C_PROBE1001_TYPE=1,C_PROBE1002_TYPE=1,C_PROBE1003_TYPE=1,C_PROBE1004_TYPE=1,C_PROBE1005_TYPE=1,"&
"C_PROBE1006_TYPE=1,C_PROBE1007_TYPE=1,C_PROBE1008_TYPE=1,C_PROBE1009_TYPE=1,C_PROBE1010_TYPE=1,C_PROBE1011_TYPE=1,C_PROBE1012_TYPE=1,C_PROBE1013_TYPE=1,C_PROBE1014_TYPE=1,C_PROBE1015_TYPE=1,C_PROBE1016_TYPE=1,C_PROBE1017_TYPE=1,C_PROBE1018_TYPE=1,C_PROBE1019_TYPE=1,C_PROBE1020_TYPE=1,C_PROBE1021_TYPE=1,C_PROBE1022_TYPE=1,C_PROBE1023_TYPE=1},";
attribute syn_noprune : boolean;
attribute syn_noprune of U0 : label is true;
SIGNAL sl_iport0 : STD_LOGIC_VECTOR (36 downto 0);
SIGNAL sl_oport0 : STD_LOGIC_VECTOR (16 downto 0);
BEGIN
U0 : ila_v6_2_4_ila
GENERIC MAP (
C_XLNX_HW_PROBE_INFO => "DEFAULT",
C_XDEVICEFAMILY => "artix7",
C_CORE_TYPE => 1,
C_CORE_INFO1 => 0,
C_CORE_INFO2 => 0,
C_CAPTURE_TYPE => 0,
C_MU_TYPE => 0,
C_TC_TYPE => 0,
C_NUM_OF_PROBES => 4,
C_DATA_DEPTH => 8192,
C_MAJOR_VERSION => 2017,
C_MINOR_VERSION => 3,
C_BUILD_REVISION => 0,
C_CORE_MAJOR_VER => 6,
C_CORE_MINOR_VER => 2,
C_XSDB_SLAVE_TYPE => 17,
C_NEXT_SLAVE => 0,
C_CSE_DRV_VER => 2,
C_USE_TEST_REG => 1,
C_PIPE_IFACE => 1,
C_RAM_STYLE => "SUBCORE",
C_TRIGOUT_EN => 0,
C_TRIGIN_EN => 0,
C_ADV_TRIGGER => 0,
C_EN_DDR_ILA => 0,
C_EN_STRG_QUAL => 1,
C_INPUT_PIPE_STAGES => 0,
C_EN_TIME_TAG => 0,
C_TIME_TAG_WIDTH => 32,
C_ILA_CLK_FREQ => 72000000,
C_PROBE0_WIDTH => 1,
C_PROBE1_WIDTH => 8,
C_PROBE2_WIDTH => 1,
C_PROBE3_WIDTH => 8,
C_PROBE4_WIDTH => 1,
C_PROBE5_WIDTH => 1,
C_PROBE6_WIDTH => 1,
C_PROBE7_WIDTH => 1,
C_PROBE8_WIDTH => 1,
C_PROBE9_WIDTH => 1,
C_PROBE10_WIDTH => 1,
C_PROBE11_WIDTH => 1,
C_PROBE12_WIDTH => 1,
C_PROBE13_WIDTH => 1,
C_PROBE14_WIDTH => 1,
C_PROBE15_WIDTH => 1,
C_PROBE16_WIDTH => 1,
C_PROBE17_WIDTH => 1,
C_PROBE18_WIDTH => 1,
C_PROBE19_WIDTH => 1,
C_PROBE20_WIDTH => 1,
C_PROBE21_WIDTH => 1,
C_PROBE22_WIDTH => 1,
C_PROBE23_WIDTH => 1,
C_PROBE24_WIDTH => 1,
C_PROBE25_WIDTH => 1,
C_PROBE26_WIDTH => 1,
C_PROBE27_WIDTH => 1,
C_PROBE28_WIDTH => 1,
C_PROBE29_WIDTH => 1,
C_PROBE30_WIDTH => 1,
C_PROBE31_WIDTH => 1,
C_PROBE32_WIDTH => 1,
C_PROBE33_WIDTH => 1,
C_PROBE34_WIDTH => 1,
C_PROBE35_WIDTH => 1,
C_PROBE36_WIDTH => 1,
C_PROBE37_WIDTH => 1,
C_PROBE38_WIDTH => 1,
C_PROBE39_WIDTH => 1,
C_PROBE40_WIDTH => 1,
C_PROBE41_WIDTH => 1,
C_PROBE42_WIDTH => 1,
C_PROBE43_WIDTH => 1,
C_PROBE44_WIDTH => 1,
C_PROBE45_WIDTH => 1,
C_PROBE46_WIDTH => 1,
C_PROBE47_WIDTH => 1,
C_PROBE48_WIDTH => 1,
C_PROBE49_WIDTH => 1,
C_PROBE50_WIDTH => 1,
C_PROBE51_WIDTH => 1,
C_PROBE52_WIDTH => 1,
C_PROBE53_WIDTH => 1,
C_PROBE54_WIDTH => 1,
C_PROBE55_WIDTH => 1,
C_PROBE56_WIDTH => 1,
C_PROBE57_WIDTH => 1,
C_PROBE58_WIDTH => 1,
C_PROBE59_WIDTH => 1,
C_PROBE60_WIDTH => 1,
C_PROBE61_WIDTH => 1,
C_PROBE62_WIDTH => 1,
C_PROBE63_WIDTH => 1,
C_PROBE64_WIDTH => 1,
C_PROBE65_WIDTH => 1,
C_PROBE66_WIDTH => 1,
C_PROBE67_WIDTH => 1,
C_PROBE68_WIDTH => 1,
C_PROBE69_WIDTH => 1,
C_PROBE70_WIDTH => 1,
C_PROBE71_WIDTH => 1,
C_PROBE72_WIDTH => 1,
C_PROBE73_WIDTH => 1,
C_PROBE74_WIDTH => 1,
C_PROBE75_WIDTH => 1,
C_PROBE76_WIDTH => 1,
C_PROBE77_WIDTH => 1,
C_PROBE78_WIDTH => 1,
C_PROBE79_WIDTH => 1,
C_PROBE80_WIDTH => 1,
C_PROBE81_WIDTH => 1,
C_PROBE82_WIDTH => 1,
C_PROBE83_WIDTH => 1,
C_PROBE84_WIDTH => 1,
C_PROBE85_WIDTH => 1,
C_PROBE86_WIDTH => 1,
C_PROBE87_WIDTH => 1,
C_PROBE88_WIDTH => 1,
C_PROBE89_WIDTH => 1,
C_PROBE90_WIDTH => 1,
C_PROBE91_WIDTH => 1,
C_PROBE92_WIDTH => 1,
C_PROBE93_WIDTH => 1,
C_PROBE94_WIDTH => 1,
C_PROBE95_WIDTH => 1,
C_PROBE96_WIDTH => 1,
C_PROBE97_WIDTH => 1,
C_PROBE98_WIDTH => 1,
C_PROBE99_WIDTH => 1,
C_PROBE100_WIDTH => 1,
C_PROBE101_WIDTH => 1,
C_PROBE102_WIDTH => 1,
C_PROBE103_WIDTH => 1,
C_PROBE104_WIDTH => 1,
C_PROBE105_WIDTH => 1,
C_PROBE106_WIDTH => 1,
C_PROBE107_WIDTH => 1,
C_PROBE108_WIDTH => 1,
C_PROBE109_WIDTH => 1,
C_PROBE110_WIDTH => 1,
C_PROBE111_WIDTH => 1,
C_PROBE112_WIDTH => 1,
C_PROBE113_WIDTH => 1,
C_PROBE114_WIDTH => 1,
C_PROBE115_WIDTH => 1,
C_PROBE116_WIDTH => 1,
C_PROBE117_WIDTH => 1,
C_PROBE118_WIDTH => 1,
C_PROBE119_WIDTH => 1,
C_PROBE120_WIDTH => 1,
C_PROBE121_WIDTH => 1,
C_PROBE122_WIDTH => 1,
C_PROBE123_WIDTH => 1,
C_PROBE124_WIDTH => 1,
C_PROBE125_WIDTH => 1,
C_PROBE126_WIDTH => 1,
C_PROBE127_WIDTH => 1,
C_PROBE128_WIDTH => 1,
C_PROBE129_WIDTH => 1,
C_PROBE130_WIDTH => 1,
C_PROBE131_WIDTH => 1,
C_PROBE132_WIDTH => 1,
C_PROBE133_WIDTH => 1,
C_PROBE134_WIDTH => 1,
C_PROBE135_WIDTH => 1,
C_PROBE136_WIDTH => 1,
C_PROBE137_WIDTH => 1,
C_PROBE138_WIDTH => 1,
C_PROBE139_WIDTH => 1,
C_PROBE140_WIDTH => 1,
C_PROBE141_WIDTH => 1,
C_PROBE142_WIDTH => 1,
C_PROBE143_WIDTH => 1,
C_PROBE144_WIDTH => 1,
C_PROBE145_WIDTH => 1,
C_PROBE146_WIDTH => 1,
C_PROBE147_WIDTH => 1,
C_PROBE148_WIDTH => 1,
C_PROBE149_WIDTH => 1,
C_PROBE150_WIDTH => 1,
C_PROBE151_WIDTH => 1,
C_PROBE152_WIDTH => 1,
C_PROBE153_WIDTH => 1,
C_PROBE154_WIDTH => 1,
C_PROBE155_WIDTH => 1,
C_PROBE156_WIDTH => 1,
C_PROBE157_WIDTH => 1,
C_PROBE158_WIDTH => 1,
C_PROBE159_WIDTH => 1,
C_PROBE160_WIDTH => 1,
C_PROBE161_WIDTH => 1,
C_PROBE162_WIDTH => 1,
C_PROBE163_WIDTH => 1,
C_PROBE164_WIDTH => 1,
C_PROBE165_WIDTH => 1,
C_PROBE166_WIDTH => 1,
C_PROBE167_WIDTH => 1,
C_PROBE168_WIDTH => 1,
C_PROBE169_WIDTH => 1,
C_PROBE170_WIDTH => 1,
C_PROBE171_WIDTH => 1,
C_PROBE172_WIDTH => 1,
C_PROBE173_WIDTH => 1,
C_PROBE174_WIDTH => 1,
C_PROBE175_WIDTH => 1,
C_PROBE176_WIDTH => 1,
C_PROBE177_WIDTH => 1,
C_PROBE178_WIDTH => 1,
C_PROBE179_WIDTH => 1,
C_PROBE180_WIDTH => 1,
C_PROBE181_WIDTH => 1,
C_PROBE182_WIDTH => 1,
C_PROBE183_WIDTH => 1,
C_PROBE184_WIDTH => 1,
C_PROBE185_WIDTH => 1,
C_PROBE186_WIDTH => 1,
C_PROBE187_WIDTH => 1,
C_PROBE188_WIDTH => 1,
C_PROBE189_WIDTH => 1,
C_PROBE190_WIDTH => 1,
C_PROBE191_WIDTH => 1,
C_PROBE192_WIDTH => 1,
C_PROBE193_WIDTH => 1,
C_PROBE194_WIDTH => 1,
C_PROBE195_WIDTH => 1,
C_PROBE196_WIDTH => 1,
C_PROBE197_WIDTH => 1,
C_PROBE198_WIDTH => 1,
C_PROBE199_WIDTH => 1,
C_PROBE200_WIDTH => 1,
C_PROBE201_WIDTH => 1,
C_PROBE202_WIDTH => 1,
C_PROBE203_WIDTH => 1,
C_PROBE204_WIDTH => 1,
C_PROBE205_WIDTH => 1,
C_PROBE206_WIDTH => 1,
C_PROBE207_WIDTH => 1,
C_PROBE208_WIDTH => 1,
C_PROBE209_WIDTH => 1,
C_PROBE210_WIDTH => 1,
C_PROBE211_WIDTH => 1,
C_PROBE212_WIDTH => 1,
C_PROBE213_WIDTH => 1,
C_PROBE214_WIDTH => 1,
C_PROBE215_WIDTH => 1,
C_PROBE216_WIDTH => 1,
C_PROBE217_WIDTH => 1,
C_PROBE218_WIDTH => 1,
C_PROBE219_WIDTH => 1,
C_PROBE220_WIDTH => 1,
C_PROBE221_WIDTH => 1,
C_PROBE222_WIDTH => 1,
C_PROBE223_WIDTH => 1,
C_PROBE224_WIDTH => 1,
C_PROBE225_WIDTH => 1,
C_PROBE226_WIDTH => 1,
C_PROBE227_WIDTH => 1,
C_PROBE228_WIDTH => 1,
C_PROBE229_WIDTH => 1,
C_PROBE230_WIDTH => 1,
C_PROBE231_WIDTH => 1,
C_PROBE232_WIDTH => 1,
C_PROBE233_WIDTH => 1,
C_PROBE234_WIDTH => 1,
C_PROBE235_WIDTH => 1,
C_PROBE236_WIDTH => 1,
C_PROBE237_WIDTH => 1,
C_PROBE238_WIDTH => 1,
C_PROBE239_WIDTH => 1,
C_PROBE240_WIDTH => 1,
C_PROBE241_WIDTH => 1,
C_PROBE242_WIDTH => 1,
C_PROBE243_WIDTH => 1,
C_PROBE244_WIDTH => 1,
C_PROBE245_WIDTH => 1,
C_PROBE246_WIDTH => 1,
C_PROBE247_WIDTH => 1,
C_PROBE248_WIDTH => 1,
C_PROBE249_WIDTH => 1,
C_PROBE250_WIDTH => 1,
C_PROBE251_WIDTH => 1,
C_PROBE252_WIDTH => 1,
C_PROBE253_WIDTH => 1,
C_PROBE254_WIDTH => 1,
C_PROBE255_WIDTH => 1,
C_PROBE256_WIDTH => 1,
C_PROBE257_WIDTH => 1,
C_PROBE258_WIDTH => 1,
C_PROBE259_WIDTH => 1,
C_PROBE260_WIDTH => 1,
C_PROBE261_WIDTH => 1,
C_PROBE262_WIDTH => 1,
C_PROBE263_WIDTH => 1,
C_PROBE264_WIDTH => 1,
C_PROBE265_WIDTH => 1,
C_PROBE266_WIDTH => 1,
C_PROBE267_WIDTH => 1,
C_PROBE268_WIDTH => 1,
C_PROBE269_WIDTH => 1,
C_PROBE270_WIDTH => 1,
C_PROBE271_WIDTH => 1,
C_PROBE272_WIDTH => 1,
C_PROBE273_WIDTH => 1,
C_PROBE274_WIDTH => 1,
C_PROBE275_WIDTH => 1,
C_PROBE276_WIDTH => 1,
C_PROBE277_WIDTH => 1,
C_PROBE278_WIDTH => 1,
C_PROBE279_WIDTH => 1,
C_PROBE280_WIDTH => 1,
C_PROBE281_WIDTH => 1,
C_PROBE282_WIDTH => 1,
C_PROBE283_WIDTH => 1,
C_PROBE284_WIDTH => 1,
C_PROBE285_WIDTH => 1,
C_PROBE286_WIDTH => 1,
C_PROBE287_WIDTH => 1,
C_PROBE288_WIDTH => 1,
C_PROBE289_WIDTH => 1,
C_PROBE290_WIDTH => 1,
C_PROBE291_WIDTH => 1,
C_PROBE292_WIDTH => 1,
C_PROBE293_WIDTH => 1,
C_PROBE294_WIDTH => 1,
C_PROBE295_WIDTH => 1,
C_PROBE296_WIDTH => 1,
C_PROBE297_WIDTH => 1,
C_PROBE298_WIDTH => 1,
C_PROBE299_WIDTH => 1,
C_PROBE300_WIDTH => 1,
C_PROBE301_WIDTH => 1,
C_PROBE302_WIDTH => 1,
C_PROBE303_WIDTH => 1,
C_PROBE304_WIDTH => 1,
C_PROBE305_WIDTH => 1,
C_PROBE306_WIDTH => 1,
C_PROBE307_WIDTH => 1,
C_PROBE308_WIDTH => 1,
C_PROBE309_WIDTH => 1,
C_PROBE310_WIDTH => 1,
C_PROBE311_WIDTH => 1,
C_PROBE312_WIDTH => 1,
C_PROBE313_WIDTH => 1,
C_PROBE314_WIDTH => 1,
C_PROBE315_WIDTH => 1,
C_PROBE316_WIDTH => 1,
C_PROBE317_WIDTH => 1,
C_PROBE318_WIDTH => 1,
C_PROBE319_WIDTH => 1,
C_PROBE320_WIDTH => 1,
C_PROBE321_WIDTH => 1,
C_PROBE322_WIDTH => 1,
C_PROBE323_WIDTH => 1,
C_PROBE324_WIDTH => 1,
C_PROBE325_WIDTH => 1,
C_PROBE326_WIDTH => 1,
C_PROBE327_WIDTH => 1,
C_PROBE328_WIDTH => 1,
C_PROBE329_WIDTH => 1,
C_PROBE330_WIDTH => 1,
C_PROBE331_WIDTH => 1,
C_PROBE332_WIDTH => 1,
C_PROBE333_WIDTH => 1,
C_PROBE334_WIDTH => 1,
C_PROBE335_WIDTH => 1,
C_PROBE336_WIDTH => 1,
C_PROBE337_WIDTH => 1,
C_PROBE338_WIDTH => 1,
C_PROBE339_WIDTH => 1,
C_PROBE340_WIDTH => 1,
C_PROBE341_WIDTH => 1,
C_PROBE342_WIDTH => 1,
C_PROBE343_WIDTH => 1,
C_PROBE344_WIDTH => 1,
C_PROBE345_WIDTH => 1,
C_PROBE346_WIDTH => 1,
C_PROBE347_WIDTH => 1,
C_PROBE348_WIDTH => 1,
C_PROBE349_WIDTH => 1,
C_PROBE350_WIDTH => 1,
C_PROBE351_WIDTH => 1,
C_PROBE352_WIDTH => 1,
C_PROBE353_WIDTH => 1,
C_PROBE354_WIDTH => 1,
C_PROBE355_WIDTH => 1,
C_PROBE356_WIDTH => 1,
C_PROBE357_WIDTH => 1,
C_PROBE358_WIDTH => 1,
C_PROBE359_WIDTH => 1,
C_PROBE360_WIDTH => 1,
C_PROBE361_WIDTH => 1,
C_PROBE362_WIDTH => 1,
C_PROBE363_WIDTH => 1,
C_PROBE364_WIDTH => 1,
C_PROBE365_WIDTH => 1,
C_PROBE366_WIDTH => 1,
C_PROBE367_WIDTH => 1,
C_PROBE368_WIDTH => 1,
C_PROBE369_WIDTH => 1,
C_PROBE370_WIDTH => 1,
C_PROBE371_WIDTH => 1,
C_PROBE372_WIDTH => 1,
C_PROBE373_WIDTH => 1,
C_PROBE374_WIDTH => 1,
C_PROBE375_WIDTH => 1,
C_PROBE376_WIDTH => 1,
C_PROBE377_WIDTH => 1,
C_PROBE378_WIDTH => 1,
C_PROBE379_WIDTH => 1,
C_PROBE380_WIDTH => 1,
C_PROBE381_WIDTH => 1,
C_PROBE382_WIDTH => 1,
C_PROBE383_WIDTH => 1,
C_PROBE384_WIDTH => 1,
C_PROBE385_WIDTH => 1,
C_PROBE386_WIDTH => 1,
C_PROBE387_WIDTH => 1,
C_PROBE388_WIDTH => 1,
C_PROBE389_WIDTH => 1,
C_PROBE390_WIDTH => 1,
C_PROBE391_WIDTH => 1,
C_PROBE392_WIDTH => 1,
C_PROBE393_WIDTH => 1,
C_PROBE394_WIDTH => 1,
C_PROBE395_WIDTH => 1,
C_PROBE396_WIDTH => 1,
C_PROBE397_WIDTH => 1,
C_PROBE398_WIDTH => 1,
C_PROBE399_WIDTH => 1,
C_PROBE400_WIDTH => 1,
C_PROBE401_WIDTH => 1,
C_PROBE402_WIDTH => 1,
C_PROBE403_WIDTH => 1,
C_PROBE404_WIDTH => 1,
C_PROBE405_WIDTH => 1,
C_PROBE406_WIDTH => 1,
C_PROBE407_WIDTH => 1,
C_PROBE408_WIDTH => 1,
C_PROBE409_WIDTH => 1,
C_PROBE410_WIDTH => 1,
C_PROBE411_WIDTH => 1,
C_PROBE412_WIDTH => 1,
C_PROBE413_WIDTH => 1,
C_PROBE414_WIDTH => 1,
C_PROBE415_WIDTH => 1,
C_PROBE416_WIDTH => 1,
C_PROBE417_WIDTH => 1,
C_PROBE418_WIDTH => 1,
C_PROBE419_WIDTH => 1,
C_PROBE420_WIDTH => 1,
C_PROBE421_WIDTH => 1,
C_PROBE422_WIDTH => 1,
C_PROBE423_WIDTH => 1,
C_PROBE424_WIDTH => 1,
C_PROBE425_WIDTH => 1,
C_PROBE426_WIDTH => 1,
C_PROBE427_WIDTH => 1,
C_PROBE428_WIDTH => 1,
C_PROBE429_WIDTH => 1,
C_PROBE430_WIDTH => 1,
C_PROBE431_WIDTH => 1,
C_PROBE432_WIDTH => 1,
C_PROBE433_WIDTH => 1,
C_PROBE434_WIDTH => 1,
C_PROBE435_WIDTH => 1,
C_PROBE436_WIDTH => 1,
C_PROBE437_WIDTH => 1,
C_PROBE438_WIDTH => 1,
C_PROBE439_WIDTH => 1,
C_PROBE440_WIDTH => 1,
C_PROBE441_WIDTH => 1,
C_PROBE442_WIDTH => 1,
C_PROBE443_WIDTH => 1,
C_PROBE444_WIDTH => 1,
C_PROBE445_WIDTH => 1,
C_PROBE446_WIDTH => 1,
C_PROBE447_WIDTH => 1,
C_PROBE448_WIDTH => 1,
C_PROBE449_WIDTH => 1,
C_PROBE450_WIDTH => 1,
C_PROBE451_WIDTH => 1,
C_PROBE452_WIDTH => 1,
C_PROBE453_WIDTH => 1,
C_PROBE454_WIDTH => 1,
C_PROBE455_WIDTH => 1,
C_PROBE456_WIDTH => 1,
C_PROBE457_WIDTH => 1,
C_PROBE458_WIDTH => 1,
C_PROBE459_WIDTH => 1,
C_PROBE460_WIDTH => 1,
C_PROBE461_WIDTH => 1,
C_PROBE462_WIDTH => 1,
C_PROBE463_WIDTH => 1,
C_PROBE464_WIDTH => 1,
C_PROBE465_WIDTH => 1,
C_PROBE466_WIDTH => 1,
C_PROBE467_WIDTH => 1,
C_PROBE468_WIDTH => 1,
C_PROBE469_WIDTH => 1,
C_PROBE470_WIDTH => 1,
C_PROBE471_WIDTH => 1,
C_PROBE472_WIDTH => 1,
C_PROBE473_WIDTH => 1,
C_PROBE474_WIDTH => 1,
C_PROBE475_WIDTH => 1,
C_PROBE476_WIDTH => 1,
C_PROBE477_WIDTH => 1,
C_PROBE478_WIDTH => 1,
C_PROBE479_WIDTH => 1,
C_PROBE480_WIDTH => 1,
C_PROBE481_WIDTH => 1,
C_PROBE482_WIDTH => 1,
C_PROBE483_WIDTH => 1,
C_PROBE484_WIDTH => 1,
C_PROBE485_WIDTH => 1,
C_PROBE486_WIDTH => 1,
C_PROBE487_WIDTH => 1,
C_PROBE488_WIDTH => 1,
C_PROBE489_WIDTH => 1,
C_PROBE490_WIDTH => 1,
C_PROBE491_WIDTH => 1,
C_PROBE492_WIDTH => 1,
C_PROBE493_WIDTH => 1,
C_PROBE494_WIDTH => 1,
C_PROBE495_WIDTH => 1,
C_PROBE496_WIDTH => 1,
C_PROBE497_WIDTH => 1,
C_PROBE498_WIDTH => 1,
C_PROBE499_WIDTH => 1,
C_PROBE500_WIDTH => 1,
C_PROBE501_WIDTH => 1,
C_PROBE502_WIDTH => 1,
C_PROBE503_WIDTH => 1,
C_PROBE504_WIDTH => 1,
C_PROBE505_WIDTH => 1,
C_PROBE506_WIDTH => 1,
C_PROBE507_WIDTH => 1,
C_PROBE508_WIDTH => 1,
C_PROBE509_WIDTH => 1,
C_PROBE510_WIDTH => 1,
C_PROBE511_WIDTH => 1,
C_PROBE512_WIDTH => 1,
C_PROBE513_WIDTH => 1,
C_PROBE514_WIDTH => 1,
C_PROBE515_WIDTH => 1,
C_PROBE516_WIDTH => 1,
C_PROBE517_WIDTH => 1,
C_PROBE518_WIDTH => 1,
C_PROBE519_WIDTH => 1,
C_PROBE520_WIDTH => 1,
C_PROBE521_WIDTH => 1,
C_PROBE522_WIDTH => 1,
C_PROBE523_WIDTH => 1,
C_PROBE524_WIDTH => 1,
C_PROBE525_WIDTH => 1,
C_PROBE526_WIDTH => 1,
C_PROBE527_WIDTH => 1,
C_PROBE528_WIDTH => 1,
C_PROBE529_WIDTH => 1,
C_PROBE530_WIDTH => 1,
C_PROBE531_WIDTH => 1,
C_PROBE532_WIDTH => 1,
C_PROBE533_WIDTH => 1,
C_PROBE534_WIDTH => 1,
C_PROBE535_WIDTH => 1,
C_PROBE536_WIDTH => 1,
C_PROBE537_WIDTH => 1,
C_PROBE538_WIDTH => 1,
C_PROBE539_WIDTH => 1,
C_PROBE540_WIDTH => 1,
C_PROBE541_WIDTH => 1,
C_PROBE542_WIDTH => 1,
C_PROBE543_WIDTH => 1,
C_PROBE544_WIDTH => 1,
C_PROBE545_WIDTH => 1,
C_PROBE546_WIDTH => 1,
C_PROBE547_WIDTH => 1,
C_PROBE548_WIDTH => 1,
C_PROBE549_WIDTH => 1,
C_PROBE550_WIDTH => 1,
C_PROBE551_WIDTH => 1,
C_PROBE552_WIDTH => 1,
C_PROBE553_WIDTH => 1,
C_PROBE554_WIDTH => 1,
C_PROBE555_WIDTH => 1,
C_PROBE556_WIDTH => 1,
C_PROBE557_WIDTH => 1,
C_PROBE558_WIDTH => 1,
C_PROBE559_WIDTH => 1,
C_PROBE560_WIDTH => 1,
C_PROBE561_WIDTH => 1,
C_PROBE562_WIDTH => 1,
C_PROBE563_WIDTH => 1,
C_PROBE564_WIDTH => 1,
C_PROBE565_WIDTH => 1,
C_PROBE566_WIDTH => 1,
C_PROBE567_WIDTH => 1,
C_PROBE568_WIDTH => 1,
C_PROBE569_WIDTH => 1,
C_PROBE570_WIDTH => 1,
C_PROBE571_WIDTH => 1,
C_PROBE572_WIDTH => 1,
C_PROBE573_WIDTH => 1,
C_PROBE574_WIDTH => 1,
C_PROBE575_WIDTH => 1,
C_PROBE576_WIDTH => 1,
C_PROBE577_WIDTH => 1,
C_PROBE578_WIDTH => 1,
C_PROBE579_WIDTH => 1,
C_PROBE580_WIDTH => 1,
C_PROBE581_WIDTH => 1,
C_PROBE582_WIDTH => 1,
C_PROBE583_WIDTH => 1,
C_PROBE584_WIDTH => 1,
C_PROBE585_WIDTH => 1,
C_PROBE586_WIDTH => 1,
C_PROBE587_WIDTH => 1,
C_PROBE588_WIDTH => 1,
C_PROBE589_WIDTH => 1,
C_PROBE590_WIDTH => 1,
C_PROBE591_WIDTH => 1,
C_PROBE592_WIDTH => 1,
C_PROBE593_WIDTH => 1,
C_PROBE594_WIDTH => 1,
C_PROBE595_WIDTH => 1,
C_PROBE596_WIDTH => 1,
C_PROBE597_WIDTH => 1,
C_PROBE598_WIDTH => 1,
C_PROBE599_WIDTH => 1,
C_PROBE600_WIDTH => 1,
C_PROBE601_WIDTH => 1,
C_PROBE602_WIDTH => 1,
C_PROBE603_WIDTH => 1,
C_PROBE604_WIDTH => 1,
C_PROBE605_WIDTH => 1,
C_PROBE606_WIDTH => 1,
C_PROBE607_WIDTH => 1,
C_PROBE608_WIDTH => 1,
C_PROBE609_WIDTH => 1,
C_PROBE610_WIDTH => 1,
C_PROBE611_WIDTH => 1,
C_PROBE612_WIDTH => 1,
C_PROBE613_WIDTH => 1,
C_PROBE614_WIDTH => 1,
C_PROBE615_WIDTH => 1,
C_PROBE616_WIDTH => 1,
C_PROBE617_WIDTH => 1,
C_PROBE618_WIDTH => 1,
C_PROBE619_WIDTH => 1,
C_PROBE620_WIDTH => 1,
C_PROBE621_WIDTH => 1,
C_PROBE622_WIDTH => 1,
C_PROBE623_WIDTH => 1,
C_PROBE624_WIDTH => 1,
C_PROBE625_WIDTH => 1,
C_PROBE626_WIDTH => 1,
C_PROBE627_WIDTH => 1,
C_PROBE628_WIDTH => 1,
C_PROBE629_WIDTH => 1,
C_PROBE630_WIDTH => 1,
C_PROBE631_WIDTH => 1,
C_PROBE632_WIDTH => 1,
C_PROBE633_WIDTH => 1,
C_PROBE634_WIDTH => 1,
C_PROBE635_WIDTH => 1,
C_PROBE636_WIDTH => 1,
C_PROBE637_WIDTH => 1,
C_PROBE638_WIDTH => 1,
C_PROBE639_WIDTH => 1,
C_PROBE640_WIDTH => 1,
C_PROBE641_WIDTH => 1,
C_PROBE642_WIDTH => 1,
C_PROBE643_WIDTH => 1,
C_PROBE644_WIDTH => 1,
C_PROBE645_WIDTH => 1,
C_PROBE646_WIDTH => 1,
C_PROBE647_WIDTH => 1,
C_PROBE648_WIDTH => 1,
C_PROBE649_WIDTH => 1,
C_PROBE650_WIDTH => 1,
C_PROBE651_WIDTH => 1,
C_PROBE652_WIDTH => 1,
C_PROBE653_WIDTH => 1,
C_PROBE654_WIDTH => 1,
C_PROBE655_WIDTH => 1,
C_PROBE656_WIDTH => 1,
C_PROBE657_WIDTH => 1,
C_PROBE658_WIDTH => 1,
C_PROBE659_WIDTH => 1,
C_PROBE660_WIDTH => 1,
C_PROBE661_WIDTH => 1,
C_PROBE662_WIDTH => 1,
C_PROBE663_WIDTH => 1,
C_PROBE664_WIDTH => 1,
C_PROBE665_WIDTH => 1,
C_PROBE666_WIDTH => 1,
C_PROBE667_WIDTH => 1,
C_PROBE668_WIDTH => 1,
C_PROBE669_WIDTH => 1,
C_PROBE670_WIDTH => 1,
C_PROBE671_WIDTH => 1,
C_PROBE672_WIDTH => 1,
C_PROBE673_WIDTH => 1,
C_PROBE674_WIDTH => 1,
C_PROBE675_WIDTH => 1,
C_PROBE676_WIDTH => 1,
C_PROBE677_WIDTH => 1,
C_PROBE678_WIDTH => 1,
C_PROBE679_WIDTH => 1,
C_PROBE680_WIDTH => 1,
C_PROBE681_WIDTH => 1,
C_PROBE682_WIDTH => 1,
C_PROBE683_WIDTH => 1,
C_PROBE684_WIDTH => 1,
C_PROBE685_WIDTH => 1,
C_PROBE686_WIDTH => 1,
C_PROBE687_WIDTH => 1,
C_PROBE688_WIDTH => 1,
C_PROBE689_WIDTH => 1,
C_PROBE690_WIDTH => 1,
C_PROBE691_WIDTH => 1,
C_PROBE692_WIDTH => 1,
C_PROBE693_WIDTH => 1,
C_PROBE694_WIDTH => 1,
C_PROBE695_WIDTH => 1,
C_PROBE696_WIDTH => 1,
C_PROBE697_WIDTH => 1,
C_PROBE698_WIDTH => 1,
C_PROBE699_WIDTH => 1,
C_PROBE700_WIDTH => 1,
C_PROBE701_WIDTH => 1,
C_PROBE702_WIDTH => 1,
C_PROBE703_WIDTH => 1,
C_PROBE704_WIDTH => 1,
C_PROBE705_WIDTH => 1,
C_PROBE706_WIDTH => 1,
C_PROBE707_WIDTH => 1,
C_PROBE708_WIDTH => 1,
C_PROBE709_WIDTH => 1,
C_PROBE710_WIDTH => 1,
C_PROBE711_WIDTH => 1,
C_PROBE712_WIDTH => 1,
C_PROBE713_WIDTH => 1,
C_PROBE714_WIDTH => 1,
C_PROBE715_WIDTH => 1,
C_PROBE716_WIDTH => 1,
C_PROBE717_WIDTH => 1,
C_PROBE718_WIDTH => 1,
C_PROBE719_WIDTH => 1,
C_PROBE720_WIDTH => 1,
C_PROBE721_WIDTH => 1,
C_PROBE722_WIDTH => 1,
C_PROBE723_WIDTH => 1,
C_PROBE724_WIDTH => 1,
C_PROBE725_WIDTH => 1,
C_PROBE726_WIDTH => 1,
C_PROBE727_WIDTH => 1,
C_PROBE728_WIDTH => 1,
C_PROBE729_WIDTH => 1,
C_PROBE730_WIDTH => 1,
C_PROBE731_WIDTH => 1,
C_PROBE732_WIDTH => 1,
C_PROBE733_WIDTH => 1,
C_PROBE734_WIDTH => 1,
C_PROBE735_WIDTH => 1,
C_PROBE736_WIDTH => 1,
C_PROBE737_WIDTH => 1,
C_PROBE738_WIDTH => 1,
C_PROBE739_WIDTH => 1,
C_PROBE740_WIDTH => 1,
C_PROBE741_WIDTH => 1,
C_PROBE742_WIDTH => 1,
C_PROBE743_WIDTH => 1,
C_PROBE744_WIDTH => 1,
C_PROBE745_WIDTH => 1,
C_PROBE746_WIDTH => 1,
C_PROBE747_WIDTH => 1,
C_PROBE748_WIDTH => 1,
C_PROBE749_WIDTH => 1,
C_PROBE750_WIDTH => 1,
C_PROBE751_WIDTH => 1,
C_PROBE752_WIDTH => 1,
C_PROBE753_WIDTH => 1,
C_PROBE754_WIDTH => 1,
C_PROBE755_WIDTH => 1,
C_PROBE756_WIDTH => 1,
C_PROBE757_WIDTH => 1,
C_PROBE758_WIDTH => 1,
C_PROBE759_WIDTH => 1,
C_PROBE760_WIDTH => 1,
C_PROBE761_WIDTH => 1,
C_PROBE762_WIDTH => 1,
C_PROBE763_WIDTH => 1,
C_PROBE764_WIDTH => 1,
C_PROBE765_WIDTH => 1,
C_PROBE766_WIDTH => 1,
C_PROBE767_WIDTH => 1,
C_PROBE768_WIDTH => 1,
C_PROBE769_WIDTH => 1,
C_PROBE770_WIDTH => 1,
C_PROBE771_WIDTH => 1,
C_PROBE772_WIDTH => 1,
C_PROBE773_WIDTH => 1,
C_PROBE774_WIDTH => 1,
C_PROBE775_WIDTH => 1,
C_PROBE776_WIDTH => 1,
C_PROBE777_WIDTH => 1,
C_PROBE778_WIDTH => 1,
C_PROBE779_WIDTH => 1,
C_PROBE780_WIDTH => 1,
C_PROBE781_WIDTH => 1,
C_PROBE782_WIDTH => 1,
C_PROBE783_WIDTH => 1,
C_PROBE784_WIDTH => 1,
C_PROBE785_WIDTH => 1,
C_PROBE786_WIDTH => 1,
C_PROBE787_WIDTH => 1,
C_PROBE788_WIDTH => 1,
C_PROBE789_WIDTH => 1,
C_PROBE790_WIDTH => 1,
C_PROBE791_WIDTH => 1,
C_PROBE792_WIDTH => 1,
C_PROBE793_WIDTH => 1,
C_PROBE794_WIDTH => 1,
C_PROBE795_WIDTH => 1,
C_PROBE796_WIDTH => 1,
C_PROBE797_WIDTH => 1,
C_PROBE798_WIDTH => 1,
C_PROBE799_WIDTH => 1,
C_PROBE800_WIDTH => 1,
C_PROBE801_WIDTH => 1,
C_PROBE802_WIDTH => 1,
C_PROBE803_WIDTH => 1,
C_PROBE804_WIDTH => 1,
C_PROBE805_WIDTH => 1,
C_PROBE806_WIDTH => 1,
C_PROBE807_WIDTH => 1,
C_PROBE808_WIDTH => 1,
C_PROBE809_WIDTH => 1,
C_PROBE810_WIDTH => 1,
C_PROBE811_WIDTH => 1,
C_PROBE812_WIDTH => 1,
C_PROBE813_WIDTH => 1,
C_PROBE814_WIDTH => 1,
C_PROBE815_WIDTH => 1,
C_PROBE816_WIDTH => 1,
C_PROBE817_WIDTH => 1,
C_PROBE818_WIDTH => 1,
C_PROBE819_WIDTH => 1,
C_PROBE820_WIDTH => 1,
C_PROBE821_WIDTH => 1,
C_PROBE822_WIDTH => 1,
C_PROBE823_WIDTH => 1,
C_PROBE824_WIDTH => 1,
C_PROBE825_WIDTH => 1,
C_PROBE826_WIDTH => 1,
C_PROBE827_WIDTH => 1,
C_PROBE828_WIDTH => 1,
C_PROBE829_WIDTH => 1,
C_PROBE830_WIDTH => 1,
C_PROBE831_WIDTH => 1,
C_PROBE832_WIDTH => 1,
C_PROBE833_WIDTH => 1,
C_PROBE834_WIDTH => 1,
C_PROBE835_WIDTH => 1,
C_PROBE836_WIDTH => 1,
C_PROBE837_WIDTH => 1,
C_PROBE838_WIDTH => 1,
C_PROBE839_WIDTH => 1,
C_PROBE840_WIDTH => 1,
C_PROBE841_WIDTH => 1,
C_PROBE842_WIDTH => 1,
C_PROBE843_WIDTH => 1,
C_PROBE844_WIDTH => 1,
C_PROBE845_WIDTH => 1,
C_PROBE846_WIDTH => 1,
C_PROBE847_WIDTH => 1,
C_PROBE848_WIDTH => 1,
C_PROBE849_WIDTH => 1,
C_PROBE850_WIDTH => 1,
C_PROBE851_WIDTH => 1,
C_PROBE852_WIDTH => 1,
C_PROBE853_WIDTH => 1,
C_PROBE854_WIDTH => 1,
C_PROBE855_WIDTH => 1,
C_PROBE856_WIDTH => 1,
C_PROBE857_WIDTH => 1,
C_PROBE858_WIDTH => 1,
C_PROBE859_WIDTH => 1,
C_PROBE860_WIDTH => 1,
C_PROBE861_WIDTH => 1,
C_PROBE862_WIDTH => 1,
C_PROBE863_WIDTH => 1,
C_PROBE864_WIDTH => 1,
C_PROBE865_WIDTH => 1,
C_PROBE866_WIDTH => 1,
C_PROBE867_WIDTH => 1,
C_PROBE868_WIDTH => 1,
C_PROBE869_WIDTH => 1,
C_PROBE870_WIDTH => 1,
C_PROBE871_WIDTH => 1,
C_PROBE872_WIDTH => 1,
C_PROBE873_WIDTH => 1,
C_PROBE874_WIDTH => 1,
C_PROBE875_WIDTH => 1,
C_PROBE876_WIDTH => 1,
C_PROBE877_WIDTH => 1,
C_PROBE878_WIDTH => 1,
C_PROBE879_WIDTH => 1,
C_PROBE880_WIDTH => 1,
C_PROBE881_WIDTH => 1,
C_PROBE882_WIDTH => 1,
C_PROBE883_WIDTH => 1,
C_PROBE884_WIDTH => 1,
C_PROBE885_WIDTH => 1,
C_PROBE886_WIDTH => 1,
C_PROBE887_WIDTH => 1,
C_PROBE888_WIDTH => 1,
C_PROBE889_WIDTH => 1,
C_PROBE890_WIDTH => 1,
C_PROBE891_WIDTH => 1,
C_PROBE892_WIDTH => 1,
C_PROBE893_WIDTH => 1,
C_PROBE894_WIDTH => 1,
C_PROBE895_WIDTH => 1,
C_PROBE896_WIDTH => 1,
C_PROBE897_WIDTH => 1,
C_PROBE898_WIDTH => 1,
C_PROBE899_WIDTH => 1,
C_PROBE900_WIDTH => 1,
C_PROBE901_WIDTH => 1,
C_PROBE902_WIDTH => 1,
C_PROBE903_WIDTH => 1,
C_PROBE904_WIDTH => 1,
C_PROBE905_WIDTH => 1,
C_PROBE906_WIDTH => 1,
C_PROBE907_WIDTH => 1,
C_PROBE908_WIDTH => 1,
C_PROBE909_WIDTH => 1,
C_PROBE910_WIDTH => 1,
C_PROBE911_WIDTH => 1,
C_PROBE912_WIDTH => 1,
C_PROBE913_WIDTH => 1,
C_PROBE914_WIDTH => 1,
C_PROBE915_WIDTH => 1,
C_PROBE916_WIDTH => 1,
C_PROBE917_WIDTH => 1,
C_PROBE918_WIDTH => 1,
C_PROBE919_WIDTH => 1,
C_PROBE920_WIDTH => 1,
C_PROBE921_WIDTH => 1,
C_PROBE922_WIDTH => 1,
C_PROBE923_WIDTH => 1,
C_PROBE924_WIDTH => 1,
C_PROBE925_WIDTH => 1,
C_PROBE926_WIDTH => 1,
C_PROBE927_WIDTH => 1,
C_PROBE928_WIDTH => 1,
C_PROBE929_WIDTH => 1,
C_PROBE930_WIDTH => 1,
C_PROBE931_WIDTH => 1,
C_PROBE932_WIDTH => 1,
C_PROBE933_WIDTH => 1,
C_PROBE934_WIDTH => 1,
C_PROBE935_WIDTH => 1,
C_PROBE936_WIDTH => 1,
C_PROBE937_WIDTH => 1,
C_PROBE938_WIDTH => 1,
C_PROBE939_WIDTH => 1,
C_PROBE940_WIDTH => 1,
C_PROBE941_WIDTH => 1,
C_PROBE942_WIDTH => 1,
C_PROBE943_WIDTH => 1,
C_PROBE944_WIDTH => 1,
C_PROBE945_WIDTH => 1,
C_PROBE946_WIDTH => 1,
C_PROBE947_WIDTH => 1,
C_PROBE948_WIDTH => 1,
C_PROBE949_WIDTH => 1,
C_PROBE950_WIDTH => 1,
C_PROBE951_WIDTH => 1,
C_PROBE952_WIDTH => 1,
C_PROBE953_WIDTH => 1,
C_PROBE954_WIDTH => 1,
C_PROBE955_WIDTH => 1,
C_PROBE956_WIDTH => 1,
C_PROBE957_WIDTH => 1,
C_PROBE958_WIDTH => 1,
C_PROBE959_WIDTH => 1,
C_PROBE960_WIDTH => 1,
C_PROBE961_WIDTH => 1,
C_PROBE962_WIDTH => 1,
C_PROBE963_WIDTH => 1,
C_PROBE964_WIDTH => 1,
C_PROBE965_WIDTH => 1,
C_PROBE966_WIDTH => 1,
C_PROBE967_WIDTH => 1,
C_PROBE968_WIDTH => 1,
C_PROBE969_WIDTH => 1,
C_PROBE970_WIDTH => 1,
C_PROBE971_WIDTH => 1,
C_PROBE972_WIDTH => 1,
C_PROBE973_WIDTH => 1,
C_PROBE974_WIDTH => 1,
C_PROBE975_WIDTH => 1,
C_PROBE976_WIDTH => 1,
C_PROBE977_WIDTH => 1,
C_PROBE978_WIDTH => 1,
C_PROBE979_WIDTH => 1,
C_PROBE980_WIDTH => 1,
C_PROBE981_WIDTH => 1,
C_PROBE982_WIDTH => 1,
C_PROBE983_WIDTH => 1,
C_PROBE984_WIDTH => 1,
C_PROBE985_WIDTH => 1,
C_PROBE986_WIDTH => 1,
C_PROBE987_WIDTH => 1,
C_PROBE988_WIDTH => 1,
C_PROBE989_WIDTH => 1,
C_PROBE990_WIDTH => 1,
C_PROBE991_WIDTH => 1,
C_PROBE992_WIDTH => 1,
C_PROBE993_WIDTH => 1,
C_PROBE994_WIDTH => 1,
C_PROBE995_WIDTH => 1,
C_PROBE996_WIDTH => 1,
C_PROBE997_WIDTH => 1,
C_PROBE998_WIDTH => 1,
C_PROBE999_WIDTH => 1,
C_PROBE1000_WIDTH => 1,
C_PROBE1001_WIDTH => 1,
C_PROBE1002_WIDTH => 1,
C_PROBE1003_WIDTH => 1,
C_PROBE1004_WIDTH => 1,
C_PROBE1005_WIDTH => 1,
C_PROBE1006_WIDTH => 1,
C_PROBE1007_WIDTH => 1,
C_PROBE1008_WIDTH => 1,
C_PROBE1009_WIDTH => 1,
C_PROBE1010_WIDTH => 1,
C_PROBE1011_WIDTH => 1,
C_PROBE1012_WIDTH => 1,
C_PROBE1013_WIDTH => 1,
C_PROBE1014_WIDTH => 1,
C_PROBE1015_WIDTH => 1,
C_PROBE1016_WIDTH => 1,
C_PROBE1017_WIDTH => 1,
C_PROBE1018_WIDTH => 1,
C_PROBE1019_WIDTH => 1,
C_PROBE1020_WIDTH => 1,
C_PROBE1021_WIDTH => 1,
C_PROBE1022_WIDTH => 1,
C_PROBE1023_WIDTH => 1,
C_PROBE0_MU_CNT => 2,
C_PROBE1_MU_CNT => 2,
C_PROBE2_MU_CNT => 2,
C_PROBE3_MU_CNT => 2,
C_PROBE4_MU_CNT => 1,
C_PROBE5_MU_CNT => 1,
C_PROBE6_MU_CNT => 1,
C_PROBE7_MU_CNT => 1,
C_PROBE8_MU_CNT => 1,
C_PROBE9_MU_CNT => 1,
C_PROBE10_MU_CNT => 1,
C_PROBE11_MU_CNT => 1,
C_PROBE12_MU_CNT => 1,
C_PROBE13_MU_CNT => 1,
C_PROBE14_MU_CNT => 1,
C_PROBE15_MU_CNT => 1,
C_PROBE16_MU_CNT => 1,
C_PROBE17_MU_CNT => 1,
C_PROBE18_MU_CNT => 1,
C_PROBE19_MU_CNT => 1,
C_PROBE20_MU_CNT => 1,
C_PROBE21_MU_CNT => 1,
C_PROBE22_MU_CNT => 1,
C_PROBE23_MU_CNT => 1,
C_PROBE24_MU_CNT => 1,
C_PROBE25_MU_CNT => 1,
C_PROBE26_MU_CNT => 1,
C_PROBE27_MU_CNT => 1,
C_PROBE28_MU_CNT => 1,
C_PROBE29_MU_CNT => 1,
C_PROBE30_MU_CNT => 1,
C_PROBE31_MU_CNT => 1,
C_PROBE32_MU_CNT => 1,
C_PROBE33_MU_CNT => 1,
C_PROBE34_MU_CNT => 1,
C_PROBE35_MU_CNT => 1,
C_PROBE36_MU_CNT => 1,
C_PROBE37_MU_CNT => 1,
C_PROBE38_MU_CNT => 1,
C_PROBE39_MU_CNT => 1,
C_PROBE40_MU_CNT => 1,
C_PROBE41_MU_CNT => 1,
C_PROBE42_MU_CNT => 1,
C_PROBE43_MU_CNT => 1,
C_PROBE44_MU_CNT => 1,
C_PROBE45_MU_CNT => 1,
C_PROBE46_MU_CNT => 1,
C_PROBE47_MU_CNT => 1,
C_PROBE48_MU_CNT => 1,
C_PROBE49_MU_CNT => 1,
C_PROBE50_MU_CNT => 1,
C_PROBE51_MU_CNT => 1,
C_PROBE52_MU_CNT => 1,
C_PROBE53_MU_CNT => 1,
C_PROBE54_MU_CNT => 1,
C_PROBE55_MU_CNT => 1,
C_PROBE56_MU_CNT => 1,
C_PROBE57_MU_CNT => 1,
C_PROBE58_MU_CNT => 1,
C_PROBE59_MU_CNT => 1,
C_PROBE60_MU_CNT => 1,
C_PROBE61_MU_CNT => 1,
C_PROBE62_MU_CNT => 1,
C_PROBE63_MU_CNT => 1,
C_PROBE64_MU_CNT => 1,
C_PROBE65_MU_CNT => 1,
C_PROBE66_MU_CNT => 1,
C_PROBE67_MU_CNT => 1,
C_PROBE68_MU_CNT => 1,
C_PROBE69_MU_CNT => 1,
C_PROBE70_MU_CNT => 1,
C_PROBE71_MU_CNT => 1,
C_PROBE72_MU_CNT => 1,
C_PROBE73_MU_CNT => 1,
C_PROBE74_MU_CNT => 1,
C_PROBE75_MU_CNT => 1,
C_PROBE76_MU_CNT => 1,
C_PROBE77_MU_CNT => 1,
C_PROBE78_MU_CNT => 1,
C_PROBE79_MU_CNT => 1,
C_PROBE80_MU_CNT => 1,
C_PROBE81_MU_CNT => 1,
C_PROBE82_MU_CNT => 1,
C_PROBE83_MU_CNT => 1,
C_PROBE84_MU_CNT => 1,
C_PROBE85_MU_CNT => 1,
C_PROBE86_MU_CNT => 1,
C_PROBE87_MU_CNT => 1,
C_PROBE88_MU_CNT => 1,
C_PROBE89_MU_CNT => 1,
C_PROBE90_MU_CNT => 1,
C_PROBE91_MU_CNT => 1,
C_PROBE92_MU_CNT => 1,
C_PROBE93_MU_CNT => 1,
C_PROBE94_MU_CNT => 1,
C_PROBE95_MU_CNT => 1,
C_PROBE96_MU_CNT => 1,
C_PROBE97_MU_CNT => 1,
C_PROBE98_MU_CNT => 1,
C_PROBE99_MU_CNT => 1,
C_PROBE100_MU_CNT => 1,
C_PROBE101_MU_CNT => 1,
C_PROBE102_MU_CNT => 1,
C_PROBE103_MU_CNT => 1,
C_PROBE104_MU_CNT => 1,
C_PROBE105_MU_CNT => 1,
C_PROBE106_MU_CNT => 1,
C_PROBE107_MU_CNT => 1,
C_PROBE108_MU_CNT => 1,
C_PROBE109_MU_CNT => 1,
C_PROBE110_MU_CNT => 1,
C_PROBE111_MU_CNT => 1,
C_PROBE112_MU_CNT => 1,
C_PROBE113_MU_CNT => 1,
C_PROBE114_MU_CNT => 1,
C_PROBE115_MU_CNT => 1,
C_PROBE116_MU_CNT => 1,
C_PROBE117_MU_CNT => 1,
C_PROBE118_MU_CNT => 1,
C_PROBE119_MU_CNT => 1,
C_PROBE120_MU_CNT => 1,
C_PROBE121_MU_CNT => 1,
C_PROBE122_MU_CNT => 1,
C_PROBE123_MU_CNT => 1,
C_PROBE124_MU_CNT => 1,
C_PROBE125_MU_CNT => 1,
C_PROBE126_MU_CNT => 1,
C_PROBE127_MU_CNT => 1,
C_PROBE128_MU_CNT => 1,
C_PROBE129_MU_CNT => 1,
C_PROBE130_MU_CNT => 1,
C_PROBE131_MU_CNT => 1,
C_PROBE132_MU_CNT => 1,
C_PROBE133_MU_CNT => 1,
C_PROBE134_MU_CNT => 1,
C_PROBE135_MU_CNT => 1,
C_PROBE136_MU_CNT => 1,
C_PROBE137_MU_CNT => 1,
C_PROBE138_MU_CNT => 1,
C_PROBE139_MU_CNT => 1,
C_PROBE140_MU_CNT => 1,
C_PROBE141_MU_CNT => 1,
C_PROBE142_MU_CNT => 1,
C_PROBE143_MU_CNT => 1,
C_PROBE144_MU_CNT => 1,
C_PROBE145_MU_CNT => 1,
C_PROBE146_MU_CNT => 1,
C_PROBE147_MU_CNT => 1,
C_PROBE148_MU_CNT => 1,
C_PROBE149_MU_CNT => 1,
C_PROBE150_MU_CNT => 1,
C_PROBE151_MU_CNT => 1,
C_PROBE152_MU_CNT => 1,
C_PROBE153_MU_CNT => 1,
C_PROBE154_MU_CNT => 1,
C_PROBE155_MU_CNT => 1,
C_PROBE156_MU_CNT => 1,
C_PROBE157_MU_CNT => 1,
C_PROBE158_MU_CNT => 1,
C_PROBE159_MU_CNT => 1,
C_PROBE160_MU_CNT => 1,
C_PROBE161_MU_CNT => 1,
C_PROBE162_MU_CNT => 1,
C_PROBE163_MU_CNT => 1,
C_PROBE164_MU_CNT => 1,
C_PROBE165_MU_CNT => 1,
C_PROBE166_MU_CNT => 1,
C_PROBE167_MU_CNT => 1,
C_PROBE168_MU_CNT => 1,
C_PROBE169_MU_CNT => 1,
C_PROBE170_MU_CNT => 1,
C_PROBE171_MU_CNT => 1,
C_PROBE172_MU_CNT => 1,
C_PROBE173_MU_CNT => 1,
C_PROBE174_MU_CNT => 1,
C_PROBE175_MU_CNT => 1,
C_PROBE176_MU_CNT => 1,
C_PROBE177_MU_CNT => 1,
C_PROBE178_MU_CNT => 1,
C_PROBE179_MU_CNT => 1,
C_PROBE180_MU_CNT => 1,
C_PROBE181_MU_CNT => 1,
C_PROBE182_MU_CNT => 1,
C_PROBE183_MU_CNT => 1,
C_PROBE184_MU_CNT => 1,
C_PROBE185_MU_CNT => 1,
C_PROBE186_MU_CNT => 1,
C_PROBE187_MU_CNT => 1,
C_PROBE188_MU_CNT => 1,
C_PROBE189_MU_CNT => 1,
C_PROBE190_MU_CNT => 1,
C_PROBE191_MU_CNT => 1,
C_PROBE192_MU_CNT => 1,
C_PROBE193_MU_CNT => 1,
C_PROBE194_MU_CNT => 1,
C_PROBE195_MU_CNT => 1,
C_PROBE196_MU_CNT => 1,
C_PROBE197_MU_CNT => 1,
C_PROBE198_MU_CNT => 1,
C_PROBE199_MU_CNT => 1,
C_PROBE200_MU_CNT => 1,
C_PROBE201_MU_CNT => 1,
C_PROBE202_MU_CNT => 1,
C_PROBE203_MU_CNT => 1,
C_PROBE204_MU_CNT => 1,
C_PROBE205_MU_CNT => 1,
C_PROBE206_MU_CNT => 1,
C_PROBE207_MU_CNT => 1,
C_PROBE208_MU_CNT => 1,
C_PROBE209_MU_CNT => 1,
C_PROBE210_MU_CNT => 1,
C_PROBE211_MU_CNT => 1,
C_PROBE212_MU_CNT => 1,
C_PROBE213_MU_CNT => 1,
C_PROBE214_MU_CNT => 1,
C_PROBE215_MU_CNT => 1,
C_PROBE216_MU_CNT => 1,
C_PROBE217_MU_CNT => 1,
C_PROBE218_MU_CNT => 1,
C_PROBE219_MU_CNT => 1,
C_PROBE220_MU_CNT => 1,
C_PROBE221_MU_CNT => 1,
C_PROBE222_MU_CNT => 1,
C_PROBE223_MU_CNT => 1,
C_PROBE224_MU_CNT => 1,
C_PROBE225_MU_CNT => 1,
C_PROBE226_MU_CNT => 1,
C_PROBE227_MU_CNT => 1,
C_PROBE228_MU_CNT => 1,
C_PROBE229_MU_CNT => 1,
C_PROBE230_MU_CNT => 1,
C_PROBE231_MU_CNT => 1,
C_PROBE232_MU_CNT => 1,
C_PROBE233_MU_CNT => 1,
C_PROBE234_MU_CNT => 1,
C_PROBE235_MU_CNT => 1,
C_PROBE236_MU_CNT => 1,
C_PROBE237_MU_CNT => 1,
C_PROBE238_MU_CNT => 1,
C_PROBE239_MU_CNT => 1,
C_PROBE240_MU_CNT => 1,
C_PROBE241_MU_CNT => 1,
C_PROBE242_MU_CNT => 1,
C_PROBE243_MU_CNT => 1,
C_PROBE244_MU_CNT => 1,
C_PROBE245_MU_CNT => 1,
C_PROBE246_MU_CNT => 1,
C_PROBE247_MU_CNT => 1,
C_PROBE248_MU_CNT => 1,
C_PROBE249_MU_CNT => 1,
C_PROBE250_MU_CNT => 1,
C_PROBE251_MU_CNT => 1,
C_PROBE252_MU_CNT => 1,
C_PROBE253_MU_CNT => 1,
C_PROBE254_MU_CNT => 1,
C_PROBE255_MU_CNT => 1,
C_PROBE256_MU_CNT => 1,
C_PROBE257_MU_CNT => 1,
C_PROBE258_MU_CNT => 1,
C_PROBE259_MU_CNT => 1,
C_PROBE260_MU_CNT => 1,
C_PROBE261_MU_CNT => 1,
C_PROBE262_MU_CNT => 1,
C_PROBE263_MU_CNT => 1,
C_PROBE264_MU_CNT => 1,
C_PROBE265_MU_CNT => 1,
C_PROBE266_MU_CNT => 1,
C_PROBE267_MU_CNT => 1,
C_PROBE268_MU_CNT => 1,
C_PROBE269_MU_CNT => 1,
C_PROBE270_MU_CNT => 1,
C_PROBE271_MU_CNT => 1,
C_PROBE272_MU_CNT => 1,
C_PROBE273_MU_CNT => 1,
C_PROBE274_MU_CNT => 1,
C_PROBE275_MU_CNT => 1,
C_PROBE276_MU_CNT => 1,
C_PROBE277_MU_CNT => 1,
C_PROBE278_MU_CNT => 1,
C_PROBE279_MU_CNT => 1,
C_PROBE280_MU_CNT => 1,
C_PROBE281_MU_CNT => 1,
C_PROBE282_MU_CNT => 1,
C_PROBE283_MU_CNT => 1,
C_PROBE284_MU_CNT => 1,
C_PROBE285_MU_CNT => 1,
C_PROBE286_MU_CNT => 1,
C_PROBE287_MU_CNT => 1,
C_PROBE288_MU_CNT => 1,
C_PROBE289_MU_CNT => 1,
C_PROBE290_MU_CNT => 1,
C_PROBE291_MU_CNT => 1,
C_PROBE292_MU_CNT => 1,
C_PROBE293_MU_CNT => 1,
C_PROBE294_MU_CNT => 1,
C_PROBE295_MU_CNT => 1,
C_PROBE296_MU_CNT => 1,
C_PROBE297_MU_CNT => 1,
C_PROBE298_MU_CNT => 1,
C_PROBE299_MU_CNT => 1,
C_PROBE300_MU_CNT => 1,
C_PROBE301_MU_CNT => 1,
C_PROBE302_MU_CNT => 1,
C_PROBE303_MU_CNT => 1,
C_PROBE304_MU_CNT => 1,
C_PROBE305_MU_CNT => 1,
C_PROBE306_MU_CNT => 1,
C_PROBE307_MU_CNT => 1,
C_PROBE308_MU_CNT => 1,
C_PROBE309_MU_CNT => 1,
C_PROBE310_MU_CNT => 1,
C_PROBE311_MU_CNT => 1,
C_PROBE312_MU_CNT => 1,
C_PROBE313_MU_CNT => 1,
C_PROBE314_MU_CNT => 1,
C_PROBE315_MU_CNT => 1,
C_PROBE316_MU_CNT => 1,
C_PROBE317_MU_CNT => 1,
C_PROBE318_MU_CNT => 1,
C_PROBE319_MU_CNT => 1,
C_PROBE320_MU_CNT => 1,
C_PROBE321_MU_CNT => 1,
C_PROBE322_MU_CNT => 1,
C_PROBE323_MU_CNT => 1,
C_PROBE324_MU_CNT => 1,
C_PROBE325_MU_CNT => 1,
C_PROBE326_MU_CNT => 1,
C_PROBE327_MU_CNT => 1,
C_PROBE328_MU_CNT => 1,
C_PROBE329_MU_CNT => 1,
C_PROBE330_MU_CNT => 1,
C_PROBE331_MU_CNT => 1,
C_PROBE332_MU_CNT => 1,
C_PROBE333_MU_CNT => 1,
C_PROBE334_MU_CNT => 1,
C_PROBE335_MU_CNT => 1,
C_PROBE336_MU_CNT => 1,
C_PROBE337_MU_CNT => 1,
C_PROBE338_MU_CNT => 1,
C_PROBE339_MU_CNT => 1,
C_PROBE340_MU_CNT => 1,
C_PROBE341_MU_CNT => 1,
C_PROBE342_MU_CNT => 1,
C_PROBE343_MU_CNT => 1,
C_PROBE344_MU_CNT => 1,
C_PROBE345_MU_CNT => 1,
C_PROBE346_MU_CNT => 1,
C_PROBE347_MU_CNT => 1,
C_PROBE348_MU_CNT => 1,
C_PROBE349_MU_CNT => 1,
C_PROBE350_MU_CNT => 1,
C_PROBE351_MU_CNT => 1,
C_PROBE352_MU_CNT => 1,
C_PROBE353_MU_CNT => 1,
C_PROBE354_MU_CNT => 1,
C_PROBE355_MU_CNT => 1,
C_PROBE356_MU_CNT => 1,
C_PROBE357_MU_CNT => 1,
C_PROBE358_MU_CNT => 1,
C_PROBE359_MU_CNT => 1,
C_PROBE360_MU_CNT => 1,
C_PROBE361_MU_CNT => 1,
C_PROBE362_MU_CNT => 1,
C_PROBE363_MU_CNT => 1,
C_PROBE364_MU_CNT => 1,
C_PROBE365_MU_CNT => 1,
C_PROBE366_MU_CNT => 1,
C_PROBE367_MU_CNT => 1,
C_PROBE368_MU_CNT => 1,
C_PROBE369_MU_CNT => 1,
C_PROBE370_MU_CNT => 1,
C_PROBE371_MU_CNT => 1,
C_PROBE372_MU_CNT => 1,
C_PROBE373_MU_CNT => 1,
C_PROBE374_MU_CNT => 1,
C_PROBE375_MU_CNT => 1,
C_PROBE376_MU_CNT => 1,
C_PROBE377_MU_CNT => 1,
C_PROBE378_MU_CNT => 1,
C_PROBE379_MU_CNT => 1,
C_PROBE380_MU_CNT => 1,
C_PROBE381_MU_CNT => 1,
C_PROBE382_MU_CNT => 1,
C_PROBE383_MU_CNT => 1,
C_PROBE384_MU_CNT => 1,
C_PROBE385_MU_CNT => 1,
C_PROBE386_MU_CNT => 1,
C_PROBE387_MU_CNT => 1,
C_PROBE388_MU_CNT => 1,
C_PROBE389_MU_CNT => 1,
C_PROBE390_MU_CNT => 1,
C_PROBE391_MU_CNT => 1,
C_PROBE392_MU_CNT => 1,
C_PROBE393_MU_CNT => 1,
C_PROBE394_MU_CNT => 1,
C_PROBE395_MU_CNT => 1,
C_PROBE396_MU_CNT => 1,
C_PROBE397_MU_CNT => 1,
C_PROBE398_MU_CNT => 1,
C_PROBE399_MU_CNT => 1,
C_PROBE400_MU_CNT => 1,
C_PROBE401_MU_CNT => 1,
C_PROBE402_MU_CNT => 1,
C_PROBE403_MU_CNT => 1,
C_PROBE404_MU_CNT => 1,
C_PROBE405_MU_CNT => 1,
C_PROBE406_MU_CNT => 1,
C_PROBE407_MU_CNT => 1,
C_PROBE408_MU_CNT => 1,
C_PROBE409_MU_CNT => 1,
C_PROBE410_MU_CNT => 1,
C_PROBE411_MU_CNT => 1,
C_PROBE412_MU_CNT => 1,
C_PROBE413_MU_CNT => 1,
C_PROBE414_MU_CNT => 1,
C_PROBE415_MU_CNT => 1,
C_PROBE416_MU_CNT => 1,
C_PROBE417_MU_CNT => 1,
C_PROBE418_MU_CNT => 1,
C_PROBE419_MU_CNT => 1,
C_PROBE420_MU_CNT => 1,
C_PROBE421_MU_CNT => 1,
C_PROBE422_MU_CNT => 1,
C_PROBE423_MU_CNT => 1,
C_PROBE424_MU_CNT => 1,
C_PROBE425_MU_CNT => 1,
C_PROBE426_MU_CNT => 1,
C_PROBE427_MU_CNT => 1,
C_PROBE428_MU_CNT => 1,
C_PROBE429_MU_CNT => 1,
C_PROBE430_MU_CNT => 1,
C_PROBE431_MU_CNT => 1,
C_PROBE432_MU_CNT => 1,
C_PROBE433_MU_CNT => 1,
C_PROBE434_MU_CNT => 1,
C_PROBE435_MU_CNT => 1,
C_PROBE436_MU_CNT => 1,
C_PROBE437_MU_CNT => 1,
C_PROBE438_MU_CNT => 1,
C_PROBE439_MU_CNT => 1,
C_PROBE440_MU_CNT => 1,
C_PROBE441_MU_CNT => 1,
C_PROBE442_MU_CNT => 1,
C_PROBE443_MU_CNT => 1,
C_PROBE444_MU_CNT => 1,
C_PROBE445_MU_CNT => 1,
C_PROBE446_MU_CNT => 1,
C_PROBE447_MU_CNT => 1,
C_PROBE448_MU_CNT => 1,
C_PROBE449_MU_CNT => 1,
C_PROBE450_MU_CNT => 1,
C_PROBE451_MU_CNT => 1,
C_PROBE452_MU_CNT => 1,
C_PROBE453_MU_CNT => 1,
C_PROBE454_MU_CNT => 1,
C_PROBE455_MU_CNT => 1,
C_PROBE456_MU_CNT => 1,
C_PROBE457_MU_CNT => 1,
C_PROBE458_MU_CNT => 1,
C_PROBE459_MU_CNT => 1,
C_PROBE460_MU_CNT => 1,
C_PROBE461_MU_CNT => 1,
C_PROBE462_MU_CNT => 1,
C_PROBE463_MU_CNT => 1,
C_PROBE464_MU_CNT => 1,
C_PROBE465_MU_CNT => 1,
C_PROBE466_MU_CNT => 1,
C_PROBE467_MU_CNT => 1,
C_PROBE468_MU_CNT => 1,
C_PROBE469_MU_CNT => 1,
C_PROBE470_MU_CNT => 1,
C_PROBE471_MU_CNT => 1,
C_PROBE472_MU_CNT => 1,
C_PROBE473_MU_CNT => 1,
C_PROBE474_MU_CNT => 1,
C_PROBE475_MU_CNT => 1,
C_PROBE476_MU_CNT => 1,
C_PROBE477_MU_CNT => 1,
C_PROBE478_MU_CNT => 1,
C_PROBE479_MU_CNT => 1,
C_PROBE480_MU_CNT => 1,
C_PROBE481_MU_CNT => 1,
C_PROBE482_MU_CNT => 1,
C_PROBE483_MU_CNT => 1,
C_PROBE484_MU_CNT => 1,
C_PROBE485_MU_CNT => 1,
C_PROBE486_MU_CNT => 1,
C_PROBE487_MU_CNT => 1,
C_PROBE488_MU_CNT => 1,
C_PROBE489_MU_CNT => 1,
C_PROBE490_MU_CNT => 1,
C_PROBE491_MU_CNT => 1,
C_PROBE492_MU_CNT => 1,
C_PROBE493_MU_CNT => 1,
C_PROBE494_MU_CNT => 1,
C_PROBE495_MU_CNT => 1,
C_PROBE496_MU_CNT => 1,
C_PROBE497_MU_CNT => 1,
C_PROBE498_MU_CNT => 1,
C_PROBE499_MU_CNT => 1,
C_PROBE500_MU_CNT => 1,
C_PROBE501_MU_CNT => 1,
C_PROBE502_MU_CNT => 1,
C_PROBE503_MU_CNT => 1,
C_PROBE504_MU_CNT => 1,
C_PROBE505_MU_CNT => 1,
C_PROBE506_MU_CNT => 1,
C_PROBE507_MU_CNT => 1,
C_PROBE508_MU_CNT => 1,
C_PROBE509_MU_CNT => 1,
C_PROBE510_MU_CNT => 1,
C_PROBE511_MU_CNT => 1,
C_PROBE512_MU_CNT => 1,
C_PROBE513_MU_CNT => 1,
C_PROBE514_MU_CNT => 1,
C_PROBE515_MU_CNT => 1,
C_PROBE516_MU_CNT => 1,
C_PROBE517_MU_CNT => 1,
C_PROBE518_MU_CNT => 1,
C_PROBE519_MU_CNT => 1,
C_PROBE520_MU_CNT => 1,
C_PROBE521_MU_CNT => 1,
C_PROBE522_MU_CNT => 1,
C_PROBE523_MU_CNT => 1,
C_PROBE524_MU_CNT => 1,
C_PROBE525_MU_CNT => 1,
C_PROBE526_MU_CNT => 1,
C_PROBE527_MU_CNT => 1,
C_PROBE528_MU_CNT => 1,
C_PROBE529_MU_CNT => 1,
C_PROBE530_MU_CNT => 1,
C_PROBE531_MU_CNT => 1,
C_PROBE532_MU_CNT => 1,
C_PROBE533_MU_CNT => 1,
C_PROBE534_MU_CNT => 1,
C_PROBE535_MU_CNT => 1,
C_PROBE536_MU_CNT => 1,
C_PROBE537_MU_CNT => 1,
C_PROBE538_MU_CNT => 1,
C_PROBE539_MU_CNT => 1,
C_PROBE540_MU_CNT => 1,
C_PROBE541_MU_CNT => 1,
C_PROBE542_MU_CNT => 1,
C_PROBE543_MU_CNT => 1,
C_PROBE544_MU_CNT => 1,
C_PROBE545_MU_CNT => 1,
C_PROBE546_MU_CNT => 1,
C_PROBE547_MU_CNT => 1,
C_PROBE548_MU_CNT => 1,
C_PROBE549_MU_CNT => 1,
C_PROBE550_MU_CNT => 1,
C_PROBE551_MU_CNT => 1,
C_PROBE552_MU_CNT => 1,
C_PROBE553_MU_CNT => 1,
C_PROBE554_MU_CNT => 1,
C_PROBE555_MU_CNT => 1,
C_PROBE556_MU_CNT => 1,
C_PROBE557_MU_CNT => 1,
C_PROBE558_MU_CNT => 1,
C_PROBE559_MU_CNT => 1,
C_PROBE560_MU_CNT => 1,
C_PROBE561_MU_CNT => 1,
C_PROBE562_MU_CNT => 1,
C_PROBE563_MU_CNT => 1,
C_PROBE564_MU_CNT => 1,
C_PROBE565_MU_CNT => 1,
C_PROBE566_MU_CNT => 1,
C_PROBE567_MU_CNT => 1,
C_PROBE568_MU_CNT => 1,
C_PROBE569_MU_CNT => 1,
C_PROBE570_MU_CNT => 1,
C_PROBE571_MU_CNT => 1,
C_PROBE572_MU_CNT => 1,
C_PROBE573_MU_CNT => 1,
C_PROBE574_MU_CNT => 1,
C_PROBE575_MU_CNT => 1,
C_PROBE576_MU_CNT => 1,
C_PROBE577_MU_CNT => 1,
C_PROBE578_MU_CNT => 1,
C_PROBE579_MU_CNT => 1,
C_PROBE580_MU_CNT => 1,
C_PROBE581_MU_CNT => 1,
C_PROBE582_MU_CNT => 1,
C_PROBE583_MU_CNT => 1,
C_PROBE584_MU_CNT => 1,
C_PROBE585_MU_CNT => 1,
C_PROBE586_MU_CNT => 1,
C_PROBE587_MU_CNT => 1,
C_PROBE588_MU_CNT => 1,
C_PROBE589_MU_CNT => 1,
C_PROBE590_MU_CNT => 1,
C_PROBE591_MU_CNT => 1,
C_PROBE592_MU_CNT => 1,
C_PROBE593_MU_CNT => 1,
C_PROBE594_MU_CNT => 1,
C_PROBE595_MU_CNT => 1,
C_PROBE596_MU_CNT => 1,
C_PROBE597_MU_CNT => 1,
C_PROBE598_MU_CNT => 1,
C_PROBE599_MU_CNT => 1,
C_PROBE600_MU_CNT => 1,
C_PROBE601_MU_CNT => 1,
C_PROBE602_MU_CNT => 1,
C_PROBE603_MU_CNT => 1,
C_PROBE604_MU_CNT => 1,
C_PROBE605_MU_CNT => 1,
C_PROBE606_MU_CNT => 1,
C_PROBE607_MU_CNT => 1,
C_PROBE608_MU_CNT => 1,
C_PROBE609_MU_CNT => 1,
C_PROBE610_MU_CNT => 1,
C_PROBE611_MU_CNT => 1,
C_PROBE612_MU_CNT => 1,
C_PROBE613_MU_CNT => 1,
C_PROBE614_MU_CNT => 1,
C_PROBE615_MU_CNT => 1,
C_PROBE616_MU_CNT => 1,
C_PROBE617_MU_CNT => 1,
C_PROBE618_MU_CNT => 1,
C_PROBE619_MU_CNT => 1,
C_PROBE620_MU_CNT => 1,
C_PROBE621_MU_CNT => 1,
C_PROBE622_MU_CNT => 1,
C_PROBE623_MU_CNT => 1,
C_PROBE624_MU_CNT => 1,
C_PROBE625_MU_CNT => 1,
C_PROBE626_MU_CNT => 1,
C_PROBE627_MU_CNT => 1,
C_PROBE628_MU_CNT => 1,
C_PROBE629_MU_CNT => 1,
C_PROBE630_MU_CNT => 1,
C_PROBE631_MU_CNT => 1,
C_PROBE632_MU_CNT => 1,
C_PROBE633_MU_CNT => 1,
C_PROBE634_MU_CNT => 1,
C_PROBE635_MU_CNT => 1,
C_PROBE636_MU_CNT => 1,
C_PROBE637_MU_CNT => 1,
C_PROBE638_MU_CNT => 1,
C_PROBE639_MU_CNT => 1,
C_PROBE640_MU_CNT => 1,
C_PROBE641_MU_CNT => 1,
C_PROBE642_MU_CNT => 1,
C_PROBE643_MU_CNT => 1,
C_PROBE644_MU_CNT => 1,
C_PROBE645_MU_CNT => 1,
C_PROBE646_MU_CNT => 1,
C_PROBE647_MU_CNT => 1,
C_PROBE648_MU_CNT => 1,
C_PROBE649_MU_CNT => 1,
C_PROBE650_MU_CNT => 1,
C_PROBE651_MU_CNT => 1,
C_PROBE652_MU_CNT => 1,
C_PROBE653_MU_CNT => 1,
C_PROBE654_MU_CNT => 1,
C_PROBE655_MU_CNT => 1,
C_PROBE656_MU_CNT => 1,
C_PROBE657_MU_CNT => 1,
C_PROBE658_MU_CNT => 1,
C_PROBE659_MU_CNT => 1,
C_PROBE660_MU_CNT => 1,
C_PROBE661_MU_CNT => 1,
C_PROBE662_MU_CNT => 1,
C_PROBE663_MU_CNT => 1,
C_PROBE664_MU_CNT => 1,
C_PROBE665_MU_CNT => 1,
C_PROBE666_MU_CNT => 1,
C_PROBE667_MU_CNT => 1,
C_PROBE668_MU_CNT => 1,
C_PROBE669_MU_CNT => 1,
C_PROBE670_MU_CNT => 1,
C_PROBE671_MU_CNT => 1,
C_PROBE672_MU_CNT => 1,
C_PROBE673_MU_CNT => 1,
C_PROBE674_MU_CNT => 1,
C_PROBE675_MU_CNT => 1,
C_PROBE676_MU_CNT => 1,
C_PROBE677_MU_CNT => 1,
C_PROBE678_MU_CNT => 1,
C_PROBE679_MU_CNT => 1,
C_PROBE680_MU_CNT => 1,
C_PROBE681_MU_CNT => 1,
C_PROBE682_MU_CNT => 1,
C_PROBE683_MU_CNT => 1,
C_PROBE684_MU_CNT => 1,
C_PROBE685_MU_CNT => 1,
C_PROBE686_MU_CNT => 1,
C_PROBE687_MU_CNT => 1,
C_PROBE688_MU_CNT => 1,
C_PROBE689_MU_CNT => 1,
C_PROBE690_MU_CNT => 1,
C_PROBE691_MU_CNT => 1,
C_PROBE692_MU_CNT => 1,
C_PROBE693_MU_CNT => 1,
C_PROBE694_MU_CNT => 1,
C_PROBE695_MU_CNT => 1,
C_PROBE696_MU_CNT => 1,
C_PROBE697_MU_CNT => 1,
C_PROBE698_MU_CNT => 1,
C_PROBE699_MU_CNT => 1,
C_PROBE700_MU_CNT => 1,
C_PROBE701_MU_CNT => 1,
C_PROBE702_MU_CNT => 1,
C_PROBE703_MU_CNT => 1,
C_PROBE704_MU_CNT => 1,
C_PROBE705_MU_CNT => 1,
C_PROBE706_MU_CNT => 1,
C_PROBE707_MU_CNT => 1,
C_PROBE708_MU_CNT => 1,
C_PROBE709_MU_CNT => 1,
C_PROBE710_MU_CNT => 1,
C_PROBE711_MU_CNT => 1,
C_PROBE712_MU_CNT => 1,
C_PROBE713_MU_CNT => 1,
C_PROBE714_MU_CNT => 1,
C_PROBE715_MU_CNT => 1,
C_PROBE716_MU_CNT => 1,
C_PROBE717_MU_CNT => 1,
C_PROBE718_MU_CNT => 1,
C_PROBE719_MU_CNT => 1,
C_PROBE720_MU_CNT => 1,
C_PROBE721_MU_CNT => 1,
C_PROBE722_MU_CNT => 1,
C_PROBE723_MU_CNT => 1,
C_PROBE724_MU_CNT => 1,
C_PROBE725_MU_CNT => 1,
C_PROBE726_MU_CNT => 1,
C_PROBE727_MU_CNT => 1,
C_PROBE728_MU_CNT => 1,
C_PROBE729_MU_CNT => 1,
C_PROBE730_MU_CNT => 1,
C_PROBE731_MU_CNT => 1,
C_PROBE732_MU_CNT => 1,
C_PROBE733_MU_CNT => 1,
C_PROBE734_MU_CNT => 1,
C_PROBE735_MU_CNT => 1,
C_PROBE736_MU_CNT => 1,
C_PROBE737_MU_CNT => 1,
C_PROBE738_MU_CNT => 1,
C_PROBE739_MU_CNT => 1,
C_PROBE740_MU_CNT => 1,
C_PROBE741_MU_CNT => 1,
C_PROBE742_MU_CNT => 1,
C_PROBE743_MU_CNT => 1,
C_PROBE744_MU_CNT => 1,
C_PROBE745_MU_CNT => 1,
C_PROBE746_MU_CNT => 1,
C_PROBE747_MU_CNT => 1,
C_PROBE748_MU_CNT => 1,
C_PROBE749_MU_CNT => 1,
C_PROBE750_MU_CNT => 1,
C_PROBE751_MU_CNT => 1,
C_PROBE752_MU_CNT => 1,
C_PROBE753_MU_CNT => 1,
C_PROBE754_MU_CNT => 1,
C_PROBE755_MU_CNT => 1,
C_PROBE756_MU_CNT => 1,
C_PROBE757_MU_CNT => 1,
C_PROBE758_MU_CNT => 1,
C_PROBE759_MU_CNT => 1,
C_PROBE760_MU_CNT => 1,
C_PROBE761_MU_CNT => 1,
C_PROBE762_MU_CNT => 1,
C_PROBE763_MU_CNT => 1,
C_PROBE764_MU_CNT => 1,
C_PROBE765_MU_CNT => 1,
C_PROBE766_MU_CNT => 1,
C_PROBE767_MU_CNT => 1,
C_PROBE768_MU_CNT => 1,
C_PROBE769_MU_CNT => 1,
C_PROBE770_MU_CNT => 1,
C_PROBE771_MU_CNT => 1,
C_PROBE772_MU_CNT => 1,
C_PROBE773_MU_CNT => 1,
C_PROBE774_MU_CNT => 1,
C_PROBE775_MU_CNT => 1,
C_PROBE776_MU_CNT => 1,
C_PROBE777_MU_CNT => 1,
C_PROBE778_MU_CNT => 1,
C_PROBE779_MU_CNT => 1,
C_PROBE780_MU_CNT => 1,
C_PROBE781_MU_CNT => 1,
C_PROBE782_MU_CNT => 1,
C_PROBE783_MU_CNT => 1,
C_PROBE784_MU_CNT => 1,
C_PROBE785_MU_CNT => 1,
C_PROBE786_MU_CNT => 1,
C_PROBE787_MU_CNT => 1,
C_PROBE788_MU_CNT => 1,
C_PROBE789_MU_CNT => 1,
C_PROBE790_MU_CNT => 1,
C_PROBE791_MU_CNT => 1,
C_PROBE792_MU_CNT => 1,
C_PROBE793_MU_CNT => 1,
C_PROBE794_MU_CNT => 1,
C_PROBE795_MU_CNT => 1,
C_PROBE796_MU_CNT => 1,
C_PROBE797_MU_CNT => 1,
C_PROBE798_MU_CNT => 1,
C_PROBE799_MU_CNT => 1,
C_PROBE800_MU_CNT => 1,
C_PROBE801_MU_CNT => 1,
C_PROBE802_MU_CNT => 1,
C_PROBE803_MU_CNT => 1,
C_PROBE804_MU_CNT => 1,
C_PROBE805_MU_CNT => 1,
C_PROBE806_MU_CNT => 1,
C_PROBE807_MU_CNT => 1,
C_PROBE808_MU_CNT => 1,
C_PROBE809_MU_CNT => 1,
C_PROBE810_MU_CNT => 1,
C_PROBE811_MU_CNT => 1,
C_PROBE812_MU_CNT => 1,
C_PROBE813_MU_CNT => 1,
C_PROBE814_MU_CNT => 1,
C_PROBE815_MU_CNT => 1,
C_PROBE816_MU_CNT => 1,
C_PROBE817_MU_CNT => 1,
C_PROBE818_MU_CNT => 1,
C_PROBE819_MU_CNT => 1,
C_PROBE820_MU_CNT => 1,
C_PROBE821_MU_CNT => 1,
C_PROBE822_MU_CNT => 1,
C_PROBE823_MU_CNT => 1,
C_PROBE824_MU_CNT => 1,
C_PROBE825_MU_CNT => 1,
C_PROBE826_MU_CNT => 1,
C_PROBE827_MU_CNT => 1,
C_PROBE828_MU_CNT => 1,
C_PROBE829_MU_CNT => 1,
C_PROBE830_MU_CNT => 1,
C_PROBE831_MU_CNT => 1,
C_PROBE832_MU_CNT => 1,
C_PROBE833_MU_CNT => 1,
C_PROBE834_MU_CNT => 1,
C_PROBE835_MU_CNT => 1,
C_PROBE836_MU_CNT => 1,
C_PROBE837_MU_CNT => 1,
C_PROBE838_MU_CNT => 1,
C_PROBE839_MU_CNT => 1,
C_PROBE840_MU_CNT => 1,
C_PROBE841_MU_CNT => 1,
C_PROBE842_MU_CNT => 1,
C_PROBE843_MU_CNT => 1,
C_PROBE844_MU_CNT => 1,
C_PROBE845_MU_CNT => 1,
C_PROBE846_MU_CNT => 1,
C_PROBE847_MU_CNT => 1,
C_PROBE848_MU_CNT => 1,
C_PROBE849_MU_CNT => 1,
C_PROBE850_MU_CNT => 1,
C_PROBE851_MU_CNT => 1,
C_PROBE852_MU_CNT => 1,
C_PROBE853_MU_CNT => 1,
C_PROBE854_MU_CNT => 1,
C_PROBE855_MU_CNT => 1,
C_PROBE856_MU_CNT => 1,
C_PROBE857_MU_CNT => 1,
C_PROBE858_MU_CNT => 1,
C_PROBE859_MU_CNT => 1,
C_PROBE860_MU_CNT => 1,
C_PROBE861_MU_CNT => 1,
C_PROBE862_MU_CNT => 1,
C_PROBE863_MU_CNT => 1,
C_PROBE864_MU_CNT => 1,
C_PROBE865_MU_CNT => 1,
C_PROBE866_MU_CNT => 1,
C_PROBE867_MU_CNT => 1,
C_PROBE868_MU_CNT => 1,
C_PROBE869_MU_CNT => 1,
C_PROBE870_MU_CNT => 1,
C_PROBE871_MU_CNT => 1,
C_PROBE872_MU_CNT => 1,
C_PROBE873_MU_CNT => 1,
C_PROBE874_MU_CNT => 1,
C_PROBE875_MU_CNT => 1,
C_PROBE876_MU_CNT => 1,
C_PROBE877_MU_CNT => 1,
C_PROBE878_MU_CNT => 1,
C_PROBE879_MU_CNT => 1,
C_PROBE880_MU_CNT => 1,
C_PROBE881_MU_CNT => 1,
C_PROBE882_MU_CNT => 1,
C_PROBE883_MU_CNT => 1,
C_PROBE884_MU_CNT => 1,
C_PROBE885_MU_CNT => 1,
C_PROBE886_MU_CNT => 1,
C_PROBE887_MU_CNT => 1,
C_PROBE888_MU_CNT => 1,
C_PROBE889_MU_CNT => 1,
C_PROBE890_MU_CNT => 1,
C_PROBE891_MU_CNT => 1,
C_PROBE892_MU_CNT => 1,
C_PROBE893_MU_CNT => 1,
C_PROBE894_MU_CNT => 1,
C_PROBE895_MU_CNT => 1,
C_PROBE896_MU_CNT => 1,
C_PROBE897_MU_CNT => 1,
C_PROBE898_MU_CNT => 1,
C_PROBE899_MU_CNT => 1,
C_PROBE900_MU_CNT => 1,
C_PROBE901_MU_CNT => 1,
C_PROBE902_MU_CNT => 1,
C_PROBE903_MU_CNT => 1,
C_PROBE904_MU_CNT => 1,
C_PROBE905_MU_CNT => 1,
C_PROBE906_MU_CNT => 1,
C_PROBE907_MU_CNT => 1,
C_PROBE908_MU_CNT => 1,
C_PROBE909_MU_CNT => 1,
C_PROBE910_MU_CNT => 1,
C_PROBE911_MU_CNT => 1,
C_PROBE912_MU_CNT => 1,
C_PROBE913_MU_CNT => 1,
C_PROBE914_MU_CNT => 1,
C_PROBE915_MU_CNT => 1,
C_PROBE916_MU_CNT => 1,
C_PROBE917_MU_CNT => 1,
C_PROBE918_MU_CNT => 1,
C_PROBE919_MU_CNT => 1,
C_PROBE920_MU_CNT => 1,
C_PROBE921_MU_CNT => 1,
C_PROBE922_MU_CNT => 1,
C_PROBE923_MU_CNT => 1,
C_PROBE924_MU_CNT => 1,
C_PROBE925_MU_CNT => 1,
C_PROBE926_MU_CNT => 1,
C_PROBE927_MU_CNT => 1,
C_PROBE928_MU_CNT => 1,
C_PROBE929_MU_CNT => 1,
C_PROBE930_MU_CNT => 1,
C_PROBE931_MU_CNT => 1,
C_PROBE932_MU_CNT => 1,
C_PROBE933_MU_CNT => 1,
C_PROBE934_MU_CNT => 1,
C_PROBE935_MU_CNT => 1,
C_PROBE936_MU_CNT => 1,
C_PROBE937_MU_CNT => 1,
C_PROBE938_MU_CNT => 1,
C_PROBE939_MU_CNT => 1,
C_PROBE940_MU_CNT => 1,
C_PROBE941_MU_CNT => 1,
C_PROBE942_MU_CNT => 1,
C_PROBE943_MU_CNT => 1,
C_PROBE944_MU_CNT => 1,
C_PROBE945_MU_CNT => 1,
C_PROBE946_MU_CNT => 1,
C_PROBE947_MU_CNT => 1,
C_PROBE948_MU_CNT => 1,
C_PROBE949_MU_CNT => 1,
C_PROBE950_MU_CNT => 1,
C_PROBE951_MU_CNT => 1,
C_PROBE952_MU_CNT => 1,
C_PROBE953_MU_CNT => 1,
C_PROBE954_MU_CNT => 1,
C_PROBE955_MU_CNT => 1,
C_PROBE956_MU_CNT => 1,
C_PROBE957_MU_CNT => 1,
C_PROBE958_MU_CNT => 1,
C_PROBE959_MU_CNT => 1,
C_PROBE960_MU_CNT => 1,
C_PROBE961_MU_CNT => 1,
C_PROBE962_MU_CNT => 1,
C_PROBE963_MU_CNT => 1,
C_PROBE964_MU_CNT => 1,
C_PROBE965_MU_CNT => 1,
C_PROBE966_MU_CNT => 1,
C_PROBE967_MU_CNT => 1,
C_PROBE968_MU_CNT => 1,
C_PROBE969_MU_CNT => 1,
C_PROBE970_MU_CNT => 1,
C_PROBE971_MU_CNT => 1,
C_PROBE972_MU_CNT => 1,
C_PROBE973_MU_CNT => 1,
C_PROBE974_MU_CNT => 1,
C_PROBE975_MU_CNT => 1,
C_PROBE976_MU_CNT => 1,
C_PROBE977_MU_CNT => 1,
C_PROBE978_MU_CNT => 1,
C_PROBE979_MU_CNT => 1,
C_PROBE980_MU_CNT => 1,
C_PROBE981_MU_CNT => 1,
C_PROBE982_MU_CNT => 1,
C_PROBE983_MU_CNT => 1,
C_PROBE984_MU_CNT => 1,
C_PROBE985_MU_CNT => 1,
C_PROBE986_MU_CNT => 1,
C_PROBE987_MU_CNT => 1,
C_PROBE988_MU_CNT => 1,
C_PROBE989_MU_CNT => 1,
C_PROBE990_MU_CNT => 1,
C_PROBE991_MU_CNT => 1,
C_PROBE992_MU_CNT => 1,
C_PROBE993_MU_CNT => 1,
C_PROBE994_MU_CNT => 1,
C_PROBE995_MU_CNT => 1,
C_PROBE996_MU_CNT => 1,
C_PROBE997_MU_CNT => 1,
C_PROBE998_MU_CNT => 1,
C_PROBE999_MU_CNT => 1,
C_PROBE1000_MU_CNT => 1,
C_PROBE1001_MU_CNT => 1,
C_PROBE1002_MU_CNT => 1,
C_PROBE1003_MU_CNT => 1,
C_PROBE1004_MU_CNT => 1,
C_PROBE1005_MU_CNT => 1,
C_PROBE1006_MU_CNT => 1,
C_PROBE1007_MU_CNT => 1,
C_PROBE1008_MU_CNT => 1,
C_PROBE1009_MU_CNT => 1,
C_PROBE1010_MU_CNT => 1,
C_PROBE1011_MU_CNT => 1,
C_PROBE1012_MU_CNT => 1,
C_PROBE1013_MU_CNT => 1,
C_PROBE1014_MU_CNT => 1,
C_PROBE1015_MU_CNT => 1,
C_PROBE1016_MU_CNT => 1,
C_PROBE1017_MU_CNT => 1,
C_PROBE1018_MU_CNT => 1,
C_PROBE1019_MU_CNT => 1,
C_PROBE1020_MU_CNT => 1,
C_PROBE1021_MU_CNT => 1,
C_PROBE1022_MU_CNT => 1,
C_PROBE1023_MU_CNT => 1,
C_PROBE0_TYPE => 0,
C_PROBE1_TYPE => 1,
C_PROBE2_TYPE => 0,
C_PROBE3_TYPE => 1,
C_PROBE4_TYPE => 1,
C_PROBE5_TYPE => 1,
C_PROBE6_TYPE => 1,
C_PROBE7_TYPE => 1,
C_PROBE8_TYPE => 1,
C_PROBE9_TYPE => 1,
C_PROBE10_TYPE => 1,
C_PROBE11_TYPE => 1,
C_PROBE12_TYPE => 1,
C_PROBE13_TYPE => 1,
C_PROBE14_TYPE => 1,
C_PROBE15_TYPE => 1,
C_PROBE16_TYPE => 1,
C_PROBE17_TYPE => 1,
C_PROBE18_TYPE => 1,
C_PROBE19_TYPE => 1,
C_PROBE20_TYPE => 1,
C_PROBE21_TYPE => 1,
C_PROBE22_TYPE => 1,
C_PROBE23_TYPE => 1,
C_PROBE24_TYPE => 1,
C_PROBE25_TYPE => 1,
C_PROBE26_TYPE => 1,
C_PROBE27_TYPE => 1,
C_PROBE28_TYPE => 1,
C_PROBE29_TYPE => 1,
C_PROBE30_TYPE => 1,
C_PROBE31_TYPE => 1,
C_PROBE32_TYPE => 1,
C_PROBE33_TYPE => 1,
C_PROBE34_TYPE => 1,
C_PROBE35_TYPE => 1,
C_PROBE36_TYPE => 1,
C_PROBE37_TYPE => 1,
C_PROBE38_TYPE => 1,
C_PROBE39_TYPE => 1,
C_PROBE40_TYPE => 1,
C_PROBE41_TYPE => 1,
C_PROBE42_TYPE => 1,
C_PROBE43_TYPE => 1,
C_PROBE44_TYPE => 1,
C_PROBE45_TYPE => 1,
C_PROBE46_TYPE => 1,
C_PROBE47_TYPE => 1,
C_PROBE48_TYPE => 1,
C_PROBE49_TYPE => 1,
C_PROBE50_TYPE => 1,
C_PROBE51_TYPE => 1,
C_PROBE52_TYPE => 1,
C_PROBE53_TYPE => 1,
C_PROBE54_TYPE => 1,
C_PROBE55_TYPE => 1,
C_PROBE56_TYPE => 1,
C_PROBE57_TYPE => 1,
C_PROBE58_TYPE => 1,
C_PROBE59_TYPE => 1,
C_PROBE60_TYPE => 1,
C_PROBE61_TYPE => 1,
C_PROBE62_TYPE => 1,
C_PROBE63_TYPE => 1,
C_PROBE64_TYPE => 1,
C_PROBE65_TYPE => 1,
C_PROBE66_TYPE => 1,
C_PROBE67_TYPE => 1,
C_PROBE68_TYPE => 1,
C_PROBE69_TYPE => 1,
C_PROBE70_TYPE => 1,
C_PROBE71_TYPE => 1,
C_PROBE72_TYPE => 1,
C_PROBE73_TYPE => 1,
C_PROBE74_TYPE => 1,
C_PROBE75_TYPE => 1,
C_PROBE76_TYPE => 1,
C_PROBE77_TYPE => 1,
C_PROBE78_TYPE => 1,
C_PROBE79_TYPE => 1,
C_PROBE80_TYPE => 1,
C_PROBE81_TYPE => 1,
C_PROBE82_TYPE => 1,
C_PROBE83_TYPE => 1,
C_PROBE84_TYPE => 1,
C_PROBE85_TYPE => 1,
C_PROBE86_TYPE => 1,
C_PROBE87_TYPE => 1,
C_PROBE88_TYPE => 1,
C_PROBE89_TYPE => 1,
C_PROBE90_TYPE => 1,
C_PROBE91_TYPE => 1,
C_PROBE92_TYPE => 1,
C_PROBE93_TYPE => 1,
C_PROBE94_TYPE => 1,
C_PROBE95_TYPE => 1,
C_PROBE96_TYPE => 1,
C_PROBE97_TYPE => 1,
C_PROBE98_TYPE => 1,
C_PROBE99_TYPE => 1,
C_PROBE100_TYPE => 1,
C_PROBE101_TYPE => 1,
C_PROBE102_TYPE => 1,
C_PROBE103_TYPE => 1,
C_PROBE104_TYPE => 1,
C_PROBE105_TYPE => 1,
C_PROBE106_TYPE => 1,
C_PROBE107_TYPE => 1,
C_PROBE108_TYPE => 1,
C_PROBE109_TYPE => 1,
C_PROBE110_TYPE => 1,
C_PROBE111_TYPE => 1,
C_PROBE112_TYPE => 1,
C_PROBE113_TYPE => 1,
C_PROBE114_TYPE => 1,
C_PROBE115_TYPE => 1,
C_PROBE116_TYPE => 1,
C_PROBE117_TYPE => 1,
C_PROBE118_TYPE => 1,
C_PROBE119_TYPE => 1,
C_PROBE120_TYPE => 1,
C_PROBE121_TYPE => 1,
C_PROBE122_TYPE => 1,
C_PROBE123_TYPE => 1,
C_PROBE124_TYPE => 1,
C_PROBE125_TYPE => 1,
C_PROBE126_TYPE => 1,
C_PROBE127_TYPE => 1,
C_PROBE128_TYPE => 1,
C_PROBE129_TYPE => 1,
C_PROBE130_TYPE => 1,
C_PROBE131_TYPE => 1,
C_PROBE132_TYPE => 1,
C_PROBE133_TYPE => 1,
C_PROBE134_TYPE => 1,
C_PROBE135_TYPE => 1,
C_PROBE136_TYPE => 1,
C_PROBE137_TYPE => 1,
C_PROBE138_TYPE => 1,
C_PROBE139_TYPE => 1,
C_PROBE140_TYPE => 1,
C_PROBE141_TYPE => 1,
C_PROBE142_TYPE => 1,
C_PROBE143_TYPE => 1,
C_PROBE144_TYPE => 1,
C_PROBE145_TYPE => 1,
C_PROBE146_TYPE => 1,
C_PROBE147_TYPE => 1,
C_PROBE148_TYPE => 1,
C_PROBE149_TYPE => 1,
C_PROBE150_TYPE => 1,
C_PROBE151_TYPE => 1,
C_PROBE152_TYPE => 1,
C_PROBE153_TYPE => 1,
C_PROBE154_TYPE => 1,
C_PROBE155_TYPE => 1,
C_PROBE156_TYPE => 1,
C_PROBE157_TYPE => 1,
C_PROBE158_TYPE => 1,
C_PROBE159_TYPE => 1,
C_PROBE160_TYPE => 1,
C_PROBE161_TYPE => 1,
C_PROBE162_TYPE => 1,
C_PROBE163_TYPE => 1,
C_PROBE164_TYPE => 1,
C_PROBE165_TYPE => 1,
C_PROBE166_TYPE => 1,
C_PROBE167_TYPE => 1,
C_PROBE168_TYPE => 1,
C_PROBE169_TYPE => 1,
C_PROBE170_TYPE => 1,
C_PROBE171_TYPE => 1,
C_PROBE172_TYPE => 1,
C_PROBE173_TYPE => 1,
C_PROBE174_TYPE => 1,
C_PROBE175_TYPE => 1,
C_PROBE176_TYPE => 1,
C_PROBE177_TYPE => 1,
C_PROBE178_TYPE => 1,
C_PROBE179_TYPE => 1,
C_PROBE180_TYPE => 1,
C_PROBE181_TYPE => 1,
C_PROBE182_TYPE => 1,
C_PROBE183_TYPE => 1,
C_PROBE184_TYPE => 1,
C_PROBE185_TYPE => 1,
C_PROBE186_TYPE => 1,
C_PROBE187_TYPE => 1,
C_PROBE188_TYPE => 1,
C_PROBE189_TYPE => 1,
C_PROBE190_TYPE => 1,
C_PROBE191_TYPE => 1,
C_PROBE192_TYPE => 1,
C_PROBE193_TYPE => 1,
C_PROBE194_TYPE => 1,
C_PROBE195_TYPE => 1,
C_PROBE196_TYPE => 1,
C_PROBE197_TYPE => 1,
C_PROBE198_TYPE => 1,
C_PROBE199_TYPE => 1,
C_PROBE200_TYPE => 1,
C_PROBE201_TYPE => 1,
C_PROBE202_TYPE => 1,
C_PROBE203_TYPE => 1,
C_PROBE204_TYPE => 1,
C_PROBE205_TYPE => 1,
C_PROBE206_TYPE => 1,
C_PROBE207_TYPE => 1,
C_PROBE208_TYPE => 1,
C_PROBE209_TYPE => 1,
C_PROBE210_TYPE => 1,
C_PROBE211_TYPE => 1,
C_PROBE212_TYPE => 1,
C_PROBE213_TYPE => 1,
C_PROBE214_TYPE => 1,
C_PROBE215_TYPE => 1,
C_PROBE216_TYPE => 1,
C_PROBE217_TYPE => 1,
C_PROBE218_TYPE => 1,
C_PROBE219_TYPE => 1,
C_PROBE220_TYPE => 1,
C_PROBE221_TYPE => 1,
C_PROBE222_TYPE => 1,
C_PROBE223_TYPE => 1,
C_PROBE224_TYPE => 1,
C_PROBE225_TYPE => 1,
C_PROBE226_TYPE => 1,
C_PROBE227_TYPE => 1,
C_PROBE228_TYPE => 1,
C_PROBE229_TYPE => 1,
C_PROBE230_TYPE => 1,
C_PROBE231_TYPE => 1,
C_PROBE232_TYPE => 1,
C_PROBE233_TYPE => 1,
C_PROBE234_TYPE => 1,
C_PROBE235_TYPE => 1,
C_PROBE236_TYPE => 1,
C_PROBE237_TYPE => 1,
C_PROBE238_TYPE => 1,
C_PROBE239_TYPE => 1,
C_PROBE240_TYPE => 1,
C_PROBE241_TYPE => 1,
C_PROBE242_TYPE => 1,
C_PROBE243_TYPE => 1,
C_PROBE244_TYPE => 1,
C_PROBE245_TYPE => 1,
C_PROBE246_TYPE => 1,
C_PROBE247_TYPE => 1,
C_PROBE248_TYPE => 1,
C_PROBE249_TYPE => 1,
C_PROBE250_TYPE => 1,
C_PROBE251_TYPE => 1,
C_PROBE252_TYPE => 1,
C_PROBE253_TYPE => 1,
C_PROBE254_TYPE => 1,
C_PROBE255_TYPE => 1,
C_PROBE256_TYPE => 1,
C_PROBE257_TYPE => 1,
C_PROBE258_TYPE => 1,
C_PROBE259_TYPE => 1,
C_PROBE260_TYPE => 1,
C_PROBE261_TYPE => 1,
C_PROBE262_TYPE => 1,
C_PROBE263_TYPE => 1,
C_PROBE264_TYPE => 1,
C_PROBE265_TYPE => 1,
C_PROBE266_TYPE => 1,
C_PROBE267_TYPE => 1,
C_PROBE268_TYPE => 1,
C_PROBE269_TYPE => 1,
C_PROBE270_TYPE => 1,
C_PROBE271_TYPE => 1,
C_PROBE272_TYPE => 1,
C_PROBE273_TYPE => 1,
C_PROBE274_TYPE => 1,
C_PROBE275_TYPE => 1,
C_PROBE276_TYPE => 1,
C_PROBE277_TYPE => 1,
C_PROBE278_TYPE => 1,
C_PROBE279_TYPE => 1,
C_PROBE280_TYPE => 1,
C_PROBE281_TYPE => 1,
C_PROBE282_TYPE => 1,
C_PROBE283_TYPE => 1,
C_PROBE284_TYPE => 1,
C_PROBE285_TYPE => 1,
C_PROBE286_TYPE => 1,
C_PROBE287_TYPE => 1,
C_PROBE288_TYPE => 1,
C_PROBE289_TYPE => 1,
C_PROBE290_TYPE => 1,
C_PROBE291_TYPE => 1,
C_PROBE292_TYPE => 1,
C_PROBE293_TYPE => 1,
C_PROBE294_TYPE => 1,
C_PROBE295_TYPE => 1,
C_PROBE296_TYPE => 1,
C_PROBE297_TYPE => 1,
C_PROBE298_TYPE => 1,
C_PROBE299_TYPE => 1,
C_PROBE300_TYPE => 1,
C_PROBE301_TYPE => 1,
C_PROBE302_TYPE => 1,
C_PROBE303_TYPE => 1,
C_PROBE304_TYPE => 1,
C_PROBE305_TYPE => 1,
C_PROBE306_TYPE => 1,
C_PROBE307_TYPE => 1,
C_PROBE308_TYPE => 1,
C_PROBE309_TYPE => 1,
C_PROBE310_TYPE => 1,
C_PROBE311_TYPE => 1,
C_PROBE312_TYPE => 1,
C_PROBE313_TYPE => 1,
C_PROBE314_TYPE => 1,
C_PROBE315_TYPE => 1,
C_PROBE316_TYPE => 1,
C_PROBE317_TYPE => 1,
C_PROBE318_TYPE => 1,
C_PROBE319_TYPE => 1,
C_PROBE320_TYPE => 1,
C_PROBE321_TYPE => 1,
C_PROBE322_TYPE => 1,
C_PROBE323_TYPE => 1,
C_PROBE324_TYPE => 1,
C_PROBE325_TYPE => 1,
C_PROBE326_TYPE => 1,
C_PROBE327_TYPE => 1,
C_PROBE328_TYPE => 1,
C_PROBE329_TYPE => 1,
C_PROBE330_TYPE => 1,
C_PROBE331_TYPE => 1,
C_PROBE332_TYPE => 1,
C_PROBE333_TYPE => 1,
C_PROBE334_TYPE => 1,
C_PROBE335_TYPE => 1,
C_PROBE336_TYPE => 1,
C_PROBE337_TYPE => 1,
C_PROBE338_TYPE => 1,
C_PROBE339_TYPE => 1,
C_PROBE340_TYPE => 1,
C_PROBE341_TYPE => 1,
C_PROBE342_TYPE => 1,
C_PROBE343_TYPE => 1,
C_PROBE344_TYPE => 1,
C_PROBE345_TYPE => 1,
C_PROBE346_TYPE => 1,
C_PROBE347_TYPE => 1,
C_PROBE348_TYPE => 1,
C_PROBE349_TYPE => 1,
C_PROBE350_TYPE => 1,
C_PROBE351_TYPE => 1,
C_PROBE352_TYPE => 1,
C_PROBE353_TYPE => 1,
C_PROBE354_TYPE => 1,
C_PROBE355_TYPE => 1,
C_PROBE356_TYPE => 1,
C_PROBE357_TYPE => 1,
C_PROBE358_TYPE => 1,
C_PROBE359_TYPE => 1,
C_PROBE360_TYPE => 1,
C_PROBE361_TYPE => 1,
C_PROBE362_TYPE => 1,
C_PROBE363_TYPE => 1,
C_PROBE364_TYPE => 1,
C_PROBE365_TYPE => 1,
C_PROBE366_TYPE => 1,
C_PROBE367_TYPE => 1,
C_PROBE368_TYPE => 1,
C_PROBE369_TYPE => 1,
C_PROBE370_TYPE => 1,
C_PROBE371_TYPE => 1,
C_PROBE372_TYPE => 1,
C_PROBE373_TYPE => 1,
C_PROBE374_TYPE => 1,
C_PROBE375_TYPE => 1,
C_PROBE376_TYPE => 1,
C_PROBE377_TYPE => 1,
C_PROBE378_TYPE => 1,
C_PROBE379_TYPE => 1,
C_PROBE380_TYPE => 1,
C_PROBE381_TYPE => 1,
C_PROBE382_TYPE => 1,
C_PROBE383_TYPE => 1,
C_PROBE384_TYPE => 1,
C_PROBE385_TYPE => 1,
C_PROBE386_TYPE => 1,
C_PROBE387_TYPE => 1,
C_PROBE388_TYPE => 1,
C_PROBE389_TYPE => 1,
C_PROBE390_TYPE => 1,
C_PROBE391_TYPE => 1,
C_PROBE392_TYPE => 1,
C_PROBE393_TYPE => 1,
C_PROBE394_TYPE => 1,
C_PROBE395_TYPE => 1,
C_PROBE396_TYPE => 1,
C_PROBE397_TYPE => 1,
C_PROBE398_TYPE => 1,
C_PROBE399_TYPE => 1,
C_PROBE400_TYPE => 1,
C_PROBE401_TYPE => 1,
C_PROBE402_TYPE => 1,
C_PROBE403_TYPE => 1,
C_PROBE404_TYPE => 1,
C_PROBE405_TYPE => 1,
C_PROBE406_TYPE => 1,
C_PROBE407_TYPE => 1,
C_PROBE408_TYPE => 1,
C_PROBE409_TYPE => 1,
C_PROBE410_TYPE => 1,
C_PROBE411_TYPE => 1,
C_PROBE412_TYPE => 1,
C_PROBE413_TYPE => 1,
C_PROBE414_TYPE => 1,
C_PROBE415_TYPE => 1,
C_PROBE416_TYPE => 1,
C_PROBE417_TYPE => 1,
C_PROBE418_TYPE => 1,
C_PROBE419_TYPE => 1,
C_PROBE420_TYPE => 1,
C_PROBE421_TYPE => 1,
C_PROBE422_TYPE => 1,
C_PROBE423_TYPE => 1,
C_PROBE424_TYPE => 1,
C_PROBE425_TYPE => 1,
C_PROBE426_TYPE => 1,
C_PROBE427_TYPE => 1,
C_PROBE428_TYPE => 1,
C_PROBE429_TYPE => 1,
C_PROBE430_TYPE => 1,
C_PROBE431_TYPE => 1,
C_PROBE432_TYPE => 1,
C_PROBE433_TYPE => 1,
C_PROBE434_TYPE => 1,
C_PROBE435_TYPE => 1,
C_PROBE436_TYPE => 1,
C_PROBE437_TYPE => 1,
C_PROBE438_TYPE => 1,
C_PROBE439_TYPE => 1,
C_PROBE440_TYPE => 1,
C_PROBE441_TYPE => 1,
C_PROBE442_TYPE => 1,
C_PROBE443_TYPE => 1,
C_PROBE444_TYPE => 1,
C_PROBE445_TYPE => 1,
C_PROBE446_TYPE => 1,
C_PROBE447_TYPE => 1,
C_PROBE448_TYPE => 1,
C_PROBE449_TYPE => 1,
C_PROBE450_TYPE => 1,
C_PROBE451_TYPE => 1,
C_PROBE452_TYPE => 1,
C_PROBE453_TYPE => 1,
C_PROBE454_TYPE => 1,
C_PROBE455_TYPE => 1,
C_PROBE456_TYPE => 1,
C_PROBE457_TYPE => 1,
C_PROBE458_TYPE => 1,
C_PROBE459_TYPE => 1,
C_PROBE460_TYPE => 1,
C_PROBE461_TYPE => 1,
C_PROBE462_TYPE => 1,
C_PROBE463_TYPE => 1,
C_PROBE464_TYPE => 1,
C_PROBE465_TYPE => 1,
C_PROBE466_TYPE => 1,
C_PROBE467_TYPE => 1,
C_PROBE468_TYPE => 1,
C_PROBE469_TYPE => 1,
C_PROBE470_TYPE => 1,
C_PROBE471_TYPE => 1,
C_PROBE472_TYPE => 1,
C_PROBE473_TYPE => 1,
C_PROBE474_TYPE => 1,
C_PROBE475_TYPE => 1,
C_PROBE476_TYPE => 1,
C_PROBE477_TYPE => 1,
C_PROBE478_TYPE => 1,
C_PROBE479_TYPE => 1,
C_PROBE480_TYPE => 1,
C_PROBE481_TYPE => 1,
C_PROBE482_TYPE => 1,
C_PROBE483_TYPE => 1,
C_PROBE484_TYPE => 1,
C_PROBE485_TYPE => 1,
C_PROBE486_TYPE => 1,
C_PROBE487_TYPE => 1,
C_PROBE488_TYPE => 1,
C_PROBE489_TYPE => 1,
C_PROBE490_TYPE => 1,
C_PROBE491_TYPE => 1,
C_PROBE492_TYPE => 1,
C_PROBE493_TYPE => 1,
C_PROBE494_TYPE => 1,
C_PROBE495_TYPE => 1,
C_PROBE496_TYPE => 1,
C_PROBE497_TYPE => 1,
C_PROBE498_TYPE => 1,
C_PROBE499_TYPE => 1,
C_PROBE500_TYPE => 1,
C_PROBE501_TYPE => 1,
C_PROBE502_TYPE => 1,
C_PROBE503_TYPE => 1,
C_PROBE504_TYPE => 1,
C_PROBE505_TYPE => 1,
C_PROBE506_TYPE => 1,
C_PROBE507_TYPE => 1,
C_PROBE508_TYPE => 1,
C_PROBE509_TYPE => 1,
C_PROBE510_TYPE => 1,
C_PROBE511_TYPE => 1,
C_PROBE512_TYPE => 1,
C_PROBE513_TYPE => 1,
C_PROBE514_TYPE => 1,
C_PROBE515_TYPE => 1,
C_PROBE516_TYPE => 1,
C_PROBE517_TYPE => 1,
C_PROBE518_TYPE => 1,
C_PROBE519_TYPE => 1,
C_PROBE520_TYPE => 1,
C_PROBE521_TYPE => 1,
C_PROBE522_TYPE => 1,
C_PROBE523_TYPE => 1,
C_PROBE524_TYPE => 1,
C_PROBE525_TYPE => 1,
C_PROBE526_TYPE => 1,
C_PROBE527_TYPE => 1,
C_PROBE528_TYPE => 1,
C_PROBE529_TYPE => 1,
C_PROBE530_TYPE => 1,
C_PROBE531_TYPE => 1,
C_PROBE532_TYPE => 1,
C_PROBE533_TYPE => 1,
C_PROBE534_TYPE => 1,
C_PROBE535_TYPE => 1,
C_PROBE536_TYPE => 1,
C_PROBE537_TYPE => 1,
C_PROBE538_TYPE => 1,
C_PROBE539_TYPE => 1,
C_PROBE540_TYPE => 1,
C_PROBE541_TYPE => 1,
C_PROBE542_TYPE => 1,
C_PROBE543_TYPE => 1,
C_PROBE544_TYPE => 1,
C_PROBE545_TYPE => 1,
C_PROBE546_TYPE => 1,
C_PROBE547_TYPE => 1,
C_PROBE548_TYPE => 1,
C_PROBE549_TYPE => 1,
C_PROBE550_TYPE => 1,
C_PROBE551_TYPE => 1,
C_PROBE552_TYPE => 1,
C_PROBE553_TYPE => 1,
C_PROBE554_TYPE => 1,
C_PROBE555_TYPE => 1,
C_PROBE556_TYPE => 1,
C_PROBE557_TYPE => 1,
C_PROBE558_TYPE => 1,
C_PROBE559_TYPE => 1,
C_PROBE560_TYPE => 1,
C_PROBE561_TYPE => 1,
C_PROBE562_TYPE => 1,
C_PROBE563_TYPE => 1,
C_PROBE564_TYPE => 1,
C_PROBE565_TYPE => 1,
C_PROBE566_TYPE => 1,
C_PROBE567_TYPE => 1,
C_PROBE568_TYPE => 1,
C_PROBE569_TYPE => 1,
C_PROBE570_TYPE => 1,
C_PROBE571_TYPE => 1,
C_PROBE572_TYPE => 1,
C_PROBE573_TYPE => 1,
C_PROBE574_TYPE => 1,
C_PROBE575_TYPE => 1,
C_PROBE576_TYPE => 1,
C_PROBE577_TYPE => 1,
C_PROBE578_TYPE => 1,
C_PROBE579_TYPE => 1,
C_PROBE580_TYPE => 1,
C_PROBE581_TYPE => 1,
C_PROBE582_TYPE => 1,
C_PROBE583_TYPE => 1,
C_PROBE584_TYPE => 1,
C_PROBE585_TYPE => 1,
C_PROBE586_TYPE => 1,
C_PROBE587_TYPE => 1,
C_PROBE588_TYPE => 1,
C_PROBE589_TYPE => 1,
C_PROBE590_TYPE => 1,
C_PROBE591_TYPE => 1,
C_PROBE592_TYPE => 1,
C_PROBE593_TYPE => 1,
C_PROBE594_TYPE => 1,
C_PROBE595_TYPE => 1,
C_PROBE596_TYPE => 1,
C_PROBE597_TYPE => 1,
C_PROBE598_TYPE => 1,
C_PROBE599_TYPE => 1,
C_PROBE600_TYPE => 1,
C_PROBE601_TYPE => 1,
C_PROBE602_TYPE => 1,
C_PROBE603_TYPE => 1,
C_PROBE604_TYPE => 1,
C_PROBE605_TYPE => 1,
C_PROBE606_TYPE => 1,
C_PROBE607_TYPE => 1,
C_PROBE608_TYPE => 1,
C_PROBE609_TYPE => 1,
C_PROBE610_TYPE => 1,
C_PROBE611_TYPE => 1,
C_PROBE612_TYPE => 1,
C_PROBE613_TYPE => 1,
C_PROBE614_TYPE => 1,
C_PROBE615_TYPE => 1,
C_PROBE616_TYPE => 1,
C_PROBE617_TYPE => 1,
C_PROBE618_TYPE => 1,
C_PROBE619_TYPE => 1,
C_PROBE620_TYPE => 1,
C_PROBE621_TYPE => 1,
C_PROBE622_TYPE => 1,
C_PROBE623_TYPE => 1,
C_PROBE624_TYPE => 1,
C_PROBE625_TYPE => 1,
C_PROBE626_TYPE => 1,
C_PROBE627_TYPE => 1,
C_PROBE628_TYPE => 1,
C_PROBE629_TYPE => 1,
C_PROBE630_TYPE => 1,
C_PROBE631_TYPE => 1,
C_PROBE632_TYPE => 1,
C_PROBE633_TYPE => 1,
C_PROBE634_TYPE => 1,
C_PROBE635_TYPE => 1,
C_PROBE636_TYPE => 1,
C_PROBE637_TYPE => 1,
C_PROBE638_TYPE => 1,
C_PROBE639_TYPE => 1,
C_PROBE640_TYPE => 1,
C_PROBE641_TYPE => 1,
C_PROBE642_TYPE => 1,
C_PROBE643_TYPE => 1,
C_PROBE644_TYPE => 1,
C_PROBE645_TYPE => 1,
C_PROBE646_TYPE => 1,
C_PROBE647_TYPE => 1,
C_PROBE648_TYPE => 1,
C_PROBE649_TYPE => 1,
C_PROBE650_TYPE => 1,
C_PROBE651_TYPE => 1,
C_PROBE652_TYPE => 1,
C_PROBE653_TYPE => 1,
C_PROBE654_TYPE => 1,
C_PROBE655_TYPE => 1,
C_PROBE656_TYPE => 1,
C_PROBE657_TYPE => 1,
C_PROBE658_TYPE => 1,
C_PROBE659_TYPE => 1,
C_PROBE660_TYPE => 1,
C_PROBE661_TYPE => 1,
C_PROBE662_TYPE => 1,
C_PROBE663_TYPE => 1,
C_PROBE664_TYPE => 1,
C_PROBE665_TYPE => 1,
C_PROBE666_TYPE => 1,
C_PROBE667_TYPE => 1,
C_PROBE668_TYPE => 1,
C_PROBE669_TYPE => 1,
C_PROBE670_TYPE => 1,
C_PROBE671_TYPE => 1,
C_PROBE672_TYPE => 1,
C_PROBE673_TYPE => 1,
C_PROBE674_TYPE => 1,
C_PROBE675_TYPE => 1,
C_PROBE676_TYPE => 1,
C_PROBE677_TYPE => 1,
C_PROBE678_TYPE => 1,
C_PROBE679_TYPE => 1,
C_PROBE680_TYPE => 1,
C_PROBE681_TYPE => 1,
C_PROBE682_TYPE => 1,
C_PROBE683_TYPE => 1,
C_PROBE684_TYPE => 1,
C_PROBE685_TYPE => 1,
C_PROBE686_TYPE => 1,
C_PROBE687_TYPE => 1,
C_PROBE688_TYPE => 1,
C_PROBE689_TYPE => 1,
C_PROBE690_TYPE => 1,
C_PROBE691_TYPE => 1,
C_PROBE692_TYPE => 1,
C_PROBE693_TYPE => 1,
C_PROBE694_TYPE => 1,
C_PROBE695_TYPE => 1,
C_PROBE696_TYPE => 1,
C_PROBE697_TYPE => 1,
C_PROBE698_TYPE => 1,
C_PROBE699_TYPE => 1,
C_PROBE700_TYPE => 1,
C_PROBE701_TYPE => 1,
C_PROBE702_TYPE => 1,
C_PROBE703_TYPE => 1,
C_PROBE704_TYPE => 1,
C_PROBE705_TYPE => 1,
C_PROBE706_TYPE => 1,
C_PROBE707_TYPE => 1,
C_PROBE708_TYPE => 1,
C_PROBE709_TYPE => 1,
C_PROBE710_TYPE => 1,
C_PROBE711_TYPE => 1,
C_PROBE712_TYPE => 1,
C_PROBE713_TYPE => 1,
C_PROBE714_TYPE => 1,
C_PROBE715_TYPE => 1,
C_PROBE716_TYPE => 1,
C_PROBE717_TYPE => 1,
C_PROBE718_TYPE => 1,
C_PROBE719_TYPE => 1,
C_PROBE720_TYPE => 1,
C_PROBE721_TYPE => 1,
C_PROBE722_TYPE => 1,
C_PROBE723_TYPE => 1,
C_PROBE724_TYPE => 1,
C_PROBE725_TYPE => 1,
C_PROBE726_TYPE => 1,
C_PROBE727_TYPE => 1,
C_PROBE728_TYPE => 1,
C_PROBE729_TYPE => 1,
C_PROBE730_TYPE => 1,
C_PROBE731_TYPE => 1,
C_PROBE732_TYPE => 1,
C_PROBE733_TYPE => 1,
C_PROBE734_TYPE => 1,
C_PROBE735_TYPE => 1,
C_PROBE736_TYPE => 1,
C_PROBE737_TYPE => 1,
C_PROBE738_TYPE => 1,
C_PROBE739_TYPE => 1,
C_PROBE740_TYPE => 1,
C_PROBE741_TYPE => 1,
C_PROBE742_TYPE => 1,
C_PROBE743_TYPE => 1,
C_PROBE744_TYPE => 1,
C_PROBE745_TYPE => 1,
C_PROBE746_TYPE => 1,
C_PROBE747_TYPE => 1,
C_PROBE748_TYPE => 1,
C_PROBE749_TYPE => 1,
C_PROBE750_TYPE => 1,
C_PROBE751_TYPE => 1,
C_PROBE752_TYPE => 1,
C_PROBE753_TYPE => 1,
C_PROBE754_TYPE => 1,
C_PROBE755_TYPE => 1,
C_PROBE756_TYPE => 1,
C_PROBE757_TYPE => 1,
C_PROBE758_TYPE => 1,
C_PROBE759_TYPE => 1,
C_PROBE760_TYPE => 1,
C_PROBE761_TYPE => 1,
C_PROBE762_TYPE => 1,
C_PROBE763_TYPE => 1,
C_PROBE764_TYPE => 1,
C_PROBE765_TYPE => 1,
C_PROBE766_TYPE => 1,
C_PROBE767_TYPE => 1,
C_PROBE768_TYPE => 1,
C_PROBE769_TYPE => 1,
C_PROBE770_TYPE => 1,
C_PROBE771_TYPE => 1,
C_PROBE772_TYPE => 1,
C_PROBE773_TYPE => 1,
C_PROBE774_TYPE => 1,
C_PROBE775_TYPE => 1,
C_PROBE776_TYPE => 1,
C_PROBE777_TYPE => 1,
C_PROBE778_TYPE => 1,
C_PROBE779_TYPE => 1,
C_PROBE780_TYPE => 1,
C_PROBE781_TYPE => 1,
C_PROBE782_TYPE => 1,
C_PROBE783_TYPE => 1,
C_PROBE784_TYPE => 1,
C_PROBE785_TYPE => 1,
C_PROBE786_TYPE => 1,
C_PROBE787_TYPE => 1,
C_PROBE788_TYPE => 1,
C_PROBE789_TYPE => 1,
C_PROBE790_TYPE => 1,
C_PROBE791_TYPE => 1,
C_PROBE792_TYPE => 1,
C_PROBE793_TYPE => 1,
C_PROBE794_TYPE => 1,
C_PROBE795_TYPE => 1,
C_PROBE796_TYPE => 1,
C_PROBE797_TYPE => 1,
C_PROBE798_TYPE => 1,
C_PROBE799_TYPE => 1,
C_PROBE800_TYPE => 1,
C_PROBE801_TYPE => 1,
C_PROBE802_TYPE => 1,
C_PROBE803_TYPE => 1,
C_PROBE804_TYPE => 1,
C_PROBE805_TYPE => 1,
C_PROBE806_TYPE => 1,
C_PROBE807_TYPE => 1,
C_PROBE808_TYPE => 1,
C_PROBE809_TYPE => 1,
C_PROBE810_TYPE => 1,
C_PROBE811_TYPE => 1,
C_PROBE812_TYPE => 1,
C_PROBE813_TYPE => 1,
C_PROBE814_TYPE => 1,
C_PROBE815_TYPE => 1,
C_PROBE816_TYPE => 1,
C_PROBE817_TYPE => 1,
C_PROBE818_TYPE => 1,
C_PROBE819_TYPE => 1,
C_PROBE820_TYPE => 1,
C_PROBE821_TYPE => 1,
C_PROBE822_TYPE => 1,
C_PROBE823_TYPE => 1,
C_PROBE824_TYPE => 1,
C_PROBE825_TYPE => 1,
C_PROBE826_TYPE => 1,
C_PROBE827_TYPE => 1,
C_PROBE828_TYPE => 1,
C_PROBE829_TYPE => 1,
C_PROBE830_TYPE => 1,
C_PROBE831_TYPE => 1,
C_PROBE832_TYPE => 1,
C_PROBE833_TYPE => 1,
C_PROBE834_TYPE => 1,
C_PROBE835_TYPE => 1,
C_PROBE836_TYPE => 1,
C_PROBE837_TYPE => 1,
C_PROBE838_TYPE => 1,
C_PROBE839_TYPE => 1,
C_PROBE840_TYPE => 1,
C_PROBE841_TYPE => 1,
C_PROBE842_TYPE => 1,
C_PROBE843_TYPE => 1,
C_PROBE844_TYPE => 1,
C_PROBE845_TYPE => 1,
C_PROBE846_TYPE => 1,
C_PROBE847_TYPE => 1,
C_PROBE848_TYPE => 1,
C_PROBE849_TYPE => 1,
C_PROBE850_TYPE => 1,
C_PROBE851_TYPE => 1,
C_PROBE852_TYPE => 1,
C_PROBE853_TYPE => 1,
C_PROBE854_TYPE => 1,
C_PROBE855_TYPE => 1,
C_PROBE856_TYPE => 1,
C_PROBE857_TYPE => 1,
C_PROBE858_TYPE => 1,
C_PROBE859_TYPE => 1,
C_PROBE860_TYPE => 1,
C_PROBE861_TYPE => 1,
C_PROBE862_TYPE => 1,
C_PROBE863_TYPE => 1,
C_PROBE864_TYPE => 1,
C_PROBE865_TYPE => 1,
C_PROBE866_TYPE => 1,
C_PROBE867_TYPE => 1,
C_PROBE868_TYPE => 1,
C_PROBE869_TYPE => 1,
C_PROBE870_TYPE => 1,
C_PROBE871_TYPE => 1,
C_PROBE872_TYPE => 1,
C_PROBE873_TYPE => 1,
C_PROBE874_TYPE => 1,
C_PROBE875_TYPE => 1,
C_PROBE876_TYPE => 1,
C_PROBE877_TYPE => 1,
C_PROBE878_TYPE => 1,
C_PROBE879_TYPE => 1,
C_PROBE880_TYPE => 1,
C_PROBE881_TYPE => 1,
C_PROBE882_TYPE => 1,
C_PROBE883_TYPE => 1,
C_PROBE884_TYPE => 1,
C_PROBE885_TYPE => 1,
C_PROBE886_TYPE => 1,
C_PROBE887_TYPE => 1,
C_PROBE888_TYPE => 1,
C_PROBE889_TYPE => 1,
C_PROBE890_TYPE => 1,
C_PROBE891_TYPE => 1,
C_PROBE892_TYPE => 1,
C_PROBE893_TYPE => 1,
C_PROBE894_TYPE => 1,
C_PROBE895_TYPE => 1,
C_PROBE896_TYPE => 1,
C_PROBE897_TYPE => 1,
C_PROBE898_TYPE => 1,
C_PROBE899_TYPE => 1,
C_PROBE900_TYPE => 1,
C_PROBE901_TYPE => 1,
C_PROBE902_TYPE => 1,
C_PROBE903_TYPE => 1,
C_PROBE904_TYPE => 1,
C_PROBE905_TYPE => 1,
C_PROBE906_TYPE => 1,
C_PROBE907_TYPE => 1,
C_PROBE908_TYPE => 1,
C_PROBE909_TYPE => 1,
C_PROBE910_TYPE => 1,
C_PROBE911_TYPE => 1,
C_PROBE912_TYPE => 1,
C_PROBE913_TYPE => 1,
C_PROBE914_TYPE => 1,
C_PROBE915_TYPE => 1,
C_PROBE916_TYPE => 1,
C_PROBE917_TYPE => 1,
C_PROBE918_TYPE => 1,
C_PROBE919_TYPE => 1,
C_PROBE920_TYPE => 1,
C_PROBE921_TYPE => 1,
C_PROBE922_TYPE => 1,
C_PROBE923_TYPE => 1,
C_PROBE924_TYPE => 1,
C_PROBE925_TYPE => 1,
C_PROBE926_TYPE => 1,
C_PROBE927_TYPE => 1,
C_PROBE928_TYPE => 1,
C_PROBE929_TYPE => 1,
C_PROBE930_TYPE => 1,
C_PROBE931_TYPE => 1,
C_PROBE932_TYPE => 1,
C_PROBE933_TYPE => 1,
C_PROBE934_TYPE => 1,
C_PROBE935_TYPE => 1,
C_PROBE936_TYPE => 1,
C_PROBE937_TYPE => 1,
C_PROBE938_TYPE => 1,
C_PROBE939_TYPE => 1,
C_PROBE940_TYPE => 1,
C_PROBE941_TYPE => 1,
C_PROBE942_TYPE => 1,
C_PROBE943_TYPE => 1,
C_PROBE944_TYPE => 1,
C_PROBE945_TYPE => 1,
C_PROBE946_TYPE => 1,
C_PROBE947_TYPE => 1,
C_PROBE948_TYPE => 1,
C_PROBE949_TYPE => 1,
C_PROBE950_TYPE => 1,
C_PROBE951_TYPE => 1,
C_PROBE952_TYPE => 1,
C_PROBE953_TYPE => 1,
C_PROBE954_TYPE => 1,
C_PROBE955_TYPE => 1,
C_PROBE956_TYPE => 1,
C_PROBE957_TYPE => 1,
C_PROBE958_TYPE => 1,
C_PROBE959_TYPE => 1,
C_PROBE960_TYPE => 1,
C_PROBE961_TYPE => 1,
C_PROBE962_TYPE => 1,
C_PROBE963_TYPE => 1,
C_PROBE964_TYPE => 1,
C_PROBE965_TYPE => 1,
C_PROBE966_TYPE => 1,
C_PROBE967_TYPE => 1,
C_PROBE968_TYPE => 1,
C_PROBE969_TYPE => 1,
C_PROBE970_TYPE => 1,
C_PROBE971_TYPE => 1,
C_PROBE972_TYPE => 1,
C_PROBE973_TYPE => 1,
C_PROBE974_TYPE => 1,
C_PROBE975_TYPE => 1,
C_PROBE976_TYPE => 1,
C_PROBE977_TYPE => 1,
C_PROBE978_TYPE => 1,
C_PROBE979_TYPE => 1,
C_PROBE980_TYPE => 1,
C_PROBE981_TYPE => 1,
C_PROBE982_TYPE => 1,
C_PROBE983_TYPE => 1,
C_PROBE984_TYPE => 1,
C_PROBE985_TYPE => 1,
C_PROBE986_TYPE => 1,
C_PROBE987_TYPE => 1,
C_PROBE988_TYPE => 1,
C_PROBE989_TYPE => 1,
C_PROBE990_TYPE => 1,
C_PROBE991_TYPE => 1,
C_PROBE992_TYPE => 1,
C_PROBE993_TYPE => 1,
C_PROBE994_TYPE => 1,
C_PROBE995_TYPE => 1,
C_PROBE996_TYPE => 1,
C_PROBE997_TYPE => 1,
C_PROBE998_TYPE => 1,
C_PROBE999_TYPE => 1,
C_PROBE1000_TYPE => 1,
C_PROBE1001_TYPE => 1,
C_PROBE1002_TYPE => 1,
C_PROBE1003_TYPE => 1,
C_PROBE1004_TYPE => 1,
C_PROBE1005_TYPE => 1,
C_PROBE1006_TYPE => 1,
C_PROBE1007_TYPE => 1,
C_PROBE1008_TYPE => 1,
C_PROBE1009_TYPE => 1,
C_PROBE1010_TYPE => 1,
C_PROBE1011_TYPE => 1,
C_PROBE1012_TYPE => 1,
C_PROBE1013_TYPE => 1,
C_PROBE1014_TYPE => 1,
C_PROBE1015_TYPE => 1,
C_PROBE1016_TYPE => 1,
C_PROBE1017_TYPE => 1,
C_PROBE1018_TYPE => 1,
C_PROBE1019_TYPE => 1,
C_PROBE1020_TYPE => 1,
C_PROBE1021_TYPE => 1,
C_PROBE1022_TYPE => 1,
C_PROBE1023_TYPE => 1
)
PORT MAP (
clk => clk,
sl_iport0 => sl_iport0,
sl_oport0 => sl_oport0,
trig_out => open,
trig_out_ack => '0',
trig_in => '0',
trig_in_ack => open,
probe0 => probe0,
probe1 => probe1,
probe2 => probe2,
probe3 => probe3,
probe4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe32 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe33 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe34 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe35 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe36 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe37 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe38 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe39 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe40 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe41 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe42 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe43 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe44 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe45 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe46 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe47 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe48 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe49 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe50 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe51 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe52 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe53 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe54 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe55 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe56 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe57 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe58 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe59 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe60 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe61 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe62 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe63 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe64 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe65 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe66 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe67 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe68 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe69 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe70 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe71 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe72 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe73 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe74 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe75 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe76 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe77 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe78 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe79 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe80 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe81 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe82 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe83 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe84 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe85 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe86 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe87 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe88 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe89 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe90 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe91 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe92 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe93 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe94 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe95 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe96 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe97 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe98 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe99 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe100 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe101 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe102 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe103 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe104 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe105 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe106 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe107 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe108 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe109 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe110 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe111 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe112 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe113 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe114 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe115 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe116 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe117 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe118 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe119 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe120 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe121 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe122 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe123 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe124 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe125 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe126 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe127 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe128 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe129 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe130 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe131 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe132 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe133 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe134 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe135 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe136 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe137 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe138 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe139 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe140 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe141 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe142 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe143 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe144 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe145 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe146 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe147 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe148 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe149 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe150 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe151 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe152 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe153 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe154 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe155 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe156 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe157 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe158 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe159 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe160 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe161 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe162 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe163 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe164 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe165 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe166 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe167 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe168 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe169 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe170 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe171 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe172 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe173 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe174 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe175 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe176 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe177 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe178 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe179 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe180 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe181 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe182 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe183 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe184 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe185 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe186 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe187 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe188 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe189 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe190 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe191 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe192 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe193 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe194 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe195 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe196 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe197 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe198 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe199 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe200 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe201 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe202 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe203 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe204 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe205 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe206 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe207 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe208 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe209 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe210 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe211 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe212 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe213 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe214 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe215 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe216 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe217 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe218 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe219 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe220 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe221 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe222 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe223 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe224 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe225 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe226 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe227 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe228 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe229 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe230 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe231 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe232 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe233 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe234 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe235 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe236 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe237 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe238 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe239 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe240 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe241 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe242 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe243 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe244 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe245 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe246 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe247 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe248 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe249 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe250 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe251 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe252 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe253 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe254 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe255 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe256 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe257 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe258 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe259 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe260 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe261 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe262 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe263 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe264 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe265 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe266 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe267 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe268 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe269 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe270 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe271 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe272 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe273 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe274 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe275 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe276 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe277 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe278 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe279 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe280 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe281 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe282 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe283 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe284 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe285 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe286 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe287 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe288 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe289 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe290 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe291 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe292 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe293 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe294 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe295 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe296 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe297 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe298 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe299 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe300 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe301 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe302 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe303 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe304 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe305 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe306 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe307 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe308 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe309 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe310 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe311 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe312 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe313 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe314 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe315 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe316 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe317 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe318 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe319 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe320 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe321 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe322 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe323 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe324 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe325 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe326 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe327 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe328 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe329 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe330 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe331 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe332 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe333 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe334 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe335 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe336 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe337 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe338 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe339 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe340 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe341 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe342 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe343 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe344 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe345 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe346 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe347 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe348 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe349 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe350 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe351 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe352 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe353 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe354 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe355 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe356 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe357 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe358 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe359 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe360 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe361 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe362 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe363 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe364 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe365 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe366 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe367 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe368 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe369 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe370 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe371 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe372 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe373 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe374 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe375 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe376 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe377 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe378 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe379 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe380 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe381 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe382 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe383 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe384 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe385 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe386 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe387 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe388 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe389 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe390 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe391 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe392 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe393 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe394 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe395 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe396 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe397 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe398 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe399 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe400 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe401 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe402 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe403 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe404 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe405 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe406 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe407 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe408 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe409 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe410 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe411 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe412 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe413 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe414 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe415 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe416 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe417 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe418 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe419 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe420 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe421 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe422 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe423 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe424 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe425 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe426 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe427 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe428 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe429 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe430 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe431 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe432 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe433 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe434 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe435 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe436 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe437 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe438 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe439 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe440 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe441 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe442 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe443 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe444 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe445 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe446 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe447 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe448 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe449 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe450 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe451 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe452 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe453 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe454 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe455 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe456 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe457 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe458 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe459 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe460 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe461 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe462 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe463 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe464 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe465 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe466 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe467 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe468 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe469 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe470 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe471 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe472 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe473 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe474 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe475 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe476 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe477 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe478 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe479 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe480 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe481 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe482 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe483 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe484 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe485 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe486 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe487 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe488 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe489 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe490 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe491 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe492 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe493 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe494 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe495 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe496 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe497 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe498 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe499 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe500 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe501 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe502 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe503 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe504 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe505 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe506 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe507 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe508 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe509 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe510 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe511 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe512 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe513 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe514 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe515 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe516 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe517 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe518 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe519 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe520 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe521 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe522 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe523 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe524 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe525 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe526 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe527 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe528 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe529 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe530 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe531 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe532 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe533 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe534 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe535 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe536 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe537 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe538 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe539 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe540 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe541 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe542 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe543 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe544 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe545 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe546 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe547 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe548 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe549 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe550 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe551 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe552 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe553 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe554 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe555 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe556 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe557 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe558 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe559 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe560 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe561 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe562 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe563 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe564 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe565 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe566 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe567 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe568 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe569 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe570 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe571 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe572 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe573 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe574 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe575 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe576 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe577 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe578 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe579 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe580 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe581 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe582 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe583 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe584 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe585 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe586 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe587 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe588 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe589 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe590 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe591 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe592 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe593 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe594 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe595 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe596 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe597 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe598 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe599 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe600 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe601 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe602 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe603 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe604 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe605 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe606 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe607 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe608 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe609 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe610 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe611 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe612 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe613 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe614 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe615 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe616 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe617 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe618 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe619 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe620 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe621 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe622 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe623 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe624 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe625 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe626 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe627 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe628 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe629 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe630 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe631 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe632 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe633 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe634 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe635 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe636 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe637 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe638 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe639 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe640 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe641 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe642 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe643 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe644 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe645 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe646 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe647 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe648 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe649 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe650 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe651 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe652 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe653 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe654 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe655 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe656 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe657 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe658 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe659 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe660 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe661 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe662 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe663 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe664 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe665 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe666 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe667 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe668 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe669 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe670 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe671 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe672 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe673 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe674 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe675 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe676 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe677 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe678 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe679 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe680 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe681 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe682 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe683 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe684 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe685 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe686 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe687 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe688 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe689 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe690 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe691 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe692 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe693 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe694 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe695 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe696 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe697 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe698 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe699 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe700 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe701 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe702 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe703 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe704 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe705 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe706 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe707 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe708 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe709 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe710 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe711 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe712 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe713 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe714 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe715 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe716 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe717 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe718 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe719 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe720 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe721 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe722 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe723 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe724 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe725 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe726 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe727 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe728 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe729 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe730 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe731 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe732 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe733 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe734 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe735 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe736 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe737 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe738 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe739 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe740 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe741 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe742 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe743 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe744 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe745 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe746 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe747 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe748 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe749 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe750 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe751 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe752 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe753 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe754 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe755 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe756 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe757 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe758 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe759 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe760 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe761 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe762 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe763 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe764 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe765 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe766 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe767 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe768 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe769 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe770 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe771 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe772 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe773 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe774 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe775 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe776 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe777 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe778 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe779 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe780 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe781 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe782 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe783 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe784 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe785 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe786 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe787 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe788 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe789 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe790 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe791 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe792 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe793 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe794 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe795 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe796 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe797 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe798 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe799 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe800 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe801 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe802 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe803 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe804 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe805 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe806 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe807 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe808 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe809 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe810 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe811 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe812 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe813 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe814 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe815 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe816 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe817 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe818 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe819 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe820 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe821 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe822 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe823 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe824 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe825 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe826 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe827 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe828 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe829 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe830 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe831 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe832 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe833 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe834 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe835 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe836 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe837 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe838 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe839 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe840 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe841 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe842 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe843 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe844 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe845 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe846 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe847 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe848 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe849 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe850 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe851 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe852 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe853 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe854 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe855 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe856 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe857 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe858 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe859 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe860 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe861 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe862 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe863 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe864 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe865 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe866 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe867 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe868 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe869 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe870 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe871 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe872 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe873 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe874 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe875 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe876 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe877 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe878 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe879 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe880 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe881 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe882 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe883 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe884 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe885 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe886 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe887 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe888 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe889 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe890 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe891 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe892 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe893 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe894 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe895 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe896 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe897 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe898 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe899 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe900 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe901 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe902 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe903 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe904 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe905 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe906 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe907 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe908 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe909 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe910 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe911 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe912 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe913 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe914 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe915 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe916 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe917 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe918 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe919 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe920 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe921 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe922 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe923 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe924 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe925 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe926 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe927 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe928 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe929 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe930 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe931 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe932 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe933 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe934 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe935 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe936 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe937 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe938 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe939 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe940 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe941 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe942 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe943 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe944 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe945 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe946 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe947 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe948 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe949 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe950 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe951 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe952 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe953 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe954 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe955 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe956 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe957 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe958 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe959 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe960 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe961 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe962 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe963 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe964 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe965 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe966 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe967 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe968 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe969 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe970 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe971 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe972 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe973 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe974 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe975 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe976 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe977 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe978 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe979 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe980 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe981 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe982 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe983 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe984 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe985 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe986 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe987 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe988 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe989 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe990 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe991 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe992 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe993 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe994 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe995 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe996 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe997 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe998 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe999 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1000 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1001 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1002 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1003 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1004 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1005 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1006 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1007 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1008 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1009 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1010 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1011 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1012 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1013 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1014 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1015 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1016 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1017 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1018 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1019 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1020 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1021 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1022 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
probe1023 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1))
);
END DemoInterconnect_ila_0_0_arch;
|
mit
|
bc05c297f84dcd961e223c8f841b536a
| 0.712037 | 2.406698 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/PC_register.vhd
| 1 | 1,168 |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PC_register is
port (
clk_in : in std_logic;
rst_in : in std_logic;
cargaPC_i : in std_logic;
incPC_i : in std_logic;
pc_data_i : in std_logic_vector(7 downto 0);
pc_data_o : out std_logic_vector(7 downto 0)
);
end PC_register;
architecture Behavioral of PC_register is
begin
process(clk_in, rst_in)
variable pc_data_o_w : std_logic_vector(7 downto 0); -- variavel auxiliar
variable incPC_cont : integer;
begin
if (rst_in = '1') then
pc_data_o_w := "00000001";
incPC_cont := 0;
elsif (clk_in = '1' and clk_in'event) then
if (cargaPC_i = '1') then
pc_data_o_w := pc_data_i;
elsif (incPC_i = '1') then
incPC_cont := incPC_cont + 1;
if incPC_cont = 2 then
pc_data_o_w := std_logic_vector(unsigned(pc_data_o_w) + 1);
incPC_cont := 0;
end if;
end if;
end if;
pc_data_o <= pc_data_o_w;
end process;
end Behavioral;
|
mit
|
e189637df7b3464bff8839bee0b77293
| 0.620069 | 2.737089 | false | false | false | false |
andbet050197/IS773UTP
|
sumadorcompleto/sumador_competo.vhd
| 1 | 1,941 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:06:40 02/19/2017
-- Design Name:
-- Module Name: sumpleto - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sumpleto is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC);
end sumpleto;
architecture Behavioral of sumpleto is
-- VHDL Instantiation Created from source file sumador_medio.vhd -- 20:10:20 02/19/2017
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT sumador_medio
PORT(
a : IN std_logic;
b : IN std_logic;
cout : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
signal out0 : STD_LOGIC := '0';
signal c0 : STD_LOGIC := '0';
signal out1 : STD_LOGIC := '0';
begin
Inst_sumador_medio_1: sumador_medio PORT MAP(
a => a,
b => b,
cout => out0,
s => c0
);
Inst_sumador_medio_2: sumador_medio PORT MAP(
a => c0,
b => cin,
cout => out1,
s => s
);
Inst_sumador_medio_3: sumador_medio PORT MAP(
a => out0,
b => out1,
--cout => ,
s => cout
);
end Behavioral;
|
gpl-3.0
|
638fb06e1b89d0ce90e457b168923b00
| 0.592993 | 3.42328 | false | false | false | false |
inforichland/freezing-spice
|
src/common.vhd
| 1 | 6,508 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package common is
-- definition for a machine word
subtype word is std_logic_vector(31 downto 0);
subtype reg_addr_t is std_logic_vector(4 downto 0);
subtype alu_func_t is std_logic_vector(3 downto 0);
constant ALU_NONE : alu_func_t := "0000";
constant ALU_ADD : alu_func_t := "0001";
constant ALU_ADDU : alu_func_t := "0010";
constant ALU_SUB : alu_func_t := "0011";
constant ALU_SUBU : alu_func_t := "0100";
constant ALU_SLT : alu_func_t := "0101";
constant ALU_SLTU : alu_func_t := "0110";
constant ALU_AND : alu_func_t := "0111";
constant ALU_OR : alu_func_t := "1000";
constant ALU_XOR : alu_func_t := "1001";
constant ALU_SLL : alu_func_t := "1010";
constant ALU_SRA : alu_func_t := "1011";
constant ALU_SRL : alu_func_t := "1100";
subtype insn_type_t is std_logic_vector(3 downto 0);
constant OP_ILLEGAL : insn_type_t := "0000";
constant OP_LUI : insn_type_t := "0001";
constant OP_AUIPC : insn_type_t := "0010";
constant OP_JAL : insn_type_t := "0011";
constant OP_JALR : insn_type_t := "0100";
constant OP_BRANCH : insn_type_t := "0101";
constant OP_LOAD : insn_type_t := "0110";
constant OP_STORE : insn_type_t := "0111";
constant OP_ALU : insn_type_t := "1000";
constant OP_STALL : insn_type_t := "1001";
constant OP_SYSTEM : insn_type_t := "1010";
subtype branch_type_t is std_logic_vector(2 downto 0);
constant BRANCH_NONE : branch_type_t := "000";
constant BEQ : branch_type_t := "001";
constant BNE : branch_type_t := "010";
constant BLT : branch_type_t := "011";
constant BGE : branch_type_t := "100";
constant BLTU : branch_type_t := "101";
constant BGEU : branch_type_t := "110";
subtype load_type_t is std_logic_vector(2 downto 0);
constant LOAD_NONE : load_type_t := "000";
constant LB : load_type_t := "001";
constant LH : load_type_t := "010";
constant LW : load_type_t := "011";
constant LBU : load_type_t := "100";
constant LHU : load_type_t := "101";
subtype store_type_t is std_logic_vector(1 downto 0);
constant STORE_NONE : store_type_t := "00";
constant SB : store_type_t := "01";
constant SH : store_type_t := "10";
constant SW : store_type_t := "11";
subtype system_type_t is std_logic_vector(2 downto 0);
constant SYSTEM_ECALL : system_type_t := "000";
constant SYSTEM_EBREAK : system_type_t := "001";
constant SYSTEM_CSRRW : system_type_t := "010";
constant SYSTEM_CSRRS : system_type_t := "011";
constant SYSTEM_CSRRC : system_type_t := "100";
constant SYSTEM_CSRRWI : system_type_t := "101";
constant SYSTEM_CSRRSI : system_type_t := "110";
constant SYSTEM_CSRRCI : system_type_t := "111";
-- print a string with a newline
procedure println (str : in string);
procedure print (slv : in std_logic_vector);
procedure write(l : inout line; slv : in std_logic_vector);
function hstr(slv : std_logic_vector) return string;
-- instruction formats
type r_insn_t is (R_ADD, R_SLT, R_SLTU, R_AND, R_OR, R_XOR, R_SLL, R_SRL, R_SUB, R_SRA);
type i_insn_t is (I_JALR, I_LB, I_LH, I_LW, I_LBU, I_LHU, I_ADDI, I_SLTI, I_SLTIU, I_XORI, I_ORI, I_ANDI, I_SLLI, I_SRLI, I_SRAI);
type s_insn_t is (S_SB, S_SH, S_SW);
type sb_insn_t is (SB_BEQ, SB_BNE, SB_BLT, SB_BGE, SB_BLTU, SB_BGEU);
type u_insn_t is (U_LUI, U_AUIPC);
type uj_insn_t is (UJ_JAL);
-- ADDI r0, r0, r0
constant NOP : word := "00000000000000000000000000010011";
end package common;
package body common is
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- print a string with a newline
procedure println (str : in string) is
variable l : line;
begin -- procedure println
write(l, str);
writeline(output, l);
end procedure println;
procedure write(l : inout line; slv : in std_logic_vector) is
begin
for i in slv'range loop
if slv(i) = '0' then
write(l, string'("0"));
elsif slv(i) = '1' then
write(l, string'("1"));
elsif slv(i) = 'X' then
write(l, string'("X"));
elsif slv(i) = 'U' then
write(l, string'("U"));
end if;
end loop; -- i
end procedure write;
procedure print (slv : in std_logic_vector) is
variable l : line;
begin -- procedure print
write(l, slv);
writeline(output, l);
end procedure print;
end package body common;
|
bsd-3-clause
|
2d0bc5d1bdad0e90891ce367bfcf9eae
| 0.532883 | 3.334016 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica6/motorMoviendose.vhd
| 1 | 4,770 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:38:55 10/23/2011
-- Design Name:
-- Module Name: motorMoviendose - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity motorMoviendose is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
motor0 : out STD_LOGIC;
motor1 : out STD_LOGIC;
motor2 : out STD_LOGIC;
motor3 : out STD_LOGIC;
parlante : out STD_LOGIC);
end motorMoviendose;
architecture Behavioral of motorMoviendose is
-- Definiendo estados Motor
type estadosMotor is (p0,p1,p2,p3,p4,p5,p6,p7);
signal estadoActual : estadosMotor;
signal estadoAnterior : estadosMotor;
-- Definiendo señales internas
signal contadorMotor : STD_LOGIC_VECTOR (4 downto 0) := "00000";
signal cuantosPasos : STD_LOGIC_VECTOR (4 downto 0) := "10100";
signal derecha : STD_LOGIC := '1';
begin
process(reset)
begin
if (reset = '1') then
derecha <= '1';
contadorMotor <= "00000";
cuantosPasos <= "10100";
estadoActual <= p0;
estadoAnterior <= p0;
parlante <= '0';
motor0 <= '0';
motor1 <= '0';
motor2 <= '0';
motor3 <= '0';
end if;
end process;
---------------------------------------------
-- Máquina de estados Motor
---------------------------------------------
process(clock,reset,derecha,cuantosPasos,estadoAnterior,contadorMotor)
-- Responsable de calcular 'estadoActual'
-- Controla 'parlante' y 'contadorMotor'
begin
if (reset = '0' and clock'event and clock = '1') then -- Si detectó un flanco de subida en el reloj...
if (contadorMotor = cuantosPasos) then -- Si ya terminé coloco mi contador en cero
contadorMotor <= "00000";
parlante <= '0';
estadoActual <= estadoAnterior;
else
contadorMotor <= contadorMotor + 1; -- avanzo el contador...
parlante <= '1'; -- hago sonar el parlante...
if derecha = '1' then -- y, si tengo que girar a la derecha...
case estadoAnterior is
when p0 =>
estadoActual <= p1;
when p1 =>
estadoActual <= p2;
when p2 =>
estadoActual <= p3;
when p3 =>
estadoActual <= p4;
when p4 =>
estadoActual <= p5;
when p5 =>
estadoActual <= p6;
when p6 =>
estadoActual <= p7;
when p7 =>
estadoActual <= p0;
end case;
elsif derecha = '0' then -- pero, si tengo que girar a la izquierda...
case estadoAnterior is
when p0 =>
estadoActual <= p7;
when p1 =>
estadoActual <= p0;
when p2 =>
estadoActual <= p1;
when p3 =>
estadoActual <= p2;
when p4 =>
estadoActual <= p3;
when p5 =>
estadoActual <= p4;
when p6 =>
estadoActual <= p5;
when p7 =>
estadoActual <= p6;
end case;
end if;
end if;
end if;
end process maquinaEstadosMotor;
---------------------------------------------
-- Lógica secuencia motor
---------------------------------------------
secuenciaMotor : process(reset,estadoActual) -- Aquí voy a manejar las sucencias
begin
if (reset = '0') then
case estadoActual is
when p0 =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '0';
motor3 <= '1';
when p1 =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '1';
motor3 <= '1';
when p2 =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '1';
motor3 <= '0';
when p3 =>
motor0 <= '0';
motor1 <= '1';
motor2 <= '1';
motor3 <= '0';
when p4 =>
motor0 <= '0';
motor1 <= '1';
motor2 <= '0';
motor3 <= '0';
when p5 =>
motor0 <= '1';
motor1 <= '1';
motor2 <= '0';
motor3 <= '0';
when p6 =>
motor0 <= '1';
motor1 <= '0';
motor2 <= '0';
motor3 <= '0';
when p7 =>
motor0 <= '1';
motor1 <= '0';
motor2 <= '0';
motor3 <= '1';
when others =>
motor0 <= '0';
motor1 <= '0';
motor2 <= '0';
motor3 <= '0';
end case;
end if;
end process secuenciaMotor;
end Behavioral;
|
gpl-2.0
|
b485c3a6053ba046bc697169f0946347
| 0.527883 | 3.317107 | false | false | false | false |
rmilfont/Phoenix
|
topNoC.vhd
| 1 | 2,179 |
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
use work.PhoenixPackage.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
entity topNoC is
end;
architecture topNoC of topNoC is
signal clock : regNrot:=(others=>'0');
signal reset : std_logic;
signal clock_rx: regNrot:=(others=>'0');
signal rx, credit_o: regNrot;
signal clock_tx, tx, credit_i, testLink_i, testLink_o: regNrot;
signal data_in, data_out : arrayNrot_regflit;
signal currentTime: std_logic_vector(4*TAM_FLIT-1 downto 0) := (others=>'0');
begin
reset <= '1', '0' after 10 ns;
clock <= not clock after 10 ns;
clock_rx <= not clock_rx after 10 ns;
--credit_i <= (others=>'1');
credit_i <= tx;
testLink_i <= (others=>'0');
NOC: Entity work.NOC
port map(
clock => clock,
reset => reset,
clock_rxLocal => clock_rx,
rxLocal => rx,
data_inLocal_flit => data_in,
credit_oLocal => credit_o,
clock_txLocal => clock_tx,
txLocal => tx,
data_outLocal_flit => data_out,
credit_iLocal => credit_i
);
-- 0: destino do pacote
-- 1: tamanho do pacote
-- 2: nodo origem
-- 3 a 6: timestamp do nodo de origem
-- 7 a 8: numero de sequencia do pacote
-- 9 a 12: timestamp de entrada na rede
-- 13+: payload
process (reset, clock(0))
begin
if (reset = '1') then
currentTime <= (others=>'0');
elsif (rising_edge(clock(0))) then
currentTime <= currentTime + 1;
end if;
end process;
InputModules: for i in 0 to (NROT-1) generate
IM : Entity work.inputModule
generic map(address => NUMBER_TO_ADDRESS(i))
port map(
done => rx(i),
data => data_in(i),
enable => credit_o(i),
currentTime => currentTime
);
end generate InputModules;
OutputModules: for i in 0 to (NROT-1) generate
OM : Entity work.outputModule
generic map(address => NUMBER_TO_ADDRESS(i))
port map(
clock => clock(i),
tx => tx(i),
data => data_out(i),
currentTime => currentTime
);
end generate OutputModules;
end topNoC;
|
lgpl-3.0
|
9d1e6a9e3a0f1b937b56fbc6d70c4bd2
| 0.609913 | 3.218612 | false | false | false | false |
dl3yc/sdr-fm
|
testing/euler-1.0/sim/euler_tb.vhd
| 1 | 5,201 |
-- title: Testbench for VCORDIC
-- author: Sebastian Weiss
-- last change: 03.12.14
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity euler_tb is
end entity;
architecture behavioral of euler_tb is
constant A : natural := 16;
constant P : natural := 24;
constant N : natural := 15;
signal clk : std_logic := '0';
signal i : signed(A-1 downto 0) := (others => '0');
signal q : signed(A-1 downto 0) := (others => '0');
signal amp : unsigned(A-1 downto 0);
signal phi : signed(P-1 downto 0) := (others => '0');
begin
dut : entity work.euler
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => i,
q => q,
amp => amp,
phi => phi
);
process
begin
wait until rising_edge(clk);
i <= to_signed(integer(1.0 * 2.0**(A-1)-1.0),A);
q <= to_signed(integer(1.0 * 2.0**(A-1)-1.0),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
q <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.5 * 2.0**(A-1)),A);
q <= to_signed(integer(0.2 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(-0.1 * 2.0**(A-1)),A);
q <= to_signed(integer(0.9 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(-1.0 * 2.0**(A-1)+1.0),A);
q <= to_signed(integer(-1.0 * 2.0**(A-1)+1.0),A);
wait until rising_edge(clk);
i <= to_signed(integer(-0.7071 * 2.0**(A-1)),A);
q <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.5 * 2.0**(A-1)),A);
q <= to_signed(integer(-0.2 * 2.0**(A-1)),A);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
i <= to_signed(integer(0.0 * (2.0**(A-1)-1.0)),A);
q <= to_signed(integer(0.0 * (2.0**(A-1)-1.0)),A);
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.4142 * 2.0**(A-1)),A)) and (amp >= to_unsigned(integer(0.99 * 1.4142 * 2.0**(A-1)),A))
report "case 1 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P))
report "case 2 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.0 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 1.0 * 2.0**(A-1)),A))
report "case 3 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P))
report "case 4 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.5385 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.5385 * 2.0**(A-1)),A))
report "case 5 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P))
report "case 6 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.9055 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.9055 * 2.0**(A-1)),A))
report "case 7 failed!" severity error;
assert (phi < to_signed(integer(1.01 * 1.6815/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * 1.6815/(MATH_PI) * 2.0**(P-1)),P))
report "case 8 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.4142 * 2.0**(A-1)),A)) and (amp >= to_unsigned(integer(0.99 * 1.4142 * 2.0**(A-1)),A))
report "case 9 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P))
report "case 10 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.0 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 1.0 * 2.0**(A-1)),A))
report "case 11 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P))
report "case 12 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.5385 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.5385 * 2.0**(A-1)),A))
report "case 13 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P))
report "case 14 failed!" severity error;
report "all tests finished!";
wait;
end process;
clk <= not clk after 11363 ps;
end behavioral;
|
gpl-2.0
|
569ba347cd1d2ae24209eb08ecde5d0b
| 0.594117 | 2.466098 | false | false | false | false |
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/src/parallel2serial.vhd
| 1 | 2,570 |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: P2S Serializer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity parallel2serial is
generic (
DATA_WIDTH : integer := 8;
TX_WIDTH : integer := 1
);
port (
clk_i : in std_logic;
en_i : in std_logic;
send_i : in std_logic;
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
done_o : out std_logic;
shift_o : out std_logic_vector(TX_WIDTH-1 downto 0);
ss_o : out std_logic
) ;
end parallel2serial;
architecture behave of parallel2serial is
----------------------------------
constant SHIFT_STAGES : integer := integer(ceil(real(DATA_WIDTH)/real(TX_WIDTH)));
----------------------------------
signal shift_count : integer range 0 to SHIFT_STAGES := SHIFT_STAGES-1;
signal send_data : std_logic_vector(SHIFT_STAGES*TX_WIDTH-1 downto 0) := (others=>'0');
signal sending : std_logic := '0';
signal tx_done : std_logic := '0';
----------------------------------
begin
send_ctrl: process(clk_i, en_i, data_i, sending, tx_done)
begin
if rising_edge(clk_i) then
if en_i = '1' and sending='0' then
send_data <= (others=>'0');
send_data(DATA_WIDTH-1 downto 0) <= data_i; --register new data to send when not sending
sending <= '1';
elsif sending='1' and tx_done='1' then
sending <= '0';
end if;
end if;
end process;
shift_out: process(clk_i, shift_count, send_data, sending, tx_done)
begin
if rising_edge(clk_i) then
if sending = '1' and tx_done='0' and send_i='1' then
shift_o <= send_data((shift_count)*(TX_WIDTH)+(TX_WIDTH)-1 downto (shift_count)*(TX_WIDTH)); --MSB first
else
shift_o <= (others=>'0');
end if;
end if;
end process;
count_shift: process(clk_i, shift_count, send_data, sending, tx_done)
begin
if rising_edge(clk_i) then
if sending = '1' and tx_done='0' and send_i='1' then
if shift_count = 0 then
shift_count <= SHIFT_STAGES-1;
tx_done <= '1';
else
shift_count <= shift_count - 1;
end if;
ss_o <= '0';
else
tx_done <= '0';
ss_o <= '1';
end if;
end if;
end process;
busy_o <= sending;
done_o <= tx_done;
end behave;
|
mit
|
b9cdfe9e084cce2b0946094775edff33
| 0.549416 | 3.363874 | false | false | false | false |
rmilfont/Phoenix
|
NoC/Table_package.vhd
| 1 | 5,829 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.PhoenixPackage.all;
package TablePackage is
constant NREG : integer := 6;
constant MEMORY_SIZE : integer := NREG;
constant NBITS : integer := 4;
constant CELL_SIZE : integer := 2*NPORT+4*NBITS;
subtype cell is std_logic_vector(CELL_SIZE-1 downto 0);
subtype regAddr is std_logic_vector(2*NBITS-1 downto 0);
type memory is array (0 to MEMORY_SIZE-1) of cell;
type tables is array (0 to NROT-1) of memory;
constant TAB: tables :=(
-- Router 0.0
(("10000000000010000010000100"),
( "10000000100000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.1
(("11100000100000100000100001"),
("11001000000100100010000100"),
("10101000000000000000001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.2
(("10101000000000000000101000"),
("11001000000110100010000100"),
("11100000100000100001000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.3
(("11100000100110010001100001"),
("11001000001000010010000100"),
("11100001100110100010000001"),
("10101000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 0.4
(("11000000101000010010000001"),
("10000001100000100010001001"),
("10001000000000010001101000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.0
(("10101000000000000000000010"),
("10010000000010001010000100"),
("10010001000000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.1
(("10111000000000001000001000"),
("11001000000000000000100010"),
("11110001000000100000100001"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 1.2
(("11110001000100010001000001"),
("10111000000000000000001000"),
("11001000000000000010000010"),
("11110001100100100010000001"),
("11001000100110100010000100"),
("10111000100000100000101000")
),
-- Router 1.3
(("11110001000110010001100001"),
("11011000101000010010000100"),
("11110001100110100010000001"),
("11101000000000000010000010"),
("10111000100000100001001000"),
("00000000000000000000000000")
),
-- Router 1.4
(("10001000001000000010000010"),
("10000001100000100010001001"),
("10001000000000010001101000"),
("11010001000000100010000001"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.0
(("10101000000000001000000010"),
("10010001100000100010000001"),
("10010000000010010010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.1
(("10111000000000010000001000"),
("11110001100000100000100001"),
("11001000000000001000100010"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 2.2
(("10111001000000010000101000"),
("10111000000000001000001000"),
("11001000000000001001000010"),
("11110001100000100010000001"),
("11001000000110100010000100"),
("00000000000000000000000000")
),
-- Router 2.3
(("10111000000000001000001000"),
("11001000001000010010000100"),
("11110001100110100010000001"),
("11001000000000001001100010"),
("10111001000000100001001000"),
("00000000000000000000000000")
),
-- Router 2.4
(("10010001000000010001101000"),
("10010001100000100010001000"),
("11000000000000001010000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.0
(("10101000000000010000000010"),
("10010010000000100010000001"),
("10010000000010011010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.1
(("11110010000000100000100001"),
("10111000000000011000001000"),
("11001000000000010000100010"),
("11001000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.2
(("11011001100110011010000100"),
("11110010000100100010000001"),
("10111001100000100000101000"),
("11101000000000010010000010"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.3
(("11011001101000011010000100"),
("11110010000110100010000001"),
("10101000000110010010000010"),
("10101000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 3.4
(("10000001100000011001101000"),
("10000010000000100010000001"),
("10000000000000010010001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.0
(("10010000000010100010000100"),
("10100000000000011000000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.1
(("10110000000000100000001000"),
("11000000000000011000100010"),
("11000000000100100010000100"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.2
(("11010010000110100010000100"),
("10110010000000100000101000"),
("11100000000000011010000010"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.3
(("11010001101000100010000100"),
("10100000000110011010000010"),
("10100000000000100001001000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
),
-- Router 4.4
(("11000001101000011010000010"),
("10010000000000010010001000"),
("10010001100000100001101000"),
("00000000000000000000000000"),
("00000000000000000000000000"),
("00000000000000000000000000")
)
);
end TablePackage;
package body TablePackage is
end TablePackage;
|
lgpl-3.0
|
648b62a6c489ecd2a88bdbd5fef4fdbb
| 0.777492 | 4.982051 | false | false | false | false |
dl3yc/sdr-fm
|
dev/dfir/dfir.vhd
| 1 | 5,431 |
-- DFIR module for Betty SDR
-- implements a decimating FIR filter for odd filter order without symmetry presumption
-- file: dfir.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with dirac impulse
-- - test for linear phase with complex carrier
--
-- needs generics with definition of dfir_order and dfir_coeff
-- with dfir_order+1 elements in Q0.26 signed fixed point format
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dfir_types is
type dfir_coeff_t is array(natural range <>) of signed(26 downto 0);
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dfir_types.all;
entity dfir is
generic (
dfir_order : natural;
dfir_coeff : dfir_coeff_t
);
port (
clk : in std_logic;
stb : in std_logic;
d : in signed(26 downto 0);
q : out signed(26 downto 0);
rdy : out std_logic
);
end entity dfir;
architecture rtl of dfir is
-- shift register
type shift_t is array(dfir_order/2 downto 0) of signed(26 downto 0);
type sr_t is record
input : signed(26 downto 0);
shift : shift_t;
sel : std_logic;
en : std_logic;
end record;
constant sr_default : sr_t := (
input => (others => '0'),
shift => (others => (others => '0')),
sel => '0',
en => '0'
);
signal sr0 : sr_t := sr_default;
signal sr1 : sr_t := sr_default;
signal sr_en : std_logic;
signal sr_sel : std_logic := '0';
-- coeff ROM
signal rom : dfir_coeff_t(dfir_order downto 0) := dfir_coeff;
signal coeff : signed(26 downto 0);
signal coeff_index : natural range 0 to dfir_order;
-- MAC unit
type mac_t is record
in_a : signed(26 downto 0);
in_b : signed(26 downto 0);
mult_out : signed(53 downto 0);
acc_out : signed(53 downto 0);
mac_out : signed(26 downto 0);
clr : std_logic;
stb : std_logic;
en : std_logic;
end record;
constant mac_default : mac_t := (
in_a => (others => '0'),
in_b => (others => '0'),
mult_out => (others => '0'),
acc_out => (others => '0'),
mac_out => (others => '0'),
clr => '0',
stb => '0',
en => '0'
);
signal mac : mac_t := mac_default;
-- finite state machine
type state_t is (reset, prolog, multiply_and_add, epilog);
signal state : state_t;
signal fsm_index : natural range 0 to dfir_order/2;
signal phase : std_logic := '0';
begin
rom_register : process
begin
wait until rising_edge(clk);
coeff <= rom(coeff_index);
end process rom_register;
shift_register0 : process
begin
wait until rising_edge(clk);
if sr0.en = '1' and phase = '0' then
sr0.shift(sr0.shift'high downto sr0.shift'low+1) <= sr0.shift(sr0.shift'high-1 downto sr0.shift'low);
if sr0.sel = '1' then
sr0.shift(sr0.shift'low) <= sr0.input;
else
sr0.shift(sr0.shift'low) <= sr0.shift(sr0.shift'high);
end if;
end if;
end process shift_register0;
sr0.input <= d;
sr0.en <= sr_en when phase = '0' else '0';
sr0.sel <= sr_sel;
shift_register1 : process
begin
wait until rising_edge(clk);
if sr1.en = '1' and phase = '1' then
sr1.shift(sr1.shift'high downto sr1.shift'low+1) <= sr1.shift(sr1.shift'high-1 downto sr1.shift'low);
if sr1.sel = '1' then
sr1.shift(sr1.shift'low) <= sr1.input;
else
sr1.shift(sr1.shift'low) <= sr1.shift(sr1.shift'high);
end if;
end if;
end process shift_register1;
sr1.input <= d;
sr1.en <= sr_en when phase = '1' else '0';
sr1.sel <= sr_sel;
mac_unit : process
begin
wait until rising_edge(clk);
mac.in_a <= coeff;
if phase = '0' then
mac.in_b <= sr0.shift(sr0.shift'high);
else
mac.in_b <= sr1.shift(sr1.shift'high);
end if;
mac.mult_out <= mac.in_a * mac.in_b;
if mac.clr = '1' then
mac.acc_out <= (others => '0');
else
if mac.en = '1' then
mac.acc_out <= mac.acc_out + mac.mult_out;
end if;
end if;
if mac.stb = '1' then
mac.mac_out <= mac.acc_out(52 downto 26);
end if;
end process mac_unit;
fsm : process
begin
wait until rising_edge(clk);
case state is
when reset =>
sr_en <= '0';
rdy <= '0';
mac.stb <= '0';
fsm_index <= 0;
if stb = '1' then
sr_en <= '1';
sr_sel <= '1';
state <= prolog;
end if;
when prolog =>
sr_sel <= '0';
fsm_index <= fsm_index + 1;
if phase = '0' then
coeff_index <= 2 * fsm_index + 1;
else
coeff_index <= 2 * fsm_index;
end if;
if fsm_index = 0 then
sr_en <= '0';
else
sr_en <= '1';
end if;
if fsm_index = 2 and phase = '0' then
mac.clr <= '1';
end if;
if fsm_index = 3 then
mac.clr <= '0';
mac.en <= '1';
state <= multiply_and_add;
end if;
when multiply_and_add =>
if phase = '0' then
coeff_index <= 2 * fsm_index + 1;
else
coeff_index <= 2 * fsm_index;
end if;
if fsm_index = dfir_order/2 then
state <= epilog;
fsm_index <= 0;
else
fsm_index <= fsm_index + 1;
end if;
when epilog =>
fsm_index <= fsm_index + 1;
if fsm_index = 1 then
sr_en <= '0';
end if;
if fsm_index = 3 then
phase <= not phase;
state <= reset;
mac.en <= '0';
if phase = '1' then
mac.stb <= '1';
rdy <= '1';
end if;
end if;
end case;
end process fsm;
q <= mac.mac_out;
assert (dfir_order mod 2 = 1) report("only support for odd filter order") severity failure;
end architecture rtl;
|
gpl-2.0
|
0f5e3dd48640d0d1895d60146a736345
| 0.600074 | 2.674052 | false | false | false | false |
egk696/InterNoC
|
ip_repo/axi_i2c_master_1.0/hdl/axi_i2c_master_v1_0_S00_AXI.vhd
| 1 | 11,101 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_i2c_master_v1_0_S00_AXI is
generic (
-- Users to add parameters here
I2C_DATA_WIDTH : integer := 8;
I2C_CLK_DIV : integer := 720;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
i2c_sda : inout : std_logic;
i2c_scl : inout : std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_i2c_master_v1_0_S00_AXI;
architecture arch_imp of axi_i2c_master_v1_0_S00_AXI is
-- Components
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Packet logic
signal packet_byte_cnt : std_logic_vector(2 downto 0) := "100";
-- SPI interface signals
signal i2c_tx_start : std_logic := '0';
signal i2c_tx_rx_busy : std_logic := '0';
signal i2c_tx_rx_done : std_logic := '0';
signal i2c_rx_byte : std_logic_vector(SPI_DATA_WIDTH-1 downto 0);
-- PISO SIPO converters interface signals
signal p2s_load : std_logic := '0';
signal p2s_send : std_logic := '0';
signal p2s_busy : std_logic := '0';
signal p2s_ss : std_logic := '0';
signal p2s_done : std_logic := '0';
signal s2p_en : std_logic := '0';
signal s2p_done : std_logic := '0';
-- Registers
signal slv_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_wdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
wr_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
wr_addr_latch: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
wr_data_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
wr_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
rd_addr_valid: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and i2c_rx_done='1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
rd_response: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
axi_rdata <= slv_rdata;
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
9c86ca34734c26e63fa59e651cd832e0
| 0.646518 | 3.349728 | false | false | false | false |
LaNoC-UFC/NoCThor
|
NoC/RouterCC.vhd
| 1 | 1,998 |
library IEEE;
use IEEE.std_logic_1164.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity RouterCC is
generic(
address: regflit;
ramInit: memory);
port(
clock: in std_logic;
reset: in std_logic;
clock_rx: in regNport;
rx: in regNport;
data_in: in arrayNport_regflit;
credit_o: out regNport;
clock_tx: out regNport;
tx: out regNport;
data_out: out arrayNport_regflit;
credit_i: in regNport);
end RouterCC;
architecture RouterCC of RouterCC is
signal h, ack_h, data_av, sender, data_ack: regNport := (others=>'0');
signal data: arrayNport_regflit := (others=>(others=>'0'));
signal mux_in, mux_out: arrayNport_reg3 := (others=>(others=>'0'));
signal free: regNport := (others=>'0');
begin
buff : for i in EAST to LOCAL generate
B : entity work.Thor_buffer
port map(
clock => clock,
reset => reset,
data_in => data_in(i),
rx => rx(i),
h => h(i),
ack_h => ack_h(i),
data_av => data_av(i),
data => data(i),
sender => sender(i),
clock_rx => clock_rx(i),
data_ack => data_ack(i),
credit_o => credit_o(i));
clock_tx(i) <= clock;
end generate buff;
SwitchControl : Entity work.SwitchControl
generic map(
address => address,
ramInit => ramInit)
port map(
clock => clock,
reset => reset,
h => h,
ack_h => ack_h,
data => data,
sender => sender,
free => free,
mux_in => mux_in,
mux_out => mux_out);
CrossBar : Entity work.Thor_crossbar
port map(
data_av => data_av,
data_in => data,
data_ack => data_ack,
sender => sender,
free => free,
tab_in => mux_in,
tab_out => mux_out,
tx => tx,
data_out => data_out,
credit_i => credit_i);
end RouterCC;
|
lgpl-3.0
|
7ff384213f31331b0d2b08b10cf564f9
| 0.521522 | 3.567857 | false | false | false | false |
dl3yc/sdr-fm
|
dev/euler/vcordic.vhd
| 1 | 2,284 |
-- VCORDIC module for Betty SDR
-- implements CORDIC in Vector Mode
-- file: vcordic.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - functional testing with matlab as reference implementation
--
-- delay: N+2 clock cycles
--
-- !!! because of the arctan table used in the CORDIC algorithm
-- !!! it only converges in the range of -1(rad) to +1(rad)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic is
generic
(
A : natural;
P : natural;
N : natural
);
port
(
clk : in std_logic;
i : in signed(A-1 downto 0);
q : in signed(A-1 downto 0);
amp : out unsigned(A-1 downto 0);
phi : out signed(P-1 downto 0)
);
end entity;
architecture behavioral of vcordic is
type alpha_t is array(0 to N-1) of signed(P-1 downto 0); -- -180°..180°
type xy_vector is array(natural range <>) of signed(A+2 downto 0); -- -3.999..+3.999
type z_vector is array(natural range <>) of signed(P-1 downto 0); -- -180°..180°
constant K : signed(A-1 downto 0) := to_signed(integer(0.6073*2**(A-1)),A);
signal alpha : alpha_t;
signal x,y : xy_vector(N downto 0) := (others => (others => '0'));
signal z : z_vector(N downto 0) := (others => (others => '0'));
begin
table: for i in 0 to N-1 generate
alpha(i) <= to_signed(integer( atan(1.0/real(2**i)) * (real(2**(P-1))-1.0) / math_pi ),P);
end generate;
process begin
wait until rising_edge(clk);
if i >= 0 then
x(0) <= resize(i,A+3);
y(0) <= resize(q,A+3);
z(0) <= (others => '0');
elsif q >= 0 then
x(0) <= resize(q,A+3);
y(0) <= resize(-i,A+3);
z(0) <= to_signed(2**(P-2),P);-- 90° ??? TODO: TEST
else
x(0) <= resize(-q,A+3);
y(0) <= resize(i,A+3);
z(0) <= to_signed(-2**(P-2),P);-- -90° ??? TODO: TEST
end if;
for i in 1 to N loop
if x(i-1) >= 0 then
x(i) <= x(i-1) - y(i-1) / 2**(i-1);
y(i) <= y(i-1) + x(i-1) / 2**(i-1);
z(i) <= z(i-1) + alpha(i-1);
else
x(i) <= x(i-1) + y(i-1) / 2**(i-1);
y(i) <= y(i-1) - x(i-1) / 2**(i-1);
z(i) <= z(i-1) - alpha(i-1);
end if;
end loop;
amp <= resize(unsigned(shift_right((y(N) * K), (A-1))),A);
phi <= z(N);
end process;
end behavioral;
|
gpl-2.0
|
a86fb22c8c82ab7073d6598d06b6e973
| 0.564969 | 2.415695 | false | false | false | false |
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/src/serial2parallel.vhd
| 1 | 2,576 |
-- Engineer: Lefteris Kyriakakis
--
-- Create Date: 06/28/2017
-- Design Name: Serial-In-Parallel-Out Shift Register
-- Module Name: S2P Parallelizer - behave
-- Target Devices: Any
----------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity serial2parallel is
generic (
DATA_WIDTH : integer := 8;
TX_WIDTH : integer := 1
);
port (
clk_i : in std_logic;
en_i : in std_logic;
shift_i : in std_logic_vector(TX_WIDTH-1 downto 0);
done_o : out std_logic;
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
) ;
end serial2parallel;
architecture behave of serial2parallel is
----------------------------------
constant SHIFT_STAGES : integer := integer(ceil(real(DATA_WIDTH)/real(TX_WIDTH)));
----------------------------------
signal shift_count : integer range 0 to SHIFT_STAGES-1 := SHIFT_STAGES-1;
signal rx_done : std_logic := '0';
signal rx_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal shift_data : std_logic_vector(SHIFT_STAGES*TX_WIDTH-1 downto 0) := (others=>'0');
signal init_rx_ff, init_rx_ff2 : std_logic := '0';
signal rx_en : std_logic := '0';
----------------------------------
attribute shreg_extract : string;
attribute shreg_extract of rx_data : signal is "yes";
begin
init_rx_pulse: process(clk_i, en_i)
begin
if rising_edge(clk_i) then
init_rx_ff <= en_i;
init_rx_ff2 <= init_rx_ff;
rx_en <= not(init_rx_ff2) and init_rx_ff;
end if;
end process;
shift_in: process(clk_i, rx_en, rx_data, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if rx_en = '1' and rx_done='0' then
--shift_data(TX_WIDTH-1 downto 0) <= shift_i; --MSB First
--shift_data(DATA_WIDTH-1 downto TX_WIDTH) <= shift_data(DATA_WIDTH-TX_WIDTH-1 downto 0);
shift_data <= shift_data(SHIFT_STAGES*TX_WIDTH-1-TX_WIDTH downto 0) & shift_i;
end if;
end if;
end process;
count_shift: process(clk_i, rx_en, rx_data, shift_i, rx_done, shift_count)
begin
if rising_edge(clk_i) then
if rx_en = '1' then
if shift_count = 0 then
shift_count <= SHIFT_STAGES-1;
rx_done <= '1';
else
shift_count <= shift_count - 1;
end if;
elsif rx_done='1' then
rx_done <= '0';
end if;
end if;
end process;
done_o <= rx_done;
data_o <= shift_data(DATA_WIDTH-1 downto 0); --align data to the requested width
end architecture ;
|
mit
|
4c15fc3d710a6e33543f815b3dc2e732
| 0.598214 | 3.088729 | false | false | false | false |
egk696/InterNoC
|
InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_axi_spi_master_0_1/sim/DemoInterconnect_axi_spi_master_0_1.vhd
| 2 | 10,931 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: ekyr.kth.se:user:axi_spi_master:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DemoInterconnect_axi_spi_master_0_1 IS
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END DemoInterconnect_axi_spi_master_0_1;
ARCHITECTURE DemoInterconnect_axi_spi_master_0_1_arch OF DemoInterconnect_axi_spi_master_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DemoInterconnect_axi_spi_master_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_spi_master_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER; -- Width of S_AXI address bus
SPI_DATA_WIDTH : INTEGER;
SPI_CLK_DIV : INTEGER
);
PORT (
m_spi_mosi : OUT STD_LOGIC;
m_spi_miso : IN STD_LOGIC;
m_spi_ss : OUT STD_LOGIC;
m_spi_sclk : OUT STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT axi_spi_master_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW, XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST, xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S00_AXI";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK, xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s00_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_sclk: SIGNAL IS "XIL_INTERFACENAME m_spi_sclk, ASSOCIATED_CLKEN m_spi_ss, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN DemoInterconnect_axi_spi_master_0_1_m_spi_sclk";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_sclk: SIGNAL IS "xilinx.com:signal:clock:1.0 m_spi_sclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_ss: SIGNAL IS "XIL_INTERFACENAME m_spi_ss, FREQ_HZ 100000000, PHASE 0, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_ss: SIGNAL IS "xilinx.com:signal:clockenable:1.0 m_spi_ss CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_miso: SIGNAL IS "XIL_INTERFACENAME m_spi_miso, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_miso: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_miso DATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_spi_mosi: SIGNAL IS "XIL_INTERFACENAME m_spi_mosi, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_spi_mosi: SIGNAL IS "xilinx.com:signal:data:1.0 m_spi_mosi DATA";
BEGIN
U0 : axi_spi_master_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4,
SPI_DATA_WIDTH => 8,
SPI_CLK_DIV => 6
)
PORT MAP (
m_spi_mosi => m_spi_mosi,
m_spi_miso => m_spi_miso,
m_spi_ss => m_spi_ss,
m_spi_sclk => m_spi_sclk,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END DemoInterconnect_axi_spi_master_0_1_arch;
|
mit
|
4c9c09535231075d2df38b54f2bfd6c6
| 0.712744 | 3.190601 | false | false | false | false |
andbet050197/IS773UTP
|
Latch/LatchSR_AA_TB.vhd
| 1 | 1,028 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AA_TB IS
END LatchSR_AA_TB;
ARCHITECTURE behavior OF LatchSR_AA_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AA
PORT(
S : IN std_logic;
R : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
--Inputs
signal S : std_logic := '0';
signal R : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LatchSR_AA PORT MAP (
S => S,
R => R,
Q => Q,
Qn => Qn
);
-- Stimulus process
stim_proc: process
begin
-- S = '1' y R = '1';
R <= '1';
S <= '1';
wait for 100 ns;
-- S = '1' y R = '0';
R <= '0';
wait for 100 ns;
-- S = '0' y R = '1';
R <= '1';
S <= '0';
wait for 100 ns;
-- S = '0' y R = '0';
R <= '0';
wait;
end process;
END;
|
gpl-3.0
|
de47e72a40b64ec4679d12cb17aaacc4
| 0.470817 | 3.077844 | false | false | false | false |
rdveiga/Neander_VHDL
|
vhdl/decoder.vhd
| 1 | 2,830 |
-- Author: Ronaldo Dall'Agnol Veiga
-- @roniveiga
-- UFRGS - Instituto de Informática
-- Sistemas Digitais
-- Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;d
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decoder is
Port ( instruction_in : in STD_LOGIC_VECTOR (7 downto 0);
--decod_instr : out STD_LOGIC_VECTOR(3 downto 0);
s_exec_nop, s_exec_sta, s_exec_lda, s_exec_add, s_exec_or, s_exec_shr, s_exec_shl, s_exec_mul,
s_exec_and, s_exec_not, s_exec_jmp, s_exec_jn, s_exec_jz, s_exec_hlt : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
begin
-- decod_instr <= instruction_in(7 downto 4);
-- 0000 -> NOP
-- 0001 -> STA
-- 0010 -> LDA
-- 0011 -> ADD
-- 0100 -> OR
-- 0101 -> AND
-- 0110 -> NOT
-- 0111 -> SHR
-- 1000 -> JMP
-- 1001 -> JN
-- 1010 -> JZ
-- 1011 -> SHL
-- 1100 -> MUL
-- 1111 -> HLT
program: process (instruction_in(7 downto 4))
begin
-- Set all as zero
s_exec_nop <= '0';
s_exec_sta <= '0';
s_exec_lda <= '0';
s_exec_add <= '0';
s_exec_or <= '0';
s_exec_and <= '0';
s_exec_not <= '0';
s_exec_jmp <= '0';
s_exec_jn <= '0';
s_exec_jz <= '0';
s_exec_hlt <= '0';
s_exec_shr <= '0';
s_exec_shl <= '0';
s_exec_mul <= '0';
if (instruction_in(7 downto 4) = "0000") then -- NOP
s_exec_nop <= '1';
elsif (instruction_in(7 downto 4) = "0001") then -- STA
s_exec_sta <= '1';
elsif (instruction_in(7 downto 4) = "0010") then -- LDA
s_exec_lda <= '1';
elsif (instruction_in(7 downto 4) = "0011") then -- ADD
s_exec_add <= '1';
elsif (instruction_in(7 downto 4) = "0100") then -- OR
s_exec_or <= '1';
elsif (instruction_in(7 downto 4) = "0101") then -- AND
s_exec_and <= '1';
elsif (instruction_in(7 downto 4) = "0110") then -- NOT
s_exec_not <= '1';
elsif (instruction_in(7 downto 4) = "1000") then -- JMP
s_exec_jmp <= '1';
elsif (instruction_in(7 downto 4) = "1001") then -- JN
s_exec_jn <= '1';
elsif (instruction_in(7 downto 4) = "1010") then -- JZ
s_exec_jz <= '1';
elsif (instruction_in(7 downto 4) = "1111") then -- HLT
s_exec_hlt <= '1';
-- Challenge instructions SHR, SHL e MUL
elsif (instruction_in(7 downto 4) = "0111") then -- SHR
s_exec_shr <= '1';
elsif (instruction_in(7 downto 4) = "1011") then -- SHL
s_exec_shl <= '1';
elsif (instruction_in(7 downto 4) = "1100") then -- MUL
s_exec_mul <= '1';
-- End challenge
end if;
end process program;
end Behavioral;
|
mit
|
5ca7df68b25cce271b65607206991b42
| 0.585219 | 2.808342 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica7/juegoBolita.vhd
| 1 | 5,593 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:20:35 11/03/2011
-- Design Name:
-- Module Name: juegoBolita - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity juegoBolita is
-- El reloj aqu definido debe dar un flanco de subida cada
-- centsima de segundo.
Port( clk : in STD_LOGIC;
reset : in STD_LOGIC;
empezar : in STD_LOGIC;
derecha : in STD_LOGIC;
izquierda : in STD_LOGIC;
filasOut : out STD_LOGIC_VECTOR (7 downto 0);
columnasOut : out STD_LOGIC_VECTOR (7 downto 0);
puntajeOut : out STD_LOGIC_VECTOR (3 downto 0)
);
end juegoBolita;
architecture Behavioral of juegoBolita is
type estados is (rst,inicio,jugando,victoria,derrota);
signal estado : estados;
type estadosBoton is (presionado,liberado);
signal boton : estadosBoton;
signal filas : STD_LOGIC_VECTOR(2 downto 0);
signal columnas : STD_LOGIC_VECTOR(2 downto 0);
signal columnaInicio : STD_LOGIC_VECTOR(2 downto 0);
signal filaBolita : STD_LOGIC_VECTOR(2 downto 0);
signal columnaBolita : STD_LOGIC_VECTOR(2 downto 0);
signal columnaJugador: STD_LOGIC_VECTOR(2 downto 0);
signal puntaje : STD_LOGIC_VECTOR(3 downto 0);
signal avance : STD_LOGIC_VECTOR(4 downto 0);
begin
-- Mquina de Estados
process(clk,reset,empezar,derecha,izquierda,filaBolita,columnaBolita,columnaJugador,puntaje,avance)
begin -- Falta meter las seales de los estados! (estado, boton)
if reset = '1' then
estado <= rst;
boton <= liberado;
columnaBolita <= "000";
filaBolita <= "000";
columnaJugador <= "100";
puntaje <= "0000";
avance <= "00000";
elsif clk'event and clk = '1' then
case estado is
when rst =>
if empezar = '1' then
estado <= inicio;
end if;
when inicio =>
puntaje <= "0000";
columnaBolita <= columnaInicio;
filaBolita <= "111";
estado <= jugando;
when jugando =>
-- Proceso para mover la bolita del jugador
if boton = liberado then
if derecha = '1' then -- Muevo la bolita del jugador a la derecha
boton <= presionado;
columnaJugador <= columnaJugador + 1;
elsif izquierda = '1' then -- Muevo la bolita del jugador a la izquierda
boton <= presionado;
columnaJugador <= columnaJugador - 1;
end if;
elsif derecha = '0' and izquierda = '0' then
boton <= liberado;
end if;
-- Proceso para la caida de la bolita
avance <= avance + 1;
if avance = "00000" then
filaBolita <= filaBolita - 1;
elsif filaBolita = "000" then
if columnaBolita = columnaJugador then
if puntaje = "1001" then
estado <= victoria;
else
puntaje <= puntaje + 1;
end if;
else
estado <= derrota;
end if;
end if;
when victoria =>
if empezar = '1' then
estado <= inicio;
end if;
when derrota =>
if empezar = '1' then
estado <= inicio;
end if;
end case;
end if;
end process;
-- Generando columnaInicio aleatoria
process(clk,reset,empezar)
begin
if reset = '1' then
columnaInicio <= "000";
elsif empezar = '1' and clk'event and clk = '1' then
columnaInicio <= columnaInicio + 1;
end if;
end process;
-- Dibuja en el display
process(clk, reset, estado, columnaJugador, columnaBolita, filaBolita)
begin
if reset = '1' then
filas <= "000";
columnas <= "100";
elsif clk'event and clk = '1' then
end if;
end process;
-- Transformando filas y columnas para la salida (BLOQUE COMBINACIONAL)
process(reset,estado,filas,columnas)
begin
if reset = '1' then
columnasOut <= "00000000";
filasOut <= "00000000";
puntajeOut <= "0000";
else
case estado is
when victoria =>
columnasOut <= "11111111";
filasOut <= "10000001";
when derrota =>
columnasOut <= "11111111";
filasOut <= "11111111";
when others =>
puntajeOut <= puntaje;
case columnas is
when "000" => columnasOut <= "10000000";
when "001" => columnasOut <= "01000000";
when "010" => columnasOut <= "00100000";
when "011" => columnasOut <= "00010000";
when "100" => columnasOut <= "00001000";
when "101" => columnasOut <= "00000100";
when "110" => columnasOut <= "00000010";
when "111" => columnasOut <= "00000001";
when others => columnasOut <= "00000000";
end case;
case filas is
when "000" => filasOut <= "10000000";
when "001" => filasOut <= "01000000";
when "010" => filasOut <= "00100000";
when "011" => filasOut <= "00010000";
when "100" => filasOut <= "00001000";
when "101" => filasOut <= "00000100";
when "110" => filasOut <= "00000010";
when "111" => filasOut <= "00000001";
when others => filasOut <= "00000000";
end case;
end case;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
d6c322ccc2e4073485705fa434bdaffd
| 0.607903 | 3.437615 | false | false | false | false |
dl3yc/sdr-fm
|
dev/vcordic/vcordic_tb.vhd
| 1 | 810 |
-- title: Testbench for VCORDIC
-- author: Sebastian Weiss
-- last change: 03.12.14
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity vcordic_tb is
end entity;
architecture behavioral of vcordic_tb is
constant A : natural := 16;
constant P : natural := 24;
constant N : natural := 15;
signal clk : std_logic := '0';
signal i : signed(A-1 downto 0);
signal q : signed(A-1 downto 0);
signal amp : unsigned(A-1 downto 0);
signal phi : signed(P-1 downto 0) := (others => '0');
begin
dut : entity work.vcordic
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => i,
q => q,
amp => amp,
phi => phi
);
i <= x"7FFF";
q <= x"7FFF";
clk <= not clk after 11363 ps;
end behavioral;
|
gpl-2.0
|
9ee529cd38e35b8c72e0895a584099ae
| 0.593827 | 2.736486 | false | false | false | false |
vargax/ejemplos
|
vhd/fundSistDigitales/practica3/test.vhd
| 1 | 3,553 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:36:37 09/03/2011
-- Design Name:
-- Module Name: C:/Users/Digitales/Desktop/digPractica3/test.vhd
-- Project Name: Display
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: practica3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT practica3
PORT(
LED1 : IN std_logic;
LED2 : IN std_logic;
LED3 : IN std_logic;
LED4 : IN std_logic;
LED5 : IN std_logic;
LED6 : IN std_logic;
LED7 : IN std_logic;
SEGA : OUT std_logic;
SEGB : OUT std_logic;
SEGC : OUT std_logic;
SEGD : OUT std_logic;
SEGE : OUT std_logic;
SEGF : OUT std_logic;
SEGG : OUT std_logic
);
END COMPONENT;
--Inputs
signal LED1 : std_logic := '0';
signal LED2 : std_logic := '0';
signal LED3 : std_logic := '0';
signal LED4 : std_logic := '0';
signal LED5 : std_logic := '0';
signal LED6 : std_logic := '0';
signal LED7 : std_logic := '0';
--Outputs
signal SEGA : std_logic;
signal SEGB : std_logic;
signal SEGC : std_logic;
signal SEGD : std_logic;
signal SEGE : std_logic;
signal SEGF : std_logic;
signal SEGG : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: practica3 PORT MAP (
LED1 => LED1,
LED2 => LED2,
LED3 => LED3,
LED4 => LED4,
LED5 => LED5,
LED6 => LED6,
LED7 => LED7,
SEGA => SEGA,
SEGB => SEGB,
SEGC => SEGC,
SEGD => SEGD,
SEGE => SEGE,
SEGF => SEGF,
SEGG => SEGG
);
PROCESS
BEGIN
WAIT FOR 10 NS; --1
LED1 <= '1';
LED2 <= '1';
LED3 <= '1';
LED4 <= '0';
LED5 <= '1';
LED6 <= '1';
LED7 <= '1';
WAIT FOR 10 NS; --2
LED1 <= '1';
LED2 <= '1';
LED3 <= '0';
LED4 <= '1';
LED5 <= '1';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --3
LED1 <= '1';
LED2 <= '1';
LED3 <= '0';
LED4 <= '0';
LED5 <= '1';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --4
LED1 <= '0';
LED2 <= '1';
LED3 <= '0';
LED4 <= '1';
LED5 <= '0';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --5
LED1 <= '0';
LED2 <= '1';
LED3 <= '0';
LED4 <= '0';
LED5 <= '0';
LED6 <= '1';
LED7 <= '0';
WAIT FOR 10 NS; --6
LED1 <= '0';
LED2 <= '0';
LED3 <= '0';
LED4 <= '1';
LED5 <= '0';
LED6 <= '0';
LED7 <= '0';
END PROCESS;
END;
|
gpl-2.0
|
9d5138430a62e08e0c697fc161c8b070
| 0.489164 | 3.192273 | false | true | false | false |
egk696/InterNoC
|
ip_repo/uart_transceiver_v1_0/uart_rx.vhd
| 3 | 4,182 |
----------------------------------------------------------------------
-- File Downloaded from http://www.nandland.com
----------------------------------------------------------------------
-- This file contains the UART Receiver. This receiver is able to
-- receive 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When receive is complete o_rx_dv will be
-- driven high for one clock cycle.
--
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity UART_RX is
generic (
g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly
);
port (
i_Clk : in std_logic;
i_RX_Serial : in std_logic;
o_RX_DV : out std_logic;
o_RX_Byte : out std_logic_vector(7 downto 0)
);
end UART_RX;
architecture rtl of UART_RX is
type t_SM_Main is (s_Idle, s_RX_Start_Bit, s_RX_Data_Bits,
s_RX_Stop_Bit, s_Cleanup);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_RX_Data_R : std_logic := '0';
signal r_RX_Data : std_logic := '0';
signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_RX_Byte : std_logic_vector(7 downto 0) := (others => '0');
signal r_RX_DV : std_logic := '0';
begin
-- Purpose: Double-register the incoming data.
-- This allows it to be used in the UART RX Clock Domain.
-- (It removes problems caused by metastabiliy)
p_SAMPLE : process (i_Clk)
begin
if rising_edge(i_Clk) then
r_RX_Data_R <= i_RX_Serial;
r_RX_Data <= r_RX_Data_R;
end if;
end process p_SAMPLE;
-- Purpose: Control RX state machine
p_UART_RX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
r_RX_DV <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if r_RX_Data = '0' then -- Start bit detected
r_SM_Main <= s_RX_Start_Bit;
else
r_SM_Main <= s_Idle;
end if;
-- Check middle of start bit to make sure it's still low
when s_RX_Start_Bit =>
if r_Clk_Count = (g_CLKS_PER_BIT-1)/2 then
if r_RX_Data = '0' then
r_Clk_Count <= 0; -- reset counter since we found the middle
r_SM_Main <= s_RX_Data_Bits;
else
r_SM_Main <= s_Idle;
end if;
else
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Start_Bit;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles to sample serial data
when s_RX_Data_Bits =>
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Data_Bits;
else
r_Clk_Count <= 0;
r_RX_Byte(r_Bit_Index) <= r_RX_Data;
-- Check if we have sent out all bits
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_Data_Bits;
else
r_Bit_Index <= 0;
r_SM_Main <= s_RX_Stop_Bit;
end if;
end if;
-- Receive Stop bit. Stop bit = 1
when s_RX_Stop_Bit =>
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_Clk_Count < g_CLKS_PER_BIT-1 then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Stop_Bit;
else
r_RX_DV <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Cleanup;
end if;
-- Stay here 1 clock
when s_Cleanup =>
r_SM_Main <= s_Idle;
r_RX_DV <= '0';
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_RX;
o_RX_DV <= r_RX_DV;
o_RX_Byte <= r_RX_Byte;
end rtl;
|
mit
|
6b1f6bcda0addc231f20f0cc46d23a04
| 0.491392 | 3.332271 | false | false | false | false |
andbet050197/IS773UTP
|
Flip-Flops/FFDCLR_TB.vhd
| 1 | 1,147 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FFDCLR_TB IS
END FFDCLR_TB;
ARCHITECTURE behavior OF FFDCLR_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FFDCLR
PORT(
CLK : IN std_logic;
CLR : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal CLR : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal Q : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FFDCLR PORT MAP (
CLK => CLK,
CLR => CLR,
D => D,
Q => Q
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
D <= '1';
wait for 10 ns;
CLR <= '1';
wait for 40 ns;
CLR <= '0';
wait;
end process;
END;
|
gpl-3.0
|
f969b565ca3d9907b56c475c4484edc0
| 0.542284 | 3.454819 | false | false | false | false |
andbet050197/IS773UTP
|
modulo2/Motorapasos_tb.vhd
| 1 | 2,306 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:21:34 03/01/2017
-- Design Name:
-- Module Name: C:/Users/Estudiantes/Desktop/andres/motorpap/Motorapasos_tb.vhd
-- Project Name: motorpap
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Motor_a_pasos
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Motorapasos_tb IS
END Motorapasos_tb;
ARCHITECTURE behavior OF Motorapasos_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Motor_a_pasos
PORT(
StepDrive : OUT std_logic_vector(3 downto 0);
Direction : IN std_logic;
StepEnable : IN std_logic;
CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal Direction : std_logic := '0';
signal StepEnable : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal StepDrive : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Motor_a_pasos PORT MAP (
StepDrive => StepDrive,
Direction => Direction,
StepEnable => StepEnable,
CLK => CLK
);
CLK_process :process -- Clock process definitions
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
stim_proc: process -- Stimulus process
begin
StepEnable <= '1';
direction <= '1'; --Girar a la derecha
wait for 270 ms;
direction <= '0'; --Girar a la izquierda
wait for 430 ms;
StepEnable <= '0'; --Apagar habilitador
--wait for CLK_period*10;
wait;
end process;
END;
|
gpl-3.0
|
d702c2128de167b43bde122bc3225cf5
| 0.595837 | 3.767974 | false | true | false | false |
egk696/InterNoC
|
ip_repo/internoc_ni_axi_master_1.0/src/internoc_ni_type_map.vhd
| 2 | 3,501 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/16/2017 07:50:07 PM
-- Design Name:
-- Module Name: internoc_ni_type_map - behave
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.internoc_pack.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity internoc_interface_type_map is
Port (
clk_i : in STD_LOGIC;
addr_i : in STD_LOGIC_VECTOR (4 downto 0);
type_o : out STD_LOGIC_VECTOR (2 downto 0);
mode_o : out STD_LOGIC
);
end internoc_interface_type_map;
architecture behave of internoc_interface_type_map is
constant INTERFACE_MAP_ROM : INTERFACE_MAP_T := (
("00000", SLAVE_MODE, I2C_INTERFACE), --1
("00001", SLAVE_MODE, SPI_INTERFACE), --2
("00010", SLAVE_MODE, INVALID_INTERFACE), --3
("00011", SLAVE_MODE, INVALID_INTERFACE), --4
("00100", SLAVE_MODE, INVALID_INTERFACE), --5
("00101", SLAVE_MODE, INVALID_INTERFACE), --6
("00110", SLAVE_MODE, INVALID_INTERFACE), --7
("00111", SLAVE_MODE, INVALID_INTERFACE), --8
("01000", SLAVE_MODE, INVALID_INTERFACE), --9
("01001", SLAVE_MODE, INVALID_INTERFACE), --10
("01010", SLAVE_MODE, INVALID_INTERFACE), --11
("01011", SLAVE_MODE, INVALID_INTERFACE), --12
("01100", SLAVE_MODE, INVALID_INTERFACE), --13
("01101", SLAVE_MODE, INVALID_INTERFACE), --14
("01110", SLAVE_MODE, INVALID_INTERFACE), --15
("01111", SLAVE_MODE, INVALID_INTERFACE), --16
("10000", MASTER_MODE, UART_INTERFACE), --17
("10001", MASTER_MODE, UART_INTERFACE), --18
("10010", MASTER_MODE, INVALID_INTERFACE), --19
("10011", MASTER_MODE, INVALID_INTERFACE), --20
("10100", MASTER_MODE, INVALID_INTERFACE), --21
("10101", MASTER_MODE, INVALID_INTERFACE), --22
("10110", MASTER_MODE, INVALID_INTERFACE), --23
("10111", MASTER_MODE, INVALID_INTERFACE), --24
("11000", MASTER_MODE, INVALID_INTERFACE), --25
("11001", MASTER_MODE, INVALID_INTERFACE), --26
("11010", MASTER_MODE, INVALID_INTERFACE), --27
("11011", MASTER_MODE, INVALID_INTERFACE), --28
("11100", MASTER_MODE, INVALID_INTERFACE), --29
("11101", MASTER_MODE, INVALID_INTERFACE), --30
("11110", MASTER_MODE, INVALID_INTERFACE), --31
("11111", MASTER_MODE, INVALID_INTERFACE) --32
);
signal interface_type : std_logic_vector(2 downto 0) := (others=>'1');
signal interface_mode : std_logic := '0';
begin
type_o <= interface_type;
mode_o <= interface_mode;
rom_p: process(clk_i)
begin
if rising_edge(clk_i) then
interface_type <= INTERFACE_MAP_ROM(to_integer(unsigned(addr_i))).interface;
interface_mode <= INTERFACE_MAP_ROM(to_integer(unsigned(addr_i))).mode;
end if;
end process;
end behave;
|
mit
|
940114746295b920288dd5f6694e97e3
| 0.576978 | 3.724468 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.